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Rev 6 → Rev 7
/trunk/impl0/sim/testbench/nontri/test.vhd
0,0 → 1,251
-------------------------------------------------------------- |
-- test.vhd |
-------------------------------------------------------------- |
-- project: HPC-16 Microprocessor |
-- |
-- usage: basic testbench top-level |
-- |
-- dependency: cpu.vhd, ramNx16.vhd, ram8x16.vhd |
-- |
-- Author: M. Umair Siddiqui (umairsiddiqui@opencores.org) |
--------------------------------------------------------------- |
------------------------------------------------------------------------------------ |
-- -- |
-- Copyright (c) 2005, M. Umair Siddiqui all rights reserved -- |
-- -- |
-- This file is part of HPC-16. -- |
-- -- |
-- HPC-16 is free software; you can redistribute it and/or modify -- |
-- it under the terms of the GNU Lesser General Public License as published by -- |
-- the Free Software Foundation; either version 2.1 of the License, or -- |
-- (at your option) any later version. -- |
-- -- |
-- HPC-16 is distributed in the hope that it will be useful, -- |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- |
-- GNU Lesser General Public License for more details. -- |
-- -- |
-- You should have received a copy of the GNU Lesser General Public License -- |
-- along with HPC-16; if not, write to the Free Software -- |
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- |
-- -- |
------------------------------------------------------------------------------------ |
-------------------------------- |
-- -- |
-- non-tristate version -- |
-- -- |
-------------------------------- |
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_arith.all; |
use ieee.std_logic_unsigned.all; |
----------------------------------------------------------- |
entity test is |
generic |
( |
clk_period : time := 40 ns; |
half_clk_period : time := 20 ns; |
-- |
cpu_pc_preset_value : std_logic_vector(15 downto 0) := X"0000"; |
cpu_sp_preset_value : std_logic_vector(15 downto 0) := X"001e"; |
-- |
ram_adr_width : integer := 4; |
|
file_name_prefix : string := "add2"; |
sim_stop_time : time := 3000 ns; |
-- |
ram2_adr : std_logic_vector(15 downto 0) := X"ff00"; |
|
ram2_init_0 : std_logic_vector(15 downto 0) := X"7fff"; |
ram2_init_1 : std_logic_vector(15 downto 0) := X"0001"; |
ram2_init_2 : std_logic_vector(15 downto 0) := (others => '0'); |
ram2_init_3 : std_logic_vector(15 downto 0) := (others => '0'); |
ram2_init_4 : std_logic_vector(15 downto 0) := (others => '0'); |
ram2_init_5 : std_logic_vector(15 downto 0) := (others => '0'); |
ram2_init_6 : std_logic_vector(15 downto 0) := (others => '0'); |
ram2_init_7 : std_logic_vector(15 downto 0) := (others => '0') |
); |
end test; |
|
architecture sim of test is |
---------------------------------------- |
-- cpu interface signal |
---------------------------------------- |
signal clk_i : std_logic; |
signal rst_i : std_logic; |
signal ack_i : std_logic; |
signal intr_i : std_logic; |
-- |
signal sel_o : std_logic_vector(1 downto 0); |
signal stb_o : std_logic; |
signal cyc_o : std_logic; |
signal we_o : std_logic; |
-- |
signal inta_cyc_o : std_logic; |
signal i_cyc_o : std_logic; |
signal c_cyc_o : std_logic; |
signal d_cyc_o : std_logic; |
-- |
signal adr_o : std_logic_vector(15 downto 0); |
-- |
signal dat_i : std_logic_vector(15 downto 0); |
signal dat_o : std_logic_vector(15 downto 0); |
signal ram_dat_o : std_logic_vector(15 downto 0); |
signal ram2_dat_o : std_logic_vector(15 downto 0); |
----------------------------------------- |
-- ram interfacing |
----------------------------------------- |
signal ram_cs : std_logic; |
signal ram_oe : std_logic; |
-- |
signal ram2_cs : std_logic; |
signal ram2_oe : std_logic; |
begin |
---------------------------------------------------------------------- |
clk_gen : process |
begin |
wait for half_clk_period; |
clk_i <= '1'; |
wait for half_clk_period; |
clk_i <= '0'; |
if now >= sim_stop_time then |
assert false |
report "simulation completed (not an error)" |
severity error; |
wait; |
end if; |
end process; |
----------------------------------------------------------------------- |
rst_gen : process |
begin |
wait for half_clk_period; |
rst_i <= '1'; |
wait for 4 * clk_period; |
rst_i <= '0'; |
wait; |
end process; |
------------------------------------------------------------------------- |
cpu : entity work.cpu |
generic map |
( |
pc_preset_value => cpu_pc_preset_value, |
sp_preset_value => cpu_sp_preset_value |
) |
port map |
( |
CLK_I => clk_i, |
RST_I => rst_i, |
ACK_I => ack_i, |
INTR_I => intr_i, |
-- |
SEL_O => sel_o, |
STB_O => stb_o, |
CYC_O => cyc_o, |
WE_O => we_o, |
-- |
INTA_CYC_O => inta_cyc_o, |
I_CYC_O => i_cyc_o, |
C_CYC_O => c_cyc_o, |
D_CYC_O => d_cyc_o, |
-- |
DAT_I => dat_i, |
DAT_O => dat_o, |
ADR_O => adr_o |
); |
-------------------------------------------------- |
ack_gen : ack_i <= stb_o; |
----------------------------------------------------------------------- |
ram_cs_gen : process(stb_o, adr_o) |
variable temp : integer; |
constant max_loc : integer := (2 ** (ram_adr_width + 1)) - 1; |
begin |
if stb_o = '1' then |
temp := conv_integer(adr_o); |
if 0 <= temp and temp <= max_loc then |
ram_cs <= '1'; |
else |
ram_cs <= '0'; |
end if; |
end if; |
end process ram_cs_gen; |
---------------------------------------------------------------------- |
ram_oe <= not we_o; |
---------------------------------------------------------------------- |
ram: entity work.ramNx16(async) |
generic map |
( |
init_file_name => file_name_prefix & "_init_ram.txt", |
adr_width => ram_adr_width |
|
) |
port map |
( |
clk => clk_i, |
adr => adr_o(ram_adr_width downto 1), |
dat_i => dat_o, -- connected to output of cpu |
-- |
cs => ram_cs, |
we => we_o, |
ub => sel_o(1), |
lb => sel_o(0), |
oe => ram_oe, |
-- |
dat_o => ram_dat_o |
); |
-------------------------------------------------- |
ram2: entity work.ram8x16 |
generic map |
( |
init_0 => ram2_init_0, |
init_1 => ram2_init_1, |
init_2 => ram2_init_2, |
init_3 => ram2_init_3, |
init_4 => ram2_init_4, |
init_5 => ram2_init_5, |
init_6 => ram2_init_6, |
init_7 => ram2_init_7 |
|
) |
port map |
( |
clk => clk_i, |
adr => adr_o(3 downto 1), |
dat_i => dat_o, -- connected to cpu output |
-- |
cs => ram2_cs, |
we => we_o, |
ub => sel_o(1), |
lb => sel_o(0), |
oe => ram2_oe, |
-- |
dat_o => ram2_dat_o |
); |
----------------------------------------------- |
ram2_oe <= not we_o; |
---------------------------------------------- |
ram2_cs_gen : process(stb_o, adr_o) |
variable temp : integer; |
constant max_loc : integer := conv_integer(ram2_adr) + 15; |
begin |
if stb_o = '1' then |
temp := conv_integer(adr_o); |
if ram2_adr <= temp and temp <= max_loc then |
ram2_cs <= '1'; |
else |
ram2_cs <= '0'; |
end if; |
end if; |
end process ram2_cs_gen; |
---------------------------------------------- |
ram_out_mux : process(ram_cs, ram2_cs, ram_dat_o, ram2_dat_o) |
-- which ram output will drive the cpu's dat_i |
variable cs : std_logic_vector(1 downto 0); |
begin |
cs := ram_cs & ram2_cs; |
case cs is |
when "10" => dat_i <= ram_dat_o; |
when "01" => dat_i <= ram2_dat_o; |
when others => dat_i <= (others => '0'); |
end case; |
end process ram_out_mux; |
end sim; |
/trunk/impl0/sim/testbench/nontri/test2.vhd
0,0 → 1,177
-------------------------------------------------------------- |
-- test2.vhd |
-------------------------------------------------------------- |
-- project: HPC-16 Microprocessor |
-- |
-- usage: basic testbench top-level |
-- |
-- dependency: cpu.vhd, ramNx16.vhd |
-- |
-- Author: M. Umair Siddiqui (umairsiddiqui@opencores.org) |
--------------------------------------------------------------- |
------------------------------------------------------------------------------------ |
-- -- |
-- Copyright (c) 2005, M. Umair Siddiqui all rights reserved -- |
-- -- |
-- This file is part of HPC-16. -- |
-- -- |
-- HPC-16 is free software; you can redistribute it and/or modify -- |
-- it under the terms of the GNU Lesser General Public License as published by -- |
-- the Free Software Foundation; either version 2.1 of the License, or -- |
-- (at your option) any later version. -- |
-- -- |
-- HPC-16 is distributed in the hope that it will be useful, -- |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- |
-- GNU Lesser General Public License for more details. -- |
-- -- |
-- You should have received a copy of the GNU Lesser General Public License -- |
-- along with HPC-16; if not, write to the Free Software -- |
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- |
-- -- |
------------------------------------------------------------------------------------ |
-------------------------------- |
-- -- |
-- non-tristate version -- |
-- -- |
-------------------------------- |
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_arith.all; |
use ieee.std_logic_unsigned.all; |
----------------------------------------------------------- |
entity test2 is |
generic |
( |
clk_period : time := 40 ns; |
half_clk_period : time := 20 ns; |
-- |
cpu_pc_preset_value : std_logic_vector(15 downto 0) := X"0000"; |
cpu_sp_preset_value : std_logic_vector(15 downto 0) := X"001e"; |
-- |
ram_adr_width : integer := 4; |
|
file_name_prefix : string := "prog1"; |
sim_stop_time : time := 1500 ns |
); |
end test2; |
|
architecture sim of test2 is |
---------------------------------------- |
-- cpu interface signal |
---------------------------------------- |
signal clk_i : std_logic; |
signal rst_i : std_logic; |
signal ack_i : std_logic; |
signal intr_i : std_logic; |
-- |
signal sel_o : std_logic_vector(1 downto 0); |
signal stb_o : std_logic; |
signal cyc_o : std_logic; |
signal we_o : std_logic; |
-- |
signal inta_cyc_o : std_logic; |
signal i_cyc_o : std_logic; |
signal c_cyc_o : std_logic; |
signal d_cyc_o : std_logic; |
-- |
signal adr_o : std_logic_vector(15 downto 0); |
signal dat_i : std_logic_vector(15 downto 0); |
signal dat_o : std_logic_vector(15 downto 0); |
----------------------------------------- |
-- ram interfacing |
----------------------------------------- |
signal ram_cs : std_logic; |
signal ram_oe : std_logic; |
begin |
------------------------------------------------------------------------ |
ram_cs_gen : process(stb_o, adr_o) |
variable temp : integer; |
constant max_loc : integer := (2 ** (ram_adr_width + 1)) - 1; |
begin |
if stb_o = '1' then |
temp := conv_integer(adr_o); |
if 0 <= temp and temp <= max_loc then |
ram_cs <= '1'; |
else |
ram_cs <= '0'; |
end if; |
end if; |
end process ram_cs_gen; |
---------------------------------------------------------------------- |
ram_oe <= not we_o; |
---------------------------------------------------------------------- |
clk_gen : process |
begin |
wait for half_clk_period; |
clk_i <= '1'; |
wait for half_clk_period; |
clk_i <= '0'; |
if now >= sim_stop_time then |
assert false |
report "simulation completed (not an error)" |
severity error; |
wait; |
end if; |
end process; |
----------------------------------------------------------------------- |
rst_gen : process |
begin |
wait for half_clk_period; |
rst_i <= '1'; |
wait for 4 * clk_period; |
rst_i <= '0'; |
wait; |
end process; |
------------------------------------------------------------------------- |
cpu : entity work.cpu |
generic map |
( |
pc_preset_value => cpu_pc_preset_value, |
sp_preset_value => cpu_sp_preset_value |
) |
port map |
( |
CLK_I => clk_i, |
RST_I => rst_i, |
ACK_I => ack_i, |
INTR_I => intr_i, |
-- |
SEL_O => sel_o, |
STB_O => stb_o, |
CYC_O => cyc_o, |
WE_O => we_o, |
-- |
INTA_CYC_O => inta_cyc_o, |
I_CYC_O => i_cyc_o, |
C_CYC_O => c_cyc_o, |
D_CYC_O => d_cyc_o, |
-- |
DAT_I => dat_i, |
DAT_O => dat_o, |
ADR_O => adr_o |
); |
----------------------------------------------------------------------- |
ram: entity work.ramNx16(async) |
generic map |
( |
init_file_name => file_name_prefix & "_init_ram.txt", |
adr_width => ram_adr_width |
) |
port map |
( |
clk => clk_i, |
adr => adr_o(ram_adr_width downto 1), |
dat_i => dat_o, -- the output of cpu is input of ram |
-- |
cs => ram_cs, |
we => we_o, |
ub => sel_o(1), |
lb => sel_o(0), |
oe => ram_oe, |
-- |
dat_o => dat_i -- the input of cpu is output of ram |
); |
-------------------------------------------------- |
ack_gen : ack_i <= stb_o; |
end sim; |
/trunk/impl0/sim/testbench/nontri/ram8x16.vhd
0,0 → 1,122
-------------------------------------------------------------- |
-- ram8x16.vhd |
-------------------------------------------------------------- |
-- project: HPC-16 Microprocessor |
-- |
-- usage: RAM with async read and sync write operation (not synthsizable, without timing params) |
-- |
-- dependency: none |
-- |
-- Author: M. Umair Siddiqui (umairsiddiqui@opencores.org) |
--------------------------------------------------------------- |
------------------------------------------------------------------------------------ |
-- -- |
-- Copyright (c) 2005, M. Umair Siddiqui all rights reserved -- |
-- -- |
-- This file is part of HPC-16. -- |
-- -- |
-- HPC-16 is free software; you can redistribute it and/or modify -- |
-- it under the terms of the GNU Lesser General Public License as published by -- |
-- the Free Software Foundation; either version 2.1 of the License, or -- |
-- (at your option) any later version. -- |
-- -- |
-- HPC-16 is distributed in the hope that it will be useful, -- |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- |
-- GNU Lesser General Public License for more details. -- |
-- -- |
-- You should have received a copy of the GNU Lesser General Public License -- |
-- along with HPC-16; if not, write to the Free Software -- |
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- |
-- -- |
------------------------------------------------------------------------------------ |
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_arith.all; |
use ieee.std_logic_unsigned.all; |
--------------------------------------------- |
entity ram8x16 is |
generic |
( |
init_0 : std_logic_vector(15 downto 0) := (others => '0'); |
init_1 : std_logic_vector(15 downto 0) := (others => '0'); |
init_2 : std_logic_vector(15 downto 0) := (others => '0'); |
init_3 : std_logic_vector(15 downto 0) := (others => '0'); |
init_4 : std_logic_vector(15 downto 0) := (others => '0'); |
init_5 : std_logic_vector(15 downto 0) := (others => '0'); |
init_6 : std_logic_vector(15 downto 0) := (others => '0'); |
init_7 : std_logic_vector(15 downto 0) := (others => '0') |
); |
port |
( |
clk : in std_logic; |
adr : in std_logic_vector(2 downto 0); |
dat_i : in std_logic_vector(15 downto 0); |
-- |
cs : in std_logic; |
we : in std_logic; |
ub : in std_logic; |
lb : in std_logic; |
oe : in std_logic; |
-- |
dat_o : out std_logic_vector(15 downto 0) |
); |
end ram8x16; |
------------------------------------------- |
architecture sim of ram8x16 is |
type rtype is array(0 to 7) of std_logic_vector(7 downto 0); |
shared variable ram_data_lower : rtype := ( init_0(7 downto 0), |
init_1(7 downto 0), |
init_2(7 downto 0), |
init_3(7 downto 0), |
init_4(7 downto 0), |
init_5(7 downto 0), |
init_6(7 downto 0), |
init_7(7 downto 0)); |
shared variable ram_data_upper : rtype := ( init_0(15 downto 8), |
init_1(15 downto 8), |
init_2(15 downto 8), |
init_3(15 downto 8), |
init_4(15 downto 8), |
init_5(15 downto 8), |
init_6(15 downto 8), |
init_7(15 downto 8)); |
|
signal write_lower : std_logic; |
signal write_upper : std_logic; |
signal out_lower : std_logic; |
signal out_upper : std_logic; |
begin |
---------------------------------------------------------------------------- |
-- main |
---------------------------------------------------------------------------- |
write_low: write_lower <= cs and we and lb; |
write_up : write_upper <= cs and we and ub; |
---------------------------------------------------------------------------- |
upper: process(clk) |
begin |
if rising_edge(clk) then |
if write_upper = '1' then |
ram_data_upper(conv_integer(adr)) := dat_i(15 downto 8); |
end if; |
end if; |
end process upper; |
---------------------------------------------------------------------------- |
lower: process(clk) |
begin |
if rising_edge(clk) then |
if write_lower = '1' then |
ram_data_lower(conv_integer(adr)) := dat_i(7 downto 0); |
end if; |
end if; |
end process lower; |
----------------------------------------------------------------------- |
out_low : out_lower <= cs and (not we) and lb and oe; |
out_up : out_upper <= cs and (not we) and ub and oe; |
---------------------------------------------------------------------- |
dat_up : dat_o(15 downto 8) <= ram_data_upper(conv_integer(adr)) when out_upper = '1' else |
(others => 'Z'); |
dat_low : dat_o(7 downto 0) <= ram_data_lower(conv_integer(adr)) when out_lower = '1' else |
(others => 'Z'); |
---------------------------------------------------------------------- |
end sim; |
/trunk/impl0/sim/testbench/nontri/prog1_init_ram.txt
0,0 → 1,6
0:0100100100000000 |
1:0101010101010101 |
2:0000000100010000 |
3:0000001000000001 |
4:0000010001010000 |
5:1111100000000000 |
/trunk/impl0/sim/testbench/nontri/add2_init_ram.txt
0,0 → 1,11
0:0100100100000000 |
1:1111111100000000 |
2:0100100101100000 |
3:1111111100000010 |
4:0000100000100000 |
5:0000100000110110 |
6:0011000100100011 |
7:0100100110000000 |
8:1111111100000100 |
9:0001000000101000 |
10:1111100000000000 |
/trunk/impl0/sim/testbench/nontri/ramNx16.vhd
0,0 → 1,158
-------------------------------------------------------------- |
-- ramNx16.vhd |
-------------------------------------------------------------- |
-- project: HPC-16 Microprocessor |
-- |
-- usage: RAM with async read and sync write operation (not synthsizable, without timing params) |
-- |
-- dependency: none |
-- |
-- Author: M. Umair Siddiqui (umairsiddiqui@opencores.org) |
--------------------------------------------------------------- |
------------------------------------------------------------------------------------ |
-- -- |
-- Copyright (c) 2005, M. Umair Siddiqui all rights reserved -- |
-- -- |
-- This file is part of HPC-16. -- |
-- -- |
-- HPC-16 is free software; you can redistribute it and/or modify -- |
-- it under the terms of the GNU Lesser General Public License as published by -- |
-- the Free Software Foundation; either version 2.1 of the License, or -- |
-- (at your option) any later version. -- |
-- -- |
-- HPC-16 is distributed in the hope that it will be useful, -- |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- |
-- GNU Lesser General Public License for more details. -- |
-- -- |
-- You should have received a copy of the GNU Lesser General Public License -- |
-- along with HPC-16; if not, write to the Free Software -- |
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- |
-- -- |
------------------------------------------------------------------------------------ |
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_arith.all; |
use ieee.std_logic_unsigned.all; |
-- synopsis synthesis_off |
use std.textio.all; |
use ieee.std_logic_textio.all; |
-- synopsis synthesis_on |
------------------------------------- |
entity ramNx16 is |
generic |
( |
-- synopsis synthesis_off |
init_file_name : string := "init_ramNx16.txt"; |
-- synopsis synthesis_on |
adr_width : integer := 4; |
dat_width : integer := 16 |
); |
port |
( |
clk : in std_logic; |
adr : in std_logic_vector(adr_width - 1 downto 0); |
dat_i : in std_logic_vector(dat_width - 1 downto 0); |
-- |
cs : in std_logic; |
we : in std_logic; |
ub : in std_logic; |
lb : in std_logic; |
oe : in std_logic; |
-- |
dat_o : out std_logic_vector(dat_width - 1 downto 0) |
); |
end ramNx16; |
----------------------------------------------------------------------- |
----------------------------------------------------------------------- |
architecture async of ramNx16 is |
constant locs : integer := 2 ** adr_width; |
type rtype is array(0 to locs - 1) of std_logic_vector((dat_width/2) - 1 downto 0); |
shared variable ram_data_lower : rtype; |
shared variable ram_data_upper : rtype; |
-- |
signal s_init : boolean := false; |
-- |
signal write_lower : std_logic; |
signal write_upper : std_logic; |
signal out_lower : std_logic; |
signal out_upper : std_logic; |
begin |
---------------------------------------------------------------------------- |
-- assertion |
---------------------------------------------------------------------------- |
assert dat_width = 16 |
report "module is designed for 16-bit data" |
severity error; |
---------------------------------------------------------------------------- |
-- init |
---------------------------------------------------------------------------- |
-- synopsis sythesis_off |
init: process |
file init_file : text; |
variable buf : line; |
variable address: integer; |
variable sep : character; |
variable data : std_logic_vector(dat_width - 1 downto 0); |
begin |
if ((not s_init) and (init_file_name /= "none")) then |
file_open(init_file, init_file_name, read_mode); |
while (not endfile(init_file)) loop |
readline(init_file, buf); |
read(buf, address); |
read(buf, sep); |
read(buf, data); |
ram_data_lower(address) := data(7 downto 0); |
ram_data_upper(address) := data(15 downto 8); |
end loop; |
file_close(init_file); |
s_init <= true; |
end if; |
wait; |
end process init; |
-- synopsis synthesis_on |
---------------------------------------------------------------------------- |
-- main |
---------------------------------------------------------------------------- |
write_low: write_lower <= cs and lb and we; |
write_up : write_upper <= cs and ub and we; |
---------------------------------------------------------------------------- |
upper: process(clk) |
begin |
-- synopsis synthesis_off |
if (s_init) then |
-- synopsis synthesis_on |
if rising_edge(clk) then |
if write_upper = '1' then |
ram_data_upper(conv_integer(adr)) := dat_i(15 downto 8); |
end if; |
end if; |
-- synopsis synthesis_off |
end if; |
-- synopsis synthesis_on |
end process upper; |
---------------------------------------------------------------------------- |
lower: process(clk) |
begin |
-- synopsis synthesis_off |
if (s_init) then |
-- synopsis synthesis_on |
if rising_edge(clk) then |
if write_lower = '1' then |
ram_data_lower(conv_integer(adr)) := dat_i(7 downto 0); |
end if; |
end if; |
-- synopsis synthesis_off |
end if; |
-- synopsis synthesis_on |
end process lower; |
----------------------------------------------------------------------- |
out_low : out_lower <= cs and lb and (not we) and oe; |
out_up : out_upper <= cs and ub and (not we) and oe; |
---------------------------------------------------------------------- |
dat_low : dat_o(15 downto 8) <= ram_data_upper(conv_integer(adr)) when out_upper = '1' else |
(others => 'Z'); |
dat_up : dat_o(7 downto 0) <= ram_data_lower(conv_integer(adr)) when out_lower = '1' else |
(others => 'Z'); |
---------------------------------------------------------------------- |
end async; |