OpenCores
URL https://opencores.org/ocsvn/madi_receiver/madi_receiver/trunk

Subversion Repositories madi_receiver

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Rev 6 → Rev 7

/madi_receiver/web_uploads/madi_receiver.vhd
3,9 → 3,11
use ieee.std_logic_unsigned.all;
 
entity madi_receiver is
port(
clk_125_in : in std_logic;
madi_in : in std_logic;
port(
clk_125_in : in std_logic;
madi_clk_in : in std_logic;
madi_data_valid : in std_logic;
madi_symbol_in : in std_logic_vector(4 downto 0);
madi_write : out std_logic;
madi_wordclock : out std_logic;
17,143 → 19,160
architecture behavioral of madi_receiver is
type nibble_buffer is array(7 downto 0) of std_logic_vector(3 downto 0);
signal madi_nrzi_shift : std_logic_vector(1 downto 0);
signal madi_nrzi_data : std_logic;
signal madi_sync_shift : std_logic_vector(9 downto 0);
signal madi_sync_count : std_logic_vector(2 downto 0);
signal madi_sync_clk : std_logic;
signal madi_symbol : std_logic_vector(4 downto 0);
signal madi_nibble_clk : std_logic;
signal madi_nibble : std_logic_vector(3 downto 0);
signal madi_nibble_cnt : std_logic_vector(2 downto 0);
signal madi_input_shift : std_logic_vector(14 downto 0) := (others => '0');
signal madi_clk_shift : std_logic_vector(1 downto 0) := (others => '0');
signal madi_sync_detect : std_logic := '0';
signal madi_aligned : std_logic := '0';
signal madi_symbol : std_logic_vector(4 downto 0) := (others => '0');
signal madi_symbol_count : std_logic_vector(2 downto 0) := (others => '0');
signal madi_sync_count : std_logic_vector(8 downto 0) := (others => '0');
signal madi_nibble_clk : std_logic := '0';
signal madi_nibble : std_logic_vector(3 downto 0) := (others => '0');
signal madi_nibble_cnt : std_logic_vector(2 downto 0) := (others => '0');
signal madi_nibble_buffer : nibble_buffer;
signal madi_nibble_rst : std_logic;
signal madi_channel_cnt : std_logic_vector(5 downto 0) := (others => '0');
signal madi_nibble_rst : std_logic := '0';
signal madi_channel_cnt : std_logic_vector(5 downto 0) := (others => '0');
signal madi_channel_rst : std_logic := '0';
signal madi_write_buffer : std_logic;
signal madi_write_buffer : std_logic := '0';
signal madi_wordclk_shift : std_logic_vector(1 downto 0);
signal madi_wordclk_count : std_logic_vector(11 downto 0) := (others => '0');
signal madi_wordclk_max : std_logic_vector(11 downto 0) := (others => '0');
signal madi_wordclk_wait : std_logic_vector(30 downto 0) := (others => '0');
signal madi_wordclk_current : std_logic_vector(11 downto 0) := (others => '0');
signal madi_wordclk_reference : std_logic_vector(24 downto 0) := (others => '0');
signal madi_wordclk_count : std_logic_vector(11 downto 0) := (others => '0');
begin
begin
 
madi_shift_clk : process (clk_125_in)
begin
if clk_125_in'event and clk_125_in = '1' then
madi_clk_shift <= madi_clk_shift(0) & madi_clk_in;
end if;
end process madi_shift_clk;
 
madi_shift_input : process (clk_125_in)
begin
if clk_125_in'event and clk_125_in = '1' then
if madi_clk_shift = "01" then
madi_input_shift <= madi_input_shift(13 downto 4) & madi_symbol_in;
else
madi_input_shift <= madi_input_shift(13 downto 0) & '0';
end if;
end if;
end process madi_shift_input;
madi_detect_sync : process (clk_125_in)
begin
if clk_125_in'event and clk_125_in = '1' then
if madi_symbol_count = 4 then
madi_symbol_count <= (others => '0');
if madi_aligned = '1' then
madi_symbol <= madi_input_shift(9 downto 5);
end if;
else
madi_symbol_count <= madi_symbol_count + 1;
if madi_input_shift(14 downto 5) = "1100010001" then -- JK sync Symbols detected?
madi_symbol_count <= (others => '0');
madi_sync_detect <= '1';
madi_aligned <= '1';
else
madi_sync_detect <= '0';
end if;
end if;
end if;
end process madi_detect_sync;
madi_count_symbol : process (clk_125_in)
begin
if clk_125_in'event and clk_125_in = '1' then
if madi_sync_detect = '1' then
madi_sync_count <= madi_sync_count + 1;
end if;
end if;
end process madi_count_symbol;
madi_nrzi_in : process (clk_125_in)
madi_decode : process (madi_clk_in)
begin
if clk_125_in'event and clk_125_in = '1' then
madi_nrzi_shift <= madi_nrzi_shift(0) & madi_in;
if madi_nrzi_shift = "01" or madi_nrzi_shift = "10" then
madi_nrzi_data <= '1';
else
madi_nrzi_data <= '0';
end if;
if madi_clk_in'event and madi_clk_in = '1' then
case madi_symbol is
when "11110" =>
madi_nibble <= "0000";
madi_nibble_clk <= '1';
madi_nibble_rst <= '0';
when "01001" =>
madi_nibble <= "0001";
madi_nibble_clk <= '1';
madi_nibble_rst <= '0';
when "10100" =>
madi_nibble <= "0010";
madi_nibble_clk <= '1';
madi_nibble_rst <= '0';
when "10101" =>
madi_nibble <= "0011";
madi_nibble_clk <= '1';
madi_nibble_rst <= '0';
when "01010" =>
madi_nibble <= "0100";
madi_nibble_clk <= '1';
madi_nibble_rst <= '0';
when "01011" =>
madi_nibble <= "0101";
madi_nibble_clk <= '1';
madi_nibble_rst <= '0';
when "01110" =>
madi_nibble <= "0110";
madi_nibble_clk <= '1';
madi_nibble_rst <= '0';
when "01111" =>
madi_nibble <= "0111";
madi_nibble_clk <= '1';
madi_nibble_rst <= '0';
when "10010" =>
madi_nibble <= "1000";
madi_nibble_clk <= '1';
madi_nibble_rst <= '0';
when "10011" =>
madi_nibble <= "1001";
madi_nibble_clk <= '1';
madi_nibble_rst <= '0';
when "10110" =>
madi_nibble <= "1010";
madi_nibble_clk <= '1';
madi_nibble_rst <= '0';
when "10111" =>
madi_nibble <= "1011";
madi_nibble_clk <= '1';
madi_nibble_rst <= '0';
when "11010" =>
madi_nibble <= "1100";
madi_nibble_clk <= '1';
madi_nibble_rst <= '0';
when "11011" =>
madi_nibble <= "1101";
madi_nibble_clk <= '1';
madi_nibble_rst <= '0';
when "11100" =>
madi_nibble <= "1110";
madi_nibble_clk <= '1';
madi_nibble_rst <= '0';
when "11101" =>
madi_nibble <= "1111";
madi_nibble_clk <= '1';
madi_nibble_rst <= '0';
when others =>
madi_nibble <= "0000";
madi_nibble_clk <= '0';
madi_nibble_rst <= '1';
end case;
end if;
end process madi_nrzi_in;
 
madi_sync : process (clk_125_in)
begin
if clk_125_in'event and clk_125_in = '1' then
madi_sync_shift <= madi_sync_shift(madi_sync_shift'left-1 downto 0) & madi_nrzi_data;
madi_sync_count <= madi_sync_count + 1;
if madi_sync_shift = "1100010001" then -- JK sync symbols detected
madi_sync_count <= (others => '0');
end if;
if madi_sync_count = 4 then
madi_sync_clk <= '1';
madi_symbol <= madi_sync_shift(4 downto 0);
madi_sync_count <= (others => '0');
else
madi_sync_clk <= '0';
end if;
end if;
end process madi_sync;
madi_decode : process (clk_125_in)
begin
if clk_125_in'event and clk_125_in = '1' then
if madi_sync_clk = '1' then
case madi_symbol is
when "11110" =>
madi_nibble <= "0000";
madi_nibble_clk <= '1';
madi_nibble_rst <= '0';
when "01001" =>
madi_nibble <= "0001";
madi_nibble_clk <= '1';
madi_nibble_rst <= '0';
when "10100" =>
madi_nibble <= "0010";
madi_nibble_clk <= '1';
madi_nibble_rst <= '0';
when "10101" =>
madi_nibble <= "0011";
madi_nibble_clk <= '1';
madi_nibble_rst <= '0';
when "01010" =>
madi_nibble <= "0100";
madi_nibble_clk <= '1';
madi_nibble_rst <= '0';
when "01011" =>
madi_nibble <= "0101";
madi_nibble_clk <= '1';
madi_nibble_rst <= '0';
when "01110" =>
madi_nibble <= "0110";
madi_nibble_clk <= '1';
madi_nibble_rst <= '0';
when "01111" =>
madi_nibble <= "0111";
madi_nibble_clk <= '1';
madi_nibble_rst <= '0';
when "10010" =>
madi_nibble <= "1000";
madi_nibble_clk <= '1';
madi_nibble_rst <= '0';
when "10011" =>
madi_nibble <= "1001";
madi_nibble_clk <= '1';
madi_nibble_rst <= '0';
when "10110" =>
madi_nibble <= "1010";
madi_nibble_clk <= '1';
madi_nibble_rst <= '0';
when "10111" =>
madi_nibble <= "1011";
madi_nibble_clk <= '1';
madi_nibble_rst <= '0';
when "11010" =>
madi_nibble <= "1100";
madi_nibble_clk <= '1';
madi_nibble_rst <= '0';
when "11011" =>
madi_nibble <= "1101";
madi_nibble_clk <= '1';
madi_nibble_rst <= '0';
when "11101" =>
madi_nibble <= "1110";
madi_nibble_clk <= '1';
madi_nibble_rst <= '0';
when "00100" =>
madi_nibble <= "1111";
madi_nibble_clk <= '1';
madi_nibble_rst <= '0';
when others =>
madi_nibble <= "0000";
madi_nibble_clk <= '0';
madi_nibble_rst <= '1';
end case;
else
madi_nibble_clk <= '0';
madi_nibble_rst <= '0';
end if;
end if;
end process madi_decode;
place_nibble : process (clk_125_in)
place_nibble : process (madi_clk_in)
begin
if clk_125_in'event and clk_125_in = '1' then
if madi_clk_in'event and madi_clk_in = '1' then
if madi_nibble_rst = '1' then
madi_nibble_cnt <= (others => '0');
end if;
if madi_channel_rst = '1' then
madi_channel_rst <= '0';
end if;
if madi_nibble_clk = '1' then
madi_nibble_cnt <= madi_nibble_cnt + 1;
176,41 → 195,42
madi_nibble_buffer(7) <= madi_nibble;
when others =>
end case;
madi_channel_rst <= madi_nibble_buffer(0)(3);
if madi_channel_rst = '1' then
if madi_nibble(3) = '1' and madi_nibble_cnt = "000" then
madi_channel_rst <= '1';
madi_channel_cnt <= (others => '0');
end if;
end if;
if madi_nibble_cnt = 7 then
madi_data <= madi_nibble_buffer(1) & madi_nibble_buffer(2) & madi_nibble_buffer(3) & madi_nibble_buffer(4) & madi_nibble_buffer(5) & madi_nibble_buffer(6);
madi_channel_cnt <= madi_channel_cnt + 1;
madi_write_buffer <= '1';
else
madi_write_buffer <= '0';
end if;
if madi_nibble_cnt = 7 then
madi_channel_cnt <= madi_channel_cnt + 1;
madi_channel <= madi_channel_cnt;
end if;
madi_wordclk_shift <= madi_wordclk_shift(0) & madi_channel_rst;
madi_write <= madi_write_buffer;
end if;
madi_channel <= madi_channel_cnt;
end if;
madi_write <= madi_write_buffer;
end if;
end process place_nibble;
end process place_nibble;
generate_madi_wordclk : process (clk_125_in)
begin
if clk_125_in'event and clk_125_in = '1' then
if madi_wordclk_shift = "01" then
madi_wordclk_count <= (others => '0');
else
madi_wordclk_count <= madi_wordclk_count + 1;
end if;
if madi_wordclk_count > madi_wordclk_max then
madi_wordclk_max <= madi_wordclk_count;
madi_wordclk_wait <= (others => '0');
else
if madi_wordclk_wait = 2**(madi_wordclk_wait'length-1) then
madi_wordclk_wait <= madi_wordclk_wait - 1;
end if;
end if;
if madi_wordclk_count < madi_wordclk_max(madi_wordclk_max'left downto 1) then
madi_wordclk_shift <= madi_wordclk_shift(0) & madi_channel_rst;
if madi_wordclk_shift = "01" then
madi_wordclk_count <= (others => '0');
madi_wordclk_current <= (others => '0');
if madi_wordclk_current > madi_wordclk_reference(madi_wordclk_reference'left downto madi_wordclk_reference'left-11) then
madi_wordclk_reference <= madi_wordclk_reference + 1;
else
madi_wordclk_reference <= madi_wordclk_reference - 1;
end if;
else
madi_wordclk_count <= madi_wordclk_count + 1;
madi_wordclk_current <= madi_wordclk_current + 1;
end if;
if madi_wordclk_count < madi_wordclk_reference(madi_wordclk_reference'left downto madi_wordclk_reference'left-11) then
madi_wordclock <= '1';
else
madi_wordclock <= '0';
249,56 → 269,44
if bitclk_in'event and bitclk_in='1' then
wordclk_shift <= wordclk_shift(0) & wordclk_in;
bit_counter <= bit_counter + 1;
if wordclk_shift = "01" then
bit_counter <= (others => '0');
end if;
end if;
end process bit_count;
proc_adat_buffer : process (bitclk_in, bit_counter, data_in, adat_address)
proc_adat_buffer : process (bitclk_in)
begin
if bitclk_in'event and bitclk_in='1' then
case bit_counter is
when "00000000" =>
adat_buffer <= data_in(23 downto 20) & '1' & data_in(19 downto 16) & '1' & data_in(15 downto 12) & '1' & data_in(11 downto 8) & '1' & data_in(7 downto 4) & '1' & data_in(3 downto 0) & '1';
when "00000001" =>
adat_address <= adat_address +1;
adat_buffer <= '1' & data_in(0) & data_in(1) & data_in(2) & data_in(3) & '1' & data_in(4) & data_in(5) & data_in(6) & data_in(7) & '1' & data_in(8) & data_in(9) & data_in(10) & data_in(11) & '1' & data_in(12) & data_in(13) & data_in(14) & data_in(15) & '1' & data_in(16) & data_in(17) & data_in(18) & data_in(19) & '1' & data_in(20) & data_in(21) & data_in(22) & data_in(23);
adat_address <= adat_address +1;
when "00011110" =>
adat_buffer <= data_in(23 downto 20) & '1' & data_in(19 downto 16) & '1' & data_in(15 downto 12) & '1' & data_in(11 downto 8) & '1' & data_in(7 downto 4) & '1' & data_in(3 downto 0) & '1';
when "00011111" =>
adat_address <= adat_address +1;
adat_buffer <= '1' & data_in(0) & data_in(1) & data_in(2) & data_in(3) & '1' & data_in(4) & data_in(5) & data_in(6) & data_in(7) & '1' & data_in(8) & data_in(9) & data_in(10) & data_in(11) & '1' & data_in(12) & data_in(13) & data_in(14) & data_in(15) & '1' & data_in(16) & data_in(17) & data_in(18) & data_in(19) & '1' & data_in(20) & data_in(21) & data_in(22) & data_in(23);
adat_address <= adat_address +1;
when "00111100" =>
adat_buffer <= data_in(23 downto 20) & '1' & data_in(19 downto 16) & '1' & data_in(15 downto 12) & '1' & data_in(11 downto 8) & '1' & data_in(7 downto 4) & '1' & data_in(3 downto 0) & '1';
when "00111101" =>
adat_address <= adat_address +1;
adat_buffer <= '1' & data_in(0) & data_in(1) & data_in(2) & data_in(3) & '1' & data_in(4) & data_in(5) & data_in(6) & data_in(7) & '1' & data_in(8) & data_in(9) & data_in(10) & data_in(11) & '1' & data_in(12) & data_in(13) & data_in(14) & data_in(15) & '1' & data_in(16) & data_in(17) & data_in(18) & data_in(19) & '1' & data_in(20) & data_in(21) & data_in(22) & data_in(23);
adat_address <= adat_address +1;
when "01011010" =>
adat_buffer <= data_in(23 downto 20) & '1' & data_in(19 downto 16) & '1' & data_in(15 downto 12) & '1' & data_in(11 downto 8) & '1' & data_in(7 downto 4) & '1' & data_in(3 downto 0) & '1';
when "01011011" =>
adat_address <= adat_address +1;
adat_buffer <= '1' & data_in(0) & data_in(1) & data_in(2) & data_in(3) & '1' & data_in(4) & data_in(5) & data_in(6) & data_in(7) & '1' & data_in(8) & data_in(9) & data_in(10) & data_in(11) & '1' & data_in(12) & data_in(13) & data_in(14) & data_in(15) & '1' & data_in(16) & data_in(17) & data_in(18) & data_in(19) & '1' & data_in(20) & data_in(21) & data_in(22) & data_in(23);
adat_address <= adat_address +1;
when "01111000" =>
adat_buffer <= data_in(23 downto 20) & '1' & data_in(19 downto 16) & '1' & data_in(15 downto 12) & '1' & data_in(11 downto 8) & '1' & data_in(7 downto 4) & '1' & data_in(3 downto 0) & '1';
when "01111001" =>
adat_address <= adat_address +1;
adat_buffer <= '1' & data_in(0) & data_in(1) & data_in(2) & data_in(3) & '1' & data_in(4) & data_in(5) & data_in(6) & data_in(7) & '1' & data_in(8) & data_in(9) & data_in(10) & data_in(11) & '1' & data_in(12) & data_in(13) & data_in(14) & data_in(15) & '1' & data_in(16) & data_in(17) & data_in(18) & data_in(19) & '1' & data_in(20) & data_in(21) & data_in(22) & data_in(23);
adat_address <= adat_address +1;
when "10010110" =>
adat_buffer <= data_in(23 downto 20) & '1' & data_in(19 downto 16) & '1' & data_in(15 downto 12) & '1' & data_in(11 downto 8) & '1' & data_in(7 downto 4) & '1' & data_in(3 downto 0) & '1';
when "10010111" =>
adat_address <= adat_address +1;
adat_buffer <= '1' & data_in(0) & data_in(1) & data_in(2) & data_in(3) & '1' & data_in(4) & data_in(5) & data_in(6) & data_in(7) & '1' & data_in(8) & data_in(9) & data_in(10) & data_in(11) & '1' & data_in(12) & data_in(13) & data_in(14) & data_in(15) & '1' & data_in(16) & data_in(17) & data_in(18) & data_in(19) & '1' & data_in(20) & data_in(21) & data_in(22) & data_in(23);
adat_address <= adat_address +1;
when "10110100" =>
adat_buffer <= data_in(23 downto 20) & '1' & data_in(19 downto 16) & '1' & data_in(15 downto 12) & '1' & data_in(11 downto 8) & '1' & data_in(7 downto 4) & '1' & data_in(3 downto 0) & '1';
when "10110101" =>
adat_address <= adat_address +1;
adat_buffer <= '1' & data_in(0) & data_in(1) & data_in(2) & data_in(3) & '1' & data_in(4) & data_in(5) & data_in(6) & data_in(7) & '1' & data_in(8) & data_in(9) & data_in(10) & data_in(11) & '1' & data_in(12) & data_in(13) & data_in(14) & data_in(15) & '1' & data_in(16) & data_in(17) & data_in(18) & data_in(19) & '1' & data_in(20) & data_in(21) & data_in(22) & data_in(23);
adat_address <= adat_address +1;
when "11010010" =>
adat_buffer <= data_in(23 downto 20) & '1' & data_in(19 downto 16) & '1' & data_in(15 downto 12) & '1' & data_in(11 downto 8) & '1' & data_in(7 downto 4) & '1' & data_in(3 downto 0) & '1';
when "11010011" =>
adat_address <= adat_address +1;
when "11110000" =>
adat_buffer <= "0000" & '1' & "0000000000" & '1' & "00000000000000";
when "11110001" =>
adat_address <= (others => '0');
adat_buffer <= '1' & data_in(0) & data_in(1) & data_in(2) & data_in(3) & '1' & data_in(4) & data_in(5) & data_in(6) & data_in(7) & '1' & data_in(8) & data_in(9) & data_in(10) & data_in(11) & '1' & data_in(12) & data_in(13) & data_in(14) & data_in(15) & '1' & data_in(16) & data_in(17) & data_in(18) & data_in(19) & '1' & data_in(20) & data_in(21) & data_in(22) & data_in(23);
adat_address <= (others => '0');
when "11110000" =>
-- Sync sequence USER Dummy bits (no tx)
adat_buffer <= '1' & "0000000000" & '1' & "0000" & "00000000000000";
when others =>
adat_buffer <= adat_buffer(adat_buffer'left-1 downto 0) & '0';
adat_buffer <= adat_buffer(adat_buffer'left-1 downto 0) & '0';
end case;
end if;
end if;
end process proc_adat_buffer;
proc_adat_nrzi : process (bitclk_in)
317,92 → 325,6
end behavioral;
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
 
entity dp_ram is
port(
clock : in std_logic;
data : in std_logic_vector(23 downto 0);
rdaddress : in std_logic_vector(2 downto 0);
wraddress : in std_logic_vector(2 downto 0);
wren : in std_logic := '1';
q : out std_logic_vector(23 downto 0)
);
end dp_ram;
 
architecture syn of dp_ram is
 
SIGNAL sub_wire0 : std_logic_vector(23 downto 0);
 
component altsyncram
generic (
address_reg_b : string;
clock_enable_input_a : string;
clock_enable_input_b : string;
clock_enable_output_a : string;
clock_enable_output_b : string;
intended_device_family : string;
lpm_type : string;
numwords_a : natural;
numwords_b : natural;
operation_mode : string;
outdata_aclr_b : string;
outdata_reg_b : string;
power_up_uninitialized : string;
read_during_write_mode_mixed_ports : string;
widthad_a : natural;
widthad_b : natural;
width_a : natural;
width_b : natural;
width_byteena_a : natural
);
port(
wren_a : in std_logic ;
clock0 : in std_logic ;
address_a : in std_logic_vector(2 downto 0);
address_b : in std_logic_vector(2 downto 0);
q_b : out std_logic_vector(23 downto 0);
data_a : in std_logic_vector(23 downto 0)
);
end component;
 
begin
q <= sub_wire0(23 downto 0);
altsyncram_component : altsyncram
generic map(
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
intended_device_family => "Cyclone II",
lpm_type => "altsyncram",
numwords_a => 8,
numwords_b => 8,
operation_mode => "DUAL_PORT",
outdata_aclr_b => "NONE",
outdata_reg_b => "CLOCK0",
power_up_uninitialized => "FALSE",
read_during_write_mode_mixed_ports => "OLD_DATA",
widthad_a => 3,
widthad_b => 3,
width_a => 24,
width_b => 24,
width_byteena_a => 1
)
port map(
wren_a => wren,
clock0 => clock,
address_a => wraddress,
address_b => rdaddress,
data_a => data,
q_b => sub_wire0
);
end syn;
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
409,10 → 331,12
 
entity madi_to_adat is
port(
madi_clk_in : in std_logic;
madi_data_valid : in std_logic;
madi_symbol_in : in std_logic_vector(4 downto 0);
clk_125_in : in std_logic;
madi_in : in std_logic;
 
word_clk_in : in std_logic;
word_clk_out : out std_logic;
bit_clk_in : in std_logic;
adat_0_out : out std_logic;
429,7 → 353,8
architecture behavioral of madi_to_adat is
signal madi_channel : std_logic_vector(5 downto 0);
signal madi_data : std_logic_vector(23 downto 0);
signal madi_write : std_logic;
signal madi_write : std_logic;
signal word_clk : std_logic;
signal madi_write_0 : std_logic;
signal madi_write_1 : std_logic;
460,8 → 385,10
 
component madi_receiver is
port(
madi_clk_in : in std_logic;
clk_125_in : in std_logic;
madi_in : in std_logic;
madi_data_valid : in std_logic;
madi_symbol_in : in std_logic_vector(4 downto 0);
madi_write : out std_logic;
madi_wordclock : out std_logic;
492,14 → 419,18
);
end component dp_ram;
 
begin
begin
 
word_clk_out <= word_clk;
 
madi_receive : madi_receiver
port map(
madi_clk_in => madi_clk_in,
clk_125_in => clk_125_in,
madi_in => madi_in,
madi_data_valid => madi_data_valid,
madi_symbol_in => madi_symbol_in,
madi_write => madi_write,
madi_wordclock => word_clk_out,
madi_wordclock => word_clk,
madi_channel => madi_channel,
madi_data => madi_data
);
506,9 → 437,9
 
-- adat channel 0
 
dp_ram_0_write : process (clk_125_in)
dp_ram_0_write : process (madi_clk_in)
begin
if clk_125_in'event and clk_125_in='1' then
if madi_clk_in'event and madi_clk_in='1' then
if madi_channel(5 downto 3) = 0 and madi_write = '1' then
madi_write_0 <= '1';
else
519,7 → 450,7
 
dp_ram_0 : dp_ram
port map(
clock => clk_125_in,
clock => madi_clk_in,
data => madi_data,
rdaddress => adat_addr_0,
wraddress => madi_channel(2 downto 0),
532,15 → 463,15
data_in => adat_data_0,
address_out => adat_addr_0,
bitclk_in => bit_clk_in,
wordclk_in => word_clk_in,
wordclk_in => word_clk,
adat_out => adat_0_out
);
 
-- adat channel 1
 
dp_ram_1_write : process (clk_125_in)
dp_ram_1_write : process (madi_clk_in)
begin
if clk_125_in'event and clk_125_in='1' then
if madi_clk_in'event and madi_clk_in='1' then
if madi_channel(5 downto 3) = 1 and madi_write = '1' then
madi_write_1 <= '1';
else
551,7 → 482,7
 
dp_ram_1 : dp_ram
port map(
clock => clk_125_in,
clock => madi_clk_in,
data => madi_data,
rdaddress => adat_addr_1,
wraddress => madi_channel(2 downto 0),
564,15 → 495,15
data_in => adat_data_1,
address_out => adat_addr_1,
bitclk_in => bit_clk_in,
wordclk_in => word_clk_in,
wordclk_in => word_clk,
adat_out => adat_1_out
);
 
-- adat channel 2
 
dp_ram_2_write : process (clk_125_in)
dp_ram_2_write : process (madi_clk_in)
begin
if clk_125_in'event and clk_125_in='1' then
if madi_clk_in'event and madi_clk_in='1' then
if madi_channel(5 downto 3) = 2 and madi_write = '1' then
madi_write_2 <= '1';
else
583,7 → 514,7
 
dp_ram_2 : dp_ram
port map(
clock => clk_125_in,
clock => madi_clk_in,
data => madi_data,
rdaddress => adat_addr_2,
wraddress => madi_channel(2 downto 0),
596,15 → 527,15
data_in => adat_data_2,
address_out => adat_addr_2,
bitclk_in => bit_clk_in,
wordclk_in => word_clk_in,
wordclk_in => word_clk,
adat_out => adat_2_out
);
 
-- adat channel 3
 
dp_ram_3_write : process (clk_125_in)
dp_ram_3_write : process (madi_clk_in)
begin
if clk_125_in'event and clk_125_in='1' then
if madi_clk_in'event and madi_clk_in='1' then
if madi_channel(5 downto 3) = 3 and madi_write = '1' then
madi_write_3 <= '1';
else
615,7 → 546,7
 
dp_ram_3 : dp_ram
port map(
clock => clk_125_in,
clock => madi_clk_in,
data => madi_data,
rdaddress => adat_addr_3,
wraddress => madi_channel(2 downto 0),
628,15 → 559,15
data_in => adat_data_3,
address_out => adat_addr_3,
bitclk_in => bit_clk_in,
wordclk_in => word_clk_in,
wordclk_in => word_clk,
adat_out => adat_3_out
);
 
-- adat channel 4
 
dp_ram_4_write : process (clk_125_in)
dp_ram_4_write : process (madi_clk_in)
begin
if clk_125_in'event and clk_125_in='1' then
if madi_clk_in'event and madi_clk_in='1' then
if madi_channel(5 downto 3) = 4 and madi_write = '1' then
madi_write_4 <= '1';
else
647,7 → 578,7
 
dp_ram_4 : dp_ram
port map(
clock => clk_125_in,
clock => madi_clk_in,
data => madi_data,
rdaddress => adat_addr_4,
wraddress => madi_channel(2 downto 0),
660,15 → 591,15
data_in => adat_data_4,
address_out => adat_addr_4,
bitclk_in => bit_clk_in,
wordclk_in => word_clk_in,
wordclk_in => word_clk,
adat_out => adat_4_out
);
 
-- adat channel 5
 
dp_ram_5_write : process (clk_125_in)
dp_ram_5_write : process (madi_clk_in)
begin
if clk_125_in'event and clk_125_in='1' then
if madi_clk_in'event and madi_clk_in='1' then
if madi_channel(5 downto 3) = 5 and madi_write = '1' then
madi_write_5 <= '1';
else
679,7 → 610,7
 
dp_ram_5 : dp_ram
port map(
clock => clk_125_in,
clock => madi_clk_in,
data => madi_data,
rdaddress => adat_addr_5,
wraddress => madi_channel(2 downto 0),
692,15 → 623,15
data_in => adat_data_5,
address_out => adat_addr_5,
bitclk_in => bit_clk_in,
wordclk_in => word_clk_in,
wordclk_in => word_clk,
adat_out => adat_5_out
);
 
-- adat channel 6
 
dp_ram_6_write : process (clk_125_in)
dp_ram_6_write : process (madi_clk_in)
begin
if clk_125_in'event and clk_125_in='1' then
if madi_clk_in'event and madi_clk_in='1' then
if madi_channel(5 downto 3) = 6 and madi_write = '1' then
madi_write_6 <= '1';
else
711,7 → 642,7
 
dp_ram_6 : dp_ram
port map(
clock => clk_125_in,
clock => madi_clk_in,
data => madi_data,
rdaddress => adat_addr_6,
wraddress => madi_channel(2 downto 0),
724,15 → 655,15
data_in => adat_data_6,
address_out => adat_addr_6,
bitclk_in => bit_clk_in,
wordclk_in => word_clk_in,
wordclk_in => word_clk,
adat_out => adat_6_out
);
 
-- adat channel 7
 
dp_ram_7_write : process (clk_125_in)
dp_ram_7_write : process (madi_clk_in)
begin
if clk_125_in'event and clk_125_in='1' then
if madi_clk_in'event and madi_clk_in='1' then
if madi_channel(5 downto 3) = 7 and madi_write = '1' then
madi_write_7 <= '1';
else
743,7 → 674,7
 
dp_ram_7 : dp_ram
port map(
clock => clk_125_in,
clock => madi_clk_in,
data => madi_data,
rdaddress => adat_addr_7,
wraddress => madi_channel(2 downto 0),
756,7 → 687,7
data_in => adat_data_7,
address_out => adat_addr_7,
bitclk_in => bit_clk_in,
wordclk_in => word_clk_in,
wordclk_in => word_clk,
adat_out => adat_7_out
);
 

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