OpenCores

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/tags/alpha/xilinx_primitives.zip

tags/alpha/xilinx_primitives.zip Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: tags/alpha/README.txt =================================================================== --- tags/alpha/README.txt (revision 6) +++ tags/alpha/README.txt (nonexistent) @@ -1,119 +0,0 @@ - -This is a Mini-RISC CPU/Microcontroller that is mostly compatible with the -PIC 16C57 from Microchip. - - -Legal -===== - -PIC, Microship, etc. are Trademarks of Microchip Technology Inc. - -I have no idea if implementing this core will or will not violate -patents, copyrights or cause any other type of lawsuits. - -I provide this core AS IS, without any warrenties. If you decide to -build this core, you are responsible for any legal resolutions, such -as patents and copyrights, and perhaps others .... - - This source file(s) may be used and distributed without - restriction provided that this copyright statement is not - removed from the file and that any derivative work contains - the original copyright notice and the associated disclaimer. - - THIS SOURCE FILE(S) IS/ARE PROVIDED "AS IS" AND WITHOUT ANY - EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT - LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND - FITNESS FOR A PARTICULAR PURPOSE. - - -Motivation -========== - -After seeing the "free_risc8" on the free-ip web site, I got excited -and downloaded the core. Pretty soon I found out that it had many -many errors and omissions from the original 16C57. So I started looking -at the code. This is when I realized it was very badly designed and -could not be made run faster. So, I sat down and wrote my own PIC IP -core last night. A lot of work was spend in writing test code to ensure -that it was 100% compatible from the software point of view. - -- A PIC compatible Microcontroller that runs a lot faster -- Separate (External to the core) Program Memory -- Options to extend the core - - -Compatibility -============= - -This design should be fully software compatible to the Microchip Implementation -of the PIC 16C57, except for the following extensions: - -- Port A is full 8 bits wide -- Hardware stack is 4 level deep [original 2 levels] (can be easily expanded) -- Executions of instructions that modify the PC has become a lot more expensive - due to the pipeline and execution of instructions on every cycle. - Any instruction that writes to the PC (PC as destination (f), call, goto, retlw) - now takes 4 cycles to execute (instead of 2 in the origianl implementation). - The 4 'skip' instructions, remain as in the original implmentation: 1 cycle - if not skipped, 2 cycles if skipped. -- Sampling of IO ports might be off -- Timer and watchdog might be off a few cycles - - -Performance -=========== - -- Single cycle instruction execution, except as noted above. -- Here are results of some sample implementations: - - Xilinx Spartan2 (Device: xc2s30-6-cs144): Fmax: 50Mhz, Utilization: 66%, Ports: Tsu: 2.2nS, Tcq: 7.7nS - - Xilinx Virtex (Device: xcv50-4-cs144) : Fmax: 40Mhz, Utilization: 35%, Ports: Tsu: 3.0nS, Tcq: 6.2nS - - Xilinx VirtexE (Device: xcv50e-8-cs144): Fmax: 66Mhz, Utilization: 35%, Ports: Tsu: 1.7nS, Tcq: 4.5nS - Half of the cycle time is spend in routing delays. My guess is that by placing - proper locatiuon contrains and guiding the back-end tools, a significant - speed improvement can be achieved .... -- I estimat about 25K gates with the xilinx primitives, (excluding Register - File and Programm Memory). - -Implementing the core -===================== - -The only file you should edit if you really want to implement this core, is the -'primitives.v' file. It contains all parts that can be optimized, depending on -the technology used. It includes memories, and arithmetic modules. -I added a primitives_xilinx,v file and xilinx_primitives.zip which contain -primitives for xilinx. -'risc_core.v' is the top level without program memory and tristate Io buffers for ports. -This is probably a good starting point if you want to instantiate the core in to a larger -design. If you just want a PIC clone, take a loot at 'risc_core_top.v', it was written -with Xilinx FPGAs in mind, but should be easily addaptred to other vendors FPGAs - just -replace the memory blocks ... - -To-Do -===== - -Things that need to be done - -1) Write more test/compliance test vectors - - Verify that all instructions after a goto/call/retlw/write to PCL are not executed - - Verify ALU - - Timer and Watchdog tests - - Perhaps some other ereas ? - -2) Extensions ? - - I guess this is on a "as needed" basis - - A friend suggested to add registers that can be shared by two or more cores in a MP type configuration - -Author -====== - -I have been doing ASIC design, verification and synthesis for over 15 years. -This core is only a "mid-night hack", and should used with caution. - -I'd also like to know if anyone will actually use this core. Please send me a -note if you will ! - -Rudolf Usselmann -russelmann@hotmail.com - -Feel free to send me comments, suggestions and bug reports. - Index: tags/alpha/scode/tmr_wdt.asm =================================================================== --- tags/alpha/scode/tmr_wdt.asm (revision 6) +++ tags/alpha/scode/tmr_wdt.asm (nonexistent) @@ -1,155 +0,0 @@ -;///////////////////////////////////////////////////////////////////// -;//// //// -;//// Mini-RISC-1 //// -;//// Timer / Wachdog //// -;//// Tests Timer / Wachdog //// -;//// //// -;//// Author: Rudolf Usselmann //// -;//// russelmann@hotmail.com //// -;//// //// -;///////////////////////////////////////////////////////////////////// -;//// //// -;//// Copyright (C) 2000 Rudolf Usselmann //// -;//// russelmann@hotmail.com //// -;//// //// -;//// This source file may be used and distributed without //// -;//// restriction provided that this copyright statement is not //// -;//// removed from the file and that any derivative work contains //// -;//// the original copyright notice and the associated disclaimer.//// -;//// //// -;//// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY //// -;//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT //// -;//// LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND //// -;//// FITNESS FOR A PARTICULAR PURPOSE. //// -;//// //// -;///////////////////////////////////////////////////////////////////// - - list p=16c57 - #include p16c5x.inc - -; global Registers -r0 equ 0x8 -r1 equ 0x9 -r2 equ 0xa -r3 equ 0xb -r4 equ 0xc -r5 equ 0xd -r6 equ 0xe -r7 equ 0xf - -; banked Registers -br0 equ 0x10 -br1 equ 0x11 -br2 equ 0x12 -br3 equ 0x13 -br4 equ 0x14 -br5 equ 0x15 -br6 equ 0x16 -br7 equ 0x17 -br8 equ 0x18 -br9 equ 0x19 -br10 equ 0x1a -br11 equ 0x1b -br12 equ 0x1c -br13 equ 0x1d -br14 equ 0x1e -br15 equ 0x1f - - -; PORTB Indicates Test Number -; PORTA Indicates Status: 0 - Running; 1 - done OK; ff - stoped on error - -main ; Main code entry - ; Port IO Test - ; All ports have a Pull up resistor - - ; SETUP all ports - clrw - movwf FSR - movwf PORTA - movwf PORTB - movwf PORTC - tris PORTA - tris PORTB - tris PORTC - - ; --------------------------------------- - ; ---- Test RMW on Register fil ---- - ; --------------------------------------- - - movlw 0x01 ; TEST 1 - movwf PORTB ; Set Test Number - - movlw 0x00 - option - movwf TMR0 - clrwdt - nop - nop - nop - nop - - clrw - movwf r1 - -loop2 ; repeat 256 times - clrw - movwf r0 - - - ; repeat 256 times -loop1 - movfw TMR0 - decfsz r0,F - goto loop1 - - decfsz r1,F - goto loop2 - - - - nop - nop - nop - nop - nop - nop - - clrw - movwf TMR0 - clrwdt - - nop - nop - nop - nop - movlw 0x01 - movwf PORTA - nop - nop - nop - nop -good ; Loop in good on success - goto good - nop - nop - nop - nop - -lerr - movlw 0xff - movwf PORTA - - nop - nop - nop - nop -lerr_loop ; Loop in lerr on failure - goto lerr_loop - nop - nop - nop - nop - - END - Index: tags/alpha/scode/sanity1.rom =================================================================== --- tags/alpha/scode/sanity1.rom (revision 6) +++ tags/alpha/scode/sanity1.rom (nonexistent) @@ -1,181 +0,0 @@ - -@000 040 -@001 025 -@002 026 -@003 027 -@004 FFF -@005 005 -@006 006 -@007 007 -@008 705 -@009 AAF -@00A 725 -@00B AAF -@00C 745 -@00D AAF -@00E 765 -@00F AAF -@010 785 -@011 AAF -@012 7A5 -@013 AAF -@014 7C5 -@015 AAF -@016 7E5 -@017 AAF -@018 706 -@019 AAF -@01A 726 -@01B AAF -@01C 746 -@01D AAF -@01E 766 -@01F AAF -@020 786 -@021 AAF -@022 7A6 -@023 AAF -@024 7C6 -@025 AAF -@026 7E6 -@027 AAF -@028 707 -@029 AAF -@02A 727 -@02B AAF -@02C 747 -@02D AAF -@02E 767 -@02F AAF -@030 787 -@031 AAF -@032 7A7 -@033 AAF -@034 7C5 -@035 AAF -@036 7E7 -@037 AAF -@038 040 -@039 005 -@03A 006 -@03B 007 -@03C 040 -@03D FAA -@03E 025 -@03F 026 -@040 027 -@041 605 -@042 AAF -@043 725 -@044 AAF -@045 645 -@046 AAF -@047 765 -@048 AAF -@049 685 -@04A AAF -@04B 7A5 -@04C AAF -@04D 6C5 -@04E AAF -@04F 7E5 -@050 AAF -@051 606 -@052 AAF -@053 726 -@054 AAF -@055 646 -@056 AAF -@057 766 -@058 AAF -@059 686 -@05A AAF -@05B 7A6 -@05C AAF -@05D 6C6 -@05E AAF -@05F 7E6 -@060 AAF -@061 607 -@062 AAF -@063 727 -@064 AAF -@065 647 -@066 AAF -@067 767 -@068 AAF -@069 687 -@06A AAF -@06B 7A7 -@06C AAF -@06D 6C7 -@06E AAF -@06F 7E7 -@070 AAF -@071 040 -@072 F55 -@073 025 -@074 026 -@075 027 -@076 705 -@077 AAF -@078 625 -@079 AAF -@07A 745 -@07B AAF -@07C 665 -@07D AAF -@07E 785 -@07F AAF -@080 6A5 -@081 AAF -@082 7C5 -@083 AAF -@084 6E5 -@085 AAF -@086 706 -@087 AAF -@088 626 -@089 AAF -@08A 746 -@08B AAF -@08C 666 -@08D AAF -@08E 786 -@08F AAF -@090 6A6 -@091 AAF -@092 7C6 -@093 AAF -@094 6E6 -@095 AAF -@096 707 -@097 AAF -@098 627 -@099 AAF -@09A 747 -@09B AAF -@09C 667 -@09D AAF -@09E 787 -@09F AAF -@0A0 6A7 -@0A1 AAF -@0A2 7C7 -@0A3 AAF -@0A4 6E7 -@0A5 AAF -@0A6 000 -@0A7 000 -@0A8 000 -@0A9 000 -@0AA AAA -@0AB 000 -@0AC 000 -@0AD 000 -@0AE 000 -@0AF AAF -@0B0 000 -@0B1 000 -@0B2 000 -@0B3 000 Index: tags/alpha/scode/rf1.rom =================================================================== --- tags/alpha/scode/rf1.rom (revision 6) +++ tags/alpha/scode/rf1.rom (nonexistent) @@ -1,584 +0,0 @@ - -@000 040 -@001 024 -@002 025 -@003 026 -@004 027 -@005 005 -@006 006 -@007 007 -@008 5A3 -@009 C81 -@00A 028 -@00B C82 -@00C 029 -@00D C83 -@00E 02A -@00F C84 -@010 02B -@011 C85 -@012 02C -@013 C86 -@014 02D -@015 C87 -@016 02E -@017 C88 -@018 02F -@019 C90 -@01A 030 -@01B C91 -@01C 031 -@01D C92 -@01E 032 -@01F C93 -@020 033 -@021 C94 -@022 034 -@023 C95 -@024 035 -@025 C96 -@026 036 -@027 C97 -@028 037 -@029 C98 -@02A 038 -@02B C99 -@02C 039 -@02D C9A -@02E 03A -@02F C9B -@030 03B -@031 C9C -@032 03C -@033 C9D -@034 03D -@035 C9E -@036 03E -@037 C9F -@038 03F -@039 5A4 -@03A CA0 -@03B 030 -@03C CA1 -@03D 031 -@03E CA2 -@03F 032 -@040 CA3 -@041 033 -@042 CA4 -@043 034 -@044 CA5 -@045 035 -@046 CA6 -@047 036 -@048 CA7 -@049 037 -@04A CA8 -@04B 038 -@04C CA9 -@04D 039 -@04E CAA -@04F 03A -@050 CAB -@051 03B -@052 CAC -@053 03C -@054 CAD -@055 03D -@056 CAE -@057 03E -@058 CAF -@059 03F -@05A 4A4 -@05B 5C4 -@05C CB0 -@05D 030 -@05E CB1 -@05F 031 -@060 CB2 -@061 032 -@062 CB3 -@063 033 -@064 CB4 -@065 034 -@066 CB5 -@067 035 -@068 CB6 -@069 036 -@06A CB7 -@06B 037 -@06C CB8 -@06D 038 -@06E CB9 -@06F 039 -@070 CBA -@071 03A -@072 CBB -@073 03B -@074 CBC -@075 03C -@076 CBD -@077 03D -@078 CBE -@079 03E -@07A CBF -@07B 03F -@07C 5A4 -@07D 5C4 -@07E CC0 -@07F 030 -@080 CC1 -@081 031 -@082 CC2 -@083 032 -@084 CC3 -@085 033 -@086 CC4 -@087 034 -@088 CC5 -@089 035 -@08A CC6 -@08B 036 -@08C CC7 -@08D 037 -@08E CC8 -@08F 038 -@090 CC9 -@091 039 -@092 CCA -@093 03A -@094 CCB -@095 03B -@096 CCC -@097 03C -@098 CCD -@099 03D -@09A CCE -@09B 03E -@09C CCF -@09D 03F -@09E C01 -@09F 026 -@0A0 040 -@0A1 024 -@0A2 C81 -@0A3 088 -@0A4 743 -@0A5 A3C -@0A6 C82 -@0A7 089 -@0A8 743 -@0A9 A3C -@0AA C83 -@0AB 08A -@0AC 743 -@0AD A3C -@0AE C84 -@0AF 08B -@0B0 743 -@0B1 A3C -@0B2 C85 -@0B3 08C -@0B4 743 -@0B5 A3C -@0B6 C86 -@0B7 08D -@0B8 743 -@0B9 A3C -@0BA C87 -@0BB 08E -@0BC 743 -@0BD A3C -@0BE C88 -@0BF 08F -@0C0 743 -@0C1 A3C -@0C2 C90 -@0C3 090 -@0C4 743 -@0C5 A3C -@0C6 C91 -@0C7 091 -@0C8 743 -@0C9 A3C -@0CA C92 -@0CB 092 -@0CC 743 -@0CD A3C -@0CE C93 -@0CF 093 -@0D0 743 -@0D1 A3C -@0D2 C94 -@0D3 094 -@0D4 743 -@0D5 A3C -@0D6 C95 -@0D7 095 -@0D8 743 -@0D9 A3C -@0DA C96 -@0DB 096 -@0DC 743 -@0DD A3C -@0DE C97 -@0DF 097 -@0E0 743 -@0E1 A3C -@0E2 C98 -@0E3 098 -@0E4 743 -@0E5 A3C -@0E6 C99 -@0E7 099 -@0E8 743 -@0E9 A3C -@0EA C9A -@0EB 09A -@0EC 743 -@0ED A3C -@0EE C9B -@0EF 09B -@0F0 743 -@0F1 A3C -@0F2 C9C -@0F3 09C -@0F4 743 -@0F5 A3C -@0F6 C9D -@0F7 09D -@0F8 743 -@0F9 A3C -@0FA C9E -@0FB 09E -@0FC 743 -@0FD A3C -@0FE C9F -@0FF 09F -@100 743 -@101 A3C -@102 C02 -@103 026 -@104 5A4 -@105 C81 -@106 088 -@107 743 -@108 A3C -@109 C82 -@10A 089 -@10B 743 -@10C A3C -@10D C83 -@10E 08A -@10F 743 -@110 A3C -@111 C84 -@112 08B -@113 743 -@114 A3C -@115 C85 -@116 08C -@117 743 -@118 A3C -@119 C86 -@11A 08D -@11B 743 -@11C A3C -@11D C87 -@11E 08E -@11F 743 -@120 A3C -@121 C88 -@122 08F -@123 743 -@124 A3C -@125 CA0 -@126 090 -@127 743 -@128 A3C -@129 CA1 -@12A 091 -@12B 743 -@12C A3C -@12D CA2 -@12E 092 -@12F 743 -@130 A3C -@131 CA3 -@132 093 -@133 743 -@134 A3C -@135 CA4 -@136 094 -@137 743 -@138 A3C -@139 CA5 -@13A 095 -@13B 743 -@13C A3C -@13D CA6 -@13E 096 -@13F 743 -@140 A3C -@141 CA7 -@142 097 -@143 743 -@144 A3C -@145 CA8 -@146 098 -@147 743 -@148 A3C -@149 CA9 -@14A 099 -@14B 743 -@14C A3C -@14D CAA -@14E 09A -@14F 743 -@150 A3C -@151 CAB -@152 09B -@153 743 -@154 A3C -@155 CAC -@156 09C -@157 743 -@158 A3C -@159 CAD -@15A 09D -@15B 743 -@15C A3C -@15D CAE -@15E 09E -@15F 743 -@160 A3C -@161 CAF -@162 09F -@163 743 -@164 A3C -@165 C03 -@166 026 -@167 4A4 -@168 5C4 -@169 C81 -@16A 088 -@16B 743 -@16C A3C -@16D C82 -@16E 089 -@16F 743 -@170 A3C -@171 C83 -@172 08A -@173 743 -@174 A3C -@175 C84 -@176 08B -@177 743 -@178 A3C -@179 C85 -@17A 08C -@17B 743 -@17C A3C -@17D C86 -@17E 08D -@17F 743 -@180 A3C -@181 C87 -@182 08E -@183 743 -@184 A3C -@185 C88 -@186 08F -@187 743 -@188 A3C -@189 CB0 -@18A 090 -@18B 743 -@18C A3C -@18D CB1 -@18E 091 -@18F 743 -@190 A3C -@191 CB2 -@192 092 -@193 743 -@194 A3C -@195 CB3 -@196 093 -@197 743 -@198 A3C -@199 CB4 -@19A 094 -@19B 743 -@19C A3C -@19D CB5 -@19E 095 -@19F 743 -@1A0 A3C -@1A1 CB6 -@1A2 096 -@1A3 743 -@1A4 A3C -@1A5 CB7 -@1A6 097 -@1A7 743 -@1A8 A3C -@1A9 CB8 -@1AA 098 -@1AB 743 -@1AC A3C -@1AD CB9 -@1AE 099 -@1AF 743 -@1B0 A3C -@1B1 CBA -@1B2 09A -@1B3 743 -@1B4 A3C -@1B5 CBB -@1B6 09B -@1B7 743 -@1B8 A3C -@1B9 CBC -@1BA 09C -@1BB 743 -@1BC A3C -@1BD CBD -@1BE 09D -@1BF 743 -@1C0 A3C -@1C1 CBE -@1C2 09E -@1C3 743 -@1C4 A3C -@1C5 CBF -@1C6 09F -@1C7 743 -@1C8 A3C -@1C9 C04 -@1CA 026 -@1CB 5A4 -@1CC 5C4 -@1CD C81 -@1CE 088 -@1CF 743 -@1D0 A3C -@1D1 C82 -@1D2 089 -@1D3 743 -@1D4 A3C -@1D5 C83 -@1D6 08A -@1D7 743 -@1D8 A3C -@1D9 C84 -@1DA 08B -@1DB 743 -@1DC A3C -@1DD C85 -@1DE 08C -@1DF 743 -@1E0 A3C -@1E1 C86 -@1E2 08D -@1E3 743 -@1E4 A3C -@1E5 C87 -@1E6 08E -@1E7 743 -@1E8 A3C -@1E9 C88 -@1EA 08F -@1EB 743 -@1EC A3C -@1ED CC0 -@1EE 090 -@1EF 743 -@1F0 A3C -@1F1 CC1 -@1F2 091 -@1F3 743 -@1F4 A3C -@1F5 CC2 -@1F6 092 -@1F7 743 -@1F8 A3C -@1F9 CC3 -@1FA 093 -@1FB 743 -@1FC A3C -@1FD CC4 -@1FE 094 -@1FF 743 -@200 A3C -@201 CC5 -@202 095 -@203 743 -@204 A3C -@205 CC6 -@206 096 -@207 743 -@208 A3C -@209 CC7 -@20A 097 -@20B 743 -@20C A3C -@20D CC8 -@20E 098 -@20F 743 -@210 A3C -@211 CC9 -@212 099 -@213 743 -@214 A3C -@215 CCA -@216 09A -@217 743 -@218 A3C -@219 CCB -@21A 09B -@21B 743 -@21C A3C -@21D CCC -@21E 09C -@21F 743 -@220 A3C -@221 CCD -@222 09D -@223 743 -@224 A3C -@225 CCE -@226 09E -@227 743 -@228 A3C -@229 CCF -@22A 09F -@22B 743 -@22C A3C -@22D 000 -@22E 000 -@22F 000 -@230 000 -@231 C01 -@232 025 -@233 000 -@234 000 -@235 000 -@236 000 -@237 A37 -@238 000 -@239 000 -@23A 000 -@23B 000 -@23C CFF -@23D 025 -@23E 000 -@23F 000 -@240 000 -@241 000 -@242 A42 -@243 000 -@244 000 -@245 000 -@246 000 Index: tags/alpha/scode/sanity2.rom =================================================================== --- tags/alpha/scode/sanity2.rom (revision 6) +++ tags/alpha/scode/sanity2.rom (nonexistent) @@ -1,282 +0,0 @@ - -@000 040 -@001 024 -@002 025 -@003 026 -@004 027 -@005 005 -@006 006 -@007 007 -@008 C0B -@009 028 -@00A 202 -@00B 088 -@00C 743 -@00D B23 -@00E C01 -@00F 026 -@010 C13 -@011 02B -@012 202 -@013 08B -@014 743 -@015 B23 -@016 C02 -@017 026 -@018 C1D -@019 022 -@01A B23 -@01B B23 -@01C B23 -@01D A21 -@01E B23 -@01F B23 -@020 B23 -@021 C03 -@022 026 -@023 C28 -@024 022 -@025 B23 -@026 B23 -@027 B23 -@028 A2C -@029 B23 -@02A B23 -@02B B23 -@02C C04 -@02D 026 -@02E C35 -@02F 028 -@030 C32 -@031 088 -@032 1E2 -@033 B23 -@034 B23 -@035 B23 -@036 A3A -@037 B23 -@038 B23 -@039 B23 -@03A C05 -@03B 026 -@03C C43 -@03D 038 -@03E C40 -@03F 098 -@040 1E2 -@041 B23 -@042 B23 -@043 B23 -@044 A48 -@045 B23 -@046 B23 -@047 B23 -@048 C06 -@049 026 -@04A A60 -@060 522 -@061 B23 -@062 B23 -@063 A68 -@064 B23 -@065 B23 -@066 B23 -@067 B23 -@068 C07 -@069 026 -@06A 542 -@06B B23 -@06C B23 -@06D B23 -@06E B23 -@06F A72 -@070 B23 -@071 B23 -@072 C08 -@073 026 -@074 A7C -@075 B23 -@076 B23 -@077 B23 -@078 B23 -@079 A7D -@07A B23 -@07B B23 -@07C 442 -@07D C09 -@07E 026 -@07F A8A -@080 000 -@081 000 -@082 000 -@083 000 -@084 CFF -@085 025 -@086 000 -@087 000 -@088 000 -@089 000 -@08A C0A -@08B 026 -@08C 9A5 -@08D 028 -@08E C55 -@08F 088 -@090 743 -@091 B23 -@092 9A7 -@093 028 -@094 CAA -@095 088 -@096 743 -@097 B23 -@098 9AA -@099 028 -@09A CC3 -@09B 088 -@09C 743 -@09D B23 -@09E 9AE -@09F 028 -@0A0 C3C -@0A1 088 -@0A2 743 -@0A3 B23 -@0A4 AC5 -@0A5 855 -@0A6 B23 -@0A7 000 -@0A8 8AA -@0A9 B23 -@0AA 000 -@0AB 000 -@0AC 8C3 -@0AD B23 -@0AE 000 -@0AF 000 -@0B0 000 -@0B1 83C -@0B2 B23 -@0B3 1E2 -@0B4 8FF -@0B5 8FE -@0B6 8FD -@0B7 8FC -@0B8 8FB -@0B9 8FA -@0BA 8F9 -@0BB 8F8 -@0BC 8F7 -@0BD 8F6 -@0BE 8F5 -@0BF B23 -@0C0 B23 -@0C1 B23 -@0C2 B23 -@0C3 B23 -@0C4 B23 -@0C5 C0B -@0C6 026 -@0C7 C00 -@0C8 028 -@0C9 9B3 -@0CA 268 -@0CB 0A8 -@0CC 743 -@0CD B23 -@0CE C01 -@0CF 028 -@0D0 9B3 -@0D1 268 -@0D2 0A8 -@0D3 743 -@0D4 B23 -@0D5 C02 -@0D6 028 -@0D7 9B3 -@0D8 268 -@0D9 0A8 -@0DA 743 -@0DB B23 -@0DC C03 -@0DD 028 -@0DE 9B3 -@0DF 268 -@0E0 0A8 -@0E1 743 -@0E2 B23 -@0E3 C04 -@0E4 028 -@0E5 9B3 -@0E6 268 -@0E7 0A8 -@0E8 743 -@0E9 B23 -@0EA C05 -@0EB 028 -@0EC 9B3 -@0ED 268 -@0EE 0A8 -@0EF 743 -@0F0 B23 -@0F1 C06 -@0F2 028 -@0F3 9B3 -@0F4 268 -@0F5 0A8 -@0F6 743 -@0F7 B23 -@0F8 C07 -@0F9 028 -@0FA 9B3 -@0FB 268 -@0FC 0A8 -@0FD 743 -@0FE B23 -@0FF C08 -@100 028 -@101 9B3 -@102 268 -@103 0A8 -@104 743 -@105 B23 -@106 C09 -@107 028 -@108 9B3 -@109 268 -@10A 0A8 -@10B 743 -@10C B23 -@10D C0A -@10E 028 -@10F 9B3 -@110 268 -@111 0A8 -@112 743 -@113 B23 -@114 000 -@115 000 -@116 000 -@117 000 -@118 C01 -@119 025 -@11A 000 -@11B 000 -@11C 000 -@11D 000 -@11E B1E -@11F 000 -@120 000 -@121 000 -@122 000 -@123 CFF -@124 025 -@125 000 -@126 000 -@127 000 -@128 000 -@129 B29 -@12A 000 -@12B 000 -@12C 000 -@12D 000 Index: tags/alpha/scode/rf2.rom =================================================================== --- tags/alpha/scode/rf2.rom (revision 6) +++ tags/alpha/scode/rf2.rom (nonexistent) @@ -1,720 +0,0 @@ - -@000 040 -@001 024 -@002 025 -@003 026 -@004 027 -@005 005 -@006 006 -@007 007 -@008 5A3 -@009 C81 -@00A 028 -@00B C82 -@00C 029 -@00D C83 -@00E 02A -@00F C84 -@010 02B -@011 C85 -@012 02C -@013 C86 -@014 02D -@015 C87 -@016 02E -@017 C88 -@018 02F -@019 C90 -@01A 030 -@01B C91 -@01C 031 -@01D C92 -@01E 032 -@01F C93 -@020 033 -@021 C94 -@022 034 -@023 C95 -@024 035 -@025 C96 -@026 036 -@027 C97 -@028 037 -@029 C98 -@02A 038 -@02B C99 -@02C 039 -@02D C9A -@02E 03A -@02F C9B -@030 03B -@031 C9C -@032 03C -@033 C9D -@034 03D -@035 C9E -@036 03E -@037 C9F -@038 03F -@039 5A4 -@03A CA0 -@03B 030 -@03C CA1 -@03D 031 -@03E CA2 -@03F 032 -@040 CA3 -@041 033 -@042 CA4 -@043 034 -@044 CA5 -@045 035 -@046 CA6 -@047 036 -@048 CA7 -@049 037 -@04A CA8 -@04B 038 -@04C CA9 -@04D 039 -@04E CAA -@04F 03A -@050 CAB -@051 03B -@052 CAC -@053 03C -@054 CAD -@055 03D -@056 CAE -@057 03E -@058 CAF -@059 03F -@05A 4A4 -@05B 5C4 -@05C CB0 -@05D 030 -@05E CB1 -@05F 031 -@060 CB2 -@061 032 -@062 CB3 -@063 033 -@064 CB4 -@065 034 -@066 CB5 -@067 035 -@068 CB6 -@069 036 -@06A CB7 -@06B 037 -@06C CB8 -@06D 038 -@06E CB9 -@06F 039 -@070 CBA -@071 03A -@072 CBB -@073 03B -@074 CBC -@075 03C -@076 CBD -@077 03D -@078 CBE -@079 03E -@07A CBF -@07B 03F -@07C 5A4 -@07D 5C4 -@07E CC0 -@07F 030 -@080 CC1 -@081 031 -@082 CC2 -@083 032 -@084 CC3 -@085 033 -@086 CC4 -@087 034 -@088 CC5 -@089 035 -@08A CC6 -@08B 036 -@08C CC7 -@08D 037 -@08E CC8 -@08F 038 -@090 CC9 -@091 039 -@092 CCA -@093 03A -@094 CCB -@095 03B -@096 CCC -@097 03C -@098 CCD -@099 03D -@09A CCE -@09B 03E -@09C CCF -@09D 03F -@09E C08 -@09F 024 -@0A0 260 -@0A1 2A4 -@0A2 260 -@0A3 2A4 -@0A4 260 -@0A5 2A4 -@0A6 260 -@0A7 2A4 -@0A8 260 -@0A9 2A4 -@0AA 260 -@0AB 2A4 -@0AC 260 -@0AD 2A4 -@0AE 260 -@0AF 2A4 -@0B0 C10 -@0B1 024 -@0B2 260 -@0B3 2A4 -@0B4 260 -@0B5 2A4 -@0B6 260 -@0B7 2A4 -@0B8 260 -@0B9 2A4 -@0BA 260 -@0BB 2A4 -@0BC 260 -@0BD 2A4 -@0BE 260 -@0BF 2A4 -@0C0 260 -@0C1 2A4 -@0C2 260 -@0C3 2A4 -@0C4 260 -@0C5 2A4 -@0C6 260 -@0C7 2A4 -@0C8 260 -@0C9 2A4 -@0CA 260 -@0CB 2A4 -@0CC 260 -@0CD 2A4 -@0CE 260 -@0CF 2A4 -@0D0 260 -@0D1 2A4 -@0D2 C10 -@0D3 024 -@0D4 5A4 -@0D5 260 -@0D6 2A4 -@0D7 260 -@0D8 2A4 -@0D9 260 -@0DA 2A4 -@0DB 260 -@0DC 2A4 -@0DD 260 -@0DE 2A4 -@0DF 260 -@0E0 2A4 -@0E1 260 -@0E2 2A4 -@0E3 260 -@0E4 2A4 -@0E5 260 -@0E6 2A4 -@0E7 260 -@0E8 2A4 -@0E9 260 -@0EA 2A4 -@0EB 260 -@0EC 2A4 -@0ED 260 -@0EE 2A4 -@0EF 260 -@0F0 2A4 -@0F1 260 -@0F2 2A4 -@0F3 260 -@0F4 2A4 -@0F5 C10 -@0F6 024 -@0F7 5C4 -@0F8 260 -@0F9 2A4 -@0FA 260 -@0FB 2A4 -@0FC 260 -@0FD 2A4 -@0FE 260 -@0FF 2A4 -@100 260 -@101 2A4 -@102 260 -@103 2A4 -@104 260 -@105 2A4 -@106 260 -@107 2A4 -@108 260 -@109 2A4 -@10A 260 -@10B 2A4 -@10C 260 -@10D 2A4 -@10E 260 -@10F 2A4 -@110 260 -@111 2A4 -@112 260 -@113 2A4 -@114 260 -@115 2A4 -@116 260 -@117 2A4 -@118 C10 -@119 024 -@11A 5A4 -@11B 5C4 -@11C 260 -@11D 2A4 -@11E 260 -@11F 2A4 -@120 260 -@121 2A4 -@122 260 -@123 2A4 -@124 260 -@125 2A4 -@126 260 -@127 2A4 -@128 260 -@129 2A4 -@12A 260 -@12B 2A4 -@12C 260 -@12D 2A4 -@12E 260 -@12F 2A4 -@130 260 -@131 2A4 -@132 260 -@133 2A4 -@134 260 -@135 2A4 -@136 260 -@137 2A4 -@138 260 -@139 2A4 -@13A 260 -@13B 2A4 -@13C C01 -@13D 026 -@13E C08 -@13F 024 -@140 C7E -@141 080 -@142 743 -@143 AC4 -@144 C7D -@145 2A4 -@146 080 -@147 743 -@148 AC4 -@149 C7C -@14A 2A4 -@14B 080 -@14C 743 -@14D AC4 -@14E C7B -@14F 2A4 -@150 080 -@151 743 -@152 AC4 -@153 C7A -@154 2A4 -@155 080 -@156 743 -@157 AC4 -@158 C79 -@159 2A4 -@15A 080 -@15B 743 -@15C AC4 -@15D C78 -@15E 2A4 -@15F 080 -@160 743 -@161 AC4 -@162 C77 -@163 2A4 -@164 080 -@165 743 -@166 AC4 -@167 C10 -@168 024 -@169 C6F -@16A 080 -@16B 743 -@16C AC4 -@16D C6E -@16E 2A4 -@16F 080 -@170 743 -@171 AC4 -@172 C6D -@173 2A4 -@174 080 -@175 743 -@176 AC4 -@177 C6C -@178 2A4 -@179 080 -@17A 743 -@17B AC4 -@17C C6B -@17D 2A4 -@17E 080 -@17F 743 -@180 AC4 -@181 C6A -@182 2A4 -@183 080 -@184 743 -@185 AC4 -@186 C69 -@187 2A4 -@188 080 -@189 743 -@18A AC4 -@18B C68 -@18C 2A4 -@18D 080 -@18E 743 -@18F AC4 -@190 C67 -@191 2A4 -@192 080 -@193 743 -@194 AC4 -@195 C66 -@196 2A4 -@197 080 -@198 743 -@199 AC4 -@19A C65 -@19B 2A4 -@19C 080 -@19D 743 -@19E AC4 -@19F C64 -@1A0 2A4 -@1A1 080 -@1A2 743 -@1A3 AC4 -@1A4 C63 -@1A5 2A4 -@1A6 080 -@1A7 743 -@1A8 AC4 -@1A9 C62 -@1AA 2A4 -@1AB 080 -@1AC 743 -@1AD AC4 -@1AE C61 -@1AF 2A4 -@1B0 080 -@1B1 743 -@1B2 AC4 -@1B3 C60 -@1B4 2A4 -@1B5 080 -@1B6 743 -@1B7 AC4 -@1B8 C02 -@1B9 026 -@1BA C10 -@1BB 024 -@1BC 5A4 -@1BD C5F -@1BE 080 -@1BF 743 -@1C0 AC4 -@1C1 C5E -@1C2 2A4 -@1C3 080 -@1C4 743 -@1C5 AC4 -@1C6 C5D -@1C7 2A4 -@1C8 080 -@1C9 743 -@1CA AC4 -@1CB C5C -@1CC 2A4 -@1CD 080 -@1CE 743 -@1CF AC4 -@1D0 C5B -@1D1 2A4 -@1D2 080 -@1D3 743 -@1D4 AC4 -@1D5 C5A -@1D6 2A4 -@1D7 080 -@1D8 743 -@1D9 AC4 -@1DA C59 -@1DB 2A4 -@1DC 080 -@1DD 743 -@1DE AC4 -@1DF C58 -@1E0 2A4 -@1E1 080 -@1E2 743 -@1E3 AC4 -@1E4 C57 -@1E5 2A4 -@1E6 080 -@1E7 743 -@1E8 AC4 -@1E9 C56 -@1EA 2A4 -@1EB 080 -@1EC 743 -@1ED AC4 -@1EE C55 -@1EF 2A4 -@1F0 080 -@1F1 743 -@1F2 AC4 -@1F3 C54 -@1F4 2A4 -@1F5 080 -@1F6 743 -@1F7 AC4 -@1F8 C53 -@1F9 2A4 -@1FA 080 -@1FB 743 -@1FC AC4 -@1FD C52 -@1FE 2A4 -@1FF 080 -@200 743 -@201 AC4 -@202 C51 -@203 2A4 -@204 080 -@205 743 -@206 AC4 -@207 C50 -@208 2A4 -@209 080 -@20A 743 -@20B AC4 -@20C C03 -@20D 026 -@20E C10 -@20F 024 -@210 5C4 -@211 C4F -@212 080 -@213 743 -@214 AC4 -@215 C4E -@216 2A4 -@217 080 -@218 743 -@219 AC4 -@21A C4D -@21B 2A4 -@21C 080 -@21D 743 -@21E AC4 -@21F C4C -@220 2A4 -@221 080 -@222 743 -@223 AC4 -@224 C4B -@225 2A4 -@226 080 -@227 743 -@228 AC4 -@229 C4A -@22A 2A4 -@22B 080 -@22C 743 -@22D AC4 -@22E C49 -@22F 2A4 -@230 080 -@231 743 -@232 AC4 -@233 C48 -@234 2A4 -@235 080 -@236 743 -@237 AC4 -@238 C47 -@239 2A4 -@23A 080 -@23B 743 -@23C AC4 -@23D C46 -@23E 2A4 -@23F 080 -@240 743 -@241 AC4 -@242 C45 -@243 2A4 -@244 080 -@245 743 -@246 AC4 -@247 C44 -@248 2A4 -@249 080 -@24A 743 -@24B AC4 -@24C C43 -@24D 2A4 -@24E 080 -@24F 743 -@250 AC4 -@251 C42 -@252 2A4 -@253 080 -@254 743 -@255 AC4 -@256 C41 -@257 2A4 -@258 080 -@259 743 -@25A AC4 -@25B C40 -@25C 2A4 -@25D 080 -@25E 743 -@25F AC4 -@260 C04 -@261 026 -@262 C10 -@263 024 -@264 5A4 -@265 5C4 -@266 C3F -@267 080 -@268 743 -@269 AC4 -@26A C3E -@26B 2A4 -@26C 080 -@26D 743 -@26E AC4 -@26F C3D -@270 2A4 -@271 080 -@272 743 -@273 AC4 -@274 C3C -@275 2A4 -@276 080 -@277 743 -@278 AC4 -@279 C3B -@27A 2A4 -@27B 080 -@27C 743 -@27D AC4 -@27E C3A -@27F 2A4 -@280 080 -@281 743 -@282 AC4 -@283 C39 -@284 2A4 -@285 080 -@286 743 -@287 AC4 -@288 C38 -@289 2A4 -@28A 080 -@28B 743 -@28C AC4 -@28D C37 -@28E 2A4 -@28F 080 -@290 743 -@291 AC4 -@292 C36 -@293 2A4 -@294 080 -@295 743 -@296 AC4 -@297 C35 -@298 2A4 -@299 080 -@29A 743 -@29B AC4 -@29C C34 -@29D 2A4 -@29E 080 -@29F 743 -@2A0 AC4 -@2A1 C33 -@2A2 2A4 -@2A3 080 -@2A4 743 -@2A5 AC4 -@2A6 C32 -@2A7 2A4 -@2A8 080 -@2A9 743 -@2AA AC4 -@2AB C31 -@2AC 2A4 -@2AD 080 -@2AE 743 -@2AF AC4 -@2B0 C30 -@2B1 2A4 -@2B2 080 -@2B3 743 -@2B4 AC4 -@2B5 000 -@2B6 000 -@2B7 000 -@2B8 000 -@2B9 C01 -@2BA 025 -@2BB 000 -@2BC 000 -@2BD 000 -@2BE 000 -@2BF ABF -@2C0 000 -@2C1 000 -@2C2 000 -@2C3 000 -@2C4 CFF -@2C5 025 -@2C6 000 -@2C7 000 -@2C8 000 -@2C9 000 -@2CA ACA -@2CB 000 -@2CC 000 -@2CD 000 -@2CE 000 Index: tags/alpha/scode/rf3.rom =================================================================== --- tags/alpha/scode/rf3.rom (revision 6) +++ tags/alpha/scode/rf3.rom (nonexistent) @@ -1,219 +0,0 @@ - -@000 040 -@001 024 -@002 025 -@003 026 -@004 027 -@005 005 -@006 006 -@007 007 -@008 C01 -@009 026 -@00A CFC -@00B 028 -@00C 2A8 -@00D 2A8 -@00E 2A8 -@00F 2A8 -@010 743 -@011 ACF -@012 CFC -@013 038 -@014 2B8 -@015 2B8 -@016 2B8 -@017 2B8 -@018 743 -@019 ACF -@01A C02 -@01B 026 -@01C C09 -@01D 024 -@01E CFC -@01F 020 -@020 2A0 -@021 2A0 -@022 2A0 -@023 2A0 -@024 743 -@025 ACF -@026 C19 -@027 024 -@028 CFC -@029 020 -@02A 2A0 -@02B 2A0 -@02C 2A0 -@02D 2A0 -@02E 743 -@02F ACF -@030 C03 -@031 026 -@032 C04 -@033 028 -@034 0E8 -@035 0E8 -@036 0E8 -@037 0E8 -@038 743 -@039 ACF -@03A C04 -@03B 030 -@03C 0F0 -@03D 0F0 -@03E 0F0 -@03F 0F0 -@040 743 -@041 ACF -@042 C04 -@043 026 -@044 C09 -@045 024 -@046 C04 -@047 020 -@048 0E0 -@049 0E0 -@04A 0E0 -@04B 0E0 -@04C 743 -@04D ACF -@04E C19 -@04F 024 -@050 C04 -@051 020 -@052 0E0 -@053 0E0 -@054 0E0 -@055 0E0 -@056 743 -@057 ACF -@058 C05 -@059 026 -@05A CFC -@05B 02C -@05C 3EC -@05D 3EC -@05E 3EC -@05F 3EC -@060 ACF -@061 CFC -@062 038 -@063 3F8 -@064 3F8 -@065 3F8 -@066 3F8 -@067 ACF -@068 C06 -@069 026 -@06A C09 -@06B 024 -@06C CFC -@06D 020 -@06E 3E0 -@06F 3E0 -@070 3E0 -@071 3E0 -@072 ACF -@073 C19 -@074 024 -@075 CFC -@076 020 -@077 3E0 -@078 3E0 -@079 3E0 -@07A 3E0 -@07B ACF -@07C C07 -@07D 026 -@07E C04 -@07F 028 -@080 2E8 -@081 2E8 -@082 2E8 -@083 2E8 -@084 ACF -@085 C04 -@086 030 -@087 2F0 -@088 2F0 -@089 2F0 -@08A 2F0 -@08B ACF -@08C C08 -@08D 026 -@08E C09 -@08F 024 -@090 C04 -@091 020 -@092 2E0 -@093 2E0 -@094 2E0 -@095 2E0 -@096 ACF -@097 C19 -@098 024 -@099 C04 -@09A 020 -@09B 2E0 -@09C 2E0 -@09D 2E0 -@09E 2E0 -@09F ACF -@0A0 C09 -@0A1 026 -@0A2 CFC -@0A3 024 -@0A4 2A4 -@0A5 2A4 -@0A6 2A4 -@0A7 2A4 -@0A8 743 -@0A9 ACF -@0AA C04 -@0AB 024 -@0AC C7F -@0AD 0E4 -@0AE 0E4 -@0AF 0E4 -@0B0 0E4 -@0B1 164 -@0B2 743 -@0B3 ACF -@0B4 C0A -@0B5 026 -@0B6 CFC -@0B7 023 -@0B8 C18 -@0B9 2A3 -@0BA 2A3 -@0BB 2A3 -@0BC 2A3 -@0BD 083 -@0BE 743 -@0BF ACF -@0C0 000 -@0C1 000 -@0C2 000 -@0C3 000 -@0C4 C01 -@0C5 025 -@0C6 000 -@0C7 000 -@0C8 000 -@0C9 000 -@0CA ACA -@0CB 000 -@0CC 000 -@0CD 000 -@0CE 000 -@0CF CFF -@0D0 025 -@0D1 000 -@0D2 000 -@0D3 000 -@0D4 000 -@0D5 AD5 -@0D6 000 -@0D7 000 -@0D8 000 -@0D9 000 Index: tags/alpha/scode/sanity1.asm =================================================================== --- tags/alpha/scode/sanity1.asm (revision 6) +++ tags/alpha/scode/sanity1.asm (nonexistent) @@ -1,250 +0,0 @@ -;///////////////////////////////////////////////////////////////////// -;//// //// -;//// Mini-RISC-1 //// -;//// Compliance Test 1 //// -;//// Tests Ports //// -;//// //// -;//// Author: Rudolf Usselmann //// -;//// russelmann@hotmail.com //// -;//// //// -;///////////////////////////////////////////////////////////////////// -;//// //// -;//// Copyright (C) 2000 Rudolf Usselmann //// -;//// russelmann@hotmail.com //// -;//// //// -;//// This source file may be used and distributed without //// -;//// restriction provided that this copyright statement is not //// -;//// removed from the file and that any derivative work contains //// -;//// the original copyright notice and the associated disclaimer.//// -;//// //// -;//// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY //// -;//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT //// -;//// LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND //// -;//// FITNESS FOR A PARTICULAR PURPOSE. //// -;//// //// -;///////////////////////////////////////////////////////////////////// - - list p=16c57 - #include p16c5x.inc - - -main ; Main code entry - ; Port IO Test - ; All ports have a Pull up resistor - - ; Tristate all ports - clrw - movwf PORTA - movwf PORTB - movwf PORTC - xorlw 0xff - tris PORTA - tris PORTB - tris PORTC - - ; Now check that porta is 0xff - btfss PORTA,0 - goto lerr - btfss PORTA,1 - goto lerr - btfss PORTA,2 - goto lerr - btfss PORTA,3 - goto lerr - btfss PORTA,4 - goto lerr - btfss PORTA,5 - goto lerr - btfss PORTA,6 - goto lerr - btfss PORTA,7 - goto lerr - - - ; Now check that portb is 0xff - btfss PORTB,0 - goto lerr - btfss PORTB,1 - goto lerr - btfss PORTB,2 - goto lerr - btfss PORTB,3 - goto lerr - btfss PORTB,4 - goto lerr - btfss PORTB,5 - goto lerr - btfss PORTB,6 - goto lerr - btfss PORTB,7 - goto lerr - - ; Now check that portc is 0xff - btfss PORTC,0 - goto lerr - btfss PORTC,1 - goto lerr - btfss PORTC,2 - goto lerr - btfss PORTC,3 - goto lerr - btfss PORTC,4 - goto lerr - btfss PORTC,5 - goto lerr - btfss PORTA,6 - goto lerr - btfss PORTC,7 - goto lerr - - - - ; Enable all ports - clrw - tris PORTA - tris PORTB - tris PORTC - - ; Drive them all 0xaa - clrw - xorlw 0xaa - movwf PORTA - movwf PORTB - movwf PORTC - - ; Now check that porta is 0xaa - btfsc PORTA,0 - goto lerr - btfss PORTA,1 - goto lerr - btfsc PORTA,2 - goto lerr - btfss PORTA,3 - goto lerr - btfsc PORTA,4 - goto lerr - btfss PORTA,5 - goto lerr - btfsc PORTA,6 - goto lerr - btfss PORTA,7 - goto lerr - - ; Now check that portb is 0xaa - btfsc PORTB,0 - goto lerr - btfss PORTB,1 - goto lerr - btfsc PORTB,2 - goto lerr - btfss PORTB,3 - goto lerr - btfsc PORTB,4 - goto lerr - btfss PORTB,5 - goto lerr - btfsc PORTB,6 - goto lerr - btfss PORTB,7 - goto lerr - - ; Now check that portc is 0xaa - btfsc PORTC,0 - goto lerr - btfss PORTC,1 - goto lerr - btfsc PORTC,2 - goto lerr - btfss PORTC,3 - goto lerr - btfsc PORTC,4 - goto lerr - btfss PORTC,5 - goto lerr - btfsc PORTC,6 - goto lerr - btfss PORTC,7 - goto lerr - - ; Drive them all 0x55 - clrw - xorlw 0x55 - movwf PORTA - movwf PORTB - movwf PORTC - - ; Now check that porta is 0x55 - btfss PORTA,0 - goto lerr - btfsc PORTA,1 - goto lerr - btfss PORTA,2 - goto lerr - btfsc PORTA,3 - goto lerr - btfss PORTA,4 - goto lerr - btfsc PORTA,5 - goto lerr - btfss PORTA,6 - goto lerr - btfsc PORTA,7 - goto lerr - - ; Now check that portb is 0x55 - btfss PORTB,0 - goto lerr - btfsc PORTB,1 - goto lerr - btfss PORTB,2 - goto lerr - btfsc PORTB,3 - goto lerr - btfss PORTB,4 - goto lerr - btfsc PORTB,5 - goto lerr - btfss PORTB,6 - goto lerr - btfsc PORTB,7 - goto lerr - - ; Now check that portc is 0x55 - btfss PORTC,0 - goto lerr - btfsc PORTC,1 - goto lerr - btfss PORTC,2 - goto lerr - btfsc PORTC,3 - goto lerr - btfss PORTC,4 - goto lerr - btfsc PORTC,5 - goto lerr - btfss PORTC,6 - goto lerr - btfsc PORTC,7 - goto lerr - - nop - nop - nop - nop - -good ; Loop in good on success - goto good - nop - nop - nop - nop - -lerr ; Loop in lerr on failure - goto lerr - nop - nop - nop - nop - - END - Index: tags/alpha/scode/rf1.asm =================================================================== --- tags/alpha/scode/rf1.asm (revision 6) +++ tags/alpha/scode/rf1.asm (nonexistent) @@ -1,694 +0,0 @@ -;///////////////////////////////////////////////////////////////////// -;//// //// -;//// Mini-RISC-1 //// -;//// Register File Test 1 //// -;//// Tests Register File //// -;//// //// -;//// Author: Rudolf Usselmann //// -;//// russelmann@hotmail.com //// -;//// //// -;///////////////////////////////////////////////////////////////////// -;//// //// -;//// Copyright (C) 2000 Rudolf Usselmann //// -;//// russelmann@hotmail.com //// -;//// //// -;//// This source file may be used and distributed without //// -;//// restriction provided that this copyright statement is not //// -;//// removed from the file and that any derivative work contains //// -;//// the original copyright notice and the associated disclaimer.//// -;//// //// -;//// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY //// -;//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT //// -;//// LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND //// -;//// FITNESS FOR A PARTICULAR PURPOSE. //// -;//// //// -;///////////////////////////////////////////////////////////////////// - - list p=16c57 - #include p16c5x.inc - -; global Registers -r0 equ 0x8 -r1 equ 0x9 -r2 equ 0xa -r3 equ 0xb -r4 equ 0xc -r5 equ 0xd -r6 equ 0xe -r7 equ 0xf - -; banked Registers -br0 equ 0x10 -br1 equ 0x11 -br2 equ 0x12 -br3 equ 0x13 -br4 equ 0x14 -br5 equ 0x15 -br6 equ 0x16 -br7 equ 0x17 -br8 equ 0x18 -br9 equ 0x19 -br10 equ 0x1a -br11 equ 0x1b -br12 equ 0x1c -br13 equ 0x1d -br14 equ 0x1e -br15 equ 0x1f - - -; PORTB Indicates Test Number -; PORTA Indicates Status: 0 - Running; 1 - done OK; ff - stoped on error - -main ; Main code entry - ; Port IO Test - ; All ports have a Pull up resistor - - ; SETUP all ports - clrw - movwf FSR - movwf PORTA - movwf PORTB - movwf PORTC - tris PORTA - tris PORTB - tris PORTC - - bsf STATUS,5 - - ; --------------------------------------- - ; ---- Test the entire register file ---- - ; --------------------------------------- - - movlw 0x81 - movwf r0 - movlw 0x82 - movwf r1 - movlw 0x83 - movwf r2 - movlw 0x84 - movwf r3 - movlw 0x85 - movwf r4 - movlw 0x86 - movwf r5 - movlw 0x87 - movwf r6 - movlw 0x88 - movwf r7 - - - movlw 0x90 - movwf br0 - movlw 0x91 - movwf br1 - movlw 0x92 - movwf br2 - movlw 0x93 - movwf br3 - movlw 0x94 - movwf br4 - movlw 0x95 - movwf br5 - movlw 0x96 - movwf br6 - movlw 0x97 - movwf br7 - movlw 0x98 - movwf br8 - movlw 0x99 - movwf br9 - movlw 0x9a - movwf br10 - movlw 0x9b - movwf br11 - movlw 0x9c - movwf br12 - movlw 0x9d - movwf br13 - movlw 0x9e - movwf br14 - movlw 0x9f - movwf br15 - - bsf FSR,5 ; Select Register Bank 01 - - movlw 0xa0 - movwf br0 - movlw 0xa1 - movwf br1 - movlw 0xa2 - movwf br2 - movlw 0xa3 - movwf br3 - movlw 0xa4 - movwf br4 - movlw 0xa5 - movwf br5 - movlw 0xa6 - movwf br6 - movlw 0xa7 - movwf br7 - movlw 0xa8 - movwf br8 - movlw 0xa9 - movwf br9 - movlw 0xaa - movwf br10 - movlw 0xab - movwf br11 - movlw 0xac - movwf br12 - movlw 0xad - movwf br13 - movlw 0xae - movwf br14 - movlw 0xaf - movwf br15 - - bcf FSR,5 ; Select Register Bank 10 - bsf FSR,6 - - movlw 0xb0 - movwf br0 - movlw 0xb1 - movwf br1 - movlw 0xb2 - movwf br2 - movlw 0xb3 - movwf br3 - movlw 0xb4 - movwf br4 - movlw 0xb5 - movwf br5 - movlw 0xb6 - movwf br6 - movlw 0xb7 - movwf br7 - movlw 0xb8 - movwf br8 - movlw 0xb9 - movwf br9 - movlw 0xba - movwf br10 - movlw 0xbb - movwf br11 - movlw 0xbc - movwf br12 - movlw 0xbd - movwf br13 - movlw 0xbe - movwf br14 - movlw 0xbf - movwf br15 - - bsf FSR,5 ; Select Register Bank 11 - bsf FSR,6 - - movlw 0xc0 - movwf br0 - movlw 0xc1 - movwf br1 - movlw 0xc2 - movwf br2 - movlw 0xc3 - movwf br3 - movlw 0xc4 - movwf br4 - movlw 0xc5 - movwf br5 - movlw 0xc6 - movwf br6 - movlw 0xc7 - movwf br7 - movlw 0xc8 - movwf br8 - movlw 0xc9 - movwf br9 - movlw 0xca - movwf br10 - movlw 0xcb - movwf br11 - movlw 0xcc - movwf br12 - movlw 0xcd - movwf br13 - movlw 0xce - movwf br14 - movlw 0xcf - movwf br15 - - ; Register File TEST 1 - movlw 0x01 - movwf PORTB ; Set Test Number - - clrw - movwf FSR - - movlw 0x81 - subwf r0,W - btfss STATUS,Z - goto lerr - movlw 0x82 - subwf r1,W - btfss STATUS,Z - goto lerr - movlw 0x83 - subwf r2,W - btfss STATUS,Z - goto lerr - movlw 0x84 - subwf r3,W - btfss STATUS,Z - goto lerr - movlw 0x85 - subwf r4,W - btfss STATUS,Z - goto lerr - movlw 0x86 - subwf r5,W - btfss STATUS,Z - goto lerr - movlw 0x87 - subwf r6,W - btfss STATUS,Z - goto lerr - movlw 0x88 - subwf r7,W - btfss STATUS,Z - goto lerr - - movlw 0x90 - subwf br0,W - btfss STATUS,Z - goto lerr - movlw 0x91 - subwf br1,W - btfss STATUS,Z - goto lerr - movlw 0x92 - subwf br2,W - btfss STATUS,Z - goto lerr - movlw 0x93 - subwf br3,W - btfss STATUS,Z - goto lerr - movlw 0x94 - subwf br4,W - btfss STATUS,Z - goto lerr - movlw 0x95 - subwf br5,W - btfss STATUS,Z - goto lerr - movlw 0x96 - subwf br6,W - btfss STATUS,Z - goto lerr - movlw 0x97 - subwf br7,W - btfss STATUS,Z - goto lerr - movlw 0x98 - subwf br8,W - btfss STATUS,Z - goto lerr - movlw 0x99 - subwf br9,W - btfss STATUS,Z - goto lerr - movlw 0x9a - subwf br10,W - btfss STATUS,Z - goto lerr - movlw 0x9b - subwf br11,W - btfss STATUS,Z - goto lerr - movlw 0x9c - subwf br12,W - btfss STATUS,Z - goto lerr - movlw 0x9d - subwf br13,W - btfss STATUS,Z - goto lerr - movlw 0x9e - subwf br14,W - btfss STATUS,Z - goto lerr - movlw 0x9f - subwf br15,W - btfss STATUS,Z - goto lerr - - ; Register File TEST 2 - movlw 0x02 - movwf PORTB ; Set Test Number - - bsf FSR,5 ; Select Register Bank 01 - - movlw 0x81 - subwf r0,W - btfss STATUS,Z - goto lerr - movlw 0x82 - subwf r1,W - btfss STATUS,Z - goto lerr - movlw 0x83 - subwf r2,W - btfss STATUS,Z - goto lerr - movlw 0x84 - subwf r3,W - btfss STATUS,Z - goto lerr - movlw 0x85 - subwf r4,W - btfss STATUS,Z - goto lerr - movlw 0x86 - subwf r5,W - btfss STATUS,Z - goto lerr - movlw 0x87 - subwf r6,W - btfss STATUS,Z - goto lerr - movlw 0x88 - subwf r7,W - btfss STATUS,Z - goto lerr - - movlw 0xa0 - subwf br0,W - btfss STATUS,Z - goto lerr - movlw 0xa1 - subwf br1,W - btfss STATUS,Z - goto lerr - movlw 0xa2 - subwf br2,W - btfss STATUS,Z - goto lerr - movlw 0xa3 - subwf br3,W - btfss STATUS,Z - goto lerr - movlw 0xa4 - subwf br4,W - btfss STATUS,Z - goto lerr - movlw 0xa5 - subwf br5,W - btfss STATUS,Z - goto lerr - movlw 0xa6 - subwf br6,W - btfss STATUS,Z - goto lerr - movlw 0xa7 - subwf br7,W - btfss STATUS,Z - goto lerr - movlw 0xa8 - subwf br8,W - btfss STATUS,Z - goto lerr - movlw 0xa9 - subwf br9,W - btfss STATUS,Z - goto lerr - movlw 0xaa - subwf br10,W - btfss STATUS,Z - goto lerr - movlw 0xab - subwf br11,W - btfss STATUS,Z - goto lerr - movlw 0xac - subwf br12,W - btfss STATUS,Z - goto lerr - movlw 0xad - subwf br13,W - btfss STATUS,Z - goto lerr - movlw 0xae - subwf br14,W - btfss STATUS,Z - goto lerr - movlw 0xaf - subwf br15,W - btfss STATUS,Z - goto lerr - - ; Register File TEST 3 - movlw 0x03 - movwf PORTB ; Set Test Number - - bcf FSR,5 ; Select Register Bank 10 - bsf FSR,6 - - movlw 0x81 - subwf r0,W - btfss STATUS,Z - goto lerr - movlw 0x82 - subwf r1,W - btfss STATUS,Z - goto lerr - movlw 0x83 - subwf r2,W - btfss STATUS,Z - goto lerr - movlw 0x84 - subwf r3,W - btfss STATUS,Z - goto lerr - movlw 0x85 - subwf r4,W - btfss STATUS,Z - goto lerr - movlw 0x86 - subwf r5,W - btfss STATUS,Z - goto lerr - movlw 0x87 - subwf r6,W - btfss STATUS,Z - goto lerr - movlw 0x88 - subwf r7,W - btfss STATUS,Z - goto lerr - - movlw 0xb0 - subwf br0,W - btfss STATUS,Z - goto lerr - movlw 0xb1 - subwf br1,W - btfss STATUS,Z - goto lerr - movlw 0xb2 - subwf br2,W - btfss STATUS,Z - goto lerr - movlw 0xb3 - subwf br3,W - btfss STATUS,Z - goto lerr - movlw 0xb4 - subwf br4,W - btfss STATUS,Z - goto lerr - movlw 0xb5 - subwf br5,W - btfss STATUS,Z - goto lerr - movlw 0xb6 - subwf br6,W - btfss STATUS,Z - goto lerr - movlw 0xb7 - subwf br7,W - btfss STATUS,Z - goto lerr - movlw 0xb8 - subwf br8,W - btfss STATUS,Z - goto lerr - movlw 0xb9 - subwf br9,W - btfss STATUS,Z - goto lerr - movlw 0xba - subwf br10,W - btfss STATUS,Z - goto lerr - movlw 0xbb - subwf br11,W - btfss STATUS,Z - goto lerr - movlw 0xbc - subwf br12,W - btfss STATUS,Z - goto lerr - movlw 0xbd - subwf br13,W - btfss STATUS,Z - goto lerr - movlw 0xbe - subwf br14,W - btfss STATUS,Z - goto lerr - movlw 0xbf - subwf br15,W - btfss STATUS,Z - goto lerr - - - ; Register File TEST 4 - movlw 0x04 - movwf PORTB ; Set Test Number - - bsf FSR,5 ; Select Register Bank 11 - bsf FSR,6 - - movlw 0x81 - subwf r0,W - btfss STATUS,Z - goto lerr - movlw 0x82 - subwf r1,W - btfss STATUS,Z - goto lerr - movlw 0x83 - subwf r2,W - btfss STATUS,Z - goto lerr - movlw 0x84 - subwf r3,W - btfss STATUS,Z - goto lerr - movlw 0x85 - subwf r4,W - btfss STATUS,Z - goto lerr - movlw 0x86 - subwf r5,W - btfss STATUS,Z - goto lerr - movlw 0x87 - subwf r6,W - btfss STATUS,Z - goto lerr - movlw 0x88 - subwf r7,W - btfss STATUS,Z - goto lerr - - movlw 0xc0 - subwf br0,W - btfss STATUS,Z - goto lerr - movlw 0xc1 - subwf br1,W - btfss STATUS,Z - goto lerr - movlw 0xc2 - subwf br2,W - btfss STATUS,Z - goto lerr - movlw 0xc3 - subwf br3,W - btfss STATUS,Z - goto lerr - movlw 0xc4 - subwf br4,W - btfss STATUS,Z - goto lerr - movlw 0xc5 - subwf br5,W - btfss STATUS,Z - goto lerr - movlw 0xc6 - subwf br6,W - btfss STATUS,Z - goto lerr - movlw 0xc7 - subwf br7,W - btfss STATUS,Z - goto lerr - movlw 0xc8 - subwf br8,W - btfss STATUS,Z - goto lerr - movlw 0xc9 - subwf br9,W - btfss STATUS,Z - goto lerr - movlw 0xca - subwf br10,W - btfss STATUS,Z - goto lerr - movlw 0xcb - subwf br11,W - btfss STATUS,Z - goto lerr - movlw 0xcc - subwf br12,W - btfss STATUS,Z - goto lerr - movlw 0xcd - subwf br13,W - btfss STATUS,Z - goto lerr - movlw 0xce - subwf br14,W - btfss STATUS,Z - goto lerr - movlw 0xcf - subwf br15,W - btfss STATUS,Z - goto lerr - - - nop - nop - nop - nop - movlw 0x01 - movwf PORTA - nop - nop - nop - nop -good ; Loop in good on success - goto good - nop - nop - nop - nop - -lerr - movlw 0xff - movwf PORTA - - nop - nop - nop - nop -lerr_loop ; Loop in lerr on failure - goto lerr_loop - nop - nop - nop - nop - - END - Index: tags/alpha/scode/sanity2.asm =================================================================== --- tags/alpha/scode/sanity2.asm (revision 6) +++ tags/alpha/scode/sanity2.asm (nonexistent) @@ -1,454 +0,0 @@ -;///////////////////////////////////////////////////////////////////// -;//// //// -;//// Mini-RISC-1 //// -;//// Compliance Test 2 //// -;//// Tests PLC register Rd/Wr //// -;//// //// -;//// Author: Rudolf Usselmann //// -;//// russelmann@hotmail.com //// -;//// //// -;///////////////////////////////////////////////////////////////////// -;//// //// -;//// Copyright (C) 2000 Rudolf Usselmann //// -;//// russelmann@hotmail.com //// -;//// //// -;//// This source file may be used and distributed without //// -;//// restriction provided that this copyright statement is not //// -;//// removed from the file and that any derivative work contains //// -;//// the original copyright notice and the associated disclaimer.//// -;//// //// -;//// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY //// -;//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT //// -;//// LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND //// -;//// FITNESS FOR A PARTICULAR PURPOSE. //// -;//// //// -;///////////////////////////////////////////////////////////////////// - - list p=16c57 - #include p16c5x.inc - -; global Registers -r0 equ 0x8 -r1 equ 0x9 -r2 equ 0xa -r3 equ 0xb -r4 equ 0xc -r5 equ 0xd -r6 equ 0xe -r7 equ 0xf - -; banked Registers -br0 equ 0x10 -br1 equ 0x11 -br2 equ 0x12 -br3 equ 0x13 -br4 equ 0x14 -br5 equ 0x15 -br6 equ 0x16 -br7 equ 0x17 -br8 equ 0x18 -br9 equ 0x19 -br10 equ 0x1a -br11 equ 0x1b -br12 equ 0x1c -br13 equ 0x1d -br14 equ 0x1e -br15 equ 0x1f - - -; PORTB Indicates Test Number -; PORTA Indicates Status: 0 - Running; 1 - done OK; ff - stoped on error - -main ; Main code entry - ; Port IO Test - ; All ports have a Pull up resistor - - ; SETUP all ports - clrw - movwf FSR - movwf PORTA - movwf PORTB - movwf PORTC - tris PORTA - tris PORTB - tris PORTC - - ; ------------------------------- - ; ---- Test the PLC register ---- - ; ------------------------------- - - ; PLC read test 1 TEST 0 - - movlw pclrd1 - movwf r0 - movf PCL,W -pclrd1 subwf r0,W - btfss STATUS,Z - goto lerr - - ; PLC read test 2 TEST 1 - movlw 0x01 - movwf PORTB ; Set Test Number - - movlw pclrd2 - movwf r3 - movf PCL,W -pclrd2 subwf r3,W - btfss STATUS,Z - goto lerr - - ; PLC write test 2 TEST 2 - movlw 0x02 - movwf PORTB ; Set Test Number - - movlw pclwr1 - movwf PCL - - goto lerr - goto lerr - goto lerr -pclwr1 goto pcl1 - goto lerr - goto lerr - goto lerr - -pcl1 - ; PLC write test 2 TEST 3 - movlw 0x03 - movwf PORTB ; Set Test Number - - movlw pclwr2 - movwf PCL - - goto lerr - goto lerr - goto lerr -pclwr2 goto pcl2 - goto lerr - goto lerr - goto lerr - -pcl2 ; Test other instructions that modify PC - ; This are ADDWF PC, BSF PC,X and BCF PC,X - ; (movwf pc already tested above) - - ; PLC write test 3 TEST 4 - ; test addwf PC - movlw 0x04 - movwf PORTB ; Set Test Number - - movlw pcl3b - movwf r0 - movlw pcl3a - subwf r0,W -pcl3a addwf PCL,1 - - goto lerr - goto lerr -pcl3b goto lerr - goto pcl3c - goto lerr - goto lerr - goto lerr -pcl3c - - ; PLC write test 4 TEST 5 - ; test addwf PC - movlw 0x05 - movwf PORTB ; Set Test Number - - movlw pcl4b - movwf br8 - movlw pcl4a - subwf br8,W -pcl4a addwf PCL,1 - - goto lerr - goto lerr -pcl4b goto lerr - goto pcl4c - goto lerr - goto lerr - goto lerr -pcl4c - - ; PLC write test 5 TEST 6 - ; test bsf PC,N - movlw 0x06 - movwf PORTB ; Set Test N - -; allign memory - goto pcl50 - -pcl50 org 0x60 - - bsf PCL,1 ; 60 - goto lerr ; 61 - goto lerr ; 62 - goto pcl5a ; 63 - goto lerr ; 64 - goto lerr ; 65 - goto lerr ; 66 - goto lerr ; 67 - -pcl5a - - ; PLC write test 6 TEST 7 - ; test bsf PC,N - movlw 0x07 - movwf PORTB ; Set Test N - - bsf PCL,2 ; 6A - goto lerr ; 6B - goto lerr ; 6C - goto lerr ; 6D - goto lerr ; 6E - goto pcl6a ; 6F - goto lerr ; 70 - goto lerr ; 71 - -pcl6a - - ; PLC write test 7 TEST 8 - ; test bcf PC,N - movlw 0x08 - movwf PORTB ; Set Test N - - goto pcl7a ; 74 - goto lerr ; 75 - goto lerr ; 76 - goto lerr ; 77 - goto lerr ; 78 - goto pcl7b ; 79 - goto lerr ; 7a - goto lerr ; 7b - -pcl7a - bcf PCL,2 ; 7c - -pcl7b - - - ; Make sure goto works - movlw 0x09 ; TEST 9 - movwf PORTB ; Set Test Number - - - goto gt1 - nop - nop - nop - nop - movlw 0xff - movwf PORTA - nop - nop - nop - nop -gt1 - - ; Make sure call works - movlw 0x0a ; TEST 10 - movwf PORTB ; Set Test Number - - call cal1 - movwf r0 - movlw 0x55 - subwf r0,w - btfss STATUS,Z - goto lerr - - call cal2 - movwf r0 - movlw 0xaa - subwf r0,w - btfss STATUS,Z - goto lerr - - call cal3 - movwf r0 - movlw 0xc3 - subwf r0,w - btfss STATUS,Z - goto lerr - - call cal4 - movwf r0 - movlw 0x3c - subwf r0,w - btfss STATUS,Z - goto lerr - - goto next1 - -cal1 - retlw 0x55 - goto lerr - -cal2 - nop - retlw 0xaa - goto lerr - -cal3 - nop - nop - retlw 0xc3 - goto lerr - -cal4 - nop - nop - nop - retlw 0x3c - goto lerr - -table1 - addwf PCL,F - retlw 0xff - retlw 0xfe - retlw 0xfd - retlw 0xfc - retlw 0xfb - retlw 0xfa - retlw 0xf9 - retlw 0xf8 - retlw 0xf7 - retlw 0xf6 - retlw 0xf5 - goto lerr - goto lerr - goto lerr - goto lerr - goto lerr - goto lerr - -next1 - - - ; Make sure call works (2) - movlw 0x0b ; TEST 11 - movwf PORTB ; Set Test Number - - movlw 0x0 - movwf r0 - call table1 - comf r0,F - subwf r0,F - btfss STATUS,Z - goto lerr - - movlw 0x1 - movwf r0 - call table1 - comf r0,F - subwf r0,F - btfss STATUS,Z - goto lerr - - movlw 0x2 - movwf r0 - call table1 - comf r0,F - subwf r0,F - btfss STATUS,Z - goto lerr - - movlw 0x3 - movwf r0 - call table1 - comf r0,F - subwf r0,F - btfss STATUS,Z - goto lerr - - movlw 0x4 - movwf r0 - call table1 - comf r0,F - subwf r0,F - btfss STATUS,Z - goto lerr - - movlw 0x5 - movwf r0 - call table1 - comf r0,F - subwf r0,F - btfss STATUS,Z - goto lerr - - movlw 0x6 - movwf r0 - call table1 - comf r0,F - subwf r0,F - btfss STATUS,Z - goto lerr - - movlw 0x7 - movwf r0 - call table1 - comf r0,F - subwf r0,F - btfss STATUS,Z - goto lerr - - movlw 0x8 - movwf r0 - call table1 - comf r0,F - subwf r0,F - btfss STATUS,Z - goto lerr - - movlw 0x9 - movwf r0 - call table1 - comf r0,F - subwf r0,F - btfss STATUS,Z - goto lerr - - movlw 0xa - movwf r0 - call table1 - comf r0,F - subwf r0,F - btfss STATUS,Z - goto lerr - - nop - nop - nop - nop - movlw 0x01 - movwf PORTA - nop - nop - nop - nop -good ; Loop in good on success - goto good - nop - nop - nop - nop - -lerr - movlw 0xff - movwf PORTA - - nop - nop - nop - nop -lerr_loop ; Loop in lerr on failure - goto lerr_loop - nop - nop - nop - nop - - END - Index: tags/alpha/scode/rf2.asm =================================================================== --- tags/alpha/scode/rf2.asm (revision 6) +++ tags/alpha/scode/rf2.asm (nonexistent) @@ -1,827 +0,0 @@ -;///////////////////////////////////////////////////////////////////// -;//// //// -;//// Mini-RISC-1 //// -;//// Register File Test 2 //// -;//// Tests Register File //// -;//// //// -;//// Author: Rudolf Usselmann //// -;//// russelmann@hotmail.com //// -;//// //// -;///////////////////////////////////////////////////////////////////// -;//// //// -;//// Copyright (C) 2000 Rudolf Usselmann //// -;//// russelmann@hotmail.com //// -;//// //// -;//// This source file may be used and distributed without //// -;//// restriction provided that this copyright statement is not //// -;//// removed from the file and that any derivative work contains //// -;//// the original copyright notice and the associated disclaimer.//// -;//// //// -;//// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY //// -;//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT //// -;//// LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND //// -;//// FITNESS FOR A PARTICULAR PURPOSE. //// -;//// //// -;///////////////////////////////////////////////////////////////////// - - list p=16c57 - #include p16c5x.inc - -; global Registers -r0 equ 0x8 -r1 equ 0x9 -r2 equ 0xa -r3 equ 0xb -r4 equ 0xc -r5 equ 0xd -r6 equ 0xe -r7 equ 0xf - -; banked Registers -br0 equ 0x10 -br1 equ 0x11 -br2 equ 0x12 -br3 equ 0x13 -br4 equ 0x14 -br5 equ 0x15 -br6 equ 0x16 -br7 equ 0x17 -br8 equ 0x18 -br9 equ 0x19 -br10 equ 0x1a -br11 equ 0x1b -br12 equ 0x1c -br13 equ 0x1d -br14 equ 0x1e -br15 equ 0x1f - - -; PORTB Indicates Test Number -; PORTA Indicates Status: 0 - Running; 1 - done OK; ff - stoped on error - -main ; Main code entry - ; Port IO Test - ; All ports have a Pull up resistor - - ; SETUP all ports - clrw - movwf FSR - movwf PORTA - movwf PORTB - movwf PORTC - tris PORTA - tris PORTB - tris PORTC - - bsf STATUS,5 - - ; --------------------------------------- - ; ---- Test the entire register file ---- - ; --------------------------------------- - - movlw 0x81 - movwf r0 - movlw 0x82 - movwf r1 - movlw 0x83 - movwf r2 - movlw 0x84 - movwf r3 - movlw 0x85 - movwf r4 - movlw 0x86 - movwf r5 - movlw 0x87 - movwf r6 - movlw 0x88 - movwf r7 - - - movlw 0x90 - movwf br0 - movlw 0x91 - movwf br1 - movlw 0x92 - movwf br2 - movlw 0x93 - movwf br3 - movlw 0x94 - movwf br4 - movlw 0x95 - movwf br5 - movlw 0x96 - movwf br6 - movlw 0x97 - movwf br7 - movlw 0x98 - movwf br8 - movlw 0x99 - movwf br9 - movlw 0x9a - movwf br10 - movlw 0x9b - movwf br11 - movlw 0x9c - movwf br12 - movlw 0x9d - movwf br13 - movlw 0x9e - movwf br14 - movlw 0x9f - movwf br15 - - bsf FSR,5 ; Select Register Bank 01 - - movlw 0xa0 - movwf br0 - movlw 0xa1 - movwf br1 - movlw 0xa2 - movwf br2 - movlw 0xa3 - movwf br3 - movlw 0xa4 - movwf br4 - movlw 0xa5 - movwf br5 - movlw 0xa6 - movwf br6 - movlw 0xa7 - movwf br7 - movlw 0xa8 - movwf br8 - movlw 0xa9 - movwf br9 - movlw 0xaa - movwf br10 - movlw 0xab - movwf br11 - movlw 0xac - movwf br12 - movlw 0xad - movwf br13 - movlw 0xae - movwf br14 - movlw 0xaf - movwf br15 - - bcf FSR,5 ; Select Register Bank 10 - bsf FSR,6 - - movlw 0xb0 - movwf br0 - movlw 0xb1 - movwf br1 - movlw 0xb2 - movwf br2 - movlw 0xb3 - movwf br3 - movlw 0xb4 - movwf br4 - movlw 0xb5 - movwf br5 - movlw 0xb6 - movwf br6 - movlw 0xb7 - movwf br7 - movlw 0xb8 - movwf br8 - movlw 0xb9 - movwf br9 - movlw 0xba - movwf br10 - movlw 0xbb - movwf br11 - movlw 0xbc - movwf br12 - movlw 0xbd - movwf br13 - movlw 0xbe - movwf br14 - movlw 0xbf - movwf br15 - - bsf FSR,5 ; Select Register Bank 11 - bsf FSR,6 - - movlw 0xc0 - movwf br0 - movlw 0xc1 - movwf br1 - movlw 0xc2 - movwf br2 - movlw 0xc3 - movwf br3 - movlw 0xc4 - movwf br4 - movlw 0xc5 - movwf br5 - movlw 0xc6 - movwf br6 - movlw 0xc7 - movwf br7 - movlw 0xc8 - movwf br8 - movlw 0xc9 - movwf br9 - movlw 0xca - movwf br10 - movlw 0xcb - movwf br11 - movlw 0xcc - movwf br12 - movlw 0xcd - movwf br13 - movlw 0xce - movwf br14 - movlw 0xcf - movwf br15 - - movlw r0 - movwf FSR - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - - - movlw br0 - movwf FSR - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - - movlw br0 - movwf FSR - bsf FSR,5 - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - - movlw br0 - movwf FSR - bsf FSR,6 - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - - movlw br0 - movwf FSR - bsf FSR,5 - bsf FSR,6 - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - - ; Register File TEST 1 - movlw 0x01 - movwf PORTB ; Set Test Number - - movlw r0 - movwf FSR - movlw 0x7e - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x7d - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x7c - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x7b - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x7a - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x79 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x78 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x77 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - - movlw br0 - movwf FSR - movlw 0x6f - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x6e - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x6d - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x6c - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x6b - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x6a - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x69 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x68 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x67 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x66 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x65 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x64 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x63 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x62 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x61 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x60 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - - ; Register File TEST 2 - movlw 0x02 - movwf PORTB ; Set Test Number - - movlw br0 - movwf FSR - bsf FSR,5 - movlw 0x5f - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x5e - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x5d - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x5c - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x5b - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x5a - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x59 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x58 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x57 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x56 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x55 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x54 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x53 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x52 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x51 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x50 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - - ; Register File TEST 3 - movlw 0x03 - movwf PORTB ; Set Test Number - - movlw br0 - movwf FSR - bsf FSR,6 - movlw 0x4f - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x4e - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x4d - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x4c - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x4b - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x4a - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x49 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x48 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x47 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x46 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x45 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x44 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x43 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x42 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x41 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x40 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - - ; Register File TEST 4 - movlw 0x04 - movwf PORTB ; Set Test Number - - movlw br0 - movwf FSR - bsf FSR,5 - bsf FSR,6 - movlw 0x3f - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x3e - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x3d - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x3c - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x3b - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x3a - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x39 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x38 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x37 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x36 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x35 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x34 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x33 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x32 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x31 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x30 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - - nop - nop - nop - nop - movlw 0x01 - movwf PORTA - nop - nop - nop - nop -good ; Loop in good on success - goto good - nop - nop - nop - nop - -lerr - movlw 0xff - movwf PORTA - - nop - nop - nop - nop -lerr_loop ; Loop in lerr on failure - goto lerr_loop - nop - nop - nop - nop - - END - Index: tags/alpha/scode/rf3.asm =================================================================== --- tags/alpha/scode/rf3.asm (revision 6) +++ tags/alpha/scode/rf3.asm (nonexistent) @@ -1,338 +0,0 @@ -;///////////////////////////////////////////////////////////////////// -;//// //// -;//// Mini-RISC-1 //// -;//// Register File Test 3 //// -;//// Tests Register File //// -;//// //// -;//// Author: Rudolf Usselmann //// -;//// russelmann@hotmail.com //// -;//// //// -;///////////////////////////////////////////////////////////////////// -;//// //// -;//// Copyright (C) 2000 Rudolf Usselmann //// -;//// russelmann@hotmail.com //// -;//// //// -;//// This source file may be used and distributed without //// -;//// restriction provided that this copyright statement is not //// -;//// removed from the file and that any derivative work contains //// -;//// the original copyright notice and the associated disclaimer.//// -;//// //// -;//// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY //// -;//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT //// -;//// LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND //// -;//// FITNESS FOR A PARTICULAR PURPOSE. //// -;//// //// -;///////////////////////////////////////////////////////////////////// - - list p=16c57 - #include p16c5x.inc - -; global Registers -r0 equ 0x8 -r1 equ 0x9 -r2 equ 0xa -r3 equ 0xb -r4 equ 0xc -r5 equ 0xd -r6 equ 0xe -r7 equ 0xf - -; banked Registers -br0 equ 0x10 -br1 equ 0x11 -br2 equ 0x12 -br3 equ 0x13 -br4 equ 0x14 -br5 equ 0x15 -br6 equ 0x16 -br7 equ 0x17 -br8 equ 0x18 -br9 equ 0x19 -br10 equ 0x1a -br11 equ 0x1b -br12 equ 0x1c -br13 equ 0x1d -br14 equ 0x1e -br15 equ 0x1f - - -; PORTB Indicates Test Number -; PORTA Indicates Status: 0 - Running; 1 - done OK; ff - stoped on error - -main ; Main code entry - ; Port IO Test - ; All ports have a Pull up resistor - - ; SETUP all ports - clrw - movwf FSR - movwf PORTA - movwf PORTB - movwf PORTC - tris PORTA - tris PORTB - tris PORTC - - ; --------------------------------------- - ; ---- Test RMW on Register fil ---- - ; --------------------------------------- - - movlw 0x01 ; TEST 1 - movwf PORTB ; Set Test Number - - movlw 0xfc - movwf r0 - incf r0,F - incf r0,F - incf r0,F - incf r0,F - btfss STATUS,Z - goto lerr - - movlw 0xfc - movwf br8 - incf br8,F - incf br8,F - incf br8,F - incf br8,F - btfss STATUS,Z - goto lerr - - movlw 0x02 ; TEST 2 - movwf PORTB ; Set Test Number - - movlw r1 - movwf FSR - movlw 0xfc - movwf INDF - incf INDF,F - incf INDF,F - incf INDF,F - incf INDF,F - btfss STATUS,Z - goto lerr - - movlw br9 - movwf FSR - movlw 0xfc - movwf INDF - incf INDF,F - incf INDF,F - incf INDF,F - incf INDF,F - btfss STATUS,Z - goto lerr - - - - movlw 0x03 ; TEST 3 - movwf PORTB ; Set Test Number - - movlw 0x04 - movwf r0 - decf r0,F - decf r0,F - decf r0,F - decf r0,F - btfss STATUS,Z - goto lerr - - - movlw 0x04 - movwf br0 - decf br0,F - decf br0,F - decf br0,F - decf br0,F - btfss STATUS,Z - goto lerr - - - movlw 0x04 ; TEST 4 - movwf PORTB ; Set Test Number - - movlw r1 - movwf FSR - movlw 0x04 - movwf INDF - decf INDF,F - decf INDF,F - decf INDF,F - decf INDF,F - btfss STATUS,Z - goto lerr - - movlw br9 - movwf FSR - movlw 0x04 - movwf INDF - decf INDF,F - decf INDF,F - decf INDF,F - decf INDF,F - btfss STATUS,Z - goto lerr - - - movlw 0x05 ; TEST 5 - movwf PORTB ; Set Test Number - - movlw 0xfc - movwf r4 - incfsz r4,F - incfsz r4,F - incfsz r4,F - incfsz r4,F - goto lerr - - movlw 0xfc - movwf br8 - incfsz br8,F - incfsz br8,F - incfsz br8,F - incfsz br8,F - goto lerr - - - movlw 0x06 ; TEST 6 - movwf PORTB ; Set Test Number - - movlw r1 - movwf FSR - movlw 0xfc - movwf INDF - incfsz INDF,F - incfsz INDF,F - incfsz INDF,F - incfsz INDF,F - goto lerr - - movlw br9 - movwf FSR - movlw 0xfc - movwf INDF - incfsz INDF,F - incfsz INDF,F - incfsz INDF,F - incfsz INDF,F - goto lerr - - movlw 0x07 ; TEST 7 - movwf PORTB ; Set Test Number - - movlw 0x04 - movwf r0 - decfsz r0,F - decfsz r0,F - decfsz r0,F - decfsz r0,F - goto lerr - - - movlw 0x04 - movwf br0 - decfsz br0,F - decfsz br0,F - decfsz br0,F - decfsz br0,F - goto lerr - - - movlw 0x08 ; TEST 8 - movwf PORTB ; Set Test Number - - movlw r1 - movwf FSR - movlw 0x04 - movwf INDF - decfsz INDF,F - decfsz INDF,F - decfsz INDF,F - decfsz INDF,F - goto lerr - - movlw br9 - movwf FSR - movlw 0x04 - movwf INDF - decfsz INDF,F - decfsz INDF,F - decfsz INDF,F - decfsz INDF,F - goto lerr - - - movlw 0x09 ; TEST 9 - movwf PORTB ; Set Test Number - - movlw 0xfc - movwf FSR - incf FSR,F - incf FSR,F - incf FSR,F - incf FSR,F - btfss STATUS,Z - goto lerr - - movlw 0x04 - movwf FSR - movlw 0x7f - decf FSR,F - decf FSR,F - decf FSR,F - decf FSR,F - andwf FSR,F - btfss STATUS,Z - goto lerr - - movlw 0x0a ; TEST 10 - movwf PORTB ; Set Test Number - - movlw 0xfc - movwf STATUS - movlw 0x18 - incf STATUS,F - incf STATUS,F - incf STATUS,F - incf STATUS,F - subwf STATUS,W - btfss STATUS,Z - goto lerr - - - - - nop - nop - nop - nop - movlw 0x01 - movwf PORTA - nop - nop - nop - nop -good ; Loop in good on success - goto good - nop - nop - nop - nop - -lerr - movlw 0xff - movwf PORTA - - nop - nop - nop - nop -lerr_loop ; Loop in lerr on failure - goto lerr_loop - nop - nop - nop - nop - - END - Index: tags/alpha/scode/tmr_wdt.rom =================================================================== --- tags/alpha/scode/tmr_wdt.rom (revision 6) +++ tags/alpha/scode/tmr_wdt.rom (nonexistent) @@ -1,63 +0,0 @@ - -@000 040 -@001 024 -@002 025 -@003 026 -@004 027 -@005 005 -@006 006 -@007 007 -@008 C01 -@009 026 -@00A C00 -@00B 002 -@00C 021 -@00D 004 -@00E 000 -@00F 000 -@010 000 -@011 000 -@012 040 -@013 029 -@014 040 -@015 028 -@016 201 -@017 2E8 -@018 A16 -@019 2E9 -@01A A14 -@01B 000 -@01C 000 -@01D 000 -@01E 000 -@01F 000 -@020 000 -@021 040 -@022 021 -@023 004 -@024 000 -@025 000 -@026 000 -@027 000 -@028 C01 -@029 025 -@02A 000 -@02B 000 -@02C 000 -@02D 000 -@02E A2E -@02F 000 -@030 000 -@031 000 -@032 000 -@033 CFF -@034 025 -@035 000 -@036 000 -@037 000 -@038 000 -@039 A39 -@03A 000 -@03B 000 -@03C 000 -@03D 000 Index: tags/alpha/scode/hex2v.c =================================================================== --- tags/alpha/scode/hex2v.c (revision 6) +++ tags/alpha/scode/hex2v.c (nonexistent) @@ -1,125 +0,0 @@ -/* *********************************************************************** - The Free IP Project - Free-RISC8 -- Verilog 8-bit Microcontroller - (c) 1999, The Free IP Project and Thomas Coonan - - - FREE IP GENERAL PUBLIC LICENSE - TERMS AND CONDITIONS FOR USE, COPYING, DISTRIBUTION, AND MODIFICATION - - 1. You may copy and distribute verbatim copies of this core, as long - as this file, and the other associated files, remain intact and - unmodified. Modifications are outlined below. - 2. You may use this core in any way, be it academic, commercial, or - military. Modified or not. - 3. Distribution of this core must be free of charge. Charging is - allowed only for value added services. Value added services - would include copying fees, modifications, customizations, and - inclusion in other products. - 4. If a modified source code is distributed, the original unmodified - source code must also be included (or a link to the Free IP web - site). In the modified source code there must be clear - identification of the modified version. - 5. Visit the Free IP web site for additional information. - http://www.free-ip.com - -*********************************************************************** */ - -// Intel HEX to Verilog converter. -// -// Usage: -// hex2v -// -// You probably want to simply redirect the output into a file. -// -#include -#include -#include - -// Input and Output file streams. -FILE *fpi; - -// Well.. Let's read stuff in completely before outputting.. Programs -// should be pretty small.. -// -#define MAX_MEMORY_SIZE 2048 -struct { - unsigned int nAddress; - unsigned int byData; -} Memory[MAX_MEMORY_SIZE]; - -char szLine[80]; -unsigned int start_address, address, ndata_bytes, ndata_words; -unsigned int data; -unsigned int nMemoryCount; - -int main (int argc, char *argv[]) -{ - int i; - - if (argc != 2) { - printf ("\nThe Synthetic PIC --- Intel HEX File to Verilog memory file"); - printf ("\nUsage: hex2verilog "); - printf ("\n"); - return 0; - } - - - // Open input HEX file - fpi=fopen(argv[1], "r"); - if (!fpi) { - printf("\nCan't open input file %s.\n", argv[1]); - return 1; - } - - // Read in the HEX file - // - // !! Note, that things are a little strange for us, because the PIC is - // a 12-bit instruction, addresses are 16-bit, and the hex format is - // 8-bit oriented!! - // - nMemoryCount = 0; - while (!feof(fpi)) { - // Get one Intel HEX line - fgets (szLine, 80, fpi); - if (strlen(szLine) >= 10) { - // This is the PIC, with its 12-bit "words". We're interested in these - // words and not the bytes. Read 4 hex digits at a time for each - // address. - // - sscanf (&szLine[1], "%2x%4x", &ndata_bytes, &start_address); - if (start_address >= 0 && start_address <= 20000 && ndata_bytes > 0) { - // Suck up data bytes starting at 9th byte. - i = 9; - - // Words.. not bytes.. - ndata_words = ndata_bytes/2; - start_address = start_address/2; - - // Spit out all the data that is supposed to be on this line. - for (address = start_address; address < start_address + ndata_words; address++) { - // Scan out 4 hex digits for a word. This will be one address. - sscanf (&szLine[i], "%04x", &data); - - // Need to swap bytes... - data = ((data >> 8) & 0x00ff) | ((data << 8) & 0xff00); - i += 4; - - // Store in our memory buffer - Memory[nMemoryCount].nAddress = address; - Memory[nMemoryCount].byData = data; - nMemoryCount++; - } - } - } - } - fclose (fpi); - - // Now output the Verilog $readmemh format! - // - for (i = 0; i < nMemoryCount; i++) { - printf ("\n@%03X %03X", Memory[i].nAddress, Memory[i].byData); - } - printf ("\n"); - -} Index: trunk/verilog/core/alu.v =================================================================== --- trunk/verilog/core/alu.v (revision 6) +++ trunk/verilog/core/alu.v (nonexistent) @@ -1,161 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// Mini-RISC-1 //// -//// ALU //// -//// //// -//// //// -//// Author: Rudolf Usselmann //// -//// rudi@asics.ws //// -//// //// -//// //// -//// D/L from: http://www.opencores.org/cores/minirisc/ //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000-2002 Rudolf Usselmann //// -//// www.asics.ws //// -//// rudi@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: alu.v,v 1.3 2002-10-01 12:44:24 rudi Exp $ -// -// $Date: 2002-10-01 12:44:24 $ -// $Revision: 1.3 $ -// $Author: rudi $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: not supported by cvs2svn $ -// Revision 1.2 2002/09/27 15:35:40 rudi -// Minor update to newer devices ... -// -// -// -// -// -// -// -// -// -// -// - - -`timescale 1ns / 10ps - -module alu(s1, s2, mask, out, op, c_in, c, dc, z); -input [7:0] s1, s2, mask; -output [7:0] out; -input [3:0] op; -input c_in; -output c, dc, z; - -parameter ALU_ADD = 4'h0, - ALU_SUB = 4'h1, - ALU_INC = 4'h2, - ALU_DEC = 4'h3, - - ALU_AND = 4'h4, - ALU_CLR = 4'h5, - ALU_NOT = 4'h6, - ALU_IOR = 4'h7, - ALU_MOV = 4'h8, - ALU_MOVW = 4'h9, - ALU_RLF = 4'ha, - ALU_RRF = 4'hb, - ALU_SWP = 4'hc, - ALU_XOR = 4'hd, - ALU_BCF = 4'he, - ALU_BSF = 4'hf; - -wire [7:0] out; -wire co, bo; -wire c; -wire z; -wire [5:0] tmp_add; -wire borrow_dc; - -wire [7:0] add_sub_out; -wire add_sub_sel; -wire [7:0] s2_a; -wire [8:0] rlf_out, rrf_out; -wire [7:0] out_next1, out_next2, out_next3; - -/* -reg cout; -reg [7:0] out_t; -always @(op or s1 or s2 or mask or c_in) - begin - cout = 0; - case(op) // synopsys full_case parallel_case - ALU_ADD: {cout, out_t} = s1 + s2; - ALU_AND: out_t = s1 & s2; - ALU_CLR: out_t = 8'h00; - ALU_NOT: out_t = ~s1; - ALU_DEC: out_t = s1 - 1; - ALU_INC: out_t = s1 + 1; - ALU_IOR: out_t = s1 | s2; - ALU_MOV: out_t = s1; - ALU_MOVW: out_t = s2; - ALU_RLF: {cout, out_t} = {s1[7:0], c_in}; - ALU_RRF: {cout, out_t} = {s1[0], c_in, s1[7:1]}; - ALU_SUB: {cout, out_t} = s1 - s2; - ALU_SWP: out_t = {s1[3:0], s1[7:4]}; - ALU_XOR: out_t = s1 ^ s2; - ALU_BCF: out_t = s1 & ~mask; - ALU_BSF: out_t = s1 | mask; - endcase - end -*/ - -assign rlf_out = {s1[7:0], c_in}; -assign rrf_out = {s1[0], c_in, s1[7:1]}; - -assign add_sub_sel = (op[3:2]==2'b0); - -mux4_8 u2( .sel(op[3:2]), .in0(add_sub_out), .in1(out_next1), .in2(out_next2), .in3(out_next3), .out(out) ); -mux4_8 u3( .sel(op[1:0]), .in0(s1 & s2), .in1(8'h00), .in2(~s1), .in3(s1 | s2), .out(out_next1) ); -mux4_8 u4( .sel(op[1:0]), .in0(s1), .in1(s2), .in2(rlf_out[7:0]), .in3(rrf_out[7:0]), .out(out_next2) ); -mux4_8 u5( .sel(op[1:0]), .in0({s1[3:0], s1[7:4]}), .in1(s1^s2), .in2(s1 & ~mask), .in3(s1 | mask), .out(out_next3) ); - -mux2_8 u0( .sel(op[1]), .in0(s2), .in1(8'h01), .out(s2_a) ); - -add_sub8_co u1( .sub(op[0]), .opa(s1), .opb(s2_a), .out(add_sub_out), .co(co) ); - -// C bit generation -assign c = add_sub_sel ? co : op[0] ? rrf_out[8] : rlf_out[8]; - -// Z Bit generation -assign z = (out==8'h0); - -// DC Bit geberation -// This section is really bad, but not in the critical path, -// so I leave it alone for now .... -assign borrow_dc = s1[3:0] >= s2[3:0]; -assign tmp_add = s1[3:0] + s2[3:0]; -assign dc = (op==ALU_SUB) ? borrow_dc : tmp_add[4]; - -endmodule Index: trunk/verilog/core/register_file.v =================================================================== --- trunk/verilog/core/register_file.v (revision 6) +++ trunk/verilog/core/register_file.v (nonexistent) @@ -1,124 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// Mini-RISC-1 //// -//// Register File //// -//// //// -//// //// -//// Author: Rudolf Usselmann //// -//// rudi@asics.ws //// -//// //// -//// //// -//// D/L from: http://www.opencores.org/cores/minirisc/ //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000-2002 Rudolf Usselmann //// -//// www.asics.ws //// -//// rudi@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: register_file.v,v 1.3 2002-10-01 12:44:24 rudi Exp $ -// -// $Date: 2002-10-01 12:44:24 $ -// $Revision: 1.3 $ -// $Author: rudi $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: not supported by cvs2svn $ -// Revision 1.2 2002/09/27 15:35:40 rudi -// Minor update to newer devices ... -// -// -// -// -// -// -// -// -// -// -// - -`timescale 1ns / 10ps - -module register_file( clk, rst, - rf_rd_bnk, rf_rd_addr, rf_rd_data, - rf_we, rf_wr_bnk, rf_wr_addr, rf_wr_data); - -input clk,rst; -input [1:0] rf_rd_bnk; -input [4:0] rf_rd_addr; -output [7:0] rf_rd_data; -input rf_we; -input [1:0] rf_wr_bnk; -input [4:0] rf_wr_addr; -input [7:0] rf_wr_data; - -wire clk; -wire [7:0] rf_rd_data; -wire [6:0] rd_addr; -wire [6:0] wr_addr; -wire [7:0] rf_rd_data_mem; -reg [7:0] wr_data_tmp; -reg rd_wr_addr_equal; - -// Simple Read & Write Address Mapping to memory address -assign rd_addr[6] = ~rf_rd_addr[4]; -assign rd_addr[5:3] = rf_rd_addr[4] ? {rf_rd_bnk, rf_rd_addr[3]} : 3'h0; -assign rd_addr[2:0] = rf_rd_addr[2:0]; - -assign wr_addr[6] = ~rf_wr_addr[4]; -assign wr_addr[5:3] = rf_wr_addr[4] ? {rf_wr_bnk, rf_wr_addr[3]} : 3'h0; -assign wr_addr[2:0] = rf_wr_addr[2:0]; - -// This logic is to bypass the register file if we are reading and -// writing (in previous instruction) to the same register -always @(posedge clk) - rd_wr_addr_equal <= #1 (rd_addr==wr_addr) & rf_we; - -assign rf_rd_data = rd_wr_addr_equal ? wr_data_tmp : rf_rd_data_mem; - -always @(posedge clk) - wr_data_tmp <= #1 rf_wr_data; - -// This is the actual Memory -generic_dpram #(7,8) rf0( - .rclk( clk ), - .rrst( rst ), - .rce( 1'b1 ), - .oe( 1'b1 ), - .raddr( rd_addr ), - .do( rf_rd_data_mem ), - .wclk( clk ), - .wrst( rst ), - .wce( 1'b1 ), - .we( rf_we ), - .waddr( wr_addr ), - .di( rf_wr_data ) - ); - -endmodule Index: trunk/verilog/core/primitives_xilinx.v =================================================================== --- trunk/verilog/core/primitives_xilinx.v (revision 6) +++ trunk/verilog/core/primitives_xilinx.v (nonexistent) @@ -1,1091 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// Mini-RISC-1 //// -//// Prescaler and Wachdog Counter //// -//// //// -//// //// -//// Author: Rudolf Usselmann //// -//// rudi@asics.ws //// -//// //// -//// //// -//// D/L from: http://www.opencores.org/cores/minirisc/ //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000-2002 Rudolf Usselmann //// -//// www.asics.ws //// -//// rudi@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: primitives_xilinx.v,v 1.3 2002-10-01 12:44:24 rudi Exp $ -// -// $Date: 2002-10-01 12:44:24 $ -// $Revision: 1.3 $ -// $Author: rudi $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: not supported by cvs2svn $ -// Revision 1.2 2002/09/27 15:35:40 rudi -// Minor update to newer devices ... -// -// -// -// -// -// -// -// -// -// -// - -`timescale 1ns / 10ps - -// LIB_TAG -// synopsys translate_off -`include "XilinxCoreLib/C_ADDSUB_V1_0.v" -`include "XilinxCoreLib/C_MUX_BUS_V1_0.v" -`include "XilinxCoreLib/C_COMPARE_V1_0.v" -`include "XilinxCoreLib/C_MUX_BIT_V1_0.v" -`include "XilinxCoreLib/C_MEM_DP_BLOCK_V1_0.v" -`include "XilinxCoreLib/C_REG_FD_V1_0.v" -// synopsys translate_on -// LIB_TAG_END - - -// Mux 4:1 8 bits wide -module mux4_8(sel, in0, in1, in2, in3, out); -input [1:0] sel; -input [7:0] in0, in1, in2, in3; -output [7:0] out; - -// INST_TAG -xilinx_mux4_8 u0 ( - .MA0(in0[0]), - .MA1(in0[1]), - .MA2(in0[2]), - .MA3(in0[3]), - .MA4(in0[4]), - .MA5(in0[5]), - .MA6(in0[6]), - .MA7(in0[7]), - - .MB0(in1[0]), - .MB1(in1[1]), - .MB2(in1[2]), - .MB3(in1[3]), - .MB4(in1[4]), - .MB5(in1[5]), - .MB6(in1[6]), - .MB7(in1[7]), - - .MC0(in2[0]), - .MC1(in2[1]), - .MC2(in2[2]), - .MC3(in2[3]), - .MC4(in2[4]), - .MC5(in2[5]), - .MC6(in2[6]), - .MC7(in2[7]), - - .MD0(in3[0]), - .MD1(in3[1]), - .MD2(in3[2]), - .MD3(in3[3]), - .MD4(in3[4]), - .MD5(in3[5]), - .MD6(in3[6]), - .MD7(in3[7]), - - .S0(sel[0]), - .S1(sel[1]), - - .O0(out[0]), - .O1(out[1]), - .O2(out[2]), - .O3(out[3]), - .O4(out[4]), - .O5(out[5]), - .O6(out[6]), - .O7(out[7]) ); -// INST_TAG_END - -endmodule - -/* -// MOD_TAG -module xilinx_mux4_8 (MA,MB,MC,MD,S,O); // synthesis black_box -input [7:0] MA; -input [7:0] MB; -input [7:0] MC; -input [7:0] MD; -input [1:0] S; -output [7:0] O; - -// synopsys translate_off -// synthesis translate_off - C_MUX_BUS_V1_0 #( - "00000000", - 1, - 0, - 0, - 0, - 0, - 0, - 1, - 0, - 0, - 0, - 0, - 4, - 0, - 2, - "00000000", - 0, - 1, - 8) - inst ( - .MA(MA), - .MB(MB), - .MC(MC), - .MD(MD), - .S(S), - .O(O)); -// synthesis translate_on -// synopsys translate_on -endmodule -// MOD_TAG_END -*/ - -// 8 bit comparator -module cmp8_eq(a,b,eq); -input [7:0] a,b; -output eq; - -// INST_TAG -xilinx_cmp8_eq u0 ( - .A0(a[0]), - .A1(a[1]), - .A2(a[2]), - .A3(a[3]), - .A4(a[4]), - .A5(a[5]), - .A6(a[6]), - .A7(a[7]), - - .B0(b[0]), - .B1(b[1]), - .B2(b[2]), - .B3(b[3]), - .B4(b[4]), - .B5(b[5]), - .B6(b[6]), - .B7(b[7]), - - .A_EQ_B(eq) ); -// INST_TAG_END - -endmodule - -/* -// MOD_TAG -module xilinx_cmp8_eq (A,B,A_EQ_B); // synthesis black_box -input [7 : 0] A; -input [7 : 0] B; -output A_EQ_B; - -// synopsys translate_off -// synthesis translate_off - C_COMPARE_V1_0 #( - "0", - 0, - "0", - 1, - 1, - 0, - 0, - 1, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 1, - 8) - inst ( - .A(A), - .B(B), - .A_EQ_B(A_EQ_B)); -// synthesis translate_on -// synopsys translate_on -endmodule -// MOD_TAG_END -*/ - -// MUX 2:1 7 bits wide -module mux2_7(sel, in0, in1, out); -input sel; -input [6:0] in0, in1; -output [6:0] out; - -// INST_TAG -xilinx_mux2_7 u0 ( - .MA0(in0[0]), - .MA1(in0[1]), - .MA2(in0[2]), - .MA3(in0[3]), - .MA4(in0[4]), - .MA5(in0[5]), - .MA6(in0[6]), - - .MB0(in1[0]), - .MB1(in1[1]), - .MB2(in1[2]), - .MB3(in1[3]), - .MB4(in1[4]), - .MB5(in1[5]), - .MB6(in1[6]), - - .S0(sel), - - .O0(out[0]), - .O1(out[1]), - .O2(out[2]), - .O3(out[3]), - .O4(out[4]), - .O5(out[5]), - .O6(out[6]) ); -// INST_TAG_END - -endmodule - -/* -// MOD_TAG -module xilinx_mux2_7 (MA,MB,S,O); // synthesis black_box -input [6 : 0] MA; -input [6 : 0] MB; -input [0 : 0] S; -output [6 : 0] O; - -// synopsys translate_off -// synthesis translate_off - C_MUX_BUS_V1_0 #( - "0000000", - 1, - 0, - 0, - 0, - 0, - 0, - 1, - 0, - 0, - 0, - 0, - 2, - 0, - 1, - "0000000", - 0, - 1, - 7) - inst ( - .MA(MA), - .MB(MB), - .S(S), - .O(O)); -// synthesis translate_on -// synopsys translate_on -endmodule -// MOD_TAG_END -*/ - - -// Mux 8:1 1 bit wide -module mux8_1( sel, in, out); -input [2:0] sel; -input [7:0] in; -output out; - -// INST_TAG -xilinx_mux8_1 u0 ( - .M0(in[0]), - .M1(in[1]), - .M2(in[2]), - .M3(in[3]), - .M4(in[4]), - .M5(in[5]), - .M6(in[6]), - .M7(in[7]), - - .S0(sel[0]), - .S1(sel[1]), - .S2(sel[2]), - - - .O(out)); -// INST_TAG_END - -endmodule - -/* -// MOD_TAG -module xilinx_mux8_1 (M,S,O); // synthesis black_box -input [7 : 0] M; -input [2 : 0] S; -output O; - -// synopsys translate_off -// synthesis translate_off - C_MUX_BIT_V1_0 #( - "0", - 1, - 0, - 0, - 0, - 0, - 1, - 0, - 0, - 0, - 0, - 8, - 3, - "0", - 0, - 1) - inst ( - .M(M), - .S(S), - .O(O)); -// synthesis translate_on -// synopsys translate_on -endmodule -// MOD_TAG_END -*/ - -// Mux 2:1 8 bits wide -module mux2_8(sel, in0, in1, out); -input sel; -input [7:0] in0, in1; -output [7:0] out; - -// INST_TAG -xilinx_mux2_8 u0( - .MA0(in0[0]), - .MA1(in0[1]), - .MA2(in0[2]), - .MA3(in0[3]), - .MA4(in0[4]), - .MA5(in0[5]), - .MA6(in0[6]), - .MA7(in0[7]), - - .MB0(in1[0]), - .MB1(in1[1]), - .MB2(in1[2]), - .MB3(in1[3]), - .MB4(in1[4]), - .MB5(in1[5]), - .MB6(in1[6]), - .MB7(in1[7]), - - .S0(sel), - - .O0(out[0]), - .O1(out[1]), - .O2(out[2]), - .O3(out[3]), - .O4(out[4]), - .O5(out[5]), - .O6(out[6]), - .O7(out[7]) ); -// INST_TAG_END - -endmodule - - -/* -// MOD_TAG -module xilinx_mux2_8 (MA, MB, S, O); // synthesis black_box -input [7 : 0] MA; -input [7 : 0] MB; -input [0 : 0] S; -output [7 : 0] O; - -// synopsys translate_off -// synthesis translate_off - C_MUX_BUS_V1_0 #( - "00000000", - 1, - 0, - 0, - 0, - 0, - 0, - 1, - 0, - 0, - 0, - 0, - 2, - 0, - 1, - "00000000", - 0, - 1, - 8) - inst ( - .MA(MA), - .MB(MB), - .S(S), - .O(O)); -// synthesis translate_on -// synopsys translate_on -endmodule -// MOD_TAG_END -*/ - -// Mux 8:1 8 bits wide -module mux8_8(sel, in0, in1, in2, in3, in4, in5, in6, in7, out); -input [2:0] sel; -input [7:0] in0, in1, in2, in3, in4, in5, in6, in7; -output [7:0] out; - -// INST_TAG -xilinx_mux8_8 u0 ( - .MA0(in0[0]), - .MA1(in0[1]), - .MA2(in0[2]), - .MA3(in0[3]), - .MA4(in0[4]), - .MA5(in0[5]), - .MA6(in0[6]), - .MA7(in0[7]), - - .MB0(in1[0]), - .MB1(in1[1]), - .MB2(in1[2]), - .MB3(in1[3]), - .MB4(in1[4]), - .MB5(in1[5]), - .MB6(in1[6]), - .MB7(in1[7]), - - .MC0(in2[0]), - .MC1(in2[1]), - .MC2(in2[2]), - .MC3(in2[3]), - .MC4(in2[4]), - .MC5(in2[5]), - .MC6(in2[6]), - .MC7(in2[7]), - - .MD0(in3[0]), - .MD1(in3[1]), - .MD2(in3[2]), - .MD3(in3[3]), - .MD4(in3[4]), - .MD5(in3[5]), - .MD6(in3[6]), - .MD7(in3[7]), - - .ME0(in4[0]), - .ME1(in4[1]), - .ME2(in4[2]), - .ME3(in4[3]), - .ME4(in4[4]), - .ME5(in4[5]), - .ME6(in4[6]), - .ME7(in4[7]), - - .MF0(in5[0]), - .MF1(in5[1]), - .MF2(in5[2]), - .MF3(in5[3]), - .MF4(in5[4]), - .MF5(in5[5]), - .MF6(in5[6]), - .MF7(in5[7]), - - .MG0(in6[0]), - .MG1(in6[1]), - .MG2(in6[2]), - .MG3(in6[3]), - .MG4(in6[4]), - .MG5(in6[5]), - .MG6(in6[6]), - .MG7(in6[7]), - - .MH0(in7[0]), - .MH1(in7[1]), - .MH2(in7[2]), - .MH3(in7[3]), - .MH4(in7[4]), - .MH5(in7[5]), - .MH6(in7[6]), - .MH7(in7[7]), - - .S0(sel[0]), - .S1(sel[1]), - .S2(sel[2]), - - .O0(out[0]), - .O1(out[1]), - .O2(out[2]), - .O3(out[3]), - .O4(out[4]), - .O5(out[5]), - .O6(out[6]), - .O7(out[7]) ); - -// INST_TAG_END - -endmodule - -/* -// MOD_TAG -module xilinx_mux8_8 (MA,MB,MC,MD,ME,MF,MG,MH,S,O); // synthesis black_box -input [7 : 0] MA; -input [7 : 0] MB; -input [7 : 0] MC; -input [7 : 0] MD; -input [7 : 0] ME; -input [7 : 0] MF; -input [7 : 0] MG; -input [7 : 0] MH; -input [2 : 0] S; -output [7 : 0] O; - -// synopsys translate_off -// synthesis translate_off - C_MUX_BUS_V1_0 #( - "00000000", - 1, - 0, - 0, - 0, - 0, - 0, - 1, - 0, - 0, - 0, - 0, - 8, - 0, - 3, - "00000000", - 0, - 1, - 8) - inst ( - .MA(MA), - .MB(MB), - .MC(MC), - .MD(MD), - .ME(ME), - .MF(MF), - .MG(MG), - .MH(MH), - .S(S), - .O(O)); -// synthesis translate_on -// synopsys translate_on -endmodule -// MOD_TAG_END -*/ - -// Mux 2:1 11 bits wide -module mux2_11(sel, in0, in1, out); -input sel; -input [10:0] in0, in1; -output [10:0] out; - -// INST_TAG -xilinx_mux2_11 u0 ( - .MA0(in0[0]), - .MA1(in0[1]), - .MA2(in0[2]), - .MA3(in0[3]), - .MA4(in0[4]), - .MA5(in0[5]), - .MA6(in0[6]), - .MA7(in0[7]), - .MA8(in0[8]), - .MA9(in0[9]), - .MA10(in0[10]), - - .MB0(in1[0]), - .MB1(in1[1]), - .MB2(in1[2]), - .MB3(in1[3]), - .MB4(in1[4]), - .MB5(in1[5]), - .MB6(in1[6]), - .MB7(in1[7]), - .MB8(in1[8]), - .MB9(in1[9]), - .MB10(in1[10]), - - .S0(sel), - - .O0(out[0]), - .O1(out[1]), - .O2(out[2]), - .O3(out[3]), - .O4(out[4]), - .O5(out[5]), - .O6(out[6]), - .O7(out[7]), - .O8(out[8]), - .O9(out[9]), - .O10(out[10]) ); -// INST_TAG_END - -endmodule - -/* -// MOD_TAG -module xilinx_mux2_11 (MA,MB,S,O); // synthesis black_box -input [10 : 0] MA; -input [10 : 0] MB; -input [0 : 0] S; -output [10 : 0] O; - -// synopsys translate_off -// synthesis translate_off - C_MUX_BUS_V1_0 #( - "00000000000", - 1, - 0, - 0, - 0, - 0, - 0, - 1, - 0, - 0, - 0, - 0, - 2, - 0, - 1, - "00000000000", - 0, - 1, - 11) - inst ( - .MA(MA), - .MB(MB), - .S(S), - .O(O)); -// synthesis translate_on -// synopsys translate_on -endmodule -// MOD_TAG_END -*/ - - -// 8bit Add/Sub with carry/borrow out -module add_sub8_co(sub, opa, opb, out, co); -input sub; -input [7:0] opa, opb; -output [7:0] out; -output co; - -wire add; -assign add = ~sub; - -// INST_TAG -xilinx_add_sub8_co u0 ( - .A0(opa[0]), - .A1(opa[1]), - .A2(opa[2]), - .A3(opa[3]), - .A4(opa[4]), - .A5(opa[5]), - .A6(opa[6]), - .A7(opa[7]), - - .B0(opb[0]), - .B1(opb[1]), - .B2(opb[2]), - .B3(opb[3]), - .B4(opb[4]), - .B5(opb[5]), - .B6(opb[6]), - .B7(opb[7]), - - .C_OUT(co), - .ADD(add), - - .S0(out[0]), - .S1(out[1]), - .S2(out[2]), - .S3(out[3]), - .S4(out[4]), - .S5(out[5]), - .S6(out[6]), - .S7(out[7]) ); -// INST_TAG_END - -endmodule - -/* -// MOD_TAG -module xilinx_add_sub8_co (A,B,C_OUT,ADD,S); // synthesis black_box -input [7 : 0] A; -input [7 : 0] B; -output C_OUT; -input ADD; -output [7 : 0] S; - -// synopsys translate_off -// synthesis translate_off - C_ADDSUB_V1_0 #( - 2, - "0000", - 1, - 8, - 0, - 0, - 0, - 1, - "0", - 8, - 1, - 0, - 1, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 1, - 0, - 0, - 0, - 0, - 0, - 1, - 0, - 0, - 0, - 7, - 0, - 8, - 1, - "0", - 0, - 1) - inst ( - .A(A), - .B(B), - .C_OUT(C_OUT), - .ADD(ADD), - .S(S)); -// synthesis translate_on -// synopsys translate_on -endmodule -// MOD_TAG_END -*/ - -// 11 bit incrementer -module inc11(in, out); -input [10:0] in; -output [10:0] out; - -// INST_TAG -xilinx_inc11 u0 ( - .A0(in[0]), - .A1(in[1]), - .A2(in[2]), - .A3(in[3]), - .A4(in[4]), - .A5(in[5]), - .A6(in[6]), - .A7(in[7]), - .A8(in[8]), - .A9(in[9]), - .A10(in[10]), - - .S0(out[0]), - .S1(out[1]), - .S2(out[2]), - .S3(out[3]), - .S4(out[4]), - .S5(out[5]), - .S6(out[6]), - .S7(out[7]), - .S8(out[8]), - .S9(out[9]), - .S10(out[10]) ); -// INST_TAG_END - -endmodule - -/* -// MOD_TAG -module xilinx_inc11 (A,S); // synthesis black_box -input [10 : 0] A; -output [10 : 0] S; - -// synopsys translate_off -// synthesis translate_off - C_ADDSUB_V1_0 #( - 0, - "0000", - 1, - 11, - 0, - 0, - 1, - 1, - "0001", - 11, - 1, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 1, - 0, - 0, - 0, - 10, - 0, - 11, - 1, - "0", - 0, - 1) - inst ( - .A(A), - .S(S)); -// synthesis translate_on -// synopsys translate_on -endmodule -// MOD_TAG_END -*/ - -// 8 bit incrementer -module inc8(in, out); -input [7:0] in; -output [7:0] out; - -// INST_TAG -xilinx_inc8 u0 ( - .A0(in[0]), - .A1(in[1]), - .A2(in[2]), - .A3(in[3]), - .A4(in[4]), - .A5(in[5]), - .A6(in[6]), - .A7(in[7]), - - .S0(out[0]), - .S1(out[1]), - .S2(out[2]), - .S3(out[3]), - .S4(out[4]), - .S5(out[5]), - .S6(out[6]), - .S7(out[7]) ); -// INST_TAG_END - -endmodule - -/* -// MOD_TAG -module xilinx_inc8 (A,S); // synthesis black_box -input [7 : 0] A; -output [7 : 0] S; - -// synopsys translate_off -// synthesis translate_off - C_ADDSUB_V1_0 #( - 0, - "0000", - 1, - 8, - 0, - 0, - 1, - 1, - "0001", - 8, - 1, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 1, - 0, - 0, - 0, - 7, - 0, - 8, - 1, - "0", - 0, - 1) - inst ( - .A(A), - .S(S)); -// synthesis translate_on -// synopsys translate_on -endmodule -// MOD_TAG_END -*/ - - -// A Basic Synchrounous FIFO (4 entries deep) -module sfifo4x11(clk, push, din, pop, dout); -input clk; -input push; -input [10:0] din; -input pop; -output [10:0] dout; - -reg [10:0] stack1, stack2, stack3, stack4; - -assign dout = stack1; - -always @(posedge clk) - begin - if(push) // PUSH stack - begin - stack4 <= #1 stack3; - stack3 <= #1 stack2; - stack2 <= #1 stack1; - stack1 <= #1 din; - end - if(pop) // POP stack - begin - stack1 <= #1 stack2; - stack2 <= #1 stack3; - stack3 <= #1 stack4; - end - end - -endmodule - - -// Synchrounous SRAM -// 128 bytes by 8 bits -// 1 read port, 1 write port -// FOR XILINX VERTEX SERIES -module ssram_128x8(clk, rd_addr, rd_data, we, wr_addr, wr_data); -input clk; -input [6:0] rd_addr; -output [7:0] rd_data; -input we; -input [6:0] wr_addr; -input [7:0] wr_data; - -wire [7:0] tmp; - - -// Alternatively RAMs can be instantiated directly -RAMB4_S8_S8 u0( - .DOA( rd_data ), - .ADDRA( {2'b0, rd_addr} ), - .DIA( 8'h00 ), - .ENA( 1'b1 ), - .CLKA( clk ), - .WEA( 1'b0 ), - .RSTA( 1'b0 ), - .DOB( tmp ), - .ADDRB( {2'b0, wr_addr} ), - .DIB( wr_data ), - .ENB( 1'b1 ), - .CLKB( clk ), - .WEB( we ), - .RSTB( 1'b0 ) ); - - -endmodule - - - -// This block is the global Set/Rest for Xilinx VIrtex Serries -// Connect it up as described in Xilinx documentation -// Leave it out for Non Xilinx implementations -module glbl(rst); -input rst; - -wire GSR; - -assign GSR = rst; - -endmodule - - Index: trunk/verilog/core/presclr_wdt.v =================================================================== --- trunk/verilog/core/presclr_wdt.v (revision 6) +++ trunk/verilog/core/presclr_wdt.v (nonexistent) @@ -1,150 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// Mini-RISC-1 //// -//// Prescaler and Wachdog Counter //// -//// //// -//// //// -//// Author: Rudolf Usselmann //// -//// rudi@asics.ws //// -//// //// -//// //// -//// D/L from: http://www.opencores.org/cores/minirisc/ //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000-2002 Rudolf Usselmann //// -//// www.asics.ws //// -//// rudi@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: presclr_wdt.v,v 1.2 2002-09-27 15:35:40 rudi Exp $ -// -// $Date: 2002-09-27 15:35:40 $ -// $Revision: 1.2 $ -// $Author: rudi $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: not supported by cvs2svn $ -// -// -// -// -// -// -// -// -// -// - - -`timescale 1ns / 10ps - -// Prescaler and Wachdog Counter -module presclr_wdt(clk, rst, tcki, option, tmr0_we, tmr0_cnt_en, wdt_en, wdt_clr, wdt_to); -input clk; -input rst; -input tcki; -input [5:0] option; -input tmr0_we; -output tmr0_cnt_en; -input wdt_en, wdt_clr; -output wdt_to; - - -reg [7:0] prescaler; -reg [7:0] wdt; -reg tmr0_cnt_en; -reg tcki_r; -reg wdt_to; -wire tose; -wire tosc; -wire psa; -wire [2:0] ps; -wire tcki_a, tcki_b; -wire presclr_ce; -wire prsclr_clr; -wire wdt_to_direct; -reg presclr_out, presclr_out_r1; -reg presclr_out_next; -wire [7:0] presclr_plus_1, wdt_plus_1; -wire [7:0] prescaler_next, prescaler_next1; -wire [7:0] wdt_next, wdt_next1; - -// Inputs select -assign ps = option[2:0]; -assign psa = option[3]; -assign tose = option[4]; -assign tosc = option[5]; - -always @(posedge clk) - tcki_r <= #1 tcki; - -assign tcki_a = tose ^ tcki_r; -assign tcki_b = tosc ? tcki_a : 1'b1; -assign presclr_ce = psa ? wdt_to_direct : tcki_b; - -always @(posedge clk) - tmr0_cnt_en <= #1 psa ? tcki_b : presclr_out; - -// Prescaler -assign prsclr_clr = psa ? wdt_clr : tmr0_we; - -always @(posedge clk) - if(rst | prsclr_clr) prescaler <= #1 8'h00; - else - if(presclr_ce) prescaler <= #1 prescaler + 8'h01; - -always @(ps or prescaler) - case(ps) - 3'd0: presclr_out_next = prescaler[0]; - 3'd1: presclr_out_next = prescaler[1]; - 3'd2: presclr_out_next = prescaler[2]; - 3'd3: presclr_out_next = prescaler[3]; - 3'd4: presclr_out_next = prescaler[4]; - 3'd5: presclr_out_next = prescaler[5]; - 3'd6: presclr_out_next = prescaler[6]; - 3'd7: presclr_out_next = prescaler[7]; - endcase - -always @(posedge clk) - presclr_out_r1 <= #1 presclr_out_next; - -always @(posedge clk) // Edge detector for prescaler output - presclr_out <= #1 presclr_out_next & ~presclr_out_r1 & ~prsclr_clr; - -// Wachdog timer -always @(posedge clk) - wdt_to <= #1 psa ? presclr_out : wdt_to_direct; - -always @(posedge clk) - if(rst | wdt_clr) wdt <= #1 8'h00; - else - if(wdt_en) wdt <= #1 wdt + 8'h01; // wdt_plus_1; - -assign wdt_to_direct = (wdt == 8'hff); - -endmodule Index: trunk/verilog/core/risc_core.v =================================================================== --- trunk/verilog/core/risc_core.v (revision 6) +++ trunk/verilog/core/risc_core.v (nonexistent) @@ -1,838 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// Mini-RISC-1 //// -//// Mini-Risc Core //// -//// //// -//// //// -//// Author: Rudolf Usselmann //// -//// rudi@asics.ws //// -//// //// -//// //// -//// D/L from: http://www.opencores.org/cores/minirisc/ //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000-2002 Rudolf Usselmann //// -//// www.asics.ws //// -//// rudi@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: risc_core.v,v 1.3 2002-10-01 12:44:24 rudi Exp $ -// -// $Date: 2002-10-01 12:44:24 $ -// $Revision: 1.3 $ -// $Author: rudi $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: not supported by cvs2svn $ -// Revision 1.2 2002/09/27 15:35:40 rudi -// Minor update to newer devices ... -// -// -// -// -// -// -// -// -// -// -// - -`timescale 1ns / 10ps - -module mrisc( - clk, - rst_in, - - inst_addr, - inst_data, - - portain, - portbin, - portcin, - - portaout, - portbout, - portcout, - - trisa, - trisb, - trisc, - - tcki, - wdt_en ); - -// Basic Core I/O. -input clk; -input rst_in; - -// Program memory interface -output [10:0] inst_addr; -input [11:0] inst_data; - -// Basic I/O Ports -input [7:0] portain; -input [7:0] portbin; -input [7:0] portcin; - -output [7:0] portaout; -output [7:0] portbout; -output [7:0] portcout; - -output [7:0] trisa; -output [7:0] trisb; -output [7:0] trisc; - -input tcki; -input wdt_en; - -// This should be set to the ROM location where our restart vector is. -// As set here, we have 512 words of program space. -parameter PC_RST_VECTOR = 11'h000, // Should be: 11'h7FF, - STAT_RST_VALUE = 8'h18, - OPT_RST_VALUE = 8'h3f, - FSR_RST_VALUE = 7'h0, - TRIS_RST_VALUE = 8'hff; - -parameter ALU_ADD = 4'h0, - ALU_SUB = 4'h1, - ALU_INC = 4'h2, - ALU_DEC = 4'h3, - - ALU_AND = 4'h4, - ALU_CLR = 4'h5, - ALU_NOT = 4'h6, - ALU_IOR = 4'h7, - ALU_MOV = 4'h8, - ALU_MOVW = 4'h9, - ALU_RLF = 4'ha, - ALU_RRF = 4'hb, - ALU_SWP = 4'hc, - ALU_XOR = 4'hd, - ALU_BCF = 4'he, - ALU_BSF = 4'hf; - -parameter // Byte Oriented RF Operations - I_ADDWF = 12'b0001_11??_????, - I_ANDWF = 12'b0001_01??_????, - I_CLRF = 12'b0000_011?_????, - I_CLRW = 12'b0000_0100_0000, - I_COMF = 12'b0010_01??_????, - I_DEC = 12'b0000_11??_????, - I_DECFSZ = 12'b0010_11??_????, - I_INCF = 12'b0010_10??_????, - I_INCFSZ = 12'b0011_11??_????, - I_IORWF = 12'b0001_00??_????, - I_MOV = 12'b0010_00??_????, - I_MOVWF = 12'b0000_001?_????, - I_NOP = 12'b0000_0000_0000, - I_RLF = 12'b0011_01??_????, - I_RRF = 12'b0011_00??_????, - I_SUBWF = 12'b0000_10??_????, - I_SWAPF = 12'b0011_10??_????, - I_XORWF = 12'b0001_10??_????, - - // Bit Oriented RF Operations - I_BCF = 12'b0100_????_????, - I_BSF = 12'b0101_????_????, - I_BTFSC = 12'b0110_????_????, - I_BTFSS = 12'b0111_????_????, - - // Literal & Controll Operations - I_ANDLW = 12'b1110_????_????, - I_CALL = 12'b1001_????_????, - I_CLRWDT = 12'b0000_0000_0100, - I_GOTO = 12'b101?_????_????, - I_IORLW = 12'b1101_????_????, - I_MOVLW = 12'b1100_????_????, - I_OPTION = 12'b0000_0000_0010, - I_RETLW = 12'b1000_????_????, - I_SLEEP = 12'b0000_0000_0011, - I_TRIS = 12'b0000_0000_0???, - I_XORLW = 12'b1111_????_????; - -parameter // sfr register address encodings - INDF_ADDR = 3'h0, - TMR0_ADDR = 3'h1, - PCL_ADDR = 3'h2, - STAT_ADDR = 3'h3, - FSR_ADDR = 3'h4, - PORTA_ADDR = 3'h5, - PORTB_ADDR = 3'h6, - PORTC_ADDR = 3'h7; - -parameter // Source 1 Select - K_SEL = 2'b10, - SFR_SEL = 2'b00, - RF_SEL = 2'b01; - -parameter // STATUS Register status bits we - STAT_WR_C = 3'b001, - STAT_WR_DC = 3'b010, - STAT_WR_Z = 3'b100; - - -// Instruction Register -reg rst; -reg [11:0] instr_0, instr_1; -reg rst_r1, rst_r2; -wire valid; -reg valid_1; - -reg [7:0] mask; -reg [7:0] sfr_rd_data; -reg [3:0] alu_op; -reg src1_sel; -reg [1:0] src1_sel_; - -wire [7:0] dout; // ALU output -wire [7:0] src1; // ALU Source 1 - -reg [2:0] stat_bwe; // status bits we -wire c_out, dc_out, z_out; - -reg pc_skz, pc_skz_; -reg pc_bset, pc_bset_; -reg pc_bclr, pc_bclr_; -reg pc_call, pc_call_; -reg pc_goto, pc_goto_; -reg pc_retlw, pc_retlw_; - -wire invalidate_1; -wire invalidate_0_; -reg invalidate_0; - -// stage 1 dst decode -reg w_we_; -reg rf_we_; -reg sfr_we_; -reg tris_we_; - -// stage 2 dst decode -reg w_we; -wire rf_we; -reg rf_we1, rf_we2, rf_we3; - -reg opt_we; -reg trisa_we; -reg trisb_we; -reg trisc_we; - -wire indf_we_; -reg tmr0_we; -wire pc_we_; -reg pc_we; -reg stat_we; -reg fsr_we; -reg porta_we; -reg portb_we; -reg portc_we; - -wire bit_sel; -wire [7:0] tmr0_next, tmr0_next1, tmr0_plus_1; -wire tmr0_cnt_en; -reg wdt_clr; -wire wdt_to; -wire wdt_en; -wire tcki; - -wire [7:0] sfr_rd_data_tmp1, sfr_rd_data_tmp2, sfr_rd_data_tmp3; - -// Register File Connections -wire [1:0] rf_rd_bnk, rf_wr_bnk; -wire [4:0] rf_rd_addr, rf_wr_addr; -wire [7:0] rf_rd_data, rf_wr_data; - -// Program Counter -reg [10:0] inst_addr; -reg [10:0] pc; -wire [10:0] pc_next; -wire [10:0] pc_plus_1; -wire [10:0] stack_out; -reg [10:0] pc_r, pc_r2; -wire [10:0] pc_next1, pc_next2, pc_next3; - -// W Register -reg [7:0] w; // Working Register -reg [7:0] status; // Status Register -wire [7:0] status_next; -reg [6:0] fsr; // fsr register ( for indirect addressing) -wire [6:0] fsr_next; -reg [7:0] tmr0; // Timer 0 -reg [5:0] option; // Option Register - -// Tristate Control registers. -reg [7:0] trisa; -reg [7:0] trisb; -reg [7:0] trisc; - -// I/O Port registers -reg [7:0] porta_r; // PORTA input register -reg [7:0] portb_r; // PORTB input register -reg [7:0] portc_r; // PORTC input register -reg [7:0] portaout; // PORTA output register -reg [7:0] portbout; // PORTB output register -reg [7:0] portcout; // PORTC output register - -//////////////////////////////////////////////////////////////////////// -// External Reset is Synchrounous to clock -always @(posedge clk) - rst <= #1 rst_in; - -//////////////////////////////////////////////////////////////////////// -// Synchrounous Register File -register_file u0( .clk( clk ), - .rst( rst ), - .rf_rd_bnk( rf_rd_bnk ), - .rf_rd_addr( rf_rd_addr ), - .rf_rd_data( rf_rd_data ), - .rf_we( rf_we ), - .rf_wr_bnk( rf_wr_bnk ), - .rf_wr_addr( rf_wr_addr ), - .rf_wr_data( rf_wr_data ) - ); - -//////////////////////////////////////////////////////////////////////// -// Always Fetch Next Instruction -always @(posedge clk) - instr_0 <= #1 inst_data; - -//////////////////////////////////////////////////////////////////////// -// Instr Decode & Read Logic - -always @(posedge clk) - begin - rst_r1 <= #1 rst | wdt_to; - rst_r2 <= #1 rst | rst_r1 | wdt_to; - end - -assign valid = ~rst_r2 & ~invalidate_1; -always @(posedge clk) - valid_1 <= #1 valid; - -always @(posedge clk) - instr_1 <= #1 instr_0; - -always @(posedge clk) // Basic Decode extracted directly from the instruction - begin - // Mask for bit modification instructions - case(instr_0[7:5]) // synopsys full_case parallel_case - 0: mask <= #1 8'h01; - 1: mask <= #1 8'h02; - 2: mask <= #1 8'h04; - 3: mask <= #1 8'h08; - 4: mask <= #1 8'h10; - 5: mask <= #1 8'h20; - 6: mask <= #1 8'h40; - 7: mask <= #1 8'h80; - endcase - end - -always @(posedge clk) - pc_r <= #1 pc; // Previous version of PC to accomodate for pipeline - -always @(posedge clk) // SFR Read Operands - if(src1_sel_[1]) sfr_rd_data <= #1 instr_0[7:0]; - else - case(instr_0[2:0]) // synopsys full_case parallel_case - 1: sfr_rd_data <= #1 tmr0_next; - 2: sfr_rd_data <= #1 pc_r[7:0]; - 3: sfr_rd_data <= #1 status_next; - 4: sfr_rd_data <= #1 {1'b1, fsr_next}; - 5: sfr_rd_data <= #1 porta_r; - 6: sfr_rd_data <= #1 portb_r; - 7: sfr_rd_data <= #1 portc_r; - endcase - - -/* -always @(posedge clk) - sfr_rd_data <= #1 sfr_rd_data_tmp1; - - -reg [3:0] sfr_sel; -wire [3:0] sfr_sel_src; - -assign sfr_sel_src = {src1_sel_[1],instr_0[2:0]}; - -always @(sfr_sel_src) - casex(sfr_sel_src) // synopsys full_case parallel_case - 4'b1_???: sfr_sel = 4'b01_11; - 4'b0_001: sfr_sel = 4'bxx_00; - 4'b0_010: sfr_sel = 4'b00_11; - 4'b0_011: sfr_sel = 4'bxx_01; - 4'b0_100: sfr_sel = 4'bxx_10; - 4'b0_101: sfr_sel = 4'b10_11; - 4'b0_11?: sfr_sel = 4'b11_11; - endcase - - -mux4_8 u1( .sel(sfr_sel[1:0]), .out(sfr_rd_data_tmp1), - .in0(tmr0_next), .in1(status_next), - .in2({1'b1, fsr_next}), .in3(sfr_rd_data_tmp2) ); - -mux4_8 u2( .sel(sfr_sel[3:2]), .out(sfr_rd_data_tmp2), - .in0(pc_r[7:0]), .in1(instr_0[7:0]), - .in2(porta_r), .in3(sfr_rd_data_tmp3) ); - -mux2_8 u2b( .sel(instr_0[0]), .out(sfr_rd_data_tmp3), - .in0(portb_r), .in1(portc_r) ); -*/ - -reg instd_zero; - -always @(posedge clk) - instd_zero <= #1 !(|inst_data[4:0]); - -// Register File Read Port -assign rf_rd_bnk = fsr_next[6:5]; -assign rf_rd_addr = instd_zero ? fsr_next[4:0] : instr_0[4:0]; - -// ALU OP -always @(posedge clk) - casex(instr_0) // synopsys full_case parallel_case - // Byte Oriented RF Operations - I_ADDWF: alu_op <= #1 ALU_ADD; // ADDWF - I_ANDWF: alu_op <= #1 ALU_AND; // ANDWF - I_CLRF: alu_op <= #1 ALU_CLR; // CLRF - I_CLRW: alu_op <= #1 ALU_CLR; // CLRW - I_COMF: alu_op <= #1 ALU_NOT; // COMF - I_DEC: alu_op <= #1 ALU_DEC; // DEC - I_DECFSZ: alu_op <= #1 ALU_DEC; // DECFSZ - I_INCF: alu_op <= #1 ALU_INC; // INCF - I_INCFSZ: alu_op <= #1 ALU_INC; // INCFSZ - I_IORWF: alu_op <= #1 ALU_IOR; // IORWF - I_MOV: alu_op <= #1 ALU_MOV; // MOV - I_MOVWF: alu_op <= #1 ALU_MOVW; // MOVWF - I_RLF: alu_op <= #1 ALU_RLF; // RLF - I_RRF: alu_op <= #1 ALU_RRF; // RRF - I_SUBWF: alu_op <= #1 ALU_SUB; // SUBWF - I_SWAPF: alu_op <= #1 ALU_SWP; // SWAPF - I_XORWF: alu_op <= #1 ALU_XOR; // XORWF - // Bit Oriented RF Operations - I_BCF: alu_op <= #1 ALU_BCF; // BCF - I_BSF: alu_op <= #1 ALU_BSF; // BSF - // Literal & Controll Operations - I_ANDLW: alu_op <= #1 ALU_AND; // ANDLW - I_IORLW: alu_op <= #1 ALU_IOR; // IORLW - I_MOVLW: alu_op <= #1 ALU_MOV; // MOWLW - I_RETLW: alu_op <= #1 ALU_MOV; // RETLW - I_XORLW: alu_op <= #1 ALU_XOR; // XORLW - endcase - - -// Source Select -// This CPU source 1 can be one of: rf (or sfr) or k, -// second source (if any) is always w -always @(instr_0) - casex(instr_0) // synopsys full_case parallel_case - I_ANDLW: src1_sel_ = K_SEL; - I_CALL: src1_sel_ = K_SEL; - I_GOTO: src1_sel_ = K_SEL; - I_IORLW: src1_sel_ = K_SEL; - I_MOVLW: src1_sel_ = K_SEL; - I_RETLW: src1_sel_ = K_SEL; - I_XORLW: src1_sel_ = K_SEL; - default: src1_sel_ = ( (instr_0[4:3]==2'h0) & (instr_0[2:0] != 3'h0 )) ? SFR_SEL : RF_SEL; - endcase - -always @(posedge clk) - src1_sel <= #1 src1_sel_[0]; - -// Destination Select -// Destination can be one of: rf, w, option, tris OR one of sfr registers: -// indf, tmr0, pc, status, fsr, porta, portb, portc, option, trisa, trisb, trisc -// Stage 1 -// select w, pc, rf or sfr -reg w_we1, w_we1_; - -always @(instr_0) - begin - casex(instr_0) // synopsys full_case parallel_case - I_ADDWF, I_ANDWF, I_COMF, I_DEC, - I_DECFSZ, I_INCF, I_INCFSZ, I_IORWF, - I_MOV, I_RLF, I_RRF, I_SUBWF, - I_SWAPF, I_XORWF: // w or f - w_we1_ = 1; - default: w_we1_ = 0; - endcase - end - -always @(instr_0) - begin - w_we_ = 0; - rf_we_ = 0; - sfr_we_ = 0; - tris_we_= 0; - casex(instr_0) // synopsys full_case parallel_case - - I_ADDWF, I_ANDWF, I_COMF, I_DEC, - I_DECFSZ, I_INCF, I_INCFSZ, I_IORWF, - I_MOV, I_RLF, I_RRF, I_SUBWF, - I_SWAPF, I_XORWF: // w or f - begin - rf_we_ = instr_0[5] & (instr_0[4] | instr_0[3]); - sfr_we_ = instr_0[5] & ~instr_0[4] & ~instr_0[3]; - end - - I_MOVWF, I_CLRF, I_BCF, I_BSF: // only f - begin - rf_we_ = instr_0[4] | instr_0[3]; - sfr_we_ = ~instr_0[4] & ~instr_0[3]; - end - - I_CLRW, I_IORLW, I_MOVLW, - I_ANDLW, I_RETLW, I_XORLW: w_we_ = 1; // only w - I_TRIS: tris_we_ = 1; // trisa or trisb or trisc - - endcase - end - -assign indf_we_ = sfr_we_ & (instr_0[2:0] == INDF_ADDR); -assign pc_we_ = sfr_we_ & (instr_0[2:0] == PCL_ADDR); - -// Stage 2 destination encoder -// write enable outputs are registered now -always @(posedge clk) w_we <= #1 w_we_; // working register write 0 enable - -always @(posedge clk) w_we1 <= #1 w_we1_; // working register write 1 enable - - -// Register File Write Enable is composed of thee conditions: 1) direct register writing (0x10-0x1f); -// 2) Direct Global Register writing (0x08-0x0f), and 3) Indirect Register File Writing -// The logic has been partitioned and balanced between the decode and execute stage ... -assign rf_we = rf_we1 | (rf_we2 & rf_we3); // register file write enable Composite - -always @(posedge clk) - rf_we1 <= #1 valid & rf_we_; // register file write enable 1 - -always @(posedge clk) - rf_we2 <= #1 valid & (fsr_next[4] | fsr_next[3]);// register file write enable 2 - -always @(posedge clk) - rf_we3 <= #1 indf_we_; // register file write enable 3 - -always @(posedge clk) - wdt_clr <= #1 instr_0[11:0] == I_CLRWDT; - - -always @(posedge clk) - opt_we <= #1 instr_0[11:0] == I_OPTION; - - -always @(posedge clk) - trisa_we <= #1 tris_we_ & (instr_0[2:0] == PORTA_ADDR); - -always @(posedge clk) - trisb_we <= #1 tris_we_ & (instr_0[2:0] == PORTB_ADDR); - -always @(posedge clk) - trisc_we <= #1 tris_we_ & (instr_0[2:0] == PORTC_ADDR); - -always @(posedge clk) - begin - // SFR registers - tmr0_we <= #1 sfr_we_ & (instr_0[2:0] == TMR0_ADDR); - pc_we <= #1 valid & pc_we_; - stat_we <= #1 valid & sfr_we_ & (instr_0[2:0] == STAT_ADDR); - fsr_we <= #1 valid & sfr_we_ & (instr_0[2:0] == FSR_ADDR); - porta_we <= #1 sfr_we_ & (instr_0[2:0] == PORTA_ADDR); - portb_we <= #1 sfr_we_ & (instr_0[2:0] == PORTB_ADDR); - portc_we <= #1 sfr_we_ & (instr_0[2:0] == PORTC_ADDR); - end - - -// Instructions that directly modify PC -always @(instr_0) - begin - pc_skz_ = 0; - pc_bset_ = 0; - pc_bclr_ = 0; - pc_call_ = 0; - pc_goto_ = 0; - pc_retlw_ = 0; - casex(instr_0) // synopsys full_case parallel_case - // Byte Oriented RF Operations - I_DECFSZ, - I_INCFSZ: pc_skz_ = 1; - // Bit Oriented RF Operations - I_BTFSS: pc_bset_ = 1; - I_BTFSC: pc_bclr_ = 1; - // Literal & Controll Operations - I_CALL: pc_call_ = 1; - I_GOTO: pc_goto_ = 1; - I_RETLW: pc_retlw_ = 1; - endcase - end - -always @(posedge clk) - begin - pc_skz <= #1 valid & pc_skz_; - pc_bset <= #1 valid & pc_bset_; - pc_bclr <= #1 valid & pc_bclr_; - pc_call <= #1 valid & pc_call_; - pc_goto <= #1 valid & pc_goto_; - pc_retlw <= #1 valid & pc_retlw_; - end - -assign invalidate_0_ = (pc_call_ | pc_goto_ | pc_retlw_ | pc_we_); - -always @(posedge clk) - invalidate_0 <= #1 invalidate_0_; - -// Status bits WE -always @(posedge clk) - begin - stat_bwe <= #1 0; - if(valid) - casex(instr_0) // synopsys full_case parallel_case - // Byte Oriented RF Operations - I_ADDWF: stat_bwe <= #1 STAT_WR_C | STAT_WR_DC | STAT_WR_Z; - I_ANDWF: stat_bwe <= #1 STAT_WR_Z; - I_CLRF: stat_bwe <= #1 STAT_WR_Z; - I_CLRW: stat_bwe <= #1 STAT_WR_Z; - I_COMF: stat_bwe <= #1 STAT_WR_Z; - I_DEC: stat_bwe <= #1 STAT_WR_Z; - I_INCF: stat_bwe <= #1 STAT_WR_Z; - I_IORWF: stat_bwe <= #1 STAT_WR_Z; - I_MOV: stat_bwe <= #1 STAT_WR_Z; - I_RLF: stat_bwe <= #1 STAT_WR_C; - I_RRF: stat_bwe <= #1 STAT_WR_C; - I_SUBWF: stat_bwe <= #1 STAT_WR_C | STAT_WR_DC | STAT_WR_Z; - I_XORWF: stat_bwe <= #1 STAT_WR_Z; - // Literal & Controll Operations - I_ANDLW: stat_bwe <= #1 STAT_WR_Z; - //I_CLRWDT: // Modifies TO & PD *** FIX ME *** - I_IORLW: stat_bwe <= #1 STAT_WR_Z; - //I_SLEEP: // Modifies TO & PD *** FIX ME *** - I_XORLW: stat_bwe <= #1 STAT_WR_Z; - endcase - end - -//////////////////////////////////////////////////////////////////////// -// Wr & Execute Logic (including PC) -// Second Pipeline Stage -//////////////////////////////////////////////////////////////////////// - -// Source OP Sel -//assign src1 = src1_sel ? rf_rd_data : sfr_rd_data; -mux2_8 u3( .sel(src1_sel), .in0(sfr_rd_data), .in1(rf_rd_data), .out(src1) ); - -alu u4( .s1( src1 ), - .s2( w ), - .mask( mask ), - .out( dout ), - .op( alu_op ), - .c_in( status[0] ), - .c( c_out ), - .dc( dc_out ), - .z( z_out ) - ); - -// Register file connections -assign rf_wr_bnk = fsr[6:5]; -assign rf_wr_addr = (instr_1[4:0]==0) ? fsr[4:0] : instr_1[4:0]; -assign rf_wr_data = dout; - -wire [7:0] status_next2; - -// Deal with all special registers (SFR) writes -/* -always @(rst or status or stat_we or stat_bwe or dout or c_out or dc_out or z_out) - if(rst) status_next = STAT_RST_VALUE; - else - begin - status_next = status; // Default Keep Value - if(stat_we) status_next = dout | 8'h18; - else - begin - if(stat_bwe[0]) status_next[0] = c_out; - if(stat_bwe[1]) status_next[1] = dc_out; - if(stat_bwe[2]) status_next[2] = z_out; - end - end -*/ - -assign status_next2[0] = stat_bwe[0] ? c_out : status[0]; -assign status_next2[1] = stat_bwe[1] ? dc_out : status[1]; -assign status_next2[2] = stat_bwe[2] ? z_out : status[2]; - -mux2_8 u21( .sel(stat_we), .in1( {dout | 8'h18} ), .in0( {status[7:3],status_next2[2:0]} ), .out(status_next) ); - -always @(posedge clk) - if(rst) status <= #1 STAT_RST_VALUE; - else status <= #1 status_next; - -//assign fsr_next = fsr_we ? dout[6:0] : fsr; - -mux2_7 u31( .sel(fsr_we), .in1(dout[6:0]), .in0(fsr), .out(fsr_next) ); - -always @(posedge clk) - if(rst) fsr <= #1 FSR_RST_VALUE; - else fsr <= #1 fsr_next; - -always @(posedge clk) - if(valid_1 & (w_we | (w_we1 & ~instr_1[5])) ) w <= #1 dout; - -always @(posedge clk) - if(rst) trisa <= #1 TRIS_RST_VALUE; - else - if(trisa_we & valid_1) trisa <= #1 w; - -always @(posedge clk) - if(rst) trisb <= #1 TRIS_RST_VALUE; - else - if(trisb_we & valid_1) trisb <= #1 w; - -always @(posedge clk) - if(rst) trisc <= #1 TRIS_RST_VALUE; - else - if(trisc_we & valid_1) trisc <= #1 w; - -always @(posedge clk) - if(rst) option <= #1 OPT_RST_VALUE; - else - if(opt_we & valid_1) option <= #1 w[5:0]; - -always @(posedge clk) - if(porta_we & valid_1) portaout <= #1 dout; - -always @(posedge clk) - if(portb_we & valid_1) portbout <= #1 dout; - -always @(posedge clk) - if(portc_we & valid_1) portcout <= #1 dout; - -always @(posedge clk) - begin - porta_r <= #1 portain; - portb_r <= #1 portbin; - portc_r <= #1 portcin; - end - -/////////////////////////////////////////////////////////////////////// -// Timer Logic - -//assign tmr0_next = tmr0_we ? dout : tmr0_cnt_en ? tmr0_plus_1 : tmr0; -//assign tmr0_next = tmr0_we ? dout : tmr0_cnt_en ? (tmr0 + 1) : tmr0; - - -mux2_8 u5( .sel(tmr0_we & valid_1), - .in0(tmr0_next1), .in1(dout), - .out(tmr0_next) ); -mux2_8 u6( .sel(tmr0_cnt_en), - .in0(tmr0), .in1(tmr0_plus_1), - .out(tmr0_next1) ); - -inc8 u7( .in(tmr0), .out(tmr0_plus_1) ); - -always @(posedge clk) - tmr0 <= #1 tmr0_next; - -presclr_wdt u8( .clk( clk ), - .rst( rst ), - .tcki( tcki ), - .option( option[5:0] ), - .tmr0_we( tmr0_we & valid_1 ), - .tmr0_cnt_en( tmr0_cnt_en ), - .wdt_en( wdt_en ), - .wdt_clr( wdt_clr & valid_1 ), - .wdt_to( wdt_to ) - ); - - -//////////////////////////////////////////////////////////////////////// -// Programm Counter Logic - -always @(posedge clk) - pc_r2 <= #1 pc_r; - -// 'inst_addr' is a duplication of the 'pc'. The only time when it is really needed -// is when the program memory is not on the chip and we want to place the registers -// directly in the IO pads to reduce Tcq (For example in a Xilinx FPGA implementation). -// If the program memory is on the chip or if the implmentation allows feedback from -// registers in the IO cells, this is not needed. Synopsys FPGA compiler appears to -// make the correct decission either way, and gett rid of unneded logic ... - -always @(posedge clk) - if(rst) inst_addr <= #1 PC_RST_VECTOR; - else inst_addr <= #1 pc_next; - -always @(posedge clk) - if(rst) pc <= #1 PC_RST_VECTOR; - else pc <= #1 pc_next; - -/* -always @(pc_plus_1 or dout or pc_we or status or stack_out or - pc_call or pc_goto or pc_retlw or instr_1) - if(pc_we) pc_next = {status[6:5], 1'b0, dout}; - else - if(!pc_call & !pc_goto & !pc_retlw) pc_next = pc_plus_1; - else - if(pc_call) pc_next = {status[6:5], 1'b0, instr_1[7:0]}; - else - if(pc_goto) pc_next = {status[6:5], instr_1[8:0]}; - else - if(pc_retlw) pc_next = stack_out; -*/ - - -wire [10:0] pc_tmp1, pc_tmp2, pc_tmp3; -wire pc_sel1; - -assign pc_tmp1 = {status[6:5], 1'b0, dout[7:0]}; -assign pc_tmp2 = {status[6:5], 1'b0, instr_1[7:0]}; -assign pc_tmp3 = {status[6:5], instr_1[8:0]}; -assign pc_sel1 = (!pc_call & !pc_goto & !pc_retlw); - -mux2_11 u9 ( .sel(pc_we), .in0(pc_next1), .in1(pc_tmp1), .out(pc_next) ); -mux2_11 u10( .sel(pc_sel1), .in0(pc_next2), .in1(pc_plus_1), .out(pc_next1) ); -mux2_11 u11( .sel(pc_call), .in0(pc_next3), .in1(pc_tmp2), .out(pc_next2) ); -mux2_11 u12( .sel(pc_goto), .in0(stack_out), .in1(pc_tmp3), .out(pc_next3) ); - - -inc11 u13( .in(pc), .out(pc_plus_1) ); - -reg invalidate_1_r1, invalidate_1_r2; - -assign invalidate_1 = (pc_skz & z_out) | (pc_bset & bit_sel) | - (pc_bclr & !bit_sel) | (invalidate_0 & valid_1) | invalidate_1_r1; - - -always @(posedge clk) - begin - invalidate_1_r1 <= #1 (invalidate_0 & valid_1) | invalidate_1_r2; - invalidate_1_r2 <= #1 (invalidate_0 & valid_1); - end - -//assign bit_sel = src1[ instr_1[7:5] ]; -mux8_1 u22( .sel(instr_1[7:5]), .in(src1), .out(bit_sel) ); - -sfifo4x11 u14( .clk(clk), .push(pc_call), .din(pc_r2), .pop(pc_retlw), .dout(stack_out) ); - -endmodule Index: trunk/verilog/core/risc_core_top.v =================================================================== --- trunk/verilog/core/risc_core_top.v (revision 6) +++ trunk/verilog/core/risc_core_top.v (nonexistent) @@ -1,186 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// Mini-RISC-1 //// -//// Mini-Risc Core Top Levcel //// -//// //// -//// //// -//// Author: Rudolf Usselmann //// -//// rudi@asics.ws //// -//// //// -//// //// -//// D/L from: http://www.opencores.org/cores/minirisc/ //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000-2002 Rudolf Usselmann //// -//// www.asics.ws //// -//// rudi@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: risc_core_top.v,v 1.3 2002-10-01 12:44:24 rudi Exp $ -// -// $Date: 2002-10-01 12:44:24 $ -// $Revision: 1.3 $ -// $Author: rudi $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: not supported by cvs2svn $ -// Revision 1.2 2002/09/27 15:35:40 rudi -// Minor update to newer devices ... -// -// -// -// -// -// -// -// -// -// -// - -`timescale 1ns / 10ps - -module mrisc_top( - clk, rst_in, - porta, portb, portc, - tcki, - wdt_en ); // synthesis syn_useioff=1 syn_hier="flatten,remove" - -// Basic Core I/O. -input clk; -input rst_in; - -// I/O Ports -inout [7:0] porta; -inout [7:0] portb; -inout [7:0] portc; - -input tcki; -input wdt_en; - -//////////////////////////////////////////////////////////////////////// -// -// Local Wires -// - -wire [10:0] inst_addr; -wire [11:0] inst_data; - -wire [7:0] portain; -wire [7:0] portbin; -wire [7:0] portcin; - -wire [7:0] portaout; -wire [7:0] portbout; -wire [7:0] portcout; - -wire [7:0] trisa; -wire [7:0] trisb; -wire [7:0] trisc; - -//////////////////////////////////////////////////////////////////////// -// -// IO Buffers -// - -assign porta[0] = trisa[0] ? 1'bz : portaout[0]; -assign porta[1] = trisa[1] ? 1'bz : portaout[1]; -assign porta[2] = trisa[2] ? 1'bz : portaout[2]; -assign porta[3] = trisa[3] ? 1'bz : portaout[3]; -assign porta[4] = trisa[4] ? 1'bz : portaout[4]; -assign porta[5] = trisa[5] ? 1'bz : portaout[5]; -assign porta[6] = trisa[6] ? 1'bz : portaout[6]; -assign porta[7] = trisa[7] ? 1'bz : portaout[7]; - -assign portb[0] = trisb[0] ? 1'bz : portbout[0]; -assign portb[1] = trisb[1] ? 1'bz : portbout[1]; -assign portb[2] = trisb[2] ? 1'bz : portbout[2]; -assign portb[3] = trisb[3] ? 1'bz : portbout[3]; -assign portb[4] = trisb[4] ? 1'bz : portbout[4]; -assign portb[5] = trisb[5] ? 1'bz : portbout[5]; -assign portb[6] = trisb[6] ? 1'bz : portbout[6]; -assign portb[7] = trisb[7] ? 1'bz : portbout[7]; - -assign portc[0] = trisc[0] ? 1'bz : portcout[0]; -assign portc[1] = trisc[1] ? 1'bz : portcout[1]; -assign portc[2] = trisc[2] ? 1'bz : portcout[2]; -assign portc[3] = trisc[3] ? 1'bz : portcout[3]; -assign portc[4] = trisc[4] ? 1'bz : portcout[4]; -assign portc[5] = trisc[5] ? 1'bz : portcout[5]; -assign portc[6] = trisc[6] ? 1'bz : portcout[6]; -assign portc[7] = trisc[7] ? 1'bz : portcout[7]; - -assign portain = porta; -assign portbin = portb; -assign portcin = portc; - -//////////////////////////////////////////////////////////////////////// -// -// Mini Risc Core -// - -mrisc u0( - clk, - rst_in, - - inst_addr, - inst_data, - - portain, - portbin, - portcin, - - portaout, - portbout, - portcout, - - trisa, - trisb, - trisc, - - tcki, - wdt_en ); - - -//////////////////////////////////////////////////////////////////////// -// -// Program memory -// - -generic_spram #(11,12) imem( - .clk( clk ), - .rst( rst_in ), - .ce( 1'b1 ), - .we( 1'b0 ), - .oe( 1'b1 ), - .addr( inst_addr ), - .di( 12'h0 ), - .do( inst_data ) - ); - -endmodule Index: trunk/verilog/core/primitives.v =================================================================== --- trunk/verilog/core/primitives.v (revision 6) +++ trunk/verilog/core/primitives.v (nonexistent) @@ -1,218 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// Mini-RISC-1 //// -//// Primitives //// -//// //// -//// //// -//// Author: Rudolf Usselmann //// -//// rudi@asics.ws //// -//// //// -//// //// -//// D/L from: http://www.opencores.org/cores/minirisc/ //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000-2002 Rudolf Usselmann //// -//// www.asics.ws //// -//// rudi@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: primitives.v,v 1.3 2002-10-01 12:44:24 rudi Exp $ -// -// $Date: 2002-10-01 12:44:24 $ -// $Revision: 1.3 $ -// $Author: rudi $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: not supported by cvs2svn $ -// Revision 1.2 2002/09/27 15:35:40 rudi -// Minor update to newer devices ... -// -// -// -// -// -// -// -// -// -// -// - -`timescale 1ns / 10ps - -// Mux 4:1 8 bits wide -module mux4_8(sel, in0, in1, in2, in3, out); -input [1:0] sel; -input [7:0] in0, in1, in2, in3; -output [7:0] out; - -reg [7:0] out; - -always @(sel or in0 or in1 or in2 or in3) - case(sel) // synopsys full_case parallel_case - 0: out = in0; - 1: out = in1; - 2: out = in2; - 3: out = in3; - endcase - -endmodule - -// 8 bit comparator -module cmp8_eq(a,b,eq); -input [7:0] a,b; -output eq; - -assign eq = (a==b); - -endmodule - -// MUX 2:1 7 bits wide -module mux2_7(sel, in0, in1, out); -input sel; -input [6:0] in0, in1; -output [6:0] out; - -assign out = sel ? in1 : in0; - -endmodule - -// Mux 8:1 1 bit wide -module mux8_1( sel, in, out); -input [2:0] sel; -input [7:0] in; -output out; - -assign out = in[sel]; - -endmodule - -// Mux 2:1 8 bits wide -module mux2_8(sel, in0, in1, out); -input sel; -input [7:0] in0, in1; -output [7:0] out; - -assign out = sel ? in1 : in0; - -endmodule - -// Mux 8:1 8 bits wide -module mux8_8(sel, in0, in1, in2, in3, in4, in5, in6, in7, out); -input [2:0] sel; -input [7:0] in0, in1, in2, in3, in4, in5, in6, in7; -output [7:0] out; - -reg [7:0] out; - -always @(sel or in0 or in1 or in2 or in3 or in4 or in5 or in6 or in7) - case(sel) // synopsys full_case parallel_case - 3'd0: out = in0; - 3'd1: out = in1; - 3'd2: out = in2; - 3'd3: out = in3; - 3'd4: out = in4; - 3'd5: out = in5; - 3'd6: out = in6; - 3'd7: out = in7; - endcase - -endmodule - -// Mux 2:1 11 bits wide -module mux2_11(sel, in0, in1, out); -input sel; -input [10:0] in0, in1; -output [10:0] out; - -assign out = sel ? in1 : in0; - -endmodule - - -// 8bit Add/Sub with carry/borrow out -module add_sub8_co(sub, opa, opb, out, co); -input sub; -input [7:0] opa, opb; -output [7:0] out; -output co; - -assign {co, out} = sub ? (opa - opb) : (opa + opb); - -endmodule - -// 11 bit incrementer -module inc11(in, out); -input [10:0] in; -output [10:0] out; - -assign out = in + 11'h1; - -endmodule - -// 8 bit incrementer -module inc8(in, out); -input [7:0] in; -output [7:0] out; - -assign out = in + 8'h1; - -endmodule - -// A Basic Synchrounous FIFO (4 entries deep) -module sfifo4x11(clk, push, din, pop, dout); -input clk; -input push; -input [10:0] din; -input pop; -output [10:0] dout; - -reg [10:0] stack1, stack2, stack3, stack4; - -assign dout = stack1; - -always @(posedge clk) - begin - if(push) // PUSH stack - begin - stack4 <= #1 stack3; - stack3 <= #1 stack2; - stack2 <= #1 stack1; - stack1 <= #1 din; - end - if(pop) // POP stack - begin - stack1 <= #1 stack2; - stack2 <= #1 stack3; - stack3 <= #1 stack4; - end - end - -endmodule - - Index: trunk/verilog/testbench/prog_mem.v =================================================================== --- trunk/verilog/testbench/prog_mem.v (revision 6) +++ trunk/verilog/testbench/prog_mem.v (nonexistent) @@ -1,89 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// Mini-RISC-1 //// -//// Program Memory //// -//// //// -//// //// -//// Author: Rudolf Usselmann //// -//// rudi@asics.ws //// -//// //// -//// //// -//// D/L from: http://www.opencores.org/cores/minirisc/ //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000-2002 Rudolf Usselmann //// -//// www.asics.ws //// -//// rudi@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: prog_mem.v,v 1.2 2002-09-27 15:35:41 rudi Exp $ -// -// $Date: 2002-09-27 15:35:41 $ -// $Revision: 1.2 $ -// $Author: rudi $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: not supported by cvs2svn $ -// -// -// -// -// -// -// -// -// -// - -`timescale 1ns / 10ps - -// For simulation only -// May be off or on chip - -module prog_mem ( clk, address, we, din, dout ); - -input clk; -input [10:0] address; -input we; -input [11:0] din; -output [11:0] dout; - -parameter depth = 2048; - -reg [10:0] addr_r; -reg [11:0] mem[0:depth-1]; - -always @(posedge clk) - addr_r <= address; - -assign dout = mem[addr_r]; - -always @(posedge clk) - if (we) mem[address] <= din; - -endmodule Index: trunk/verilog/testbench/test.v =================================================================== --- trunk/verilog/testbench/test.v (revision 6) +++ trunk/verilog/testbench/test.v (nonexistent) @@ -1,329 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// Test Bench //// -//// //// -//// //// -//// Author: Rudolf Usselmann //// -//// rudi@asics.ws //// -//// //// -//// //// -//// D/L from: http://www.opencores.org/cores/minirisc/ //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000-2002 Rudolf Usselmann //// -//// www.asics.ws //// -//// rudi@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: test.v,v 1.1 2002-09-27 15:35:41 rudi Exp $ -// -// $Date: 2002-09-27 15:35:41 $ -// $Revision: 1.1 $ -// $Author: rudi $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: not supported by cvs2svn $ -// -// -// -// -// -// -// -// -// -// - -`timescale 1ns / 10ps - -module test; - -reg clk; -reg reset; -reg tcki; - -// Declare I/O Port connections -wire [7:0] porta; // I/O Port A -wire [7:0] portb; // I/O Port B -wire [7:0] portc; // I/O Port C - -wire [7:0] portain; -wire [7:0] portbin; -wire [7:0] portcin; - -wire [7:0] portaout; -wire [7:0] portbout; -wire [7:0] portcout; - -wire [7:0] trisa; -wire [7:0] trisb; -wire [7:0] trisc; - -// Declare ROM and rom signals -wire [10:0] inst_addr; -wire [11:0] inst_data; - - -always #10 clk = ~clk; -always #20 tcki = ~tcki; - -// Instantiate one CPU to be tested. -mrisc u0( - .clk (clk), - .rst_in (reset), - .inst_addr (inst_addr), - .inst_data (inst_data), - - .portain (portain), - .portbin (portbin), - .portcin (portcin), - - .portaout (portaout), - .portbout (portbout), - .portcout (portcout), - - .trisa (trisa), - .trisb (trisb), - .trisc (trisc), - - .tcki (tcki), - .wdt_en (1'b1) - - ); - -// IO buffers for IO Ports -assign porta = trisa ? 8'bz : portaout; -assign portain = porta; - -assign portb = trisb ? 8'bz : portbout; -assign portbin = portb; - -assign portc = trisc ? 8'bz : portcout; -assign portcin = portc; - -// Pullups for IO Ports -pullup ua0(porta[0]); -pullup ua1(porta[1]); -pullup ua2(porta[2]); -pullup ua3(porta[3]); -pullup ua4(porta[4]); -pullup ua5(porta[5]); -pullup ua6(porta[6]); -pullup ua7(porta[7]); - -pullup ub0(portb[0]); -pullup ub1(portb[1]); -pullup ub2(portb[2]); -pullup ub3(portb[3]); -pullup ub4(portb[4]); -pullup ub5(portb[5]); -pullup ub6(portb[6]); -pullup ub7(portb[7]); - -pullup uc0(portc[0]); -pullup uc1(portc[1]); -pullup uc2(portc[2]); -pullup uc3(portc[3]); -pullup uc4(portc[4]); -pullup uc5(portc[5]); -pullup uc6(portc[6]); -pullup uc7(portc[7]); - - -// Instantiate the Program RAM. -prog_mem u1 ( - .clk (clk), - .address (inst_addr), - .we (1'b0), // This testbench doesn't allow writing to PRAM - .din (12'b000000000000), // This testbench doesn't allow writing to PRAM - .dout (inst_data) -); - -// This is the only initial block in the test module and this is where -// you select what test you want to do. - -initial - begin - $display ("\n\nMini-RISC. Version 1.0\n\n"); - - //$dumpfile ("mini-risc.vcd"); - //$dumpvars (0, test); - - clk = 0; - tcki = 0; - - sanity1; - - $readmemh ("../scode/sanity2.rom", u1.mem); run_code("Sanity 2 "); - - $readmemh ("../scode/rf1.rom", u1.mem); run_code("Register File 1 "); - - $readmemh ("../scode/rf2.rom", u1.mem); run_code("Register File 2 "); - - $readmemh ("../scode/rf3.rom", u1.mem); run_code("Register File 3 "); - - //$readmemh ("scode/tmr_wdt.rom", u1.mem); run_code("Timer / WDT "); - - //$dumpflush; - $finish; - end - - -task sanity1; - -`define GOOD 12'h0aa -`define BAD 12'h0af -`define SANITY1 "../scode/sanity1.rom" - - begin - $display ("========== Starting Sanity 1 Test ========== \n"); - reset = 1; - repeat(10) @(posedge clk); - reset = 0; - - //$display ("Loading program memory with %s", `SANITY1); - $readmemh (`SANITY1, u1.mem); - while(inst_addr != `GOOD & inst_addr != `BAD) @(posedge clk); - - if(inst_addr == `GOOD) - begin - $display("Sanity1 test PASSED !!!"); - end - else - if(inst_addr == `BAD) - begin - $display("Sanity1 test FAILED !!!"); - end - else - $display("Sanity1 test status UNKNOWN !!!"); - - - repeat(4) @(posedge clk); - $display("=============================================\n\n\n"); - - end -endtask - -task run_code; -input [16*8-1:0] str; - - - begin - $display ("========== Starting %s Test ========== \n",str); - reset = 1; - repeat(10) @(posedge clk); - reset = 0; - - //$display ("Loading program memory with %s", `SANITY2); - //$readmemh (`SANITY2, u1.mem); - - repeat(10) @(posedge clk); - while(porta == 8'h00) @(posedge clk); - - - if(porta == 8'h01) - begin - $display("Test %s PASSED !!!",str); - end - else - if(porta == 8'hff) - begin - $display("Test %s FAILED in test %d !!!", str, portb); - end - else - $display("Test %s status UNKNOWN (%h test: %d) !!!", str, porta, portb); - - - repeat(4) @(posedge clk); - $display("\n=============================================\n\n\n"); - - end -endtask - -/* -always @(posedge clk) - if(!reset) - begin - if( |u0.w ===1'bx ) $display("%t: Warning :W went unknown",$time); - if( |u0.pc ===1'bx ) $display("%t: Warning :PC went unknown",$time); - if( |u0.status ===1'bx ) $display("%t: Warning :STATUS went unknown",$time); - end -*/ - -reg [8*8-1:0] inst_string; - -always @(inst_data) begin - casex (inst_data) - 12'b0000_0000_0000: inst_string = "NOP "; - 12'b0000_001X_XXXX: inst_string = "MOVWF "; - 12'b0000_0100_0000: inst_string = "CLRW "; - 12'b0000_011X_XXXX: inst_string = "CLRF "; - 12'b0000_10XX_XXXX: inst_string = "SUBWF "; - 12'b0000_11XX_XXXX: inst_string = "DECF "; - 12'b0001_00XX_XXXX: inst_string = "IORWF "; - 12'b0001_01XX_XXXX: inst_string = "ANDWF "; - 12'b0001_10XX_XXXX: inst_string = "XORWF "; - 12'b0001_11XX_XXXX: inst_string = "ADDWF "; - 12'b0010_00XX_XXXX: inst_string = "MOVF "; - 12'b0010_01XX_XXXX: inst_string = "COMF "; - 12'b0010_10XX_XXXX: inst_string = "INCF "; - 12'b0010_11XX_XXXX: inst_string = "DECFSZ "; - 12'b0011_00XX_XXXX: inst_string = "RRF "; - 12'b0011_01XX_XXXX: inst_string = "RLF "; - 12'b0011_10XX_XXXX: inst_string = "SWAPF "; - 12'b0011_11XX_XXXX: inst_string = "INCFSZ "; - - // *** Bit-Oriented File Register Operations - 12'b0100_XXXX_XXXX: inst_string = "BCF "; - 12'b0101_XXXX_XXXX: inst_string = "BSF "; - 12'b0110_XXXX_XXXX: inst_string = "BTFSC "; - 12'b0111_XXXX_XXXX: inst_string = "BTFSS "; - - // *** Literal and Control Operations - 12'b0000_0000_0010: inst_string = "OPTION "; - 12'b0000_0000_0011: inst_string = "SLEEP "; - 12'b0000_0000_0100: inst_string = "CLRWDT "; - 12'b0000_0000_0101: inst_string = "TRIS "; - 12'b0000_0000_0110: inst_string = "TRIS "; - 12'b0000_0000_0111: inst_string = "TRIS "; - 12'b1000_XXXX_XXXX: inst_string = "RETLW "; - 12'b1001_XXXX_XXXX: inst_string = "CALL "; - 12'b101X_XXXX_XXXX: inst_string = "GOTO "; - 12'b1100_XXXX_XXXX: inst_string = "MOVLW "; - 12'b1101_XXXX_XXXX: inst_string = "IORLW "; - 12'b1110_XXXX_XXXX: inst_string = "ANDLW "; - 12'b1111_XXXX_XXXX: inst_string = "XORLW "; - - default: inst_string = "-XXXXXX-"; - endcase - //$display("Executing[%h] %s",inst_addr, inst_string); -end - - -endmodule - Index: trunk/xilinx_primitives.zip =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/xilinx_primitives.zip =================================================================== --- trunk/xilinx_primitives.zip (revision 6) +++ trunk/xilinx_primitives.zip (nonexistent)

trunk/xilinx_primitives.zip Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/sim/run =================================================================== --- trunk/sim/run (revision 6) +++ trunk/sim/run (nonexistent) @@ -1,16 +0,0 @@ -#!/bin/csh - -ncverilog \ - +define+TEST_BENCH \ - \ - ../verilog/core/alu.v \ - ../verilog/core/presclr_wdt.v \ - ../verilog/core/risc_core.v \ - ../verilog/core/primitives.v \ - ../verilog/core/register_file.v \ - ../verilog/core/risc_core_top.v \ - ../verilog/testbench/prog_mem.v \ - ../verilog/testbench/test.v \ - \ - ../../generic_memories/rtl/verilog/generic_spram.v \ - ../../generic_memories/rtl/verilog/generic_dpram.v

trunk/sim/run Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/README.txt =================================================================== --- trunk/README.txt (revision 6) +++ trunk/README.txt (nonexistent) @@ -1,120 +0,0 @@ - -This is a Mini-RISC CPU/Microcontroller that is mostly compatible with the -PIC 16C57 from Microchip. - - -Legal -===== - -PIC, Microship, etc. are Trademarks of Microchip Technology Inc. - -I have no idea if implementing this core will or will not violate -patents, copyrights or cause any other type of lawsuits. - -I provide this core AS IS, without any warrenties. If you decide to -build this core, you are responsible for any legal resolutions, such -as patents and copyrights, and perhaps others .... - - This source file(s) may be used and distributed without - restriction provided that this copyright statement is not - removed from the file and that any derivative work contains - the original copyright notice and the associated disclaimer. - - THIS SOURCE FILE(S) IS/ARE PROVIDED "AS IS" AND WITHOUT ANY - EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT - LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND - FITNESS FOR A PARTICULAR PURPOSE. - - -Motivation -========== - -After seeing the "free_risc8" on the free-ip web site, I got excited -and downloaded the core. Pretty soon I found out that it had many -many errors and omissions from the original 16C57. So I started looking -at the code. This is when I realized it was very badly designed and -could not be made run faster. So, I sat down and wrote my own PIC IP -core last night. A lot of work was spend in writing test code to ensure -that it was 100% compatible from the software point of view. - -- A PIC compatible Microcontroller that runs a lot faster -- Separate (External to the core) Program Memory -- Options to extend the core - - -Compatibility -============= - -This design should be fully software compatible to the Microchip Implementation -of the PIC 16C57, except for the following extensions: - -- Port A is full 8 bits wide -- Hardware stack is 4 level deep [original 2 levels] (can be easily expanded) -- Executions of instructions that modify the PC has become a lot more expensive - due to the pipeline and execution of instructions on every cycle. - Any instruction that writes to the PC (PC as destination (f), call, goto, retlw) - now takes 4 cycles to execute (instead of 2 in the origianl implementation). - The 4 'skip' instructions, remain as in the original implmentation: 1 cycle - if not skipped, 2 cycles if skipped. -- Sampling of IO ports might be off -- Timer and watchdog might be off a few cycles - - -Performance -=========== - -- Single cycle instruction execution, except as noted above. -- Here are results of some sample implementations: - - Xilinx Spartan 2e ((Device: xc2s50e-6): Fmax: 80Mhz, Utilization: 30% - - Xilinx Spartan2 (Device: xc2s30-6-cs144): Fmax: 50Mhz, Utilization: 66%, Ports: Tsu: 2.2nS, Tcq: 7.7nS - - Xilinx Virtex (Device: xcv50-4-cs144) : Fmax: 40Mhz, Utilization: 35%, Ports: Tsu: 3.0nS, Tcq: 6.2nS - - Xilinx VirtexE (Device: xcv50e-8-cs144): Fmax: 66Mhz, Utilization: 35%, Ports: Tsu: 1.7nS, Tcq: 4.5nS - Half of the cycle time is spend in routing delays. My guess is that by placing - proper locatiuon contrains and guiding the back-end tools, a significant - speed improvement can be achieved .... -- I estimat about 25K gates with the xilinx primitives, (excluding Register - File and Programm Memory). - -Implementing the core -===================== - -The only file you should edit if you really want to implement this core, is the -'primitives.v' file. It contains all parts that can be optimized, depending on -the technology used. It includes memories, and arithmetic modules. -I added a primitives_xilinx,v file and xilinx_primitives.zip which contain -primitives for xilinx. -'risc_core.v' is the top level without program memory and tristate Io buffers for ports. -This is probably a good starting point if you want to instantiate the core in to a larger -design. If you just want a PIC clone, take a loot at 'risc_core_top.v', it was written -with Xilinx FPGAs in mind, but should be easily addaptred to other vendors FPGAs - just -replace the memory blocks ... - -To-Do -===== - -Things that need to be done - -1) Write more test/compliance test vectors - - Verify that all instructions after a goto/call/retlw/write to PCL are not executed - - Verify ALU - - Timer and Watchdog tests - - Perhaps some other ereas ? - -2) Extensions ? - - I guess this is on a "as needed" basis - - A friend suggested to add registers that can be shared by two or more cores in a MP type configuration - -Author -====== - -I have been doing ASIC design, verification and synthesis for over 15 years. -This core is only a "mid-night hack", and should used with caution. - -I'd also like to know if anyone will actually use this core. Please send me a -note if you will ! - -Rudolf Usselmann -russelmann@hotmail.com - -Feel free to send me comments, suggestions and bug reports. - Index: trunk/scode/tmr_wdt.asm =================================================================== --- trunk/scode/tmr_wdt.asm (revision 6) +++ trunk/scode/tmr_wdt.asm (nonexistent) @@ -1,155 +0,0 @@ -;///////////////////////////////////////////////////////////////////// -;//// //// -;//// Mini-RISC-1 //// -;//// Timer / Wachdog //// -;//// Tests Timer / Wachdog //// -;//// //// -;//// Author: Rudolf Usselmann //// -;//// russelmann@hotmail.com //// -;//// //// -;///////////////////////////////////////////////////////////////////// -;//// //// -;//// Copyright (C) 2000 Rudolf Usselmann //// -;//// russelmann@hotmail.com //// -;//// //// -;//// This source file may be used and distributed without //// -;//// restriction provided that this copyright statement is not //// -;//// removed from the file and that any derivative work contains //// -;//// the original copyright notice and the associated disclaimer.//// -;//// //// -;//// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY //// -;//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT //// -;//// LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND //// -;//// FITNESS FOR A PARTICULAR PURPOSE. //// -;//// //// -;///////////////////////////////////////////////////////////////////// - - list p=16c57 - #include p16c5x.inc - -; global Registers -r0 equ 0x8 -r1 equ 0x9 -r2 equ 0xa -r3 equ 0xb -r4 equ 0xc -r5 equ 0xd -r6 equ 0xe -r7 equ 0xf - -; banked Registers -br0 equ 0x10 -br1 equ 0x11 -br2 equ 0x12 -br3 equ 0x13 -br4 equ 0x14 -br5 equ 0x15 -br6 equ 0x16 -br7 equ 0x17 -br8 equ 0x18 -br9 equ 0x19 -br10 equ 0x1a -br11 equ 0x1b -br12 equ 0x1c -br13 equ 0x1d -br14 equ 0x1e -br15 equ 0x1f - - -; PORTB Indicates Test Number -; PORTA Indicates Status: 0 - Running; 1 - done OK; ff - stoped on error - -main ; Main code entry - ; Port IO Test - ; All ports have a Pull up resistor - - ; SETUP all ports - clrw - movwf FSR - movwf PORTA - movwf PORTB - movwf PORTC - tris PORTA - tris PORTB - tris PORTC - - ; --------------------------------------- - ; ---- Test RMW on Register fil ---- - ; --------------------------------------- - - movlw 0x01 ; TEST 1 - movwf PORTB ; Set Test Number - - movlw 0x00 - option - movwf TMR0 - clrwdt - nop - nop - nop - nop - - clrw - movwf r1 - -loop2 ; repeat 256 times - clrw - movwf r0 - - - ; repeat 256 times -loop1 - movfw TMR0 - decfsz r0,F - goto loop1 - - decfsz r1,F - goto loop2 - - - - nop - nop - nop - nop - nop - nop - - clrw - movwf TMR0 - clrwdt - - nop - nop - nop - nop - movlw 0x01 - movwf PORTA - nop - nop - nop - nop -good ; Loop in good on success - goto good - nop - nop - nop - nop - -lerr - movlw 0xff - movwf PORTA - - nop - nop - nop - nop -lerr_loop ; Loop in lerr on failure - goto lerr_loop - nop - nop - nop - nop - - END - Index: trunk/scode/sanity1.rom =================================================================== --- trunk/scode/sanity1.rom (revision 6) +++ trunk/scode/sanity1.rom (nonexistent) @@ -1,181 +0,0 @@ - -@000 040 -@001 025 -@002 026 -@003 027 -@004 FFF -@005 005 -@006 006 -@007 007 -@008 705 -@009 AAF -@00A 725 -@00B AAF -@00C 745 -@00D AAF -@00E 765 -@00F AAF -@010 785 -@011 AAF -@012 7A5 -@013 AAF -@014 7C5 -@015 AAF -@016 7E5 -@017 AAF -@018 706 -@019 AAF -@01A 726 -@01B AAF -@01C 746 -@01D AAF -@01E 766 -@01F AAF -@020 786 -@021 AAF -@022 7A6 -@023 AAF -@024 7C6 -@025 AAF -@026 7E6 -@027 AAF -@028 707 -@029 AAF -@02A 727 -@02B AAF -@02C 747 -@02D AAF -@02E 767 -@02F AAF -@030 787 -@031 AAF -@032 7A7 -@033 AAF -@034 7C5 -@035 AAF -@036 7E7 -@037 AAF -@038 040 -@039 005 -@03A 006 -@03B 007 -@03C 040 -@03D FAA -@03E 025 -@03F 026 -@040 027 -@041 605 -@042 AAF -@043 725 -@044 AAF -@045 645 -@046 AAF -@047 765 -@048 AAF -@049 685 -@04A AAF -@04B 7A5 -@04C AAF -@04D 6C5 -@04E AAF -@04F 7E5 -@050 AAF -@051 606 -@052 AAF -@053 726 -@054 AAF -@055 646 -@056 AAF -@057 766 -@058 AAF -@059 686 -@05A AAF -@05B 7A6 -@05C AAF -@05D 6C6 -@05E AAF -@05F 7E6 -@060 AAF -@061 607 -@062 AAF -@063 727 -@064 AAF -@065 647 -@066 AAF -@067 767 -@068 AAF -@069 687 -@06A AAF -@06B 7A7 -@06C AAF -@06D 6C7 -@06E AAF -@06F 7E7 -@070 AAF -@071 040 -@072 F55 -@073 025 -@074 026 -@075 027 -@076 705 -@077 AAF -@078 625 -@079 AAF -@07A 745 -@07B AAF -@07C 665 -@07D AAF -@07E 785 -@07F AAF -@080 6A5 -@081 AAF -@082 7C5 -@083 AAF -@084 6E5 -@085 AAF -@086 706 -@087 AAF -@088 626 -@089 AAF -@08A 746 -@08B AAF -@08C 666 -@08D AAF -@08E 786 -@08F AAF -@090 6A6 -@091 AAF -@092 7C6 -@093 AAF -@094 6E6 -@095 AAF -@096 707 -@097 AAF -@098 627 -@099 AAF -@09A 747 -@09B AAF -@09C 667 -@09D AAF -@09E 787 -@09F AAF -@0A0 6A7 -@0A1 AAF -@0A2 7C7 -@0A3 AAF -@0A4 6E7 -@0A5 AAF -@0A6 000 -@0A7 000 -@0A8 000 -@0A9 000 -@0AA AAA -@0AB 000 -@0AC 000 -@0AD 000 -@0AE 000 -@0AF AAF -@0B0 000 -@0B1 000 -@0B2 000 -@0B3 000 Index: trunk/scode/rf1.rom =================================================================== --- trunk/scode/rf1.rom (revision 6) +++ trunk/scode/rf1.rom (nonexistent) @@ -1,584 +0,0 @@ - -@000 040 -@001 024 -@002 025 -@003 026 -@004 027 -@005 005 -@006 006 -@007 007 -@008 5A3 -@009 C81 -@00A 028 -@00B C82 -@00C 029 -@00D C83 -@00E 02A -@00F C84 -@010 02B -@011 C85 -@012 02C -@013 C86 -@014 02D -@015 C87 -@016 02E -@017 C88 -@018 02F -@019 C90 -@01A 030 -@01B C91 -@01C 031 -@01D C92 -@01E 032 -@01F C93 -@020 033 -@021 C94 -@022 034 -@023 C95 -@024 035 -@025 C96 -@026 036 -@027 C97 -@028 037 -@029 C98 -@02A 038 -@02B C99 -@02C 039 -@02D C9A -@02E 03A -@02F C9B -@030 03B -@031 C9C -@032 03C -@033 C9D -@034 03D -@035 C9E -@036 03E -@037 C9F -@038 03F -@039 5A4 -@03A CA0 -@03B 030 -@03C CA1 -@03D 031 -@03E CA2 -@03F 032 -@040 CA3 -@041 033 -@042 CA4 -@043 034 -@044 CA5 -@045 035 -@046 CA6 -@047 036 -@048 CA7 -@049 037 -@04A CA8 -@04B 038 -@04C CA9 -@04D 039 -@04E CAA -@04F 03A -@050 CAB -@051 03B -@052 CAC -@053 03C -@054 CAD -@055 03D -@056 CAE -@057 03E -@058 CAF -@059 03F -@05A 4A4 -@05B 5C4 -@05C CB0 -@05D 030 -@05E CB1 -@05F 031 -@060 CB2 -@061 032 -@062 CB3 -@063 033 -@064 CB4 -@065 034 -@066 CB5 -@067 035 -@068 CB6 -@069 036 -@06A CB7 -@06B 037 -@06C CB8 -@06D 038 -@06E CB9 -@06F 039 -@070 CBA -@071 03A -@072 CBB -@073 03B -@074 CBC -@075 03C -@076 CBD -@077 03D -@078 CBE -@079 03E -@07A CBF -@07B 03F -@07C 5A4 -@07D 5C4 -@07E CC0 -@07F 030 -@080 CC1 -@081 031 -@082 CC2 -@083 032 -@084 CC3 -@085 033 -@086 CC4 -@087 034 -@088 CC5 -@089 035 -@08A CC6 -@08B 036 -@08C CC7 -@08D 037 -@08E CC8 -@08F 038 -@090 CC9 -@091 039 -@092 CCA -@093 03A -@094 CCB -@095 03B -@096 CCC -@097 03C -@098 CCD -@099 03D -@09A CCE -@09B 03E -@09C CCF -@09D 03F -@09E C01 -@09F 026 -@0A0 040 -@0A1 024 -@0A2 C81 -@0A3 088 -@0A4 743 -@0A5 A3C -@0A6 C82 -@0A7 089 -@0A8 743 -@0A9 A3C -@0AA C83 -@0AB 08A -@0AC 743 -@0AD A3C -@0AE C84 -@0AF 08B -@0B0 743 -@0B1 A3C -@0B2 C85 -@0B3 08C -@0B4 743 -@0B5 A3C -@0B6 C86 -@0B7 08D -@0B8 743 -@0B9 A3C -@0BA C87 -@0BB 08E -@0BC 743 -@0BD A3C -@0BE C88 -@0BF 08F -@0C0 743 -@0C1 A3C -@0C2 C90 -@0C3 090 -@0C4 743 -@0C5 A3C -@0C6 C91 -@0C7 091 -@0C8 743 -@0C9 A3C -@0CA C92 -@0CB 092 -@0CC 743 -@0CD A3C -@0CE C93 -@0CF 093 -@0D0 743 -@0D1 A3C -@0D2 C94 -@0D3 094 -@0D4 743 -@0D5 A3C -@0D6 C95 -@0D7 095 -@0D8 743 -@0D9 A3C -@0DA C96 -@0DB 096 -@0DC 743 -@0DD A3C -@0DE C97 -@0DF 097 -@0E0 743 -@0E1 A3C -@0E2 C98 -@0E3 098 -@0E4 743 -@0E5 A3C -@0E6 C99 -@0E7 099 -@0E8 743 -@0E9 A3C -@0EA C9A -@0EB 09A -@0EC 743 -@0ED A3C -@0EE C9B -@0EF 09B -@0F0 743 -@0F1 A3C -@0F2 C9C -@0F3 09C -@0F4 743 -@0F5 A3C -@0F6 C9D -@0F7 09D -@0F8 743 -@0F9 A3C -@0FA C9E -@0FB 09E -@0FC 743 -@0FD A3C -@0FE C9F -@0FF 09F -@100 743 -@101 A3C -@102 C02 -@103 026 -@104 5A4 -@105 C81 -@106 088 -@107 743 -@108 A3C -@109 C82 -@10A 089 -@10B 743 -@10C A3C -@10D C83 -@10E 08A -@10F 743 -@110 A3C -@111 C84 -@112 08B -@113 743 -@114 A3C -@115 C85 -@116 08C -@117 743 -@118 A3C -@119 C86 -@11A 08D -@11B 743 -@11C A3C -@11D C87 -@11E 08E -@11F 743 -@120 A3C -@121 C88 -@122 08F -@123 743 -@124 A3C -@125 CA0 -@126 090 -@127 743 -@128 A3C -@129 CA1 -@12A 091 -@12B 743 -@12C A3C -@12D CA2 -@12E 092 -@12F 743 -@130 A3C -@131 CA3 -@132 093 -@133 743 -@134 A3C -@135 CA4 -@136 094 -@137 743 -@138 A3C -@139 CA5 -@13A 095 -@13B 743 -@13C A3C -@13D CA6 -@13E 096 -@13F 743 -@140 A3C -@141 CA7 -@142 097 -@143 743 -@144 A3C -@145 CA8 -@146 098 -@147 743 -@148 A3C -@149 CA9 -@14A 099 -@14B 743 -@14C A3C -@14D CAA -@14E 09A -@14F 743 -@150 A3C -@151 CAB -@152 09B -@153 743 -@154 A3C -@155 CAC -@156 09C -@157 743 -@158 A3C -@159 CAD -@15A 09D -@15B 743 -@15C A3C -@15D CAE -@15E 09E -@15F 743 -@160 A3C -@161 CAF -@162 09F -@163 743 -@164 A3C -@165 C03 -@166 026 -@167 4A4 -@168 5C4 -@169 C81 -@16A 088 -@16B 743 -@16C A3C -@16D C82 -@16E 089 -@16F 743 -@170 A3C -@171 C83 -@172 08A -@173 743 -@174 A3C -@175 C84 -@176 08B -@177 743 -@178 A3C -@179 C85 -@17A 08C -@17B 743 -@17C A3C -@17D C86 -@17E 08D -@17F 743 -@180 A3C -@181 C87 -@182 08E -@183 743 -@184 A3C -@185 C88 -@186 08F -@187 743 -@188 A3C -@189 CB0 -@18A 090 -@18B 743 -@18C A3C -@18D CB1 -@18E 091 -@18F 743 -@190 A3C -@191 CB2 -@192 092 -@193 743 -@194 A3C -@195 CB3 -@196 093 -@197 743 -@198 A3C -@199 CB4 -@19A 094 -@19B 743 -@19C A3C -@19D CB5 -@19E 095 -@19F 743 -@1A0 A3C -@1A1 CB6 -@1A2 096 -@1A3 743 -@1A4 A3C -@1A5 CB7 -@1A6 097 -@1A7 743 -@1A8 A3C -@1A9 CB8 -@1AA 098 -@1AB 743 -@1AC A3C -@1AD CB9 -@1AE 099 -@1AF 743 -@1B0 A3C -@1B1 CBA -@1B2 09A -@1B3 743 -@1B4 A3C -@1B5 CBB -@1B6 09B -@1B7 743 -@1B8 A3C -@1B9 CBC -@1BA 09C -@1BB 743 -@1BC A3C -@1BD CBD -@1BE 09D -@1BF 743 -@1C0 A3C -@1C1 CBE -@1C2 09E -@1C3 743 -@1C4 A3C -@1C5 CBF -@1C6 09F -@1C7 743 -@1C8 A3C -@1C9 C04 -@1CA 026 -@1CB 5A4 -@1CC 5C4 -@1CD C81 -@1CE 088 -@1CF 743 -@1D0 A3C -@1D1 C82 -@1D2 089 -@1D3 743 -@1D4 A3C -@1D5 C83 -@1D6 08A -@1D7 743 -@1D8 A3C -@1D9 C84 -@1DA 08B -@1DB 743 -@1DC A3C -@1DD C85 -@1DE 08C -@1DF 743 -@1E0 A3C -@1E1 C86 -@1E2 08D -@1E3 743 -@1E4 A3C -@1E5 C87 -@1E6 08E -@1E7 743 -@1E8 A3C -@1E9 C88 -@1EA 08F -@1EB 743 -@1EC A3C -@1ED CC0 -@1EE 090 -@1EF 743 -@1F0 A3C -@1F1 CC1 -@1F2 091 -@1F3 743 -@1F4 A3C -@1F5 CC2 -@1F6 092 -@1F7 743 -@1F8 A3C -@1F9 CC3 -@1FA 093 -@1FB 743 -@1FC A3C -@1FD CC4 -@1FE 094 -@1FF 743 -@200 A3C -@201 CC5 -@202 095 -@203 743 -@204 A3C -@205 CC6 -@206 096 -@207 743 -@208 A3C -@209 CC7 -@20A 097 -@20B 743 -@20C A3C -@20D CC8 -@20E 098 -@20F 743 -@210 A3C -@211 CC9 -@212 099 -@213 743 -@214 A3C -@215 CCA -@216 09A -@217 743 -@218 A3C -@219 CCB -@21A 09B -@21B 743 -@21C A3C -@21D CCC -@21E 09C -@21F 743 -@220 A3C -@221 CCD -@222 09D -@223 743 -@224 A3C -@225 CCE -@226 09E -@227 743 -@228 A3C -@229 CCF -@22A 09F -@22B 743 -@22C A3C -@22D 000 -@22E 000 -@22F 000 -@230 000 -@231 C01 -@232 025 -@233 000 -@234 000 -@235 000 -@236 000 -@237 A37 -@238 000 -@239 000 -@23A 000 -@23B 000 -@23C CFF -@23D 025 -@23E 000 -@23F 000 -@240 000 -@241 000 -@242 A42 -@243 000 -@244 000 -@245 000 -@246 000 Index: trunk/scode/sanity2.rom =================================================================== --- trunk/scode/sanity2.rom (revision 6) +++ trunk/scode/sanity2.rom (nonexistent) @@ -1,282 +0,0 @@ - -@000 040 -@001 024 -@002 025 -@003 026 -@004 027 -@005 005 -@006 006 -@007 007 -@008 C0B -@009 028 -@00A 202 -@00B 088 -@00C 743 -@00D B23 -@00E C01 -@00F 026 -@010 C13 -@011 02B -@012 202 -@013 08B -@014 743 -@015 B23 -@016 C02 -@017 026 -@018 C1D -@019 022 -@01A B23 -@01B B23 -@01C B23 -@01D A21 -@01E B23 -@01F B23 -@020 B23 -@021 C03 -@022 026 -@023 C28 -@024 022 -@025 B23 -@026 B23 -@027 B23 -@028 A2C -@029 B23 -@02A B23 -@02B B23 -@02C C04 -@02D 026 -@02E C35 -@02F 028 -@030 C32 -@031 088 -@032 1E2 -@033 B23 -@034 B23 -@035 B23 -@036 A3A -@037 B23 -@038 B23 -@039 B23 -@03A C05 -@03B 026 -@03C C43 -@03D 038 -@03E C40 -@03F 098 -@040 1E2 -@041 B23 -@042 B23 -@043 B23 -@044 A48 -@045 B23 -@046 B23 -@047 B23 -@048 C06 -@049 026 -@04A A60 -@060 522 -@061 B23 -@062 B23 -@063 A68 -@064 B23 -@065 B23 -@066 B23 -@067 B23 -@068 C07 -@069 026 -@06A 542 -@06B B23 -@06C B23 -@06D B23 -@06E B23 -@06F A72 -@070 B23 -@071 B23 -@072 C08 -@073 026 -@074 A7C -@075 B23 -@076 B23 -@077 B23 -@078 B23 -@079 A7D -@07A B23 -@07B B23 -@07C 442 -@07D C09 -@07E 026 -@07F A8A -@080 000 -@081 000 -@082 000 -@083 000 -@084 CFF -@085 025 -@086 000 -@087 000 -@088 000 -@089 000 -@08A C0A -@08B 026 -@08C 9A5 -@08D 028 -@08E C55 -@08F 088 -@090 743 -@091 B23 -@092 9A7 -@093 028 -@094 CAA -@095 088 -@096 743 -@097 B23 -@098 9AA -@099 028 -@09A CC3 -@09B 088 -@09C 743 -@09D B23 -@09E 9AE -@09F 028 -@0A0 C3C -@0A1 088 -@0A2 743 -@0A3 B23 -@0A4 AC5 -@0A5 855 -@0A6 B23 -@0A7 000 -@0A8 8AA -@0A9 B23 -@0AA 000 -@0AB 000 -@0AC 8C3 -@0AD B23 -@0AE 000 -@0AF 000 -@0B0 000 -@0B1 83C -@0B2 B23 -@0B3 1E2 -@0B4 8FF -@0B5 8FE -@0B6 8FD -@0B7 8FC -@0B8 8FB -@0B9 8FA -@0BA 8F9 -@0BB 8F8 -@0BC 8F7 -@0BD 8F6 -@0BE 8F5 -@0BF B23 -@0C0 B23 -@0C1 B23 -@0C2 B23 -@0C3 B23 -@0C4 B23 -@0C5 C0B -@0C6 026 -@0C7 C00 -@0C8 028 -@0C9 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000 Index: trunk/scode/rf2.rom =================================================================== --- trunk/scode/rf2.rom (revision 6) +++ trunk/scode/rf2.rom (nonexistent) @@ -1,720 +0,0 @@ - -@000 040 -@001 024 -@002 025 -@003 026 -@004 027 -@005 005 -@006 006 -@007 007 -@008 5A3 -@009 C81 -@00A 028 -@00B C82 -@00C 029 -@00D C83 -@00E 02A -@00F C84 -@010 02B -@011 C85 -@012 02C -@013 C86 -@014 02D -@015 C87 -@016 02E -@017 C88 -@018 02F -@019 C90 -@01A 030 -@01B C91 -@01C 031 -@01D C92 -@01E 032 -@01F C93 -@020 033 -@021 C94 -@022 034 -@023 C95 -@024 035 -@025 C96 -@026 036 -@027 C97 -@028 037 -@029 C98 -@02A 038 -@02B C99 -@02C 039 -@02D C9A -@02E 03A -@02F C9B -@030 03B -@031 C9C -@032 03C -@033 C9D -@034 03D -@035 C9E -@036 03E -@037 C9F -@038 03F -@039 5A4 -@03A CA0 -@03B 030 -@03C CA1 -@03D 031 -@03E CA2 -@03F 032 -@040 CA3 -@041 033 -@042 CA4 -@043 034 -@044 CA5 -@045 035 -@046 CA6 -@047 036 -@048 CA7 -@049 037 -@04A CA8 -@04B 038 -@04C CA9 -@04D 039 -@04E CAA -@04F 03A -@050 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2A4 -@1E1 080 -@1E2 743 -@1E3 AC4 -@1E4 C57 -@1E5 2A4 -@1E6 080 -@1E7 743 -@1E8 AC4 -@1E9 C56 -@1EA 2A4 -@1EB 080 -@1EC 743 -@1ED AC4 -@1EE C55 -@1EF 2A4 -@1F0 080 -@1F1 743 -@1F2 AC4 -@1F3 C54 -@1F4 2A4 -@1F5 080 -@1F6 743 -@1F7 AC4 -@1F8 C53 -@1F9 2A4 -@1FA 080 -@1FB 743 -@1FC AC4 -@1FD C52 -@1FE 2A4 -@1FF 080 -@200 743 -@201 AC4 -@202 C51 -@203 2A4 -@204 080 -@205 743 -@206 AC4 -@207 C50 -@208 2A4 -@209 080 -@20A 743 -@20B AC4 -@20C C03 -@20D 026 -@20E C10 -@20F 024 -@210 5C4 -@211 C4F -@212 080 -@213 743 -@214 AC4 -@215 C4E -@216 2A4 -@217 080 -@218 743 -@219 AC4 -@21A C4D -@21B 2A4 -@21C 080 -@21D 743 -@21E AC4 -@21F C4C -@220 2A4 -@221 080 -@222 743 -@223 AC4 -@224 C4B -@225 2A4 -@226 080 -@227 743 -@228 AC4 -@229 C4A -@22A 2A4 -@22B 080 -@22C 743 -@22D AC4 -@22E C49 -@22F 2A4 -@230 080 -@231 743 -@232 AC4 -@233 C48 -@234 2A4 -@235 080 -@236 743 -@237 AC4 -@238 C47 -@239 2A4 -@23A 080 -@23B 743 -@23C AC4 -@23D C46 -@23E 2A4 -@23F 080 -@240 743 -@241 AC4 -@242 C45 -@243 2A4 -@244 080 -@245 743 -@246 AC4 -@247 C44 -@248 2A4 -@249 080 -@24A 743 -@24B AC4 -@24C C43 -@24D 2A4 -@24E 080 -@24F 743 -@250 AC4 -@251 C42 -@252 2A4 -@253 080 -@254 743 -@255 AC4 -@256 C41 -@257 2A4 -@258 080 -@259 743 -@25A AC4 -@25B C40 -@25C 2A4 -@25D 080 -@25E 743 -@25F AC4 -@260 C04 -@261 026 -@262 C10 -@263 024 -@264 5A4 -@265 5C4 -@266 C3F -@267 080 -@268 743 -@269 AC4 -@26A C3E -@26B 2A4 -@26C 080 -@26D 743 -@26E AC4 -@26F C3D -@270 2A4 -@271 080 -@272 743 -@273 AC4 -@274 C3C -@275 2A4 -@276 080 -@277 743 -@278 AC4 -@279 C3B -@27A 2A4 -@27B 080 -@27C 743 -@27D AC4 -@27E C3A -@27F 2A4 -@280 080 -@281 743 -@282 AC4 -@283 C39 -@284 2A4 -@285 080 -@286 743 -@287 AC4 -@288 C38 -@289 2A4 -@28A 080 -@28B 743 -@28C AC4 -@28D C37 -@28E 2A4 -@28F 080 -@290 743 -@291 AC4 -@292 C36 -@293 2A4 -@294 080 -@295 743 -@296 AC4 -@297 C35 -@298 2A4 -@299 080 -@29A 743 -@29B AC4 -@29C C34 -@29D 2A4 -@29E 080 -@29F 743 -@2A0 AC4 -@2A1 C33 -@2A2 2A4 -@2A3 080 -@2A4 743 -@2A5 AC4 -@2A6 C32 -@2A7 2A4 -@2A8 080 -@2A9 743 -@2AA AC4 -@2AB C31 -@2AC 2A4 -@2AD 080 -@2AE 743 -@2AF AC4 -@2B0 C30 -@2B1 2A4 -@2B2 080 -@2B3 743 -@2B4 AC4 -@2B5 000 -@2B6 000 -@2B7 000 -@2B8 000 -@2B9 C01 -@2BA 025 -@2BB 000 -@2BC 000 -@2BD 000 -@2BE 000 -@2BF ABF -@2C0 000 -@2C1 000 -@2C2 000 -@2C3 000 -@2C4 CFF -@2C5 025 -@2C6 000 -@2C7 000 -@2C8 000 -@2C9 000 -@2CA ACA -@2CB 000 -@2CC 000 -@2CD 000 -@2CE 000 Index: trunk/scode/rf3.rom =================================================================== --- trunk/scode/rf3.rom (revision 6) +++ trunk/scode/rf3.rom (nonexistent) @@ -1,219 +0,0 @@ - -@000 040 -@001 024 -@002 025 -@003 026 -@004 027 -@005 005 -@006 006 -@007 007 -@008 C01 -@009 026 -@00A CFC -@00B 028 -@00C 2A8 -@00D 2A8 -@00E 2A8 -@00F 2A8 -@010 743 -@011 ACF -@012 CFC -@013 038 -@014 2B8 -@015 2B8 -@016 2B8 -@017 2B8 -@018 743 -@019 ACF -@01A C02 -@01B 026 -@01C C09 -@01D 024 -@01E CFC -@01F 020 -@020 2A0 -@021 2A0 -@022 2A0 -@023 2A0 -@024 743 -@025 ACF -@026 C19 -@027 024 -@028 CFC -@029 020 -@02A 2A0 -@02B 2A0 -@02C 2A0 -@02D 2A0 -@02E 743 -@02F ACF -@030 C03 -@031 026 -@032 C04 -@033 028 -@034 0E8 -@035 0E8 -@036 0E8 -@037 0E8 -@038 743 -@039 ACF -@03A C04 -@03B 030 -@03C 0F0 -@03D 0F0 -@03E 0F0 -@03F 0F0 -@040 743 -@041 ACF -@042 C04 -@043 026 -@044 C09 -@045 024 -@046 C04 -@047 020 -@048 0E0 -@049 0E0 -@04A 0E0 -@04B 0E0 -@04C 743 -@04D ACF -@04E C19 -@04F 024 -@050 C04 -@051 020 -@052 0E0 -@053 0E0 -@054 0E0 -@055 0E0 -@056 743 -@057 ACF -@058 C05 -@059 026 -@05A CFC -@05B 02C -@05C 3EC -@05D 3EC -@05E 3EC -@05F 3EC -@060 ACF -@061 CFC -@062 038 -@063 3F8 -@064 3F8 -@065 3F8 -@066 3F8 -@067 ACF -@068 C06 -@069 026 -@06A C09 -@06B 024 -@06C CFC -@06D 020 -@06E 3E0 -@06F 3E0 -@070 3E0 -@071 3E0 -@072 ACF -@073 C19 -@074 024 -@075 CFC -@076 020 -@077 3E0 -@078 3E0 -@079 3E0 -@07A 3E0 -@07B ACF -@07C C07 -@07D 026 -@07E C04 -@07F 028 -@080 2E8 -@081 2E8 -@082 2E8 -@083 2E8 -@084 ACF -@085 C04 -@086 030 -@087 2F0 -@088 2F0 -@089 2F0 -@08A 2F0 -@08B ACF -@08C C08 -@08D 026 -@08E C09 -@08F 024 -@090 C04 -@091 020 -@092 2E0 -@093 2E0 -@094 2E0 -@095 2E0 -@096 ACF -@097 C19 -@098 024 -@099 C04 -@09A 020 -@09B 2E0 -@09C 2E0 -@09D 2E0 -@09E 2E0 -@09F ACF -@0A0 C09 -@0A1 026 -@0A2 CFC -@0A3 024 -@0A4 2A4 -@0A5 2A4 -@0A6 2A4 -@0A7 2A4 -@0A8 743 -@0A9 ACF -@0AA C04 -@0AB 024 -@0AC C7F -@0AD 0E4 -@0AE 0E4 -@0AF 0E4 -@0B0 0E4 -@0B1 164 -@0B2 743 -@0B3 ACF -@0B4 C0A -@0B5 026 -@0B6 CFC -@0B7 023 -@0B8 C18 -@0B9 2A3 -@0BA 2A3 -@0BB 2A3 -@0BC 2A3 -@0BD 083 -@0BE 743 -@0BF ACF -@0C0 000 -@0C1 000 -@0C2 000 -@0C3 000 -@0C4 C01 -@0C5 025 -@0C6 000 -@0C7 000 -@0C8 000 -@0C9 000 -@0CA ACA -@0CB 000 -@0CC 000 -@0CD 000 -@0CE 000 -@0CF CFF -@0D0 025 -@0D1 000 -@0D2 000 -@0D3 000 -@0D4 000 -@0D5 AD5 -@0D6 000 -@0D7 000 -@0D8 000 -@0D9 000 Index: trunk/scode/sanity1.asm =================================================================== --- trunk/scode/sanity1.asm (revision 6) +++ trunk/scode/sanity1.asm (nonexistent) @@ -1,250 +0,0 @@ -;///////////////////////////////////////////////////////////////////// -;//// //// -;//// Mini-RISC-1 //// -;//// Compliance Test 1 //// -;//// Tests Ports //// -;//// //// -;//// Author: Rudolf Usselmann //// -;//// russelmann@hotmail.com //// -;//// //// -;///////////////////////////////////////////////////////////////////// -;//// //// -;//// Copyright (C) 2000 Rudolf Usselmann //// -;//// russelmann@hotmail.com //// -;//// //// -;//// This source file may be used and distributed without //// -;//// restriction provided that this copyright statement is not //// -;//// removed from the file and that any derivative work contains //// -;//// the original copyright notice and the associated disclaimer.//// -;//// //// -;//// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY //// -;//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT //// -;//// LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND //// -;//// FITNESS FOR A PARTICULAR PURPOSE. //// -;//// //// -;///////////////////////////////////////////////////////////////////// - - list p=16c57 - #include p16c5x.inc - - -main ; Main code entry - ; Port IO Test - ; All ports have a Pull up resistor - - ; Tristate all ports - clrw - movwf PORTA - movwf PORTB - movwf PORTC - xorlw 0xff - tris PORTA - tris PORTB - tris PORTC - - ; Now check that porta is 0xff - btfss PORTA,0 - goto lerr - btfss PORTA,1 - goto lerr - btfss PORTA,2 - goto lerr - btfss PORTA,3 - goto lerr - btfss PORTA,4 - goto lerr - btfss PORTA,5 - goto lerr - btfss PORTA,6 - goto lerr - btfss PORTA,7 - goto lerr - - - ; Now check that portb is 0xff - btfss PORTB,0 - goto lerr - btfss PORTB,1 - goto lerr - btfss PORTB,2 - goto lerr - btfss PORTB,3 - goto lerr - btfss PORTB,4 - goto lerr - btfss PORTB,5 - goto lerr - btfss PORTB,6 - goto lerr - btfss PORTB,7 - goto lerr - - ; Now check that portc is 0xff - btfss PORTC,0 - goto lerr - btfss PORTC,1 - goto lerr - btfss PORTC,2 - goto lerr - btfss PORTC,3 - goto lerr - btfss PORTC,4 - goto lerr - btfss PORTC,5 - goto lerr - btfss PORTA,6 - goto lerr - btfss PORTC,7 - goto lerr - - - - ; Enable all ports - clrw - tris PORTA - tris PORTB - tris PORTC - - ; Drive them all 0xaa - clrw - xorlw 0xaa - movwf PORTA - movwf PORTB - movwf PORTC - - ; Now check that porta is 0xaa - btfsc PORTA,0 - goto lerr - btfss PORTA,1 - goto lerr - btfsc PORTA,2 - goto lerr - btfss PORTA,3 - goto lerr - btfsc PORTA,4 - goto lerr - btfss PORTA,5 - goto lerr - btfsc PORTA,6 - goto lerr - btfss PORTA,7 - goto lerr - - ; Now check that portb is 0xaa - btfsc PORTB,0 - goto lerr - btfss PORTB,1 - goto lerr - btfsc PORTB,2 - goto lerr - btfss PORTB,3 - goto lerr - btfsc PORTB,4 - goto lerr - btfss PORTB,5 - goto lerr - btfsc PORTB,6 - goto lerr - btfss PORTB,7 - goto lerr - - ; Now check that portc is 0xaa - btfsc PORTC,0 - goto lerr - btfss PORTC,1 - goto lerr - btfsc PORTC,2 - goto lerr - btfss PORTC,3 - goto lerr - btfsc PORTC,4 - goto lerr - btfss PORTC,5 - goto lerr - btfsc PORTC,6 - goto lerr - btfss PORTC,7 - goto lerr - - ; Drive them all 0x55 - clrw - xorlw 0x55 - movwf PORTA - movwf PORTB - movwf PORTC - - ; Now check that porta is 0x55 - btfss PORTA,0 - goto lerr - btfsc PORTA,1 - goto lerr - btfss PORTA,2 - goto lerr - btfsc PORTA,3 - goto lerr - btfss PORTA,4 - goto lerr - btfsc PORTA,5 - goto lerr - btfss PORTA,6 - goto lerr - btfsc PORTA,7 - goto lerr - - ; Now check that portb is 0x55 - btfss PORTB,0 - goto lerr - btfsc PORTB,1 - goto lerr - btfss PORTB,2 - goto lerr - btfsc PORTB,3 - goto lerr - btfss PORTB,4 - goto lerr - btfsc PORTB,5 - goto lerr - btfss PORTB,6 - goto lerr - btfsc PORTB,7 - goto lerr - - ; Now check that portc is 0x55 - btfss PORTC,0 - goto lerr - btfsc PORTC,1 - goto lerr - btfss PORTC,2 - goto lerr - btfsc PORTC,3 - goto lerr - btfss PORTC,4 - goto lerr - btfsc PORTC,5 - goto lerr - btfss PORTC,6 - goto lerr - btfsc PORTC,7 - goto lerr - - nop - nop - nop - nop - -good ; Loop in good on success - goto good - nop - nop - nop - nop - -lerr ; Loop in lerr on failure - goto lerr - nop - nop - nop - nop - - END - Index: trunk/scode/rf1.asm =================================================================== --- trunk/scode/rf1.asm (revision 6) +++ trunk/scode/rf1.asm (nonexistent) @@ -1,694 +0,0 @@ -;///////////////////////////////////////////////////////////////////// -;//// //// -;//// Mini-RISC-1 //// -;//// Register File Test 1 //// -;//// Tests Register File //// -;//// //// -;//// Author: Rudolf Usselmann //// -;//// russelmann@hotmail.com //// -;//// //// -;///////////////////////////////////////////////////////////////////// -;//// //// -;//// Copyright (C) 2000 Rudolf Usselmann //// -;//// russelmann@hotmail.com //// -;//// //// -;//// This source file may be used and distributed without //// -;//// restriction provided that this copyright statement is not //// -;//// removed from the file and that any derivative work contains //// -;//// the original copyright notice and the associated disclaimer.//// -;//// //// -;//// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY //// -;//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT //// -;//// LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND //// -;//// FITNESS FOR A PARTICULAR PURPOSE. //// -;//// //// -;///////////////////////////////////////////////////////////////////// - - list p=16c57 - #include p16c5x.inc - -; global Registers -r0 equ 0x8 -r1 equ 0x9 -r2 equ 0xa -r3 equ 0xb -r4 equ 0xc -r5 equ 0xd -r6 equ 0xe -r7 equ 0xf - -; banked Registers -br0 equ 0x10 -br1 equ 0x11 -br2 equ 0x12 -br3 equ 0x13 -br4 equ 0x14 -br5 equ 0x15 -br6 equ 0x16 -br7 equ 0x17 -br8 equ 0x18 -br9 equ 0x19 -br10 equ 0x1a -br11 equ 0x1b -br12 equ 0x1c -br13 equ 0x1d -br14 equ 0x1e -br15 equ 0x1f - - -; PORTB Indicates Test Number -; PORTA Indicates Status: 0 - Running; 1 - done OK; ff - stoped on error - -main ; Main code entry - ; Port IO Test - ; All ports have a Pull up resistor - - ; SETUP all ports - clrw - movwf FSR - movwf PORTA - movwf PORTB - movwf PORTC - tris PORTA - tris PORTB - tris PORTC - - bsf STATUS,5 - - ; --------------------------------------- - ; ---- Test the entire register file ---- - ; --------------------------------------- - - movlw 0x81 - movwf r0 - movlw 0x82 - movwf r1 - movlw 0x83 - movwf r2 - movlw 0x84 - movwf r3 - movlw 0x85 - movwf r4 - movlw 0x86 - movwf r5 - movlw 0x87 - movwf r6 - movlw 0x88 - movwf r7 - - - movlw 0x90 - movwf br0 - movlw 0x91 - movwf br1 - movlw 0x92 - movwf br2 - movlw 0x93 - movwf br3 - movlw 0x94 - movwf br4 - movlw 0x95 - movwf br5 - movlw 0x96 - movwf br6 - movlw 0x97 - movwf br7 - movlw 0x98 - movwf br8 - movlw 0x99 - movwf br9 - movlw 0x9a - movwf br10 - movlw 0x9b - movwf br11 - movlw 0x9c - movwf br12 - movlw 0x9d - movwf br13 - movlw 0x9e - movwf br14 - movlw 0x9f - movwf br15 - - bsf FSR,5 ; Select Register Bank 01 - - movlw 0xa0 - movwf br0 - movlw 0xa1 - movwf br1 - movlw 0xa2 - movwf br2 - movlw 0xa3 - movwf br3 - movlw 0xa4 - movwf br4 - movlw 0xa5 - movwf br5 - movlw 0xa6 - movwf br6 - movlw 0xa7 - movwf br7 - movlw 0xa8 - movwf br8 - movlw 0xa9 - movwf br9 - movlw 0xaa - movwf br10 - movlw 0xab - movwf br11 - movlw 0xac - movwf br12 - movlw 0xad - movwf br13 - movlw 0xae - movwf br14 - movlw 0xaf - movwf br15 - - bcf FSR,5 ; Select Register Bank 10 - bsf FSR,6 - - movlw 0xb0 - movwf br0 - movlw 0xb1 - movwf br1 - movlw 0xb2 - movwf br2 - movlw 0xb3 - movwf br3 - movlw 0xb4 - movwf br4 - movlw 0xb5 - movwf br5 - movlw 0xb6 - movwf br6 - movlw 0xb7 - movwf br7 - movlw 0xb8 - movwf br8 - movlw 0xb9 - movwf br9 - movlw 0xba - movwf br10 - movlw 0xbb - movwf br11 - movlw 0xbc - movwf br12 - movlw 0xbd - movwf br13 - movlw 0xbe - movwf br14 - movlw 0xbf - movwf br15 - - bsf FSR,5 ; Select Register Bank 11 - bsf FSR,6 - - movlw 0xc0 - movwf br0 - movlw 0xc1 - movwf br1 - movlw 0xc2 - movwf br2 - movlw 0xc3 - movwf br3 - movlw 0xc4 - movwf br4 - movlw 0xc5 - movwf br5 - movlw 0xc6 - movwf br6 - movlw 0xc7 - movwf br7 - movlw 0xc8 - movwf br8 - movlw 0xc9 - movwf br9 - movlw 0xca - movwf br10 - movlw 0xcb - movwf br11 - movlw 0xcc - movwf br12 - movlw 0xcd - movwf br13 - movlw 0xce - movwf br14 - movlw 0xcf - movwf br15 - - ; Register File TEST 1 - movlw 0x01 - movwf PORTB ; Set Test Number - - clrw - movwf FSR - - movlw 0x81 - subwf r0,W - btfss STATUS,Z - goto lerr - movlw 0x82 - subwf r1,W - btfss STATUS,Z - goto lerr - movlw 0x83 - subwf r2,W - btfss STATUS,Z - goto lerr - movlw 0x84 - subwf r3,W - btfss STATUS,Z - goto lerr - movlw 0x85 - subwf r4,W - btfss STATUS,Z - goto lerr - movlw 0x86 - subwf r5,W - btfss STATUS,Z - goto lerr - movlw 0x87 - subwf r6,W - btfss STATUS,Z - goto lerr - movlw 0x88 - subwf r7,W - btfss STATUS,Z - goto lerr - - movlw 0x90 - subwf br0,W - btfss STATUS,Z - goto lerr - movlw 0x91 - subwf br1,W - btfss STATUS,Z - goto lerr - movlw 0x92 - subwf br2,W - btfss STATUS,Z - goto lerr - movlw 0x93 - subwf br3,W - btfss STATUS,Z - goto lerr - movlw 0x94 - subwf br4,W - btfss STATUS,Z - goto lerr - movlw 0x95 - subwf br5,W - btfss STATUS,Z - goto lerr - movlw 0x96 - subwf br6,W - btfss STATUS,Z - goto lerr - movlw 0x97 - subwf br7,W - btfss STATUS,Z - goto lerr - movlw 0x98 - subwf br8,W - btfss STATUS,Z - goto lerr - movlw 0x99 - subwf br9,W - btfss STATUS,Z - goto lerr - movlw 0x9a - subwf br10,W - btfss STATUS,Z - goto lerr - movlw 0x9b - subwf br11,W - btfss STATUS,Z - goto lerr - movlw 0x9c - subwf br12,W - btfss STATUS,Z - goto lerr - movlw 0x9d - subwf br13,W - btfss STATUS,Z - goto lerr - movlw 0x9e - subwf br14,W - btfss STATUS,Z - goto lerr - movlw 0x9f - subwf br15,W - btfss STATUS,Z - goto lerr - - ; Register File TEST 2 - movlw 0x02 - movwf PORTB ; Set Test Number - - bsf FSR,5 ; Select Register Bank 01 - - movlw 0x81 - subwf r0,W - btfss STATUS,Z - goto lerr - movlw 0x82 - subwf r1,W - btfss STATUS,Z - goto lerr - movlw 0x83 - subwf r2,W - btfss STATUS,Z - goto lerr - movlw 0x84 - subwf r3,W - btfss STATUS,Z - goto lerr - movlw 0x85 - subwf r4,W - btfss STATUS,Z - goto lerr - movlw 0x86 - subwf r5,W - btfss STATUS,Z - goto lerr - movlw 0x87 - subwf r6,W - btfss STATUS,Z - goto lerr - movlw 0x88 - subwf r7,W - btfss STATUS,Z - goto lerr - - movlw 0xa0 - subwf br0,W - btfss STATUS,Z - goto lerr - movlw 0xa1 - subwf br1,W - btfss STATUS,Z - goto lerr - movlw 0xa2 - subwf br2,W - btfss STATUS,Z - goto lerr - movlw 0xa3 - subwf br3,W - btfss STATUS,Z - goto lerr - movlw 0xa4 - subwf br4,W - btfss STATUS,Z - goto lerr - movlw 0xa5 - subwf br5,W - btfss STATUS,Z - goto lerr - movlw 0xa6 - subwf br6,W - btfss STATUS,Z - goto lerr - movlw 0xa7 - subwf br7,W - btfss STATUS,Z - goto lerr - movlw 0xa8 - subwf br8,W - btfss STATUS,Z - goto lerr - movlw 0xa9 - subwf br9,W - btfss STATUS,Z - goto lerr - movlw 0xaa - subwf br10,W - btfss STATUS,Z - goto lerr - movlw 0xab - subwf br11,W - btfss STATUS,Z - goto lerr - movlw 0xac - subwf br12,W - btfss STATUS,Z - goto lerr - movlw 0xad - subwf br13,W - btfss STATUS,Z - goto lerr - movlw 0xae - subwf br14,W - btfss STATUS,Z - goto lerr - movlw 0xaf - subwf br15,W - btfss STATUS,Z - goto lerr - - ; Register File TEST 3 - movlw 0x03 - movwf PORTB ; Set Test Number - - bcf FSR,5 ; Select Register Bank 10 - bsf FSR,6 - - movlw 0x81 - subwf r0,W - btfss STATUS,Z - goto lerr - movlw 0x82 - subwf r1,W - btfss STATUS,Z - goto lerr - movlw 0x83 - subwf r2,W - btfss STATUS,Z - goto lerr - movlw 0x84 - subwf r3,W - btfss STATUS,Z - goto lerr - movlw 0x85 - subwf r4,W - btfss STATUS,Z - goto lerr - movlw 0x86 - subwf r5,W - btfss STATUS,Z - goto lerr - movlw 0x87 - subwf r6,W - btfss STATUS,Z - goto lerr - movlw 0x88 - subwf r7,W - btfss STATUS,Z - goto lerr - - movlw 0xb0 - subwf br0,W - btfss STATUS,Z - goto lerr - movlw 0xb1 - subwf br1,W - btfss STATUS,Z - goto lerr - movlw 0xb2 - subwf br2,W - btfss STATUS,Z - goto lerr - movlw 0xb3 - subwf br3,W - btfss STATUS,Z - goto lerr - movlw 0xb4 - subwf br4,W - btfss STATUS,Z - goto lerr - movlw 0xb5 - subwf br5,W - btfss STATUS,Z - goto lerr - movlw 0xb6 - subwf br6,W - btfss STATUS,Z - goto lerr - movlw 0xb7 - subwf br7,W - btfss STATUS,Z - goto lerr - movlw 0xb8 - subwf br8,W - btfss STATUS,Z - goto lerr - movlw 0xb9 - subwf br9,W - btfss STATUS,Z - goto lerr - movlw 0xba - subwf br10,W - btfss STATUS,Z - goto lerr - movlw 0xbb - subwf br11,W - btfss STATUS,Z - goto lerr - movlw 0xbc - subwf br12,W - btfss STATUS,Z - goto lerr - movlw 0xbd - subwf br13,W - btfss STATUS,Z - goto lerr - movlw 0xbe - subwf br14,W - btfss STATUS,Z - goto lerr - movlw 0xbf - subwf br15,W - btfss STATUS,Z - goto lerr - - - ; Register File TEST 4 - movlw 0x04 - movwf PORTB ; Set Test Number - - bsf FSR,5 ; Select Register Bank 11 - bsf FSR,6 - - movlw 0x81 - subwf r0,W - btfss STATUS,Z - goto lerr - movlw 0x82 - subwf r1,W - btfss STATUS,Z - goto lerr - movlw 0x83 - subwf r2,W - btfss STATUS,Z - goto lerr - movlw 0x84 - subwf r3,W - btfss STATUS,Z - goto lerr - movlw 0x85 - subwf r4,W - btfss STATUS,Z - goto lerr - movlw 0x86 - subwf r5,W - btfss STATUS,Z - goto lerr - movlw 0x87 - subwf r6,W - btfss STATUS,Z - goto lerr - movlw 0x88 - subwf r7,W - btfss STATUS,Z - goto lerr - - movlw 0xc0 - subwf br0,W - btfss STATUS,Z - goto lerr - movlw 0xc1 - subwf br1,W - btfss STATUS,Z - goto lerr - movlw 0xc2 - subwf br2,W - btfss STATUS,Z - goto lerr - movlw 0xc3 - subwf br3,W - btfss STATUS,Z - goto lerr - movlw 0xc4 - subwf br4,W - btfss STATUS,Z - goto lerr - movlw 0xc5 - subwf br5,W - btfss STATUS,Z - goto lerr - movlw 0xc6 - subwf br6,W - btfss STATUS,Z - goto lerr - movlw 0xc7 - subwf br7,W - btfss STATUS,Z - goto lerr - movlw 0xc8 - subwf br8,W - btfss STATUS,Z - goto lerr - movlw 0xc9 - subwf br9,W - btfss STATUS,Z - goto lerr - movlw 0xca - subwf br10,W - btfss STATUS,Z - goto lerr - movlw 0xcb - subwf br11,W - btfss STATUS,Z - goto lerr - movlw 0xcc - subwf br12,W - btfss STATUS,Z - goto lerr - movlw 0xcd - subwf br13,W - btfss STATUS,Z - goto lerr - movlw 0xce - subwf br14,W - btfss STATUS,Z - goto lerr - movlw 0xcf - subwf br15,W - btfss STATUS,Z - goto lerr - - - nop - nop - nop - nop - movlw 0x01 - movwf PORTA - nop - nop - nop - nop -good ; Loop in good on success - goto good - nop - nop - nop - nop - -lerr - movlw 0xff - movwf PORTA - - nop - nop - nop - nop -lerr_loop ; Loop in lerr on failure - goto lerr_loop - nop - nop - nop - nop - - END - Index: trunk/scode/sanity2.asm =================================================================== --- trunk/scode/sanity2.asm (revision 6) +++ trunk/scode/sanity2.asm (nonexistent) @@ -1,454 +0,0 @@ -;///////////////////////////////////////////////////////////////////// -;//// //// -;//// Mini-RISC-1 //// -;//// Compliance Test 2 //// -;//// Tests PLC register Rd/Wr //// -;//// //// -;//// Author: Rudolf Usselmann //// -;//// russelmann@hotmail.com //// -;//// //// -;///////////////////////////////////////////////////////////////////// -;//// //// -;//// Copyright (C) 2000 Rudolf Usselmann //// -;//// russelmann@hotmail.com //// -;//// //// -;//// This source file may be used and distributed without //// -;//// restriction provided that this copyright statement is not //// -;//// removed from the file and that any derivative work contains //// -;//// the original copyright notice and the associated disclaimer.//// -;//// //// -;//// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY //// -;//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT //// -;//// LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND //// -;//// FITNESS FOR A PARTICULAR PURPOSE. //// -;//// //// -;///////////////////////////////////////////////////////////////////// - - list p=16c57 - #include p16c5x.inc - -; global Registers -r0 equ 0x8 -r1 equ 0x9 -r2 equ 0xa -r3 equ 0xb -r4 equ 0xc -r5 equ 0xd -r6 equ 0xe -r7 equ 0xf - -; banked Registers -br0 equ 0x10 -br1 equ 0x11 -br2 equ 0x12 -br3 equ 0x13 -br4 equ 0x14 -br5 equ 0x15 -br6 equ 0x16 -br7 equ 0x17 -br8 equ 0x18 -br9 equ 0x19 -br10 equ 0x1a -br11 equ 0x1b -br12 equ 0x1c -br13 equ 0x1d -br14 equ 0x1e -br15 equ 0x1f - - -; PORTB Indicates Test Number -; PORTA Indicates Status: 0 - Running; 1 - done OK; ff - stoped on error - -main ; Main code entry - ; Port IO Test - ; All ports have a Pull up resistor - - ; SETUP all ports - clrw - movwf FSR - movwf PORTA - movwf PORTB - movwf PORTC - tris PORTA - tris PORTB - tris PORTC - - ; ------------------------------- - ; ---- Test the PLC register ---- - ; ------------------------------- - - ; PLC read test 1 TEST 0 - - movlw pclrd1 - movwf r0 - movf PCL,W -pclrd1 subwf r0,W - btfss STATUS,Z - goto lerr - - ; PLC read test 2 TEST 1 - movlw 0x01 - movwf PORTB ; Set Test Number - - movlw pclrd2 - movwf r3 - movf PCL,W -pclrd2 subwf r3,W - btfss STATUS,Z - goto lerr - - ; PLC write test 2 TEST 2 - movlw 0x02 - movwf PORTB ; Set Test Number - - movlw pclwr1 - movwf PCL - - goto lerr - goto lerr - goto lerr -pclwr1 goto pcl1 - goto lerr - goto lerr - goto lerr - -pcl1 - ; PLC write test 2 TEST 3 - movlw 0x03 - movwf PORTB ; Set Test Number - - movlw pclwr2 - movwf PCL - - goto lerr - goto lerr - goto lerr -pclwr2 goto pcl2 - goto lerr - goto lerr - goto lerr - -pcl2 ; Test other instructions that modify PC - ; This are ADDWF PC, BSF PC,X and BCF PC,X - ; (movwf pc already tested above) - - ; PLC write test 3 TEST 4 - ; test addwf PC - movlw 0x04 - movwf PORTB ; Set Test Number - - movlw pcl3b - movwf r0 - movlw pcl3a - subwf r0,W -pcl3a addwf PCL,1 - - goto lerr - goto lerr -pcl3b goto lerr - goto pcl3c - goto lerr - goto lerr - goto lerr -pcl3c - - ; PLC write test 4 TEST 5 - ; test addwf PC - movlw 0x05 - movwf PORTB ; Set Test Number - - movlw pcl4b - movwf br8 - movlw pcl4a - subwf br8,W -pcl4a addwf PCL,1 - - goto lerr - goto lerr -pcl4b goto lerr - goto pcl4c - goto lerr - goto lerr - goto lerr -pcl4c - - ; PLC write test 5 TEST 6 - ; test bsf PC,N - movlw 0x06 - movwf PORTB ; Set Test N - -; allign memory - goto pcl50 - -pcl50 org 0x60 - - bsf PCL,1 ; 60 - goto lerr ; 61 - goto lerr ; 62 - goto pcl5a ; 63 - goto lerr ; 64 - goto lerr ; 65 - goto lerr ; 66 - goto lerr ; 67 - -pcl5a - - ; PLC write test 6 TEST 7 - ; test bsf PC,N - movlw 0x07 - movwf PORTB ; Set Test N - - bsf PCL,2 ; 6A - goto lerr ; 6B - goto lerr ; 6C - goto lerr ; 6D - goto lerr ; 6E - goto pcl6a ; 6F - goto lerr ; 70 - goto lerr ; 71 - -pcl6a - - ; PLC write test 7 TEST 8 - ; test bcf PC,N - movlw 0x08 - movwf PORTB ; Set Test N - - goto pcl7a ; 74 - goto lerr ; 75 - goto lerr ; 76 - goto lerr ; 77 - goto lerr ; 78 - goto pcl7b ; 79 - goto lerr ; 7a - goto lerr ; 7b - -pcl7a - bcf PCL,2 ; 7c - -pcl7b - - - ; Make sure goto works - movlw 0x09 ; TEST 9 - movwf PORTB ; Set Test Number - - - goto gt1 - nop - nop - nop - nop - movlw 0xff - movwf PORTA - nop - nop - nop - nop -gt1 - - ; Make sure call works - movlw 0x0a ; TEST 10 - movwf PORTB ; Set Test Number - - call cal1 - movwf r0 - movlw 0x55 - subwf r0,w - btfss STATUS,Z - goto lerr - - call cal2 - movwf r0 - movlw 0xaa - subwf r0,w - btfss STATUS,Z - goto lerr - - call cal3 - movwf r0 - movlw 0xc3 - subwf r0,w - btfss STATUS,Z - goto lerr - - call cal4 - movwf r0 - movlw 0x3c - subwf r0,w - btfss STATUS,Z - goto lerr - - goto next1 - -cal1 - retlw 0x55 - goto lerr - -cal2 - nop - retlw 0xaa - goto lerr - -cal3 - nop - nop - retlw 0xc3 - goto lerr - -cal4 - nop - nop - nop - retlw 0x3c - goto lerr - -table1 - addwf PCL,F - retlw 0xff - retlw 0xfe - retlw 0xfd - retlw 0xfc - retlw 0xfb - retlw 0xfa - retlw 0xf9 - retlw 0xf8 - retlw 0xf7 - retlw 0xf6 - retlw 0xf5 - goto lerr - goto lerr - goto lerr - goto lerr - goto lerr - goto lerr - -next1 - - - ; Make sure call works (2) - movlw 0x0b ; TEST 11 - movwf PORTB ; Set Test Number - - movlw 0x0 - movwf r0 - call table1 - comf r0,F - subwf r0,F - btfss STATUS,Z - goto lerr - - movlw 0x1 - movwf r0 - call table1 - comf r0,F - subwf r0,F - btfss STATUS,Z - goto lerr - - movlw 0x2 - movwf r0 - call table1 - comf r0,F - subwf r0,F - btfss STATUS,Z - goto lerr - - movlw 0x3 - movwf r0 - call table1 - comf r0,F - subwf r0,F - btfss STATUS,Z - goto lerr - - movlw 0x4 - movwf r0 - call table1 - comf r0,F - subwf r0,F - btfss STATUS,Z - goto lerr - - movlw 0x5 - movwf r0 - call table1 - comf r0,F - subwf r0,F - btfss STATUS,Z - goto lerr - - movlw 0x6 - movwf r0 - call table1 - comf r0,F - subwf r0,F - btfss STATUS,Z - goto lerr - - movlw 0x7 - movwf r0 - call table1 - comf r0,F - subwf r0,F - btfss STATUS,Z - goto lerr - - movlw 0x8 - movwf r0 - call table1 - comf r0,F - subwf r0,F - btfss STATUS,Z - goto lerr - - movlw 0x9 - movwf r0 - call table1 - comf r0,F - subwf r0,F - btfss STATUS,Z - goto lerr - - movlw 0xa - movwf r0 - call table1 - comf r0,F - subwf r0,F - btfss STATUS,Z - goto lerr - - nop - nop - nop - nop - movlw 0x01 - movwf PORTA - nop - nop - nop - nop -good ; Loop in good on success - goto good - nop - nop - nop - nop - -lerr - movlw 0xff - movwf PORTA - - nop - nop - nop - nop -lerr_loop ; Loop in lerr on failure - goto lerr_loop - nop - nop - nop - nop - - END - Index: trunk/scode/rf2.asm =================================================================== --- trunk/scode/rf2.asm (revision 6) +++ trunk/scode/rf2.asm (nonexistent) @@ -1,827 +0,0 @@ -;///////////////////////////////////////////////////////////////////// -;//// //// -;//// Mini-RISC-1 //// -;//// Register File Test 2 //// -;//// Tests Register File //// -;//// //// -;//// Author: Rudolf Usselmann //// -;//// russelmann@hotmail.com //// -;//// //// -;///////////////////////////////////////////////////////////////////// -;//// //// -;//// Copyright (C) 2000 Rudolf Usselmann //// -;//// russelmann@hotmail.com //// -;//// //// -;//// This source file may be used and distributed without //// -;//// restriction provided that this copyright statement is not //// -;//// removed from the file and that any derivative work contains //// -;//// the original copyright notice and the associated disclaimer.//// -;//// //// -;//// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY //// -;//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT //// -;//// LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND //// -;//// FITNESS FOR A PARTICULAR PURPOSE. //// -;//// //// -;///////////////////////////////////////////////////////////////////// - - list p=16c57 - #include p16c5x.inc - -; global Registers -r0 equ 0x8 -r1 equ 0x9 -r2 equ 0xa -r3 equ 0xb -r4 equ 0xc -r5 equ 0xd -r6 equ 0xe -r7 equ 0xf - -; banked Registers -br0 equ 0x10 -br1 equ 0x11 -br2 equ 0x12 -br3 equ 0x13 -br4 equ 0x14 -br5 equ 0x15 -br6 equ 0x16 -br7 equ 0x17 -br8 equ 0x18 -br9 equ 0x19 -br10 equ 0x1a -br11 equ 0x1b -br12 equ 0x1c -br13 equ 0x1d -br14 equ 0x1e -br15 equ 0x1f - - -; PORTB Indicates Test Number -; PORTA Indicates Status: 0 - Running; 1 - done OK; ff - stoped on error - -main ; Main code entry - ; Port IO Test - ; All ports have a Pull up resistor - - ; SETUP all ports - clrw - movwf FSR - movwf PORTA - movwf PORTB - movwf PORTC - tris PORTA - tris PORTB - tris PORTC - - bsf STATUS,5 - - ; --------------------------------------- - ; ---- Test the entire register file ---- - ; --------------------------------------- - - movlw 0x81 - movwf r0 - movlw 0x82 - movwf r1 - movlw 0x83 - movwf r2 - movlw 0x84 - movwf r3 - movlw 0x85 - movwf r4 - movlw 0x86 - movwf r5 - movlw 0x87 - movwf r6 - movlw 0x88 - movwf r7 - - - movlw 0x90 - movwf br0 - movlw 0x91 - movwf br1 - movlw 0x92 - movwf br2 - movlw 0x93 - movwf br3 - movlw 0x94 - movwf br4 - movlw 0x95 - movwf br5 - movlw 0x96 - movwf br6 - movlw 0x97 - movwf br7 - movlw 0x98 - movwf br8 - movlw 0x99 - movwf br9 - movlw 0x9a - movwf br10 - movlw 0x9b - movwf br11 - movlw 0x9c - movwf br12 - movlw 0x9d - movwf br13 - movlw 0x9e - movwf br14 - movlw 0x9f - movwf br15 - - bsf FSR,5 ; Select Register Bank 01 - - movlw 0xa0 - movwf br0 - movlw 0xa1 - movwf br1 - movlw 0xa2 - movwf br2 - movlw 0xa3 - movwf br3 - movlw 0xa4 - movwf br4 - movlw 0xa5 - movwf br5 - movlw 0xa6 - movwf br6 - movlw 0xa7 - movwf br7 - movlw 0xa8 - movwf br8 - movlw 0xa9 - movwf br9 - movlw 0xaa - movwf br10 - movlw 0xab - movwf br11 - movlw 0xac - movwf br12 - movlw 0xad - movwf br13 - movlw 0xae - movwf br14 - movlw 0xaf - movwf br15 - - bcf FSR,5 ; Select Register Bank 10 - bsf FSR,6 - - movlw 0xb0 - movwf br0 - movlw 0xb1 - movwf br1 - movlw 0xb2 - movwf br2 - movlw 0xb3 - movwf br3 - movlw 0xb4 - movwf br4 - movlw 0xb5 - movwf br5 - movlw 0xb6 - movwf br6 - movlw 0xb7 - movwf br7 - movlw 0xb8 - movwf br8 - movlw 0xb9 - movwf br9 - movlw 0xba - movwf br10 - movlw 0xbb - movwf br11 - movlw 0xbc - movwf br12 - movlw 0xbd - movwf br13 - movlw 0xbe - movwf br14 - movlw 0xbf - movwf br15 - - bsf FSR,5 ; Select Register Bank 11 - bsf FSR,6 - - movlw 0xc0 - movwf br0 - movlw 0xc1 - movwf br1 - movlw 0xc2 - movwf br2 - movlw 0xc3 - movwf br3 - movlw 0xc4 - movwf br4 - movlw 0xc5 - movwf br5 - movlw 0xc6 - movwf br6 - movlw 0xc7 - movwf br7 - movlw 0xc8 - movwf br8 - movlw 0xc9 - movwf br9 - movlw 0xca - movwf br10 - movlw 0xcb - movwf br11 - movlw 0xcc - movwf br12 - movlw 0xcd - movwf br13 - movlw 0xce - movwf br14 - movlw 0xcf - movwf br15 - - movlw r0 - movwf FSR - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - - - movlw br0 - movwf FSR - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - - movlw br0 - movwf FSR - bsf FSR,5 - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - - movlw br0 - movwf FSR - bsf FSR,6 - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - - movlw br0 - movwf FSR - bsf FSR,5 - bsf FSR,6 - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - comf INDF,F - incf FSR,F - - ; Register File TEST 1 - movlw 0x01 - movwf PORTB ; Set Test Number - - movlw r0 - movwf FSR - movlw 0x7e - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x7d - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x7c - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x7b - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x7a - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x79 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x78 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x77 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - - movlw br0 - movwf FSR - movlw 0x6f - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x6e - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x6d - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x6c - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x6b - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x6a - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x69 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x68 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x67 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x66 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x65 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x64 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x63 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x62 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x61 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x60 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - - ; Register File TEST 2 - movlw 0x02 - movwf PORTB ; Set Test Number - - movlw br0 - movwf FSR - bsf FSR,5 - movlw 0x5f - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x5e - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x5d - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x5c - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x5b - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x5a - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x59 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x58 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x57 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x56 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x55 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x54 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x53 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x52 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x51 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x50 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - - ; Register File TEST 3 - movlw 0x03 - movwf PORTB ; Set Test Number - - movlw br0 - movwf FSR - bsf FSR,6 - movlw 0x4f - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x4e - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x4d - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x4c - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x4b - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x4a - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x49 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x48 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x47 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x46 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x45 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x44 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x43 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x42 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x41 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x40 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - - ; Register File TEST 4 - movlw 0x04 - movwf PORTB ; Set Test Number - - movlw br0 - movwf FSR - bsf FSR,5 - bsf FSR,6 - movlw 0x3f - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x3e - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x3d - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x3c - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x3b - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x3a - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x39 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x38 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x37 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x36 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x35 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x34 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x33 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x32 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x31 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - movlw 0x30 - incf FSR,F - subwf INDF,W - btfss STATUS,Z - goto lerr - - nop - nop - nop - nop - movlw 0x01 - movwf PORTA - nop - nop - nop - nop -good ; Loop in good on success - goto good - nop - nop - nop - nop - -lerr - movlw 0xff - movwf PORTA - - nop - nop - nop - nop -lerr_loop ; Loop in lerr on failure - goto lerr_loop - nop - nop - nop - nop - - END - Index: trunk/scode/rf3.asm =================================================================== --- trunk/scode/rf3.asm (revision 6) +++ trunk/scode/rf3.asm (nonexistent) @@ -1,338 +0,0 @@ -;///////////////////////////////////////////////////////////////////// -;//// //// -;//// Mini-RISC-1 //// -;//// Register File Test 3 //// -;//// Tests Register File //// -;//// //// -;//// Author: Rudolf Usselmann //// -;//// russelmann@hotmail.com //// -;//// //// -;///////////////////////////////////////////////////////////////////// -;//// //// -;//// Copyright (C) 2000 Rudolf Usselmann //// -;//// russelmann@hotmail.com //// -;//// //// -;//// This source file may be used and distributed without //// -;//// restriction provided that this copyright statement is not //// -;//// removed from the file and that any derivative work contains //// -;//// the original copyright notice and the associated disclaimer.//// -;//// //// -;//// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY //// -;//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT //// -;//// LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND //// -;//// FITNESS FOR A PARTICULAR PURPOSE. //// -;//// //// -;///////////////////////////////////////////////////////////////////// - - list p=16c57 - #include p16c5x.inc - -; global Registers -r0 equ 0x8 -r1 equ 0x9 -r2 equ 0xa -r3 equ 0xb -r4 equ 0xc -r5 equ 0xd -r6 equ 0xe -r7 equ 0xf - -; banked Registers -br0 equ 0x10 -br1 equ 0x11 -br2 equ 0x12 -br3 equ 0x13 -br4 equ 0x14 -br5 equ 0x15 -br6 equ 0x16 -br7 equ 0x17 -br8 equ 0x18 -br9 equ 0x19 -br10 equ 0x1a -br11 equ 0x1b -br12 equ 0x1c -br13 equ 0x1d -br14 equ 0x1e -br15 equ 0x1f - - -; PORTB Indicates Test Number -; PORTA Indicates Status: 0 - Running; 1 - done OK; ff - stoped on error - -main ; Main code entry - ; Port IO Test - ; All ports have a Pull up resistor - - ; SETUP all ports - clrw - movwf FSR - movwf PORTA - movwf PORTB - movwf PORTC - tris PORTA - tris PORTB - tris PORTC - - ; --------------------------------------- - ; ---- Test RMW on Register fil ---- - ; --------------------------------------- - - movlw 0x01 ; TEST 1 - movwf PORTB ; Set Test Number - - movlw 0xfc - movwf r0 - incf r0,F - incf r0,F - incf r0,F - incf r0,F - btfss STATUS,Z - goto lerr - - movlw 0xfc - movwf br8 - incf br8,F - incf br8,F - incf br8,F - incf br8,F - btfss STATUS,Z - goto lerr - - movlw 0x02 ; TEST 2 - movwf PORTB ; Set Test Number - - movlw r1 - movwf FSR - movlw 0xfc - movwf INDF - incf INDF,F - incf INDF,F - incf INDF,F - incf INDF,F - btfss STATUS,Z - goto lerr - - movlw br9 - movwf FSR - movlw 0xfc - movwf INDF - incf INDF,F - incf INDF,F - incf INDF,F - incf INDF,F - btfss STATUS,Z - goto lerr - - - - movlw 0x03 ; TEST 3 - movwf PORTB ; Set Test Number - - movlw 0x04 - movwf r0 - decf r0,F - decf r0,F - decf r0,F - decf r0,F - btfss STATUS,Z - goto lerr - - - movlw 0x04 - movwf br0 - decf br0,F - decf br0,F - decf br0,F - decf br0,F - btfss STATUS,Z - goto lerr - - - movlw 0x04 ; TEST 4 - movwf PORTB ; Set Test Number - - movlw r1 - movwf FSR - movlw 0x04 - movwf INDF - decf INDF,F - decf INDF,F - decf INDF,F - decf INDF,F - btfss STATUS,Z - goto lerr - - movlw br9 - movwf FSR - movlw 0x04 - movwf INDF - decf INDF,F - decf INDF,F - decf INDF,F - decf INDF,F - btfss STATUS,Z - goto lerr - - - movlw 0x05 ; TEST 5 - movwf PORTB ; Set Test Number - - movlw 0xfc - movwf r4 - incfsz r4,F - incfsz r4,F - incfsz r4,F - incfsz r4,F - goto lerr - - movlw 0xfc - movwf br8 - incfsz br8,F - incfsz br8,F - incfsz br8,F - incfsz br8,F - goto lerr - - - movlw 0x06 ; TEST 6 - movwf PORTB ; Set Test Number - - movlw r1 - movwf FSR - movlw 0xfc - movwf INDF - incfsz INDF,F - incfsz INDF,F - incfsz INDF,F - incfsz INDF,F - goto lerr - - movlw br9 - movwf FSR - movlw 0xfc - movwf INDF - incfsz INDF,F - incfsz INDF,F - incfsz INDF,F - incfsz INDF,F - goto lerr - - movlw 0x07 ; TEST 7 - movwf PORTB ; Set Test Number - - movlw 0x04 - movwf r0 - decfsz r0,F - decfsz r0,F - decfsz r0,F - decfsz r0,F - goto lerr - - - movlw 0x04 - movwf br0 - decfsz br0,F - decfsz br0,F - decfsz br0,F - decfsz br0,F - goto lerr - - - movlw 0x08 ; TEST 8 - movwf PORTB ; Set Test Number - - movlw r1 - movwf FSR - movlw 0x04 - movwf INDF - decfsz INDF,F - decfsz INDF,F - decfsz INDF,F - decfsz INDF,F - goto lerr - - movlw br9 - movwf FSR - movlw 0x04 - movwf INDF - decfsz INDF,F - decfsz INDF,F - decfsz INDF,F - decfsz INDF,F - goto lerr - - - movlw 0x09 ; TEST 9 - movwf PORTB ; Set Test Number - - movlw 0xfc - movwf FSR - incf FSR,F - incf FSR,F - incf FSR,F - incf FSR,F - btfss STATUS,Z - goto lerr - - movlw 0x04 - movwf FSR - movlw 0x7f - decf FSR,F - decf FSR,F - decf FSR,F - decf FSR,F - andwf FSR,F - btfss STATUS,Z - goto lerr - - movlw 0x0a ; TEST 10 - movwf PORTB ; Set Test Number - - movlw 0xfc - movwf STATUS - movlw 0x18 - incf STATUS,F - incf STATUS,F - incf STATUS,F - incf STATUS,F - subwf STATUS,W - btfss STATUS,Z - goto lerr - - - - - nop - nop - nop - nop - movlw 0x01 - movwf PORTA - nop - nop - nop - nop -good ; Loop in good on success - goto good - nop - nop - nop - nop - -lerr - movlw 0xff - movwf PORTA - - nop - nop - nop - nop -lerr_loop ; Loop in lerr on failure - goto lerr_loop - nop - nop - nop - nop - - END - Index: trunk/scode/tmr_wdt.rom =================================================================== --- trunk/scode/tmr_wdt.rom (revision 6) +++ trunk/scode/tmr_wdt.rom (nonexistent) @@ -1,63 +0,0 @@ - -@000 040 -@001 024 -@002 025 -@003 026 -@004 027 -@005 005 -@006 006 -@007 007 -@008 C01 -@009 026 -@00A C00 -@00B 002 -@00C 021 -@00D 004 -@00E 000 -@00F 000 -@010 000 -@011 000 -@012 040 -@013 029 -@014 040 -@015 028 -@016 201 -@017 2E8 -@018 A16 -@019 2E9 -@01A A14 -@01B 000 -@01C 000 -@01D 000 -@01E 000 -@01F 000 -@020 000 -@021 040 -@022 021 -@023 004 -@024 000 -@025 000 -@026 000 -@027 000 -@028 C01 -@029 025 -@02A 000 -@02B 000 -@02C 000 -@02D 000 -@02E A2E -@02F 000 -@030 000 -@031 000 -@032 000 -@033 CFF -@034 025 -@035 000 -@036 000 -@037 000 -@038 000 -@039 A39 -@03A 000 -@03B 000 -@03C 000 -@03D 000 Index: trunk/scode/hex2v.c =================================================================== --- trunk/scode/hex2v.c (revision 6) +++ trunk/scode/hex2v.c (nonexistent) @@ -1,125 +0,0 @@ -/* *********************************************************************** - The Free IP Project - Free-RISC8 -- Verilog 8-bit Microcontroller - (c) 1999, The Free IP Project and Thomas Coonan - - - FREE IP GENERAL PUBLIC LICENSE - TERMS AND CONDITIONS FOR USE, COPYING, DISTRIBUTION, AND MODIFICATION - - 1. You may copy and distribute verbatim copies of this core, as long - as this file, and the other associated files, remain intact and - unmodified. Modifications are outlined below. - 2. You may use this core in any way, be it academic, commercial, or - military. Modified or not. - 3. Distribution of this core must be free of charge. Charging is - allowed only for value added services. Value added services - would include copying fees, modifications, customizations, and - inclusion in other products. - 4. If a modified source code is distributed, the original unmodified - source code must also be included (or a link to the Free IP web - site). In the modified source code there must be clear - identification of the modified version. - 5. Visit the Free IP web site for additional information. - http://www.free-ip.com - -*********************************************************************** */ - -// Intel HEX to Verilog converter. -// -// Usage: -// hex2v -// -// You probably want to simply redirect the output into a file. -// -#include -#include -#include - -// Input and Output file streams. -FILE *fpi; - -// Well.. Let's read stuff in completely before outputting.. Programs -// should be pretty small.. -// -#define MAX_MEMORY_SIZE 2048 -struct { - unsigned int nAddress; - unsigned int byData; -} Memory[MAX_MEMORY_SIZE]; - -char szLine[80]; -unsigned int start_address, address, ndata_bytes, ndata_words; -unsigned int data; -unsigned int nMemoryCount; - -int main (int argc, char *argv[]) -{ - int i; - - if (argc != 2) { - printf ("\nThe Synthetic PIC --- Intel HEX File to Verilog memory file"); - printf ("\nUsage: hex2verilog "); - printf ("\n"); - return 0; - } - - - // Open input HEX file - fpi=fopen(argv[1], "r"); - if (!fpi) { - printf("\nCan't open input file %s.\n", argv[1]); - return 1; - } - - // Read in the HEX file - // - // !! Note, that things are a little strange for us, because the PIC is - // a 12-bit instruction, addresses are 16-bit, and the hex format is - // 8-bit oriented!! - // - nMemoryCount = 0; - while (!feof(fpi)) { - // Get one Intel HEX line - fgets (szLine, 80, fpi); - if (strlen(szLine) >= 10) { - // This is the PIC, with its 12-bit "words". We're interested in these - // words and not the bytes. Read 4 hex digits at a time for each - // address. - // - sscanf (&szLine[1], "%2x%4x", &ndata_bytes, &start_address); - if (start_address >= 0 && start_address <= 20000 && ndata_bytes > 0) { - // Suck up data bytes starting at 9th byte. - i = 9; - - // Words.. not bytes.. - ndata_words = ndata_bytes/2; - start_address = start_address/2; - - // Spit out all the data that is supposed to be on this line. - for (address = start_address; address < start_address + ndata_words; address++) { - // Scan out 4 hex digits for a word. This will be one address. - sscanf (&szLine[i], "%04x", &data); - - // Need to swap bytes... - data = ((data >> 8) & 0x00ff) | ((data << 8) & 0xff00); - i += 4; - - // Store in our memory buffer - Memory[nMemoryCount].nAddress = address; - Memory[nMemoryCount].byData = data; - nMemoryCount++; - } - } - } - } - fclose (fpi); - - // Now output the Verilog $readmemh format! - // - for (i = 0; i < nMemoryCount; i++) { - printf ("\n@%03X %03X", Memory[i].nAddress, Memory[i].byData); - } - printf ("\n"); - -} Index: minirisc/trunk/verilog/core/primitives.v =================================================================== --- minirisc/trunk/verilog/core/primitives.v (nonexistent) +++ minirisc/trunk/verilog/core/primitives.v (revision 7) @@ -0,0 +1,218 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Mini-RISC-1 //// +//// Primitives //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// D/L from: http://www.opencores.org/cores/minirisc/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: primitives.v,v 1.3 2002-10-01 12:44:24 rudi Exp $ +// +// $Date: 2002-10-01 12:44:24 $ +// $Revision: 1.3 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.2 2002/09/27 15:35:40 rudi +// Minor update to newer devices ... +// +// +// +// +// +// +// +// +// +// +// + +`timescale 1ns / 10ps + +// Mux 4:1 8 bits wide +module mux4_8(sel, in0, in1, in2, in3, out); +input [1:0] sel; +input [7:0] in0, in1, in2, in3; +output [7:0] out; + +reg [7:0] out; + +always @(sel or in0 or in1 or in2 or in3) + case(sel) // synopsys full_case parallel_case + 0: out = in0; + 1: out = in1; + 2: out = in2; + 3: out = in3; + endcase + +endmodule + +// 8 bit comparator +module cmp8_eq(a,b,eq); +input [7:0] a,b; +output eq; + +assign eq = (a==b); + +endmodule + +// MUX 2:1 7 bits wide +module mux2_7(sel, in0, in1, out); +input sel; +input [6:0] in0, in1; +output [6:0] out; + +assign out = sel ? in1 : in0; + +endmodule + +// Mux 8:1 1 bit wide +module mux8_1( sel, in, out); +input [2:0] sel; +input [7:0] in; +output out; + +assign out = in[sel]; + +endmodule + +// Mux 2:1 8 bits wide +module mux2_8(sel, in0, in1, out); +input sel; +input [7:0] in0, in1; +output [7:0] out; + +assign out = sel ? in1 : in0; + +endmodule + +// Mux 8:1 8 bits wide +module mux8_8(sel, in0, in1, in2, in3, in4, in5, in6, in7, out); +input [2:0] sel; +input [7:0] in0, in1, in2, in3, in4, in5, in6, in7; +output [7:0] out; + +reg [7:0] out; + +always @(sel or in0 or in1 or in2 or in3 or in4 or in5 or in6 or in7) + case(sel) // synopsys full_case parallel_case + 3'd0: out = in0; + 3'd1: out = in1; + 3'd2: out = in2; + 3'd3: out = in3; + 3'd4: out = in4; + 3'd5: out = in5; + 3'd6: out = in6; + 3'd7: out = in7; + endcase + +endmodule + +// Mux 2:1 11 bits wide +module mux2_11(sel, in0, in1, out); +input sel; +input [10:0] in0, in1; +output [10:0] out; + +assign out = sel ? in1 : in0; + +endmodule + + +// 8bit Add/Sub with carry/borrow out +module add_sub8_co(sub, opa, opb, out, co); +input sub; +input [7:0] opa, opb; +output [7:0] out; +output co; + +assign {co, out} = sub ? (opa - opb) : (opa + opb); + +endmodule + +// 11 bit incrementer +module inc11(in, out); +input [10:0] in; +output [10:0] out; + +assign out = in + 11'h1; + +endmodule + +// 8 bit incrementer +module inc8(in, out); +input [7:0] in; +output [7:0] out; + +assign out = in + 8'h1; + +endmodule + +// A Basic Synchrounous FIFO (4 entries deep) +module sfifo4x11(clk, push, din, pop, dout); +input clk; +input push; +input [10:0] din; +input pop; +output [10:0] dout; + +reg [10:0] stack1, stack2, stack3, stack4; + +assign dout = stack1; + +always @(posedge clk) + begin + if(push) // PUSH stack + begin + stack4 <= #1 stack3; + stack3 <= #1 stack2; + stack2 <= #1 stack1; + stack1 <= #1 din; + end + if(pop) // POP stack + begin + stack1 <= #1 stack2; + stack2 <= #1 stack3; + stack3 <= #1 stack4; + end + end + +endmodule + + Index: minirisc/trunk/verilog/core/alu.v =================================================================== --- minirisc/trunk/verilog/core/alu.v (nonexistent) +++ minirisc/trunk/verilog/core/alu.v (revision 7) @@ -0,0 +1,161 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Mini-RISC-1 //// +//// ALU //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// D/L from: http://www.opencores.org/cores/minirisc/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: alu.v,v 1.3 2002-10-01 12:44:24 rudi Exp $ +// +// $Date: 2002-10-01 12:44:24 $ +// $Revision: 1.3 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.2 2002/09/27 15:35:40 rudi +// Minor update to newer devices ... +// +// +// +// +// +// +// +// +// +// +// + + +`timescale 1ns / 10ps + +module alu(s1, s2, mask, out, op, c_in, c, dc, z); +input [7:0] s1, s2, mask; +output [7:0] out; +input [3:0] op; +input c_in; +output c, dc, z; + +parameter ALU_ADD = 4'h0, + ALU_SUB = 4'h1, + ALU_INC = 4'h2, + ALU_DEC = 4'h3, + + ALU_AND = 4'h4, + ALU_CLR = 4'h5, + ALU_NOT = 4'h6, + ALU_IOR = 4'h7, + ALU_MOV = 4'h8, + ALU_MOVW = 4'h9, + ALU_RLF = 4'ha, + ALU_RRF = 4'hb, + ALU_SWP = 4'hc, + ALU_XOR = 4'hd, + ALU_BCF = 4'he, + ALU_BSF = 4'hf; + +wire [7:0] out; +wire co, bo; +wire c; +wire z; +wire [5:0] tmp_add; +wire borrow_dc; + +wire [7:0] add_sub_out; +wire add_sub_sel; +wire [7:0] s2_a; +wire [8:0] rlf_out, rrf_out; +wire [7:0] out_next1, out_next2, out_next3; + +/* +reg cout; +reg [7:0] out_t; +always @(op or s1 or s2 or mask or c_in) + begin + cout = 0; + case(op) // synopsys full_case parallel_case + ALU_ADD: {cout, out_t} = s1 + s2; + ALU_AND: out_t = s1 & s2; + ALU_CLR: out_t = 8'h00; + ALU_NOT: out_t = ~s1; + ALU_DEC: out_t = s1 - 1; + ALU_INC: out_t = s1 + 1; + ALU_IOR: out_t = s1 | s2; + ALU_MOV: out_t = s1; + ALU_MOVW: out_t = s2; + ALU_RLF: {cout, out_t} = {s1[7:0], c_in}; + ALU_RRF: {cout, out_t} = {s1[0], c_in, s1[7:1]}; + ALU_SUB: {cout, out_t} = s1 - s2; + ALU_SWP: out_t = {s1[3:0], s1[7:4]}; + ALU_XOR: out_t = s1 ^ s2; + ALU_BCF: out_t = s1 & ~mask; + ALU_BSF: out_t = s1 | mask; + endcase + end +*/ + +assign rlf_out = {s1[7:0], c_in}; +assign rrf_out = {s1[0], c_in, s1[7:1]}; + +assign add_sub_sel = (op[3:2]==2'b0); + +mux4_8 u2( .sel(op[3:2]), .in0(add_sub_out), .in1(out_next1), .in2(out_next2), .in3(out_next3), .out(out) ); +mux4_8 u3( .sel(op[1:0]), .in0(s1 & s2), .in1(8'h00), .in2(~s1), .in3(s1 | s2), .out(out_next1) ); +mux4_8 u4( .sel(op[1:0]), .in0(s1), .in1(s2), .in2(rlf_out[7:0]), .in3(rrf_out[7:0]), .out(out_next2) ); +mux4_8 u5( .sel(op[1:0]), .in0({s1[3:0], s1[7:4]}), .in1(s1^s2), .in2(s1 & ~mask), .in3(s1 | mask), .out(out_next3) ); + +mux2_8 u0( .sel(op[1]), .in0(s2), .in1(8'h01), .out(s2_a) ); + +add_sub8_co u1( .sub(op[0]), .opa(s1), .opb(s2_a), .out(add_sub_out), .co(co) ); + +// C bit generation +assign c = add_sub_sel ? co : op[0] ? rrf_out[8] : rlf_out[8]; + +// Z Bit generation +assign z = (out==8'h0); + +// DC Bit geberation +// This section is really bad, but not in the critical path, +// so I leave it alone for now .... +assign borrow_dc = s1[3:0] >= s2[3:0]; +assign tmp_add = s1[3:0] + s2[3:0]; +assign dc = (op==ALU_SUB) ? borrow_dc : tmp_add[4]; + +endmodule Index: minirisc/trunk/verilog/core/register_file.v =================================================================== --- minirisc/trunk/verilog/core/register_file.v (nonexistent) +++ minirisc/trunk/verilog/core/register_file.v (revision 7) @@ -0,0 +1,124 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Mini-RISC-1 //// +//// Register File //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// D/L from: http://www.opencores.org/cores/minirisc/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: register_file.v,v 1.3 2002-10-01 12:44:24 rudi Exp $ +// +// $Date: 2002-10-01 12:44:24 $ +// $Revision: 1.3 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.2 2002/09/27 15:35:40 rudi +// Minor update to newer devices ... +// +// +// +// +// +// +// +// +// +// +// + +`timescale 1ns / 10ps + +module register_file( clk, rst, + rf_rd_bnk, rf_rd_addr, rf_rd_data, + rf_we, rf_wr_bnk, rf_wr_addr, rf_wr_data); + +input clk,rst; +input [1:0] rf_rd_bnk; +input [4:0] rf_rd_addr; +output [7:0] rf_rd_data; +input rf_we; +input [1:0] rf_wr_bnk; +input [4:0] rf_wr_addr; +input [7:0] rf_wr_data; + +wire clk; +wire [7:0] rf_rd_data; +wire [6:0] rd_addr; +wire [6:0] wr_addr; +wire [7:0] rf_rd_data_mem; +reg [7:0] wr_data_tmp; +reg rd_wr_addr_equal; + +// Simple Read & Write Address Mapping to memory address +assign rd_addr[6] = ~rf_rd_addr[4]; +assign rd_addr[5:3] = rf_rd_addr[4] ? {rf_rd_bnk, rf_rd_addr[3]} : 3'h0; +assign rd_addr[2:0] = rf_rd_addr[2:0]; + +assign wr_addr[6] = ~rf_wr_addr[4]; +assign wr_addr[5:3] = rf_wr_addr[4] ? {rf_wr_bnk, rf_wr_addr[3]} : 3'h0; +assign wr_addr[2:0] = rf_wr_addr[2:0]; + +// This logic is to bypass the register file if we are reading and +// writing (in previous instruction) to the same register +always @(posedge clk) + rd_wr_addr_equal <= #1 (rd_addr==wr_addr) & rf_we; + +assign rf_rd_data = rd_wr_addr_equal ? wr_data_tmp : rf_rd_data_mem; + +always @(posedge clk) + wr_data_tmp <= #1 rf_wr_data; + +// This is the actual Memory +generic_dpram #(7,8) rf0( + .rclk( clk ), + .rrst( rst ), + .rce( 1'b1 ), + .oe( 1'b1 ), + .raddr( rd_addr ), + .do( rf_rd_data_mem ), + .wclk( clk ), + .wrst( rst ), + .wce( 1'b1 ), + .we( rf_we ), + .waddr( wr_addr ), + .di( rf_wr_data ) + ); + +endmodule Index: minirisc/trunk/verilog/core/primitives_xilinx.v =================================================================== --- minirisc/trunk/verilog/core/primitives_xilinx.v (nonexistent) +++ minirisc/trunk/verilog/core/primitives_xilinx.v (revision 7) @@ -0,0 +1,1091 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Mini-RISC-1 //// +//// Prescaler and Wachdog Counter //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// D/L from: http://www.opencores.org/cores/minirisc/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: primitives_xilinx.v,v 1.3 2002-10-01 12:44:24 rudi Exp $ +// +// $Date: 2002-10-01 12:44:24 $ +// $Revision: 1.3 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.2 2002/09/27 15:35:40 rudi +// Minor update to newer devices ... +// +// +// +// +// +// +// +// +// +// +// + +`timescale 1ns / 10ps + +// LIB_TAG +// synopsys translate_off +`include "XilinxCoreLib/C_ADDSUB_V1_0.v" +`include "XilinxCoreLib/C_MUX_BUS_V1_0.v" +`include "XilinxCoreLib/C_COMPARE_V1_0.v" +`include "XilinxCoreLib/C_MUX_BIT_V1_0.v" +`include "XilinxCoreLib/C_MEM_DP_BLOCK_V1_0.v" +`include "XilinxCoreLib/C_REG_FD_V1_0.v" +// synopsys translate_on +// LIB_TAG_END + + +// Mux 4:1 8 bits wide +module mux4_8(sel, in0, in1, in2, in3, out); +input [1:0] sel; +input [7:0] in0, in1, in2, in3; +output [7:0] out; + +// INST_TAG +xilinx_mux4_8 u0 ( + .MA0(in0[0]), + .MA1(in0[1]), + .MA2(in0[2]), + .MA3(in0[3]), + .MA4(in0[4]), + .MA5(in0[5]), + .MA6(in0[6]), + .MA7(in0[7]), + + .MB0(in1[0]), + .MB1(in1[1]), + .MB2(in1[2]), + .MB3(in1[3]), + .MB4(in1[4]), + .MB5(in1[5]), + .MB6(in1[6]), + .MB7(in1[7]), + + .MC0(in2[0]), + .MC1(in2[1]), + .MC2(in2[2]), + .MC3(in2[3]), + .MC4(in2[4]), + .MC5(in2[5]), + .MC6(in2[6]), + .MC7(in2[7]), + + .MD0(in3[0]), + .MD1(in3[1]), + .MD2(in3[2]), + .MD3(in3[3]), + .MD4(in3[4]), + .MD5(in3[5]), + .MD6(in3[6]), + .MD7(in3[7]), + + .S0(sel[0]), + .S1(sel[1]), + + .O0(out[0]), + .O1(out[1]), + .O2(out[2]), + .O3(out[3]), + .O4(out[4]), + .O5(out[5]), + .O6(out[6]), + .O7(out[7]) ); +// INST_TAG_END + +endmodule + +/* +// MOD_TAG +module xilinx_mux4_8 (MA,MB,MC,MD,S,O); // synthesis black_box +input [7:0] MA; +input [7:0] MB; +input [7:0] MC; +input [7:0] MD; +input [1:0] S; +output [7:0] O; + +// synopsys translate_off +// synthesis translate_off + C_MUX_BUS_V1_0 #( + "00000000", + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 4, + 0, + 2, + "00000000", + 0, + 1, + 8) + inst ( + .MA(MA), + .MB(MB), + .MC(MC), + .MD(MD), + .S(S), + .O(O)); +// synthesis translate_on +// synopsys translate_on +endmodule +// MOD_TAG_END +*/ + +// 8 bit comparator +module cmp8_eq(a,b,eq); +input [7:0] a,b; +output eq; + +// INST_TAG +xilinx_cmp8_eq u0 ( + .A0(a[0]), + .A1(a[1]), + .A2(a[2]), + .A3(a[3]), + .A4(a[4]), + .A5(a[5]), + .A6(a[6]), + .A7(a[7]), + + .B0(b[0]), + .B1(b[1]), + .B2(b[2]), + .B3(b[3]), + .B4(b[4]), + .B5(b[5]), + .B6(b[6]), + .B7(b[7]), + + .A_EQ_B(eq) ); +// INST_TAG_END + +endmodule + +/* +// MOD_TAG +module xilinx_cmp8_eq (A,B,A_EQ_B); // synthesis black_box +input [7 : 0] A; +input [7 : 0] B; +output A_EQ_B; + +// synopsys translate_off +// synthesis translate_off + C_COMPARE_V1_0 #( + "0", + 0, + "0", + 1, + 1, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 8) + inst ( + .A(A), + .B(B), + .A_EQ_B(A_EQ_B)); +// synthesis translate_on +// synopsys translate_on +endmodule +// MOD_TAG_END +*/ + +// MUX 2:1 7 bits wide +module mux2_7(sel, in0, in1, out); +input sel; +input [6:0] in0, in1; +output [6:0] out; + +// INST_TAG +xilinx_mux2_7 u0 ( + .MA0(in0[0]), + .MA1(in0[1]), + .MA2(in0[2]), + .MA3(in0[3]), + .MA4(in0[4]), + .MA5(in0[5]), + .MA6(in0[6]), + + .MB0(in1[0]), + .MB1(in1[1]), + .MB2(in1[2]), + .MB3(in1[3]), + .MB4(in1[4]), + .MB5(in1[5]), + .MB6(in1[6]), + + .S0(sel), + + .O0(out[0]), + .O1(out[1]), + .O2(out[2]), + .O3(out[3]), + .O4(out[4]), + .O5(out[5]), + .O6(out[6]) ); +// INST_TAG_END + +endmodule + +/* +// MOD_TAG +module xilinx_mux2_7 (MA,MB,S,O); // synthesis black_box +input [6 : 0] MA; +input [6 : 0] MB; +input [0 : 0] S; +output [6 : 0] O; + +// synopsys translate_off +// synthesis translate_off + C_MUX_BUS_V1_0 #( + "0000000", + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 2, + 0, + 1, + "0000000", + 0, + 1, + 7) + inst ( + .MA(MA), + .MB(MB), + .S(S), + .O(O)); +// synthesis translate_on +// synopsys translate_on +endmodule +// MOD_TAG_END +*/ + + +// Mux 8:1 1 bit wide +module mux8_1( sel, in, out); +input [2:0] sel; +input [7:0] in; +output out; + +// INST_TAG +xilinx_mux8_1 u0 ( + .M0(in[0]), + .M1(in[1]), + .M2(in[2]), + .M3(in[3]), + .M4(in[4]), + .M5(in[5]), + .M6(in[6]), + .M7(in[7]), + + .S0(sel[0]), + .S1(sel[1]), + .S2(sel[2]), + + + .O(out)); +// INST_TAG_END + +endmodule + +/* +// MOD_TAG +module xilinx_mux8_1 (M,S,O); // synthesis black_box +input [7 : 0] M; +input [2 : 0] S; +output O; + +// synopsys translate_off +// synthesis translate_off + C_MUX_BIT_V1_0 #( + "0", + 1, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 8, + 3, + "0", + 0, + 1) + inst ( + .M(M), + .S(S), + .O(O)); +// synthesis translate_on +// synopsys translate_on +endmodule +// MOD_TAG_END +*/ + +// Mux 2:1 8 bits wide +module mux2_8(sel, in0, in1, out); +input sel; +input [7:0] in0, in1; +output [7:0] out; + +// INST_TAG +xilinx_mux2_8 u0( + .MA0(in0[0]), + .MA1(in0[1]), + .MA2(in0[2]), + .MA3(in0[3]), + .MA4(in0[4]), + .MA5(in0[5]), + .MA6(in0[6]), + .MA7(in0[7]), + + .MB0(in1[0]), + .MB1(in1[1]), + .MB2(in1[2]), + .MB3(in1[3]), + .MB4(in1[4]), + .MB5(in1[5]), + .MB6(in1[6]), + .MB7(in1[7]), + + .S0(sel), + + .O0(out[0]), + .O1(out[1]), + .O2(out[2]), + .O3(out[3]), + .O4(out[4]), + .O5(out[5]), + .O6(out[6]), + .O7(out[7]) ); +// INST_TAG_END + +endmodule + + +/* +// MOD_TAG +module xilinx_mux2_8 (MA, MB, S, O); // synthesis black_box +input [7 : 0] MA; +input [7 : 0] MB; +input [0 : 0] S; +output [7 : 0] O; + +// synopsys translate_off +// synthesis translate_off + C_MUX_BUS_V1_0 #( + "00000000", + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 2, + 0, + 1, + "00000000", + 0, + 1, + 8) + inst ( + .MA(MA), + .MB(MB), + .S(S), + .O(O)); +// synthesis translate_on +// synopsys translate_on +endmodule +// MOD_TAG_END +*/ + +// Mux 8:1 8 bits wide +module mux8_8(sel, in0, in1, in2, in3, in4, in5, in6, in7, out); +input [2:0] sel; +input [7:0] in0, in1, in2, in3, in4, in5, in6, in7; +output [7:0] out; + +// INST_TAG +xilinx_mux8_8 u0 ( + .MA0(in0[0]), + .MA1(in0[1]), + .MA2(in0[2]), + .MA3(in0[3]), + .MA4(in0[4]), + .MA5(in0[5]), + .MA6(in0[6]), + .MA7(in0[7]), + + .MB0(in1[0]), + .MB1(in1[1]), + .MB2(in1[2]), + .MB3(in1[3]), + .MB4(in1[4]), + .MB5(in1[5]), + .MB6(in1[6]), + .MB7(in1[7]), + + .MC0(in2[0]), + .MC1(in2[1]), + .MC2(in2[2]), + .MC3(in2[3]), + .MC4(in2[4]), + .MC5(in2[5]), + .MC6(in2[6]), + .MC7(in2[7]), + + .MD0(in3[0]), + .MD1(in3[1]), + .MD2(in3[2]), + .MD3(in3[3]), + .MD4(in3[4]), + .MD5(in3[5]), + .MD6(in3[6]), + .MD7(in3[7]), + + .ME0(in4[0]), + .ME1(in4[1]), + .ME2(in4[2]), + .ME3(in4[3]), + .ME4(in4[4]), + .ME5(in4[5]), + .ME6(in4[6]), + .ME7(in4[7]), + + .MF0(in5[0]), + .MF1(in5[1]), + .MF2(in5[2]), + .MF3(in5[3]), + .MF4(in5[4]), + .MF5(in5[5]), + .MF6(in5[6]), + .MF7(in5[7]), + + .MG0(in6[0]), + .MG1(in6[1]), + .MG2(in6[2]), + .MG3(in6[3]), + .MG4(in6[4]), + .MG5(in6[5]), + .MG6(in6[6]), + .MG7(in6[7]), + + .MH0(in7[0]), + .MH1(in7[1]), + .MH2(in7[2]), + .MH3(in7[3]), + .MH4(in7[4]), + .MH5(in7[5]), + .MH6(in7[6]), + .MH7(in7[7]), + + .S0(sel[0]), + .S1(sel[1]), + .S2(sel[2]), + + .O0(out[0]), + .O1(out[1]), + .O2(out[2]), + .O3(out[3]), + .O4(out[4]), + .O5(out[5]), + .O6(out[6]), + .O7(out[7]) ); + +// INST_TAG_END + +endmodule + +/* +// MOD_TAG +module xilinx_mux8_8 (MA,MB,MC,MD,ME,MF,MG,MH,S,O); // synthesis black_box +input [7 : 0] MA; +input [7 : 0] MB; +input [7 : 0] MC; +input [7 : 0] MD; +input [7 : 0] ME; +input [7 : 0] MF; +input [7 : 0] MG; +input [7 : 0] MH; +input [2 : 0] S; +output [7 : 0] O; + +// synopsys translate_off +// synthesis translate_off + C_MUX_BUS_V1_0 #( + "00000000", + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 8, + 0, + 3, + "00000000", + 0, + 1, + 8) + inst ( + .MA(MA), + .MB(MB), + .MC(MC), + .MD(MD), + .ME(ME), + .MF(MF), + .MG(MG), + .MH(MH), + .S(S), + .O(O)); +// synthesis translate_on +// synopsys translate_on +endmodule +// MOD_TAG_END +*/ + +// Mux 2:1 11 bits wide +module mux2_11(sel, in0, in1, out); +input sel; +input [10:0] in0, in1; +output [10:0] out; + +// INST_TAG +xilinx_mux2_11 u0 ( + .MA0(in0[0]), + .MA1(in0[1]), + .MA2(in0[2]), + .MA3(in0[3]), + .MA4(in0[4]), + .MA5(in0[5]), + .MA6(in0[6]), + .MA7(in0[7]), + .MA8(in0[8]), + .MA9(in0[9]), + .MA10(in0[10]), + + .MB0(in1[0]), + .MB1(in1[1]), + .MB2(in1[2]), + .MB3(in1[3]), + .MB4(in1[4]), + .MB5(in1[5]), + .MB6(in1[6]), + .MB7(in1[7]), + .MB8(in1[8]), + .MB9(in1[9]), + .MB10(in1[10]), + + .S0(sel), + + .O0(out[0]), + .O1(out[1]), + .O2(out[2]), + .O3(out[3]), + .O4(out[4]), + .O5(out[5]), + .O6(out[6]), + .O7(out[7]), + .O8(out[8]), + .O9(out[9]), + .O10(out[10]) ); +// INST_TAG_END + +endmodule + +/* +// MOD_TAG +module xilinx_mux2_11 (MA,MB,S,O); // synthesis black_box +input [10 : 0] MA; +input [10 : 0] MB; +input [0 : 0] S; +output [10 : 0] O; + +// synopsys translate_off +// synthesis translate_off + C_MUX_BUS_V1_0 #( + "00000000000", + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 2, + 0, + 1, + "00000000000", + 0, + 1, + 11) + inst ( + .MA(MA), + .MB(MB), + .S(S), + .O(O)); +// synthesis translate_on +// synopsys translate_on +endmodule +// MOD_TAG_END +*/ + + +// 8bit Add/Sub with carry/borrow out +module add_sub8_co(sub, opa, opb, out, co); +input sub; +input [7:0] opa, opb; +output [7:0] out; +output co; + +wire add; +assign add = ~sub; + +// INST_TAG +xilinx_add_sub8_co u0 ( + .A0(opa[0]), + .A1(opa[1]), + .A2(opa[2]), + .A3(opa[3]), + .A4(opa[4]), + .A5(opa[5]), + .A6(opa[6]), + .A7(opa[7]), + + .B0(opb[0]), + .B1(opb[1]), + .B2(opb[2]), + .B3(opb[3]), + .B4(opb[4]), + .B5(opb[5]), + .B6(opb[6]), + .B7(opb[7]), + + .C_OUT(co), + .ADD(add), + + .S0(out[0]), + .S1(out[1]), + .S2(out[2]), + .S3(out[3]), + .S4(out[4]), + .S5(out[5]), + .S6(out[6]), + .S7(out[7]) ); +// INST_TAG_END + +endmodule + +/* +// MOD_TAG +module xilinx_add_sub8_co (A,B,C_OUT,ADD,S); // synthesis black_box +input [7 : 0] A; +input [7 : 0] B; +output C_OUT; +input ADD; +output [7 : 0] S; + +// synopsys translate_off +// synthesis translate_off + C_ADDSUB_V1_0 #( + 2, + "0000", + 1, + 8, + 0, + 0, + 0, + 1, + "0", + 8, + 1, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 7, + 0, + 8, + 1, + "0", + 0, + 1) + inst ( + .A(A), + .B(B), + .C_OUT(C_OUT), + .ADD(ADD), + .S(S)); +// synthesis translate_on +// synopsys translate_on +endmodule +// MOD_TAG_END +*/ + +// 11 bit incrementer +module inc11(in, out); +input [10:0] in; +output [10:0] out; + +// INST_TAG +xilinx_inc11 u0 ( + .A0(in[0]), + .A1(in[1]), + .A2(in[2]), + .A3(in[3]), + .A4(in[4]), + .A5(in[5]), + .A6(in[6]), + .A7(in[7]), + .A8(in[8]), + .A9(in[9]), + .A10(in[10]), + + .S0(out[0]), + .S1(out[1]), + .S2(out[2]), + .S3(out[3]), + .S4(out[4]), + .S5(out[5]), + .S6(out[6]), + .S7(out[7]), + .S8(out[8]), + .S9(out[9]), + .S10(out[10]) ); +// INST_TAG_END + +endmodule + +/* +// MOD_TAG +module xilinx_inc11 (A,S); // synthesis black_box +input [10 : 0] A; +output [10 : 0] S; + +// synopsys translate_off +// synthesis translate_off + C_ADDSUB_V1_0 #( + 0, + "0000", + 1, + 11, + 0, + 0, + 1, + 1, + "0001", + 11, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 10, + 0, + 11, + 1, + "0", + 0, + 1) + inst ( + .A(A), + .S(S)); +// synthesis translate_on +// synopsys translate_on +endmodule +// MOD_TAG_END +*/ + +// 8 bit incrementer +module inc8(in, out); +input [7:0] in; +output [7:0] out; + +// INST_TAG +xilinx_inc8 u0 ( + .A0(in[0]), + .A1(in[1]), + .A2(in[2]), + .A3(in[3]), + .A4(in[4]), + .A5(in[5]), + .A6(in[6]), + .A7(in[7]), + + .S0(out[0]), + .S1(out[1]), + .S2(out[2]), + .S3(out[3]), + .S4(out[4]), + .S5(out[5]), + .S6(out[6]), + .S7(out[7]) ); +// INST_TAG_END + +endmodule + +/* +// MOD_TAG +module xilinx_inc8 (A,S); // synthesis black_box +input [7 : 0] A; +output [7 : 0] S; + +// synopsys translate_off +// synthesis translate_off + C_ADDSUB_V1_0 #( + 0, + "0000", + 1, + 8, + 0, + 0, + 1, + 1, + "0001", + 8, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 7, + 0, + 8, + 1, + "0", + 0, + 1) + inst ( + .A(A), + .S(S)); +// synthesis translate_on +// synopsys translate_on +endmodule +// MOD_TAG_END +*/ + + +// A Basic Synchrounous FIFO (4 entries deep) +module sfifo4x11(clk, push, din, pop, dout); +input clk; +input push; +input [10:0] din; +input pop; +output [10:0] dout; + +reg [10:0] stack1, stack2, stack3, stack4; + +assign dout = stack1; + +always @(posedge clk) + begin + if(push) // PUSH stack + begin + stack4 <= #1 stack3; + stack3 <= #1 stack2; + stack2 <= #1 stack1; + stack1 <= #1 din; + end + if(pop) // POP stack + begin + stack1 <= #1 stack2; + stack2 <= #1 stack3; + stack3 <= #1 stack4; + end + end + +endmodule + + +// Synchrounous SRAM +// 128 bytes by 8 bits +// 1 read port, 1 write port +// FOR XILINX VERTEX SERIES +module ssram_128x8(clk, rd_addr, rd_data, we, wr_addr, wr_data); +input clk; +input [6:0] rd_addr; +output [7:0] rd_data; +input we; +input [6:0] wr_addr; +input [7:0] wr_data; + +wire [7:0] tmp; + + +// Alternatively RAMs can be instantiated directly +RAMB4_S8_S8 u0( + .DOA( rd_data ), + .ADDRA( {2'b0, rd_addr} ), + .DIA( 8'h00 ), + .ENA( 1'b1 ), + .CLKA( clk ), + .WEA( 1'b0 ), + .RSTA( 1'b0 ), + .DOB( tmp ), + .ADDRB( {2'b0, wr_addr} ), + .DIB( wr_data ), + .ENB( 1'b1 ), + .CLKB( clk ), + .WEB( we ), + .RSTB( 1'b0 ) ); + + +endmodule + + + +// This block is the global Set/Rest for Xilinx VIrtex Serries +// Connect it up as described in Xilinx documentation +// Leave it out for Non Xilinx implementations +module glbl(rst); +input rst; + +wire GSR; + +assign GSR = rst; + +endmodule + + Index: minirisc/trunk/verilog/core/risc_core.v =================================================================== --- minirisc/trunk/verilog/core/risc_core.v (nonexistent) +++ minirisc/trunk/verilog/core/risc_core.v (revision 7) @@ -0,0 +1,838 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Mini-RISC-1 //// +//// Mini-Risc Core //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// D/L from: http://www.opencores.org/cores/minirisc/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: risc_core.v,v 1.3 2002-10-01 12:44:24 rudi Exp $ +// +// $Date: 2002-10-01 12:44:24 $ +// $Revision: 1.3 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.2 2002/09/27 15:35:40 rudi +// Minor update to newer devices ... +// +// +// +// +// +// +// +// +// +// +// + +`timescale 1ns / 10ps + +module mrisc( + clk, + rst_in, + + inst_addr, + inst_data, + + portain, + portbin, + portcin, + + portaout, + portbout, + portcout, + + trisa, + trisb, + trisc, + + tcki, + wdt_en ); + +// Basic Core I/O. +input clk; +input rst_in; + +// Program memory interface +output [10:0] inst_addr; +input [11:0] inst_data; + +// Basic I/O Ports +input [7:0] portain; +input [7:0] portbin; +input [7:0] portcin; + +output [7:0] portaout; +output [7:0] portbout; +output [7:0] portcout; + +output [7:0] trisa; +output [7:0] trisb; +output [7:0] trisc; + +input tcki; +input wdt_en; + +// This should be set to the ROM location where our restart vector is. +// As set here, we have 512 words of program space. +parameter PC_RST_VECTOR = 11'h000, // Should be: 11'h7FF, + STAT_RST_VALUE = 8'h18, + OPT_RST_VALUE = 8'h3f, + FSR_RST_VALUE = 7'h0, + TRIS_RST_VALUE = 8'hff; + +parameter ALU_ADD = 4'h0, + ALU_SUB = 4'h1, + ALU_INC = 4'h2, + ALU_DEC = 4'h3, + + ALU_AND = 4'h4, + ALU_CLR = 4'h5, + ALU_NOT = 4'h6, + ALU_IOR = 4'h7, + ALU_MOV = 4'h8, + ALU_MOVW = 4'h9, + ALU_RLF = 4'ha, + ALU_RRF = 4'hb, + ALU_SWP = 4'hc, + ALU_XOR = 4'hd, + ALU_BCF = 4'he, + ALU_BSF = 4'hf; + +parameter // Byte Oriented RF Operations + I_ADDWF = 12'b0001_11??_????, + I_ANDWF = 12'b0001_01??_????, + I_CLRF = 12'b0000_011?_????, + I_CLRW = 12'b0000_0100_0000, + I_COMF = 12'b0010_01??_????, + I_DEC = 12'b0000_11??_????, + I_DECFSZ = 12'b0010_11??_????, + I_INCF = 12'b0010_10??_????, + I_INCFSZ = 12'b0011_11??_????, + I_IORWF = 12'b0001_00??_????, + I_MOV = 12'b0010_00??_????, + I_MOVWF = 12'b0000_001?_????, + I_NOP = 12'b0000_0000_0000, + I_RLF = 12'b0011_01??_????, + I_RRF = 12'b0011_00??_????, + I_SUBWF = 12'b0000_10??_????, + I_SWAPF = 12'b0011_10??_????, + I_XORWF = 12'b0001_10??_????, + + // Bit Oriented RF Operations + I_BCF = 12'b0100_????_????, + I_BSF = 12'b0101_????_????, + I_BTFSC = 12'b0110_????_????, + I_BTFSS = 12'b0111_????_????, + + // Literal & Controll Operations + I_ANDLW = 12'b1110_????_????, + I_CALL = 12'b1001_????_????, + I_CLRWDT = 12'b0000_0000_0100, + I_GOTO = 12'b101?_????_????, + I_IORLW = 12'b1101_????_????, + I_MOVLW = 12'b1100_????_????, + I_OPTION = 12'b0000_0000_0010, + I_RETLW = 12'b1000_????_????, + I_SLEEP = 12'b0000_0000_0011, + I_TRIS = 12'b0000_0000_0???, + I_XORLW = 12'b1111_????_????; + +parameter // sfr register address encodings + INDF_ADDR = 3'h0, + TMR0_ADDR = 3'h1, + PCL_ADDR = 3'h2, + STAT_ADDR = 3'h3, + FSR_ADDR = 3'h4, + PORTA_ADDR = 3'h5, + PORTB_ADDR = 3'h6, + PORTC_ADDR = 3'h7; + +parameter // Source 1 Select + K_SEL = 2'b10, + SFR_SEL = 2'b00, + RF_SEL = 2'b01; + +parameter // STATUS Register status bits we + STAT_WR_C = 3'b001, + STAT_WR_DC = 3'b010, + STAT_WR_Z = 3'b100; + + +// Instruction Register +reg rst; +reg [11:0] instr_0, instr_1; +reg rst_r1, rst_r2; +wire valid; +reg valid_1; + +reg [7:0] mask; +reg [7:0] sfr_rd_data; +reg [3:0] alu_op; +reg src1_sel; +reg [1:0] src1_sel_; + +wire [7:0] dout; // ALU output +wire [7:0] src1; // ALU Source 1 + +reg [2:0] stat_bwe; // status bits we +wire c_out, dc_out, z_out; + +reg pc_skz, pc_skz_; +reg pc_bset, pc_bset_; +reg pc_bclr, pc_bclr_; +reg pc_call, pc_call_; +reg pc_goto, pc_goto_; +reg pc_retlw, pc_retlw_; + +wire invalidate_1; +wire invalidate_0_; +reg invalidate_0; + +// stage 1 dst decode +reg w_we_; +reg rf_we_; +reg sfr_we_; +reg tris_we_; + +// stage 2 dst decode +reg w_we; +wire rf_we; +reg rf_we1, rf_we2, rf_we3; + +reg opt_we; +reg trisa_we; +reg trisb_we; +reg trisc_we; + +wire indf_we_; +reg tmr0_we; +wire pc_we_; +reg pc_we; +reg stat_we; +reg fsr_we; +reg porta_we; +reg portb_we; +reg portc_we; + +wire bit_sel; +wire [7:0] tmr0_next, tmr0_next1, tmr0_plus_1; +wire tmr0_cnt_en; +reg wdt_clr; +wire wdt_to; +wire wdt_en; +wire tcki; + +wire [7:0] sfr_rd_data_tmp1, sfr_rd_data_tmp2, sfr_rd_data_tmp3; + +// Register File Connections +wire [1:0] rf_rd_bnk, rf_wr_bnk; +wire [4:0] rf_rd_addr, rf_wr_addr; +wire [7:0] rf_rd_data, rf_wr_data; + +// Program Counter +reg [10:0] inst_addr; +reg [10:0] pc; +wire [10:0] pc_next; +wire [10:0] pc_plus_1; +wire [10:0] stack_out; +reg [10:0] pc_r, pc_r2; +wire [10:0] pc_next1, pc_next2, pc_next3; + +// W Register +reg [7:0] w; // Working Register +reg [7:0] status; // Status Register +wire [7:0] status_next; +reg [6:0] fsr; // fsr register ( for indirect addressing) +wire [6:0] fsr_next; +reg [7:0] tmr0; // Timer 0 +reg [5:0] option; // Option Register + +// Tristate Control registers. +reg [7:0] trisa; +reg [7:0] trisb; +reg [7:0] trisc; + +// I/O Port registers +reg [7:0] porta_r; // PORTA input register +reg [7:0] portb_r; // PORTB input register +reg [7:0] portc_r; // PORTC input register +reg [7:0] portaout; // PORTA output register +reg [7:0] portbout; // PORTB output register +reg [7:0] portcout; // PORTC output register + +//////////////////////////////////////////////////////////////////////// +// External Reset is Synchrounous to clock +always @(posedge clk) + rst <= #1 rst_in; + +//////////////////////////////////////////////////////////////////////// +// Synchrounous Register File +register_file u0( .clk( clk ), + .rst( rst ), + .rf_rd_bnk( rf_rd_bnk ), + .rf_rd_addr( rf_rd_addr ), + .rf_rd_data( rf_rd_data ), + .rf_we( rf_we ), + .rf_wr_bnk( rf_wr_bnk ), + .rf_wr_addr( rf_wr_addr ), + .rf_wr_data( rf_wr_data ) + ); + +//////////////////////////////////////////////////////////////////////// +// Always Fetch Next Instruction +always @(posedge clk) + instr_0 <= #1 inst_data; + +//////////////////////////////////////////////////////////////////////// +// Instr Decode & Read Logic + +always @(posedge clk) + begin + rst_r1 <= #1 rst | wdt_to; + rst_r2 <= #1 rst | rst_r1 | wdt_to; + end + +assign valid = ~rst_r2 & ~invalidate_1; +always @(posedge clk) + valid_1 <= #1 valid; + +always @(posedge clk) + instr_1 <= #1 instr_0; + +always @(posedge clk) // Basic Decode extracted directly from the instruction + begin + // Mask for bit modification instructions + case(instr_0[7:5]) // synopsys full_case parallel_case + 0: mask <= #1 8'h01; + 1: mask <= #1 8'h02; + 2: mask <= #1 8'h04; + 3: mask <= #1 8'h08; + 4: mask <= #1 8'h10; + 5: mask <= #1 8'h20; + 6: mask <= #1 8'h40; + 7: mask <= #1 8'h80; + endcase + end + +always @(posedge clk) + pc_r <= #1 pc; // Previous version of PC to accomodate for pipeline + +always @(posedge clk) // SFR Read Operands + if(src1_sel_[1]) sfr_rd_data <= #1 instr_0[7:0]; + else + case(instr_0[2:0]) // synopsys full_case parallel_case + 1: sfr_rd_data <= #1 tmr0_next; + 2: sfr_rd_data <= #1 pc_r[7:0]; + 3: sfr_rd_data <= #1 status_next; + 4: sfr_rd_data <= #1 {1'b1, fsr_next}; + 5: sfr_rd_data <= #1 porta_r; + 6: sfr_rd_data <= #1 portb_r; + 7: sfr_rd_data <= #1 portc_r; + endcase + + +/* +always @(posedge clk) + sfr_rd_data <= #1 sfr_rd_data_tmp1; + + +reg [3:0] sfr_sel; +wire [3:0] sfr_sel_src; + +assign sfr_sel_src = {src1_sel_[1],instr_0[2:0]}; + +always @(sfr_sel_src) + casex(sfr_sel_src) // synopsys full_case parallel_case + 4'b1_???: sfr_sel = 4'b01_11; + 4'b0_001: sfr_sel = 4'bxx_00; + 4'b0_010: sfr_sel = 4'b00_11; + 4'b0_011: sfr_sel = 4'bxx_01; + 4'b0_100: sfr_sel = 4'bxx_10; + 4'b0_101: sfr_sel = 4'b10_11; + 4'b0_11?: sfr_sel = 4'b11_11; + endcase + + +mux4_8 u1( .sel(sfr_sel[1:0]), .out(sfr_rd_data_tmp1), + .in0(tmr0_next), .in1(status_next), + .in2({1'b1, fsr_next}), .in3(sfr_rd_data_tmp2) ); + +mux4_8 u2( .sel(sfr_sel[3:2]), .out(sfr_rd_data_tmp2), + .in0(pc_r[7:0]), .in1(instr_0[7:0]), + .in2(porta_r), .in3(sfr_rd_data_tmp3) ); + +mux2_8 u2b( .sel(instr_0[0]), .out(sfr_rd_data_tmp3), + .in0(portb_r), .in1(portc_r) ); +*/ + +reg instd_zero; + +always @(posedge clk) + instd_zero <= #1 !(|inst_data[4:0]); + +// Register File Read Port +assign rf_rd_bnk = fsr_next[6:5]; +assign rf_rd_addr = instd_zero ? fsr_next[4:0] : instr_0[4:0]; + +// ALU OP +always @(posedge clk) + casex(instr_0) // synopsys full_case parallel_case + // Byte Oriented RF Operations + I_ADDWF: alu_op <= #1 ALU_ADD; // ADDWF + I_ANDWF: alu_op <= #1 ALU_AND; // ANDWF + I_CLRF: alu_op <= #1 ALU_CLR; // CLRF + I_CLRW: alu_op <= #1 ALU_CLR; // CLRW + I_COMF: alu_op <= #1 ALU_NOT; // COMF + I_DEC: alu_op <= #1 ALU_DEC; // DEC + I_DECFSZ: alu_op <= #1 ALU_DEC; // DECFSZ + I_INCF: alu_op <= #1 ALU_INC; // INCF + I_INCFSZ: alu_op <= #1 ALU_INC; // INCFSZ + I_IORWF: alu_op <= #1 ALU_IOR; // IORWF + I_MOV: alu_op <= #1 ALU_MOV; // MOV + I_MOVWF: alu_op <= #1 ALU_MOVW; // MOVWF + I_RLF: alu_op <= #1 ALU_RLF; // RLF + I_RRF: alu_op <= #1 ALU_RRF; // RRF + I_SUBWF: alu_op <= #1 ALU_SUB; // SUBWF + I_SWAPF: alu_op <= #1 ALU_SWP; // SWAPF + I_XORWF: alu_op <= #1 ALU_XOR; // XORWF + // Bit Oriented RF Operations + I_BCF: alu_op <= #1 ALU_BCF; // BCF + I_BSF: alu_op <= #1 ALU_BSF; // BSF + // Literal & Controll Operations + I_ANDLW: alu_op <= #1 ALU_AND; // ANDLW + I_IORLW: alu_op <= #1 ALU_IOR; // IORLW + I_MOVLW: alu_op <= #1 ALU_MOV; // MOWLW + I_RETLW: alu_op <= #1 ALU_MOV; // RETLW + I_XORLW: alu_op <= #1 ALU_XOR; // XORLW + endcase + + +// Source Select +// This CPU source 1 can be one of: rf (or sfr) or k, +// second source (if any) is always w +always @(instr_0) + casex(instr_0) // synopsys full_case parallel_case + I_ANDLW: src1_sel_ = K_SEL; + I_CALL: src1_sel_ = K_SEL; + I_GOTO: src1_sel_ = K_SEL; + I_IORLW: src1_sel_ = K_SEL; + I_MOVLW: src1_sel_ = K_SEL; + I_RETLW: src1_sel_ = K_SEL; + I_XORLW: src1_sel_ = K_SEL; + default: src1_sel_ = ( (instr_0[4:3]==2'h0) & (instr_0[2:0] != 3'h0 )) ? SFR_SEL : RF_SEL; + endcase + +always @(posedge clk) + src1_sel <= #1 src1_sel_[0]; + +// Destination Select +// Destination can be one of: rf, w, option, tris OR one of sfr registers: +// indf, tmr0, pc, status, fsr, porta, portb, portc, option, trisa, trisb, trisc +// Stage 1 +// select w, pc, rf or sfr +reg w_we1, w_we1_; + +always @(instr_0) + begin + casex(instr_0) // synopsys full_case parallel_case + I_ADDWF, I_ANDWF, I_COMF, I_DEC, + I_DECFSZ, I_INCF, I_INCFSZ, I_IORWF, + I_MOV, I_RLF, I_RRF, I_SUBWF, + I_SWAPF, I_XORWF: // w or f + w_we1_ = 1; + default: w_we1_ = 0; + endcase + end + +always @(instr_0) + begin + w_we_ = 0; + rf_we_ = 0; + sfr_we_ = 0; + tris_we_= 0; + casex(instr_0) // synopsys full_case parallel_case + + I_ADDWF, I_ANDWF, I_COMF, I_DEC, + I_DECFSZ, I_INCF, I_INCFSZ, I_IORWF, + I_MOV, I_RLF, I_RRF, I_SUBWF, + I_SWAPF, I_XORWF: // w or f + begin + rf_we_ = instr_0[5] & (instr_0[4] | instr_0[3]); + sfr_we_ = instr_0[5] & ~instr_0[4] & ~instr_0[3]; + end + + I_MOVWF, I_CLRF, I_BCF, I_BSF: // only f + begin + rf_we_ = instr_0[4] | instr_0[3]; + sfr_we_ = ~instr_0[4] & ~instr_0[3]; + end + + I_CLRW, I_IORLW, I_MOVLW, + I_ANDLW, I_RETLW, I_XORLW: w_we_ = 1; // only w + I_TRIS: tris_we_ = 1; // trisa or trisb or trisc + + endcase + end + +assign indf_we_ = sfr_we_ & (instr_0[2:0] == INDF_ADDR); +assign pc_we_ = sfr_we_ & (instr_0[2:0] == PCL_ADDR); + +// Stage 2 destination encoder +// write enable outputs are registered now +always @(posedge clk) w_we <= #1 w_we_; // working register write 0 enable + +always @(posedge clk) w_we1 <= #1 w_we1_; // working register write 1 enable + + +// Register File Write Enable is composed of thee conditions: 1) direct register writing (0x10-0x1f); +// 2) Direct Global Register writing (0x08-0x0f), and 3) Indirect Register File Writing +// The logic has been partitioned and balanced between the decode and execute stage ... +assign rf_we = rf_we1 | (rf_we2 & rf_we3); // register file write enable Composite + +always @(posedge clk) + rf_we1 <= #1 valid & rf_we_; // register file write enable 1 + +always @(posedge clk) + rf_we2 <= #1 valid & (fsr_next[4] | fsr_next[3]);// register file write enable 2 + +always @(posedge clk) + rf_we3 <= #1 indf_we_; // register file write enable 3 + +always @(posedge clk) + wdt_clr <= #1 instr_0[11:0] == I_CLRWDT; + + +always @(posedge clk) + opt_we <= #1 instr_0[11:0] == I_OPTION; + + +always @(posedge clk) + trisa_we <= #1 tris_we_ & (instr_0[2:0] == PORTA_ADDR); + +always @(posedge clk) + trisb_we <= #1 tris_we_ & (instr_0[2:0] == PORTB_ADDR); + +always @(posedge clk) + trisc_we <= #1 tris_we_ & (instr_0[2:0] == PORTC_ADDR); + +always @(posedge clk) + begin + // SFR registers + tmr0_we <= #1 sfr_we_ & (instr_0[2:0] == TMR0_ADDR); + pc_we <= #1 valid & pc_we_; + stat_we <= #1 valid & sfr_we_ & (instr_0[2:0] == STAT_ADDR); + fsr_we <= #1 valid & sfr_we_ & (instr_0[2:0] == FSR_ADDR); + porta_we <= #1 sfr_we_ & (instr_0[2:0] == PORTA_ADDR); + portb_we <= #1 sfr_we_ & (instr_0[2:0] == PORTB_ADDR); + portc_we <= #1 sfr_we_ & (instr_0[2:0] == PORTC_ADDR); + end + + +// Instructions that directly modify PC +always @(instr_0) + begin + pc_skz_ = 0; + pc_bset_ = 0; + pc_bclr_ = 0; + pc_call_ = 0; + pc_goto_ = 0; + pc_retlw_ = 0; + casex(instr_0) // synopsys full_case parallel_case + // Byte Oriented RF Operations + I_DECFSZ, + I_INCFSZ: pc_skz_ = 1; + // Bit Oriented RF Operations + I_BTFSS: pc_bset_ = 1; + I_BTFSC: pc_bclr_ = 1; + // Literal & Controll Operations + I_CALL: pc_call_ = 1; + I_GOTO: pc_goto_ = 1; + I_RETLW: pc_retlw_ = 1; + endcase + end + +always @(posedge clk) + begin + pc_skz <= #1 valid & pc_skz_; + pc_bset <= #1 valid & pc_bset_; + pc_bclr <= #1 valid & pc_bclr_; + pc_call <= #1 valid & pc_call_; + pc_goto <= #1 valid & pc_goto_; + pc_retlw <= #1 valid & pc_retlw_; + end + +assign invalidate_0_ = (pc_call_ | pc_goto_ | pc_retlw_ | pc_we_); + +always @(posedge clk) + invalidate_0 <= #1 invalidate_0_; + +// Status bits WE +always @(posedge clk) + begin + stat_bwe <= #1 0; + if(valid) + casex(instr_0) // synopsys full_case parallel_case + // Byte Oriented RF Operations + I_ADDWF: stat_bwe <= #1 STAT_WR_C | STAT_WR_DC | STAT_WR_Z; + I_ANDWF: stat_bwe <= #1 STAT_WR_Z; + I_CLRF: stat_bwe <= #1 STAT_WR_Z; + I_CLRW: stat_bwe <= #1 STAT_WR_Z; + I_COMF: stat_bwe <= #1 STAT_WR_Z; + I_DEC: stat_bwe <= #1 STAT_WR_Z; + I_INCF: stat_bwe <= #1 STAT_WR_Z; + I_IORWF: stat_bwe <= #1 STAT_WR_Z; + I_MOV: stat_bwe <= #1 STAT_WR_Z; + I_RLF: stat_bwe <= #1 STAT_WR_C; + I_RRF: stat_bwe <= #1 STAT_WR_C; + I_SUBWF: stat_bwe <= #1 STAT_WR_C | STAT_WR_DC | STAT_WR_Z; + I_XORWF: stat_bwe <= #1 STAT_WR_Z; + // Literal & Controll Operations + I_ANDLW: stat_bwe <= #1 STAT_WR_Z; + //I_CLRWDT: // Modifies TO & PD *** FIX ME *** + I_IORLW: stat_bwe <= #1 STAT_WR_Z; + //I_SLEEP: // Modifies TO & PD *** FIX ME *** + I_XORLW: stat_bwe <= #1 STAT_WR_Z; + endcase + end + +//////////////////////////////////////////////////////////////////////// +// Wr & Execute Logic (including PC) +// Second Pipeline Stage +//////////////////////////////////////////////////////////////////////// + +// Source OP Sel +//assign src1 = src1_sel ? rf_rd_data : sfr_rd_data; +mux2_8 u3( .sel(src1_sel), .in0(sfr_rd_data), .in1(rf_rd_data), .out(src1) ); + +alu u4( .s1( src1 ), + .s2( w ), + .mask( mask ), + .out( dout ), + .op( alu_op ), + .c_in( status[0] ), + .c( c_out ), + .dc( dc_out ), + .z( z_out ) + ); + +// Register file connections +assign rf_wr_bnk = fsr[6:5]; +assign rf_wr_addr = (instr_1[4:0]==0) ? fsr[4:0] : instr_1[4:0]; +assign rf_wr_data = dout; + +wire [7:0] status_next2; + +// Deal with all special registers (SFR) writes +/* +always @(rst or status or stat_we or stat_bwe or dout or c_out or dc_out or z_out) + if(rst) status_next = STAT_RST_VALUE; + else + begin + status_next = status; // Default Keep Value + if(stat_we) status_next = dout | 8'h18; + else + begin + if(stat_bwe[0]) status_next[0] = c_out; + if(stat_bwe[1]) status_next[1] = dc_out; + if(stat_bwe[2]) status_next[2] = z_out; + end + end +*/ + +assign status_next2[0] = stat_bwe[0] ? c_out : status[0]; +assign status_next2[1] = stat_bwe[1] ? dc_out : status[1]; +assign status_next2[2] = stat_bwe[2] ? z_out : status[2]; + +mux2_8 u21( .sel(stat_we), .in1( {dout | 8'h18} ), .in0( {status[7:3],status_next2[2:0]} ), .out(status_next) ); + +always @(posedge clk) + if(rst) status <= #1 STAT_RST_VALUE; + else status <= #1 status_next; + +//assign fsr_next = fsr_we ? dout[6:0] : fsr; + +mux2_7 u31( .sel(fsr_we), .in1(dout[6:0]), .in0(fsr), .out(fsr_next) ); + +always @(posedge clk) + if(rst) fsr <= #1 FSR_RST_VALUE; + else fsr <= #1 fsr_next; + +always @(posedge clk) + if(valid_1 & (w_we | (w_we1 & ~instr_1[5])) ) w <= #1 dout; + +always @(posedge clk) + if(rst) trisa <= #1 TRIS_RST_VALUE; + else + if(trisa_we & valid_1) trisa <= #1 w; + +always @(posedge clk) + if(rst) trisb <= #1 TRIS_RST_VALUE; + else + if(trisb_we & valid_1) trisb <= #1 w; + +always @(posedge clk) + if(rst) trisc <= #1 TRIS_RST_VALUE; + else + if(trisc_we & valid_1) trisc <= #1 w; + +always @(posedge clk) + if(rst) option <= #1 OPT_RST_VALUE; + else + if(opt_we & valid_1) option <= #1 w[5:0]; + +always @(posedge clk) + if(porta_we & valid_1) portaout <= #1 dout; + +always @(posedge clk) + if(portb_we & valid_1) portbout <= #1 dout; + +always @(posedge clk) + if(portc_we & valid_1) portcout <= #1 dout; + +always @(posedge clk) + begin + porta_r <= #1 portain; + portb_r <= #1 portbin; + portc_r <= #1 portcin; + end + +/////////////////////////////////////////////////////////////////////// +// Timer Logic + +//assign tmr0_next = tmr0_we ? dout : tmr0_cnt_en ? tmr0_plus_1 : tmr0; +//assign tmr0_next = tmr0_we ? dout : tmr0_cnt_en ? (tmr0 + 1) : tmr0; + + +mux2_8 u5( .sel(tmr0_we & valid_1), + .in0(tmr0_next1), .in1(dout), + .out(tmr0_next) ); +mux2_8 u6( .sel(tmr0_cnt_en), + .in0(tmr0), .in1(tmr0_plus_1), + .out(tmr0_next1) ); + +inc8 u7( .in(tmr0), .out(tmr0_plus_1) ); + +always @(posedge clk) + tmr0 <= #1 tmr0_next; + +presclr_wdt u8( .clk( clk ), + .rst( rst ), + .tcki( tcki ), + .option( option[5:0] ), + .tmr0_we( tmr0_we & valid_1 ), + .tmr0_cnt_en( tmr0_cnt_en ), + .wdt_en( wdt_en ), + .wdt_clr( wdt_clr & valid_1 ), + .wdt_to( wdt_to ) + ); + + +//////////////////////////////////////////////////////////////////////// +// Programm Counter Logic + +always @(posedge clk) + pc_r2 <= #1 pc_r; + +// 'inst_addr' is a duplication of the 'pc'. The only time when it is really needed +// is when the program memory is not on the chip and we want to place the registers +// directly in the IO pads to reduce Tcq (For example in a Xilinx FPGA implementation). +// If the program memory is on the chip or if the implmentation allows feedback from +// registers in the IO cells, this is not needed. Synopsys FPGA compiler appears to +// make the correct decission either way, and gett rid of unneded logic ... + +always @(posedge clk) + if(rst) inst_addr <= #1 PC_RST_VECTOR; + else inst_addr <= #1 pc_next; + +always @(posedge clk) + if(rst) pc <= #1 PC_RST_VECTOR; + else pc <= #1 pc_next; + +/* +always @(pc_plus_1 or dout or pc_we or status or stack_out or + pc_call or pc_goto or pc_retlw or instr_1) + if(pc_we) pc_next = {status[6:5], 1'b0, dout}; + else + if(!pc_call & !pc_goto & !pc_retlw) pc_next = pc_plus_1; + else + if(pc_call) pc_next = {status[6:5], 1'b0, instr_1[7:0]}; + else + if(pc_goto) pc_next = {status[6:5], instr_1[8:0]}; + else + if(pc_retlw) pc_next = stack_out; +*/ + + +wire [10:0] pc_tmp1, pc_tmp2, pc_tmp3; +wire pc_sel1; + +assign pc_tmp1 = {status[6:5], 1'b0, dout[7:0]}; +assign pc_tmp2 = {status[6:5], 1'b0, instr_1[7:0]}; +assign pc_tmp3 = {status[6:5], instr_1[8:0]}; +assign pc_sel1 = (!pc_call & !pc_goto & !pc_retlw); + +mux2_11 u9 ( .sel(pc_we), .in0(pc_next1), .in1(pc_tmp1), .out(pc_next) ); +mux2_11 u10( .sel(pc_sel1), .in0(pc_next2), .in1(pc_plus_1), .out(pc_next1) ); +mux2_11 u11( .sel(pc_call), .in0(pc_next3), .in1(pc_tmp2), .out(pc_next2) ); +mux2_11 u12( .sel(pc_goto), .in0(stack_out), .in1(pc_tmp3), .out(pc_next3) ); + + +inc11 u13( .in(pc), .out(pc_plus_1) ); + +reg invalidate_1_r1, invalidate_1_r2; + +assign invalidate_1 = (pc_skz & z_out) | (pc_bset & bit_sel) | + (pc_bclr & !bit_sel) | (invalidate_0 & valid_1) | invalidate_1_r1; + + +always @(posedge clk) + begin + invalidate_1_r1 <= #1 (invalidate_0 & valid_1) | invalidate_1_r2; + invalidate_1_r2 <= #1 (invalidate_0 & valid_1); + end + +//assign bit_sel = src1[ instr_1[7:5] ]; +mux8_1 u22( .sel(instr_1[7:5]), .in(src1), .out(bit_sel) ); + +sfifo4x11 u14( .clk(clk), .push(pc_call), .din(pc_r2), .pop(pc_retlw), .dout(stack_out) ); + +endmodule Index: minirisc/trunk/verilog/core/risc_core_top.v =================================================================== --- minirisc/trunk/verilog/core/risc_core_top.v (nonexistent) +++ minirisc/trunk/verilog/core/risc_core_top.v (revision 7) @@ -0,0 +1,186 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Mini-RISC-1 //// +//// Mini-Risc Core Top Levcel //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// D/L from: http://www.opencores.org/cores/minirisc/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: risc_core_top.v,v 1.3 2002-10-01 12:44:24 rudi Exp $ +// +// $Date: 2002-10-01 12:44:24 $ +// $Revision: 1.3 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.2 2002/09/27 15:35:40 rudi +// Minor update to newer devices ... +// +// +// +// +// +// +// +// +// +// +// + +`timescale 1ns / 10ps + +module mrisc_top( + clk, rst_in, + porta, portb, portc, + tcki, + wdt_en ); // synthesis syn_useioff=1 syn_hier="flatten,remove" + +// Basic Core I/O. +input clk; +input rst_in; + +// I/O Ports +inout [7:0] porta; +inout [7:0] portb; +inout [7:0] portc; + +input tcki; +input wdt_en; + +//////////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +wire [10:0] inst_addr; +wire [11:0] inst_data; + +wire [7:0] portain; +wire [7:0] portbin; +wire [7:0] portcin; + +wire [7:0] portaout; +wire [7:0] portbout; +wire [7:0] portcout; + +wire [7:0] trisa; +wire [7:0] trisb; +wire [7:0] trisc; + +//////////////////////////////////////////////////////////////////////// +// +// IO Buffers +// + +assign porta[0] = trisa[0] ? 1'bz : portaout[0]; +assign porta[1] = trisa[1] ? 1'bz : portaout[1]; +assign porta[2] = trisa[2] ? 1'bz : portaout[2]; +assign porta[3] = trisa[3] ? 1'bz : portaout[3]; +assign porta[4] = trisa[4] ? 1'bz : portaout[4]; +assign porta[5] = trisa[5] ? 1'bz : portaout[5]; +assign porta[6] = trisa[6] ? 1'bz : portaout[6]; +assign porta[7] = trisa[7] ? 1'bz : portaout[7]; + +assign portb[0] = trisb[0] ? 1'bz : portbout[0]; +assign portb[1] = trisb[1] ? 1'bz : portbout[1]; +assign portb[2] = trisb[2] ? 1'bz : portbout[2]; +assign portb[3] = trisb[3] ? 1'bz : portbout[3]; +assign portb[4] = trisb[4] ? 1'bz : portbout[4]; +assign portb[5] = trisb[5] ? 1'bz : portbout[5]; +assign portb[6] = trisb[6] ? 1'bz : portbout[6]; +assign portb[7] = trisb[7] ? 1'bz : portbout[7]; + +assign portc[0] = trisc[0] ? 1'bz : portcout[0]; +assign portc[1] = trisc[1] ? 1'bz : portcout[1]; +assign portc[2] = trisc[2] ? 1'bz : portcout[2]; +assign portc[3] = trisc[3] ? 1'bz : portcout[3]; +assign portc[4] = trisc[4] ? 1'bz : portcout[4]; +assign portc[5] = trisc[5] ? 1'bz : portcout[5]; +assign portc[6] = trisc[6] ? 1'bz : portcout[6]; +assign portc[7] = trisc[7] ? 1'bz : portcout[7]; + +assign portain = porta; +assign portbin = portb; +assign portcin = portc; + +//////////////////////////////////////////////////////////////////////// +// +// Mini Risc Core +// + +mrisc u0( + clk, + rst_in, + + inst_addr, + inst_data, + + portain, + portbin, + portcin, + + portaout, + portbout, + portcout, + + trisa, + trisb, + trisc, + + tcki, + wdt_en ); + + +//////////////////////////////////////////////////////////////////////// +// +// Program memory +// + +generic_spram #(11,12) imem( + .clk( clk ), + .rst( rst_in ), + .ce( 1'b1 ), + .we( 1'b0 ), + .oe( 1'b1 ), + .addr( inst_addr ), + .di( 12'h0 ), + .do( inst_data ) + ); + +endmodule Index: minirisc/trunk/verilog/core/presclr_wdt.v =================================================================== --- minirisc/trunk/verilog/core/presclr_wdt.v (nonexistent) +++ minirisc/trunk/verilog/core/presclr_wdt.v (revision 7) @@ -0,0 +1,150 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Mini-RISC-1 //// +//// Prescaler and Wachdog Counter //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// D/L from: http://www.opencores.org/cores/minirisc/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: presclr_wdt.v,v 1.2 2002-09-27 15:35:40 rudi Exp $ +// +// $Date: 2002-09-27 15:35:40 $ +// $Revision: 1.2 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// +// +// +// +// +// +// +// +// +// + + +`timescale 1ns / 10ps + +// Prescaler and Wachdog Counter +module presclr_wdt(clk, rst, tcki, option, tmr0_we, tmr0_cnt_en, wdt_en, wdt_clr, wdt_to); +input clk; +input rst; +input tcki; +input [5:0] option; +input tmr0_we; +output tmr0_cnt_en; +input wdt_en, wdt_clr; +output wdt_to; + + +reg [7:0] prescaler; +reg [7:0] wdt; +reg tmr0_cnt_en; +reg tcki_r; +reg wdt_to; +wire tose; +wire tosc; +wire psa; +wire [2:0] ps; +wire tcki_a, tcki_b; +wire presclr_ce; +wire prsclr_clr; +wire wdt_to_direct; +reg presclr_out, presclr_out_r1; +reg presclr_out_next; +wire [7:0] presclr_plus_1, wdt_plus_1; +wire [7:0] prescaler_next, prescaler_next1; +wire [7:0] wdt_next, wdt_next1; + +// Inputs select +assign ps = option[2:0]; +assign psa = option[3]; +assign tose = option[4]; +assign tosc = option[5]; + +always @(posedge clk) + tcki_r <= #1 tcki; + +assign tcki_a = tose ^ tcki_r; +assign tcki_b = tosc ? tcki_a : 1'b1; +assign presclr_ce = psa ? wdt_to_direct : tcki_b; + +always @(posedge clk) + tmr0_cnt_en <= #1 psa ? tcki_b : presclr_out; + +// Prescaler +assign prsclr_clr = psa ? wdt_clr : tmr0_we; + +always @(posedge clk) + if(rst | prsclr_clr) prescaler <= #1 8'h00; + else + if(presclr_ce) prescaler <= #1 prescaler + 8'h01; + +always @(ps or prescaler) + case(ps) + 3'd0: presclr_out_next = prescaler[0]; + 3'd1: presclr_out_next = prescaler[1]; + 3'd2: presclr_out_next = prescaler[2]; + 3'd3: presclr_out_next = prescaler[3]; + 3'd4: presclr_out_next = prescaler[4]; + 3'd5: presclr_out_next = prescaler[5]; + 3'd6: presclr_out_next = prescaler[6]; + 3'd7: presclr_out_next = prescaler[7]; + endcase + +always @(posedge clk) + presclr_out_r1 <= #1 presclr_out_next; + +always @(posedge clk) // Edge detector for prescaler output + presclr_out <= #1 presclr_out_next & ~presclr_out_r1 & ~prsclr_clr; + +// Wachdog timer +always @(posedge clk) + wdt_to <= #1 psa ? presclr_out : wdt_to_direct; + +always @(posedge clk) + if(rst | wdt_clr) wdt <= #1 8'h00; + else + if(wdt_en) wdt <= #1 wdt + 8'h01; // wdt_plus_1; + +assign wdt_to_direct = (wdt == 8'hff); + +endmodule Index: minirisc/trunk/verilog/testbench/test.v =================================================================== --- minirisc/trunk/verilog/testbench/test.v (nonexistent) +++ minirisc/trunk/verilog/testbench/test.v (revision 7) @@ -0,0 +1,329 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Test Bench //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// D/L from: http://www.opencores.org/cores/minirisc/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: test.v,v 1.1 2002-09-27 15:35:41 rudi Exp $ +// +// $Date: 2002-09-27 15:35:41 $ +// $Revision: 1.1 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// +// +// +// +// +// +// +// +// +// + +`timescale 1ns / 10ps + +module test; + +reg clk; +reg reset; +reg tcki; + +// Declare I/O Port connections +wire [7:0] porta; // I/O Port A +wire [7:0] portb; // I/O Port B +wire [7:0] portc; // I/O Port C + +wire [7:0] portain; +wire [7:0] portbin; +wire [7:0] portcin; + +wire [7:0] portaout; +wire [7:0] portbout; +wire [7:0] portcout; + +wire [7:0] trisa; +wire [7:0] trisb; +wire [7:0] trisc; + +// Declare ROM and rom signals +wire [10:0] inst_addr; +wire [11:0] inst_data; + + +always #10 clk = ~clk; +always #20 tcki = ~tcki; + +// Instantiate one CPU to be tested. +mrisc u0( + .clk (clk), + .rst_in (reset), + .inst_addr (inst_addr), + .inst_data (inst_data), + + .portain (portain), + .portbin (portbin), + .portcin (portcin), + + .portaout (portaout), + .portbout (portbout), + .portcout (portcout), + + .trisa (trisa), + .trisb (trisb), + .trisc (trisc), + + .tcki (tcki), + .wdt_en (1'b1) + + ); + +// IO buffers for IO Ports +assign porta = trisa ? 8'bz : portaout; +assign portain = porta; + +assign portb = trisb ? 8'bz : portbout; +assign portbin = portb; + +assign portc = trisc ? 8'bz : portcout; +assign portcin = portc; + +// Pullups for IO Ports +pullup ua0(porta[0]); +pullup ua1(porta[1]); +pullup ua2(porta[2]); +pullup ua3(porta[3]); +pullup ua4(porta[4]); +pullup ua5(porta[5]); +pullup ua6(porta[6]); +pullup ua7(porta[7]); + +pullup ub0(portb[0]); +pullup ub1(portb[1]); +pullup ub2(portb[2]); +pullup ub3(portb[3]); +pullup ub4(portb[4]); +pullup ub5(portb[5]); +pullup ub6(portb[6]); +pullup ub7(portb[7]); + +pullup uc0(portc[0]); +pullup uc1(portc[1]); +pullup uc2(portc[2]); +pullup uc3(portc[3]); +pullup uc4(portc[4]); +pullup uc5(portc[5]); +pullup uc6(portc[6]); +pullup uc7(portc[7]); + + +// Instantiate the Program RAM. +prog_mem u1 ( + .clk (clk), + .address (inst_addr), + .we (1'b0), // This testbench doesn't allow writing to PRAM + .din (12'b000000000000), // This testbench doesn't allow writing to PRAM + .dout (inst_data) +); + +// This is the only initial block in the test module and this is where +// you select what test you want to do. + +initial + begin + $display ("\n\nMini-RISC. Version 1.0\n\n"); + + //$dumpfile ("mini-risc.vcd"); + //$dumpvars (0, test); + + clk = 0; + tcki = 0; + + sanity1; + + $readmemh ("../scode/sanity2.rom", u1.mem); run_code("Sanity 2 "); + + $readmemh ("../scode/rf1.rom", u1.mem); run_code("Register File 1 "); + + $readmemh ("../scode/rf2.rom", u1.mem); run_code("Register File 2 "); + + $readmemh ("../scode/rf3.rom", u1.mem); run_code("Register File 3 "); + + //$readmemh ("scode/tmr_wdt.rom", u1.mem); run_code("Timer / WDT "); + + //$dumpflush; + $finish; + end + + +task sanity1; + +`define GOOD 12'h0aa +`define BAD 12'h0af +`define SANITY1 "../scode/sanity1.rom" + + begin + $display ("========== Starting Sanity 1 Test ========== \n"); + reset = 1; + repeat(10) @(posedge clk); + reset = 0; + + //$display ("Loading program memory with %s", `SANITY1); + $readmemh (`SANITY1, u1.mem); + while(inst_addr != `GOOD & inst_addr != `BAD) @(posedge clk); + + if(inst_addr == `GOOD) + begin + $display("Sanity1 test PASSED !!!"); + end + else + if(inst_addr == `BAD) + begin + $display("Sanity1 test FAILED !!!"); + end + else + $display("Sanity1 test status UNKNOWN !!!"); + + + repeat(4) @(posedge clk); + $display("=============================================\n\n\n"); + + end +endtask + +task run_code; +input [16*8-1:0] str; + + + begin + $display ("========== Starting %s Test ========== \n",str); + reset = 1; + repeat(10) @(posedge clk); + reset = 0; + + //$display ("Loading program memory with %s", `SANITY2); + //$readmemh (`SANITY2, u1.mem); + + repeat(10) @(posedge clk); + while(porta == 8'h00) @(posedge clk); + + + if(porta == 8'h01) + begin + $display("Test %s PASSED !!!",str); + end + else + if(porta == 8'hff) + begin + $display("Test %s FAILED in test %d !!!", str, portb); + end + else + $display("Test %s status UNKNOWN (%h test: %d) !!!", str, porta, portb); + + + repeat(4) @(posedge clk); + $display("\n=============================================\n\n\n"); + + end +endtask + +/* +always @(posedge clk) + if(!reset) + begin + if( |u0.w ===1'bx ) $display("%t: Warning :W went unknown",$time); + if( |u0.pc ===1'bx ) $display("%t: Warning :PC went unknown",$time); + if( |u0.status ===1'bx ) $display("%t: Warning :STATUS went unknown",$time); + end +*/ + +reg [8*8-1:0] inst_string; + +always @(inst_data) begin + casex (inst_data) + 12'b0000_0000_0000: inst_string = "NOP "; + 12'b0000_001X_XXXX: inst_string = "MOVWF "; + 12'b0000_0100_0000: inst_string = "CLRW "; + 12'b0000_011X_XXXX: inst_string = "CLRF "; + 12'b0000_10XX_XXXX: inst_string = "SUBWF "; + 12'b0000_11XX_XXXX: inst_string = "DECF "; + 12'b0001_00XX_XXXX: inst_string = "IORWF "; + 12'b0001_01XX_XXXX: inst_string = "ANDWF "; + 12'b0001_10XX_XXXX: inst_string = "XORWF "; + 12'b0001_11XX_XXXX: inst_string = "ADDWF "; + 12'b0010_00XX_XXXX: inst_string = "MOVF "; + 12'b0010_01XX_XXXX: inst_string = "COMF "; + 12'b0010_10XX_XXXX: inst_string = "INCF "; + 12'b0010_11XX_XXXX: inst_string = "DECFSZ "; + 12'b0011_00XX_XXXX: inst_string = "RRF "; + 12'b0011_01XX_XXXX: inst_string = "RLF "; + 12'b0011_10XX_XXXX: inst_string = "SWAPF "; + 12'b0011_11XX_XXXX: inst_string = "INCFSZ "; + + // *** Bit-Oriented File Register Operations + 12'b0100_XXXX_XXXX: inst_string = "BCF "; + 12'b0101_XXXX_XXXX: inst_string = "BSF "; + 12'b0110_XXXX_XXXX: inst_string = "BTFSC "; + 12'b0111_XXXX_XXXX: inst_string = "BTFSS "; + + // *** Literal and Control Operations + 12'b0000_0000_0010: inst_string = "OPTION "; + 12'b0000_0000_0011: inst_string = "SLEEP "; + 12'b0000_0000_0100: inst_string = "CLRWDT "; + 12'b0000_0000_0101: inst_string = "TRIS "; + 12'b0000_0000_0110: inst_string = "TRIS "; + 12'b0000_0000_0111: inst_string = "TRIS "; + 12'b1000_XXXX_XXXX: inst_string = "RETLW "; + 12'b1001_XXXX_XXXX: inst_string = "CALL "; + 12'b101X_XXXX_XXXX: inst_string = "GOTO "; + 12'b1100_XXXX_XXXX: inst_string = "MOVLW "; + 12'b1101_XXXX_XXXX: inst_string = "IORLW "; + 12'b1110_XXXX_XXXX: inst_string = "ANDLW "; + 12'b1111_XXXX_XXXX: inst_string = "XORLW "; + + default: inst_string = "-XXXXXX-"; + endcase + //$display("Executing[%h] %s",inst_addr, inst_string); +end + + +endmodule + Index: minirisc/trunk/verilog/testbench/prog_mem.v =================================================================== --- minirisc/trunk/verilog/testbench/prog_mem.v (nonexistent) +++ minirisc/trunk/verilog/testbench/prog_mem.v (revision 7) @@ -0,0 +1,89 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Mini-RISC-1 //// +//// Program Memory //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// D/L from: http://www.opencores.org/cores/minirisc/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: prog_mem.v,v 1.2 2002-09-27 15:35:41 rudi Exp $ +// +// $Date: 2002-09-27 15:35:41 $ +// $Revision: 1.2 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// +// +// +// +// +// +// +// +// +// + +`timescale 1ns / 10ps + +// For simulation only +// May be off or on chip + +module prog_mem ( clk, address, we, din, dout ); + +input clk; +input [10:0] address; +input we; +input [11:0] din; +output [11:0] dout; + +parameter depth = 2048; + +reg [10:0] addr_r; +reg [11:0] mem[0:depth-1]; + +always @(posedge clk) + addr_r <= address; + +assign dout = mem[addr_r]; + +always @(posedge clk) + if (we) mem[address] <= din; + +endmodule Index: minirisc/trunk/sim/run =================================================================== --- minirisc/trunk/sim/run (nonexistent) +++ minirisc/trunk/sim/run (revision 7) @@ -0,0 +1,16 @@ +#!/bin/csh + +ncverilog \ + +define+TEST_BENCH \ + \ + ../verilog/core/alu.v \ + ../verilog/core/presclr_wdt.v \ + ../verilog/core/risc_core.v \ + ../verilog/core/primitives.v \ + ../verilog/core/register_file.v \ + ../verilog/core/risc_core_top.v \ + ../verilog/testbench/prog_mem.v \ + ../verilog/testbench/test.v \ + \ + ../../generic_memories/rtl/verilog/generic_spram.v \ + ../../generic_memories/rtl/verilog/generic_dpram.v

minirisc/trunk/sim/run Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: minirisc/trunk/README.txt =================================================================== --- minirisc/trunk/README.txt (nonexistent) +++ minirisc/trunk/README.txt (revision 7) @@ -0,0 +1,120 @@ + +This is a Mini-RISC CPU/Microcontroller that is mostly compatible with the +PIC 16C57 from Microchip. + + +Legal +===== + +PIC, Microship, etc. are Trademarks of Microchip Technology Inc. + +I have no idea if implementing this core will or will not violate +patents, copyrights or cause any other type of lawsuits. + +I provide this core AS IS, without any warrenties. If you decide to +build this core, you are responsible for any legal resolutions, such +as patents and copyrights, and perhaps others .... + + This source file(s) may be used and distributed without + restriction provided that this copyright statement is not + removed from the file and that any derivative work contains + the original copyright notice and the associated disclaimer. + + THIS SOURCE FILE(S) IS/ARE PROVIDED "AS IS" AND WITHOUT ANY + EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT + LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND + FITNESS FOR A PARTICULAR PURPOSE. + + +Motivation +========== + +After seeing the "free_risc8" on the free-ip web site, I got excited +and downloaded the core. Pretty soon I found out that it had many +many errors and omissions from the original 16C57. So I started looking +at the code. This is when I realized it was very badly designed and +could not be made run faster. So, I sat down and wrote my own PIC IP +core last night. A lot of work was spend in writing test code to ensure +that it was 100% compatible from the software point of view. + +- A PIC compatible Microcontroller that runs a lot faster +- Separate (External to the core) Program Memory +- Options to extend the core + + +Compatibility +============= + +This design should be fully software compatible to the Microchip Implementation +of the PIC 16C57, except for the following extensions: + +- Port A is full 8 bits wide +- Hardware stack is 4 level deep [original 2 levels] (can be easily expanded) +- Executions of instructions that modify the PC has become a lot more expensive + due to the pipeline and execution of instructions on every cycle. + Any instruction that writes to the PC (PC as destination (f), call, goto, retlw) + now takes 4 cycles to execute (instead of 2 in the origianl implementation). + The 4 'skip' instructions, remain as in the original implmentation: 1 cycle + if not skipped, 2 cycles if skipped. +- Sampling of IO ports might be off +- Timer and watchdog might be off a few cycles + + +Performance +=========== + +- Single cycle instruction execution, except as noted above. +- Here are results of some sample implementations: + - Xilinx Spartan 2e ((Device: xc2s50e-6): Fmax: 80Mhz, Utilization: 30% + - Xilinx Spartan2 (Device: xc2s30-6-cs144): Fmax: 50Mhz, Utilization: 66%, Ports: Tsu: 2.2nS, Tcq: 7.7nS + - Xilinx Virtex (Device: xcv50-4-cs144) : Fmax: 40Mhz, Utilization: 35%, Ports: Tsu: 3.0nS, Tcq: 6.2nS + - Xilinx VirtexE (Device: xcv50e-8-cs144): Fmax: 66Mhz, Utilization: 35%, Ports: Tsu: 1.7nS, Tcq: 4.5nS + Half of the cycle time is spend in routing delays. My guess is that by placing + proper locatiuon contrains and guiding the back-end tools, a significant + speed improvement can be achieved .... +- I estimat about 25K gates with the xilinx primitives, (excluding Register + File and Programm Memory). + +Implementing the core +===================== + +The only file you should edit if you really want to implement this core, is the +'primitives.v' file. It contains all parts that can be optimized, depending on +the technology used. It includes memories, and arithmetic modules. +I added a primitives_xilinx,v file and xilinx_primitives.zip which contain +primitives for xilinx. +'risc_core.v' is the top level without program memory and tristate Io buffers for ports. +This is probably a good starting point if you want to instantiate the core in to a larger +design. If you just want a PIC clone, take a loot at 'risc_core_top.v', it was written +with Xilinx FPGAs in mind, but should be easily addaptred to other vendors FPGAs - just +replace the memory blocks ... + +To-Do +===== + +Things that need to be done + +1) Write more test/compliance test vectors + - Verify that all instructions after a goto/call/retlw/write to PCL are not executed + - Verify ALU + - Timer and Watchdog tests + - Perhaps some other ereas ? + +2) Extensions ? + - I guess this is on a "as needed" basis + - A friend suggested to add registers that can be shared by two or more cores in a MP type configuration + +Author +====== + +I have been doing ASIC design, verification and synthesis for over 15 years. +This core is only a "mid-night hack", and should used with caution. + +I'd also like to know if anyone will actually use this core. Please send me a +note if you will ! + +Rudolf Usselmann +russelmann@hotmail.com + +Feel free to send me comments, suggestions and bug reports. + Index: minirisc/trunk/xilinx_primitives.zip =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: minirisc/trunk/xilinx_primitives.zip =================================================================== --- minirisc/trunk/xilinx_primitives.zip (nonexistent) +++ minirisc/trunk/xilinx_primitives.zip (revision 7)

minirisc/trunk/xilinx_primitives.zip Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: minirisc/trunk/scode/tmr_wdt.asm =================================================================== --- minirisc/trunk/scode/tmr_wdt.asm (nonexistent) +++ minirisc/trunk/scode/tmr_wdt.asm (revision 7) @@ -0,0 +1,155 @@ +;///////////////////////////////////////////////////////////////////// +;//// //// +;//// Mini-RISC-1 //// +;//// Timer / Wachdog //// +;//// Tests Timer / Wachdog //// +;//// //// +;//// Author: Rudolf Usselmann //// +;//// russelmann@hotmail.com //// +;//// //// +;///////////////////////////////////////////////////////////////////// +;//// //// +;//// Copyright (C) 2000 Rudolf Usselmann //// +;//// russelmann@hotmail.com //// +;//// //// +;//// This source file may be used and distributed without //// +;//// restriction provided that this copyright statement is not //// +;//// removed from the file and that any derivative work contains //// +;//// the original copyright notice and the associated disclaimer.//// +;//// //// +;//// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY //// +;//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT //// +;//// LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND //// +;//// FITNESS FOR A PARTICULAR PURPOSE. //// +;//// //// +;///////////////////////////////////////////////////////////////////// + + list p=16c57 + #include p16c5x.inc + +; global Registers +r0 equ 0x8 +r1 equ 0x9 +r2 equ 0xa +r3 equ 0xb +r4 equ 0xc +r5 equ 0xd +r6 equ 0xe +r7 equ 0xf + +; banked Registers +br0 equ 0x10 +br1 equ 0x11 +br2 equ 0x12 +br3 equ 0x13 +br4 equ 0x14 +br5 equ 0x15 +br6 equ 0x16 +br7 equ 0x17 +br8 equ 0x18 +br9 equ 0x19 +br10 equ 0x1a +br11 equ 0x1b +br12 equ 0x1c +br13 equ 0x1d +br14 equ 0x1e +br15 equ 0x1f + + +; PORTB Indicates Test Number +; PORTA Indicates Status: 0 - Running; 1 - done OK; ff - stoped on error + +main ; Main code entry + ; Port IO Test + ; All ports have a Pull up resistor + + ; SETUP all ports + clrw + movwf FSR + movwf PORTA + movwf PORTB + movwf PORTC + tris PORTA + tris PORTB + tris PORTC + + ; --------------------------------------- + ; ---- Test RMW on Register fil ---- + ; --------------------------------------- + + movlw 0x01 ; TEST 1 + movwf PORTB ; Set Test Number + + movlw 0x00 + option + movwf TMR0 + clrwdt + nop + nop + nop + nop + + clrw + movwf r1 + +loop2 ; repeat 256 times + clrw + movwf r0 + + + ; repeat 256 times +loop1 + movfw TMR0 + decfsz r0,F + goto loop1 + + decfsz r1,F + goto loop2 + + + + nop + nop + nop + nop + nop + nop + + clrw + movwf TMR0 + clrwdt + + nop + nop + nop + nop + movlw 0x01 + movwf PORTA + nop + nop + nop + nop +good ; Loop in good on success + goto good + nop + nop + nop + nop + +lerr + movlw 0xff + movwf PORTA + + nop + nop + nop + nop +lerr_loop ; Loop in lerr on failure + goto lerr_loop + nop + nop + nop + nop + + END + Index: minirisc/trunk/scode/rf1.rom =================================================================== --- minirisc/trunk/scode/rf1.rom (nonexistent) +++ minirisc/trunk/scode/rf1.rom (revision 7) @@ -0,0 +1,584 @@ + +@000 040 +@001 024 +@002 025 +@003 026 +@004 027 +@005 005 +@006 006 +@007 007 +@008 5A3 +@009 C81 +@00A 028 +@00B C82 +@00C 029 +@00D C83 +@00E 02A +@00F C84 +@010 02B +@011 C85 +@012 02C +@013 C86 +@014 02D +@015 C87 +@016 02E +@017 C88 +@018 02F +@019 C90 +@01A 030 +@01B C91 +@01C 031 +@01D C92 +@01E 032 +@01F C93 +@020 033 +@021 C94 +@022 034 +@023 C95 +@024 035 +@025 C96 +@026 036 +@027 C97 +@028 037 +@029 C98 +@02A 038 +@02B C99 +@02C 039 +@02D C9A +@02E 03A +@02F C9B +@030 03B +@031 C9C +@032 03C +@033 C9D +@034 03D +@035 C9E +@036 03E +@037 C9F +@038 03F +@039 5A4 +@03A CA0 +@03B 030 +@03C CA1 +@03D 031 +@03E CA2 +@03F 032 +@040 CA3 +@041 033 +@042 CA4 +@043 034 +@044 CA5 +@045 035 +@046 CA6 +@047 036 +@048 CA7 +@049 037 +@04A CA8 +@04B 038 +@04C CA9 +@04D 039 +@04E CAA +@04F 03A +@050 CAB +@051 03B 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+@1E2 08D +@1E3 743 +@1E4 A3C +@1E5 C87 +@1E6 08E +@1E7 743 +@1E8 A3C +@1E9 C88 +@1EA 08F +@1EB 743 +@1EC A3C +@1ED CC0 +@1EE 090 +@1EF 743 +@1F0 A3C +@1F1 CC1 +@1F2 091 +@1F3 743 +@1F4 A3C +@1F5 CC2 +@1F6 092 +@1F7 743 +@1F8 A3C +@1F9 CC3 +@1FA 093 +@1FB 743 +@1FC A3C +@1FD CC4 +@1FE 094 +@1FF 743 +@200 A3C +@201 CC5 +@202 095 +@203 743 +@204 A3C +@205 CC6 +@206 096 +@207 743 +@208 A3C +@209 CC7 +@20A 097 +@20B 743 +@20C A3C +@20D CC8 +@20E 098 +@20F 743 +@210 A3C +@211 CC9 +@212 099 +@213 743 +@214 A3C +@215 CCA +@216 09A +@217 743 +@218 A3C +@219 CCB +@21A 09B +@21B 743 +@21C A3C +@21D CCC +@21E 09C +@21F 743 +@220 A3C +@221 CCD +@222 09D +@223 743 +@224 A3C +@225 CCE +@226 09E +@227 743 +@228 A3C +@229 CCF +@22A 09F +@22B 743 +@22C A3C +@22D 000 +@22E 000 +@22F 000 +@230 000 +@231 C01 +@232 025 +@233 000 +@234 000 +@235 000 +@236 000 +@237 A37 +@238 000 +@239 000 +@23A 000 +@23B 000 +@23C CFF +@23D 025 +@23E 000 +@23F 000 +@240 000 +@241 000 +@242 A42 +@243 000 +@244 000 +@245 000 +@246 000 Index: minirisc/trunk/scode/sanity1.rom =================================================================== --- minirisc/trunk/scode/sanity1.rom (nonexistent) +++ minirisc/trunk/scode/sanity1.rom (revision 7) @@ -0,0 +1,181 @@ + +@000 040 +@001 025 +@002 026 +@003 027 +@004 FFF +@005 005 +@006 006 +@007 007 +@008 705 +@009 AAF +@00A 725 +@00B AAF +@00C 745 +@00D AAF +@00E 765 +@00F AAF +@010 785 +@011 AAF +@012 7A5 +@013 AAF +@014 7C5 +@015 AAF +@016 7E5 +@017 AAF +@018 706 +@019 AAF +@01A 726 +@01B AAF +@01C 746 +@01D AAF +@01E 766 +@01F AAF +@020 786 +@021 AAF +@022 7A6 +@023 AAF +@024 7C6 +@025 AAF +@026 7E6 +@027 AAF +@028 707 +@029 AAF +@02A 727 +@02B AAF +@02C 747 +@02D AAF +@02E 767 +@02F AAF +@030 787 +@031 AAF +@032 7A7 +@033 AAF +@034 7C5 +@035 AAF +@036 7E7 +@037 AAF +@038 040 +@039 005 +@03A 006 +@03B 007 +@03C 040 +@03D FAA +@03E 025 +@03F 026 +@040 027 +@041 605 +@042 AAF +@043 725 +@044 AAF +@045 645 +@046 AAF +@047 765 +@048 AAF +@049 685 +@04A AAF +@04B 7A5 +@04C AAF +@04D 6C5 +@04E AAF +@04F 7E5 +@050 AAF +@051 606 +@052 AAF +@053 726 +@054 AAF +@055 646 +@056 AAF +@057 766 +@058 AAF +@059 686 +@05A AAF +@05B 7A6 +@05C AAF +@05D 6C6 +@05E AAF +@05F 7E6 +@060 AAF +@061 607 +@062 AAF +@063 727 +@064 AAF +@065 647 +@066 AAF +@067 767 +@068 AAF +@069 687 +@06A AAF +@06B 7A7 +@06C AAF +@06D 6C7 +@06E AAF +@06F 7E7 +@070 AAF +@071 040 +@072 F55 +@073 025 +@074 026 +@075 027 +@076 705 +@077 AAF +@078 625 +@079 AAF +@07A 745 +@07B AAF +@07C 665 +@07D AAF +@07E 785 +@07F AAF +@080 6A5 +@081 AAF +@082 7C5 +@083 AAF +@084 6E5 +@085 AAF +@086 706 +@087 AAF +@088 626 +@089 AAF +@08A 746 +@08B AAF +@08C 666 +@08D AAF +@08E 786 +@08F AAF +@090 6A6 +@091 AAF +@092 7C6 +@093 AAF +@094 6E6 +@095 AAF +@096 707 +@097 AAF +@098 627 +@099 AAF +@09A 747 +@09B AAF +@09C 667 +@09D AAF +@09E 787 +@09F AAF +@0A0 6A7 +@0A1 AAF +@0A2 7C7 +@0A3 AAF +@0A4 6E7 +@0A5 AAF +@0A6 000 +@0A7 000 +@0A8 000 +@0A9 000 +@0AA AAA +@0AB 000 +@0AC 000 +@0AD 000 +@0AE 000 +@0AF AAF +@0B0 000 +@0B1 000 +@0B2 000 +@0B3 000 Index: minirisc/trunk/scode/rf2.rom =================================================================== --- minirisc/trunk/scode/rf2.rom (nonexistent) +++ minirisc/trunk/scode/rf2.rom (revision 7) @@ -0,0 +1,720 @@ + +@000 040 +@001 024 +@002 025 +@003 026 +@004 027 +@005 005 +@006 006 +@007 007 +@008 5A3 +@009 C81 +@00A 028 +@00B C82 +@00C 029 +@00D C83 +@00E 02A +@00F C84 +@010 02B +@011 C85 +@012 02C +@013 C86 +@014 02D +@015 C87 +@016 02E +@017 C88 +@018 02F +@019 C90 +@01A 030 +@01B C91 +@01C 031 +@01D C92 +@01E 032 +@01F C93 +@020 033 +@021 C94 +@022 034 +@023 C95 +@024 035 +@025 C96 +@026 036 +@027 C97 +@028 037 +@029 C98 +@02A 038 +@02B C99 +@02C 039 +@02D C9A +@02E 03A +@02F C9B +@030 03B +@031 C9C +@032 03C +@033 C9D +@034 03D +@035 C9E +@036 03E +@037 C9F +@038 03F +@039 5A4 +@03A CA0 +@03B 030 +@03C CA1 +@03D 031 +@03E CA2 +@03F 032 +@040 CA3 +@041 033 +@042 CA4 +@043 034 +@044 CA5 +@045 035 +@046 CA6 +@047 036 +@048 CA7 +@049 037 +@04A CA8 +@04B 038 +@04C CA9 +@04D 039 +@04E CAA +@04F 03A +@050 CAB +@051 03B +@052 CAC +@053 03C +@054 CAD +@055 03D +@056 CAE +@057 03E +@058 CAF +@059 03F +@05A 4A4 +@05B 5C4 +@05C CB0 +@05D 030 +@05E CB1 +@05F 031 +@060 CB2 +@061 032 +@062 CB3 +@063 033 +@064 CB4 +@065 034 +@066 CB5 +@067 035 +@068 CB6 +@069 036 +@06A CB7 +@06B 037 +@06C CB8 +@06D 038 +@06E CB9 +@06F 039 +@070 CBA +@071 03A +@072 CBB +@073 03B +@074 CBC +@075 03C +@076 CBD +@077 03D +@078 CBE +@079 03E +@07A CBF +@07B 03F +@07C 5A4 +@07D 5C4 +@07E CC0 +@07F 030 +@080 CC1 +@081 031 +@082 CC2 +@083 032 +@084 CC3 +@085 033 +@086 CC4 +@087 034 +@088 CC5 +@089 035 +@08A CC6 +@08B 036 +@08C CC7 +@08D 037 +@08E CC8 +@08F 038 +@090 CC9 +@091 039 +@092 CCA +@093 03A +@094 CCB +@095 03B +@096 CCC +@097 03C +@098 CCD +@099 03D +@09A CCE +@09B 03E +@09C CCF +@09D 03F +@09E C08 +@09F 024 +@0A0 260 +@0A1 2A4 +@0A2 260 +@0A3 2A4 +@0A4 260 +@0A5 2A4 +@0A6 260 +@0A7 2A4 +@0A8 260 +@0A9 2A4 +@0AA 260 +@0AB 2A4 +@0AC 260 +@0AD 2A4 +@0AE 260 +@0AF 2A4 +@0B0 C10 +@0B1 024 +@0B2 260 +@0B3 2A4 +@0B4 260 +@0B5 2A4 +@0B6 260 +@0B7 2A4 +@0B8 260 +@0B9 2A4 +@0BA 260 +@0BB 2A4 +@0BC 260 +@0BD 2A4 +@0BE 260 +@0BF 2A4 +@0C0 260 +@0C1 2A4 +@0C2 260 +@0C3 2A4 +@0C4 260 +@0C5 2A4 +@0C6 260 +@0C7 2A4 +@0C8 260 +@0C9 2A4 +@0CA 260 +@0CB 2A4 +@0CC 260 +@0CD 2A4 +@0CE 260 +@0CF 2A4 +@0D0 260 +@0D1 2A4 +@0D2 C10 +@0D3 024 +@0D4 5A4 +@0D5 260 +@0D6 2A4 +@0D7 260 +@0D8 2A4 +@0D9 260 +@0DA 2A4 +@0DB 260 +@0DC 2A4 +@0DD 260 +@0DE 2A4 +@0DF 260 +@0E0 2A4 +@0E1 260 +@0E2 2A4 +@0E3 260 +@0E4 2A4 +@0E5 260 +@0E6 2A4 +@0E7 260 +@0E8 2A4 +@0E9 260 +@0EA 2A4 +@0EB 260 +@0EC 2A4 +@0ED 260 +@0EE 2A4 +@0EF 260 +@0F0 2A4 +@0F1 260 +@0F2 2A4 +@0F3 260 +@0F4 2A4 +@0F5 C10 +@0F6 024 +@0F7 5C4 +@0F8 260 +@0F9 2A4 +@0FA 260 +@0FB 2A4 +@0FC 260 +@0FD 2A4 +@0FE 260 +@0FF 2A4 +@100 260 +@101 2A4 +@102 260 +@103 2A4 +@104 260 +@105 2A4 +@106 260 +@107 2A4 +@108 260 +@109 2A4 +@10A 260 +@10B 2A4 +@10C 260 +@10D 2A4 +@10E 260 +@10F 2A4 +@110 260 +@111 2A4 +@112 260 +@113 2A4 +@114 260 +@115 2A4 +@116 260 +@117 2A4 +@118 C10 +@119 024 +@11A 5A4 +@11B 5C4 +@11C 260 +@11D 2A4 +@11E 260 +@11F 2A4 +@120 260 +@121 2A4 +@122 260 +@123 2A4 +@124 260 +@125 2A4 +@126 260 +@127 2A4 +@128 260 +@129 2A4 +@12A 260 +@12B 2A4 +@12C 260 +@12D 2A4 +@12E 260 +@12F 2A4 +@130 260 +@131 2A4 +@132 260 +@133 2A4 +@134 260 +@135 2A4 +@136 260 +@137 2A4 +@138 260 +@139 2A4 +@13A 260 +@13B 2A4 +@13C C01 +@13D 026 +@13E C08 +@13F 024 +@140 C7E +@141 080 +@142 743 +@143 AC4 +@144 C7D +@145 2A4 +@146 080 +@147 743 +@148 AC4 +@149 C7C +@14A 2A4 +@14B 080 +@14C 743 +@14D AC4 +@14E C7B +@14F 2A4 +@150 080 +@151 743 +@152 AC4 +@153 C7A +@154 2A4 +@155 080 +@156 743 +@157 AC4 +@158 C79 +@159 2A4 +@15A 080 +@15B 743 +@15C AC4 +@15D C78 +@15E 2A4 +@15F 080 +@160 743 +@161 AC4 +@162 C77 +@163 2A4 +@164 080 +@165 743 +@166 AC4 +@167 C10 +@168 024 +@169 C6F +@16A 080 +@16B 743 +@16C AC4 +@16D C6E +@16E 2A4 +@16F 080 +@170 743 +@171 AC4 +@172 C6D +@173 2A4 +@174 080 +@175 743 +@176 AC4 +@177 C6C +@178 2A4 +@179 080 +@17A 743 +@17B AC4 +@17C C6B +@17D 2A4 +@17E 080 +@17F 743 +@180 AC4 +@181 C6A +@182 2A4 +@183 080 +@184 743 +@185 AC4 +@186 C69 +@187 2A4 +@188 080 +@189 743 +@18A AC4 +@18B C68 +@18C 2A4 +@18D 080 +@18E 743 +@18F AC4 +@190 C67 +@191 2A4 +@192 080 +@193 743 +@194 AC4 +@195 C66 +@196 2A4 +@197 080 +@198 743 +@199 AC4 +@19A C65 +@19B 2A4 +@19C 080 +@19D 743 +@19E AC4 +@19F C64 +@1A0 2A4 +@1A1 080 +@1A2 743 +@1A3 AC4 +@1A4 C63 +@1A5 2A4 +@1A6 080 +@1A7 743 +@1A8 AC4 +@1A9 C62 +@1AA 2A4 +@1AB 080 +@1AC 743 +@1AD AC4 +@1AE C61 +@1AF 2A4 +@1B0 080 +@1B1 743 +@1B2 AC4 +@1B3 C60 +@1B4 2A4 +@1B5 080 +@1B6 743 +@1B7 AC4 +@1B8 C02 +@1B9 026 +@1BA C10 +@1BB 024 +@1BC 5A4 +@1BD C5F +@1BE 080 +@1BF 743 +@1C0 AC4 +@1C1 C5E +@1C2 2A4 +@1C3 080 +@1C4 743 +@1C5 AC4 +@1C6 C5D +@1C7 2A4 +@1C8 080 +@1C9 743 +@1CA AC4 +@1CB C5C +@1CC 2A4 +@1CD 080 +@1CE 743 +@1CF AC4 +@1D0 C5B +@1D1 2A4 +@1D2 080 +@1D3 743 +@1D4 AC4 +@1D5 C5A +@1D6 2A4 +@1D7 080 +@1D8 743 +@1D9 AC4 +@1DA C59 +@1DB 2A4 +@1DC 080 +@1DD 743 +@1DE AC4 +@1DF C58 +@1E0 2A4 +@1E1 080 +@1E2 743 +@1E3 AC4 +@1E4 C57 +@1E5 2A4 +@1E6 080 +@1E7 743 +@1E8 AC4 +@1E9 C56 +@1EA 2A4 +@1EB 080 +@1EC 743 +@1ED AC4 +@1EE C55 +@1EF 2A4 +@1F0 080 +@1F1 743 +@1F2 AC4 +@1F3 C54 +@1F4 2A4 +@1F5 080 +@1F6 743 +@1F7 AC4 +@1F8 C53 +@1F9 2A4 +@1FA 080 +@1FB 743 +@1FC AC4 +@1FD C52 +@1FE 2A4 +@1FF 080 +@200 743 +@201 AC4 +@202 C51 +@203 2A4 +@204 080 +@205 743 +@206 AC4 +@207 C50 +@208 2A4 +@209 080 +@20A 743 +@20B AC4 +@20C C03 +@20D 026 +@20E C10 +@20F 024 +@210 5C4 +@211 C4F +@212 080 +@213 743 +@214 AC4 +@215 C4E +@216 2A4 +@217 080 +@218 743 +@219 AC4 +@21A C4D +@21B 2A4 +@21C 080 +@21D 743 +@21E AC4 +@21F C4C +@220 2A4 +@221 080 +@222 743 +@223 AC4 +@224 C4B +@225 2A4 +@226 080 +@227 743 +@228 AC4 +@229 C4A +@22A 2A4 +@22B 080 +@22C 743 +@22D AC4 +@22E C49 +@22F 2A4 +@230 080 +@231 743 +@232 AC4 +@233 C48 +@234 2A4 +@235 080 +@236 743 +@237 AC4 +@238 C47 +@239 2A4 +@23A 080 +@23B 743 +@23C AC4 +@23D C46 +@23E 2A4 +@23F 080 +@240 743 +@241 AC4 +@242 C45 +@243 2A4 +@244 080 +@245 743 +@246 AC4 +@247 C44 +@248 2A4 +@249 080 +@24A 743 +@24B AC4 +@24C C43 +@24D 2A4 +@24E 080 +@24F 743 +@250 AC4 +@251 C42 +@252 2A4 +@253 080 +@254 743 +@255 AC4 +@256 C41 +@257 2A4 +@258 080 +@259 743 +@25A AC4 +@25B C40 +@25C 2A4 +@25D 080 +@25E 743 +@25F AC4 +@260 C04 +@261 026 +@262 C10 +@263 024 +@264 5A4 +@265 5C4 +@266 C3F +@267 080 +@268 743 +@269 AC4 +@26A C3E +@26B 2A4 +@26C 080 +@26D 743 +@26E AC4 +@26F C3D +@270 2A4 +@271 080 +@272 743 +@273 AC4 +@274 C3C +@275 2A4 +@276 080 +@277 743 +@278 AC4 +@279 C3B +@27A 2A4 +@27B 080 +@27C 743 +@27D AC4 +@27E C3A +@27F 2A4 +@280 080 +@281 743 +@282 AC4 +@283 C39 +@284 2A4 +@285 080 +@286 743 +@287 AC4 +@288 C38 +@289 2A4 +@28A 080 +@28B 743 +@28C AC4 +@28D C37 +@28E 2A4 +@28F 080 +@290 743 +@291 AC4 +@292 C36 +@293 2A4 +@294 080 +@295 743 +@296 AC4 +@297 C35 +@298 2A4 +@299 080 +@29A 743 +@29B AC4 +@29C C34 +@29D 2A4 +@29E 080 +@29F 743 +@2A0 AC4 +@2A1 C33 +@2A2 2A4 +@2A3 080 +@2A4 743 +@2A5 AC4 +@2A6 C32 +@2A7 2A4 +@2A8 080 +@2A9 743 +@2AA AC4 +@2AB C31 +@2AC 2A4 +@2AD 080 +@2AE 743 +@2AF AC4 +@2B0 C30 +@2B1 2A4 +@2B2 080 +@2B3 743 +@2B4 AC4 +@2B5 000 +@2B6 000 +@2B7 000 +@2B8 000 +@2B9 C01 +@2BA 025 +@2BB 000 +@2BC 000 +@2BD 000 +@2BE 000 +@2BF ABF +@2C0 000 +@2C1 000 +@2C2 000 +@2C3 000 +@2C4 CFF +@2C5 025 +@2C6 000 +@2C7 000 +@2C8 000 +@2C9 000 +@2CA ACA +@2CB 000 +@2CC 000 +@2CD 000 +@2CE 000 Index: minirisc/trunk/scode/sanity2.rom =================================================================== --- minirisc/trunk/scode/sanity2.rom (nonexistent) +++ minirisc/trunk/scode/sanity2.rom (revision 7) @@ -0,0 +1,282 @@ + +@000 040 +@001 024 +@002 025 +@003 026 +@004 027 +@005 005 +@006 006 +@007 007 +@008 C0B +@009 028 +@00A 202 +@00B 088 +@00C 743 +@00D B23 +@00E C01 +@00F 026 +@010 C13 +@011 02B +@012 202 +@013 08B +@014 743 +@015 B23 +@016 C02 +@017 026 +@018 C1D +@019 022 +@01A B23 +@01B B23 +@01C B23 +@01D A21 +@01E B23 +@01F B23 +@020 B23 +@021 C03 +@022 026 +@023 C28 +@024 022 +@025 B23 +@026 B23 +@027 B23 +@028 A2C +@029 B23 +@02A B23 +@02B B23 +@02C C04 +@02D 026 +@02E C35 +@02F 028 +@030 C32 +@031 088 +@032 1E2 +@033 B23 +@034 B23 +@035 B23 +@036 A3A +@037 B23 +@038 B23 +@039 B23 +@03A C05 +@03B 026 +@03C C43 +@03D 038 +@03E C40 +@03F 098 +@040 1E2 +@041 B23 +@042 B23 +@043 B23 +@044 A48 +@045 B23 +@046 B23 +@047 B23 +@048 C06 +@049 026 +@04A A60 +@060 522 +@061 B23 +@062 B23 +@063 A68 +@064 B23 +@065 B23 +@066 B23 +@067 B23 +@068 C07 +@069 026 +@06A 542 +@06B B23 +@06C B23 +@06D B23 +@06E B23 +@06F A72 +@070 B23 +@071 B23 +@072 C08 +@073 026 +@074 A7C +@075 B23 +@076 B23 +@077 B23 +@078 B23 +@079 A7D +@07A B23 +@07B B23 +@07C 442 +@07D C09 +@07E 026 +@07F A8A +@080 000 +@081 000 +@082 000 +@083 000 +@084 CFF +@085 025 +@086 000 +@087 000 +@088 000 +@089 000 +@08A C0A +@08B 026 +@08C 9A5 +@08D 028 +@08E C55 +@08F 088 +@090 743 +@091 B23 +@092 9A7 +@093 028 +@094 CAA +@095 088 +@096 743 +@097 B23 +@098 9AA +@099 028 +@09A CC3 +@09B 088 +@09C 743 +@09D B23 +@09E 9AE +@09F 028 +@0A0 C3C +@0A1 088 +@0A2 743 +@0A3 B23 +@0A4 AC5 +@0A5 855 +@0A6 B23 +@0A7 000 +@0A8 8AA +@0A9 B23 +@0AA 000 +@0AB 000 +@0AC 8C3 +@0AD B23 +@0AE 000 +@0AF 000 +@0B0 000 +@0B1 83C +@0B2 B23 +@0B3 1E2 +@0B4 8FF +@0B5 8FE +@0B6 8FD +@0B7 8FC +@0B8 8FB +@0B9 8FA +@0BA 8F9 +@0BB 8F8 +@0BC 8F7 +@0BD 8F6 +@0BE 8F5 +@0BF B23 +@0C0 B23 +@0C1 B23 +@0C2 B23 +@0C3 B23 +@0C4 B23 +@0C5 C0B +@0C6 026 +@0C7 C00 +@0C8 028 +@0C9 9B3 +@0CA 268 +@0CB 0A8 +@0CC 743 +@0CD B23 +@0CE C01 +@0CF 028 +@0D0 9B3 +@0D1 268 +@0D2 0A8 +@0D3 743 +@0D4 B23 +@0D5 C02 +@0D6 028 +@0D7 9B3 +@0D8 268 +@0D9 0A8 +@0DA 743 +@0DB B23 +@0DC C03 +@0DD 028 +@0DE 9B3 +@0DF 268 +@0E0 0A8 +@0E1 743 +@0E2 B23 +@0E3 C04 +@0E4 028 +@0E5 9B3 +@0E6 268 +@0E7 0A8 +@0E8 743 +@0E9 B23 +@0EA C05 +@0EB 028 +@0EC 9B3 +@0ED 268 +@0EE 0A8 +@0EF 743 +@0F0 B23 +@0F1 C06 +@0F2 028 +@0F3 9B3 +@0F4 268 +@0F5 0A8 +@0F6 743 +@0F7 B23 +@0F8 C07 +@0F9 028 +@0FA 9B3 +@0FB 268 +@0FC 0A8 +@0FD 743 +@0FE B23 +@0FF C08 +@100 028 +@101 9B3 +@102 268 +@103 0A8 +@104 743 +@105 B23 +@106 C09 +@107 028 +@108 9B3 +@109 268 +@10A 0A8 +@10B 743 +@10C B23 +@10D C0A +@10E 028 +@10F 9B3 +@110 268 +@111 0A8 +@112 743 +@113 B23 +@114 000 +@115 000 +@116 000 +@117 000 +@118 C01 +@119 025 +@11A 000 +@11B 000 +@11C 000 +@11D 000 +@11E B1E +@11F 000 +@120 000 +@121 000 +@122 000 +@123 CFF +@124 025 +@125 000 +@126 000 +@127 000 +@128 000 +@129 B29 +@12A 000 +@12B 000 +@12C 000 +@12D 000 Index: minirisc/trunk/scode/rf3.rom =================================================================== --- minirisc/trunk/scode/rf3.rom (nonexistent) +++ minirisc/trunk/scode/rf3.rom (revision 7) @@ -0,0 +1,219 @@ + +@000 040 +@001 024 +@002 025 +@003 026 +@004 027 +@005 005 +@006 006 +@007 007 +@008 C01 +@009 026 +@00A CFC +@00B 028 +@00C 2A8 +@00D 2A8 +@00E 2A8 +@00F 2A8 +@010 743 +@011 ACF +@012 CFC +@013 038 +@014 2B8 +@015 2B8 +@016 2B8 +@017 2B8 +@018 743 +@019 ACF +@01A C02 +@01B 026 +@01C C09 +@01D 024 +@01E CFC +@01F 020 +@020 2A0 +@021 2A0 +@022 2A0 +@023 2A0 +@024 743 +@025 ACF +@026 C19 +@027 024 +@028 CFC +@029 020 +@02A 2A0 +@02B 2A0 +@02C 2A0 +@02D 2A0 +@02E 743 +@02F ACF +@030 C03 +@031 026 +@032 C04 +@033 028 +@034 0E8 +@035 0E8 +@036 0E8 +@037 0E8 +@038 743 +@039 ACF +@03A C04 +@03B 030 +@03C 0F0 +@03D 0F0 +@03E 0F0 +@03F 0F0 +@040 743 +@041 ACF +@042 C04 +@043 026 +@044 C09 +@045 024 +@046 C04 +@047 020 +@048 0E0 +@049 0E0 +@04A 0E0 +@04B 0E0 +@04C 743 +@04D ACF +@04E C19 +@04F 024 +@050 C04 +@051 020 +@052 0E0 +@053 0E0 +@054 0E0 +@055 0E0 +@056 743 +@057 ACF +@058 C05 +@059 026 +@05A CFC +@05B 02C +@05C 3EC +@05D 3EC +@05E 3EC +@05F 3EC +@060 ACF +@061 CFC +@062 038 +@063 3F8 +@064 3F8 +@065 3F8 +@066 3F8 +@067 ACF +@068 C06 +@069 026 +@06A C09 +@06B 024 +@06C CFC +@06D 020 +@06E 3E0 +@06F 3E0 +@070 3E0 +@071 3E0 +@072 ACF +@073 C19 +@074 024 +@075 CFC +@076 020 +@077 3E0 +@078 3E0 +@079 3E0 +@07A 3E0 +@07B ACF +@07C C07 +@07D 026 +@07E C04 +@07F 028 +@080 2E8 +@081 2E8 +@082 2E8 +@083 2E8 +@084 ACF +@085 C04 +@086 030 +@087 2F0 +@088 2F0 +@089 2F0 +@08A 2F0 +@08B ACF +@08C C08 +@08D 026 +@08E C09 +@08F 024 +@090 C04 +@091 020 +@092 2E0 +@093 2E0 +@094 2E0 +@095 2E0 +@096 ACF +@097 C19 +@098 024 +@099 C04 +@09A 020 +@09B 2E0 +@09C 2E0 +@09D 2E0 +@09E 2E0 +@09F ACF +@0A0 C09 +@0A1 026 +@0A2 CFC +@0A3 024 +@0A4 2A4 +@0A5 2A4 +@0A6 2A4 +@0A7 2A4 +@0A8 743 +@0A9 ACF +@0AA C04 +@0AB 024 +@0AC C7F +@0AD 0E4 +@0AE 0E4 +@0AF 0E4 +@0B0 0E4 +@0B1 164 +@0B2 743 +@0B3 ACF +@0B4 C0A +@0B5 026 +@0B6 CFC +@0B7 023 +@0B8 C18 +@0B9 2A3 +@0BA 2A3 +@0BB 2A3 +@0BC 2A3 +@0BD 083 +@0BE 743 +@0BF ACF +@0C0 000 +@0C1 000 +@0C2 000 +@0C3 000 +@0C4 C01 +@0C5 025 +@0C6 000 +@0C7 000 +@0C8 000 +@0C9 000 +@0CA ACA +@0CB 000 +@0CC 000 +@0CD 000 +@0CE 000 +@0CF CFF +@0D0 025 +@0D1 000 +@0D2 000 +@0D3 000 +@0D4 000 +@0D5 AD5 +@0D6 000 +@0D7 000 +@0D8 000 +@0D9 000 Index: minirisc/trunk/scode/rf1.asm =================================================================== --- minirisc/trunk/scode/rf1.asm (nonexistent) +++ minirisc/trunk/scode/rf1.asm (revision 7) @@ -0,0 +1,694 @@ +;///////////////////////////////////////////////////////////////////// +;//// //// +;//// Mini-RISC-1 //// +;//// Register File Test 1 //// +;//// Tests Register File //// +;//// //// +;//// Author: Rudolf Usselmann //// +;//// russelmann@hotmail.com //// +;//// //// +;///////////////////////////////////////////////////////////////////// +;//// //// +;//// Copyright (C) 2000 Rudolf Usselmann //// +;//// russelmann@hotmail.com //// +;//// //// +;//// This source file may be used and distributed without //// +;//// restriction provided that this copyright statement is not //// +;//// removed from the file and that any derivative work contains //// +;//// the original copyright notice and the associated disclaimer.//// +;//// //// +;//// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY //// +;//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT //// +;//// LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND //// +;//// FITNESS FOR A PARTICULAR PURPOSE. //// +;//// //// +;///////////////////////////////////////////////////////////////////// + + list p=16c57 + #include p16c5x.inc + +; global Registers +r0 equ 0x8 +r1 equ 0x9 +r2 equ 0xa +r3 equ 0xb +r4 equ 0xc +r5 equ 0xd +r6 equ 0xe +r7 equ 0xf + +; banked Registers +br0 equ 0x10 +br1 equ 0x11 +br2 equ 0x12 +br3 equ 0x13 +br4 equ 0x14 +br5 equ 0x15 +br6 equ 0x16 +br7 equ 0x17 +br8 equ 0x18 +br9 equ 0x19 +br10 equ 0x1a +br11 equ 0x1b +br12 equ 0x1c +br13 equ 0x1d +br14 equ 0x1e +br15 equ 0x1f + + +; PORTB Indicates Test Number +; PORTA Indicates Status: 0 - Running; 1 - done OK; ff - stoped on error + +main ; Main code entry + ; Port IO Test + ; All ports have a Pull up resistor + + ; SETUP all ports + clrw + movwf FSR + movwf PORTA + movwf PORTB + movwf PORTC + tris PORTA + tris PORTB + tris PORTC + + bsf STATUS,5 + + ; --------------------------------------- + ; ---- Test the entire register file ---- + ; --------------------------------------- + + movlw 0x81 + movwf r0 + movlw 0x82 + movwf r1 + movlw 0x83 + movwf r2 + movlw 0x84 + movwf r3 + movlw 0x85 + movwf r4 + movlw 0x86 + movwf r5 + movlw 0x87 + movwf r6 + movlw 0x88 + movwf r7 + + + movlw 0x90 + movwf br0 + movlw 0x91 + movwf br1 + movlw 0x92 + movwf br2 + movlw 0x93 + movwf br3 + movlw 0x94 + movwf br4 + movlw 0x95 + movwf br5 + movlw 0x96 + movwf br6 + movlw 0x97 + movwf br7 + movlw 0x98 + movwf br8 + movlw 0x99 + movwf br9 + movlw 0x9a + movwf br10 + movlw 0x9b + movwf br11 + movlw 0x9c + movwf br12 + movlw 0x9d + movwf br13 + movlw 0x9e + movwf br14 + movlw 0x9f + movwf br15 + + bsf FSR,5 ; Select Register Bank 01 + + movlw 0xa0 + movwf br0 + movlw 0xa1 + movwf br1 + movlw 0xa2 + movwf br2 + movlw 0xa3 + movwf br3 + movlw 0xa4 + movwf br4 + movlw 0xa5 + movwf br5 + movlw 0xa6 + movwf br6 + movlw 0xa7 + movwf br7 + movlw 0xa8 + movwf br8 + movlw 0xa9 + movwf br9 + movlw 0xaa + movwf br10 + movlw 0xab + movwf br11 + movlw 0xac + movwf br12 + movlw 0xad + movwf br13 + movlw 0xae + movwf br14 + movlw 0xaf + movwf br15 + + bcf FSR,5 ; Select Register Bank 10 + bsf FSR,6 + + movlw 0xb0 + movwf br0 + movlw 0xb1 + movwf br1 + movlw 0xb2 + movwf br2 + movlw 0xb3 + movwf br3 + movlw 0xb4 + movwf br4 + movlw 0xb5 + movwf br5 + movlw 0xb6 + movwf br6 + movlw 0xb7 + movwf br7 + movlw 0xb8 + movwf br8 + movlw 0xb9 + movwf br9 + movlw 0xba + movwf br10 + movlw 0xbb + movwf br11 + movlw 0xbc + movwf br12 + movlw 0xbd + movwf br13 + movlw 0xbe + movwf br14 + movlw 0xbf + movwf br15 + + bsf FSR,5 ; Select Register Bank 11 + bsf FSR,6 + + movlw 0xc0 + movwf br0 + movlw 0xc1 + movwf br1 + movlw 0xc2 + movwf br2 + movlw 0xc3 + movwf br3 + movlw 0xc4 + movwf br4 + movlw 0xc5 + movwf br5 + movlw 0xc6 + movwf br6 + movlw 0xc7 + movwf br7 + movlw 0xc8 + movwf br8 + movlw 0xc9 + movwf br9 + movlw 0xca + movwf br10 + movlw 0xcb + movwf br11 + movlw 0xcc + movwf br12 + movlw 0xcd + movwf br13 + movlw 0xce + movwf br14 + movlw 0xcf + movwf br15 + + ; Register File TEST 1 + movlw 0x01 + movwf PORTB ; Set Test Number + + clrw + movwf FSR + + movlw 0x81 + subwf r0,W + btfss STATUS,Z + goto lerr + movlw 0x82 + subwf r1,W + btfss STATUS,Z + goto lerr + movlw 0x83 + subwf r2,W + btfss STATUS,Z + goto lerr + movlw 0x84 + subwf r3,W + btfss STATUS,Z + goto lerr + movlw 0x85 + subwf r4,W + btfss STATUS,Z + goto lerr + movlw 0x86 + subwf r5,W + btfss STATUS,Z + goto lerr + movlw 0x87 + subwf r6,W + btfss STATUS,Z + goto lerr + movlw 0x88 + subwf r7,W + btfss STATUS,Z + goto lerr + + movlw 0x90 + subwf br0,W + btfss STATUS,Z + goto lerr + movlw 0x91 + subwf br1,W + btfss STATUS,Z + goto lerr + movlw 0x92 + subwf br2,W + btfss STATUS,Z + goto lerr + movlw 0x93 + subwf br3,W + btfss STATUS,Z + goto lerr + movlw 0x94 + subwf br4,W + btfss STATUS,Z + goto lerr + movlw 0x95 + subwf br5,W + btfss STATUS,Z + goto lerr + movlw 0x96 + subwf br6,W + btfss STATUS,Z + goto lerr + movlw 0x97 + subwf br7,W + btfss STATUS,Z + goto lerr + movlw 0x98 + subwf br8,W + btfss STATUS,Z + goto lerr + movlw 0x99 + subwf br9,W + btfss STATUS,Z + goto lerr + movlw 0x9a + subwf br10,W + btfss STATUS,Z + goto lerr + movlw 0x9b + subwf br11,W + btfss STATUS,Z + goto lerr + movlw 0x9c + subwf br12,W + btfss STATUS,Z + goto lerr + movlw 0x9d + subwf br13,W + btfss STATUS,Z + goto lerr + movlw 0x9e + subwf br14,W + btfss STATUS,Z + goto lerr + movlw 0x9f + subwf br15,W + btfss STATUS,Z + goto lerr + + ; Register File TEST 2 + movlw 0x02 + movwf PORTB ; Set Test Number + + bsf FSR,5 ; Select Register Bank 01 + + movlw 0x81 + subwf r0,W + btfss STATUS,Z + goto lerr + movlw 0x82 + subwf r1,W + btfss STATUS,Z + goto lerr + movlw 0x83 + subwf r2,W + btfss STATUS,Z + goto lerr + movlw 0x84 + subwf r3,W + btfss STATUS,Z + goto lerr + movlw 0x85 + subwf r4,W + btfss STATUS,Z + goto lerr + movlw 0x86 + subwf r5,W + btfss STATUS,Z + goto lerr + movlw 0x87 + subwf r6,W + btfss STATUS,Z + goto lerr + movlw 0x88 + subwf r7,W + btfss STATUS,Z + goto lerr + + movlw 0xa0 + subwf br0,W + btfss STATUS,Z + goto lerr + movlw 0xa1 + subwf br1,W + btfss STATUS,Z + goto lerr + movlw 0xa2 + subwf br2,W + btfss STATUS,Z + goto lerr + movlw 0xa3 + subwf br3,W + btfss STATUS,Z + goto lerr + movlw 0xa4 + subwf br4,W + btfss STATUS,Z + goto lerr + movlw 0xa5 + subwf br5,W + btfss STATUS,Z + goto lerr + movlw 0xa6 + subwf br6,W + btfss STATUS,Z + goto lerr + movlw 0xa7 + subwf br7,W + btfss STATUS,Z + goto lerr + movlw 0xa8 + subwf br8,W + btfss STATUS,Z + goto lerr + movlw 0xa9 + subwf br9,W + btfss STATUS,Z + goto lerr + movlw 0xaa + subwf br10,W + btfss STATUS,Z + goto lerr + movlw 0xab + subwf br11,W + btfss STATUS,Z + goto lerr + movlw 0xac + subwf br12,W + btfss STATUS,Z + goto lerr + movlw 0xad + subwf br13,W + btfss STATUS,Z + goto lerr + movlw 0xae + subwf br14,W + btfss STATUS,Z + goto lerr + movlw 0xaf + subwf br15,W + btfss STATUS,Z + goto lerr + + ; Register File TEST 3 + movlw 0x03 + movwf PORTB ; Set Test Number + + bcf FSR,5 ; Select Register Bank 10 + bsf FSR,6 + + movlw 0x81 + subwf r0,W + btfss STATUS,Z + goto lerr + movlw 0x82 + subwf r1,W + btfss STATUS,Z + goto lerr + movlw 0x83 + subwf r2,W + btfss STATUS,Z + goto lerr + movlw 0x84 + subwf r3,W + btfss STATUS,Z + goto lerr + movlw 0x85 + subwf r4,W + btfss STATUS,Z + goto lerr + movlw 0x86 + subwf r5,W + btfss STATUS,Z + goto lerr + movlw 0x87 + subwf r6,W + btfss STATUS,Z + goto lerr + movlw 0x88 + subwf r7,W + btfss STATUS,Z + goto lerr + + movlw 0xb0 + subwf br0,W + btfss STATUS,Z + goto lerr + movlw 0xb1 + subwf br1,W + btfss STATUS,Z + goto lerr + movlw 0xb2 + subwf br2,W + btfss STATUS,Z + goto lerr + movlw 0xb3 + subwf br3,W + btfss STATUS,Z + goto lerr + movlw 0xb4 + subwf br4,W + btfss STATUS,Z + goto lerr + movlw 0xb5 + subwf br5,W + btfss STATUS,Z + goto lerr + movlw 0xb6 + subwf br6,W + btfss STATUS,Z + goto lerr + movlw 0xb7 + subwf br7,W + btfss STATUS,Z + goto lerr + movlw 0xb8 + subwf br8,W + btfss STATUS,Z + goto lerr + movlw 0xb9 + subwf br9,W + btfss STATUS,Z + goto lerr + movlw 0xba + subwf br10,W + btfss STATUS,Z + goto lerr + movlw 0xbb + subwf br11,W + btfss STATUS,Z + goto lerr + movlw 0xbc + subwf br12,W + btfss STATUS,Z + goto lerr + movlw 0xbd + subwf br13,W + btfss STATUS,Z + goto lerr + movlw 0xbe + subwf br14,W + btfss STATUS,Z + goto lerr + movlw 0xbf + subwf br15,W + btfss STATUS,Z + goto lerr + + + ; Register File TEST 4 + movlw 0x04 + movwf PORTB ; Set Test Number + + bsf FSR,5 ; Select Register Bank 11 + bsf FSR,6 + + movlw 0x81 + subwf r0,W + btfss STATUS,Z + goto lerr + movlw 0x82 + subwf r1,W + btfss STATUS,Z + goto lerr + movlw 0x83 + subwf r2,W + btfss STATUS,Z + goto lerr + movlw 0x84 + subwf r3,W + btfss STATUS,Z + goto lerr + movlw 0x85 + subwf r4,W + btfss STATUS,Z + goto lerr + movlw 0x86 + subwf r5,W + btfss STATUS,Z + goto lerr + movlw 0x87 + subwf r6,W + btfss STATUS,Z + goto lerr + movlw 0x88 + subwf r7,W + btfss STATUS,Z + goto lerr + + movlw 0xc0 + subwf br0,W + btfss STATUS,Z + goto lerr + movlw 0xc1 + subwf br1,W + btfss STATUS,Z + goto lerr + movlw 0xc2 + subwf br2,W + btfss STATUS,Z + goto lerr + movlw 0xc3 + subwf br3,W + btfss STATUS,Z + goto lerr + movlw 0xc4 + subwf br4,W + btfss STATUS,Z + goto lerr + movlw 0xc5 + subwf br5,W + btfss STATUS,Z + goto lerr + movlw 0xc6 + subwf br6,W + btfss STATUS,Z + goto lerr + movlw 0xc7 + subwf br7,W + btfss STATUS,Z + goto lerr + movlw 0xc8 + subwf br8,W + btfss STATUS,Z + goto lerr + movlw 0xc9 + subwf br9,W + btfss STATUS,Z + goto lerr + movlw 0xca + subwf br10,W + btfss STATUS,Z + goto lerr + movlw 0xcb + subwf br11,W + btfss STATUS,Z + goto lerr + movlw 0xcc + subwf br12,W + btfss STATUS,Z + goto lerr + movlw 0xcd + subwf br13,W + btfss STATUS,Z + goto lerr + movlw 0xce + subwf br14,W + btfss STATUS,Z + goto lerr + movlw 0xcf + subwf br15,W + btfss STATUS,Z + goto lerr + + + nop + nop + nop + nop + movlw 0x01 + movwf PORTA + nop + nop + nop + nop +good ; Loop in good on success + goto good + nop + nop + nop + nop + +lerr + movlw 0xff + movwf PORTA + + nop + nop + nop + nop +lerr_loop ; Loop in lerr on failure + goto lerr_loop + nop + nop + nop + nop + + END + Index: minirisc/trunk/scode/sanity1.asm =================================================================== --- minirisc/trunk/scode/sanity1.asm (nonexistent) +++ minirisc/trunk/scode/sanity1.asm (revision 7) @@ -0,0 +1,250 @@ +;///////////////////////////////////////////////////////////////////// +;//// //// +;//// Mini-RISC-1 //// +;//// Compliance Test 1 //// +;//// Tests Ports //// +;//// //// +;//// Author: Rudolf Usselmann //// +;//// russelmann@hotmail.com //// +;//// //// +;///////////////////////////////////////////////////////////////////// +;//// //// +;//// Copyright (C) 2000 Rudolf Usselmann //// +;//// russelmann@hotmail.com //// +;//// //// +;//// This source file may be used and distributed without //// +;//// restriction provided that this copyright statement is not //// +;//// removed from the file and that any derivative work contains //// +;//// the original copyright notice and the associated disclaimer.//// +;//// //// +;//// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY //// +;//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT //// +;//// LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND //// +;//// FITNESS FOR A PARTICULAR PURPOSE. //// +;//// //// +;///////////////////////////////////////////////////////////////////// + + list p=16c57 + #include p16c5x.inc + + +main ; Main code entry + ; Port IO Test + ; All ports have a Pull up resistor + + ; Tristate all ports + clrw + movwf PORTA + movwf PORTB + movwf PORTC + xorlw 0xff + tris PORTA + tris PORTB + tris PORTC + + ; Now check that porta is 0xff + btfss PORTA,0 + goto lerr + btfss PORTA,1 + goto lerr + btfss PORTA,2 + goto lerr + btfss PORTA,3 + goto lerr + btfss PORTA,4 + goto lerr + btfss PORTA,5 + goto lerr + btfss PORTA,6 + goto lerr + btfss PORTA,7 + goto lerr + + + ; Now check that portb is 0xff + btfss PORTB,0 + goto lerr + btfss PORTB,1 + goto lerr + btfss PORTB,2 + goto lerr + btfss PORTB,3 + goto lerr + btfss PORTB,4 + goto lerr + btfss PORTB,5 + goto lerr + btfss PORTB,6 + goto lerr + btfss PORTB,7 + goto lerr + + ; Now check that portc is 0xff + btfss PORTC,0 + goto lerr + btfss PORTC,1 + goto lerr + btfss PORTC,2 + goto lerr + btfss PORTC,3 + goto lerr + btfss PORTC,4 + goto lerr + btfss PORTC,5 + goto lerr + btfss PORTA,6 + goto lerr + btfss PORTC,7 + goto lerr + + + + ; Enable all ports + clrw + tris PORTA + tris PORTB + tris PORTC + + ; Drive them all 0xaa + clrw + xorlw 0xaa + movwf PORTA + movwf PORTB + movwf PORTC + + ; Now check that porta is 0xaa + btfsc PORTA,0 + goto lerr + btfss PORTA,1 + goto lerr + btfsc PORTA,2 + goto lerr + btfss PORTA,3 + goto lerr + btfsc PORTA,4 + goto lerr + btfss PORTA,5 + goto lerr + btfsc PORTA,6 + goto lerr + btfss PORTA,7 + goto lerr + + ; Now check that portb is 0xaa + btfsc PORTB,0 + goto lerr + btfss PORTB,1 + goto lerr + btfsc PORTB,2 + goto lerr + btfss PORTB,3 + goto lerr + btfsc PORTB,4 + goto lerr + btfss PORTB,5 + goto lerr + btfsc PORTB,6 + goto lerr + btfss PORTB,7 + goto lerr + + ; Now check that portc is 0xaa + btfsc PORTC,0 + goto lerr + btfss PORTC,1 + goto lerr + btfsc PORTC,2 + goto lerr + btfss PORTC,3 + goto lerr + btfsc PORTC,4 + goto lerr + btfss PORTC,5 + goto lerr + btfsc PORTC,6 + goto lerr + btfss PORTC,7 + goto lerr + + ; Drive them all 0x55 + clrw + xorlw 0x55 + movwf PORTA + movwf PORTB + movwf PORTC + + ; Now check that porta is 0x55 + btfss PORTA,0 + goto lerr + btfsc PORTA,1 + goto lerr + btfss PORTA,2 + goto lerr + btfsc PORTA,3 + goto lerr + btfss PORTA,4 + goto lerr + btfsc PORTA,5 + goto lerr + btfss PORTA,6 + goto lerr + btfsc PORTA,7 + goto lerr + + ; Now check that portb is 0x55 + btfss PORTB,0 + goto lerr + btfsc PORTB,1 + goto lerr + btfss PORTB,2 + goto lerr + btfsc PORTB,3 + goto lerr + btfss PORTB,4 + goto lerr + btfsc PORTB,5 + goto lerr + btfss PORTB,6 + goto lerr + btfsc PORTB,7 + goto lerr + + ; Now check that portc is 0x55 + btfss PORTC,0 + goto lerr + btfsc PORTC,1 + goto lerr + btfss PORTC,2 + goto lerr + btfsc PORTC,3 + goto lerr + btfss PORTC,4 + goto lerr + btfsc PORTC,5 + goto lerr + btfss PORTC,6 + goto lerr + btfsc PORTC,7 + goto lerr + + nop + nop + nop + nop + +good ; Loop in good on success + goto good + nop + nop + nop + nop + +lerr ; Loop in lerr on failure + goto lerr + nop + nop + nop + nop + + END + Index: minirisc/trunk/scode/rf2.asm =================================================================== --- minirisc/trunk/scode/rf2.asm (nonexistent) +++ minirisc/trunk/scode/rf2.asm (revision 7) @@ -0,0 +1,827 @@ +;///////////////////////////////////////////////////////////////////// +;//// //// +;//// Mini-RISC-1 //// +;//// Register File Test 2 //// +;//// Tests Register File //// +;//// //// +;//// Author: Rudolf Usselmann //// +;//// russelmann@hotmail.com //// +;//// //// +;///////////////////////////////////////////////////////////////////// +;//// //// +;//// Copyright (C) 2000 Rudolf Usselmann //// +;//// russelmann@hotmail.com //// +;//// //// +;//// This source file may be used and distributed without //// +;//// restriction provided that this copyright statement is not //// +;//// removed from the file and that any derivative work contains //// +;//// the original copyright notice and the associated disclaimer.//// +;//// //// +;//// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY //// +;//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT //// +;//// LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND //// +;//// FITNESS FOR A PARTICULAR PURPOSE. //// +;//// //// +;///////////////////////////////////////////////////////////////////// + + list p=16c57 + #include p16c5x.inc + +; global Registers +r0 equ 0x8 +r1 equ 0x9 +r2 equ 0xa +r3 equ 0xb +r4 equ 0xc +r5 equ 0xd +r6 equ 0xe +r7 equ 0xf + +; banked Registers +br0 equ 0x10 +br1 equ 0x11 +br2 equ 0x12 +br3 equ 0x13 +br4 equ 0x14 +br5 equ 0x15 +br6 equ 0x16 +br7 equ 0x17 +br8 equ 0x18 +br9 equ 0x19 +br10 equ 0x1a +br11 equ 0x1b +br12 equ 0x1c +br13 equ 0x1d +br14 equ 0x1e +br15 equ 0x1f + + +; PORTB Indicates Test Number +; PORTA Indicates Status: 0 - Running; 1 - done OK; ff - stoped on error + +main ; Main code entry + ; Port IO Test + ; All ports have a Pull up resistor + + ; SETUP all ports + clrw + movwf FSR + movwf PORTA + movwf PORTB + movwf PORTC + tris PORTA + tris PORTB + tris PORTC + + bsf STATUS,5 + + ; --------------------------------------- + ; ---- Test the entire register file ---- + ; --------------------------------------- + + movlw 0x81 + movwf r0 + movlw 0x82 + movwf r1 + movlw 0x83 + movwf r2 + movlw 0x84 + movwf r3 + movlw 0x85 + movwf r4 + movlw 0x86 + movwf r5 + movlw 0x87 + movwf r6 + movlw 0x88 + movwf r7 + + + movlw 0x90 + movwf br0 + movlw 0x91 + movwf br1 + movlw 0x92 + movwf br2 + movlw 0x93 + movwf br3 + movlw 0x94 + movwf br4 + movlw 0x95 + movwf br5 + movlw 0x96 + movwf br6 + movlw 0x97 + movwf br7 + movlw 0x98 + movwf br8 + movlw 0x99 + movwf br9 + movlw 0x9a + movwf br10 + movlw 0x9b + movwf br11 + movlw 0x9c + movwf br12 + movlw 0x9d + movwf br13 + movlw 0x9e + movwf br14 + movlw 0x9f + movwf br15 + + bsf FSR,5 ; Select Register Bank 01 + + movlw 0xa0 + movwf br0 + movlw 0xa1 + movwf br1 + movlw 0xa2 + movwf br2 + movlw 0xa3 + movwf br3 + movlw 0xa4 + movwf br4 + movlw 0xa5 + movwf br5 + movlw 0xa6 + movwf br6 + movlw 0xa7 + movwf br7 + movlw 0xa8 + movwf br8 + movlw 0xa9 + movwf br9 + movlw 0xaa + movwf br10 + movlw 0xab + movwf br11 + movlw 0xac + movwf br12 + movlw 0xad + movwf br13 + movlw 0xae + movwf br14 + movlw 0xaf + movwf br15 + + bcf FSR,5 ; Select Register Bank 10 + bsf FSR,6 + + movlw 0xb0 + movwf br0 + movlw 0xb1 + movwf br1 + movlw 0xb2 + movwf br2 + movlw 0xb3 + movwf br3 + movlw 0xb4 + movwf br4 + movlw 0xb5 + movwf br5 + movlw 0xb6 + movwf br6 + movlw 0xb7 + movwf br7 + movlw 0xb8 + movwf br8 + movlw 0xb9 + movwf br9 + movlw 0xba + movwf br10 + movlw 0xbb + movwf br11 + movlw 0xbc + movwf br12 + movlw 0xbd + movwf br13 + movlw 0xbe + movwf br14 + movlw 0xbf + movwf br15 + + bsf FSR,5 ; Select Register Bank 11 + bsf FSR,6 + + movlw 0xc0 + movwf br0 + movlw 0xc1 + movwf br1 + movlw 0xc2 + movwf br2 + movlw 0xc3 + movwf br3 + movlw 0xc4 + movwf br4 + movlw 0xc5 + movwf br5 + movlw 0xc6 + movwf br6 + movlw 0xc7 + movwf br7 + movlw 0xc8 + movwf br8 + movlw 0xc9 + movwf br9 + movlw 0xca + movwf br10 + movlw 0xcb + movwf br11 + movlw 0xcc + movwf br12 + movlw 0xcd + movwf br13 + movlw 0xce + movwf br14 + movlw 0xcf + movwf br15 + + movlw r0 + movwf FSR + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + + + movlw br0 + movwf FSR + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + + movlw br0 + movwf FSR + bsf FSR,5 + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + + movlw br0 + movwf FSR + bsf FSR,6 + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + + movlw br0 + movwf FSR + bsf FSR,5 + bsf FSR,6 + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + + ; Register File TEST 1 + movlw 0x01 + movwf PORTB ; Set Test Number + + movlw r0 + movwf FSR + movlw 0x7e + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x7d + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x7c + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x7b + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x7a + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x79 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x78 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x77 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + + movlw br0 + movwf FSR + movlw 0x6f + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x6e + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x6d + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x6c + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x6b + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x6a + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x69 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x68 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x67 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x66 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x65 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x64 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x63 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x62 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x61 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x60 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + + ; Register File TEST 2 + movlw 0x02 + movwf PORTB ; Set Test Number + + movlw br0 + movwf FSR + bsf FSR,5 + movlw 0x5f + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x5e + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x5d + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x5c + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x5b + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x5a + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x59 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x58 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x57 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x56 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x55 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x54 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x53 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x52 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x51 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x50 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + + ; Register File TEST 3 + movlw 0x03 + movwf PORTB ; Set Test Number + + movlw br0 + movwf FSR + bsf FSR,6 + movlw 0x4f + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x4e + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x4d + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x4c + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x4b + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x4a + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x49 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x48 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x47 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x46 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x45 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x44 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x43 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x42 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x41 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x40 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + + ; Register File TEST 4 + movlw 0x04 + movwf PORTB ; Set Test Number + + movlw br0 + movwf FSR + bsf FSR,5 + bsf FSR,6 + movlw 0x3f + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x3e + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x3d + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x3c + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x3b + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x3a + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x39 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x38 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x37 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x36 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x35 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x34 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x33 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x32 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x31 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x30 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + + nop + nop + nop + nop + movlw 0x01 + movwf PORTA + nop + nop + nop + nop +good ; Loop in good on success + goto good + nop + nop + nop + nop + +lerr + movlw 0xff + movwf PORTA + + nop + nop + nop + nop +lerr_loop ; Loop in lerr on failure + goto lerr_loop + nop + nop + nop + nop + + END + Index: minirisc/trunk/scode/sanity2.asm =================================================================== --- minirisc/trunk/scode/sanity2.asm (nonexistent) +++ minirisc/trunk/scode/sanity2.asm (revision 7) @@ -0,0 +1,454 @@ +;///////////////////////////////////////////////////////////////////// +;//// //// +;//// Mini-RISC-1 //// +;//// Compliance Test 2 //// +;//// Tests PLC register Rd/Wr //// +;//// //// +;//// Author: Rudolf Usselmann //// +;//// russelmann@hotmail.com //// +;//// //// +;///////////////////////////////////////////////////////////////////// +;//// //// +;//// Copyright (C) 2000 Rudolf Usselmann //// +;//// russelmann@hotmail.com //// +;//// //// +;//// This source file may be used and distributed without //// +;//// restriction provided that this copyright statement is not //// +;//// removed from the file and that any derivative work contains //// +;//// the original copyright notice and the associated disclaimer.//// +;//// //// +;//// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY //// +;//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT //// +;//// LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND //// +;//// FITNESS FOR A PARTICULAR PURPOSE. //// +;//// //// +;///////////////////////////////////////////////////////////////////// + + list p=16c57 + #include p16c5x.inc + +; global Registers +r0 equ 0x8 +r1 equ 0x9 +r2 equ 0xa +r3 equ 0xb +r4 equ 0xc +r5 equ 0xd +r6 equ 0xe +r7 equ 0xf + +; banked Registers +br0 equ 0x10 +br1 equ 0x11 +br2 equ 0x12 +br3 equ 0x13 +br4 equ 0x14 +br5 equ 0x15 +br6 equ 0x16 +br7 equ 0x17 +br8 equ 0x18 +br9 equ 0x19 +br10 equ 0x1a +br11 equ 0x1b +br12 equ 0x1c +br13 equ 0x1d +br14 equ 0x1e +br15 equ 0x1f + + +; PORTB Indicates Test Number +; PORTA Indicates Status: 0 - Running; 1 - done OK; ff - stoped on error + +main ; Main code entry + ; Port IO Test + ; All ports have a Pull up resistor + + ; SETUP all ports + clrw + movwf FSR + movwf PORTA + movwf PORTB + movwf PORTC + tris PORTA + tris PORTB + tris PORTC + + ; ------------------------------- + ; ---- Test the PLC register ---- + ; ------------------------------- + + ; PLC read test 1 TEST 0 + + movlw pclrd1 + movwf r0 + movf PCL,W +pclrd1 subwf r0,W + btfss STATUS,Z + goto lerr + + ; PLC read test 2 TEST 1 + movlw 0x01 + movwf PORTB ; Set Test Number + + movlw pclrd2 + movwf r3 + movf PCL,W +pclrd2 subwf r3,W + btfss STATUS,Z + goto lerr + + ; PLC write test 2 TEST 2 + movlw 0x02 + movwf PORTB ; Set Test Number + + movlw pclwr1 + movwf PCL + + goto lerr + goto lerr + goto lerr +pclwr1 goto pcl1 + goto lerr + goto lerr + goto lerr + +pcl1 + ; PLC write test 2 TEST 3 + movlw 0x03 + movwf PORTB ; Set Test Number + + movlw pclwr2 + movwf PCL + + goto lerr + goto lerr + goto lerr +pclwr2 goto pcl2 + goto lerr + goto lerr + goto lerr + +pcl2 ; Test other instructions that modify PC + ; This are ADDWF PC, BSF PC,X and BCF PC,X + ; (movwf pc already tested above) + + ; PLC write test 3 TEST 4 + ; test addwf PC + movlw 0x04 + movwf PORTB ; Set Test Number + + movlw pcl3b + movwf r0 + movlw pcl3a + subwf r0,W +pcl3a addwf PCL,1 + + goto lerr + goto lerr +pcl3b goto lerr + goto pcl3c + goto lerr + goto lerr + goto lerr +pcl3c + + ; PLC write test 4 TEST 5 + ; test addwf PC + movlw 0x05 + movwf PORTB ; Set Test Number + + movlw pcl4b + movwf br8 + movlw pcl4a + subwf br8,W +pcl4a addwf PCL,1 + + goto lerr + goto lerr +pcl4b goto lerr + goto pcl4c + goto lerr + goto lerr + goto lerr +pcl4c + + ; PLC write test 5 TEST 6 + ; test bsf PC,N + movlw 0x06 + movwf PORTB ; Set Test N + +; allign memory + goto pcl50 + +pcl50 org 0x60 + + bsf PCL,1 ; 60 + goto lerr ; 61 + goto lerr ; 62 + goto pcl5a ; 63 + goto lerr ; 64 + goto lerr ; 65 + goto lerr ; 66 + goto lerr ; 67 + +pcl5a + + ; PLC write test 6 TEST 7 + ; test bsf PC,N + movlw 0x07 + movwf PORTB ; Set Test N + + bsf PCL,2 ; 6A + goto lerr ; 6B + goto lerr ; 6C + goto lerr ; 6D + goto lerr ; 6E + goto pcl6a ; 6F + goto lerr ; 70 + goto lerr ; 71 + +pcl6a + + ; PLC write test 7 TEST 8 + ; test bcf PC,N + movlw 0x08 + movwf PORTB ; Set Test N + + goto pcl7a ; 74 + goto lerr ; 75 + goto lerr ; 76 + goto lerr ; 77 + goto lerr ; 78 + goto pcl7b ; 79 + goto lerr ; 7a + goto lerr ; 7b + +pcl7a + bcf PCL,2 ; 7c + +pcl7b + + + ; Make sure goto works + movlw 0x09 ; TEST 9 + movwf PORTB ; Set Test Number + + + goto gt1 + nop + nop + nop + nop + movlw 0xff + movwf PORTA + nop + nop + nop + nop +gt1 + + ; Make sure call works + movlw 0x0a ; TEST 10 + movwf PORTB ; Set Test Number + + call cal1 + movwf r0 + movlw 0x55 + subwf r0,w + btfss STATUS,Z + goto lerr + + call cal2 + movwf r0 + movlw 0xaa + subwf r0,w + btfss STATUS,Z + goto lerr + + call cal3 + movwf r0 + movlw 0xc3 + subwf r0,w + btfss STATUS,Z + goto lerr + + call cal4 + movwf r0 + movlw 0x3c + subwf r0,w + btfss STATUS,Z + goto lerr + + goto next1 + +cal1 + retlw 0x55 + goto lerr + +cal2 + nop + retlw 0xaa + goto lerr + +cal3 + nop + nop + retlw 0xc3 + goto lerr + +cal4 + nop + nop + nop + retlw 0x3c + goto lerr + +table1 + addwf PCL,F + retlw 0xff + retlw 0xfe + retlw 0xfd + retlw 0xfc + retlw 0xfb + retlw 0xfa + retlw 0xf9 + retlw 0xf8 + retlw 0xf7 + retlw 0xf6 + retlw 0xf5 + goto lerr + goto lerr + goto lerr + goto lerr + goto lerr + goto lerr + +next1 + + + ; Make sure call works (2) + movlw 0x0b ; TEST 11 + movwf PORTB ; Set Test Number + + movlw 0x0 + movwf r0 + call table1 + comf r0,F + subwf r0,F + btfss STATUS,Z + goto lerr + + movlw 0x1 + movwf r0 + call table1 + comf r0,F + subwf r0,F + btfss STATUS,Z + goto lerr + + movlw 0x2 + movwf r0 + call table1 + comf r0,F + subwf r0,F + btfss STATUS,Z + goto lerr + + movlw 0x3 + movwf r0 + call table1 + comf r0,F + subwf r0,F + btfss STATUS,Z + goto lerr + + movlw 0x4 + movwf r0 + call table1 + comf r0,F + subwf r0,F + btfss STATUS,Z + goto lerr + + movlw 0x5 + movwf r0 + call table1 + comf r0,F + subwf r0,F + btfss STATUS,Z + goto lerr + + movlw 0x6 + movwf r0 + call table1 + comf r0,F + subwf r0,F + btfss STATUS,Z + goto lerr + + movlw 0x7 + movwf r0 + call table1 + comf r0,F + subwf r0,F + btfss STATUS,Z + goto lerr + + movlw 0x8 + movwf r0 + call table1 + comf r0,F + subwf r0,F + btfss STATUS,Z + goto lerr + + movlw 0x9 + movwf r0 + call table1 + comf r0,F + subwf r0,F + btfss STATUS,Z + goto lerr + + movlw 0xa + movwf r0 + call table1 + comf r0,F + subwf r0,F + btfss STATUS,Z + goto lerr + + nop + nop + nop + nop + movlw 0x01 + movwf PORTA + nop + nop + nop + nop +good ; Loop in good on success + goto good + nop + nop + nop + nop + +lerr + movlw 0xff + movwf PORTA + + nop + nop + nop + nop +lerr_loop ; Loop in lerr on failure + goto lerr_loop + nop + nop + nop + nop + + END + Index: minirisc/trunk/scode/rf3.asm =================================================================== --- minirisc/trunk/scode/rf3.asm (nonexistent) +++ minirisc/trunk/scode/rf3.asm (revision 7) @@ -0,0 +1,338 @@ +;///////////////////////////////////////////////////////////////////// +;//// //// +;//// Mini-RISC-1 //// +;//// Register File Test 3 //// +;//// Tests Register File //// +;//// //// +;//// Author: Rudolf Usselmann //// +;//// russelmann@hotmail.com //// +;//// //// +;///////////////////////////////////////////////////////////////////// +;//// //// +;//// Copyright (C) 2000 Rudolf Usselmann //// +;//// russelmann@hotmail.com //// +;//// //// +;//// This source file may be used and distributed without //// +;//// restriction provided that this copyright statement is not //// +;//// removed from the file and that any derivative work contains //// +;//// the original copyright notice and the associated disclaimer.//// +;//// //// +;//// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY //// +;//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT //// +;//// LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND //// +;//// FITNESS FOR A PARTICULAR PURPOSE. //// +;//// //// +;///////////////////////////////////////////////////////////////////// + + list p=16c57 + #include p16c5x.inc + +; global Registers +r0 equ 0x8 +r1 equ 0x9 +r2 equ 0xa +r3 equ 0xb +r4 equ 0xc +r5 equ 0xd +r6 equ 0xe +r7 equ 0xf + +; banked Registers +br0 equ 0x10 +br1 equ 0x11 +br2 equ 0x12 +br3 equ 0x13 +br4 equ 0x14 +br5 equ 0x15 +br6 equ 0x16 +br7 equ 0x17 +br8 equ 0x18 +br9 equ 0x19 +br10 equ 0x1a +br11 equ 0x1b +br12 equ 0x1c +br13 equ 0x1d +br14 equ 0x1e +br15 equ 0x1f + + +; PORTB Indicates Test Number +; PORTA Indicates Status: 0 - Running; 1 - done OK; ff - stoped on error + +main ; Main code entry + ; Port IO Test + ; All ports have a Pull up resistor + + ; SETUP all ports + clrw + movwf FSR + movwf PORTA + movwf PORTB + movwf PORTC + tris PORTA + tris PORTB + tris PORTC + + ; --------------------------------------- + ; ---- Test RMW on Register fil ---- + ; --------------------------------------- + + movlw 0x01 ; TEST 1 + movwf PORTB ; Set Test Number + + movlw 0xfc + movwf r0 + incf r0,F + incf r0,F + incf r0,F + incf r0,F + btfss STATUS,Z + goto lerr + + movlw 0xfc + movwf br8 + incf br8,F + incf br8,F + incf br8,F + incf br8,F + btfss STATUS,Z + goto lerr + + movlw 0x02 ; TEST 2 + movwf PORTB ; Set Test Number + + movlw r1 + movwf FSR + movlw 0xfc + movwf INDF + incf INDF,F + incf INDF,F + incf INDF,F + incf INDF,F + btfss STATUS,Z + goto lerr + + movlw br9 + movwf FSR + movlw 0xfc + movwf INDF + incf INDF,F + incf INDF,F + incf INDF,F + incf INDF,F + btfss STATUS,Z + goto lerr + + + + movlw 0x03 ; TEST 3 + movwf PORTB ; Set Test Number + + movlw 0x04 + movwf r0 + decf r0,F + decf r0,F + decf r0,F + decf r0,F + btfss STATUS,Z + goto lerr + + + movlw 0x04 + movwf br0 + decf br0,F + decf br0,F + decf br0,F + decf br0,F + btfss STATUS,Z + goto lerr + + + movlw 0x04 ; TEST 4 + movwf PORTB ; Set Test Number + + movlw r1 + movwf FSR + movlw 0x04 + movwf INDF + decf INDF,F + decf INDF,F + decf INDF,F + decf INDF,F + btfss STATUS,Z + goto lerr + + movlw br9 + movwf FSR + movlw 0x04 + movwf INDF + decf INDF,F + decf INDF,F + decf INDF,F + decf INDF,F + btfss STATUS,Z + goto lerr + + + movlw 0x05 ; TEST 5 + movwf PORTB ; Set Test Number + + movlw 0xfc + movwf r4 + incfsz r4,F + incfsz r4,F + incfsz r4,F + incfsz r4,F + goto lerr + + movlw 0xfc + movwf br8 + incfsz br8,F + incfsz br8,F + incfsz br8,F + incfsz br8,F + goto lerr + + + movlw 0x06 ; TEST 6 + movwf PORTB ; Set Test Number + + movlw r1 + movwf FSR + movlw 0xfc + movwf INDF + incfsz INDF,F + incfsz INDF,F + incfsz INDF,F + incfsz INDF,F + goto lerr + + movlw br9 + movwf FSR + movlw 0xfc + movwf INDF + incfsz INDF,F + incfsz INDF,F + incfsz INDF,F + incfsz INDF,F + goto lerr + + movlw 0x07 ; TEST 7 + movwf PORTB ; Set Test Number + + movlw 0x04 + movwf r0 + decfsz r0,F + decfsz r0,F + decfsz r0,F + decfsz r0,F + goto lerr + + + movlw 0x04 + movwf br0 + decfsz br0,F + decfsz br0,F + decfsz br0,F + decfsz br0,F + goto lerr + + + movlw 0x08 ; TEST 8 + movwf PORTB ; Set Test Number + + movlw r1 + movwf FSR + movlw 0x04 + movwf INDF + decfsz INDF,F + decfsz INDF,F + decfsz INDF,F + decfsz INDF,F + goto lerr + + movlw br9 + movwf FSR + movlw 0x04 + movwf INDF + decfsz INDF,F + decfsz INDF,F + decfsz INDF,F + decfsz INDF,F + goto lerr + + + movlw 0x09 ; TEST 9 + movwf PORTB ; Set Test Number + + movlw 0xfc + movwf FSR + incf FSR,F + incf FSR,F + incf FSR,F + incf FSR,F + btfss STATUS,Z + goto lerr + + movlw 0x04 + movwf FSR + movlw 0x7f + decf FSR,F + decf FSR,F + decf FSR,F + decf FSR,F + andwf FSR,F + btfss STATUS,Z + goto lerr + + movlw 0x0a ; TEST 10 + movwf PORTB ; Set Test Number + + movlw 0xfc + movwf STATUS + movlw 0x18 + incf STATUS,F + incf STATUS,F + incf STATUS,F + incf STATUS,F + subwf STATUS,W + btfss STATUS,Z + goto lerr + + + + + nop + nop + nop + nop + movlw 0x01 + movwf PORTA + nop + nop + nop + nop +good ; Loop in good on success + goto good + nop + nop + nop + nop + +lerr + movlw 0xff + movwf PORTA + + nop + nop + nop + nop +lerr_loop ; Loop in lerr on failure + goto lerr_loop + nop + nop + nop + nop + + END + Index: minirisc/trunk/scode/tmr_wdt.rom =================================================================== --- minirisc/trunk/scode/tmr_wdt.rom (nonexistent) +++ minirisc/trunk/scode/tmr_wdt.rom (revision 7) @@ -0,0 +1,63 @@ + +@000 040 +@001 024 +@002 025 +@003 026 +@004 027 +@005 005 +@006 006 +@007 007 +@008 C01 +@009 026 +@00A C00 +@00B 002 +@00C 021 +@00D 004 +@00E 000 +@00F 000 +@010 000 +@011 000 +@012 040 +@013 029 +@014 040 +@015 028 +@016 201 +@017 2E8 +@018 A16 +@019 2E9 +@01A A14 +@01B 000 +@01C 000 +@01D 000 +@01E 000 +@01F 000 +@020 000 +@021 040 +@022 021 +@023 004 +@024 000 +@025 000 +@026 000 +@027 000 +@028 C01 +@029 025 +@02A 000 +@02B 000 +@02C 000 +@02D 000 +@02E A2E +@02F 000 +@030 000 +@031 000 +@032 000 +@033 CFF +@034 025 +@035 000 +@036 000 +@037 000 +@038 000 +@039 A39 +@03A 000 +@03B 000 +@03C 000 +@03D 000 Index: minirisc/trunk/scode/hex2v.c =================================================================== --- minirisc/trunk/scode/hex2v.c (nonexistent) +++ minirisc/trunk/scode/hex2v.c (revision 7) @@ -0,0 +1,125 @@ +/* *********************************************************************** + The Free IP Project + Free-RISC8 -- Verilog 8-bit Microcontroller + (c) 1999, The Free IP Project and Thomas Coonan + + + FREE IP GENERAL PUBLIC LICENSE + TERMS AND CONDITIONS FOR USE, COPYING, DISTRIBUTION, AND MODIFICATION + + 1. You may copy and distribute verbatim copies of this core, as long + as this file, and the other associated files, remain intact and + unmodified. Modifications are outlined below. + 2. You may use this core in any way, be it academic, commercial, or + military. Modified or not. + 3. Distribution of this core must be free of charge. Charging is + allowed only for value added services. Value added services + would include copying fees, modifications, customizations, and + inclusion in other products. + 4. If a modified source code is distributed, the original unmodified + source code must also be included (or a link to the Free IP web + site). In the modified source code there must be clear + identification of the modified version. + 5. Visit the Free IP web site for additional information. + http://www.free-ip.com + +*********************************************************************** */ + +// Intel HEX to Verilog converter. +// +// Usage: +// hex2v +// +// You probably want to simply redirect the output into a file. +// +#include +#include +#include + +// Input and Output file streams. +FILE *fpi; + +// Well.. Let's read stuff in completely before outputting.. Programs +// should be pretty small.. +// +#define MAX_MEMORY_SIZE 2048 +struct { + unsigned int nAddress; + unsigned int byData; +} Memory[MAX_MEMORY_SIZE]; + +char szLine[80]; +unsigned int start_address, address, ndata_bytes, ndata_words; +unsigned int data; +unsigned int nMemoryCount; + +int main (int argc, char *argv[]) +{ + int i; + + if (argc != 2) { + printf ("\nThe Synthetic PIC --- Intel HEX File to Verilog memory file"); + printf ("\nUsage: hex2verilog "); + printf ("\n"); + return 0; + } + + + // Open input HEX file + fpi=fopen(argv[1], "r"); + if (!fpi) { + printf("\nCan't open input file %s.\n", argv[1]); + return 1; + } + + // Read in the HEX file + // + // !! Note, that things are a little strange for us, because the PIC is + // a 12-bit instruction, addresses are 16-bit, and the hex format is + // 8-bit oriented!! + // + nMemoryCount = 0; + while (!feof(fpi)) { + // Get one Intel HEX line + fgets (szLine, 80, fpi); + if (strlen(szLine) >= 10) { + // This is the PIC, with its 12-bit "words". We're interested in these + // words and not the bytes. Read 4 hex digits at a time for each + // address. + // + sscanf (&szLine[1], "%2x%4x", &ndata_bytes, &start_address); + if (start_address >= 0 && start_address <= 20000 && ndata_bytes > 0) { + // Suck up data bytes starting at 9th byte. + i = 9; + + // Words.. not bytes.. + ndata_words = ndata_bytes/2; + start_address = start_address/2; + + // Spit out all the data that is supposed to be on this line. + for (address = start_address; address < start_address + ndata_words; address++) { + // Scan out 4 hex digits for a word. This will be one address. + sscanf (&szLine[i], "%04x", &data); + + // Need to swap bytes... + data = ((data >> 8) & 0x00ff) | ((data << 8) & 0xff00); + i += 4; + + // Store in our memory buffer + Memory[nMemoryCount].nAddress = address; + Memory[nMemoryCount].byData = data; + nMemoryCount++; + } + } + } + } + fclose (fpi); + + // Now output the Verilog $readmemh format! + // + for (i = 0; i < nMemoryCount; i++) { + printf ("\n@%03X %03X", Memory[i].nAddress, Memory[i].byData); + } + printf ("\n"); + +} Index: minirisc/trunk =================================================================== --- minirisc/trunk (nonexistent) +++ minirisc/trunk (revision 7)

minirisc/trunk Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: minirisc/web_uploads =================================================================== --- minirisc/web_uploads (nonexistent) +++ minirisc/web_uploads (revision 7)

minirisc/web_uploads Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: minirisc/branches =================================================================== --- minirisc/branches (nonexistent) +++ minirisc/branches (revision 7)

minirisc/branches Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: minirisc/tags/alpha/xilinx_primitives.zip =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: minirisc/tags/alpha/xilinx_primitives.zip =================================================================== --- minirisc/tags/alpha/xilinx_primitives.zip (nonexistent) +++ minirisc/tags/alpha/xilinx_primitives.zip (revision 7)

minirisc/tags/alpha/xilinx_primitives.zip Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: minirisc/tags/alpha/scode/tmr_wdt.asm =================================================================== --- minirisc/tags/alpha/scode/tmr_wdt.asm (nonexistent) +++ minirisc/tags/alpha/scode/tmr_wdt.asm (revision 7) @@ -0,0 +1,155 @@ +;///////////////////////////////////////////////////////////////////// +;//// //// +;//// Mini-RISC-1 //// +;//// Timer / Wachdog //// +;//// Tests Timer / Wachdog //// +;//// //// +;//// Author: Rudolf Usselmann //// +;//// russelmann@hotmail.com //// +;//// //// +;///////////////////////////////////////////////////////////////////// +;//// //// +;//// Copyright (C) 2000 Rudolf Usselmann //// +;//// russelmann@hotmail.com //// +;//// //// +;//// This source file may be used and distributed without //// +;//// restriction provided that this copyright statement is not //// +;//// removed from the file and that any derivative work contains //// +;//// the original copyright notice and the associated disclaimer.//// +;//// //// +;//// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY //// +;//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT //// +;//// LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND //// +;//// FITNESS FOR A PARTICULAR PURPOSE. //// +;//// //// +;///////////////////////////////////////////////////////////////////// + + list p=16c57 + #include p16c5x.inc + +; global Registers +r0 equ 0x8 +r1 equ 0x9 +r2 equ 0xa +r3 equ 0xb +r4 equ 0xc +r5 equ 0xd +r6 equ 0xe +r7 equ 0xf + +; banked Registers +br0 equ 0x10 +br1 equ 0x11 +br2 equ 0x12 +br3 equ 0x13 +br4 equ 0x14 +br5 equ 0x15 +br6 equ 0x16 +br7 equ 0x17 +br8 equ 0x18 +br9 equ 0x19 +br10 equ 0x1a +br11 equ 0x1b +br12 equ 0x1c +br13 equ 0x1d +br14 equ 0x1e +br15 equ 0x1f + + +; PORTB Indicates Test Number +; PORTA Indicates Status: 0 - Running; 1 - done OK; ff - stoped on error + +main ; Main code entry + ; Port IO Test + ; All ports have a Pull up resistor + + ; SETUP all ports + clrw + movwf FSR + movwf PORTA + movwf PORTB + movwf PORTC + tris PORTA + tris PORTB + tris PORTC + + ; --------------------------------------- + ; ---- Test RMW on Register fil ---- + ; --------------------------------------- + + movlw 0x01 ; TEST 1 + movwf PORTB ; Set Test Number + + movlw 0x00 + option + movwf TMR0 + clrwdt + nop + nop + nop + nop + + clrw + movwf r1 + +loop2 ; repeat 256 times + clrw + movwf r0 + + + ; repeat 256 times +loop1 + movfw TMR0 + decfsz r0,F + goto loop1 + + decfsz r1,F + goto loop2 + + + + nop + nop + nop + nop + nop + nop + + clrw + movwf TMR0 + clrwdt + + nop + nop + nop + nop + movlw 0x01 + movwf PORTA + nop + nop + nop + nop +good ; Loop in good on success + goto good + nop + nop + nop + nop + +lerr + movlw 0xff + movwf PORTA + + nop + nop + nop + nop +lerr_loop ; Loop in lerr on failure + goto lerr_loop + nop + nop + nop + nop + + END + Index: minirisc/tags/alpha/scode/rf1.rom =================================================================== --- minirisc/tags/alpha/scode/rf1.rom (nonexistent) +++ minirisc/tags/alpha/scode/rf1.rom (revision 7) @@ -0,0 +1,584 @@ + +@000 040 +@001 024 +@002 025 +@003 026 +@004 027 +@005 005 +@006 006 +@007 007 +@008 5A3 +@009 C81 +@00A 028 +@00B C82 +@00C 029 +@00D C83 +@00E 02A +@00F C84 +@010 02B +@011 C85 +@012 02C +@013 C86 +@014 02D +@015 C87 +@016 02E +@017 C88 +@018 02F +@019 C90 +@01A 030 +@01B C91 +@01C 031 +@01D C92 +@01E 032 +@01F C93 +@020 033 +@021 C94 +@022 034 +@023 C95 +@024 035 +@025 C96 +@026 036 +@027 C97 +@028 037 +@029 C98 +@02A 038 +@02B C99 +@02C 039 +@02D C9A +@02E 03A +@02F C9B +@030 03B +@031 C9C +@032 03C +@033 C9D +@034 03D +@035 C9E +@036 03E +@037 C9F +@038 03F +@039 5A4 +@03A CA0 +@03B 030 +@03C CA1 +@03D 031 +@03E CA2 +@03F 032 +@040 CA3 +@041 033 +@042 CA4 +@043 034 +@044 CA5 +@045 035 +@046 CA6 +@047 036 +@048 CA7 +@049 037 +@04A CA8 +@04B 038 +@04C CA9 +@04D 039 +@04E CAA +@04F 03A +@050 CAB +@051 03B +@052 CAC +@053 03C +@054 CAD +@055 03D +@056 CAE +@057 03E +@058 CAF +@059 03F +@05A 4A4 +@05B 5C4 +@05C CB0 +@05D 030 +@05E CB1 +@05F 031 +@060 CB2 +@061 032 +@062 CB3 +@063 033 +@064 CB4 +@065 034 +@066 CB5 +@067 035 +@068 CB6 +@069 036 +@06A CB7 +@06B 037 +@06C CB8 +@06D 038 +@06E CB9 +@06F 039 +@070 CBA +@071 03A +@072 CBB +@073 03B +@074 CBC +@075 03C +@076 CBD +@077 03D +@078 CBE +@079 03E +@07A CBF +@07B 03F +@07C 5A4 +@07D 5C4 +@07E CC0 +@07F 030 +@080 CC1 +@081 031 +@082 CC2 +@083 032 +@084 CC3 +@085 033 +@086 CC4 +@087 034 +@088 CC5 +@089 035 +@08A CC6 +@08B 036 +@08C CC7 +@08D 037 +@08E CC8 +@08F 038 +@090 CC9 +@091 039 +@092 CCA +@093 03A +@094 CCB +@095 03B +@096 CCC +@097 03C +@098 CCD +@099 03D +@09A CCE +@09B 03E +@09C CCF +@09D 03F +@09E C01 +@09F 026 +@0A0 040 +@0A1 024 +@0A2 C81 +@0A3 088 +@0A4 743 +@0A5 A3C +@0A6 C82 +@0A7 089 +@0A8 743 +@0A9 A3C +@0AA C83 +@0AB 08A +@0AC 743 +@0AD A3C +@0AE C84 +@0AF 08B +@0B0 743 +@0B1 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C85 +@116 08C +@117 743 +@118 A3C +@119 C86 +@11A 08D +@11B 743 +@11C A3C +@11D C87 +@11E 08E +@11F 743 +@120 A3C +@121 C88 +@122 08F +@123 743 +@124 A3C +@125 CA0 +@126 090 +@127 743 +@128 A3C +@129 CA1 +@12A 091 +@12B 743 +@12C A3C +@12D CA2 +@12E 092 +@12F 743 +@130 A3C +@131 CA3 +@132 093 +@133 743 +@134 A3C +@135 CA4 +@136 094 +@137 743 +@138 A3C +@139 CA5 +@13A 095 +@13B 743 +@13C A3C +@13D CA6 +@13E 096 +@13F 743 +@140 A3C +@141 CA7 +@142 097 +@143 743 +@144 A3C +@145 CA8 +@146 098 +@147 743 +@148 A3C +@149 CA9 +@14A 099 +@14B 743 +@14C A3C +@14D CAA +@14E 09A +@14F 743 +@150 A3C +@151 CAB +@152 09B +@153 743 +@154 A3C +@155 CAC +@156 09C +@157 743 +@158 A3C +@159 CAD +@15A 09D +@15B 743 +@15C A3C +@15D CAE +@15E 09E +@15F 743 +@160 A3C +@161 CAF +@162 09F +@163 743 +@164 A3C +@165 C03 +@166 026 +@167 4A4 +@168 5C4 +@169 C81 +@16A 088 +@16B 743 +@16C A3C +@16D C82 +@16E 089 +@16F 743 +@170 A3C +@171 C83 +@172 08A +@173 743 +@174 A3C +@175 C84 +@176 08B +@177 743 +@178 A3C +@179 C85 +@17A 08C +@17B 743 +@17C A3C +@17D C86 +@17E 08D +@17F 743 +@180 A3C +@181 C87 +@182 08E +@183 743 +@184 A3C +@185 C88 +@186 08F +@187 743 +@188 A3C +@189 CB0 +@18A 090 +@18B 743 +@18C A3C +@18D CB1 +@18E 091 +@18F 743 +@190 A3C +@191 CB2 +@192 092 +@193 743 +@194 A3C +@195 CB3 +@196 093 +@197 743 +@198 A3C +@199 CB4 +@19A 094 +@19B 743 +@19C A3C +@19D CB5 +@19E 095 +@19F 743 +@1A0 A3C +@1A1 CB6 +@1A2 096 +@1A3 743 +@1A4 A3C +@1A5 CB7 +@1A6 097 +@1A7 743 +@1A8 A3C +@1A9 CB8 +@1AA 098 +@1AB 743 +@1AC A3C +@1AD CB9 +@1AE 099 +@1AF 743 +@1B0 A3C +@1B1 CBA +@1B2 09A +@1B3 743 +@1B4 A3C +@1B5 CBB +@1B6 09B +@1B7 743 +@1B8 A3C +@1B9 CBC +@1BA 09C +@1BB 743 +@1BC A3C +@1BD CBD +@1BE 09D +@1BF 743 +@1C0 A3C +@1C1 CBE +@1C2 09E +@1C3 743 +@1C4 A3C +@1C5 CBF +@1C6 09F +@1C7 743 +@1C8 A3C +@1C9 C04 +@1CA 026 +@1CB 5A4 +@1CC 5C4 +@1CD C81 +@1CE 088 +@1CF 743 +@1D0 A3C +@1D1 C82 +@1D2 089 +@1D3 743 +@1D4 A3C +@1D5 C83 +@1D6 08A +@1D7 743 +@1D8 A3C +@1D9 C84 +@1DA 08B +@1DB 743 +@1DC A3C +@1DD C85 +@1DE 08C +@1DF 743 +@1E0 A3C +@1E1 C86 +@1E2 08D +@1E3 743 +@1E4 A3C +@1E5 C87 +@1E6 08E +@1E7 743 +@1E8 A3C +@1E9 C88 +@1EA 08F +@1EB 743 +@1EC A3C +@1ED CC0 +@1EE 090 +@1EF 743 +@1F0 A3C +@1F1 CC1 +@1F2 091 +@1F3 743 +@1F4 A3C +@1F5 CC2 +@1F6 092 +@1F7 743 +@1F8 A3C +@1F9 CC3 +@1FA 093 +@1FB 743 +@1FC A3C +@1FD CC4 +@1FE 094 +@1FF 743 +@200 A3C +@201 CC5 +@202 095 +@203 743 +@204 A3C +@205 CC6 +@206 096 +@207 743 +@208 A3C +@209 CC7 +@20A 097 +@20B 743 +@20C A3C +@20D CC8 +@20E 098 +@20F 743 +@210 A3C +@211 CC9 +@212 099 +@213 743 +@214 A3C +@215 CCA +@216 09A +@217 743 +@218 A3C +@219 CCB +@21A 09B +@21B 743 +@21C A3C +@21D CCC +@21E 09C +@21F 743 +@220 A3C +@221 CCD +@222 09D +@223 743 +@224 A3C +@225 CCE +@226 09E +@227 743 +@228 A3C +@229 CCF +@22A 09F +@22B 743 +@22C A3C +@22D 000 +@22E 000 +@22F 000 +@230 000 +@231 C01 +@232 025 +@233 000 +@234 000 +@235 000 +@236 000 +@237 A37 +@238 000 +@239 000 +@23A 000 +@23B 000 +@23C CFF +@23D 025 +@23E 000 +@23F 000 +@240 000 +@241 000 +@242 A42 +@243 000 +@244 000 +@245 000 +@246 000 Index: minirisc/tags/alpha/scode/sanity1.rom =================================================================== --- minirisc/tags/alpha/scode/sanity1.rom (nonexistent) +++ minirisc/tags/alpha/scode/sanity1.rom (revision 7) @@ -0,0 +1,181 @@ + +@000 040 +@001 025 +@002 026 +@003 027 +@004 FFF +@005 005 +@006 006 +@007 007 +@008 705 +@009 AAF +@00A 725 +@00B AAF +@00C 745 +@00D AAF +@00E 765 +@00F AAF +@010 785 +@011 AAF +@012 7A5 +@013 AAF +@014 7C5 +@015 AAF +@016 7E5 +@017 AAF +@018 706 +@019 AAF +@01A 726 +@01B AAF +@01C 746 +@01D AAF +@01E 766 +@01F AAF +@020 786 +@021 AAF +@022 7A6 +@023 AAF +@024 7C6 +@025 AAF +@026 7E6 +@027 AAF +@028 707 +@029 AAF +@02A 727 +@02B AAF +@02C 747 +@02D AAF +@02E 767 +@02F AAF +@030 787 +@031 AAF +@032 7A7 +@033 AAF +@034 7C5 +@035 AAF +@036 7E7 +@037 AAF +@038 040 +@039 005 +@03A 006 +@03B 007 +@03C 040 +@03D FAA +@03E 025 +@03F 026 +@040 027 +@041 605 +@042 AAF +@043 725 +@044 AAF +@045 645 +@046 AAF +@047 765 +@048 AAF +@049 685 +@04A AAF +@04B 7A5 +@04C AAF +@04D 6C5 +@04E AAF +@04F 7E5 +@050 AAF +@051 606 +@052 AAF +@053 726 +@054 AAF +@055 646 +@056 AAF +@057 766 +@058 AAF +@059 686 +@05A AAF +@05B 7A6 +@05C AAF +@05D 6C6 +@05E AAF +@05F 7E6 +@060 AAF +@061 607 +@062 AAF +@063 727 +@064 AAF +@065 647 +@066 AAF +@067 767 +@068 AAF +@069 687 +@06A AAF +@06B 7A7 +@06C AAF +@06D 6C7 +@06E AAF +@06F 7E7 +@070 AAF +@071 040 +@072 F55 +@073 025 +@074 026 +@075 027 +@076 705 +@077 AAF +@078 625 +@079 AAF +@07A 745 +@07B AAF +@07C 665 +@07D AAF +@07E 785 +@07F AAF +@080 6A5 +@081 AAF +@082 7C5 +@083 AAF +@084 6E5 +@085 AAF +@086 706 +@087 AAF +@088 626 +@089 AAF +@08A 746 +@08B AAF +@08C 666 +@08D AAF +@08E 786 +@08F AAF +@090 6A6 +@091 AAF +@092 7C6 +@093 AAF +@094 6E6 +@095 AAF +@096 707 +@097 AAF +@098 627 +@099 AAF +@09A 747 +@09B AAF +@09C 667 +@09D AAF +@09E 787 +@09F AAF +@0A0 6A7 +@0A1 AAF +@0A2 7C7 +@0A3 AAF +@0A4 6E7 +@0A5 AAF +@0A6 000 +@0A7 000 +@0A8 000 +@0A9 000 +@0AA AAA +@0AB 000 +@0AC 000 +@0AD 000 +@0AE 000 +@0AF AAF +@0B0 000 +@0B1 000 +@0B2 000 +@0B3 000 Index: minirisc/tags/alpha/scode/rf2.rom =================================================================== --- minirisc/tags/alpha/scode/rf2.rom (nonexistent) +++ minirisc/tags/alpha/scode/rf2.rom (revision 7) @@ -0,0 +1,720 @@ + +@000 040 +@001 024 +@002 025 +@003 026 +@004 027 +@005 005 +@006 006 +@007 007 +@008 5A3 +@009 C81 +@00A 028 +@00B C82 +@00C 029 +@00D C83 +@00E 02A +@00F C84 +@010 02B +@011 C85 +@012 02C +@013 C86 +@014 02D +@015 C87 +@016 02E +@017 C88 +@018 02F +@019 C90 +@01A 030 +@01B C91 +@01C 031 +@01D C92 +@01E 032 +@01F C93 +@020 033 +@021 C94 +@022 034 +@023 C95 +@024 035 +@025 C96 +@026 036 +@027 C97 +@028 037 +@029 C98 +@02A 038 +@02B C99 +@02C 039 +@02D C9A +@02E 03A +@02F C9B +@030 03B +@031 C9C +@032 03C +@033 C9D +@034 03D +@035 C9E +@036 03E +@037 C9F +@038 03F +@039 5A4 +@03A CA0 +@03B 030 +@03C CA1 +@03D 031 +@03E CA2 +@03F 032 +@040 CA3 +@041 033 +@042 CA4 +@043 034 +@044 CA5 +@045 035 +@046 CA6 +@047 036 +@048 CA7 +@049 037 +@04A CA8 +@04B 038 +@04C CA9 +@04D 039 +@04E CAA +@04F 03A +@050 CAB +@051 03B +@052 CAC +@053 03C +@054 CAD +@055 03D +@056 CAE +@057 03E +@058 CAF +@059 03F +@05A 4A4 +@05B 5C4 +@05C CB0 +@05D 030 +@05E CB1 +@05F 031 +@060 CB2 +@061 032 +@062 CB3 +@063 033 +@064 CB4 +@065 034 +@066 CB5 +@067 035 +@068 CB6 +@069 036 +@06A CB7 +@06B 037 +@06C CB8 +@06D 038 +@06E CB9 +@06F 039 +@070 CBA +@071 03A +@072 CBB +@073 03B +@074 CBC +@075 03C +@076 CBD +@077 03D +@078 CBE +@079 03E +@07A CBF +@07B 03F +@07C 5A4 +@07D 5C4 +@07E CC0 +@07F 030 +@080 CC1 +@081 031 +@082 CC2 +@083 032 +@084 CC3 +@085 033 +@086 CC4 +@087 034 +@088 CC5 +@089 035 +@08A CC6 +@08B 036 +@08C CC7 +@08D 037 +@08E CC8 +@08F 038 +@090 CC9 +@091 039 +@092 CCA +@093 03A +@094 CCB +@095 03B +@096 CCC +@097 03C +@098 CCD +@099 03D +@09A CCE +@09B 03E +@09C CCF +@09D 03F +@09E C08 +@09F 024 +@0A0 260 +@0A1 2A4 +@0A2 260 +@0A3 2A4 +@0A4 260 +@0A5 2A4 +@0A6 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2A4 +@16F 080 +@170 743 +@171 AC4 +@172 C6D +@173 2A4 +@174 080 +@175 743 +@176 AC4 +@177 C6C +@178 2A4 +@179 080 +@17A 743 +@17B AC4 +@17C C6B +@17D 2A4 +@17E 080 +@17F 743 +@180 AC4 +@181 C6A +@182 2A4 +@183 080 +@184 743 +@185 AC4 +@186 C69 +@187 2A4 +@188 080 +@189 743 +@18A AC4 +@18B C68 +@18C 2A4 +@18D 080 +@18E 743 +@18F AC4 +@190 C67 +@191 2A4 +@192 080 +@193 743 +@194 AC4 +@195 C66 +@196 2A4 +@197 080 +@198 743 +@199 AC4 +@19A C65 +@19B 2A4 +@19C 080 +@19D 743 +@19E AC4 +@19F C64 +@1A0 2A4 +@1A1 080 +@1A2 743 +@1A3 AC4 +@1A4 C63 +@1A5 2A4 +@1A6 080 +@1A7 743 +@1A8 AC4 +@1A9 C62 +@1AA 2A4 +@1AB 080 +@1AC 743 +@1AD AC4 +@1AE C61 +@1AF 2A4 +@1B0 080 +@1B1 743 +@1B2 AC4 +@1B3 C60 +@1B4 2A4 +@1B5 080 +@1B6 743 +@1B7 AC4 +@1B8 C02 +@1B9 026 +@1BA C10 +@1BB 024 +@1BC 5A4 +@1BD C5F +@1BE 080 +@1BF 743 +@1C0 AC4 +@1C1 C5E +@1C2 2A4 +@1C3 080 +@1C4 743 +@1C5 AC4 +@1C6 C5D +@1C7 2A4 +@1C8 080 +@1C9 743 +@1CA AC4 +@1CB C5C +@1CC 2A4 +@1CD 080 +@1CE 743 +@1CF AC4 +@1D0 C5B +@1D1 2A4 +@1D2 080 +@1D3 743 +@1D4 AC4 +@1D5 C5A +@1D6 2A4 +@1D7 080 +@1D8 743 +@1D9 AC4 +@1DA C59 +@1DB 2A4 +@1DC 080 +@1DD 743 +@1DE AC4 +@1DF C58 +@1E0 2A4 +@1E1 080 +@1E2 743 +@1E3 AC4 +@1E4 C57 +@1E5 2A4 +@1E6 080 +@1E7 743 +@1E8 AC4 +@1E9 C56 +@1EA 2A4 +@1EB 080 +@1EC 743 +@1ED AC4 +@1EE C55 +@1EF 2A4 +@1F0 080 +@1F1 743 +@1F2 AC4 +@1F3 C54 +@1F4 2A4 +@1F5 080 +@1F6 743 +@1F7 AC4 +@1F8 C53 +@1F9 2A4 +@1FA 080 +@1FB 743 +@1FC AC4 +@1FD C52 +@1FE 2A4 +@1FF 080 +@200 743 +@201 AC4 +@202 C51 +@203 2A4 +@204 080 +@205 743 +@206 AC4 +@207 C50 +@208 2A4 +@209 080 +@20A 743 +@20B AC4 +@20C C03 +@20D 026 +@20E C10 +@20F 024 +@210 5C4 +@211 C4F +@212 080 +@213 743 +@214 AC4 +@215 C4E +@216 2A4 +@217 080 +@218 743 +@219 AC4 +@21A C4D +@21B 2A4 +@21C 080 +@21D 743 +@21E AC4 +@21F C4C +@220 2A4 +@221 080 +@222 743 +@223 AC4 +@224 C4B +@225 2A4 +@226 080 +@227 743 +@228 AC4 +@229 C4A +@22A 2A4 +@22B 080 +@22C 743 +@22D AC4 +@22E C49 +@22F 2A4 +@230 080 +@231 743 +@232 AC4 +@233 C48 +@234 2A4 +@235 080 +@236 743 +@237 AC4 +@238 C47 +@239 2A4 +@23A 080 +@23B 743 +@23C AC4 +@23D C46 +@23E 2A4 +@23F 080 +@240 743 +@241 AC4 +@242 C45 +@243 2A4 +@244 080 +@245 743 +@246 AC4 +@247 C44 +@248 2A4 +@249 080 +@24A 743 +@24B AC4 +@24C C43 +@24D 2A4 +@24E 080 +@24F 743 +@250 AC4 +@251 C42 +@252 2A4 +@253 080 +@254 743 +@255 AC4 +@256 C41 +@257 2A4 +@258 080 +@259 743 +@25A AC4 +@25B C40 +@25C 2A4 +@25D 080 +@25E 743 +@25F AC4 +@260 C04 +@261 026 +@262 C10 +@263 024 +@264 5A4 +@265 5C4 +@266 C3F +@267 080 +@268 743 +@269 AC4 +@26A C3E +@26B 2A4 +@26C 080 +@26D 743 +@26E AC4 +@26F C3D +@270 2A4 +@271 080 +@272 743 +@273 AC4 +@274 C3C +@275 2A4 +@276 080 +@277 743 +@278 AC4 +@279 C3B +@27A 2A4 +@27B 080 +@27C 743 +@27D AC4 +@27E C3A +@27F 2A4 +@280 080 +@281 743 +@282 AC4 +@283 C39 +@284 2A4 +@285 080 +@286 743 +@287 AC4 +@288 C38 +@289 2A4 +@28A 080 +@28B 743 +@28C AC4 +@28D C37 +@28E 2A4 +@28F 080 +@290 743 +@291 AC4 +@292 C36 +@293 2A4 +@294 080 +@295 743 +@296 AC4 +@297 C35 +@298 2A4 +@299 080 +@29A 743 +@29B AC4 +@29C C34 +@29D 2A4 +@29E 080 +@29F 743 +@2A0 AC4 +@2A1 C33 +@2A2 2A4 +@2A3 080 +@2A4 743 +@2A5 AC4 +@2A6 C32 +@2A7 2A4 +@2A8 080 +@2A9 743 +@2AA AC4 +@2AB C31 +@2AC 2A4 +@2AD 080 +@2AE 743 +@2AF AC4 +@2B0 C30 +@2B1 2A4 +@2B2 080 +@2B3 743 +@2B4 AC4 +@2B5 000 +@2B6 000 +@2B7 000 +@2B8 000 +@2B9 C01 +@2BA 025 +@2BB 000 +@2BC 000 +@2BD 000 +@2BE 000 +@2BF ABF +@2C0 000 +@2C1 000 +@2C2 000 +@2C3 000 +@2C4 CFF +@2C5 025 +@2C6 000 +@2C7 000 +@2C8 000 +@2C9 000 +@2CA ACA +@2CB 000 +@2CC 000 +@2CD 000 +@2CE 000 Index: minirisc/tags/alpha/scode/sanity2.rom =================================================================== --- minirisc/tags/alpha/scode/sanity2.rom (nonexistent) +++ minirisc/tags/alpha/scode/sanity2.rom (revision 7) @@ -0,0 +1,282 @@ + +@000 040 +@001 024 +@002 025 +@003 026 +@004 027 +@005 005 +@006 006 +@007 007 +@008 C0B +@009 028 +@00A 202 +@00B 088 +@00C 743 +@00D B23 +@00E C01 +@00F 026 +@010 C13 +@011 02B +@012 202 +@013 08B +@014 743 +@015 B23 +@016 C02 +@017 026 +@018 C1D +@019 022 +@01A B23 +@01B B23 +@01C B23 +@01D A21 +@01E B23 +@01F B23 +@020 B23 +@021 C03 +@022 026 +@023 C28 +@024 022 +@025 B23 +@026 B23 +@027 B23 +@028 A2C +@029 B23 +@02A B23 +@02B B23 +@02C C04 +@02D 026 +@02E C35 +@02F 028 +@030 C32 +@031 088 +@032 1E2 +@033 B23 +@034 B23 +@035 B23 +@036 A3A +@037 B23 +@038 B23 +@039 B23 +@03A C05 +@03B 026 +@03C C43 +@03D 038 +@03E C40 +@03F 098 +@040 1E2 +@041 B23 +@042 B23 +@043 B23 +@044 A48 +@045 B23 +@046 B23 +@047 B23 +@048 C06 +@049 026 +@04A A60 +@060 522 +@061 B23 +@062 B23 +@063 A68 +@064 B23 +@065 B23 +@066 B23 +@067 B23 +@068 C07 +@069 026 +@06A 542 +@06B B23 +@06C B23 +@06D B23 +@06E B23 +@06F A72 +@070 B23 +@071 B23 +@072 C08 +@073 026 +@074 A7C +@075 B23 +@076 B23 +@077 B23 +@078 B23 +@079 A7D +@07A B23 +@07B B23 +@07C 442 +@07D C09 +@07E 026 +@07F A8A +@080 000 +@081 000 +@082 000 +@083 000 +@084 CFF +@085 025 +@086 000 +@087 000 +@088 000 +@089 000 +@08A C0A +@08B 026 +@08C 9A5 +@08D 028 +@08E C55 +@08F 088 +@090 743 +@091 B23 +@092 9A7 +@093 028 +@094 CAA +@095 088 +@096 743 +@097 B23 +@098 9AA +@099 028 +@09A CC3 +@09B 088 +@09C 743 +@09D B23 +@09E 9AE +@09F 028 +@0A0 C3C +@0A1 088 +@0A2 743 +@0A3 B23 +@0A4 AC5 +@0A5 855 +@0A6 B23 +@0A7 000 +@0A8 8AA +@0A9 B23 +@0AA 000 +@0AB 000 +@0AC 8C3 +@0AD B23 +@0AE 000 +@0AF 000 +@0B0 000 +@0B1 83C +@0B2 B23 +@0B3 1E2 +@0B4 8FF +@0B5 8FE +@0B6 8FD +@0B7 8FC +@0B8 8FB +@0B9 8FA +@0BA 8F9 +@0BB 8F8 +@0BC 8F7 +@0BD 8F6 +@0BE 8F5 +@0BF B23 +@0C0 B23 +@0C1 B23 +@0C2 B23 +@0C3 B23 +@0C4 B23 +@0C5 C0B +@0C6 026 +@0C7 C00 +@0C8 028 +@0C9 9B3 +@0CA 268 +@0CB 0A8 +@0CC 743 +@0CD B23 +@0CE C01 +@0CF 028 +@0D0 9B3 +@0D1 268 +@0D2 0A8 +@0D3 743 +@0D4 B23 +@0D5 C02 +@0D6 028 +@0D7 9B3 +@0D8 268 +@0D9 0A8 +@0DA 743 +@0DB B23 +@0DC C03 +@0DD 028 +@0DE 9B3 +@0DF 268 +@0E0 0A8 +@0E1 743 +@0E2 B23 +@0E3 C04 +@0E4 028 +@0E5 9B3 +@0E6 268 +@0E7 0A8 +@0E8 743 +@0E9 B23 +@0EA C05 +@0EB 028 +@0EC 9B3 +@0ED 268 +@0EE 0A8 +@0EF 743 +@0F0 B23 +@0F1 C06 +@0F2 028 +@0F3 9B3 +@0F4 268 +@0F5 0A8 +@0F6 743 +@0F7 B23 +@0F8 C07 +@0F9 028 +@0FA 9B3 +@0FB 268 +@0FC 0A8 +@0FD 743 +@0FE B23 +@0FF C08 +@100 028 +@101 9B3 +@102 268 +@103 0A8 +@104 743 +@105 B23 +@106 C09 +@107 028 +@108 9B3 +@109 268 +@10A 0A8 +@10B 743 +@10C B23 +@10D C0A +@10E 028 +@10F 9B3 +@110 268 +@111 0A8 +@112 743 +@113 B23 +@114 000 +@115 000 +@116 000 +@117 000 +@118 C01 +@119 025 +@11A 000 +@11B 000 +@11C 000 +@11D 000 +@11E B1E +@11F 000 +@120 000 +@121 000 +@122 000 +@123 CFF +@124 025 +@125 000 +@126 000 +@127 000 +@128 000 +@129 B29 +@12A 000 +@12B 000 +@12C 000 +@12D 000 Index: minirisc/tags/alpha/scode/rf3.rom =================================================================== --- minirisc/tags/alpha/scode/rf3.rom (nonexistent) +++ minirisc/tags/alpha/scode/rf3.rom (revision 7) @@ -0,0 +1,219 @@ + +@000 040 +@001 024 +@002 025 +@003 026 +@004 027 +@005 005 +@006 006 +@007 007 +@008 C01 +@009 026 +@00A CFC +@00B 028 +@00C 2A8 +@00D 2A8 +@00E 2A8 +@00F 2A8 +@010 743 +@011 ACF +@012 CFC +@013 038 +@014 2B8 +@015 2B8 +@016 2B8 +@017 2B8 +@018 743 +@019 ACF +@01A C02 +@01B 026 +@01C C09 +@01D 024 +@01E CFC +@01F 020 +@020 2A0 +@021 2A0 +@022 2A0 +@023 2A0 +@024 743 +@025 ACF +@026 C19 +@027 024 +@028 CFC +@029 020 +@02A 2A0 +@02B 2A0 +@02C 2A0 +@02D 2A0 +@02E 743 +@02F ACF +@030 C03 +@031 026 +@032 C04 +@033 028 +@034 0E8 +@035 0E8 +@036 0E8 +@037 0E8 +@038 743 +@039 ACF +@03A C04 +@03B 030 +@03C 0F0 +@03D 0F0 +@03E 0F0 +@03F 0F0 +@040 743 +@041 ACF +@042 C04 +@043 026 +@044 C09 +@045 024 +@046 C04 +@047 020 +@048 0E0 +@049 0E0 +@04A 0E0 +@04B 0E0 +@04C 743 +@04D ACF +@04E C19 +@04F 024 +@050 C04 +@051 020 +@052 0E0 +@053 0E0 +@054 0E0 +@055 0E0 +@056 743 +@057 ACF +@058 C05 +@059 026 +@05A CFC +@05B 02C +@05C 3EC +@05D 3EC +@05E 3EC +@05F 3EC +@060 ACF +@061 CFC +@062 038 +@063 3F8 +@064 3F8 +@065 3F8 +@066 3F8 +@067 ACF +@068 C06 +@069 026 +@06A C09 +@06B 024 +@06C CFC +@06D 020 +@06E 3E0 +@06F 3E0 +@070 3E0 +@071 3E0 +@072 ACF +@073 C19 +@074 024 +@075 CFC +@076 020 +@077 3E0 +@078 3E0 +@079 3E0 +@07A 3E0 +@07B ACF +@07C C07 +@07D 026 +@07E C04 +@07F 028 +@080 2E8 +@081 2E8 +@082 2E8 +@083 2E8 +@084 ACF +@085 C04 +@086 030 +@087 2F0 +@088 2F0 +@089 2F0 +@08A 2F0 +@08B ACF +@08C C08 +@08D 026 +@08E C09 +@08F 024 +@090 C04 +@091 020 +@092 2E0 +@093 2E0 +@094 2E0 +@095 2E0 +@096 ACF +@097 C19 +@098 024 +@099 C04 +@09A 020 +@09B 2E0 +@09C 2E0 +@09D 2E0 +@09E 2E0 +@09F ACF +@0A0 C09 +@0A1 026 +@0A2 CFC +@0A3 024 +@0A4 2A4 +@0A5 2A4 +@0A6 2A4 +@0A7 2A4 +@0A8 743 +@0A9 ACF +@0AA C04 +@0AB 024 +@0AC C7F +@0AD 0E4 +@0AE 0E4 +@0AF 0E4 +@0B0 0E4 +@0B1 164 +@0B2 743 +@0B3 ACF +@0B4 C0A +@0B5 026 +@0B6 CFC +@0B7 023 +@0B8 C18 +@0B9 2A3 +@0BA 2A3 +@0BB 2A3 +@0BC 2A3 +@0BD 083 +@0BE 743 +@0BF ACF +@0C0 000 +@0C1 000 +@0C2 000 +@0C3 000 +@0C4 C01 +@0C5 025 +@0C6 000 +@0C7 000 +@0C8 000 +@0C9 000 +@0CA ACA +@0CB 000 +@0CC 000 +@0CD 000 +@0CE 000 +@0CF CFF +@0D0 025 +@0D1 000 +@0D2 000 +@0D3 000 +@0D4 000 +@0D5 AD5 +@0D6 000 +@0D7 000 +@0D8 000 +@0D9 000 Index: minirisc/tags/alpha/scode/rf1.asm =================================================================== --- minirisc/tags/alpha/scode/rf1.asm (nonexistent) +++ minirisc/tags/alpha/scode/rf1.asm (revision 7) @@ -0,0 +1,694 @@ +;///////////////////////////////////////////////////////////////////// +;//// //// +;//// Mini-RISC-1 //// +;//// Register File Test 1 //// +;//// Tests Register File //// +;//// //// +;//// Author: Rudolf Usselmann //// +;//// russelmann@hotmail.com //// +;//// //// +;///////////////////////////////////////////////////////////////////// +;//// //// +;//// Copyright (C) 2000 Rudolf Usselmann //// +;//// russelmann@hotmail.com //// +;//// //// +;//// This source file may be used and distributed without //// +;//// restriction provided that this copyright statement is not //// +;//// removed from the file and that any derivative work contains //// +;//// the original copyright notice and the associated disclaimer.//// +;//// //// +;//// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY //// +;//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT //// +;//// LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND //// +;//// FITNESS FOR A PARTICULAR PURPOSE. //// +;//// //// +;///////////////////////////////////////////////////////////////////// + + list p=16c57 + #include p16c5x.inc + +; global Registers +r0 equ 0x8 +r1 equ 0x9 +r2 equ 0xa +r3 equ 0xb +r4 equ 0xc +r5 equ 0xd +r6 equ 0xe +r7 equ 0xf + +; banked Registers +br0 equ 0x10 +br1 equ 0x11 +br2 equ 0x12 +br3 equ 0x13 +br4 equ 0x14 +br5 equ 0x15 +br6 equ 0x16 +br7 equ 0x17 +br8 equ 0x18 +br9 equ 0x19 +br10 equ 0x1a +br11 equ 0x1b +br12 equ 0x1c +br13 equ 0x1d +br14 equ 0x1e +br15 equ 0x1f + + +; PORTB Indicates Test Number +; PORTA Indicates Status: 0 - Running; 1 - done OK; ff - stoped on error + +main ; Main code entry + ; Port IO Test + ; All ports have a Pull up resistor + + ; SETUP all ports + clrw + movwf FSR + movwf PORTA + movwf PORTB + movwf PORTC + tris PORTA + tris PORTB + tris PORTC + + bsf STATUS,5 + + ; --------------------------------------- + ; ---- Test the entire register file ---- + ; --------------------------------------- + + movlw 0x81 + movwf r0 + movlw 0x82 + movwf r1 + movlw 0x83 + movwf r2 + movlw 0x84 + movwf r3 + movlw 0x85 + movwf r4 + movlw 0x86 + movwf r5 + movlw 0x87 + movwf r6 + movlw 0x88 + movwf r7 + + + movlw 0x90 + movwf br0 + movlw 0x91 + movwf br1 + movlw 0x92 + movwf br2 + movlw 0x93 + movwf br3 + movlw 0x94 + movwf br4 + movlw 0x95 + movwf br5 + movlw 0x96 + movwf br6 + movlw 0x97 + movwf br7 + movlw 0x98 + movwf br8 + movlw 0x99 + movwf br9 + movlw 0x9a + movwf br10 + movlw 0x9b + movwf br11 + movlw 0x9c + movwf br12 + movlw 0x9d + movwf br13 + movlw 0x9e + movwf br14 + movlw 0x9f + movwf br15 + + bsf FSR,5 ; Select Register Bank 01 + + movlw 0xa0 + movwf br0 + movlw 0xa1 + movwf br1 + movlw 0xa2 + movwf br2 + movlw 0xa3 + movwf br3 + movlw 0xa4 + movwf br4 + movlw 0xa5 + movwf br5 + movlw 0xa6 + movwf br6 + movlw 0xa7 + movwf br7 + movlw 0xa8 + movwf br8 + movlw 0xa9 + movwf br9 + movlw 0xaa + movwf br10 + movlw 0xab + movwf br11 + movlw 0xac + movwf br12 + movlw 0xad + movwf br13 + movlw 0xae + movwf br14 + movlw 0xaf + movwf br15 + + bcf FSR,5 ; Select Register Bank 10 + bsf FSR,6 + + movlw 0xb0 + movwf br0 + movlw 0xb1 + movwf br1 + movlw 0xb2 + movwf br2 + movlw 0xb3 + movwf br3 + movlw 0xb4 + movwf br4 + movlw 0xb5 + movwf br5 + movlw 0xb6 + movwf br6 + movlw 0xb7 + movwf br7 + movlw 0xb8 + movwf br8 + movlw 0xb9 + movwf br9 + movlw 0xba + movwf br10 + movlw 0xbb + movwf br11 + movlw 0xbc + movwf br12 + movlw 0xbd + movwf br13 + movlw 0xbe + movwf br14 + movlw 0xbf + movwf br15 + + bsf FSR,5 ; Select Register Bank 11 + bsf FSR,6 + + movlw 0xc0 + movwf br0 + movlw 0xc1 + movwf br1 + movlw 0xc2 + movwf br2 + movlw 0xc3 + movwf br3 + movlw 0xc4 + movwf br4 + movlw 0xc5 + movwf br5 + movlw 0xc6 + movwf br6 + movlw 0xc7 + movwf br7 + movlw 0xc8 + movwf br8 + movlw 0xc9 + movwf br9 + movlw 0xca + movwf br10 + movlw 0xcb + movwf br11 + movlw 0xcc + movwf br12 + movlw 0xcd + movwf br13 + movlw 0xce + movwf br14 + movlw 0xcf + movwf br15 + + ; Register File TEST 1 + movlw 0x01 + movwf PORTB ; Set Test Number + + clrw + movwf FSR + + movlw 0x81 + subwf r0,W + btfss STATUS,Z + goto lerr + movlw 0x82 + subwf r1,W + btfss STATUS,Z + goto lerr + movlw 0x83 + subwf r2,W + btfss STATUS,Z + goto lerr + movlw 0x84 + subwf r3,W + btfss STATUS,Z + goto lerr + movlw 0x85 + subwf r4,W + btfss STATUS,Z + goto lerr + movlw 0x86 + subwf r5,W + btfss STATUS,Z + goto lerr + movlw 0x87 + subwf r6,W + btfss STATUS,Z + goto lerr + movlw 0x88 + subwf r7,W + btfss STATUS,Z + goto lerr + + movlw 0x90 + subwf br0,W + btfss STATUS,Z + goto lerr + movlw 0x91 + subwf br1,W + btfss STATUS,Z + goto lerr + movlw 0x92 + subwf br2,W + btfss STATUS,Z + goto lerr + movlw 0x93 + subwf br3,W + btfss STATUS,Z + goto lerr + movlw 0x94 + subwf br4,W + btfss STATUS,Z + goto lerr + movlw 0x95 + subwf br5,W + btfss STATUS,Z + goto lerr + movlw 0x96 + subwf br6,W + btfss STATUS,Z + goto lerr + movlw 0x97 + subwf br7,W + btfss STATUS,Z + goto lerr + movlw 0x98 + subwf br8,W + btfss STATUS,Z + goto lerr + movlw 0x99 + subwf br9,W + btfss STATUS,Z + goto lerr + movlw 0x9a + subwf br10,W + btfss STATUS,Z + goto lerr + movlw 0x9b + subwf br11,W + btfss STATUS,Z + goto lerr + movlw 0x9c + subwf br12,W + btfss STATUS,Z + goto lerr + movlw 0x9d + subwf br13,W + btfss STATUS,Z + goto lerr + movlw 0x9e + subwf br14,W + btfss STATUS,Z + goto lerr + movlw 0x9f + subwf br15,W + btfss STATUS,Z + goto lerr + + ; Register File TEST 2 + movlw 0x02 + movwf PORTB ; Set Test Number + + bsf FSR,5 ; Select Register Bank 01 + + movlw 0x81 + subwf r0,W + btfss STATUS,Z + goto lerr + movlw 0x82 + subwf r1,W + btfss STATUS,Z + goto lerr + movlw 0x83 + subwf r2,W + btfss STATUS,Z + goto lerr + movlw 0x84 + subwf r3,W + btfss STATUS,Z + goto lerr + movlw 0x85 + subwf r4,W + btfss STATUS,Z + goto lerr + movlw 0x86 + subwf r5,W + btfss STATUS,Z + goto lerr + movlw 0x87 + subwf r6,W + btfss STATUS,Z + goto lerr + movlw 0x88 + subwf r7,W + btfss STATUS,Z + goto lerr + + movlw 0xa0 + subwf br0,W + btfss STATUS,Z + goto lerr + movlw 0xa1 + subwf br1,W + btfss STATUS,Z + goto lerr + movlw 0xa2 + subwf br2,W + btfss STATUS,Z + goto lerr + movlw 0xa3 + subwf br3,W + btfss STATUS,Z + goto lerr + movlw 0xa4 + subwf br4,W + btfss STATUS,Z + goto lerr + movlw 0xa5 + subwf br5,W + btfss STATUS,Z + goto lerr + movlw 0xa6 + subwf br6,W + btfss STATUS,Z + goto lerr + movlw 0xa7 + subwf br7,W + btfss STATUS,Z + goto lerr + movlw 0xa8 + subwf br8,W + btfss STATUS,Z + goto lerr + movlw 0xa9 + subwf br9,W + btfss STATUS,Z + goto lerr + movlw 0xaa + subwf br10,W + btfss STATUS,Z + goto lerr + movlw 0xab + subwf br11,W + btfss STATUS,Z + goto lerr + movlw 0xac + subwf br12,W + btfss STATUS,Z + goto lerr + movlw 0xad + subwf br13,W + btfss STATUS,Z + goto lerr + movlw 0xae + subwf br14,W + btfss STATUS,Z + goto lerr + movlw 0xaf + subwf br15,W + btfss STATUS,Z + goto lerr + + ; Register File TEST 3 + movlw 0x03 + movwf PORTB ; Set Test Number + + bcf FSR,5 ; Select Register Bank 10 + bsf FSR,6 + + movlw 0x81 + subwf r0,W + btfss STATUS,Z + goto lerr + movlw 0x82 + subwf r1,W + btfss STATUS,Z + goto lerr + movlw 0x83 + subwf r2,W + btfss STATUS,Z + goto lerr + movlw 0x84 + subwf r3,W + btfss STATUS,Z + goto lerr + movlw 0x85 + subwf r4,W + btfss STATUS,Z + goto lerr + movlw 0x86 + subwf r5,W + btfss STATUS,Z + goto lerr + movlw 0x87 + subwf r6,W + btfss STATUS,Z + goto lerr + movlw 0x88 + subwf r7,W + btfss STATUS,Z + goto lerr + + movlw 0xb0 + subwf br0,W + btfss STATUS,Z + goto lerr + movlw 0xb1 + subwf br1,W + btfss STATUS,Z + goto lerr + movlw 0xb2 + subwf br2,W + btfss STATUS,Z + goto lerr + movlw 0xb3 + subwf br3,W + btfss STATUS,Z + goto lerr + movlw 0xb4 + subwf br4,W + btfss STATUS,Z + goto lerr + movlw 0xb5 + subwf br5,W + btfss STATUS,Z + goto lerr + movlw 0xb6 + subwf br6,W + btfss STATUS,Z + goto lerr + movlw 0xb7 + subwf br7,W + btfss STATUS,Z + goto lerr + movlw 0xb8 + subwf br8,W + btfss STATUS,Z + goto lerr + movlw 0xb9 + subwf br9,W + btfss STATUS,Z + goto lerr + movlw 0xba + subwf br10,W + btfss STATUS,Z + goto lerr + movlw 0xbb + subwf br11,W + btfss STATUS,Z + goto lerr + movlw 0xbc + subwf br12,W + btfss STATUS,Z + goto lerr + movlw 0xbd + subwf br13,W + btfss STATUS,Z + goto lerr + movlw 0xbe + subwf br14,W + btfss STATUS,Z + goto lerr + movlw 0xbf + subwf br15,W + btfss STATUS,Z + goto lerr + + + ; Register File TEST 4 + movlw 0x04 + movwf PORTB ; Set Test Number + + bsf FSR,5 ; Select Register Bank 11 + bsf FSR,6 + + movlw 0x81 + subwf r0,W + btfss STATUS,Z + goto lerr + movlw 0x82 + subwf r1,W + btfss STATUS,Z + goto lerr + movlw 0x83 + subwf r2,W + btfss STATUS,Z + goto lerr + movlw 0x84 + subwf r3,W + btfss STATUS,Z + goto lerr + movlw 0x85 + subwf r4,W + btfss STATUS,Z + goto lerr + movlw 0x86 + subwf r5,W + btfss STATUS,Z + goto lerr + movlw 0x87 + subwf r6,W + btfss STATUS,Z + goto lerr + movlw 0x88 + subwf r7,W + btfss STATUS,Z + goto lerr + + movlw 0xc0 + subwf br0,W + btfss STATUS,Z + goto lerr + movlw 0xc1 + subwf br1,W + btfss STATUS,Z + goto lerr + movlw 0xc2 + subwf br2,W + btfss STATUS,Z + goto lerr + movlw 0xc3 + subwf br3,W + btfss STATUS,Z + goto lerr + movlw 0xc4 + subwf br4,W + btfss STATUS,Z + goto lerr + movlw 0xc5 + subwf br5,W + btfss STATUS,Z + goto lerr + movlw 0xc6 + subwf br6,W + btfss STATUS,Z + goto lerr + movlw 0xc7 + subwf br7,W + btfss STATUS,Z + goto lerr + movlw 0xc8 + subwf br8,W + btfss STATUS,Z + goto lerr + movlw 0xc9 + subwf br9,W + btfss STATUS,Z + goto lerr + movlw 0xca + subwf br10,W + btfss STATUS,Z + goto lerr + movlw 0xcb + subwf br11,W + btfss STATUS,Z + goto lerr + movlw 0xcc + subwf br12,W + btfss STATUS,Z + goto lerr + movlw 0xcd + subwf br13,W + btfss STATUS,Z + goto lerr + movlw 0xce + subwf br14,W + btfss STATUS,Z + goto lerr + movlw 0xcf + subwf br15,W + btfss STATUS,Z + goto lerr + + + nop + nop + nop + nop + movlw 0x01 + movwf PORTA + nop + nop + nop + nop +good ; Loop in good on success + goto good + nop + nop + nop + nop + +lerr + movlw 0xff + movwf PORTA + + nop + nop + nop + nop +lerr_loop ; Loop in lerr on failure + goto lerr_loop + nop + nop + nop + nop + + END + Index: minirisc/tags/alpha/scode/sanity1.asm =================================================================== --- minirisc/tags/alpha/scode/sanity1.asm (nonexistent) +++ minirisc/tags/alpha/scode/sanity1.asm (revision 7) @@ -0,0 +1,250 @@ +;///////////////////////////////////////////////////////////////////// +;//// //// +;//// Mini-RISC-1 //// +;//// Compliance Test 1 //// +;//// Tests Ports //// +;//// //// +;//// Author: Rudolf Usselmann //// +;//// russelmann@hotmail.com //// +;//// //// +;///////////////////////////////////////////////////////////////////// +;//// //// +;//// Copyright (C) 2000 Rudolf Usselmann //// +;//// russelmann@hotmail.com //// +;//// //// +;//// This source file may be used and distributed without //// +;//// restriction provided that this copyright statement is not //// +;//// removed from the file and that any derivative work contains //// +;//// the original copyright notice and the associated disclaimer.//// +;//// //// +;//// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY //// +;//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT //// +;//// LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND //// +;//// FITNESS FOR A PARTICULAR PURPOSE. //// +;//// //// +;///////////////////////////////////////////////////////////////////// + + list p=16c57 + #include p16c5x.inc + + +main ; Main code entry + ; Port IO Test + ; All ports have a Pull up resistor + + ; Tristate all ports + clrw + movwf PORTA + movwf PORTB + movwf PORTC + xorlw 0xff + tris PORTA + tris PORTB + tris PORTC + + ; Now check that porta is 0xff + btfss PORTA,0 + goto lerr + btfss PORTA,1 + goto lerr + btfss PORTA,2 + goto lerr + btfss PORTA,3 + goto lerr + btfss PORTA,4 + goto lerr + btfss PORTA,5 + goto lerr + btfss PORTA,6 + goto lerr + btfss PORTA,7 + goto lerr + + + ; Now check that portb is 0xff + btfss PORTB,0 + goto lerr + btfss PORTB,1 + goto lerr + btfss PORTB,2 + goto lerr + btfss PORTB,3 + goto lerr + btfss PORTB,4 + goto lerr + btfss PORTB,5 + goto lerr + btfss PORTB,6 + goto lerr + btfss PORTB,7 + goto lerr + + ; Now check that portc is 0xff + btfss PORTC,0 + goto lerr + btfss PORTC,1 + goto lerr + btfss PORTC,2 + goto lerr + btfss PORTC,3 + goto lerr + btfss PORTC,4 + goto lerr + btfss PORTC,5 + goto lerr + btfss PORTA,6 + goto lerr + btfss PORTC,7 + goto lerr + + + + ; Enable all ports + clrw + tris PORTA + tris PORTB + tris PORTC + + ; Drive them all 0xaa + clrw + xorlw 0xaa + movwf PORTA + movwf PORTB + movwf PORTC + + ; Now check that porta is 0xaa + btfsc PORTA,0 + goto lerr + btfss PORTA,1 + goto lerr + btfsc PORTA,2 + goto lerr + btfss PORTA,3 + goto lerr + btfsc PORTA,4 + goto lerr + btfss PORTA,5 + goto lerr + btfsc PORTA,6 + goto lerr + btfss PORTA,7 + goto lerr + + ; Now check that portb is 0xaa + btfsc PORTB,0 + goto lerr + btfss PORTB,1 + goto lerr + btfsc PORTB,2 + goto lerr + btfss PORTB,3 + goto lerr + btfsc PORTB,4 + goto lerr + btfss PORTB,5 + goto lerr + btfsc PORTB,6 + goto lerr + btfss PORTB,7 + goto lerr + + ; Now check that portc is 0xaa + btfsc PORTC,0 + goto lerr + btfss PORTC,1 + goto lerr + btfsc PORTC,2 + goto lerr + btfss PORTC,3 + goto lerr + btfsc PORTC,4 + goto lerr + btfss PORTC,5 + goto lerr + btfsc PORTC,6 + goto lerr + btfss PORTC,7 + goto lerr + + ; Drive them all 0x55 + clrw + xorlw 0x55 + movwf PORTA + movwf PORTB + movwf PORTC + + ; Now check that porta is 0x55 + btfss PORTA,0 + goto lerr + btfsc PORTA,1 + goto lerr + btfss PORTA,2 + goto lerr + btfsc PORTA,3 + goto lerr + btfss PORTA,4 + goto lerr + btfsc PORTA,5 + goto lerr + btfss PORTA,6 + goto lerr + btfsc PORTA,7 + goto lerr + + ; Now check that portb is 0x55 + btfss PORTB,0 + goto lerr + btfsc PORTB,1 + goto lerr + btfss PORTB,2 + goto lerr + btfsc PORTB,3 + goto lerr + btfss PORTB,4 + goto lerr + btfsc PORTB,5 + goto lerr + btfss PORTB,6 + goto lerr + btfsc PORTB,7 + goto lerr + + ; Now check that portc is 0x55 + btfss PORTC,0 + goto lerr + btfsc PORTC,1 + goto lerr + btfss PORTC,2 + goto lerr + btfsc PORTC,3 + goto lerr + btfss PORTC,4 + goto lerr + btfsc PORTC,5 + goto lerr + btfss PORTC,6 + goto lerr + btfsc PORTC,7 + goto lerr + + nop + nop + nop + nop + +good ; Loop in good on success + goto good + nop + nop + nop + nop + +lerr ; Loop in lerr on failure + goto lerr + nop + nop + nop + nop + + END + Index: minirisc/tags/alpha/scode/rf2.asm =================================================================== --- minirisc/tags/alpha/scode/rf2.asm (nonexistent) +++ minirisc/tags/alpha/scode/rf2.asm (revision 7) @@ -0,0 +1,827 @@ +;///////////////////////////////////////////////////////////////////// +;//// //// +;//// Mini-RISC-1 //// +;//// Register File Test 2 //// +;//// Tests Register File //// +;//// //// +;//// Author: Rudolf Usselmann //// +;//// russelmann@hotmail.com //// +;//// //// +;///////////////////////////////////////////////////////////////////// +;//// //// +;//// Copyright (C) 2000 Rudolf Usselmann //// +;//// russelmann@hotmail.com //// +;//// //// +;//// This source file may be used and distributed without //// +;//// restriction provided that this copyright statement is not //// +;//// removed from the file and that any derivative work contains //// +;//// the original copyright notice and the associated disclaimer.//// +;//// //// +;//// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY //// +;//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT //// +;//// LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND //// +;//// FITNESS FOR A PARTICULAR PURPOSE. //// +;//// //// +;///////////////////////////////////////////////////////////////////// + + list p=16c57 + #include p16c5x.inc + +; global Registers +r0 equ 0x8 +r1 equ 0x9 +r2 equ 0xa +r3 equ 0xb +r4 equ 0xc +r5 equ 0xd +r6 equ 0xe +r7 equ 0xf + +; banked Registers +br0 equ 0x10 +br1 equ 0x11 +br2 equ 0x12 +br3 equ 0x13 +br4 equ 0x14 +br5 equ 0x15 +br6 equ 0x16 +br7 equ 0x17 +br8 equ 0x18 +br9 equ 0x19 +br10 equ 0x1a +br11 equ 0x1b +br12 equ 0x1c +br13 equ 0x1d +br14 equ 0x1e +br15 equ 0x1f + + +; PORTB Indicates Test Number +; PORTA Indicates Status: 0 - Running; 1 - done OK; ff - stoped on error + +main ; Main code entry + ; Port IO Test + ; All ports have a Pull up resistor + + ; SETUP all ports + clrw + movwf FSR + movwf PORTA + movwf PORTB + movwf PORTC + tris PORTA + tris PORTB + tris PORTC + + bsf STATUS,5 + + ; --------------------------------------- + ; ---- Test the entire register file ---- + ; --------------------------------------- + + movlw 0x81 + movwf r0 + movlw 0x82 + movwf r1 + movlw 0x83 + movwf r2 + movlw 0x84 + movwf r3 + movlw 0x85 + movwf r4 + movlw 0x86 + movwf r5 + movlw 0x87 + movwf r6 + movlw 0x88 + movwf r7 + + + movlw 0x90 + movwf br0 + movlw 0x91 + movwf br1 + movlw 0x92 + movwf br2 + movlw 0x93 + movwf br3 + movlw 0x94 + movwf br4 + movlw 0x95 + movwf br5 + movlw 0x96 + movwf br6 + movlw 0x97 + movwf br7 + movlw 0x98 + movwf br8 + movlw 0x99 + movwf br9 + movlw 0x9a + movwf br10 + movlw 0x9b + movwf br11 + movlw 0x9c + movwf br12 + movlw 0x9d + movwf br13 + movlw 0x9e + movwf br14 + movlw 0x9f + movwf br15 + + bsf FSR,5 ; Select Register Bank 01 + + movlw 0xa0 + movwf br0 + movlw 0xa1 + movwf br1 + movlw 0xa2 + movwf br2 + movlw 0xa3 + movwf br3 + movlw 0xa4 + movwf br4 + movlw 0xa5 + movwf br5 + movlw 0xa6 + movwf br6 + movlw 0xa7 + movwf br7 + movlw 0xa8 + movwf br8 + movlw 0xa9 + movwf br9 + movlw 0xaa + movwf br10 + movlw 0xab + movwf br11 + movlw 0xac + movwf br12 + movlw 0xad + movwf br13 + movlw 0xae + movwf br14 + movlw 0xaf + movwf br15 + + bcf FSR,5 ; Select Register Bank 10 + bsf FSR,6 + + movlw 0xb0 + movwf br0 + movlw 0xb1 + movwf br1 + movlw 0xb2 + movwf br2 + movlw 0xb3 + movwf br3 + movlw 0xb4 + movwf br4 + movlw 0xb5 + movwf br5 + movlw 0xb6 + movwf br6 + movlw 0xb7 + movwf br7 + movlw 0xb8 + movwf br8 + movlw 0xb9 + movwf br9 + movlw 0xba + movwf br10 + movlw 0xbb + movwf br11 + movlw 0xbc + movwf br12 + movlw 0xbd + movwf br13 + movlw 0xbe + movwf br14 + movlw 0xbf + movwf br15 + + bsf FSR,5 ; Select Register Bank 11 + bsf FSR,6 + + movlw 0xc0 + movwf br0 + movlw 0xc1 + movwf br1 + movlw 0xc2 + movwf br2 + movlw 0xc3 + movwf br3 + movlw 0xc4 + movwf br4 + movlw 0xc5 + movwf br5 + movlw 0xc6 + movwf br6 + movlw 0xc7 + movwf br7 + movlw 0xc8 + movwf br8 + movlw 0xc9 + movwf br9 + movlw 0xca + movwf br10 + movlw 0xcb + movwf br11 + movlw 0xcc + movwf br12 + movlw 0xcd + movwf br13 + movlw 0xce + movwf br14 + movlw 0xcf + movwf br15 + + movlw r0 + movwf FSR + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + + + movlw br0 + movwf FSR + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + + movlw br0 + movwf FSR + bsf FSR,5 + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + + movlw br0 + movwf FSR + bsf FSR,6 + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + + movlw br0 + movwf FSR + bsf FSR,5 + bsf FSR,6 + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + comf INDF,F + incf FSR,F + + ; Register File TEST 1 + movlw 0x01 + movwf PORTB ; Set Test Number + + movlw r0 + movwf FSR + movlw 0x7e + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x7d + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x7c + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x7b + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x7a + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x79 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x78 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x77 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + + movlw br0 + movwf FSR + movlw 0x6f + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x6e + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x6d + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x6c + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x6b + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x6a + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x69 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x68 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x67 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x66 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x65 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x64 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x63 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x62 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x61 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x60 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + + ; Register File TEST 2 + movlw 0x02 + movwf PORTB ; Set Test Number + + movlw br0 + movwf FSR + bsf FSR,5 + movlw 0x5f + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x5e + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x5d + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x5c + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x5b + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x5a + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x59 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x58 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x57 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x56 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x55 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x54 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x53 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x52 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x51 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x50 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + + ; Register File TEST 3 + movlw 0x03 + movwf PORTB ; Set Test Number + + movlw br0 + movwf FSR + bsf FSR,6 + movlw 0x4f + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x4e + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x4d + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x4c + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x4b + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x4a + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x49 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x48 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x47 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x46 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x45 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x44 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x43 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x42 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x41 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x40 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + + ; Register File TEST 4 + movlw 0x04 + movwf PORTB ; Set Test Number + + movlw br0 + movwf FSR + bsf FSR,5 + bsf FSR,6 + movlw 0x3f + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x3e + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x3d + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x3c + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x3b + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x3a + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x39 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x38 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x37 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x36 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x35 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x34 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x33 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x32 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x31 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + movlw 0x30 + incf FSR,F + subwf INDF,W + btfss STATUS,Z + goto lerr + + nop + nop + nop + nop + movlw 0x01 + movwf PORTA + nop + nop + nop + nop +good ; Loop in good on success + goto good + nop + nop + nop + nop + +lerr + movlw 0xff + movwf PORTA + + nop + nop + nop + nop +lerr_loop ; Loop in lerr on failure + goto lerr_loop + nop + nop + nop + nop + + END + Index: minirisc/tags/alpha/scode/sanity2.asm =================================================================== --- minirisc/tags/alpha/scode/sanity2.asm (nonexistent) +++ minirisc/tags/alpha/scode/sanity2.asm (revision 7) @@ -0,0 +1,454 @@ +;///////////////////////////////////////////////////////////////////// +;//// //// +;//// Mini-RISC-1 //// +;//// Compliance Test 2 //// +;//// Tests PLC register Rd/Wr //// +;//// //// +;//// Author: Rudolf Usselmann //// +;//// russelmann@hotmail.com //// +;//// //// +;///////////////////////////////////////////////////////////////////// +;//// //// +;//// Copyright (C) 2000 Rudolf Usselmann //// +;//// russelmann@hotmail.com //// +;//// //// +;//// This source file may be used and distributed without //// +;//// restriction provided that this copyright statement is not //// +;//// removed from the file and that any derivative work contains //// +;//// the original copyright notice and the associated disclaimer.//// +;//// //// +;//// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY //// +;//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT //// +;//// LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND //// +;//// FITNESS FOR A PARTICULAR PURPOSE. //// +;//// //// +;///////////////////////////////////////////////////////////////////// + + list p=16c57 + #include p16c5x.inc + +; global Registers +r0 equ 0x8 +r1 equ 0x9 +r2 equ 0xa +r3 equ 0xb +r4 equ 0xc +r5 equ 0xd +r6 equ 0xe +r7 equ 0xf + +; banked Registers +br0 equ 0x10 +br1 equ 0x11 +br2 equ 0x12 +br3 equ 0x13 +br4 equ 0x14 +br5 equ 0x15 +br6 equ 0x16 +br7 equ 0x17 +br8 equ 0x18 +br9 equ 0x19 +br10 equ 0x1a +br11 equ 0x1b +br12 equ 0x1c +br13 equ 0x1d +br14 equ 0x1e +br15 equ 0x1f + + +; PORTB Indicates Test Number +; PORTA Indicates Status: 0 - Running; 1 - done OK; ff - stoped on error + +main ; Main code entry + ; Port IO Test + ; All ports have a Pull up resistor + + ; SETUP all ports + clrw + movwf FSR + movwf PORTA + movwf PORTB + movwf PORTC + tris PORTA + tris PORTB + tris PORTC + + ; ------------------------------- + ; ---- Test the PLC register ---- + ; ------------------------------- + + ; PLC read test 1 TEST 0 + + movlw pclrd1 + movwf r0 + movf PCL,W +pclrd1 subwf r0,W + btfss STATUS,Z + goto lerr + + ; PLC read test 2 TEST 1 + movlw 0x01 + movwf PORTB ; Set Test Number + + movlw pclrd2 + movwf r3 + movf PCL,W +pclrd2 subwf r3,W + btfss STATUS,Z + goto lerr + + ; PLC write test 2 TEST 2 + movlw 0x02 + movwf PORTB ; Set Test Number + + movlw pclwr1 + movwf PCL + + goto lerr + goto lerr + goto lerr +pclwr1 goto pcl1 + goto lerr + goto lerr + goto lerr + +pcl1 + ; PLC write test 2 TEST 3 + movlw 0x03 + movwf PORTB ; Set Test Number + + movlw pclwr2 + movwf PCL + + goto lerr + goto lerr + goto lerr +pclwr2 goto pcl2 + goto lerr + goto lerr + goto lerr + +pcl2 ; Test other instructions that modify PC + ; This are ADDWF PC, BSF PC,X and BCF PC,X + ; (movwf pc already tested above) + + ; PLC write test 3 TEST 4 + ; test addwf PC + movlw 0x04 + movwf PORTB ; Set Test Number + + movlw pcl3b + movwf r0 + movlw pcl3a + subwf r0,W +pcl3a addwf PCL,1 + + goto lerr + goto lerr +pcl3b goto lerr + goto pcl3c + goto lerr + goto lerr + goto lerr +pcl3c + + ; PLC write test 4 TEST 5 + ; test addwf PC + movlw 0x05 + movwf PORTB ; Set Test Number + + movlw pcl4b + movwf br8 + movlw pcl4a + subwf br8,W +pcl4a addwf PCL,1 + + goto lerr + goto lerr +pcl4b goto lerr + goto pcl4c + goto lerr + goto lerr + goto lerr +pcl4c + + ; PLC write test 5 TEST 6 + ; test bsf PC,N + movlw 0x06 + movwf PORTB ; Set Test N + +; allign memory + goto pcl50 + +pcl50 org 0x60 + + bsf PCL,1 ; 60 + goto lerr ; 61 + goto lerr ; 62 + goto pcl5a ; 63 + goto lerr ; 64 + goto lerr ; 65 + goto lerr ; 66 + goto lerr ; 67 + +pcl5a + + ; PLC write test 6 TEST 7 + ; test bsf PC,N + movlw 0x07 + movwf PORTB ; Set Test N + + bsf PCL,2 ; 6A + goto lerr ; 6B + goto lerr ; 6C + goto lerr ; 6D + goto lerr ; 6E + goto pcl6a ; 6F + goto lerr ; 70 + goto lerr ; 71 + +pcl6a + + ; PLC write test 7 TEST 8 + ; test bcf PC,N + movlw 0x08 + movwf PORTB ; Set Test N + + goto pcl7a ; 74 + goto lerr ; 75 + goto lerr ; 76 + goto lerr ; 77 + goto lerr ; 78 + goto pcl7b ; 79 + goto lerr ; 7a + goto lerr ; 7b + +pcl7a + bcf PCL,2 ; 7c + +pcl7b + + + ; Make sure goto works + movlw 0x09 ; TEST 9 + movwf PORTB ; Set Test Number + + + goto gt1 + nop + nop + nop + nop + movlw 0xff + movwf PORTA + nop + nop + nop + nop +gt1 + + ; Make sure call works + movlw 0x0a ; TEST 10 + movwf PORTB ; Set Test Number + + call cal1 + movwf r0 + movlw 0x55 + subwf r0,w + btfss STATUS,Z + goto lerr + + call cal2 + movwf r0 + movlw 0xaa + subwf r0,w + btfss STATUS,Z + goto lerr + + call cal3 + movwf r0 + movlw 0xc3 + subwf r0,w + btfss STATUS,Z + goto lerr + + call cal4 + movwf r0 + movlw 0x3c + subwf r0,w + btfss STATUS,Z + goto lerr + + goto next1 + +cal1 + retlw 0x55 + goto lerr + +cal2 + nop + retlw 0xaa + goto lerr + +cal3 + nop + nop + retlw 0xc3 + goto lerr + +cal4 + nop + nop + nop + retlw 0x3c + goto lerr + +table1 + addwf PCL,F + retlw 0xff + retlw 0xfe + retlw 0xfd + retlw 0xfc + retlw 0xfb + retlw 0xfa + retlw 0xf9 + retlw 0xf8 + retlw 0xf7 + retlw 0xf6 + retlw 0xf5 + goto lerr + goto lerr + goto lerr + goto lerr + goto lerr + goto lerr + +next1 + + + ; Make sure call works (2) + movlw 0x0b ; TEST 11 + movwf PORTB ; Set Test Number + + movlw 0x0 + movwf r0 + call table1 + comf r0,F + subwf r0,F + btfss STATUS,Z + goto lerr + + movlw 0x1 + movwf r0 + call table1 + comf r0,F + subwf r0,F + btfss STATUS,Z + goto lerr + + movlw 0x2 + movwf r0 + call table1 + comf r0,F + subwf r0,F + btfss STATUS,Z + goto lerr + + movlw 0x3 + movwf r0 + call table1 + comf r0,F + subwf r0,F + btfss STATUS,Z + goto lerr + + movlw 0x4 + movwf r0 + call table1 + comf r0,F + subwf r0,F + btfss STATUS,Z + goto lerr + + movlw 0x5 + movwf r0 + call table1 + comf r0,F + subwf r0,F + btfss STATUS,Z + goto lerr + + movlw 0x6 + movwf r0 + call table1 + comf r0,F + subwf r0,F + btfss STATUS,Z + goto lerr + + movlw 0x7 + movwf r0 + call table1 + comf r0,F + subwf r0,F + btfss STATUS,Z + goto lerr + + movlw 0x8 + movwf r0 + call table1 + comf r0,F + subwf r0,F + btfss STATUS,Z + goto lerr + + movlw 0x9 + movwf r0 + call table1 + comf r0,F + subwf r0,F + btfss STATUS,Z + goto lerr + + movlw 0xa + movwf r0 + call table1 + comf r0,F + subwf r0,F + btfss STATUS,Z + goto lerr + + nop + nop + nop + nop + movlw 0x01 + movwf PORTA + nop + nop + nop + nop +good ; Loop in good on success + goto good + nop + nop + nop + nop + +lerr + movlw 0xff + movwf PORTA + + nop + nop + nop + nop +lerr_loop ; Loop in lerr on failure + goto lerr_loop + nop + nop + nop + nop + + END + Index: minirisc/tags/alpha/scode/rf3.asm =================================================================== --- minirisc/tags/alpha/scode/rf3.asm (nonexistent) +++ minirisc/tags/alpha/scode/rf3.asm (revision 7) @@ -0,0 +1,338 @@ +;///////////////////////////////////////////////////////////////////// +;//// //// +;//// Mini-RISC-1 //// +;//// Register File Test 3 //// +;//// Tests Register File //// +;//// //// +;//// Author: Rudolf Usselmann //// +;//// russelmann@hotmail.com //// +;//// //// +;///////////////////////////////////////////////////////////////////// +;//// //// +;//// Copyright (C) 2000 Rudolf Usselmann //// +;//// russelmann@hotmail.com //// +;//// //// +;//// This source file may be used and distributed without //// +;//// restriction provided that this copyright statement is not //// +;//// removed from the file and that any derivative work contains //// +;//// the original copyright notice and the associated disclaimer.//// +;//// //// +;//// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY //// +;//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT //// +;//// LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND //// +;//// FITNESS FOR A PARTICULAR PURPOSE. //// +;//// //// +;///////////////////////////////////////////////////////////////////// + + list p=16c57 + #include p16c5x.inc + +; global Registers +r0 equ 0x8 +r1 equ 0x9 +r2 equ 0xa +r3 equ 0xb +r4 equ 0xc +r5 equ 0xd +r6 equ 0xe +r7 equ 0xf + +; banked Registers +br0 equ 0x10 +br1 equ 0x11 +br2 equ 0x12 +br3 equ 0x13 +br4 equ 0x14 +br5 equ 0x15 +br6 equ 0x16 +br7 equ 0x17 +br8 equ 0x18 +br9 equ 0x19 +br10 equ 0x1a +br11 equ 0x1b +br12 equ 0x1c +br13 equ 0x1d +br14 equ 0x1e +br15 equ 0x1f + + +; PORTB Indicates Test Number +; PORTA Indicates Status: 0 - Running; 1 - done OK; ff - stoped on error + +main ; Main code entry + ; Port IO Test + ; All ports have a Pull up resistor + + ; SETUP all ports + clrw + movwf FSR + movwf PORTA + movwf PORTB + movwf PORTC + tris PORTA + tris PORTB + tris PORTC + + ; --------------------------------------- + ; ---- Test RMW on Register fil ---- + ; --------------------------------------- + + movlw 0x01 ; TEST 1 + movwf PORTB ; Set Test Number + + movlw 0xfc + movwf r0 + incf r0,F + incf r0,F + incf r0,F + incf r0,F + btfss STATUS,Z + goto lerr + + movlw 0xfc + movwf br8 + incf br8,F + incf br8,F + incf br8,F + incf br8,F + btfss STATUS,Z + goto lerr + + movlw 0x02 ; TEST 2 + movwf PORTB ; Set Test Number + + movlw r1 + movwf FSR + movlw 0xfc + movwf INDF + incf INDF,F + incf INDF,F + incf INDF,F + incf INDF,F + btfss STATUS,Z + goto lerr + + movlw br9 + movwf FSR + movlw 0xfc + movwf INDF + incf INDF,F + incf INDF,F + incf INDF,F + incf INDF,F + btfss STATUS,Z + goto lerr + + + + movlw 0x03 ; TEST 3 + movwf PORTB ; Set Test Number + + movlw 0x04 + movwf r0 + decf r0,F + decf r0,F + decf r0,F + decf r0,F + btfss STATUS,Z + goto lerr + + + movlw 0x04 + movwf br0 + decf br0,F + decf br0,F + decf br0,F + decf br0,F + btfss STATUS,Z + goto lerr + + + movlw 0x04 ; TEST 4 + movwf PORTB ; Set Test Number + + movlw r1 + movwf FSR + movlw 0x04 + movwf INDF + decf INDF,F + decf INDF,F + decf INDF,F + decf INDF,F + btfss STATUS,Z + goto lerr + + movlw br9 + movwf FSR + movlw 0x04 + movwf INDF + decf INDF,F + decf INDF,F + decf INDF,F + decf INDF,F + btfss STATUS,Z + goto lerr + + + movlw 0x05 ; TEST 5 + movwf PORTB ; Set Test Number + + movlw 0xfc + movwf r4 + incfsz r4,F + incfsz r4,F + incfsz r4,F + incfsz r4,F + goto lerr + + movlw 0xfc + movwf br8 + incfsz br8,F + incfsz br8,F + incfsz br8,F + incfsz br8,F + goto lerr + + + movlw 0x06 ; TEST 6 + movwf PORTB ; Set Test Number + + movlw r1 + movwf FSR + movlw 0xfc + movwf INDF + incfsz INDF,F + incfsz INDF,F + incfsz INDF,F + incfsz INDF,F + goto lerr + + movlw br9 + movwf FSR + movlw 0xfc + movwf INDF + incfsz INDF,F + incfsz INDF,F + incfsz INDF,F + incfsz INDF,F + goto lerr + + movlw 0x07 ; TEST 7 + movwf PORTB ; Set Test Number + + movlw 0x04 + movwf r0 + decfsz r0,F + decfsz r0,F + decfsz r0,F + decfsz r0,F + goto lerr + + + movlw 0x04 + movwf br0 + decfsz br0,F + decfsz br0,F + decfsz br0,F + decfsz br0,F + goto lerr + + + movlw 0x08 ; TEST 8 + movwf PORTB ; Set Test Number + + movlw r1 + movwf FSR + movlw 0x04 + movwf INDF + decfsz INDF,F + decfsz INDF,F + decfsz INDF,F + decfsz INDF,F + goto lerr + + movlw br9 + movwf FSR + movlw 0x04 + movwf INDF + decfsz INDF,F + decfsz INDF,F + decfsz INDF,F + decfsz INDF,F + goto lerr + + + movlw 0x09 ; TEST 9 + movwf PORTB ; Set Test Number + + movlw 0xfc + movwf FSR + incf FSR,F + incf FSR,F + incf FSR,F + incf FSR,F + btfss STATUS,Z + goto lerr + + movlw 0x04 + movwf FSR + movlw 0x7f + decf FSR,F + decf FSR,F + decf FSR,F + decf FSR,F + andwf FSR,F + btfss STATUS,Z + goto lerr + + movlw 0x0a ; TEST 10 + movwf PORTB ; Set Test Number + + movlw 0xfc + movwf STATUS + movlw 0x18 + incf STATUS,F + incf STATUS,F + incf STATUS,F + incf STATUS,F + subwf STATUS,W + btfss STATUS,Z + goto lerr + + + + + nop + nop + nop + nop + movlw 0x01 + movwf PORTA + nop + nop + nop + nop +good ; Loop in good on success + goto good + nop + nop + nop + nop + +lerr + movlw 0xff + movwf PORTA + + nop + nop + nop + nop +lerr_loop ; Loop in lerr on failure + goto lerr_loop + nop + nop + nop + nop + + END + Index: minirisc/tags/alpha/scode/tmr_wdt.rom =================================================================== --- minirisc/tags/alpha/scode/tmr_wdt.rom (nonexistent) +++ minirisc/tags/alpha/scode/tmr_wdt.rom (revision 7) @@ -0,0 +1,63 @@ + +@000 040 +@001 024 +@002 025 +@003 026 +@004 027 +@005 005 +@006 006 +@007 007 +@008 C01 +@009 026 +@00A C00 +@00B 002 +@00C 021 +@00D 004 +@00E 000 +@00F 000 +@010 000 +@011 000 +@012 040 +@013 029 +@014 040 +@015 028 +@016 201 +@017 2E8 +@018 A16 +@019 2E9 +@01A A14 +@01B 000 +@01C 000 +@01D 000 +@01E 000 +@01F 000 +@020 000 +@021 040 +@022 021 +@023 004 +@024 000 +@025 000 +@026 000 +@027 000 +@028 C01 +@029 025 +@02A 000 +@02B 000 +@02C 000 +@02D 000 +@02E A2E +@02F 000 +@030 000 +@031 000 +@032 000 +@033 CFF +@034 025 +@035 000 +@036 000 +@037 000 +@038 000 +@039 A39 +@03A 000 +@03B 000 +@03C 000 +@03D 000 Index: minirisc/tags/alpha/scode/hex2v.c =================================================================== --- minirisc/tags/alpha/scode/hex2v.c (nonexistent) +++ minirisc/tags/alpha/scode/hex2v.c (revision 7) @@ -0,0 +1,125 @@ +/* *********************************************************************** + The Free IP Project + Free-RISC8 -- Verilog 8-bit Microcontroller + (c) 1999, The Free IP Project and Thomas Coonan + + + FREE IP GENERAL PUBLIC LICENSE + TERMS AND CONDITIONS FOR USE, COPYING, DISTRIBUTION, AND MODIFICATION + + 1. You may copy and distribute verbatim copies of this core, as long + as this file, and the other associated files, remain intact and + unmodified. Modifications are outlined below. + 2. You may use this core in any way, be it academic, commercial, or + military. Modified or not. + 3. Distribution of this core must be free of charge. Charging is + allowed only for value added services. Value added services + would include copying fees, modifications, customizations, and + inclusion in other products. + 4. If a modified source code is distributed, the original unmodified + source code must also be included (or a link to the Free IP web + site). In the modified source code there must be clear + identification of the modified version. + 5. Visit the Free IP web site for additional information. + http://www.free-ip.com + +*********************************************************************** */ + +// Intel HEX to Verilog converter. +// +// Usage: +// hex2v +// +// You probably want to simply redirect the output into a file. +// +#include +#include +#include + +// Input and Output file streams. +FILE *fpi; + +// Well.. Let's read stuff in completely before outputting.. Programs +// should be pretty small.. +// +#define MAX_MEMORY_SIZE 2048 +struct { + unsigned int nAddress; + unsigned int byData; +} Memory[MAX_MEMORY_SIZE]; + +char szLine[80]; +unsigned int start_address, address, ndata_bytes, ndata_words; +unsigned int data; +unsigned int nMemoryCount; + +int main (int argc, char *argv[]) +{ + int i; + + if (argc != 2) { + printf ("\nThe Synthetic PIC --- Intel HEX File to Verilog memory file"); + printf ("\nUsage: hex2verilog "); + printf ("\n"); + return 0; + } + + + // Open input HEX file + fpi=fopen(argv[1], "r"); + if (!fpi) { + printf("\nCan't open input file %s.\n", argv[1]); + return 1; + } + + // Read in the HEX file + // + // !! Note, that things are a little strange for us, because the PIC is + // a 12-bit instruction, addresses are 16-bit, and the hex format is + // 8-bit oriented!! + // + nMemoryCount = 0; + while (!feof(fpi)) { + // Get one Intel HEX line + fgets (szLine, 80, fpi); + if (strlen(szLine) >= 10) { + // This is the PIC, with its 12-bit "words". We're interested in these + // words and not the bytes. Read 4 hex digits at a time for each + // address. + // + sscanf (&szLine[1], "%2x%4x", &ndata_bytes, &start_address); + if (start_address >= 0 && start_address <= 20000 && ndata_bytes > 0) { + // Suck up data bytes starting at 9th byte. + i = 9; + + // Words.. not bytes.. + ndata_words = ndata_bytes/2; + start_address = start_address/2; + + // Spit out all the data that is supposed to be on this line. + for (address = start_address; address < start_address + ndata_words; address++) { + // Scan out 4 hex digits for a word. This will be one address. + sscanf (&szLine[i], "%04x", &data); + + // Need to swap bytes... + data = ((data >> 8) & 0x00ff) | ((data << 8) & 0xff00); + i += 4; + + // Store in our memory buffer + Memory[nMemoryCount].nAddress = address; + Memory[nMemoryCount].byData = data; + nMemoryCount++; + } + } + } + } + fclose (fpi); + + // Now output the Verilog $readmemh format! + // + for (i = 0; i < nMemoryCount; i++) { + printf ("\n@%03X %03X", Memory[i].nAddress, Memory[i].byData); + } + printf ("\n"); + +} Index: minirisc/tags/alpha/verilog/testbench/prog_mem.v =================================================================== --- minirisc/tags/alpha/verilog/testbench/prog_mem.v (nonexistent) +++ minirisc/tags/alpha/verilog/testbench/prog_mem.v (revision 7) @@ -0,0 +1,52 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Mini-RISC-1 //// +//// Synchrounous Program Memory //// +//// //// +//// Author: Rudolf Usselmann //// +//// russelmann@hotmail.com //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Rudolf Usselmann //// +//// russelmann@hotmail.com //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT //// +//// LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND //// +//// FITNESS FOR A PARTICULAR PURPOSE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +`timescale 1ns / 10ps + +// For simulation only +// May be off or on chip + +module prog_mem ( clk, address, we, din, dout ); + +input clk; +input [10:0] address; +input we; +input [11:0] din; +output [11:0] dout; + +parameter depth = 2048; + +reg [10:0] addr_r; +reg [11:0] mem[0:depth-1]; + +always @(posedge clk) + addr_r <= address; + +assign dout = mem[addr_r]; + +always @(posedge clk) + if (we) mem[address] <= din; + +endmodule Index: minirisc/tags/alpha/verilog/core/primitives.v =================================================================== --- minirisc/tags/alpha/verilog/core/primitives.v (nonexistent) +++ minirisc/tags/alpha/verilog/core/primitives.v (revision 7) @@ -0,0 +1,203 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Mini-RISC-1 //// +//// Primitives //// +//// //// +//// Author: Rudolf Usselmann //// +//// russelmann@hotmail.com //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Rudolf Usselmann //// +//// russelmann@hotmail.com //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT //// +//// LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND //// +//// FITNESS FOR A PARTICULAR PURPOSE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +`timescale 1ns / 10ps + +// Mux 4:1 8 bits wide +module mux4_8(sel, in0, in1, in2, in3, out); +input [1:0] sel; +input [7:0] in0, in1, in2, in3; +output [7:0] out; + +reg [7:0] out; + +always @(sel or in0 or in1 or in2 or in3) + case(sel) + 0: out = in0; + 1: out = in1; + 2: out = in2; + 3: out = in3; + endcase + +endmodule + +// 8 bit comparator +module cmp8_eq(a,b,eq); +input [7:0] a,b; +output eq; + +assign eq = (a==b); + +endmodule + +// MUX 2:1 7 bits wide +module mux2_7(sel, in0, in1, out); +input sel; +input [6:0] in0, in1; +output [6:0] out; + +assign out = sel ? in1 : in0; + +endmodule + +// Mux 8:1 1 bit wide +module mux8_1( sel, in, out); +input [2:0] sel; +input [7:0] in; +output out; + +assign out = in[sel]; + +endmodule + +// Mux 2:1 8 bits wide +module mux2_8(sel, in0, in1, out); +input sel; +input [7:0] in0, in1; +output [7:0] out; + +assign out = sel ? in1 : in0; + +endmodule + +// Mux 8:1 8 bits wide +module mux8_8(sel, in0, in1, in2, in3, in4, in5, in6, in7, out); +input [2:0] sel; +input [7:0] in0, in1, in2, in3, in4, in5, in6, in7; +output [7:0] out; + +reg [7:0] out; + +always @(sel or in0 or in1 or in2 or in3 or in4 or in5 or in6 or in7) + case(sel) + 3'd0: out = in0; + 3'd1: out = in1; + 3'd2: out = in2; + 3'd3: out = in3; + 3'd4: out = in4; + 3'd5: out = in5; + 3'd6: out = in6; + 3'd7: out = in7; + endcase + +endmodule + +// Mux 2:1 11 bits wide +module mux2_11(sel, in0, in1, out); +input sel; +input [10:0] in0, in1; +output [10:0] out; + +assign out = sel ? in1 : in0; + +endmodule + + +// 8bit Add/Sub with carry/borrow out +module add_sub8_co(sub, opa, opb, out, co); +input sub; +input [7:0] opa, opb; +output [7:0] out; +output co; + +assign {co, out} = sub ? (opa - opb) : (opa + opb); + +endmodule + +// 11 bit incrementer +module inc11(in, out); +input [10:0] in; +output [10:0] out; + +assign out = in + 1; + +endmodule + +// 8 bit incrementer +module inc8(in, out); +input [7:0] in; +output [7:0] out; + +assign out = in + 1; + +endmodule + +// A Basic Synchrounous FIFO (4 entries deep) +module sfifo4x11(clk, push, din, pop, dout); +input clk; +input push; +input [10:0] din; +input pop; +output [10:0] dout; + +reg [10:0] stack1, stack2, stack3, stack4; + +assign dout = stack1; + +always @(posedge clk) + begin + if(push) // PUSH stack + begin + stack4 <= #1 stack3; + stack3 <= #1 stack2; + stack2 <= #1 stack1; + stack1 <= #1 din; + end + if(pop) // POP stack + begin + stack1 <= #1 stack2; + stack2 <= #1 stack3; + stack3 <= #1 stack4; + end + end + +endmodule + + +// Synchrounous SRAM +// 128 bytes by 8 bits +// 1 read port, 1 write port +module ssram_128x8(clk, rd_addr, rd_data, we, wr_addr, wr_data); +input clk; +input [6:0] rd_addr; +output [7:0] rd_data; +input we; +input [6:0] wr_addr; +input [7:0] wr_data; + +reg [7:0] rf_mem[0:128]; // Actual Memory + +reg [7:0] rd_data; + +always @(posedge clk) // Synchrounous Read Logic + rd_data <= #1 rf_mem[rd_addr]; + +always @(posedge clk) // Synchrounous Write Logic + if(we) + rf_mem[wr_addr] <= #1 wr_data; + +endmodule + + Index: minirisc/tags/alpha/verilog/core/test.v =================================================================== --- minirisc/tags/alpha/verilog/core/test.v (nonexistent) +++ minirisc/tags/alpha/verilog/core/test.v (revision 7) @@ -0,0 +1,295 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Mini-RISC-1 //// +//// Primitives for Xilinx Virtex Famaly //// +//// (Generated with CoreGen) //// +//// //// +//// Author: Rudolf Usselmann //// +//// russelmann@hotmail.com //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Rudolf Usselmann //// +//// russelmann@hotmail.com //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT //// +//// LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND //// +//// FITNESS FOR A PARTICULAR PURPOSE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +`timescale 1ns / 10ps + +module test; + +reg clk; +reg reset; +reg tcki; + +// Declare I/O Port connections +wire [7:0] porta; // I/O Port A +wire [7:0] portb; // I/O Port B +wire [7:0] portc; // I/O Port C + +wire [7:0] portain; +wire [7:0] portbin; +wire [7:0] portcin; + +wire [7:0] portaout; +wire [7:0] portbout; +wire [7:0] portcout; + +wire [7:0] trisa; +wire [7:0] trisb; +wire [7:0] trisc; + +// Declare ROM and rom signals +wire [10:0] inst_addr; +wire [11:0] inst_data; + + +always #10 clk = ~clk; +always #20 tcki = ~tcki; + +// Instantiate one CPU to be tested. +mrisc u0( + .clk (clk), + .rst_in (reset), + .inst_addr (inst_addr), + .inst_data (inst_data), + + .portain (portain), + .portbin (portbin), + .portcin (portcin), + + .portaout (portaout), + .portbout (portbout), + .portcout (portcout), + + .trisa (trisa), + .trisb (trisb), + .trisc (trisc), + + .tcki (tcki), + .wdt_en (1'b1) + + ); + +// IO buffers for IO Ports +assign porta = trisa ? 8'bz : portaout; +assign portain = porta; + +assign portb = trisb ? 8'bz : portbout; +assign portbin = portb; + +assign portc = trisc ? 8'bz : portcout; +assign portcin = portc; + +// Pullups for IO Ports +pullup ua0(porta[0]); +pullup ua1(porta[1]); +pullup ua2(porta[2]); +pullup ua3(porta[3]); +pullup ua4(porta[4]); +pullup ua5(porta[5]); +pullup ua6(porta[6]); +pullup ua7(porta[7]); + +pullup ub0(portb[0]); +pullup ub1(portb[1]); +pullup ub2(portb[2]); +pullup ub3(portb[3]); +pullup ub4(portb[4]); +pullup ub5(portb[5]); +pullup ub6(portb[6]); +pullup ub7(portb[7]); + +pullup uc0(portc[0]); +pullup uc1(portc[1]); +pullup uc2(portc[2]); +pullup uc3(portc[3]); +pullup uc4(portc[4]); +pullup uc5(portc[5]); +pullup uc6(portc[6]); +pullup uc7(portc[7]); + + + +// Instantiate the Program RAM. +prog_mem u1 ( + .clk (clk), + .address (inst_addr), + .we (1'b0), // This testbench doesn't allow writing to PRAM + .din (12'b000000000000), // This testbench doesn't allow writing to PRAM + .dout (inst_data) +); + +// This is the only initial block in the test module and this is where +// you select what test you want to do. + +initial + begin + $display ("\n\nMini-RISC. Version 1.0\n\n"); + + //$dumpfile ("mini-risc.vcd"); + //$dumpvars (0, test); + + clk = 0; + tcki = 0; + + sanity1; + + $readmemh ("scode/sanity2.rom", u1.mem); run_code("Sanity 2 "); + + $readmemh ("scode/rf1.rom", u1.mem); run_code("Register File 1 "); + + $readmemh ("scode/rf2.rom", u1.mem); run_code("Register File 2 "); + + $readmemh ("scode/rf3.rom", u1.mem); run_code("Register File 3 "); + + //$readmemh ("scode/tmr_wdt.rom", u1.mem); run_code("Timer / WDT "); + + //$dumpflush; + $finish; + end + + +task sanity1; + +`define GOOD 12'h0aa +`define BAD 12'h0af +`define SANITY1 "scode/sanity1.rom" + + begin + $display ("========== Starting Sanity 1 Test ========== \n"); + reset = 1; + repeat(10) @(posedge clk); + reset = 0; + + //$display ("Loading program memory with %s", `SANITY1); + $readmemh (`SANITY1, u1.mem); + while(inst_addr != `GOOD & inst_addr != `BAD) @(posedge clk); + + if(inst_addr == `GOOD) + begin + $display("Sanity1 test PASSED !!!"); + end + else + if(inst_addr == `BAD) + begin + $display("Sanity1 test FAILED !!!"); + end + else + $display("Sanity1 test status UNKNOWN !!!"); + + + repeat(4) @(posedge clk); + $display("=============================================\n\n\n"); + + end +endtask + +task run_code; +input [16*8-1:0] str; + + + begin + $display ("========== Starting %s Test ========== \n",str); + reset = 1; + repeat(10) @(posedge clk); + reset = 0; + + //$display ("Loading program memory with %s", `SANITY2); + //$readmemh (`SANITY2, u1.mem); + + repeat(10) @(posedge clk); + while(porta == 8'h00) @(posedge clk); + + + if(porta == 8'h01) + begin + $display("Test %s PASSED !!!",str); + end + else + if(porta == 8'hff) + begin + $display("Test %s FAILED in test %d !!!", str, portb); + end + else + $display("Test %s status UNKNOWN (%h test: %d) !!!", str, porta, portb); + + + repeat(4) @(posedge clk); + $display("\n=============================================\n\n\n"); + + end +endtask + +/* +always @(posedge clk) + if(!reset) + begin + if( |u0.w ===1'bx ) $display("%t: Warning :W went unknown",$time); + if( |u0.pc ===1'bx ) $display("%t: Warning :PC went unknown",$time); + if( |u0.status ===1'bx ) $display("%t: Warning :STATUS went unknown",$time); + end +*/ + +reg [8*8-1:0] inst_string; + +always @(inst_data) begin + casex (inst_data) + 12'b0000_0000_0000: inst_string = "NOP "; + 12'b0000_001X_XXXX: inst_string = "MOVWF "; + 12'b0000_0100_0000: inst_string = "CLRW "; + 12'b0000_011X_XXXX: inst_string = "CLRF "; + 12'b0000_10XX_XXXX: inst_string = "SUBWF "; + 12'b0000_11XX_XXXX: inst_string = "DECF "; + 12'b0001_00XX_XXXX: inst_string = "IORWF "; + 12'b0001_01XX_XXXX: inst_string = "ANDWF "; + 12'b0001_10XX_XXXX: inst_string = "XORWF "; + 12'b0001_11XX_XXXX: inst_string = "ADDWF "; + 12'b0010_00XX_XXXX: inst_string = "MOVF "; + 12'b0010_01XX_XXXX: inst_string = "COMF "; + 12'b0010_10XX_XXXX: inst_string = "INCF "; + 12'b0010_11XX_XXXX: inst_string = "DECFSZ "; + 12'b0011_00XX_XXXX: inst_string = "RRF "; + 12'b0011_01XX_XXXX: inst_string = "RLF "; + 12'b0011_10XX_XXXX: inst_string = "SWAPF "; + 12'b0011_11XX_XXXX: inst_string = "INCFSZ "; + + // *** Bit-Oriented File Register Operations + 12'b0100_XXXX_XXXX: inst_string = "BCF "; + 12'b0101_XXXX_XXXX: inst_string = "BSF "; + 12'b0110_XXXX_XXXX: inst_string = "BTFSC "; + 12'b0111_XXXX_XXXX: inst_string = "BTFSS "; + + // *** Literal and Control Operations + 12'b0000_0000_0010: inst_string = "OPTION "; + 12'b0000_0000_0011: inst_string = "SLEEP "; + 12'b0000_0000_0100: inst_string = "CLRWDT "; + 12'b0000_0000_0101: inst_string = "TRIS "; + 12'b0000_0000_0110: inst_string = "TRIS "; + 12'b0000_0000_0111: inst_string = "TRIS "; + 12'b1000_XXXX_XXXX: inst_string = "RETLW "; + 12'b1001_XXXX_XXXX: inst_string = "CALL "; + 12'b101X_XXXX_XXXX: inst_string = "GOTO "; + 12'b1100_XXXX_XXXX: inst_string = "MOVLW "; + 12'b1101_XXXX_XXXX: inst_string = "IORLW "; + 12'b1110_XXXX_XXXX: inst_string = "ANDLW "; + 12'b1111_XXXX_XXXX: inst_string = "XORLW "; + + default: inst_string = "-XXXXXX-"; + endcase + //$display("Executing[%h] %s",inst_addr, inst_string); +end + + +endmodule + Index: minirisc/tags/alpha/verilog/core/alu.v =================================================================== --- minirisc/tags/alpha/verilog/core/alu.v (nonexistent) +++ minirisc/tags/alpha/verilog/core/alu.v (revision 7) @@ -0,0 +1,120 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Mini-RISC-1 //// +//// ALU //// +//// //// +//// Author: Rudolf Usselmann //// +//// russelmann@hotmail.com //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Rudolf Usselmann //// +//// russelmann@hotmail.com //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT //// +//// LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND //// +//// FITNESS FOR A PARTICULAR PURPOSE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +`timescale 1ns / 10ps + +module alu(s1, s2, mask, out, op, c_in, c, dc, z); +input [7:0] s1, s2, mask; +output [7:0] out; +input [3:0] op; +input c_in; +output c, dc, z; + +parameter ALU_ADD = 4'h0, + ALU_SUB = 4'h1, + ALU_INC = 4'h2, + ALU_DEC = 4'h3, + + ALU_AND = 4'h4, + ALU_CLR = 4'h5, + ALU_NOT = 4'h6, + ALU_IOR = 4'h7, + ALU_MOV = 4'h8, + ALU_MOVW = 4'h9, + ALU_RLF = 4'ha, + ALU_RRF = 4'hb, + ALU_SWP = 4'hc, + ALU_XOR = 4'hd, + ALU_BCF = 4'he, + ALU_BSF = 4'hf; + +wire [7:0] out; +wire co, bo; +wire c; +wire z; +wire [5:0] tmp_add; +wire borrow_dc; + +wire [7:0] add_sub_out; +wire add_sub_sel; +wire [7:0] s2_a; +wire [8:0] rlf_out, rrf_out; +wire [7:0] out_next1, out_next2, out_next3; + +/* +reg cout; +reg [7:0] out_t; +always @(op or s1 or s2 or mask or c_in) + begin + cout = 0; + case(op) // synopsys full_case parallel_case + ALU_ADD: {cout, out} = s1 + s2; + ALU_AND: out_t = s1 & s2; + ALU_CLR: out_t = 8'h00; + ALU_NOT: out_t = ~s1; + ALU_DEC: out_t = s1 - 1; + ALU_INC: out_t = s1 + 1; + ALU_IOR: out_t = s1 | s2; + ALU_MOV: out_t = s1; + ALU_MOVW: out_t = s2; + ALU_RLF: {cout, out_t} = {s1[7:0], c_in}; + ALU_RRF: {cout, out_t} = {s1[0], c_in, s1[7:1]}; + ALU_SUB: {cout, out_t} = s1 - s2; + ALU_SWP: out_t = {s1[3:0], s1[7:4]}; + ALU_XOR: out_t = s1 ^ s2; + ALU_BCF: out_t = s1 & ~mask; + ALU_BSF: out_t = s1 | mask; + endcase + end +*/ + +assign rlf_out = {s1[7:0], c_in}; +assign rrf_out = {s1[0], c_in, s1[7:1]}; + +assign add_sub_sel = (op[3:2]==2'b0); + +mux4_8 u2( .sel(op[3:2]), .in0(add_sub_out), .in1(out_next1), .in2(out_next2), .in3(out_next3), .out(out) ); +mux4_8 u3( .sel(op[1:0]), .in0(s1 & s2), .in1(8'h00), .in2(~s1), .in3(s1 | s2), .out(out_next1) ); +mux4_8 u4( .sel(op[1:0]), .in0(s1), .in1(s2), .in2(rlf_out[7:0]), .in3(rrf_out[7:0]), .out(out_next2) ); +mux4_8 u5( .sel(op[1:0]), .in0({s1[3:0], s1[7:4]}), .in1(s1^s2), .in2(s1 & ~mask), .in3(s1 | mask), .out(out_next3) ); + +mux2_8 u0( .sel(op[1]), .in0(s2), .in1(8'h01), .out(s2_a) ); + +add_sub8_co u1( .sub(op[0]), .opa(s1), .opb(s2_a), .out(add_sub_out), .co(co) ); + +// C bit generation +assign c = add_sub_sel ? co : op[0] ? rrf_out[8] : rlf_out[8]; + +// Z Bit generation +assign z = (out==8'h0); + +// DC Bit geberation +// This section is really bad, but not in the critical path, +// so I leave it alone for now .... +assign borrow_dc = s1[3:0] >= s2[3:0]; +assign tmp_add = s1[3:0] + s2[3:0]; +assign dc = (op==ALU_SUB) ? borrow_dc : tmp_add[4]; + +endmodule Index: minirisc/tags/alpha/verilog/core/register_file.v =================================================================== --- minirisc/tags/alpha/verilog/core/register_file.v (nonexistent) +++ minirisc/tags/alpha/verilog/core/register_file.v (revision 7) @@ -0,0 +1,90 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Mini-RISC-1 //// +//// Register File //// +//// //// +//// Author: Rudolf Usselmann //// +//// russelmann@hotmail.com //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Rudolf Usselmann //// +//// russelmann@hotmail.com //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT //// +//// LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND //// +//// FITNESS FOR A PARTICULAR PURPOSE. //// +//// //// +///////////////////////////////////////////////////////////////////// + + +`timescale 1ns / 10ps + +module register_file( clk, + rf_rd_bnk, rf_rd_addr, rf_rd_data, + rf_we, rf_wr_bnk, rf_wr_addr, rf_wr_data); + +input clk; +input [1:0] rf_rd_bnk; +input [4:0] rf_rd_addr; +output [7:0] rf_rd_data; +input rf_we; +input [1:0] rf_wr_bnk; +input [4:0] rf_wr_addr; +input [7:0] rf_wr_data; + +wire clk; +wire [7:0] rf_rd_data; +wire [6:0] rd_addr; +wire [6:0] wr_addr; +wire [7:0] rf_rd_data_mem; +reg [7:0] wr_data_tmp; +reg rd_wr_addr_equal; +wire rd_wr_addr_equal_tmp; +//reg [6:0] rd_adr_r, wr_adr_r; + +// Simple Read & Write Address Mapping to memory address + +assign rd_addr = rf_rd_addr[4] ? + {1'b0, rf_rd_bnk, rf_rd_addr[3:0]} : + {1'b1, 2'b00, 1'b0, rf_rd_addr[2:0]}; + +assign wr_addr = rf_wr_addr[4] ? + {1'b0, rf_wr_bnk, rf_wr_addr[3:0]} : + {1'b1, 2'b00, 1'b0, rf_wr_addr[2:0]}; + +// This logic is to bypass the register file if we are reading and +// writing (in previous instruction) to the same register +always @(posedge clk) + rd_wr_addr_equal <= #1 rd_wr_addr_equal_tmp; + +//assign rd_wr_addr_equal_tmp = (rd_addr==wr_addr) & rf_we; + +cmp8_eq u0( .eq(rd_wr_addr_equal_tmp), .a({rf_we, rd_addr}), .b({1'b1, wr_addr}) ); + +//always @(posedge clk) +// rd_adr_r <= #1 {rf_rd_bnk, rf_rd_addr}; + +//always @(posedge clk) +// wr_adr_r <= #1 {rf_wr_bnk, rf_wr_addr}; + +//cmp8_eq u0( .eq(rd_wr_addr_equal), .a({rf_we, rd_adr_r}), .b({1'b1, wr_adr_r}) ); + +//assign rf_rd_data = rd_wr_addr_equal ? wr_data_tmp : rf_rd_data_mem; + +mux2_8 u2( .sel(rd_wr_addr_equal), .in1(wr_data_tmp), .in0(rf_rd_data_mem), .out(rf_rd_data) ); + +always @(posedge clk) + wr_data_tmp <= #1 rf_wr_data; + +// This is the actual Memory +ssram_128x8 u1(clk, rd_addr, rf_rd_data_mem, rf_we, wr_addr, rf_wr_data); + + +endmodule Index: minirisc/tags/alpha/verilog/core/primitives_xilinx.v =================================================================== --- minirisc/tags/alpha/verilog/core/primitives_xilinx.v (nonexistent) +++ minirisc/tags/alpha/verilog/core/primitives_xilinx.v (revision 7) @@ -0,0 +1,1054 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Mini-RISC-1 //// +//// Primitives for Xilinx Virtex Famaly //// +//// (Generated with CoreGen) //// +//// //// +//// Author: Rudolf Usselmann //// +//// russelmann@hotmail.com //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Rudolf Usselmann //// +//// russelmann@hotmail.com //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT //// +//// LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND //// +//// FITNESS FOR A PARTICULAR PURPOSE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +`timescale 1ns / 10ps + +// LIB_TAG +// synopsys translate_off +// synthesis translate_off +`include "XilinxCoreLib/C_ADDSUB_V1_0.v" +`include "XilinxCoreLib/C_MUX_BUS_V1_0.v" +`include "XilinxCoreLib/C_COMPARE_V1_0.v" +`include "XilinxCoreLib/C_MUX_BIT_V1_0.v" +`include "XilinxCoreLib/C_MEM_DP_BLOCK_V1_0.v" +`include "XilinxCoreLib/C_REG_FD_V1_0.v" +// synthesis translate_on +// synopsys translate_on +// LIB_TAG_END + + +// Mux 4:1 8 bits wide +module mux4_8(sel, in0, in1, in2, in3, out); +input [1:0] sel; +input [7:0] in0, in1, in2, in3; +output [7:0] out; + +// INST_TAG +xilinx_mux4_8 u0 ( + .MA0(in0[0]), + .MA1(in0[1]), + .MA2(in0[2]), + .MA3(in0[3]), + .MA4(in0[4]), + .MA5(in0[5]), + .MA6(in0[6]), + .MA7(in0[7]), + + .MB0(in1[0]), + .MB1(in1[1]), + .MB2(in1[2]), + .MB3(in1[3]), + .MB4(in1[4]), + .MB5(in1[5]), + .MB6(in1[6]), + .MB7(in1[7]), + + .MC0(in2[0]), + .MC1(in2[1]), + .MC2(in2[2]), + .MC3(in2[3]), + .MC4(in2[4]), + .MC5(in2[5]), + .MC6(in2[6]), + .MC7(in2[7]), + + .MD0(in3[0]), + .MD1(in3[1]), + .MD2(in3[2]), + .MD3(in3[3]), + .MD4(in3[4]), + .MD5(in3[5]), + .MD6(in3[6]), + .MD7(in3[7]), + + .S0(sel[0]), + .S1(sel[1]), + + .O0(out[0]), + .O1(out[1]), + .O2(out[2]), + .O3(out[3]), + .O4(out[4]), + .O5(out[5]), + .O6(out[6]), + .O7(out[7]) ); +// INST_TAG_END + +endmodule + +/* +// MOD_TAG +module xilinx_mux4_8 (MA,MB,MC,MD,S,O); // synthesis black_box +input [7:0] MA; +input [7:0] MB; +input [7:0] MC; +input [7:0] MD; +input [1:0] S; +output [7:0] O; + +// synopsys translate_off +// synthesis translate_off + C_MUX_BUS_V1_0 #( + "00000000", + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 4, + 0, + 2, + "00000000", + 0, + 1, + 8) + inst ( + .MA(MA), + .MB(MB), + .MC(MC), + .MD(MD), + .S(S), + .O(O)); +// synthesis translate_on +// synopsys translate_on +endmodule +// MOD_TAG_END +*/ + +// 8 bit comparator +module cmp8_eq(a,b,eq); +input [7:0] a,b; +output eq; + +// INST_TAG +xilinx_cmp8_eq u0 ( + .A0(a[0]), + .A1(a[1]), + .A2(a[2]), + .A3(a[3]), + .A4(a[4]), + .A5(a[5]), + .A6(a[6]), + .A7(a[7]), + + .B0(b[0]), + .B1(b[1]), + .B2(b[2]), + .B3(b[3]), + .B4(b[4]), + .B5(b[5]), + .B6(b[6]), + .B7(b[7]), + + .A_EQ_B(eq) ); +// INST_TAG_END + +endmodule + +/* +// MOD_TAG +module xilinx_cmp8_eq (A,B,A_EQ_B); // synthesis black_box +input [7 : 0] A; +input [7 : 0] B; +output A_EQ_B; + +// synopsys translate_off +// synthesis translate_off + C_COMPARE_V1_0 #( + "0", + 0, + "0", + 1, + 1, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 8) + inst ( + .A(A), + .B(B), + .A_EQ_B(A_EQ_B)); +// synthesis translate_on +// synopsys translate_on +endmodule +// MOD_TAG_END +*/ + +// MUX 2:1 7 bits wide +module mux2_7(sel, in0, in1, out); +input sel; +input [6:0] in0, in1; +output [6:0] out; + +// INST_TAG +xilinx_mux2_7 u0 ( + .MA0(in0[0]), + .MA1(in0[1]), + .MA2(in0[2]), + .MA3(in0[3]), + .MA4(in0[4]), + .MA5(in0[5]), + .MA6(in0[6]), + + .MB0(in1[0]), + .MB1(in1[1]), + .MB2(in1[2]), + .MB3(in1[3]), + .MB4(in1[4]), + .MB5(in1[5]), + .MB6(in1[6]), + + .S0(sel), + + .O0(out[0]), + .O1(out[1]), + .O2(out[2]), + .O3(out[3]), + .O4(out[4]), + .O5(out[5]), + .O6(out[6]) ); +// INST_TAG_END + +endmodule + +/* +// MOD_TAG +module xilinx_mux2_7 (MA,MB,S,O); // synthesis black_box +input [6 : 0] MA; +input [6 : 0] MB; +input [0 : 0] S; +output [6 : 0] O; + +// synopsys translate_off +// synthesis translate_off + C_MUX_BUS_V1_0 #( + "0000000", + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 2, + 0, + 1, + "0000000", + 0, + 1, + 7) + inst ( + .MA(MA), + .MB(MB), + .S(S), + .O(O)); +// synthesis translate_on +// synopsys translate_on +endmodule +// MOD_TAG_END +*/ + + +// Mux 8:1 1 bit wide +module mux8_1( sel, in, out); +input [2:0] sel; +input [7:0] in; +output out; + +// INST_TAG +xilinx_mux8_1 u0 ( + .M0(in[0]), + .M1(in[1]), + .M2(in[2]), + .M3(in[3]), + .M4(in[4]), + .M5(in[5]), + .M6(in[6]), + .M7(in[7]), + + .S0(sel[0]), + .S1(sel[1]), + .S2(sel[2]), + + + .O(out)); +// INST_TAG_END + +endmodule + +/* +// MOD_TAG +module xilinx_mux8_1 (M,S,O); // synthesis black_box +input [7 : 0] M; +input [2 : 0] S; +output O; + +// synopsys translate_off +// synthesis translate_off + C_MUX_BIT_V1_0 #( + "0", + 1, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 8, + 3, + "0", + 0, + 1) + inst ( + .M(M), + .S(S), + .O(O)); +// synthesis translate_on +// synopsys translate_on +endmodule +// MOD_TAG_END +*/ + +// Mux 2:1 8 bits wide +module mux2_8(sel, in0, in1, out); +input sel; +input [7:0] in0, in1; +output [7:0] out; + +// INST_TAG +xilinx_mux2_8 u0( + .MA0(in0[0]), + .MA1(in0[1]), + .MA2(in0[2]), + .MA3(in0[3]), + .MA4(in0[4]), + .MA5(in0[5]), + .MA6(in0[6]), + .MA7(in0[7]), + + .MB0(in1[0]), + .MB1(in1[1]), + .MB2(in1[2]), + .MB3(in1[3]), + .MB4(in1[4]), + .MB5(in1[5]), + .MB6(in1[6]), + .MB7(in1[7]), + + .S0(sel), + + .O0(out[0]), + .O1(out[1]), + .O2(out[2]), + .O3(out[3]), + .O4(out[4]), + .O5(out[5]), + .O6(out[6]), + .O7(out[7]) ); +// INST_TAG_END + +endmodule + + +/* +// MOD_TAG +module xilinx_mux2_8 (MA, MB, S, O); // synthesis black_box +input [7 : 0] MA; +input [7 : 0] MB; +input [0 : 0] S; +output [7 : 0] O; + +// synopsys translate_off +// synthesis translate_off + C_MUX_BUS_V1_0 #( + "00000000", + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 2, + 0, + 1, + "00000000", + 0, + 1, + 8) + inst ( + .MA(MA), + .MB(MB), + .S(S), + .O(O)); +// synthesis translate_on +// synopsys translate_on +endmodule +// MOD_TAG_END +*/ + +// Mux 8:1 8 bits wide +module mux8_8(sel, in0, in1, in2, in3, in4, in5, in6, in7, out); +input [2:0] sel; +input [7:0] in0, in1, in2, in3, in4, in5, in6, in7; +output [7:0] out; + +// INST_TAG +xilinx_mux8_8 u0 ( + .MA0(in0[0]), + .MA1(in0[1]), + .MA2(in0[2]), + .MA3(in0[3]), + .MA4(in0[4]), + .MA5(in0[5]), + .MA6(in0[6]), + .MA7(in0[7]), + + .MB0(in1[0]), + .MB1(in1[1]), + .MB2(in1[2]), + .MB3(in1[3]), + .MB4(in1[4]), + .MB5(in1[5]), + .MB6(in1[6]), + .MB7(in1[7]), + + .MC0(in2[0]), + .MC1(in2[1]), + .MC2(in2[2]), + .MC3(in2[3]), + .MC4(in2[4]), + .MC5(in2[5]), + .MC6(in2[6]), + .MC7(in2[7]), + + .MD0(in3[0]), + .MD1(in3[1]), + .MD2(in3[2]), + .MD3(in3[3]), + .MD4(in3[4]), + .MD5(in3[5]), + .MD6(in3[6]), + .MD7(in3[7]), + + .ME0(in4[0]), + .ME1(in4[1]), + .ME2(in4[2]), + .ME3(in4[3]), + .ME4(in4[4]), + .ME5(in4[5]), + .ME6(in4[6]), + .ME7(in4[7]), + + .MF0(in5[0]), + .MF1(in5[1]), + .MF2(in5[2]), + .MF3(in5[3]), + .MF4(in5[4]), + .MF5(in5[5]), + .MF6(in5[6]), + .MF7(in5[7]), + + .MG0(in6[0]), + .MG1(in6[1]), + .MG2(in6[2]), + .MG3(in6[3]), + .MG4(in6[4]), + .MG5(in6[5]), + .MG6(in6[6]), + .MG7(in6[7]), + + .MH0(in7[0]), + .MH1(in7[1]), + .MH2(in7[2]), + .MH3(in7[3]), + .MH4(in7[4]), + .MH5(in7[5]), + .MH6(in7[6]), + .MH7(in7[7]), + + .S0(sel[0]), + .S1(sel[1]), + .S2(sel[2]), + + .O0(out[0]), + .O1(out[1]), + .O2(out[2]), + .O3(out[3]), + .O4(out[4]), + .O5(out[5]), + .O6(out[6]), + .O7(out[7]) ); + +// INST_TAG_END + +endmodule + +/* +// MOD_TAG +module xilinx_mux8_8 (MA,MB,MC,MD,ME,MF,MG,MH,S,O); // synthesis black_box +input [7 : 0] MA; +input [7 : 0] MB; +input [7 : 0] MC; +input [7 : 0] MD; +input [7 : 0] ME; +input [7 : 0] MF; +input [7 : 0] MG; +input [7 : 0] MH; +input [2 : 0] S; +output [7 : 0] O; + +// synopsys translate_off +// synthesis translate_off + C_MUX_BUS_V1_0 #( + "00000000", + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 8, + 0, + 3, + "00000000", + 0, + 1, + 8) + inst ( + .MA(MA), + .MB(MB), + .MC(MC), + .MD(MD), + .ME(ME), + .MF(MF), + .MG(MG), + .MH(MH), + .S(S), + .O(O)); +// synthesis translate_on +// synopsys translate_on +endmodule +// MOD_TAG_END +*/ + +// Mux 2:1 11 bits wide +module mux2_11(sel, in0, in1, out); +input sel; +input [10:0] in0, in1; +output [10:0] out; + +// INST_TAG +xilinx_mux2_11 u0 ( + .MA0(in0[0]), + .MA1(in0[1]), + .MA2(in0[2]), + .MA3(in0[3]), + .MA4(in0[4]), + .MA5(in0[5]), + .MA6(in0[6]), + .MA7(in0[7]), + .MA8(in0[8]), + .MA9(in0[9]), + .MA10(in0[10]), + + .MB0(in1[0]), + .MB1(in1[1]), + .MB2(in1[2]), + .MB3(in1[3]), + .MB4(in1[4]), + .MB5(in1[5]), + .MB6(in1[6]), + .MB7(in1[7]), + .MB8(in1[8]), + .MB9(in1[9]), + .MB10(in1[10]), + + .S0(sel), + + .O0(out[0]), + .O1(out[1]), + .O2(out[2]), + .O3(out[3]), + .O4(out[4]), + .O5(out[5]), + .O6(out[6]), + .O7(out[7]), + .O8(out[8]), + .O9(out[9]), + .O10(out[10]) ); +// INST_TAG_END + +endmodule + +/* +// MOD_TAG +module xilinx_mux2_11 (MA,MB,S,O); // synthesis black_box +input [10 : 0] MA; +input [10 : 0] MB; +input [0 : 0] S; +output [10 : 0] O; + +// synopsys translate_off +// synthesis translate_off + C_MUX_BUS_V1_0 #( + "00000000000", + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 2, + 0, + 1, + "00000000000", + 0, + 1, + 11) + inst ( + .MA(MA), + .MB(MB), + .S(S), + .O(O)); +// synthesis translate_on +// synopsys translate_on +endmodule +// MOD_TAG_END +*/ + + +// 8bit Add/Sub with carry/borrow out +module add_sub8_co(sub, opa, opb, out, co); +input sub; +input [7:0] opa, opb; +output [7:0] out; +output co; + +wire add; +assign add = ~sub; + +// INST_TAG +xilinx_add_sub8_co u0 ( + .A0(opa[0]), + .A1(opa[1]), + .A2(opa[2]), + .A3(opa[3]), + .A4(opa[4]), + .A5(opa[5]), + .A6(opa[6]), + .A7(opa[7]), + + .B0(opb[0]), + .B1(opb[1]), + .B2(opb[2]), + .B3(opb[3]), + .B4(opb[4]), + .B5(opb[5]), + .B6(opb[6]), + .B7(opb[7]), + + .C_OUT(co), + .ADD(add), + + .S0(out[0]), + .S1(out[1]), + .S2(out[2]), + .S3(out[3]), + .S4(out[4]), + .S5(out[5]), + .S6(out[6]), + .S7(out[7]) ); +// INST_TAG_END + +endmodule + +/* +// MOD_TAG +module xilinx_add_sub8_co (A,B,C_OUT,ADD,S); // synthesis black_box +input [7 : 0] A; +input [7 : 0] B; +output C_OUT; +input ADD; +output [7 : 0] S; + +// synopsys translate_off +// synthesis translate_off + C_ADDSUB_V1_0 #( + 2, + "0000", + 1, + 8, + 0, + 0, + 0, + 1, + "0", + 8, + 1, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 7, + 0, + 8, + 1, + "0", + 0, + 1) + inst ( + .A(A), + .B(B), + .C_OUT(C_OUT), + .ADD(ADD), + .S(S)); +// synthesis translate_on +// synopsys translate_on +endmodule +// MOD_TAG_END +*/ + +// 11 bit incrementer +module inc11(in, out); +input [10:0] in; +output [10:0] out; + +// INST_TAG +xilinx_inc11 u0 ( + .A0(in[0]), + .A1(in[1]), + .A2(in[2]), + .A3(in[3]), + .A4(in[4]), + .A5(in[5]), + .A6(in[6]), + .A7(in[7]), + .A8(in[8]), + .A9(in[9]), + .A10(in[10]), + + .S0(out[0]), + .S1(out[1]), + .S2(out[2]), + .S3(out[3]), + .S4(out[4]), + .S5(out[5]), + .S6(out[6]), + .S7(out[7]), + .S8(out[8]), + .S9(out[9]), + .S10(out[10]) ); +// INST_TAG_END + +endmodule + +/* +// MOD_TAG +module xilinx_inc11 (A,S); // synthesis black_box +input [10 : 0] A; +output [10 : 0] S; + +// synopsys translate_off +// synthesis translate_off + C_ADDSUB_V1_0 #( + 0, + "0000", + 1, + 11, + 0, + 0, + 1, + 1, + "0001", + 11, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 10, + 0, + 11, + 1, + "0", + 0, + 1) + inst ( + .A(A), + .S(S)); +// synthesis translate_on +// synopsys translate_on +endmodule +// MOD_TAG_END +*/ + +// 8 bit incrementer +module inc8(in, out); +input [7:0] in; +output [7:0] out; + +// INST_TAG +xilinx_inc8 u0 ( + .A0(in[0]), + .A1(in[1]), + .A2(in[2]), + .A3(in[3]), + .A4(in[4]), + .A5(in[5]), + .A6(in[6]), + .A7(in[7]), + + .S0(out[0]), + .S1(out[1]), + .S2(out[2]), + .S3(out[3]), + .S4(out[4]), + .S5(out[5]), + .S6(out[6]), + .S7(out[7]) ); +// INST_TAG_END + +endmodule + +/* +// MOD_TAG +module xilinx_inc8 (A,S); // synthesis black_box +input [7 : 0] A; +output [7 : 0] S; + +// synopsys translate_off +// synthesis translate_off + C_ADDSUB_V1_0 #( + 0, + "0000", + 1, + 8, + 0, + 0, + 1, + 1, + "0001", + 8, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 7, + 0, + 8, + 1, + "0", + 0, + 1) + inst ( + .A(A), + .S(S)); +// synthesis translate_on +// synopsys translate_on +endmodule +// MOD_TAG_END +*/ + + +// A Basic Synchrounous FIFO (4 entries deep) +module sfifo4x11(clk, push, din, pop, dout); +input clk; +input push; +input [10:0] din; +input pop; +output [10:0] dout; + +reg [10:0] stack1, stack2, stack3, stack4; + +assign dout = stack1; + +always @(posedge clk) + begin + if(push) // PUSH stack + begin + stack4 <= #1 stack3; + stack3 <= #1 stack2; + stack2 <= #1 stack1; + stack1 <= #1 din; + end + if(pop) // POP stack + begin + stack1 <= #1 stack2; + stack2 <= #1 stack3; + stack3 <= #1 stack4; + end + end + +endmodule + + +// Synchrounous SRAM +// 128 bytes by 8 bits +// 1 read port, 1 write port +// FOR XILINX VERTEX SERIES +module ssram_128x8(clk, rd_addr, rd_data, we, wr_addr, wr_data); +input clk; +input [6:0] rd_addr; +output [7:0] rd_data; +input we; +input [6:0] wr_addr; +input [7:0] wr_data; + +wire [7:0] tmp; + + +// Alternatively RAMs can be instantiated directly +RAMB4_S8_S8 u0( + .DOA( rd_data ), + .ADDRA( {2'b0, rd_addr} ), + .DIA( 8'h00 ), + .ENA( 1'b1 ), + .CLKA( clk ), + .WEA( 1'b0 ), + .RSTA( 1'b0 ), + .DOB( tmp ), + .ADDRB( {2'b0, wr_addr} ), + .DIB( wr_data ), + .ENB( 1'b1 ), + .CLKB( clk ), + .WEB( we ), + .RSTB( 1'b0 ) ); + + +endmodule + + + +// This block is the global Set/Rest for Xilinx VIrtex Serries +// Connect it up as described in Xilinx documentation +// Leave it out for Non Xilinx implementations +module glbl(rst); +input rst; + +wire GSR; + +assign GSR = rst; + +endmodule + + Index: minirisc/tags/alpha/verilog/core/presclr_wdt.v =================================================================== --- minirisc/tags/alpha/verilog/core/presclr_wdt.v (nonexistent) +++ minirisc/tags/alpha/verilog/core/presclr_wdt.v (revision 7) @@ -0,0 +1,118 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Mini-RISC-1 //// +//// Prescaler and Wachdog Counter //// +//// //// +//// Author: Rudolf Usselmann //// +//// russelmann@hotmail.com //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Rudolf Usselmann //// +//// russelmann@hotmail.com //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT //// +//// LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND //// +//// FITNESS FOR A PARTICULAR PURPOSE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +`timescale 1ns / 10ps + +// Prescaler and Wachdog Counter +module presclr_wdt(clk, rst, tcki, option, tmr0_we, tmr0_cnt_en, wdt_en, wdt_clr, wdt_to); +input clk; +input rst; +input tcki; +input [5:0] option; +input tmr0_we; +output tmr0_cnt_en; +input wdt_en, wdt_clr; +output wdt_to; + + +reg [7:0] prescaler; +reg [7:0] wdt; + +reg tmr0_cnt_en; +reg tcki_r; +reg wdt_to; + +wire tose; +wire tosc; +wire psa; +wire [2:0] ps; +wire tcki_a, tcki_b; +wire presclr_ce; +wire prsclr_clr; +wire wdt_to_direct; +reg presclr_out, presclr_out_r1; +wire presclr_out_next; +wire [7:0] presclr_plus_1, wdt_plus_1; +wire [7:0] prescaler_next, prescaler_next1; +wire [7:0] wdt_next, wdt_next1; + +// Inputs select +assign ps = option[2:0]; +assign psa = option[3]; +assign tose = option[4]; +assign tosc = option[5]; + +always @(posedge clk) + tcki_r <= #1 tcki; + +assign tcki_a = tose ^ tcki_r; +assign tcki_b = tosc ? tcki_a : 1'b1; +assign presclr_ce = psa ? wdt_to_direct : tcki_b; + +always @(posedge clk) + tmr0_cnt_en <= #1 psa ? tcki_b : presclr_out; + + +// Prescaler +assign prsclr_clr = psa ? wdt_clr : tmr0_we; + +always @(posedge clk) + //if(rst | prsclr_clr) prescaler <= #1 8'h00; + //else + //if(presclr_ce) prescaler <= #1 presclr_plus_1; + prescaler <= #1 prescaler_next; + +mux2_8 u3( .sel(rst | prsclr_clr), .in1(8'h00), .in0(prescaler_next1), .out(prescaler_next) ); +mux2_8 u4( .sel(presclr_ce), .in1(presclr_plus_1), .in0(prescaler), .out(prescaler_next1) ); + + +mux8_1 u2( .sel(ps), .in(prescaler), .out(presclr_out_next) ); + +always @(posedge clk) + presclr_out_r1 <= #1 presclr_out_next; + +always @(posedge clk) // Edge detector for prescaler output + presclr_out <= #1 presclr_out_next & ~presclr_out_r1 & ~prsclr_clr; + +inc8 u0( .in(prescaler), .out(presclr_plus_1)); + +// Wachdog timer +always @(posedge clk) + wdt_to <= #1 psa ? presclr_out : wdt_to_direct; + +always @(posedge clk) + //if(rst | wdt_clr) wdt <= #1 8'h00; + //else + //if(wdt_en) wdt <= #1 wdt_plus_1; + wdt <= #1 wdt_next; + +mux2_8 u5( .sel(rst | wdt_clr), .in1(8'h00), .in0(wdt_next1), .out(wdt_next) ); +mux2_8 u6( .sel(wdt_en), .in1(wdt_plus_1), .in0(wdt), .out(wdt_next1) ); + +assign wdt_to_direct = (wdt == 8'hff); + +inc8 u1( .in(wdt), .out(wdt_plus_1) ); + +endmodule Index: minirisc/tags/alpha/verilog/core/risc_core.v =================================================================== --- minirisc/tags/alpha/verilog/core/risc_core.v (nonexistent) +++ minirisc/tags/alpha/verilog/core/risc_core.v (revision 7) @@ -0,0 +1,797 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Mini-RISC-1 //// +//// Mini-Risc Core //// +//// //// +//// Author: Rudolf Usselmann //// +//// russelmann@hotmail.com //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Rudolf Usselmann //// +//// russelmann@hotmail.com //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT //// +//// LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND //// +//// FITNESS FOR A PARTICULAR PURPOSE. //// +//// //// +///////////////////////////////////////////////////////////////////// + + +`timescale 1ns / 10ps + +module mrisc( + clk, + rst_in, + + inst_addr, + inst_data, + + portain, + portbin, + portcin, + + portaout, + portbout, + portcout, + + trisa, + trisb, + trisc, + + tcki, + wdt_en ); + +// Basic Core I/O. +input clk; +input rst_in; + +// Program memory interface +output [10:0] inst_addr; +input [11:0] inst_data; + +// Basic I/O Ports +input [7:0] portain; +input [7:0] portbin; +input [7:0] portcin; + +output [7:0] portaout; +output [7:0] portbout; +output [7:0] portcout; + +output [7:0] trisa; +output [7:0] trisb; +output [7:0] trisc; + +input tcki; +input wdt_en; + +// This should be set to the ROM location where our restart vector is. +// As set here, we have 512 words of program space. +parameter PC_RST_VECTOR = 11'h000, // Should be: 11'h7FF, + STAT_RST_VALUE = 8'h18, + OPT_RST_VALUE = 8'h3f, + FSR_RST_VALUE = 7'h0, + TRIS_RST_VALUE = 8'hff; + +parameter ALU_ADD = 4'h0, + ALU_SUB = 4'h1, + ALU_INC = 4'h2, + ALU_DEC = 4'h3, + + ALU_AND = 4'h4, + ALU_CLR = 4'h5, + ALU_NOT = 4'h6, + ALU_IOR = 4'h7, + ALU_MOV = 4'h8, + ALU_MOVW = 4'h9, + ALU_RLF = 4'ha, + ALU_RRF = 4'hb, + ALU_SWP = 4'hc, + ALU_XOR = 4'hd, + ALU_BCF = 4'he, + ALU_BSF = 4'hf; + +parameter // Byte Oriented RF Operations + I_ADDWF = 12'b0001_11??_????, + I_ANDWF = 12'b0001_01??_????, + I_CLRF = 12'b0000_011?_????, + I_CLRW = 12'b0000_0100_0000, + I_COMF = 12'b0010_01??_????, + I_DEC = 12'b0000_11??_????, + I_DECFSZ = 12'b0010_11??_????, + I_INCF = 12'b0010_10??_????, + I_INCFSZ = 12'b0011_11??_????, + I_IORWF = 12'b0001_00??_????, + I_MOV = 12'b0010_00??_????, + I_MOVWF = 12'b0000_001?_????, + I_NOP = 12'b0000_0000_0000, + I_RLF = 12'b0011_01??_????, + I_RRF = 12'b0011_00??_????, + I_SUBWF = 12'b0000_10??_????, + I_SWAPF = 12'b0011_10??_????, + I_XORWF = 12'b0001_10??_????, + + // Bit Oriented RF Operations + I_BCF = 12'b0100_????_????, + I_BSF = 12'b0101_????_????, + I_BTFSC = 12'b0110_????_????, + I_BTFSS = 12'b0111_????_????, + + // Literal & Controll Operations + I_ANDLW = 12'b1110_????_????, + I_CALL = 12'b1001_????_????, + I_CLRWDT = 12'b0000_0000_0100, + I_GOTO = 12'b101?_????_????, + I_IORLW = 12'b1101_????_????, + I_MOVLW = 12'b1100_????_????, + I_OPTION = 12'b0000_0000_0010, + I_RETLW = 12'b1000_????_????, + I_SLEEP = 12'b0000_0000_0011, + I_TRIS = 12'b0000_0000_0???, + I_XORLW = 12'b1111_????_????; + +parameter // sfr register address encodings + INDF_ADDR = 3'h0, + TMR0_ADDR = 3'h1, + PCL_ADDR = 3'h2, + STAT_ADDR = 3'h3, + FSR_ADDR = 3'h4, + PORTA_ADDR = 3'h5, + PORTB_ADDR = 3'h6, + PORTC_ADDR = 3'h7; + +parameter // Source 1 Select + K_SEL = 2'b10, + SFR_SEL = 2'b00, + RF_SEL = 2'b01; + +parameter // STATUS Register status bits we + STAT_WR_C = 3'b001, + STAT_WR_DC = 3'b010, + STAT_WR_Z = 3'b100; + + +// Instruction Register +reg rst; +reg [11:0] instr_0, instr_1; +reg rst_r1, rst_r2; +wire valid; +reg valid_1; + +reg [7:0] mask; +reg [7:0] sfr_rd_data; +reg [3:0] alu_op; +reg src1_sel; +reg [1:0] src1_sel_; + +wire [7:0] dout; // ALU output +wire [7:0] src1; // ALU Source 1 + +reg [2:0] stat_bwe; // status bits we +wire c_out, dc_out, z_out; + +reg pc_skz, pc_skz_; +reg pc_bset, pc_bset_; +reg pc_bclr, pc_bclr_; +reg pc_call, pc_call_; +reg pc_goto, pc_goto_; +reg pc_retlw, pc_retlw_; + +wire invalidate_1; +wire invalidate_0_; +reg invalidate_0; + +// stage 1 dst decode +reg w_we_; +reg rf_we_; +reg sfr_we_; +reg tris_we_; + +// stage 2 dst decode +reg w_we; +wire rf_we; +reg rf_we1, rf_we2, rf_we3; + +reg opt_we; +reg trisa_we; +reg trisb_we; +reg trisc_we; + +wire indf_we_; +reg tmr0_we; +wire pc_we_; +reg pc_we; +reg stat_we; +reg fsr_we; +reg porta_we; +reg portb_we; +reg portc_we; + +wire bit_sel; +wire [7:0] tmr0_next, tmr0_next1, tmr0_plus_1; +wire tmr0_cnt_en; +reg wdt_clr; +wire wdt_to; +wire wdt_en; +wire tcki; + +wire [7:0] sfr_rd_data_tmp1, sfr_rd_data_tmp2, sfr_rd_data_tmp3; + +// Register File Connections +wire [1:0] rf_rd_bnk, rf_wr_bnk; +wire [4:0] rf_rd_addr, rf_wr_addr; +wire [7:0] rf_rd_data, rf_wr_data; + +// Program Counter +reg [10:0] inst_addr; +reg [10:0] pc; +wire [10:0] pc_next; +wire [10:0] pc_plus_1; +wire [10:0] stack_out; +reg [10:0] pc_r, pc_r2; +wire [10:0] pc_next1, pc_next2, pc_next3; + +// W Register +reg [7:0] w; // Working Register +reg [7:0] status; // Status Register +wire [7:0] status_next; +reg [6:0] fsr; // fsr register ( for indirect addressing) +wire [6:0] fsr_next; +reg [7:0] tmr0; // Timer 0 +reg [5:0] option; // Option Register + +// Tristate Control registers. +reg [7:0] trisa; +reg [7:0] trisb; +reg [7:0] trisc; + +// I/O Port registers +reg [7:0] porta_r; // PORTA input register +reg [7:0] portb_r; // PORTB input register +reg [7:0] portc_r; // PORTC input register +reg [7:0] portaout; // PORTA output register +reg [7:0] portbout; // PORTB output register +reg [7:0] portcout; // PORTC output register + +//////////////////////////////////////////////////////////////////////// +// External Reset is Synchrounous to clock +always @(posedge clk) + rst <= #1 rst_in; + +//////////////////////////////////////////////////////////////////////// +// Synchrounous Register File +register_file u0( .clk(clk), .rf_rd_bnk(rf_rd_bnk), .rf_rd_addr(rf_rd_addr), .rf_rd_data(rf_rd_data), + .rf_we(rf_we), .rf_wr_bnk(rf_wr_bnk), .rf_wr_addr(rf_wr_addr), .rf_wr_data(rf_wr_data) ); + +//////////////////////////////////////////////////////////////////////// +// Always Fetch Next Instruction +always @(posedge clk) + instr_0 <= #1 inst_data; + +//////////////////////////////////////////////////////////////////////// +// Instr Decode & Read Logic + +always @(posedge clk) + begin + rst_r1 <= #1 rst | wdt_to; + rst_r2 <= #1 rst | rst_r1 | wdt_to; + end + +assign valid = ~rst_r2 & ~invalidate_1; +always @(posedge clk) + valid_1 <= #1 valid; + +always @(posedge clk) // Basic Decode extracted directly from the instruction + begin + instr_1 <= #1 instr_0; + // Mask for bit modification instructions + case(instr_0[7:5]) // synopsys full_case parallel_case + 0: mask <= #1 8'h01; + 1: mask <= #1 8'h02; + 2: mask <= #1 8'h04; + 3: mask <= #1 8'h08; + 4: mask <= #1 8'h10; + 5: mask <= #1 8'h20; + 6: mask <= #1 8'h40; + 7: mask <= #1 8'h80; + endcase + end + +always @(posedge clk) + pc_r <= #1 pc; // Previous version of PC to accomodate for pipeline + +/* +always @(posedge clk) // SFR Read Operands + if(src1_sel_[1]) sfr_rd_data <= #1 instr_0[7:0]; + else + case(instr_0[2:0]) // synopsys full_case parallel_case + 1: sfr_rd_data <= #1 tmr0_next; + 2: sfr_rd_data <= #1 pc_r[7:0]; + 3: sfr_rd_data <= #1 status_next; + 4: sfr_rd_data <= #1 {1'b1, fsr_next}; + 5: sfr_rd_data <= #1 porta_r; + 6: sfr_rd_data <= #1 portb_r; + 7: sfr_rd_data <= #1 portc_r; + endcase +*/ + +always @(posedge clk) + sfr_rd_data <= #1 sfr_rd_data_tmp1; + + +reg [3:0] sfr_sel; +wire [3:0] sfr_sel_src; + +assign sfr_sel_src = {src1_sel_[1],instr_0[2:0]}; + +always @(sfr_sel_src) + casex(sfr_sel_src) // synopsys full_case parallel_case + 4'b1_???: sfr_sel = 4'b01_11; + 4'b0_001: sfr_sel = 4'bxx_00; + 4'b0_010: sfr_sel = 4'b00_11; + 4'b0_011: sfr_sel = 4'bxx_01; + 4'b0_100: sfr_sel = 4'bxx_10; + 4'b0_101: sfr_sel = 4'b10_11; + 4'b0_11?: sfr_sel = 4'b11_11; + endcase + + +mux4_8 u1( .sel(sfr_sel[1:0]), .out(sfr_rd_data_tmp1), + .in0(tmr0_next), .in1(status_next), + .in2({1'b1, fsr_next}), .in3(sfr_rd_data_tmp2) ); + +mux4_8 u2( .sel(sfr_sel[3:2]), .out(sfr_rd_data_tmp2), + .in0(pc_r[7:0]), .in1(instr_0[7:0]), + .in2(porta_r), .in3(sfr_rd_data_tmp3) ); + +mux2_8 u2b( .sel(instr_0[0]), .out(sfr_rd_data_tmp3), + .in0(portb_r), .in1(portc_r) ); + + +// Register File Read Port +assign rf_rd_bnk = fsr_next[6:5]; +assign rf_rd_addr = (instr_0[4:0]==0) ? fsr_next[4:0] : instr_0[4:0]; + + +// ALU OP +always @(posedge clk) + casex(instr_0) // synopsys full_case + // Byte Oriented RF Operations + I_ADDWF: alu_op <= #1 ALU_ADD; // ADDWF + I_ANDWF: alu_op <= #1 ALU_AND; // ANDWF + I_CLRF: alu_op <= #1 ALU_CLR; // CLRF + I_CLRW: alu_op <= #1 ALU_CLR; // CLRW + I_COMF: alu_op <= #1 ALU_NOT; // COMF + I_DEC: alu_op <= #1 ALU_DEC; // DEC + I_DECFSZ: alu_op <= #1 ALU_DEC; // DECFSZ + I_INCF: alu_op <= #1 ALU_INC; // INCF + I_INCFSZ: alu_op <= #1 ALU_INC; // INCFSZ + I_IORWF: alu_op <= #1 ALU_IOR; // IORWF + I_MOV: alu_op <= #1 ALU_MOV; // MOV + I_MOVWF: alu_op <= #1 ALU_MOVW; // MOVWF + I_RLF: alu_op <= #1 ALU_RLF; // RLF + I_RRF: alu_op <= #1 ALU_RRF; // RRF + I_SUBWF: alu_op <= #1 ALU_SUB; // SUBWF + I_SWAPF: alu_op <= #1 ALU_SWP; // SWAPF + I_XORWF: alu_op <= #1 ALU_XOR; // XORWF + // Bit Oriented RF Operations + I_BCF: alu_op <= #1 ALU_BCF; // BCF + I_BSF: alu_op <= #1 ALU_BSF; // BSF + // Literal & Controll Operations + I_ANDLW: alu_op <= #1 ALU_AND; // ANDLW + I_IORLW: alu_op <= #1 ALU_IOR; // IORLW + I_MOVLW: alu_op <= #1 ALU_MOV; // MOWLW + I_RETLW: alu_op <= #1 ALU_MOV; // RETLW + I_XORLW: alu_op <= #1 ALU_XOR; // XORLW + endcase + + + +// Source Select +// This CPU source 1 can be one of: rf (or sfr) or k, +// second source (if any) is always w +always @(instr_0) + casex(instr_0) // synopsys full_case parallel_case + I_ANDLW: src1_sel_ = K_SEL; + I_CALL: src1_sel_ = K_SEL; + I_GOTO: src1_sel_ = K_SEL; + I_IORLW: src1_sel_ = K_SEL; + I_MOVLW: src1_sel_ = K_SEL; + I_RETLW: src1_sel_ = K_SEL; + I_XORLW: src1_sel_ = K_SEL; + default: src1_sel_ = (instr_0[4:3]==2'h0 & instr_0[2:0] != 0) ? SFR_SEL : RF_SEL; + endcase + +always @(posedge clk) + src1_sel <= #1 src1_sel_[0]; + +// Destination Select +// Destination can be one of: rf, w, option, tris OR one of sfr registers: +// indf, tmr0, pc, status, fsr, porta, portb, portc, option, trisa, trisb, trisc +// Stage 1 +// select w, pc, rf or sfr +reg w_we1, w_we1_; + +always @(instr_0) + begin + casex(instr_0) // synopsys full_case parallel_case + I_ADDWF, I_ANDWF, I_COMF, I_DEC, + I_DECFSZ, I_INCF, I_INCFSZ, I_IORWF, + I_MOV, I_RLF, I_RRF, I_SUBWF, + I_SWAPF, I_XORWF: // w or f + w_we1_ = 1; + default: w_we1_ = 0; + endcase + end + +always @(instr_0) + begin + w_we_ = 0; + rf_we_ = 0; + sfr_we_ = 0; + tris_we_= 0; + casex(instr_0) // synopsys full_case parallel_case + + I_ADDWF, I_ANDWF, I_COMF, I_DEC, + I_DECFSZ, I_INCF, I_INCFSZ, I_IORWF, + I_MOV, I_RLF, I_RRF, I_SUBWF, + I_SWAPF, I_XORWF: // w or f + begin + rf_we_ = instr_0[5] & (instr_0[4] | instr_0[3]); + sfr_we_ = instr_0[5] & ~instr_0[4] & ~instr_0[3]; + end + + I_MOVWF, I_CLRF, I_BCF, I_BSF: // only f + begin + rf_we_ = instr_0[4] | instr_0[3]; + sfr_we_ = ~instr_0[4] & ~instr_0[3]; + end + + I_CLRW, I_IORLW, I_MOVLW, + I_ANDLW, I_RETLW, I_XORLW: w_we_ = 1; // only w + I_TRIS: tris_we_ = 1; // trisa or trisb or trisc + + endcase + end + +assign indf_we_ = sfr_we_ & (instr_0[2:0] == INDF_ADDR); +assign pc_we_ = sfr_we_ & (instr_0[2:0] == PCL_ADDR); + +// Stage 2 destination encoder +// write enable outputs are registered now +always @(posedge clk) + w_we <= #1 w_we_; // working register write 0 enable + +always @(posedge clk) + w_we1 <= #1 w_we1_; // working register write 1 enable + + +// Register File Write Enable is composed of thee conditions: 1) direct register writing (0x10-0x1f); +// 2) Direct Global Register writing (0x08-0x0f), and 3) Indirect Register File Writing +// The logic has been partitioned and balanced between the decode and execute stage ... +/* +assign rf_we = (valid_1 & rf_we1) | (valid_1 & rf_we2 & rf_we3);// register file write enable Composite + +always @(posedge clk) + rf_we1 <= #1 rf_we_; // register file write enable 1 + +always @(posedge clk) + rf_we2 <= #1 fsr_next[4] | fsr_next[3]; // register file write enable 2 + +always @(posedge clk) + rf_we3 <= #1 indf_we_; // register file write enable 3 +*/ + +assign rf_we = rf_we1 | (rf_we2 & rf_we3);// register file write enable Composite + +always @(posedge clk) + rf_we1 <= #1 valid & rf_we_; // register file write enable 1 + +always @(posedge clk) + rf_we2 <= #1 valid & (fsr_next[4] | fsr_next[3]); // register file write enable 2 + +always @(posedge clk) + rf_we3 <= #1 indf_we_; // register file write enable 3 + + + + +always @(posedge clk) + wdt_clr <= #1 instr_0[11:0] == I_CLRWDT; + + +always @(posedge clk) + opt_we <= #1 instr_0[11:0] == I_OPTION; + + +always @(posedge clk) + trisa_we <= #1 tris_we_ & (instr_0[2:0] == PORTA_ADDR); + +always @(posedge clk) + trisb_we <= #1 tris_we_ & (instr_0[2:0] == PORTB_ADDR); + +always @(posedge clk) + trisc_we <= #1 tris_we_ & (instr_0[2:0] == PORTC_ADDR); + +always @(posedge clk) + begin + // SFR registers + tmr0_we <= #1 sfr_we_ & (instr_0[2:0] == TMR0_ADDR); + pc_we <= #1 valid & pc_we_; + stat_we <= #1 valid & sfr_we_ & (instr_0[2:0] == STAT_ADDR); + fsr_we <= #1 valid & sfr_we_ & (instr_0[2:0] == FSR_ADDR); + porta_we <= #1 sfr_we_ & (instr_0[2:0] == PORTA_ADDR); + portb_we <= #1 sfr_we_ & (instr_0[2:0] == PORTB_ADDR); + portc_we <= #1 sfr_we_ & (instr_0[2:0] == PORTC_ADDR); + end + + +// Instructions that directly modify PC +always @(instr_0) + begin + pc_skz_ = 0; + pc_bset_ = 0; + pc_bclr_ = 0; + pc_call_ = 0; + pc_goto_ = 0; + pc_retlw_ = 0; + casex(instr_0) // synopsys full_case parallel_case + // Byte Oriented RF Operations + I_DECFSZ, + I_INCFSZ: pc_skz_ = 1; + // Bit Oriented RF Operations + I_BTFSS: pc_bset_ = 1; + I_BTFSC: pc_bclr_ = 1; + // Literal & Controll Operations + I_CALL: pc_call_ = 1; + I_GOTO: pc_goto_ = 1; + I_RETLW: pc_retlw_ = 1; + endcase + end + + +always @(posedge clk) + begin + pc_skz <= #1 valid & pc_skz_; + pc_bset <= #1 valid & pc_bset_; + pc_bclr <= #1 valid & pc_bclr_; + pc_call <= #1 valid & pc_call_; + pc_goto <= #1 valid & pc_goto_; + pc_retlw <= #1 valid & pc_retlw_; + end + +assign invalidate_0_ = (pc_call_ | pc_goto_ | pc_retlw_ | pc_we_); + +always @(posedge clk) + invalidate_0 <= #1 invalidate_0_; + +// Status bits WE +always @(posedge clk) + begin + stat_bwe <= #1 0; + if(valid) + casex(instr_0) // synopsys full_case parallel_case + // Byte Oriented RF Operations + I_ADDWF: stat_bwe <= #1 STAT_WR_C | STAT_WR_DC | STAT_WR_Z; + I_ANDWF: stat_bwe <= #1 STAT_WR_Z; + I_CLRF: stat_bwe <= #1 STAT_WR_Z; + I_CLRW: stat_bwe <= #1 STAT_WR_Z; + I_COMF: stat_bwe <= #1 STAT_WR_Z; + I_DEC: stat_bwe <= #1 STAT_WR_Z; + I_INCF: stat_bwe <= #1 STAT_WR_Z; + I_IORWF: stat_bwe <= #1 STAT_WR_Z; + I_MOV: stat_bwe <= #1 STAT_WR_Z; + I_RLF: stat_bwe <= #1 STAT_WR_C; + I_RRF: stat_bwe <= #1 STAT_WR_C; + I_SUBWF: stat_bwe <= #1 STAT_WR_C | STAT_WR_DC | STAT_WR_Z; + I_XORWF: stat_bwe <= #1 STAT_WR_Z; + // Literal & Controll Operations + I_ANDLW: stat_bwe <= #1 STAT_WR_Z; + //I_CLRWDT: // Modifies TO & PD *** FIX ME *** + I_IORLW: stat_bwe <= #1 STAT_WR_Z; + //I_SLEEP: // Modifies TO & PD *** FIX ME *** + I_XORLW: stat_bwe <= #1 STAT_WR_Z; + endcase + end + +//////////////////////////////////////////////////////////////////////// +// Wr & Execute Logic (including PC) +// Second Pipeline Stage +//////////////////////////////////////////////////////////////////////// + +// Source OP Sel +//assign src1 = src1_sel ? rf_rd_data : sfr_rd_data; +mux2_8 u3( .sel(src1_sel), .in0(sfr_rd_data), .in1(rf_rd_data), .out(src1) ); + +alu u4( .s1(src1), .s2(w), .mask(mask), .out(dout), + .op(alu_op), .c_in(status[0]), .c(c_out), .dc(dc_out), .z(z_out) ); + +// Register file connections +assign rf_wr_bnk = fsr[6:5]; +assign rf_wr_addr = (instr_1[4:0]==0) ? fsr[4:0] : instr_1[4:0]; +assign rf_wr_data = dout; + +wire [7:0] status_next2; + +// Deal with all special registers (SFR) writes +/* +always @(rst or status or stat_we or stat_bwe or dout or c_out or dc_out or z_out) + if(rst) status_next = STAT_RST_VALUE; + else + begin + status_next = status; // Default Keep Value + if(stat_we) status_next = dout | 8'h18; + else + begin + if(stat_bwe[0]) status_next[0] = c_out; + if(stat_bwe[1]) status_next[1] = dc_out; + if(stat_bwe[2]) status_next[2] = z_out; + end + end +*/ + +assign status_next2[0] = stat_bwe[0] ? c_out : status[0]; +assign status_next2[1] = stat_bwe[1] ? dc_out : status[1]; +assign status_next2[2] = stat_bwe[2] ? z_out : status[2]; + +mux2_8 u21( .sel(stat_we), .in1( {dout | 8'h18} ), .in0( {status[7:3],status_next2[2:0]} ), .out(status_next) ); + +//synopsys sync_set_reset "rst" +always @(posedge clk) + if(rst) status <= #1 STAT_RST_VALUE; + else status <= #1 status_next; + +//assign fsr_next = fsr_we ? dout[6:0] : fsr; + +mux2_7 u31( .sel(fsr_we), .in1(dout[6:0]), .in0(fsr), .out(fsr_next) ); + +//synopsys sync_set_reset "rst" +always @(posedge clk) + if(rst) fsr <= #1 FSR_RST_VALUE; + else fsr <= #1 fsr_next; + +always @(posedge clk) + if(valid_1 & (w_we | (w_we1 & ~instr_1[5])) ) w <= #1 dout; + +//synopsys sync_set_reset "rst" +always @(posedge clk) + if(rst) trisa <= #1 TRIS_RST_VALUE; + else + if(trisa_we & valid_1) trisa <= #1 w; + +//synopsys sync_set_reset "rst" +always @(posedge clk) + if(rst) trisb <= #1 TRIS_RST_VALUE; + else + if(trisb_we & valid_1) trisb <= #1 w; + +//synopsys sync_set_reset "rst" +always @(posedge clk) + if(rst) trisc <= #1 TRIS_RST_VALUE; + else + if(trisc_we & valid_1) trisc <= #1 w; + +//synopsys sync_set_reset "rst" +always @(posedge clk) + if(rst) option <= #1 OPT_RST_VALUE; + else + if(opt_we & valid_1) option <= #1 w[5:0]; + +always @(posedge clk) + if(porta_we & valid_1) portaout <= #1 dout; + +always @(posedge clk) + if(portb_we & valid_1) portbout <= #1 dout; + +always @(posedge clk) + if(portc_we & valid_1) portcout <= #1 dout; + +always @(posedge clk) + begin + porta_r <= #1 portain; + portb_r <= #1 portbin; + portc_r <= #1 portcin; + end + +/////////////////////////////////////////////////////////////////////// +// Timer Logic + +//assign tmr0_next = tmr0_we ? dout : tmr0_cnt_en ? tmr0_plus_1 : tmr0; +//assign tmr0_next = tmr0_we ? dout : tmr0_cnt_en ? (tmr0 + 1) : tmr0; + + +mux2_8 u5( .sel(tmr0_we & valid_1), .in0(tmr0_next1), .in1(dout), .out(tmr0_next) ); +mux2_8 u6( .sel(tmr0_cnt_en), .in0(tmr0), .in1(tmr0_plus_1), .out(tmr0_next1) ); +inc8 u7( .in(tmr0), .out(tmr0_plus_1) ); + + +always @(posedge clk) + tmr0 <= #1 tmr0_next; + +presclr_wdt u8( .clk(clk), .rst(rst), .tcki(tcki), + .option(option[5:0]), + .tmr0_we(tmr0_we & valid_1), + .tmr0_cnt_en(tmr0_cnt_en), .wdt_en(wdt_en), + .wdt_clr(wdt_clr & valid_1), + .wdt_to(wdt_to)); + + +//////////////////////////////////////////////////////////////////////// +// Programm Counter Logic + +always @(posedge clk) + pc_r2 <= #1 pc_r; + +// 'inst_addr' is a duplication of the 'pc'. The only time when it is really needed +// is when the program memory is not on the chip and we want to place the registers +// directly in the IO pads to reduce Tcq (For example in a Xilinx FPGA implementation). +// If the program memory is on the chip or if the implmentation allows feedback from +// registers in the IO cells, this is not needed. Synopsys FPGA compiler appears to +// make the correct decission either way, and gett rid of unneded logic ... + +//synopsys sync_set_reset "rst" +always @(posedge clk) + if(rst) inst_addr <= #1 PC_RST_VECTOR; + else inst_addr <= #1 pc_next; + +//synopsys sync_set_reset "rst" +always @(posedge clk) + if(rst) pc <= #1 PC_RST_VECTOR; + else pc <= #1 pc_next; + +/* +always @(pc_plus_1 or dout or pc_we or status or stack_out or + pc_call or pc_goto or pc_retlw or instr_1) + if(pc_we) pc_next = {status[6:5], 1'b0, dout}; + else + if(!pc_call & !pc_goto & !pc_retlw) pc_next = pc_plus_1; + else + if(pc_call) pc_next = {status[6:5], 1'b0, instr_1[7:0]}; + else + if(pc_goto) pc_next = {status[6:5], instr_1[8:0]}; + else + if(pc_retlw) pc_next = stack_out; +*/ + + +wire [10:0] pc_tmp1, pc_tmp2, pc_tmp3; +wire pc_sel1; + +assign pc_tmp1 = {status[6:5], 1'b0, dout[7:0]}; +assign pc_tmp2 = {status[6:5], 1'b0, instr_1[7:0]}; +assign pc_tmp3 = {status[6:5], instr_1[8:0]}; +assign pc_sel1 = (!pc_call & !pc_goto & !pc_retlw); + +mux2_11 u9 ( .sel(pc_we), .in0(pc_next1), .in1(pc_tmp1), .out(pc_next) ); +mux2_11 u10( .sel(pc_sel1), .in0(pc_next2), .in1(pc_plus_1), .out(pc_next1) ); +mux2_11 u11( .sel(pc_call), .in0(pc_next3), .in1(pc_tmp2), .out(pc_next2) ); +mux2_11 u12( .sel(pc_goto), .in0(stack_out), .in1(pc_tmp3), .out(pc_next3) ); + + +inc11 u13( .in(pc), .out(pc_plus_1) ); + +reg invalidate_1_r1, invalidate_1_r2; + +assign invalidate_1 = (pc_skz & z_out) | (pc_bset & bit_sel) | + (pc_bclr & !bit_sel) | (invalidate_0 & valid_1) | invalidate_1_r1; + + +always @(posedge clk) + begin + invalidate_1_r1 <= #1 (invalidate_0 & valid_1) | invalidate_1_r2; + invalidate_1_r2 <= #1 (invalidate_0 & valid_1); + end + +//assign bit_sel = src1[ instr_1[7:5] ]; +mux8_1 u22( .sel(instr_1[7:5]), .in(src1), .out(bit_sel) ); + +sfifo4x11 u14( .clk(clk), .push(pc_call), .din(pc_r2), .pop(pc_retlw), .dout(stack_out) ); + +endmodule Index: minirisc/tags/alpha/verilog/core/risc_core_top.v =================================================================== --- minirisc/tags/alpha/verilog/core/risc_core_top.v (nonexistent) +++ minirisc/tags/alpha/verilog/core/risc_core_top.v (revision 7) @@ -0,0 +1,271 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Mini-RISC-1 //// +//// Mini-Risc Core Top Levcel //// +//// //// +//// Author: Rudolf Usselmann //// +//// russelmann@hotmail.com //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Rudolf Usselmann //// +//// russelmann@hotmail.com //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT //// +//// LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND //// +//// FITNESS FOR A PARTICULAR PURPOSE. //// +//// //// +///////////////////////////////////////////////////////////////////// + + +`timescale 1ns / 10ps + +module mrisc_top( + clk, rst_in, + porta, portb, portc, + tcki, + wdt_en ); + +// Basic Core I/O. +input clk; +input rst_in; + +// I/O Ports +inout [7:0] porta; +inout [7:0] portb; +inout [7:0] portc; + +input tcki; +input wdt_en; + +//////////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +wire [10:0] inst_addr; +wire [11:0] inst_data; + +wire [7:0] portain; +wire [7:0] portbin; +wire [7:0] portcin; + +wire [7:0] portaout; +wire [7:0] portbout; +wire [7:0] portcout; + +wire [7:0] trisa; +wire [7:0] trisb; +wire [7:0] trisc; + +wire block0, block1, wr_block0, wr_block1; + +wire [10:0] wr_adr; // This signals can be used to optionally +wire [11:0] wr_data; // fill the internal ram from external memory +wire we; + +wire [11:0] dout_unused; + +//////////////////////////////////////////////////////////////////////// +// +// IO Buffers +// + +assign porta[0] = trisa[0] ? 1'bz : portaout[0]; +assign porta[1] = trisa[1] ? 1'bz : portaout[1]; +assign porta[2] = trisa[2] ? 1'bz : portaout[2]; +assign porta[3] = trisa[3] ? 1'bz : portaout[3]; +assign porta[4] = trisa[4] ? 1'bz : portaout[4]; +assign porta[5] = trisa[5] ? 1'bz : portaout[5]; +assign porta[6] = trisa[6] ? 1'bz : portaout[6]; +assign porta[7] = trisa[7] ? 1'bz : portaout[7]; + +assign portb[0] = trisb[0] ? 1'bz : portbout[0]; +assign portb[1] = trisb[1] ? 1'bz : portbout[1]; +assign portb[2] = trisb[2] ? 1'bz : portbout[2]; +assign portb[3] = trisb[3] ? 1'bz : portbout[3]; +assign portb[4] = trisb[4] ? 1'bz : portbout[4]; +assign portb[5] = trisb[5] ? 1'bz : portbout[5]; +assign portb[6] = trisb[6] ? 1'bz : portbout[6]; +assign portb[7] = trisb[7] ? 1'bz : portbout[7]; + +assign portc[0] = trisc[0] ? 1'bz : portcout[0]; +assign portc[1] = trisc[1] ? 1'bz : portcout[1]; +assign portc[2] = trisc[2] ? 1'bz : portcout[2]; +assign portc[3] = trisc[3] ? 1'bz : portcout[3]; +assign portc[4] = trisc[4] ? 1'bz : portcout[4]; +assign portc[5] = trisc[5] ? 1'bz : portcout[5]; +assign portc[6] = trisc[6] ? 1'bz : portcout[6]; +assign portc[7] = trisc[7] ? 1'bz : portcout[7]; + +assign portain = porta; +assign portbin = portb; +assign portcin = portc; + +//////////////////////////////////////////////////////////////////////// +// +// Mini Risc Core +// + +mrisc u0( + clk, + rst_in, + + inst_addr, + inst_data, + + portain, + portbin, + portcin, + + portaout, + portbout, + portcout, + + trisa, + trisb, + trisc, + + tcki, + wdt_en ); + + +//////////////////////////////////////////////////////////////////////// +// +// Program memory +// + +// Optional interface to fill the memory from external ROM +assign wr_adr = 11'h0; +assign wr_data = 12'h0; +assign we = 1'b0; + +// Block selects +assign block0 = ~inst_addr[10]; +assign block1 = inst_addr[10]; +assign wr_block0 = ~wr_adr[10]; +assign wr_block1 = wr_adr[10]; + + +RAMB4_S4_S4 u10( + .CLKA( clk ), + .CLKB( clk ), + .RSTB( 1'b0 ), + .RSTA( 1'b0 ), + + .DOA( inst_data[3:0] ), + .ADDRA( inst_addr[9:0] ), + .DIA( 4'h0 ), + .ENA( block0 ), + .WEA( 1'b0 ), + + .DOB( dout_unused[3:0] ), + .ADDRB( wr_adr[9:0] ), + .DIB( wr_data[3:0] ), + .ENB( wr_block0 ), + .WEB( we ) ); + +RAMB4_S4_S4 u11( + .CLKA( clk ), + .CLKB( clk ), + .RSTB( 1'b0 ), + .RSTA( 1'b0 ), + + .DOA( inst_data[7:4] ), + .ADDRA( inst_addr[9:0] ), + .DIA( 4'h0 ), + .ENA( block0 ), + .WEA( 1'b0 ), + + .DOB( dout_unused[7:4] ), + .ADDRB( wr_adr[9:0] ), + .DIB( wr_data[7:4] ), + .ENB( wr_block0 ), + .WEB( we ) ); + +RAMB4_S4_S4 u12( + .CLKA( clk ), + .CLKB( clk ), + .RSTB( 1'b0 ), + .RSTA( 1'b0 ), + + .DOA( inst_data[11:8] ), + .ADDRA( inst_addr[9:0] ), + .DIA( 4'h0 ), + .ENA( block0 ), + .WEA( 1'b0 ), + + .DOB( dout_unused[11:8] ), + .ADDRB( wr_adr[9:0] ), + .DIB( wr_data[11:8] ), + .ENB( wr_block0 ), + .WEB( we ) ); + +// Depending on how much memory you need and how much is +// available in the device uncomment the below block +/* +RAMB4_S4_S4 u10( + .CLKA( clk ), + .CLKB( clk ), + .RSTB( 1'b0 ), + .RSTA( 1'b0 ), + + .DOA( inst_data[3:0] ), + .ADDRA( inst_addr[9:0] ), + .DIA( 4'h0 ), + .ENA( block1 ), + .WEA( 1'b0 ), + + .DOB( ), + .ADDRB( wr_adr[9:0] ), + .DIB( wr_data[3:0] ), + .ENB( wr_block1 ), + .WEB( we ) ); + +RAMB4_S4_S4 u11( + .CLKA( clk ), + .CLKB( clk ), + .RSTB( 1'b0 ), + .RSTA( 1'b0 ), + + .DOA( inst_data[7:4] ), + .ADDRA( inst_addr[9:0] ), + .DIA( 4'h0 ), + .ENA( block1 ), + .WEA( 1'b0 ), + + .DOB( ), + .ADDRB( wr_adr[9:0] ), + .DIB( wr_data[7:4] ), + .ENB( wr_block1 ), + .WEB( we ) ); + +RAMB4_S4_S4 u12( + .CLKA( clk ), + .CLKB( clk ), + .RSTB( 1'b0 ), + .RSTA( 1'b0 ), + + .DOA( inst_data[11:8] ), + .ADDRA( inst_addr[9:0] ), + .DIA( 4'h0 ), + .ENA( block1 ), + .WEA( 1'b0 ), + + .DOB( ), + .ADDRB( wr_adr[9:0] ), + .DIB( wr_data[11:8] ), + .ENB( wr_block1 ), + .WEB( we ) ); + +*/ + + + +endmodule Index: minirisc/tags/alpha/README.txt =================================================================== --- minirisc/tags/alpha/README.txt (nonexistent) +++ minirisc/tags/alpha/README.txt (revision 7) @@ -0,0 +1,119 @@ + +This is a Mini-RISC CPU/Microcontroller that is mostly compatible with the +PIC 16C57 from Microchip. + + +Legal +===== + +PIC, Microship, etc. are Trademarks of Microchip Technology Inc. + +I have no idea if implementing this core will or will not violate +patents, copyrights or cause any other type of lawsuits. + +I provide this core AS IS, without any warrenties. If you decide to +build this core, you are responsible for any legal resolutions, such +as patents and copyrights, and perhaps others .... + + This source file(s) may be used and distributed without + restriction provided that this copyright statement is not + removed from the file and that any derivative work contains + the original copyright notice and the associated disclaimer. + + THIS SOURCE FILE(S) IS/ARE PROVIDED "AS IS" AND WITHOUT ANY + EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT + LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND + FITNESS FOR A PARTICULAR PURPOSE. + + +Motivation +========== + +After seeing the "free_risc8" on the free-ip web site, I got excited +and downloaded the core. Pretty soon I found out that it had many +many errors and omissions from the original 16C57. So I started looking +at the code. This is when I realized it was very badly designed and +could not be made run faster. So, I sat down and wrote my own PIC IP +core last night. A lot of work was spend in writing test code to ensure +that it was 100% compatible from the software point of view. + +- A PIC compatible Microcontroller that runs a lot faster +- Separate (External to the core) Program Memory +- Options to extend the core + + +Compatibility +============= + +This design should be fully software compatible to the Microchip Implementation +of the PIC 16C57, except for the following extensions: + +- Port A is full 8 bits wide +- Hardware stack is 4 level deep [original 2 levels] (can be easily expanded) +- Executions of instructions that modify the PC has become a lot more expensive + due to the pipeline and execution of instructions on every cycle. + Any instruction that writes to the PC (PC as destination (f), call, goto, retlw) + now takes 4 cycles to execute (instead of 2 in the origianl implementation). + The 4 'skip' instructions, remain as in the original implmentation: 1 cycle + if not skipped, 2 cycles if skipped. +- Sampling of IO ports might be off +- Timer and watchdog might be off a few cycles + + +Performance +=========== + +- Single cycle instruction execution, except as noted above. +- Here are results of some sample implementations: + - Xilinx Spartan2 (Device: xc2s30-6-cs144): Fmax: 50Mhz, Utilization: 66%, Ports: Tsu: 2.2nS, Tcq: 7.7nS + - Xilinx Virtex (Device: xcv50-4-cs144) : Fmax: 40Mhz, Utilization: 35%, Ports: Tsu: 3.0nS, Tcq: 6.2nS + - Xilinx VirtexE (Device: xcv50e-8-cs144): Fmax: 66Mhz, Utilization: 35%, Ports: Tsu: 1.7nS, Tcq: 4.5nS + Half of the cycle time is spend in routing delays. My guess is that by placing + proper locatiuon contrains and guiding the back-end tools, a significant + speed improvement can be achieved .... +- I estimat about 25K gates with the xilinx primitives, (excluding Register + File and Programm Memory). + +Implementing the core +===================== + +The only file you should edit if you really want to implement this core, is the +'primitives.v' file. It contains all parts that can be optimized, depending on +the technology used. It includes memories, and arithmetic modules. +I added a primitives_xilinx,v file and xilinx_primitives.zip which contain +primitives for xilinx. +'risc_core.v' is the top level without program memory and tristate Io buffers for ports. +This is probably a good starting point if you want to instantiate the core in to a larger +design. If you just want a PIC clone, take a loot at 'risc_core_top.v', it was written +with Xilinx FPGAs in mind, but should be easily addaptred to other vendors FPGAs - just +replace the memory blocks ... + +To-Do +===== + +Things that need to be done + +1) Write more test/compliance test vectors + - Verify that all instructions after a goto/call/retlw/write to PCL are not executed + - Verify ALU + - Timer and Watchdog tests + - Perhaps some other ereas ? + +2) Extensions ? + - I guess this is on a "as needed" basis + - A friend suggested to add registers that can be shared by two or more cores in a MP type configuration + +Author +====== + +I have been doing ASIC design, verification and synthesis for over 15 years. +This core is only a "mid-night hack", and should used with caution. + +I'd also like to know if anyone will actually use this core. Please send me a +note if you will ! + +Rudolf Usselmann +russelmann@hotmail.com + +Feel free to send me comments, suggestions and bug reports. + Index: minirisc/tags =================================================================== --- minirisc/tags (nonexistent) +++ minirisc/tags (revision 7)

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