OpenCores
URL https://opencores.org/ocsvn/opb_psram_controller/opb_psram_controller/trunk

Subversion Repositories opb_psram_controller

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 6 to Rev 7
    ↔ Reverse comparison
  •

Rev 6 → Rev 7

/tags/arelease/pcore/opb_psram_v1_00_a/hdl/vhdl/psram_off_iob.vhd File deleted
/tags/arelease/pcore/opb_psram_v1_00_a/hdl/vhdl/opb_psram_controller.vhd File deleted
/tags/arelease/pcore/opb_psram_v1_00_a/hdl/vhdl/psram_wait_iob.vhd File deleted
/tags/arelease/pcore/opb_psram_v1_00_a/hdl/vhdl/opb_psram.vhd File deleted
/tags/arelease/pcore/opb_psram_v1_00_a/hdl/vhdl/psram_clk_iob.vhd File deleted
/tags/arelease/pcore/opb_psram_v1_00_a/hdl/vhdl/psram_data_iob.vhd File deleted
/tags/arelease/pcore/opb_psram_v1_00_a/data/opb_psram_v2_1_0.pao File deleted \ No newline at end of file
/tags/arelease/pcore/opb_psram_v1_00_a/data/opb_psram_v2_1_0.mpd File deleted
/trunk/pcore/opb_psram_v1_00_a/hdl/vhdl/psram_wait_iob.vhd File deleted
/trunk/pcore/opb_psram_v1_00_a/hdl/vhdl/opb_psram.vhd File deleted
/trunk/pcore/opb_psram_v1_00_a/hdl/vhdl/psram_clk_iob.vhd File deleted
/trunk/pcore/opb_psram_v1_00_a/hdl/vhdl/psram_data_iob.vhd File deleted
/trunk/pcore/opb_psram_v1_00_a/hdl/vhdl/psram_off_iob.vhd File deleted
/trunk/pcore/opb_psram_v1_00_a/hdl/vhdl/opb_psram_controller.vhd File deleted
/trunk/pcore/opb_psram_v1_00_a/data/opb_psram_v2_1_0.pao File deleted \ No newline at end of file
/trunk/pcore/opb_psram_v1_00_a/data/opb_psram_v2_1_0.mpd File deleted
/opb_psram_controller/trunk/pcore/opb_psram_v1_00_a/data/opb_psram_v2_1_0.mpd
0,0 → 1,65
###################################################################
##
## Name : opb_psram
## Desc : Microprocessor Peripheral Description
## : Automatically generated by PsfUtility
##
###################################################################
 
BEGIN opb_psram
 
## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = VHDL
OPTION CORE_STATE = ACTIVE
OPTION IP_GROUP = MICROBLAZE:PPC:USER
 
 
## Bus Interfaces
BUS_INTERFACE BUS = SOPB, BUS_TYPE = SLAVE, BUS_STD = OPB
 
## Generics for VHDL or Parameters for Verilog
PARAMETER C_BASEADDR = 0x00000000, DT = std_logic_vector(0 to 31), BUS = SOPB, ADDRESS = BASE, PAIR = C_HIGHADDR, MIN_SIZE = 0x80
PARAMETER C_HIGHADDR = 0x000000ff, DT = std_logic_vector(0 to 31), BUS = SOPB, ADDRESS = HIGH, PAIR = C_BASEADDR
PARAMETER C_USER_ID_CODE = 3, DT = INTEGER
PARAMETER C_OPB_AWIDTH = 32, DT = INTEGER, BUS = SOPB
PARAMETER C_OPB_DWIDTH = 32, DT = INTEGER, BUS = SOPB
PARAMETER C_FAMILY = spartan-3, DT = STRING
PARAMETER C_PSRAM_DQ_WIDTH = 16, DT = INTEGER, ASSIGNMENT = OPTIONAL
PARAMETER C_PSRAM_A_WIDTH = 23, DT = INTEGER, ASSIGNMENT = OPTIONAL
PARAMETER C_PSRAM_LATENCY = 3, DT = INTEGER, ASSIGNMENT = OPTIONAL
PARAMETER C_DRIVE_STRENGTH = 1, DT = INTEGER, ASSIGNMENT = OPTIONAL
 
## Ports
PORT OPB_ABus = OPB_ABus, DIR = I, VEC = [0:(C_OPB_AWIDTH-1)], BUS = SOPB
PORT OPB_BE = OPB_BE, DIR = I, VEC = [0:((C_OPB_DWIDTH/8)-1)], BUS = SOPB
PORT OPB_Clk = "", DIR = I, BUS = SOPB, SIGIS = CLK
PORT OPB_DBus = OPB_DBus, DIR = I, VEC = [0:(C_OPB_DWIDTH-1)], BUS = SOPB
PORT OPB_RNW = OPB_RNW, DIR = I, BUS = SOPB
PORT OPB_Rst = OPB_Rst, DIR = I, BUS = SOPB, SIGIS = RST
PORT OPB_select = OPB_select, DIR = I, BUS = SOPB
PORT OPB_seqAddr = OPB_seqAddr, DIR = I, BUS = SOPB
PORT Sln_DBus = Sl_DBus, DIR = O, VEC = [0:(C_OPB_DWIDTH-1)], BUS = SOPB
PORT Sln_errAck = Sl_errAck, DIR = O, BUS = SOPB
PORT Sln_retry = Sl_retry, DIR = O, BUS = SOPB
PORT Sln_toutSup = Sl_toutSup, DIR = O, BUS = SOPB
PORT Sln_xferAck = Sl_xferAck, DIR = O, BUS = SOPB
PORT PSRAM_Mem_CLK = "", DIR = IO, THREE_STATE = TRUE, TRI_I = PSRAM_Mem_CLK_I, TRI_O = PSRAM_Mem_CLK_O, TRI_T = PSRAM_Mem_CLK_T
PORT PSRAM_Mem_CLK_I = "", DIR = I
PORT PSRAM_Mem_CLK_O = "", DIR = O
PORT PSRAM_Mem_CLK_T = "", DIR = O
PORT PSRAM_Mem_DQ = "", DIR = IO, VEC = [(C_PSRAM_DQ_WIDTH-1):0], ENDIAN = LITTLE, THREE_STATE = TRUE, TRI_I = PSRAM_Mem_DQ_I, TRI_O = PSRAM_Mem_DQ_O, TRI_T = PSRAM_Mem_DQ_T, ENABLE = MULTI
PORT PSRAM_Mem_DQ_I = "", DIR = I, VEC = [(C_PSRAM_DQ_WIDTH-1):0], ENDIAN = LITTLE
PORT PSRAM_Mem_DQ_O = "", DIR = O, VEC = [(C_PSRAM_DQ_WIDTH-1):0], ENDIAN = LITTLE
PORT PSRAM_Mem_DQ_T = "", DIR = O, VEC = [(C_PSRAM_DQ_WIDTH-1):0], ENDIAN = LITTLE
PORT PSRAM_Mem_A = "", DIR = O, VEC = [(C_PSRAM_A_WIDTH-1):0], ENDIAN = LITTLE
PORT PSRAM_Mem_BE = "", DIR = O, VEC = [((C_PSRAM_DQ_WIDTH/8)-1):0], ENDIAN = LITTLE
PORT PSRAM_Mem_WE = "", DIR = O
PORT PSRAM_Mem_OEN = "", DIR = O
PORT PSRAM_Mem_CEN = "", DIR = O
PORT PSRAM_Mem_ADV = "", DIR = O
PORT PSRAM_Mem_WAIT = "", DIR = I
PORT PSRAM_Mem_CRE = "", DIR = O
 
END
/opb_psram_controller/trunk/pcore/opb_psram_v1_00_a/data/opb_psram_v2_1_0.pao
0,0 → 1,12
##############################################################################
## Filename: E:\Eigene_Dateien\Entwicklung\microblaze\psram_test\pcores/opb_psram_v1_00_a/data/opb_psram_v2_1_0.pao
## Description: Peripheral Analysis Order
## Date: Tue Feb 05 18:11:18 2008 (by Create and Import Peripheral Wizard)
##############################################################################
 
lib opb_psram_v1_00_a psram_off_iob vhdl
lib opb_psram_v1_00_a psram_clk_iob vhdl
lib opb_psram_v1_00_a psram_wait_iob vhdl
lib opb_psram_v1_00_a psram_data_iob vhdl
lib opb_psram_v1_00_a opb_psram_controller vhdl
lib opb_psram_v1_00_a opb_psram vhdl
/opb_psram_controller/trunk/pcore/opb_psram_v1_00_a/hdl/vhdl/opb_psram_controller.vhd
0,0 → 1,264
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
 
 
entity opb_psram_controller is
generic (
C_BASEADDR : std_logic_vector(0 to 31) := X"00000000";
C_HIGHADDR : std_logic_vector(0 to 31) := X"000000ff";
C_USER_ID_CODE : integer := 3;
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32;
C_FAMILY : string := "spartan-3";
C_PSRAM_DQ_WIDTH : integer := 16;
C_PSRAM_A_WIDTH : integer := 23;
 
C_PSRAM_LATENCY : integer range 0 to 7 := 3;
C_DRIVE_STRENGTH : integer range 0 to 3 := 1);
port (
OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1);
OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1);
OPB_Clk : in std_logic;
OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_RNW : in std_logic;
OPB_Rst : in std_logic;
OPB_select : in std_logic;
OPB_seqAddr : in std_logic;
Sln_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
Sln_errAck : out std_logic;
Sln_retry : out std_logic;
Sln_toutSup : out std_logic;
Sln_xferAck : out std_logic;
--
PSRAM_Mem_CLK_EN : out std_logic;
PSRAM_Mem_DQ_I_int : in std_logic_vector(C_PSRAM_DQ_WIDTH-1 downto 0);
PSRAM_Mem_DQ_O_int : out std_logic_vector(C_PSRAM_DQ_WIDTH-1 downto 0);
PSRAM_Mem_DQ_OE_int : out std_logic;
PSRAM_Mem_A_int : out std_logic_vector(C_PSRAM_A_WIDTH-1 downto 0);
PSRAM_Mem_BE_int : out std_logic_vector(C_PSRAM_DQ_WIDTH/8-1 downto 0);
PSRAM_Mem_WE_int : out std_logic;
PSRAM_Mem_OEN_int : out std_logic;
PSRAM_Mem_CEN_int : out std_logic := '1';
PSRAM_Mem_ADV_int : out std_logic := '1';
PSRAM_Mem_WAIT_int : in std_logic;
PSRAM_Mem_CRE_int : out std_logic);
 
end opb_psram_controller;
 
architecture rtl of opb_psram_controller is
signal Sln_DBus_big_end : std_logic_vector(C_OPB_DWIDTH-1 downto 0);
signal OPB_ABus_big_end : std_logic_vector(C_OPB_DWIDTH-1 downto 0);
signal OPB_DBus_big_end : std_logic_vector(C_OPB_DWIDTH-1 downto 0);
 
 
type state_t is (startup,
start_wait_ready,
start_write_pulse,
idle,
wr_wait_ready,
wr_msb,
rd_wait_ready,
rd_msb,
rd_ack,
rd_done);
signal state : state_t := startup;
signal cnt : integer range 0 to 7;
signal write_data : std_logic_vector(31 downto 0);
signal read_data : std_logic_vector(15 downto 0);
signal write_be : std_logic_vector(3 downto 0);
 
-- Sync burst acess mode[BCR[15],all other values default
constant C_BCR_CONFIG : std_logic_vector(15 downto 0) := ("00" &
conv_std_logic_vector( C_PSRAM_LATENCY,3) &
"10100" &
conv_std_logic_vector( C_DRIVE_STRENGTH,2) &
"1111");
begin -- rtl
 
-- unused outputs
Sln_errAck <= '0';
Sln_retry <= '0';
Sln_toutSup <= '0';
 
--* convert Sln_DBus_big_end to little mode
conv_big_Sln_DBus_proc : process(Sln_DBus_big_end)
begin
for i in 0 to 31 loop
Sln_DBus(31-i) <= Sln_DBus_big_end(i);
end loop; -- i
end process conv_big_Sln_DBus_proc;
 
--* convert OPB_ABus to big endian
conv_big_OPB_ABus_proc : process(OPB_ABus)
begin
for i in 0 to 31 loop
OPB_ABus_big_end(31-i) <= OPB_ABus(i);
end loop; -- i
end process conv_big_OPB_ABus_proc;
 
--* convert OPB_DBus to little mode
conv_big_OPB_DBus_proc : process(OPB_DBus)
begin
for i in 0 to 31 loop
OPB_DBus_big_end(31-i) <= OPB_DBus(i);
end loop; -- i
end process conv_big_OPB_DBus_proc;
 
--* control OPB requests
--*
--* handles OPB-read and -write request
opb_slave_proc : process (OPB_Rst, OPB_Clk)
begin
if (OPB_Rst = '1') then
-- OPB
Sln_xferAck <= '0';
Sln_DBus_big_end <= (others => '0');
-- PSRAM
PSRAM_Mem_DQ_O_int <= (others => '0');
PSRAM_Mem_DQ_OE_int <= '1'; -- oe disable
PSRAM_Mem_A_int <= (others => '0');
PSRAM_Mem_BE_int <= (others => '1');
PSRAM_Mem_WE_int <= '1';
PSRAM_Mem_OEN_int <= '1';
PSRAM_Mem_CEN_int <= '1';
PSRAM_Mem_ADV_int <= '1';
PSRAM_Mem_CRE_int <= '0';
PSRAM_Mem_CLK_EN <= '0';
state <= startup;
elsif (OPB_Clk'event and OPB_Clk = '1') then
case state is
 
when startup =>
-- write BCR Register
PSRAM_Mem_A_int <= "000" & "10" & "00" & C_BCR_CONFIG;
PSRAM_Mem_ADV_int <= '0'; -- adress strobe
PSRAM_Mem_CEN_int <= '0'; -- chip enable
PSRAM_Mem_CRE_int <= '1';
state <= start_wait_ready;
 
 
when start_wait_ready =>
PSRAM_Mem_ADV_int <= '1'; -- adress strobe
cnt <= 5;
state <= start_write_pulse;
 
when start_write_pulse =>
PSRAM_Mem_A_int <= (others => '0');
PSRAM_Mem_CRE_int <= '0'; -- normal operation
PSRAM_Mem_WE_int <= '0'; -- write operation
if (cnt = 0) then
PSRAM_Mem_WE_int <= '1'; -- write operation
PSRAM_Mem_CEN_int <= '1'; -- chip enable
PSRAM_Mem_CLK_EN <= '1';
state <= idle;
else
cnt <= cnt -1;
state <= start_write_pulse;
end if;
 
 
 
when idle =>
if (OPB_select = '1' and
((OPB_ABus >= C_BASEADDR) and (OPB_ABus <= C_HIGHADDR))) then
-- *device selected
if (OPB_RNW = '0') then
-- write
PSRAM_Mem_CRE_int <= '0'; -- normal operation
PSRAM_Mem_A_int <= OPB_ABus_big_end(C_PSRAM_A_WIDTH downto 2)& '0';
PSRAM_Mem_ADV_int <= '0'; -- adress strobe
PSRAM_Mem_CEN_int <= '0'; -- chip enable
PSRAM_Mem_WE_int <= '0'; -- write operation
write_data <= OPB_DBus_big_end;
write_be <= OPB_BE;
Sln_xferAck <= '1'; -- write ack
state <= wr_wait_ready;
else
-- read acess
PSRAM_Mem_CRE_int <= '0'; -- normal operation
PSRAM_Mem_A_int <= OPB_ABus_big_end(C_PSRAM_A_WIDTH downto 2)& '0';
PSRAM_Mem_ADV_int <= '0'; -- adress strobe
PSRAM_Mem_CEN_int <= '0'; -- chip enable
PSRAM_Mem_WE_int <= '1'; -- read operation
PSRAM_Mem_BE_int <= (others => '0'); -- TODO setup byte enable
state <= rd_wait_ready;
end if;
else
-- not selected
state <= idle;
end if;
 
---------------------------------------------------------------------
-- write
when wr_wait_ready =>
Sln_xferAck <= '0'; -- remove ack
PSRAM_Mem_ADV_int <= '1'; -- remove adress strobe
PSRAM_Mem_A_int <= (others => '0');
PSRAM_Mem_BE_int(0) <= not write_be(0);
PSRAM_Mem_BE_int(1) <= not write_be(1);
PSRAM_Mem_DQ_O_int <= write_data(15 downto 0);
PSRAM_Mem_DQ_OE_int <= '0'; -- output enable
if (PSRAM_Mem_WAIT_int = '0') then
PSRAM_Mem_BE_int(0) <= not write_be(2);
PSRAM_Mem_BE_int(1) <= not write_be(3);
PSRAM_Mem_DQ_O_int <= write_data(31 downto 16);
state <= wr_msb;
else
state <= wr_wait_ready;
end if;
 
when wr_msb =>
if (PSRAM_Mem_WAIT_int = '0') then
PSRAM_Mem_DQ_OE_int <= '1'; -- output disable
PSRAM_Mem_CEN_int <= '1'; -- chip disable
PSRAM_Mem_BE_int <= (others => '1'); -- TODO setup byte enable
PSRAM_Mem_WE_int <= '1'; -- no write operation
state <= idle;
else
-- end of page reached
state <= wr_msb;
end if;
 
---------------------------------------------------------------------
-- read
when rd_wait_ready =>
PSRAM_Mem_ADV_int <= '1'; -- remove adress strobe
PSRAM_Mem_A_int <= (others => '0');
PSRAM_Mem_OEN_int <= '0'; -- chip disable
 
-- wait assert 1 clock before ready
if (PSRAM_Mem_WAIT_int = '0') then
state <= rd_msb;
else
state <= rd_wait_ready;
end if;
 
when rd_msb =>
read_data <= PSRAM_Mem_DQ_I_int;
PSRAM_Mem_CEN_int <= '1'; -- chip disable
PSRAM_Mem_OEN_int <= '1'; -- chip disable
PSRAM_Mem_BE_int <= (others => '1'); -- byte disable
state <= rd_ack;
 
when rd_ack =>
Sln_DBus_big_end <= PSRAM_Mem_DQ_I_int & read_data;
Sln_xferAck <= '1'; -- write ack
state <= rd_done;
 
when rd_done =>
Sln_DBus_big_end <= (others => '0');
Sln_xferAck <= '0'; -- write ack
state <= idle;
when others =>
state <= startup;
end case;
end if;
end process opb_slave_proc;
 
end rtl;
/opb_psram_controller/trunk/pcore/opb_psram_v1_00_a/hdl/vhdl/opb_psram.vhd
0,0 → 1,313
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:07:10 08/30/2006
-- Design Name:
-- Module Name: adc_timing - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
 
entity opb_psram is
generic
(
C_BASEADDR : std_logic_vector(0 to 31) := X"00000000";
C_HIGHADDR : std_logic_vector(0 to 31) := X"000000ff";
C_USER_ID_CODE : integer := 3;
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32;
C_FAMILY : string := "spartan-3";
-- user generic
C_PSRAM_DQ_WIDTH : integer := 16;
C_PSRAM_A_WIDTH : integer := 23;
C_PSRAM_LATENCY : integer range 0 to 7 := 3;
C_DRIVE_STRENGTH : integer range 0 to 3 := 1);
port
(
OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1);
OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1);
OPB_Clk : in std_logic;
OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_RNW : in std_logic;
OPB_Rst : in std_logic;
OPB_select : in std_logic;
OPB_seqAddr : in std_logic;
Sln_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
Sln_errAck : out std_logic;
Sln_retry : out std_logic;
Sln_toutSup : out std_logic;
Sln_xferAck : out std_logic;
-- psram
PSRAM_Mem_CLK_I : in std_logic;
PSRAM_Mem_CLK_O : out std_logic;
PSRAM_Mem_CLK_T : out std_logic;
 
PSRAM_Mem_DQ_I : in std_logic_vector(C_PSRAM_DQ_WIDTH-1 downto 0);
PSRAM_Mem_DQ_O : out std_logic_vector(C_PSRAM_DQ_WIDTH-1 downto 0);
PSRAM_Mem_DQ_T : out std_logic_vector(C_PSRAM_DQ_WIDTH-1 downto 0);
 
PSRAM_Mem_A : out std_logic_vector(C_PSRAM_A_WIDTH-1 downto 0);
PSRAM_Mem_BE : out std_logic_vector(C_PSRAM_DQ_WIDTH/8-1 downto 0);
PSRAM_Mem_WE : out std_logic;
PSRAM_Mem_OEN : out std_logic;
PSRAM_Mem_CEN : out std_logic;
PSRAM_Mem_ADV : out std_logic;
PSRAM_Mem_wait : in std_logic;
PSRAM_Mem_CRE : out std_logic);
 
 
end opb_psram;
 
architecture Behavioral of opb_psram is
 
component psram_clk_iob
port (
clk : in std_logic;
clk_en : in std_logic;
clk_q : out std_logic);
end component;
 
component psram_data_iob
port (
iff_d : in std_logic;
iff_q : out std_logic;
iff_clk : in std_logic;
off_d : in std_logic;
off_q : out std_logic;
off_clk : in std_logic);
end component;
 
component psram_off_iob
port (
off_d : in std_logic;
off_q : out std_logic;
off_clk : in std_logic);
end component;
 
component psram_wait_iob
port (
iff_d : in std_logic;
iff_q : out std_logic;
iff_clk : in std_logic;
iff_en : in std_logic);
end component;
 
component opb_psram_controller
generic (
C_BASEADDR : std_logic_vector(0 to 31);
C_HIGHADDR : std_logic_vector(0 to 31);
C_USER_ID_CODE : integer;
C_OPB_AWIDTH : integer;
C_OPB_DWIDTH : integer;
C_FAMILY : string;
C_PSRAM_DQ_WIDTH : integer;
C_PSRAM_A_WIDTH : integer;
C_PSRAM_LATENCY : integer range 0 to 7 := 3;
C_DRIVE_STRENGTH : integer range 0 to 3 := 1);
port (
OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1);
OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1);
OPB_Clk : in std_logic;
OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_RNW : in std_logic;
OPB_Rst : in std_logic;
OPB_select : in std_logic;
OPB_seqAddr : in std_logic;
Sln_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
Sln_errAck : out std_logic;
Sln_retry : out std_logic;
Sln_toutSup : out std_logic;
Sln_xferAck : out std_logic;
PSRAM_Mem_CLK_EN : out std_logic;
PSRAM_Mem_DQ_I_int : in std_logic_vector(C_PSRAM_DQ_WIDTH-1 downto 0);
PSRAM_Mem_DQ_O_int : out std_logic_vector(C_PSRAM_DQ_WIDTH-1 downto 0);
PSRAM_Mem_DQ_OE_int : out std_logic;
PSRAM_Mem_A_int : out std_logic_vector(C_PSRAM_A_WIDTH-1 downto 0);
PSRAM_Mem_BE_int : out std_logic_vector(C_PSRAM_DQ_WIDTH/8-1 downto 0);
PSRAM_Mem_WE_int : out std_logic;
PSRAM_Mem_OEN_int : out std_logic;
PSRAM_Mem_CEN_int : out std_logic;
PSRAM_Mem_ADV_int : out std_logic;
PSRAM_Mem_WAIT_int : in std_logic;
PSRAM_Mem_CRE_int : out std_logic);
end component;
 
 
-- internal Signals
signal PSRAM_Mem_CLK_EN : std_logic;
signal PSRAM_Mem_DQ_I_int : std_logic_vector(C_PSRAM_DQ_WIDTH-1 downto 0);
signal PSRAM_Mem_DQ_O_int : std_logic_vector(C_PSRAM_DQ_WIDTH-1 downto 0);
signal PSRAM_Mem_DQ_OE_int : std_logic;
signal PSRAM_Mem_A_int : std_logic_vector(C_PSRAM_A_WIDTH-1 downto 0);
signal PSRAM_Mem_BE_int : std_logic_vector(C_PSRAM_DQ_WIDTH/8-1 downto 0);
signal PSRAM_Mem_WE_int : std_logic;
signal PSRAM_Mem_OEN_int : std_logic;
signal PSRAM_Mem_CEN_int : std_logic;
signal PSRAM_Mem_ADV_int : std_logic;
signal PSRAM_Mem_WAIT_int : std_logic;
signal PSRAM_Mem_CRE_int : std_logic;
 
signal OFF_Clk : std_logic;
signal wait_en : std_logic;
 
begin
 
 
-------------------------------------------------------------------------------
PSRAM_Mem_CLK_T <= '0'; -- allways enable
 
psram_clk_iob_1 : psram_clk_iob
port map (
clk => OPB_Clk,
clk_en => PSRAM_Mem_CLK_EN,
clk_q => PSRAM_Mem_CLK_O);
 
OFF_CLK <= not OPB_Clk;
 
 
u1 : for i in 0 to C_PSRAM_DQ_WIDTH-1 generate
psram_dq_iob_1 : psram_data_iob
port map (
iff_d => PSRAM_Mem_DQ_I(i),
iff_q => PSRAM_Mem_DQ_I_int(i),
iff_clk => OPB_Clk,
off_d => PSRAM_Mem_DQ_O_int(i),
off_q => PSRAM_Mem_DQ_O(i),
off_clk => OFF_Clk);
 
psram_a_off_1 : psram_off_iob
port map (
off_d => PSRAM_Mem_DQ_OE_int,
off_q => PSRAM_Mem_DQ_T(i),
off_clk => OFF_Clk);
 
end generate u1;
 
u2 : for i in 0 to C_PSRAM_A_WIDTH-1 generate
psram_a_off_1 : psram_off_iob
port map (
off_d => PSRAM_Mem_A_int(i),
off_q => PSRAM_Mem_A(i),
off_clk => OFF_Clk);
end generate u2;
 
u3 : for i in 0 to C_PSRAM_DQ_WIDTH/8-1 generate
psram_be_off_1 : psram_off_iob
port map (
off_d => PSRAM_Mem_BE_int(i),
off_q => PSRAM_Mem_BE(i),
off_clk => OFF_Clk);
end generate u3;
 
psram_we_off_1 : psram_off_iob
port map (
off_d => PSRAM_Mem_WE_int,
off_q => PSRAM_Mem_WE,
off_clk => OFF_Clk);
 
psram_oen_off_1 : psram_off_iob
port map (
off_d => PSRAM_Mem_OEN_int,
off_q => PSRAM_Mem_OEN,
off_clk => OFF_Clk);
 
psram_cen_off_1 : psram_off_iob
port map (
off_d => PSRAM_Mem_CEN_int,
off_q => PSRAM_Mem_CEN,
off_clk => OFF_Clk);
 
psram_adv_off_1 : psram_off_iob
port map (
off_d => PSRAM_Mem_ADV_int,
off_q => PSRAM_Mem_ADV,
off_clk => OFF_Clk);
 
psram_cre_off_1 : psram_off_iob
port map (
off_d => PSRAM_Mem_CRE_int,
off_q => PSRAM_Mem_CRE,
off_clk => OFF_Clk);
 
process(OFF_Clk)
begin
if rising_edge(OFF_Clk) then
if ((PSRAM_Mem_ADV_int = '0') or (PSRAM_Mem_CEN_int = '1'))then
wait_en <= '1';
else
wait_en <= '0';
end if;
 
end if;
end process;
 
psram_wait_iob_1 : psram_wait_iob
port map (
iff_d => PSRAM_Mem_WAIT,
iff_q => PSRAM_Mem_WAIT_int,
iff_clk => OPB_Clk,
iff_en => wait_en);
 
opb_psram_1 : opb_psram_controller
generic map (
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_USER_ID_CODE => C_USER_ID_CODE,
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_OPB_DWIDTH => C_OPB_DWIDTH,
C_FAMILY => C_FAMILY,
C_PSRAM_DQ_WIDTH => C_PSRAM_DQ_WIDTH,
C_PSRAM_A_WIDTH => C_PSRAM_A_WIDTH,
C_PSRAM_LATENCY => C_PSRAM_LATENCY,
C_DRIVE_STRENGTH => C_DRIVE_STRENGTH)
port map (
OPB_ABus => OPB_ABus,
OPB_BE => OPB_BE,
OPB_Clk => OPB_Clk,
OPB_DBus => OPB_DBus,
OPB_RNW => OPB_RNW,
OPB_Rst => OPB_Rst,
OPB_select => OPB_select,
OPB_seqAddr => OPB_seqAddr,
Sln_DBus => Sln_DBus,
Sln_errAck => Sln_errAck,
Sln_retry => Sln_retry,
Sln_toutSup => Sln_toutSup,
Sln_xferAck => Sln_xferAck,
PSRAM_Mem_CLK_EN => PSRAM_Mem_CLK_EN,
PSRAM_Mem_DQ_I_int => PSRAM_Mem_DQ_I_int,
PSRAM_Mem_DQ_O_int => PSRAM_Mem_DQ_O_int,
PSRAM_Mem_DQ_OE_int => PSRAM_Mem_DQ_OE_int,
PSRAM_Mem_A_int => PSRAM_Mem_A_int,
PSRAM_Mem_BE_int => PSRAM_Mem_BE_int,
PSRAM_Mem_WE_int => PSRAM_Mem_WE_int,
PSRAM_Mem_OEN_int => PSRAM_Mem_OEN_int,
PSRAM_Mem_CEN_int => PSRAM_Mem_CEN_int,
PSRAM_Mem_ADV_int => PSRAM_Mem_ADV_int,
PSRAM_Mem_WAIT_int => PSRAM_Mem_WAIT_int,
PSRAM_Mem_CRE_int => PSRAM_Mem_CRE_int);
 
end Behavioral;
 
/opb_psram_controller/trunk/pcore/opb_psram_v1_00_a/hdl/vhdl/psram_wait_iob.vhd
0,0 → 1,42
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
 
 
entity psram_wait_iob is
port (
iff_d : in std_logic;
iff_q : out std_logic;
iff_clk : in std_logic;
iff_en : in std_logic);
end psram_wait_iob;
 
 
architecture rtl of psram_wait_iob is
attribute iob : string;
attribute iob of psram_wait_iob_iff : label is "true";
begin -- rtl
 
-- iff
psram_wait_iob_iff : FDRSE
generic map (
INIT => '0') -- Initial value of register ('0' or '1')
port map (
Q => iff_q, -- Data output
C => iff_clk, -- Clock input
CE => '1', -- Clock enable input
D => iff_d, -- Data input
R => '0', -- Synchronous reset input
S => iff_en -- Synchronous set input
);
 
 
end rtl;
/opb_psram_controller/trunk/pcore/opb_psram_v1_00_a/hdl/vhdl/psram_clk_iob.vhd
0,0 → 1,51
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
 
 
entity psram_clk_iob is
port (
clk : in std_logic;
clk_en : in std_logic;
clk_q : out std_logic);
end psram_clk_iob;
 
 
architecture rtl of psram_clk_iob is
signal c0 : std_logic;
signal c1 : std_logic;
signal clk_en_inv : std_logic;
 
 
attribute iob : string;
attribute iob of psram_clk_iob : label is "true";
begin -- rtl
 
c0 <= clk;
c1 <= not clk;
clk_en_inv <= not clk_en;
 
 
-- clock output register
psram_clk_iob : FDDRRSE
port map (
Q => clk_Q, -- Data output (connect directly to top-level port)
C0 => c0, -- 0 degree clock input
C1 => c1, -- 180 degree clock input
CE => '1', -- Clock enable input
D0 => '1', -- Posedge data input
D1 => '0', -- Negedge data input
R => clk_en_inv, -- Synchronous reset input
S => '0' -- Synchronous preset input
);
 
 
 
end rtl;
/opb_psram_controller/trunk/pcore/opb_psram_v1_00_a/hdl/vhdl/psram_data_iob.vhd
0,0 → 1,58
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
 
 
entity psram_data_iob is
port (
iff_d : in std_logic;
iff_q : out std_logic;
iff_clk : in std_logic;
off_d : in std_logic;
off_q : out std_logic;
off_clk : in std_logic);
end psram_data_iob;
 
 
architecture rtl of psram_data_iob is
attribute iob : string;
attribute iob of psram_data_iob_iff : label is "true";
attribute iob of psram_data_iob_off : label is "true";
begin -- rtl
 
-- iff
psram_data_iob_iff : FDRSE
generic map (
INIT => '0') -- Initial value of register ('0' or '1')
port map (
Q => iff_q, -- Data output
C => iff_clk, -- Clock input
CE => '1', -- Clock enable input
D => iff_d, -- Data input
R => '0', -- Synchronous reset input
S => '0' -- Synchronous set input
);
 
-- off
psram_data_iob_off : FDRSE
generic map (
INIT => '0') -- Initial value of register ('0' or '1')
port map (
Q => off_q, -- Data output
C => off_clk, -- Clock input
CE => '1', -- Clock enable input
D => off_d, -- Data input
R => '0', -- Synchronous reset input
S => '0' -- Synchronous set input
);
 
 
end rtl;
/opb_psram_controller/trunk/pcore/opb_psram_v1_00_a/hdl/vhdl/psram_off_iob.vhd
0,0 → 1,40
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
 
 
entity psram_off_iob is
port (
off_d : in std_logic;
off_q : out std_logic;
off_clk : in std_logic);
end psram_off_iob;
 
 
architecture rtl of psram_off_iob is
attribute iob : string;
attribute iob of psram_off_iob : label is "true";
begin -- rtl
 
-- off
psram_off_iob : FDRSE
generic map (
INIT => '1') -- Initial value of register ('0' or '1')
port map (
Q => off_q, -- Data output
C => off_clk, -- Clock input
CE => '1', -- Clock enable input
D => off_d, -- Data input
R => '0', -- Synchronous reset input
S => '0' -- Synchronous set input
);
 
 
end rtl;
/opb_psram_controller/trunk
opb_psram_controller/trunk Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: opb_psram_controller/web_uploads =================================================================== --- opb_psram_controller/web_uploads (nonexistent) +++ opb_psram_controller/web_uploads (revision 7)
opb_psram_controller/web_uploads Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: opb_psram_controller/branches =================================================================== --- opb_psram_controller/branches (nonexistent) +++ opb_psram_controller/branches (revision 7)
opb_psram_controller/branches Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: opb_psram_controller/tags/arelease/pcore/opb_psram_v1_00_a/hdl/vhdl/psram_wait_iob.vhd =================================================================== --- opb_psram_controller/tags/arelease/pcore/opb_psram_v1_00_a/hdl/vhdl/psram_wait_iob.vhd (nonexistent) +++ opb_psram_controller/tags/arelease/pcore/opb_psram_v1_00_a/hdl/vhdl/psram_wait_iob.vhd (revision 7) @@ -0,0 +1,42 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use IEEE.STD_LOGIC_UNSIGNED.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +library UNISIM; +use UNISIM.VComponents.all; + + +entity psram_wait_iob is + + port ( + iff_d : in std_logic; + iff_q : out std_logic; + iff_clk : in std_logic; + iff_en : in std_logic); +end psram_wait_iob; + + +architecture rtl of psram_wait_iob is + attribute iob : string; + attribute iob of psram_wait_iob_iff : label is "true"; + +begin -- rtl + +-- iff + psram_wait_iob_iff : FDRSE + generic map ( + INIT => '0') -- Initial value of register ('0' or '1') + port map ( + Q => iff_q, -- Data output + C => iff_clk, -- Clock input + CE => '1', -- Clock enable input + D => iff_d, -- Data input + R => '0', -- Synchronous reset input + S => iff_en -- Synchronous set input + ); + + +end rtl; Index: opb_psram_controller/tags/arelease/pcore/opb_psram_v1_00_a/hdl/vhdl/opb_psram.vhd =================================================================== --- opb_psram_controller/tags/arelease/pcore/opb_psram_v1_00_a/hdl/vhdl/opb_psram.vhd (nonexistent) +++ opb_psram_controller/tags/arelease/pcore/opb_psram_v1_00_a/hdl/vhdl/opb_psram.vhd (revision 7) @@ -0,0 +1,307 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 16:07:10 08/30/2006 +-- Design Name: +-- Module Name: adc_timing - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use IEEE.STD_LOGIC_UNSIGNED.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +library UNISIM; +use UNISIM.VComponents.all; + +entity opb_psram is + generic + ( + C_BASEADDR : std_logic_vector(0 to 31) := X"00000000"; + C_HIGHADDR : std_logic_vector(0 to 31) := X"000000ff"; + C_USER_ID_CODE : integer := 3; + C_OPB_AWIDTH : integer := 32; + C_OPB_DWIDTH : integer := 32; + C_FAMILY : string := "spartan-3"; + -- user generic + C_PSRAM_DQ_WIDTH : integer := 16; + C_PSRAM_A_WIDTH : integer := 23); + port + ( + OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1); + OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1); + OPB_Clk : in std_logic; + OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1); + OPB_RNW : in std_logic; + OPB_Rst : in std_logic; + OPB_select : in std_logic; + OPB_seqAddr : in std_logic; + Sln_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1); + Sln_errAck : out std_logic; + Sln_retry : out std_logic; + Sln_toutSup : out std_logic; + Sln_xferAck : out std_logic; + -- psram + PSRAM_Mem_CLK_I : in std_logic; + PSRAM_Mem_CLK_O : out std_logic; + PSRAM_Mem_CLK_T : out std_logic; + + PSRAM_Mem_DQ_I : in std_logic_vector(C_PSRAM_DQ_WIDTH-1 downto 0); + PSRAM_Mem_DQ_O : out std_logic_vector(C_PSRAM_DQ_WIDTH-1 downto 0); + PSRAM_Mem_DQ_T : out std_logic_vector(C_PSRAM_DQ_WIDTH-1 downto 0); + + PSRAM_Mem_A : out std_logic_vector(C_PSRAM_A_WIDTH-1 downto 0); + PSRAM_Mem_BE : out std_logic_vector(C_PSRAM_DQ_WIDTH/8-1 downto 0); + PSRAM_Mem_WE : out std_logic; + PSRAM_Mem_OEN : out std_logic; + PSRAM_Mem_CEN : out std_logic; + PSRAM_Mem_ADV : out std_logic; + PSRAM_Mem_wait : in std_logic; + PSRAM_Mem_CRE : out std_logic); + + +end opb_psram; + +architecture Behavioral of opb_psram is + + component psram_clk_iob + port ( + clk : in std_logic; + clk_en : in std_logic; + clk_q : out std_logic); + end component; + + component psram_data_iob + port ( + iff_d : in std_logic; + iff_q : out std_logic; + iff_clk : in std_logic; + off_d : in std_logic; + off_q : out std_logic; + off_clk : in std_logic); + end component; + + component psram_off_iob + port ( + off_d : in std_logic; + off_q : out std_logic; + off_clk : in std_logic); + end component; + + component psram_wait_iob + port ( + iff_d : in std_logic; + iff_q : out std_logic; + iff_clk : in std_logic; + iff_en : in std_logic); + end component; + + component opb_psram_controller + generic ( + C_BASEADDR : std_logic_vector(0 to 31); + C_HIGHADDR : std_logic_vector(0 to 31); + C_USER_ID_CODE : integer; + C_OPB_AWIDTH : integer; + C_OPB_DWIDTH : integer; + C_FAMILY : string; + C_PSRAM_DQ_WIDTH : integer; + C_PSRAM_A_WIDTH : integer); + port ( + OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1); + OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1); + OPB_Clk : in std_logic; + OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1); + OPB_RNW : in std_logic; + OPB_Rst : in std_logic; + OPB_select : in std_logic; + OPB_seqAddr : in std_logic; + Sln_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1); + Sln_errAck : out std_logic; + Sln_retry : out std_logic; + Sln_toutSup : out std_logic; + Sln_xferAck : out std_logic; + PSRAM_Mem_CLK_EN : out std_logic; + PSRAM_Mem_DQ_I_int : in std_logic_vector(C_PSRAM_DQ_WIDTH-1 downto 0); + PSRAM_Mem_DQ_O_int : out std_logic_vector(C_PSRAM_DQ_WIDTH-1 downto 0); + PSRAM_Mem_DQ_OE_int : out std_logic; + PSRAM_Mem_A_int : out std_logic_vector(C_PSRAM_A_WIDTH-1 downto 0); + PSRAM_Mem_BE_int : out std_logic_vector(C_PSRAM_DQ_WIDTH/8-1 downto 0); + PSRAM_Mem_WE_int : out std_logic; + PSRAM_Mem_OEN_int : out std_logic; + PSRAM_Mem_CEN_int : out std_logic; + PSRAM_Mem_ADV_int : out std_logic; + PSRAM_Mem_WAIT_int : in std_logic; + PSRAM_Mem_CRE_int : out std_logic); + end component; + + + -- internal Signals + signal PSRAM_Mem_CLK_EN : std_logic; + signal PSRAM_Mem_DQ_I_int : std_logic_vector(C_PSRAM_DQ_WIDTH-1 downto 0); + signal PSRAM_Mem_DQ_O_int : std_logic_vector(C_PSRAM_DQ_WIDTH-1 downto 0); + signal PSRAM_Mem_DQ_OE_int : std_logic; + signal PSRAM_Mem_A_int : std_logic_vector(C_PSRAM_A_WIDTH-1 downto 0); + signal PSRAM_Mem_BE_int : std_logic_vector(C_PSRAM_DQ_WIDTH/8-1 downto 0); + signal PSRAM_Mem_WE_int : std_logic; + signal PSRAM_Mem_OEN_int : std_logic; + signal PSRAM_Mem_CEN_int : std_logic; + signal PSRAM_Mem_ADV_int : std_logic; + signal PSRAM_Mem_WAIT_int : std_logic; + signal PSRAM_Mem_CRE_int : std_logic; + + signal OFF_Clk : std_logic; + signal wait_en : std_logic; + + +begin + + +------------------------------------------------------------------------------- + + PSRAM_Mem_CLK_T <= '0'; -- allways enable + + psram_clk_iob_1 : psram_clk_iob + port map ( + clk => OPB_Clk, + clk_en => PSRAM_Mem_CLK_EN, + clk_q => PSRAM_Mem_CLK_O); + + OFF_CLK <= not OPB_Clk; + + + u1 : for i in 0 to C_PSRAM_DQ_WIDTH-1 generate + psram_dq_iob_1 : psram_data_iob + port map ( + iff_d => PSRAM_Mem_DQ_I(i), + iff_q => PSRAM_Mem_DQ_I_int(i), + iff_clk => OPB_Clk, + off_d => PSRAM_Mem_DQ_O_int(i), + off_q => PSRAM_Mem_DQ_O(i), + off_clk => OFF_Clk); + + psram_a_off_1 : psram_off_iob + port map ( + off_d => PSRAM_Mem_DQ_OE_int, + off_q => PSRAM_Mem_DQ_T(i), + off_clk => OFF_Clk); + + end generate u1; + + u2 : for i in 0 to C_PSRAM_A_WIDTH-1 generate + psram_a_off_1 : psram_off_iob + port map ( + off_d => PSRAM_Mem_A_int(i), + off_q => PSRAM_Mem_A(i), + off_clk => OFF_Clk); + end generate u2; + + u3 : for i in 0 to C_PSRAM_DQ_WIDTH/8-1 generate + psram_be_off_1 : psram_off_iob + port map ( + off_d => PSRAM_Mem_BE_int(i), + off_q => PSRAM_Mem_BE(i), + off_clk => OFF_Clk); + end generate u3; + + psram_we_off_1 : psram_off_iob + port map ( + off_d => PSRAM_Mem_WE_int, + off_q => PSRAM_Mem_WE, + off_clk => OFF_Clk); + + psram_oen_off_1 : psram_off_iob + port map ( + off_d => PSRAM_Mem_OEN_int, + off_q => PSRAM_Mem_OEN, + off_clk => OFF_Clk); + + psram_cen_off_1 : psram_off_iob + port map ( + off_d => PSRAM_Mem_CEN_int, + off_q => PSRAM_Mem_CEN, + off_clk => OFF_Clk); + + psram_adv_off_1 : psram_off_iob + port map ( + off_d => PSRAM_Mem_ADV_int, + off_q => PSRAM_Mem_ADV, + off_clk => OFF_Clk); + + psram_cre_off_1 : psram_off_iob + port map ( + off_d => PSRAM_Mem_CRE_int, + off_q => PSRAM_Mem_CRE, + off_clk => OFF_Clk); + + process(OFF_Clk) + begin + if rising_edge(OFF_Clk) then + if ((PSRAM_Mem_ADV_int = '0') or (PSRAM_Mem_CEN_int = '1'))then + wait_en <= '1'; + else + wait_en <= '0'; + end if; + + end if; + end process; + + psram_wait_iob_1 : psram_wait_iob + port map ( + iff_d => PSRAM_Mem_WAIT, + iff_q => PSRAM_Mem_WAIT_int, + iff_clk => OPB_Clk, + iff_en => wait_en); + + + opb_psram_1 : opb_psram_controller + generic map ( + C_BASEADDR => C_BASEADDR, + C_HIGHADDR => C_HIGHADDR, + C_USER_ID_CODE => C_USER_ID_CODE, + C_OPB_AWIDTH => C_OPB_AWIDTH, + C_OPB_DWIDTH => C_OPB_DWIDTH, + C_FAMILY => C_FAMILY, + C_PSRAM_DQ_WIDTH => C_PSRAM_DQ_WIDTH, + C_PSRAM_A_WIDTH => C_PSRAM_A_WIDTH) + port map ( + OPB_ABus => OPB_ABus, + OPB_BE => OPB_BE, + OPB_Clk => OPB_Clk, + OPB_DBus => OPB_DBus, + OPB_RNW => OPB_RNW, + OPB_Rst => OPB_Rst, + OPB_select => OPB_select, + OPB_seqAddr => OPB_seqAddr, + Sln_DBus => Sln_DBus, + Sln_errAck => Sln_errAck, + Sln_retry => Sln_retry, + Sln_toutSup => Sln_toutSup, + Sln_xferAck => Sln_xferAck, + PSRAM_Mem_CLK_EN => PSRAM_Mem_CLK_EN, + PSRAM_Mem_DQ_I_int => PSRAM_Mem_DQ_I_int, + PSRAM_Mem_DQ_O_int => PSRAM_Mem_DQ_O_int, + PSRAM_Mem_DQ_OE_int => PSRAM_Mem_DQ_OE_int, + PSRAM_Mem_A_int => PSRAM_Mem_A_int, + PSRAM_Mem_BE_int => PSRAM_Mem_BE_int, + PSRAM_Mem_WE_int => PSRAM_Mem_WE_int, + PSRAM_Mem_OEN_int => PSRAM_Mem_OEN_int, + PSRAM_Mem_CEN_int => PSRAM_Mem_CEN_int, + PSRAM_Mem_ADV_int => PSRAM_Mem_ADV_int, + PSRAM_Mem_WAIT_int => PSRAM_Mem_WAIT_int, + PSRAM_Mem_CRE_int => PSRAM_Mem_CRE_int); + +end Behavioral; + Index: opb_psram_controller/tags/arelease/pcore/opb_psram_v1_00_a/hdl/vhdl/psram_clk_iob.vhd =================================================================== --- opb_psram_controller/tags/arelease/pcore/opb_psram_v1_00_a/hdl/vhdl/psram_clk_iob.vhd (nonexistent) +++ opb_psram_controller/tags/arelease/pcore/opb_psram_v1_00_a/hdl/vhdl/psram_clk_iob.vhd (revision 7) @@ -0,0 +1,51 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use IEEE.STD_LOGIC_UNSIGNED.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +library UNISIM; +use UNISIM.VComponents.all; + + +entity psram_clk_iob is + port ( + clk : in std_logic; + clk_en : in std_logic; + clk_q : out std_logic); +end psram_clk_iob; + + +architecture rtl of psram_clk_iob is + signal c0 : std_logic; + signal c1 : std_logic; + signal clk_en_inv : std_logic; + + + attribute iob : string; + attribute iob of psram_clk_iob : label is "true"; + +begin -- rtl + + c0 <= clk; + c1 <= not clk; + clk_en_inv <= not clk_en; + + + -- clock output register + psram_clk_iob : FDDRRSE + port map ( + Q => clk_Q, -- Data output (connect directly to top-level port) + C0 => c0, -- 0 degree clock input + C1 => c1, -- 180 degree clock input + CE => '1', -- Clock enable input + D0 => '1', -- Posedge data input + D1 => '0', -- Negedge data input + R => clk_en_inv, -- Synchronous reset input + S => '0' -- Synchronous preset input + ); + + + +end rtl; Index: opb_psram_controller/tags/arelease/pcore/opb_psram_v1_00_a/hdl/vhdl/psram_data_iob.vhd =================================================================== --- opb_psram_controller/tags/arelease/pcore/opb_psram_v1_00_a/hdl/vhdl/psram_data_iob.vhd (nonexistent) +++ opb_psram_controller/tags/arelease/pcore/opb_psram_v1_00_a/hdl/vhdl/psram_data_iob.vhd (revision 7) @@ -0,0 +1,58 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use IEEE.STD_LOGIC_UNSIGNED.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +library UNISIM; +use UNISIM.VComponents.all; + + +entity psram_data_iob is + + port ( + iff_d : in std_logic; + iff_q : out std_logic; + iff_clk : in std_logic; + off_d : in std_logic; + off_q : out std_logic; + off_clk : in std_logic); +end psram_data_iob; + + +architecture rtl of psram_data_iob is + attribute iob : string; + attribute iob of psram_data_iob_iff : label is "true"; + attribute iob of psram_data_iob_off : label is "true"; + +begin -- rtl + +-- iff + psram_data_iob_iff : FDRSE + generic map ( + INIT => '0') -- Initial value of register ('0' or '1') + port map ( + Q => iff_q, -- Data output + C => iff_clk, -- Clock input + CE => '1', -- Clock enable input + D => iff_d, -- Data input + R => '0', -- Synchronous reset input + S => '0' -- Synchronous set input + ); + +-- off + psram_data_iob_off : FDRSE + generic map ( + INIT => '0') -- Initial value of register ('0' or '1') + port map ( + Q => off_q, -- Data output + C => off_clk, -- Clock input + CE => '1', -- Clock enable input + D => off_d, -- Data input + R => '0', -- Synchronous reset input + S => '0' -- Synchronous set input + ); + + +end rtl; Index: opb_psram_controller/tags/arelease/pcore/opb_psram_v1_00_a/hdl/vhdl/opb_psram_controller.vhd =================================================================== --- opb_psram_controller/tags/arelease/pcore/opb_psram_v1_00_a/hdl/vhdl/opb_psram_controller.vhd (nonexistent) +++ opb_psram_controller/tags/arelease/pcore/opb_psram_v1_00_a/hdl/vhdl/opb_psram_controller.vhd (revision 7) @@ -0,0 +1,256 @@ + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use IEEE.STD_LOGIC_UNSIGNED.all; + + +entity opb_psram_controller is + generic ( + C_BASEADDR : std_logic_vector(0 to 31) := X"00000000"; + C_HIGHADDR : std_logic_vector(0 to 31) := X"000000ff"; + C_USER_ID_CODE : integer := 3; + C_OPB_AWIDTH : integer := 32; + C_OPB_DWIDTH : integer := 32; + C_FAMILY : string := "spartan-3"; + C_PSRAM_DQ_WIDTH : integer := 16; + C_PSRAM_A_WIDTH : integer := 23; + C_BCR_CONFIG : std_logic_vector(15 downto 0) := "0001110100010111"); + + port ( + OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1); + OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1); + OPB_Clk : in std_logic; + OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1); + OPB_RNW : in std_logic; + OPB_Rst : in std_logic; + OPB_select : in std_logic; + OPB_seqAddr : in std_logic; + Sln_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1); + Sln_errAck : out std_logic; + Sln_retry : out std_logic; + Sln_toutSup : out std_logic; + Sln_xferAck : out std_logic; + -- + PSRAM_Mem_CLK_EN : out std_logic; + PSRAM_Mem_DQ_I_int : in std_logic_vector(C_PSRAM_DQ_WIDTH-1 downto 0); + PSRAM_Mem_DQ_O_int : out std_logic_vector(C_PSRAM_DQ_WIDTH-1 downto 0); + PSRAM_Mem_DQ_OE_int : out std_logic; + PSRAM_Mem_A_int : out std_logic_vector(C_PSRAM_A_WIDTH-1 downto 0); + PSRAM_Mem_BE_int : out std_logic_vector(C_PSRAM_DQ_WIDTH/8-1 downto 0); + PSRAM_Mem_WE_int : out std_logic; + PSRAM_Mem_OEN_int : out std_logic; + PSRAM_Mem_CEN_int : out std_logic := '1'; + PSRAM_Mem_ADV_int : out std_logic := '1'; + PSRAM_Mem_WAIT_int : in std_logic; + PSRAM_Mem_CRE_int : out std_logic); + +end opb_psram_controller; + +architecture rtl of opb_psram_controller is + signal Sln_DBus_big_end : std_logic_vector(C_OPB_DWIDTH-1 downto 0); + signal OPB_ABus_big_end : std_logic_vector(C_OPB_DWIDTH-1 downto 0); + signal OPB_DBus_big_end : std_logic_vector(C_OPB_DWIDTH-1 downto 0); + + + type state_t is (startup, + start_wait_ready, + start_write_pulse, + idle, + wr_wait_ready, + wr_msb, + rd_wait_ready, + rd_msb, + rd_ack, + rd_done); + signal state : state_t := startup; + signal cnt : integer range 0 to 7; + signal write_data : std_logic_vector(31 downto 0); + signal read_data : std_logic_vector(15 downto 0); + signal write_be : std_logic_vector(3 downto 0); + +begin -- rtl + +-- unused outputs + Sln_errAck <= '0'; + Sln_retry <= '0'; + Sln_toutSup <= '0'; + + --* convert Sln_DBus_big_end to little mode + conv_big_Sln_DBus_proc : process(Sln_DBus_big_end) + begin + for i in 0 to 31 loop + Sln_DBus(31-i) <= Sln_DBus_big_end(i); + end loop; -- i + end process conv_big_Sln_DBus_proc; + + --* convert OPB_ABus to big endian + conv_big_OPB_ABus_proc : process(OPB_ABus) + begin + for i in 0 to 31 loop + OPB_ABus_big_end(31-i) <= OPB_ABus(i); + end loop; -- i + end process conv_big_OPB_ABus_proc; + + --* convert OPB_DBus to little mode + conv_big_OPB_DBus_proc : process(OPB_DBus) + begin + for i in 0 to 31 loop + OPB_DBus_big_end(31-i) <= OPB_DBus(i); + end loop; -- i + end process conv_big_OPB_DBus_proc; + + --* control OPB requests + --* + --* handles OPB-read and -write request + opb_slave_proc : process (OPB_Rst, OPB_Clk) + begin + if (OPB_Rst = '1') then + -- OPB + Sln_xferAck <= '0'; + Sln_DBus_big_end <= (others => '0'); + -- PSRAM + PSRAM_Mem_DQ_O_int <= (others => '0'); + PSRAM_Mem_DQ_OE_int <= '1'; -- oe disable + PSRAM_Mem_A_int <= (others => '0'); + PSRAM_Mem_BE_int <= (others => '1'); + PSRAM_Mem_WE_int <= '1'; + PSRAM_Mem_OEN_int <= '1'; + PSRAM_Mem_CEN_int <= '1'; + PSRAM_Mem_ADV_int <= '1'; + PSRAM_Mem_CRE_int <= '0'; + PSRAM_Mem_CLK_EN <= '0'; + state <= startup; + elsif (OPB_Clk'event and OPB_Clk = '1') then + case state is + + when startup => + -- write BCR Register + PSRAM_Mem_A_int <= "000" & "10" & "00" & C_BCR_CONFIG; + PSRAM_Mem_ADV_int <= '0'; -- adress strobe + PSRAM_Mem_CEN_int <= '0'; -- chip enable + PSRAM_Mem_CRE_int <= '1'; + state <= start_wait_ready; + + + when start_wait_ready => + PSRAM_Mem_ADV_int <= '1'; -- adress strobe + cnt <= 5; + state <= start_write_pulse; + + when start_write_pulse => + PSRAM_Mem_A_int <= (others => '0'); + PSRAM_Mem_CRE_int <= '0'; -- normal operation + PSRAM_Mem_WE_int <= '0'; -- write operation + if (cnt = 0) then + PSRAM_Mem_WE_int <= '1'; -- write operation + PSRAM_Mem_CEN_int <= '1'; -- chip enable + PSRAM_Mem_CLK_EN <= '1'; + state <= idle; + else + cnt <= cnt -1; + state <= start_write_pulse; + end if; + + + + when idle => + if (OPB_select = '1' and + ((OPB_ABus >= C_BASEADDR) and (OPB_ABus <= C_HIGHADDR))) then + -- *device selected + if (OPB_RNW = '0') then + -- write + PSRAM_Mem_CRE_int <= '0'; -- normal operation + PSRAM_Mem_A_int <= OPB_ABus_big_end(C_PSRAM_A_WIDTH downto 2)& '0'; + PSRAM_Mem_ADV_int <= '0'; -- adress strobe + PSRAM_Mem_CEN_int <= '0'; -- chip enable + PSRAM_Mem_WE_int <= '0'; -- write operation + write_data <= OPB_DBus_big_end; + write_be <= OPB_BE; + Sln_xferAck <= '1'; -- write ack + state <= wr_wait_ready; + else + -- read acess + PSRAM_Mem_CRE_int <= '0'; -- normal operation + PSRAM_Mem_A_int <= OPB_ABus_big_end(C_PSRAM_A_WIDTH downto 2)& '0'; + PSRAM_Mem_ADV_int <= '0'; -- adress strobe + PSRAM_Mem_CEN_int <= '0'; -- chip enable + PSRAM_Mem_WE_int <= '1'; -- read operation + PSRAM_Mem_BE_int <= (others => '0'); -- TODO setup byte enable + state <= rd_wait_ready; + end if; + else + -- not selected + state <= idle; + end if; + + --------------------------------------------------------------------- + -- write + when wr_wait_ready => + Sln_xferAck <= '0'; -- remove ack + PSRAM_Mem_ADV_int <= '1'; -- remove adress strobe + PSRAM_Mem_A_int <= (others => '0'); + PSRAM_Mem_BE_int(0) <= not write_be(3); + PSRAM_Mem_BE_int(1) <= not write_be(2); + PSRAM_Mem_DQ_O_int <= write_data(15 downto 0); + PSRAM_Mem_DQ_OE_int <= '0'; -- output enable + if (PSRAM_Mem_WAIT_int = '0') then + PSRAM_Mem_BE_int(0) <= not write_be(1); + PSRAM_Mem_BE_int(1) <= not write_be(0); + PSRAM_Mem_DQ_O_int <= write_data(31 downto 16); + state <= wr_msb; + else + state <= wr_wait_ready; + end if; + + when wr_msb => + if (PSRAM_Mem_WAIT_int = '0') then + PSRAM_Mem_DQ_OE_int <= '1'; -- output disable + PSRAM_Mem_CEN_int <= '1'; -- chip disable + PSRAM_Mem_BE_int <= (others => '1'); -- TODO setup byte enable + PSRAM_Mem_WE_int <= '1'; -- no write operation + state <= idle; + else + -- end of page reached + state <= wr_msb; + end if; + + --------------------------------------------------------------------- + -- read + when rd_wait_ready => + PSRAM_Mem_ADV_int <= '1'; -- remove adress strobe + PSRAM_Mem_A_int <= (others => '0'); + PSRAM_Mem_OEN_int <= '0'; -- chip disable + + -- wait assert 1 clock before ready + if (PSRAM_Mem_WAIT_int = '0') then + state <= rd_msb; + else + state <= rd_wait_ready; + end if; + + when rd_msb => + read_data <= PSRAM_Mem_DQ_I_int; + PSRAM_Mem_CEN_int <= '1'; -- chip disable + PSRAM_Mem_OEN_int <= '1'; -- chip disable + PSRAM_Mem_BE_int <= (others => '1'); -- byte disable + state <= rd_ack; + + when rd_ack => + Sln_DBus_big_end <= PSRAM_Mem_DQ_I_int & read_data; + Sln_xferAck <= '1'; -- write ack + state <= rd_done; + + when rd_done => + Sln_DBus_big_end <= (others => '0'); + Sln_xferAck <= '0'; -- write ack + state <= idle; + + when others => + state <= startup; + end case; + end if; + end process opb_slave_proc; + + +end rtl; Index: opb_psram_controller/tags/arelease/pcore/opb_psram_v1_00_a/hdl/vhdl/psram_off_iob.vhd =================================================================== --- opb_psram_controller/tags/arelease/pcore/opb_psram_v1_00_a/hdl/vhdl/psram_off_iob.vhd (nonexistent) +++ opb_psram_controller/tags/arelease/pcore/opb_psram_v1_00_a/hdl/vhdl/psram_off_iob.vhd (revision 7) @@ -0,0 +1,40 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use IEEE.STD_LOGIC_UNSIGNED.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +library UNISIM; +use UNISIM.VComponents.all; + + +entity psram_off_iob is + port ( + off_d : in std_logic; + off_q : out std_logic; + off_clk : in std_logic); +end psram_off_iob; + + +architecture rtl of psram_off_iob is + attribute iob : string; + attribute iob of psram_off_iob : label is "true"; + +begin -- rtl + +-- off + psram_off_iob : FDRSE + generic map ( + INIT => '1') -- Initial value of register ('0' or '1') + port map ( + Q => off_q, -- Data output + C => off_clk, -- Clock input + CE => '1', -- Clock enable input + D => off_d, -- Data input + R => '0', -- Synchronous reset input + S => '0' -- Synchronous set input + ); + + +end rtl; Index: opb_psram_controller/tags/arelease/pcore/opb_psram_v1_00_a/data/opb_psram_v2_1_0.pao =================================================================== --- opb_psram_controller/tags/arelease/pcore/opb_psram_v1_00_a/data/opb_psram_v2_1_0.pao (nonexistent) +++ opb_psram_controller/tags/arelease/pcore/opb_psram_v1_00_a/data/opb_psram_v2_1_0.pao (revision 7) @@ -0,0 +1,12 @@ +############################################################################## +## Filename: E:\Eigene_Dateien\Entwicklung\microblaze\psram_test\pcores/opb_psram_v1_00_a/data/opb_psram_v2_1_0.pao +## Description: Peripheral Analysis Order +## Date: Tue Feb 05 18:11:18 2008 (by Create and Import Peripheral Wizard) +############################################################################## + +lib opb_psram_v1_00_a psram_off_iob vhdl +lib opb_psram_v1_00_a psram_clk_iob vhdl +lib opb_psram_v1_00_a psram_wait_iob vhdl +lib opb_psram_v1_00_a psram_data_iob vhdl +lib opb_psram_v1_00_a opb_psram_controller vhdl +lib opb_psram_v1_00_a opb_psram vhdl \ No newline at end of file Index: opb_psram_controller/tags/arelease/pcore/opb_psram_v1_00_a/data/opb_psram_v2_1_0.mpd =================================================================== --- opb_psram_controller/tags/arelease/pcore/opb_psram_v1_00_a/data/opb_psram_v2_1_0.mpd (nonexistent) +++ opb_psram_controller/tags/arelease/pcore/opb_psram_v1_00_a/data/opb_psram_v2_1_0.mpd (revision 7) @@ -0,0 +1,63 @@ +################################################################### +## +## Name : opb_psram +## Desc : Microprocessor Peripheral Description +## : Automatically generated by PsfUtility +## +################################################################### + +BEGIN opb_psram + +## Peripheral Options +OPTION IPTYPE = PERIPHERAL +OPTION IMP_NETLIST = TRUE +OPTION HDL = VHDL +OPTION CORE_STATE = ACTIVE +OPTION IP_GROUP = MICROBLAZE:PPC:USER + + +## Bus Interfaces +BUS_INTERFACE BUS = SOPB, BUS_TYPE = SLAVE, BUS_STD = OPB + +## Generics for VHDL or Parameters for Verilog +PARAMETER C_BASEADDR = 0x00000000, DT = std_logic_vector(0 to 31), BUS = SOPB, ADDRESS = BASE, PAIR = C_HIGHADDR, MIN_SIZE = 0x80 +PARAMETER C_HIGHADDR = 0x000000ff, DT = std_logic_vector(0 to 31), BUS = SOPB, ADDRESS = HIGH, PAIR = C_BASEADDR +PARAMETER C_USER_ID_CODE = 3, DT = INTEGER +PARAMETER C_OPB_AWIDTH = 32, DT = INTEGER, BUS = SOPB +PARAMETER C_OPB_DWIDTH = 32, DT = INTEGER, BUS = SOPB +PARAMETER C_FAMILY = spartan-3, DT = STRING +PARAMETER C_PSRAM_DQ_WIDTH = 16, DT = INTEGER, ASSIGNMENT = OPTIONAL +PARAMETER C_PSRAM_A_WIDTH = 23, DT = INTEGER, ASSIGNMENT = OPTIONAL + +## Ports +PORT OPB_ABus = OPB_ABus, DIR = I, VEC = [0:(C_OPB_AWIDTH-1)], BUS = SOPB +PORT OPB_BE = OPB_BE, DIR = I, VEC = [0:((C_OPB_DWIDTH/8)-1)], BUS = SOPB +PORT OPB_Clk = "", DIR = I, BUS = SOPB, SIGIS = CLK +PORT OPB_DBus = OPB_DBus, DIR = I, VEC = [0:(C_OPB_DWIDTH-1)], BUS = SOPB +PORT OPB_RNW = OPB_RNW, DIR = I, BUS = SOPB +PORT OPB_Rst = OPB_Rst, DIR = I, BUS = SOPB, SIGIS = RST +PORT OPB_select = OPB_select, DIR = I, BUS = SOPB +PORT OPB_seqAddr = OPB_seqAddr, DIR = I, BUS = SOPB +PORT Sln_DBus = Sl_DBus, DIR = O, VEC = [0:(C_OPB_DWIDTH-1)], BUS = SOPB +PORT Sln_errAck = Sl_errAck, DIR = O, BUS = SOPB +PORT Sln_retry = Sl_retry, DIR = O, BUS = SOPB +PORT Sln_toutSup = Sl_toutSup, DIR = O, BUS = SOPB +PORT Sln_xferAck = Sl_xferAck, DIR = O, BUS = SOPB +PORT PSRAM_Mem_CLK = "", DIR = IO, THREE_STATE = TRUE, TRI_I = PSRAM_Mem_CLK_I, TRI_O = PSRAM_Mem_CLK_O, TRI_T = PSRAM_Mem_CLK_T +PORT PSRAM_Mem_CLK_I = "", DIR = I +PORT PSRAM_Mem_CLK_O = "", DIR = O +PORT PSRAM_Mem_CLK_T = "", DIR = O +PORT PSRAM_Mem_DQ = "", DIR = IO, VEC = [(C_PSRAM_DQ_WIDTH-1):0], ENDIAN = LITTLE, THREE_STATE = TRUE, TRI_I = PSRAM_Mem_DQ_I, TRI_O = PSRAM_Mem_DQ_O, TRI_T = PSRAM_Mem_DQ_T, ENABLE = MULTI +PORT PSRAM_Mem_DQ_I = "", DIR = I, VEC = [(C_PSRAM_DQ_WIDTH-1):0], ENDIAN = LITTLE +PORT PSRAM_Mem_DQ_O = "", DIR = O, VEC = [(C_PSRAM_DQ_WIDTH-1):0], ENDIAN = LITTLE +PORT PSRAM_Mem_DQ_T = "", DIR = O, VEC = [(C_PSRAM_DQ_WIDTH-1):0], ENDIAN = LITTLE +PORT PSRAM_Mem_A = "", DIR = O, VEC = [(C_PSRAM_A_WIDTH-1):0], ENDIAN = LITTLE +PORT PSRAM_Mem_BE = "", DIR = O, VEC = [((C_PSRAM_DQ_WIDTH/8)-1):0], ENDIAN = LITTLE +PORT PSRAM_Mem_WE = "", DIR = O +PORT PSRAM_Mem_OEN = "", DIR = O +PORT PSRAM_Mem_CEN = "", DIR = O +PORT PSRAM_Mem_ADV = "", DIR = O +PORT PSRAM_Mem_WAIT = "", DIR = I +PORT PSRAM_Mem_CRE = "", DIR = O + +END Index: opb_psram_controller/tags =================================================================== --- opb_psram_controller/tags (nonexistent) +++ opb_psram_controller/tags (revision 7)
opb_psram_controller/tags Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ##

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.