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    from Rev 6 to Rev 7
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Rev 6 → Rev 7

/open_hitter/trunk/bench/vhdl/parse_price_sim.vhd
63,6 → 63,7
architecture behav of parse_price_sim is
component parse_price
port (
RX_CLK: in std_logic;
in_byte: in std_logic_vector(7 downto 0);
byte_reset: in std_logic;
byte_ready: in std_logic;
93,6 → 94,7
begin
-- Component instantiation.
parse_price_0: parse_price port map (
RX_CLK => RX_CLK,
in_byte => in_byte,
byte_reset => byte_reset,
byte_ready => byte_ready,
106,13 → 108,13
id => id
);
process (RX_CLK) is
constant pkt : std_logic_vector(103 downto 0) := X"081234567857484154534543C0";
constant pkt : std_logic_vector(111 downto 0) := X"081234567857484154534543C078";
begin
if rising_edge(RX_CLK) then
if (px_type = B"01000") and (buy_sell = B"000") and (px = B"00000000_00001000")
and (qty = B"00110100_00110100")
and (sec = B"01001000_01000001_01000001_01010100_01010100_01010011_01010011")
and (id = B"01000011_01000011")
if (px_type = B"00001") and (buy_sell = B"000") and (px = B"00010010_00110100") -- 081234
and (qty = B"01010110_01111000") -- 5678
and (sec = B"01010111_01001000_01000001_01010100_01010011_01000101_01000011") -- 57484154534543
and (id = B"11000000_01111000") -- C078
then
result_is_ok <= '1';
processing <= '0';
120,9 → 122,12
result_is_ok <= '0';
end if;
 
if ((pos > -1) and (pos < 13)) then
if ((pos > -1) and (pos < 14)) then
in_byte <= pkt(8*pos+7 downto 8*pos);
byte_reset <= '0';
byte_ready <= '1';
else
byte_ready <= '0';
end if;
 
if (restart = '1') then
131,7 → 136,7
pos <= 15;
end if;
 
if (pos > -10) then
if (pos > -1) then
pos <= pos -1;
end if;
138,6 → 143,5
end if;
end process;
 
byte_ready <= RX_CLK when ((pos > -1) and (pos < 13)) else '0';
 
end behav;
/open_hitter/trunk/bench/vhdl/parse_price.vhd
52,6 → 52,7
 
entity parse_price is
port (
RX_CLK: in std_logic;
in_byte: in std_logic_vector(7 downto 0);
byte_reset: in std_logic;
byte_ready: in std_logic;
68,39 → 69,44
 
architecture parse_price_implementation of parse_price is
signal infield: std_logic_vector(55 downto 0);
signal pos: integer range 0 to 13;
signal pos: integer range 0 to 14 := 14;
begin
parse: process (byte_ready) is
parse: process (RX_CLK) is
begin
infield(55 downto 8) <= infield(47 downto 0);
infield(7 downto 0) <= in_byte;
if rising_edge(byte_ready) then
if rising_edge(RX_CLK) then
case pos is
when 0 =>
px_type <= in_byte(4 downto 0);
buy_sell <= in_byte(7 downto 5);
infield <= (others=>'0');
when 1 =>
px <= infield(15 downto 0);
infield <= (others=>'0');
when 3 =>
qty <= infield(15 downto 0);
infield <= (others=>'0');
when 10 =>
sec <= infield(55 downto 0);
infield <= (others=>'0');
when 12 =>
id <= infield(15 downto 0);
infield <= (others=>'0');
px_type <= in_byte(7 downto 3);
buy_sell <= in_byte(2 downto 0);
when 2 =>
px(15 downto 8) <= infield(7 downto 0);
px(7 downto 0) <= in_byte;
when 4 =>
qty(15 downto 8) <= infield(7 downto 0);
qty(7 downto 0) <= in_byte;
when 11 =>
sec(55 downto 8) <= infield(47 downto 0);
sec(7 downto 0) <= in_byte;
when 13 =>
id(15 downto 8) <= infield(7 downto 0);
id(7 downto 0) <= in_byte;
price_ready <= std_logic'('1');
when others => null;
end case;
 
if byte_reset = '1' then
if (byte_reset = '1') then
pos <= 0;
elsif (pos = 14) then
pos <= 14;
elsif (byte_ready = '1') then
pos <= pos+1;
else
pos <= pos+1;
pos <= pos;
end if;
 
infield(55 downto 8) <= infield(47 downto 0);
infield(7 downto 0) <= in_byte;
 
end if;
end process parse;
 
/open_hitter/trunk/bench/vhdl/parse_price_wrapper.vhd
60,6 → 60,7
architecture behaviour of parse_price_wrapper is
component parse_price
port (
RX_CLK: in std_logic;
in_byte: in std_logic_vector(7 downto 0);
byte_reset: in std_logic;
byte_ready: in std_logic;
74,6 → 75,7
);
end component;
for parse_price_0: parse_price use entity work.parse_price;
signal RX_CLK: std_logic;
signal in_byte: std_logic_vector(7 downto 0);
signal byte_reset: std_logic;
signal byte_ready: std_logic;
87,6 → 89,7
signal id: std_logic_vector(15 downto 0); -- unique/identifier/counter
begin
parse_price_0: parse_price port map (
RX_CLK => RX_CLK,
in_byte => in_byte,
byte_reset => byte_reset,
byte_ready => byte_ready,
102,7 → 105,7
process
variable l : line;
-- WWHHAATTSSEECC
constant pkt : std_logic_vector(103 downto 0) := X"081234567857484154534543C0";
constant pkt : std_logic_vector(111 downto 0) := X"081234567857484154534543C078";
variable pos : integer;
variable offset : integer;
variable eoffset : integer;
110,18 → 113,20
write (l, String'("Exercising parse_price"));
writeline (output, l);
 
byte_reset <= '1';
byte_ready <= '0';
RX_CLK <= '0';
wait for 1 ns;
byte_reset <= '1';
byte_ready <= '1';
RX_CLK <= '1';
wait for 1 ns;
byte_ready <= '0';
RX_CLK <= '0';
wait for 1 ns;
byte_reset <= '0';
 
for pos in 12 downto 0 loop
for pos in 13 downto 0 loop
in_byte <= pkt(8*pos+7 downto 8*pos);
byte_ready <= '1';
byte_reset <= '0';
RX_CLK <= '1';
wait for 1 ns;
 
for i in in_byte'range loop
160,21 → 165,23
 
writeline(output, l);
 
byte_ready <= '0';
RX_CLK <= '0';
wait for 1 ns;
end loop;
 
 
write (l, String'("Done parse_price"));
writeline (output, l);
 
if (px_type = B"01000") and (buy_sell = B"000") and (px = B"00000000_00001000")
and (qty = B"00110100_00110100")
and (sec = B"01001000_01000001_01000001_01010100_01010100_01010011_01010011")
and (id = B"01000011_01000011")
-- 081234 5678 574841545345 43C0
if (px_type = B"00001") and (buy_sell = B"000") and (px = B"00010010_00110100") -- 081234
and (qty = B"01010110_01111000") -- 5678
and (sec = B"01010111_01001000_01000001_01010100_01010011_01000101_01000011") -- 57484154534543
and (id = B"11000000_01111000") -- C078
then
write (l, String'("... and Price is OK."));
writeline (output, l);
else
write (l, String'("... and price check failed."));
writeline (output, l);
end if;
 
wait;

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