URL
https://opencores.org/ocsvn/single_port/single_port/trunk
Subversion Repositories single_port
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- This comparison shows the changes necessary to convert path
/
- from Rev 6 to Rev 7
- ↔ Reverse comparison
Rev 6 → Rev 7
/trunk/VHDL/single_port.vhd
56,6 → 56,9
-- CVS Revision History |
-- |
-- $Log: not supported by cvs2svn $ |
-- Revision 1.2 2005/10/12 19:39:27 mgeng |
-- Buses unconstrained, LGPL header added |
-- |
-- Revision 1.1.1.1 2003/01/14 21:48:11 rpaley_yid |
-- initial checkin |
-- |
86,7 → 89,7
BEGIN |
|
mem_proc : PROCESS(d, a, rnw) |
TYPE mem_typ IS ARRAY ( 0 TO PAGENUM*PAGEDEPTH-1 ) OF STD_LOGIC_VECTOR(d'RANGE); |
TYPE mem_typ IS ARRAY ( 0 TO 2**a'length-1 ) OF STD_LOGIC_VECTOR(d'RANGE); |
VARIABLE mem : mem_typ; |
BEGIN |
IF ( rnw = '0') THEN -- Write |
102,8 → 105,8
BEGIN |
|
mem_proc : PROCESS(d, a, rnw) |
TYPE mem_typ IS ARRAY ( 0 TO PAGENUM*PAGEDEPTH-1 ) OF BIT_VECTOR(d'RANGE); |
TYPE flag_typ IS ARRAY ( 0 TO PAGENUM*PAGEDEPTH-1 ) OF BOOLEAN; |
TYPE mem_typ IS ARRAY ( 0 TO 2**a'length-1 ) OF BIT_VECTOR(d'RANGE); |
TYPE flag_typ IS ARRAY ( 0 TO 2**a'length-1 ) OF BOOLEAN; |
VARIABLE mem : mem_typ; |
VARIABLE flag : flag_typ; |
BEGIN |
/trunk/VHDL/single_port_pkg.vhd
47,6 → 47,9
-- CVS Revision History |
-- |
-- $Log: not supported by cvs2svn $ |
-- Revision 1.2 2005/10/12 19:39:27 mgeng |
-- Buses unconstrained, LGPL header added |
-- |
-- Revision 1.1.1.1 2003/01/14 21:48:11 rpaley_yid |
-- initial checkin |
-- |
62,7 → 65,6
|
PACKAGE single_port_pkg IS |
CONSTANT PAGEDEPTH : INTEGER := 256; -- memory page depth |
CONSTANT PAGENUM : INTEGER := 4096; -- number of pages in memory. |
-- Address bus type for internal memory |
SUBTYPE addr_typ IS NATURAL; |
-- Operations testbench can do. |