OpenCores
URL https://opencores.org/ocsvn/usb1_funct/usb1_funct/trunk

Subversion Repositories usb1_funct

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 6 to Rev 7
    ↔ Reverse comparison
  •

Rev 6 → Rev 7

/trunk/doc/README.txt
10,75 → 10,87
 
Test Bench
----------
There is no test bench, period !
Please don't email me asking for one, unless you want to hire
me to write one ! As I said above I have tested this core in
real hardware and it works just fine.
I have uploaded a very basic test bench. It should be viewed
as a starting point to write a more comprehensive and complete
test bench.
 
Documentation
-------------
Sorry, there is none. I just don't have the time to write it.
Sorry, there is none. I just don't have the time to write it (yet).
 
However, since this core is derived from my USB 2.0 Function
IP core, you might find something useful in there. Main
difference is that all the high speed support features have
been ripped out, and the interface was changed from a shared
memory model to a FIFO based interface. Further there is no
need for a micro-controller interface and/or register file.
memory model to a FIFO based model. Further there is no need
for a micro-controller interface and/or register file.
 
 
Here is the quick info:
 
The core comes pre-configured with 6 endpoints:
The core will perform all USB enumeration in hardware. Meaning
it will automatically respond to the hosts SETUP packets and
send back appropriate information (which you must enter in to
the ROM). The enumeration process is usually very simple. The
host first requests a device Descriptor, which tells the host
some basic information about the device. Then it gets the
configuration descriptor, which descries the entire configuration
including all interfaces and endpoints. In this implementation
no descriptor may be larger than 64 bytes.
 
ep 0 - Control endpoint [64/64]
ep 1 - isochronous IN [256/512]
ep 2 - isochronous OUT [256/512]
ep 3 - bulk IN [64/256]
ep 4 - bulk OUT [64/256]
ep 5 - interrupt IN [64/64]
I have created anew top level since last check-in. Here is the
hierarchical view of the USB core:
 
The numbers in brackets are [Max Payload Size/Max FIFO Size]
usb1_core
|
+-- usb_phy
| |
| +-- usb_tx_phy
| |
| +-- usb_rx_phy
|
+-- usb1_utmi_if
|
+-- usb1_pl
| |
| +-- usb1_pd
| |
| +-- usb1_pa
| |
| +-- usb1_idma
| |
| +-- usb1_pe
|
+-- usb1_ctrl
|
+-- usb1_rom1
|
+-- 2x generic_fifo_sc_a
|
+-- generic_dpram
 
The isochronous endpoints are handled special. Data is
always transfered in 32 byte "chunks". If the FIFO can not
accept a 32 "byte" chunk, that chunk is dropped and
'dropped_frame" signal is asserted. If the host sends a
packet that is not in multiple of 32 bytes the
"misaligned_frame" signal is asserted.
The following files have been removed and are no longer needed:
usb1_top.v
usb1_ep_in.v
usb1_ep_out.v
usb1_ep.v
usb1_fifo.v
 
This of this "chunks" as being video frames for example.
It's OK to drop one entire frame, or to display one frame
multiple times. However you don't want to loose synchronization,
where the frame begins or ends. You might want to add some
encoding on to the data stream itself as well, as a fail
save mechanism to not get out of sync. All of this might be
disabled by making sure USB1_ISO_CHUNKS is NOT defined
anywahere.
This new release is a more generic and user friendly version of the
first release. You can now easy configure the endpoints and other
features. FIFOs are external to the core, you can chose the fifo
that best fits you from the "generfic_fifos" projects at OpenCores.
This includes choosing a dual clock fifo if you need to.
 
Vendor Features allow you to define your own features and
set and check various device parameters. For example you
might wan tot count the number of drooped frames so that
the host can read this out for statistics purposes.
The new top level (usb1_core.v) has now a brief description of the
IO signals. Hopefully that description and the test bench will be
sufficient to get you started.
 
This core will perform the entire USB 1.1 enumeration
process in hardware. All you need is to edit the usb1_rom1.v
file and put appropriate values there. This allows you to build
a USB 1.1 device without the need for a micro-controller/CPU.
For example a mouse or joystick ...
Also remember that you MUST edit the ROM to properly configure the
settings for your implementation and enter proper vendor IDs, etc.
 
The top level should be considered an example how to build
your own customized USB 1.1 device.
I will try to write a more complete documentation as I get the time.
 
The 'loop' signal allows you to place the isochronous and
bulk endpoints in to a loop back mode. Use that is you just
wan to see the core talk to your Linux box. Place it in to
loop-back mode, compile it in to and FPGA and plug in to your
PC running Linux. Type 'lsusb' and you should see a device
which enumerated to "1234:5678" Strings don't work without a
dedicated driver that takes control of the device (At least
under RedHat linux 7.3).
 
 
Misc
----
The USB 1.1 Function Project Page is:
87,7 → 99,6
To find out more about me (Rudolf Usselmann), please visit:
http://www.asics.ws
 
 
Directory Structure
-------------------
[core_root]
/trunk/sim/rtl_sim/run/waves/waves.do
0,0 → 1,168
// Signalscan Version 6.8b1
 
 
define noactivityindicator
define analog waveform lines
define add variable default overlay off
define waveform window analogheight 1
define terminal automatic
define buttons control \
1 opensimmulationfile \
2 executedofile \
3 designbrowser \
4 waveform \
5 source \
6 breakpoints \
7 definesourcessearchpath \
8 exit \
9 createbreakpoint \
10 creategroup \
11 createmarker \
12 closesimmulationfile \
13 renamesimmulationfile \
14 replacesimulationfiledata \
15 listopensimmulationfiles \
16 savedofile
define buttons waveform \
1 replacesimulationfiledata \
2 cut \
3 copy \
4 paste \
5 delete \
6 zoomin \
7 zoomout \
8 zoomoutfull \
9 expand \
10 createmarker \
11 designbrowser:1 \
12 savedofile \
13 variableradixoctal \
14 variableradixdecimal \
15 variableradixhexadecimal \
16 variableradixascii
define buttons designbrowser \
1 undo \
2 cut \
3 copy \
4 paste \
5 delete \
6 cdupscope \
7 getallvariables \
8 getdeepallvariables \
9 addvariables \
10 addvarsandclosewindow \
11 closewindow \
12 scopefiltermodule \
13 scopefiltertask \
14 scopefilterfunction \
15 scopefilterblock \
16 scopefilterprimitive
define buttons event \
1 undo \
2 cut \
3 copy \
4 paste \
5 delete \
6 move \
7 closewindow \
8 duplicate \
9 defineasrisingedge \
10 defineasfallingedge \
11 defineasanyedge \
12 variableradixbinary \
13 variableradixoctal \
14 variableradixdecimal \
15 variableradixhexadecimal \
16 variableradixascii
define buttons source \
1 undo \
2 cut \
3 copy \
4 paste \
5 delete \
6 createbreakpoint \
7 creategroup \
8 createmarker \
9 createevent \
10 createregisterpage \
11 closewindow \
12 opensimmulationfile \
13 closesimmulationfile \
14 renamesimmulationfile \
15 replacesimulationfiledata \
16 listopensimmulationfiles
define buttons register \
1 undo \
2 cut \
3 copy \
4 paste \
5 delete \
6 createregisterpage \
7 closewindow \
8 continuefor \
9 continueuntil \
10 continueforever \
11 stop \
12 previous \
13 next \
14 variableradixbinary \
15 variableradixhexadecimal \
16 variableradixascii
define show related transactions
define exit noprompt
define event search direction forward
define variable fullhierarchy
define variable nofilenames
define variable nofullpathfilenames
include bookmark with filenames
include scope history without filenames
define waveform window listpane 8.94
define waveform window namepane 15.97
define multivalueindication
define pattern curpos dot
define pattern cursor1 dot
define pattern cursor2 dot
define pattern marker dot
define print designer "Rudolf Usselmann"
define print border
define print color blackonwhite
define print command "/usr/bin/lpr -P%P"
define print printer lp
define print size A4
define print range visible
define print variable visible
define rise fall time low threshold percentage 10
define rise fall time high threshold percentage 90
define rise fall time low value 0
define rise fall time high value 3.3
define sendmail command "/usr/lib/sendmail"
define sequence time width 30.00
define snap
 
define source noprompt
define time units default
define userdefinedbussymbol
define user guide directory "/usr/local/designacc/signalscan-6.5s2/doc/html"
define waveform window grid off
define waveform window waveheight 14
define waveform window wavespace 6
define web browser command netscape
define zoom outfull on initial add off
add group \
A \
test.rst \
test.clk \
 
add group \
USB \
test.tx_dn1 \
test.tx_dp1 \
test.rx_dp1 \
test.rx_dn1 \
 
 
deselect all
create marker Marker1 0ns
open window designbrowser 1 geometry 450 268 1020 752
open window waveform 1 geometry 52 97 1540 1023
zoom at 0(0)ns 0.00004911 0.00000000
/trunk/sim/rtl_sim/run/Makefile
0,0 → 1,99
 
all: sim
SHELL = /bin/sh
#MS=-s
 
##########################################################################
#
# DUT Sources
#
##########################################################################
DUT_SRC_DIR=../../../rtl/verilog
PHY_SRC_DIR=../../../../usb_phy/rtl/verilog
FIFO_SRC_DIR=../../../../generic_fifos/rtl/verilog
GMEM_SRC_DIR=../../../../generic_memories/rtl/verilog
 
#_TARGETS_= $(DUT_SRC_DIR)/usb1_top.v
 
_TARGETS_= $(DUT_SRC_DIR)/usb1_utmi_if.v \
$(DUT_SRC_DIR)/usb1_pl.v \
$(DUT_SRC_DIR)/usb1_pd.v \
$(DUT_SRC_DIR)/usb1_pa.v \
$(DUT_SRC_DIR)/usb1_pe.v \
$(DUT_SRC_DIR)/usb1_idma.v \
$(DUT_SRC_DIR)/usb1_crc5.v \
$(DUT_SRC_DIR)/usb1_crc16.v \
$(DUT_SRC_DIR)/usb1_fifo2.v \
$(DUT_SRC_DIR)/usb1_ctrl.v \
$(DUT_SRC_DIR)/usb1_rom1.v \
$(DUT_SRC_DIR)/usb1_core.v \
\
$(PHY_SRC_DIR)/usb_tx_phy.v \
$(PHY_SRC_DIR)/usb_rx_phy.v \
$(PHY_SRC_DIR)/usb_phy.v \
\
$(FIFO_SRC_DIR)/generic_fifo_sc_a.v \
\
$(GMEM_SRC_DIR)/generic_dpram.v \
\
 
 
 
 
##########################################################################
#
# Test Bench Sources
#
##########################################################################
_TOP_=test
TB_SRC_DIR=../../../bench/verilog
_TB_= $(TB_SRC_DIR)/test_bench_top.v \
 
 
##########################################################################
#
# Misc Variables
#
##########################################################################
 
INCDIR=+incdir+./$(DUT_SRC_DIR)/ +incdir+./$(TB_SRC_DIR)/
LOGF=-l .nclog
 
##########################################################################
#
# Make Targets
#
##########################################################################
 
simw_old:
@$(MAKE) $(MS) sim ACCESS="-ACCESS +r " WAVES="-DEFINE WAVES"
 
ss:
signalscan -do waves/waves.do -waves waves/waves.trn &
 
 
simw:
$(MAKE) $(MS) sim ACCESS="+access+r " WAVES="+define+WAVES"
 
sim:
ncverilog -q +define+RUDIS_TB $(_TARGETS_) $(_TB_) \
$(INCDIR) $(WAVES) $(ACCESS) $(LOGF) +ncstatus \
+ncuid+`hostname`
 
gatew:
@$(MAKE) -s gate ACCESS="+access+r" WAVES="+define+WAVES"
 
gate:
ncverilog -q +define+RUDIS_TB $(_TB_) $(UMC_LIB) \
$(GATE_NETLIST) $(INCDIR) $(WAVES) $(ACCESS) \
$(LOGF) +ncstatus +ncuid+`hostname`
 
simxl:
verilog +incdir+$(DUT_SRC_DIR) +incdir+$(TB_SRC_DIR) \
+access+r +define+WAVES $(_TARGETS_) $(_TB_)
 
clean:
rm -rf ./waves/*.dsn ./waves/*.trn \
INCA_libs ncverilog.key \
./verilog.* .nclog hal.log
 
trunk/sim/rtl_sim/run/Makefile Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/sim/rtl_sim/bin/Makefile =================================================================== --- trunk/sim/rtl_sim/bin/Makefile (nonexistent) +++ trunk/sim/rtl_sim/bin/Makefile (revision 7) @@ -0,0 +1,99 @@ + +all: sim +SHELL = /bin/sh +#MS=-s + +########################################################################## +# +# DUT Sources +# +########################################################################## +DUT_SRC_DIR=../../../rtl/verilog +PHY_SRC_DIR=../../../../usb_phy/rtl/verilog +FIFO_SRC_DIR=../../../../generic_fifos/rtl/verilog +GMEM_SRC_DIR=../../../../generic_memories/rtl/verilog + +#_TARGETS_= $(DUT_SRC_DIR)/usb1_top.v + +_TARGETS_= $(DUT_SRC_DIR)/usb1_utmi_if.v \ + $(DUT_SRC_DIR)/usb1_pl.v \ + $(DUT_SRC_DIR)/usb1_pd.v \ + $(DUT_SRC_DIR)/usb1_pa.v \ + $(DUT_SRC_DIR)/usb1_pe.v \ + $(DUT_SRC_DIR)/usb1_idma.v \ + $(DUT_SRC_DIR)/usb1_crc5.v \ + $(DUT_SRC_DIR)/usb1_crc16.v \ + $(DUT_SRC_DIR)/usb1_fifo2.v \ + $(DUT_SRC_DIR)/usb1_ctrl.v \ + $(DUT_SRC_DIR)/usb1_rom1.v \ + $(DUT_SRC_DIR)/usb1_core.v \ + \ + $(PHY_SRC_DIR)/usb_tx_phy.v \ + $(PHY_SRC_DIR)/usb_rx_phy.v \ + $(PHY_SRC_DIR)/usb_phy.v \ + \ + $(FIFO_SRC_DIR)/generic_fifo_sc_a.v \ + \ + $(GMEM_SRC_DIR)/generic_dpram.v \ + \ + + + + +########################################################################## +# +# Test Bench Sources +# +########################################################################## +_TOP_=test +TB_SRC_DIR=../../../bench/verilog +_TB_= $(TB_SRC_DIR)/test_bench_top.v \ + + +########################################################################## +# +# Misc Variables +# +########################################################################## + +INCDIR=+incdir+./$(DUT_SRC_DIR)/ +incdir+./$(TB_SRC_DIR)/ +LOGF=-l .nclog + +########################################################################## +# +# Make Targets +# +########################################################################## + +simw_old: + @$(MAKE) $(MS) sim ACCESS="-ACCESS +r " WAVES="-DEFINE WAVES" + +ss: + signalscan -do waves/waves.do -waves waves/waves.trn & + + +simw: + $(MAKE) $(MS) sim ACCESS="+access+r " WAVES="+define+WAVES" + +sim: + ncverilog -q +define+RUDIS_TB $(_TARGETS_) $(_TB_) \ + $(INCDIR) $(WAVES) $(ACCESS) $(LOGF) +ncstatus \ + +ncuid+`hostname` + +gatew: + @$(MAKE) -s gate ACCESS="+access+r" WAVES="+define+WAVES" + +gate: + ncverilog -q +define+RUDIS_TB $(_TB_) $(UMC_LIB) \ + $(GATE_NETLIST) $(INCDIR) $(WAVES) $(ACCESS) \ + $(LOGF) +ncstatus +ncuid+`hostname` + +simxl: + verilog +incdir+$(DUT_SRC_DIR) +incdir+$(TB_SRC_DIR) \ + +access+r +define+WAVES $(_TARGETS_) $(_TB_) + +clean: + rm -rf ./waves/*.dsn ./waves/*.trn \ + INCA_libs ncverilog.key \ + ./verilog.* .nclog hal.log +
trunk/sim/rtl_sim/bin/Makefile Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.