OpenCores
URL https://opencores.org/ocsvn/gpio/gpio/trunk

Subversion Repositories gpio

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 62 to Rev 63
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  •

Rev 62 → Rev 63

/trunk/bench/verilog/gpio_testbench.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2003/12/17 13:00:14 gorand
// added ECLK and NEC registers, all tests passed.
//
// Revision 1.1 2003/11/30 12:28:19 gorand
// small "names" modification...
//
98,9 → 101,14
wire gpio_eclk; // GPIO external clock
wire [gw-1:0] gpio_out; // GPIO outputs
wire [gw-1:0] gpio_oen; // GPIO output enables
wire [ 3 : 0 ] tag_o ;
wire [ 3 : 0] tag_o ;
 
//
// description of current test.
//
reg [127:0] text;
 
//
// Instantiation of Clock/Reset Generator
//
clkrst clkrst(
150,13 → 158,18
.wb_inta_o(),
 
// Auxiliary inputs interface
`ifdef GPIO_AUX_IMPLEMENT
.aux_i(gpio_aux),
`endif // GPIO_AUX_IMPLEMENT
 
// External GPIO Interface
.ext_pad_i(gpio_in),
 
`ifdef GPIO_CLKPAD
.clk_pad_i(gpio_eclk),
`endif // GPIO_CLKPAD
.ext_pad_o(gpio_out),
.ext_padoen_o(gpio_oen)
.ext_padoe_o(gpio_oen)
);
 
//
170,4 → 183,7
.gpio_oen(gpio_oen)
);
 
initial
text = " ";
 
endmodule
/trunk/bench/verilog/tb_tasks.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.10 2003/12/17 13:00:14 gorand
// added ECLK and NEC registers, all tests passed.
//
// Revision 1.9 2003/11/30 12:28:19 gorand
// small "names" modification...
//
165,7 → 168,9
input [31:0] val;
 
begin
`ifdef GPIO_RGPIO_AUX
#100 gpio_testbench.wb_master.wr(`GPIO_RGPIO_AUX<<sh_addr, val, 4'b1111);
`endif // GPIO_RGPIO_AUX
end
 
endtask
201,7 → 206,9
input [31:0] val;
 
begin
`ifdef GPIO_RGPIO_ECLK
#100 gpio_testbench.wb_master.wr(`GPIO_RGPIO_ECLK<<sh_addr, val, 4'b1111);
`endif // GPIO_RGPIO_ECLK
end
 
endtask
213,7 → 220,9
input [31:0] val;
 
begin
`ifdef GPIO_RGPIO_NEC
#100 gpio_testbench.wb_master.wr(`GPIO_RGPIO_NEC<<sh_addr, val, 4'b1111);
`endif // GPIO_RGPIO_NEC
end
 
endtask
290,8 → 299,10
 
reg [31:0] tmp;
begin
`ifdef GPIO_RGPIO_AUX
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_AUX<<sh_addr, tmp);
$write(" RGPIO_AUX:%h", tmp);
`endif // GPIO_RGPIO_AUX
end
 
endtask
329,8 → 340,10
 
reg [31:0] tmp;
begin
`ifdef GPIO_RGPIO_ECLK
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_ECLK<<sh_addr, tmp);
$write(" RGPIO_ECLK:%h", tmp);
`endif // GPIO_RGPIO_ECLK
end
 
endtask
342,8 → 355,10
 
reg [31:0] tmp;
begin
`ifdef GPIO_RGPIO_NEC
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_NEC<<sh_addr, tmp);
$write(" RGPIO_NEC:%h", tmp);
`endif // GPIO_RGPIO_NEC
end
 
endtask
436,7 → 451,9
output [31:0] tmp;
 
begin
`ifdef GPIO_RGPIO_AUX
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_AUX<<sh_addr, tmp);
`endif // GPIO_RGPIO_AUX
end
 
endtask
472,7 → 489,9
output [31:0] tmp;
 
begin
`ifdef GPIO_RGPIO_ECLK
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_ECLK<<sh_addr, tmp);
`endif // GPIO_RGPIO_ECLK
end
 
endtask
484,7 → 503,9
output [31:0] tmp;
 
begin
`ifdef GPIO_RGPIO_NEC
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_NEC<<sh_addr, tmp);
`endif // GPIO_RGPIO_NEC
end
 
endtask
575,6 → 596,8
// Wait for WB clock
@(posedge gpio_testbench.clk);
@(posedge gpio_testbench.clk);
@(posedge gpio_testbench.clk);
@(posedge gpio_testbench.clk);
 
// Read RGPIO_IN
getin(l3);
770,7 → 793,7
gpio_testbench.gpio_mon.get_gpiooen(l2);
 
// Compare gpio_oen and RGPIO_OE. Should be exactly opposite.
if (l1 != ~l2)
if (l1 != l2)
err = err + 1;
end
 
784,7 → 807,7
failed;
 
$write(" Testing auxiliary feature ...");
 
`ifdef GPIO_AUX_IMPLEMENT
//
// Phase 7
//
828,6 → 851,10
else
failed;
 
`else
$display(" Not implemented !!");
`endif // GPIO_AUX_IMPLEMENT
 
end
endtask
 
886,6 → 913,8
@(posedge gpio_testbench.clk);
@(posedge gpio_testbench.clk);
@(posedge gpio_testbench.clk);
@(posedge gpio_testbench.clk);
@(posedge gpio_testbench.clk);
 
// Sample interrupt request. Should be one.
l2 = gpio_testbench.gpio_top.wb_inta_o;
979,6 → 1008,8
@(posedge gpio_testbench.clk);
@(posedge gpio_testbench.clk);
@(posedge gpio_testbench.clk);
@(posedge gpio_testbench.clk);
@(posedge gpio_testbench.clk);
 
// Sample interrupt request. Should be one.
l2 = gpio_testbench.gpio_top.wb_inta_o;
1038,18 → 1069,42
ints_working = 0;
gpio_testbench.gpio_mon.set_gpioin(0);
gpio_testbench.gpio_mon.set_gpioaux(0);
gpio_testbench.gpio_mon.set_gpioeclk(0);
gpio_testbench.gpio_mon.set_gpioeclk(0);
$display;
$display("###");
$display("### GPIO IP Core Verification ###");
$display("###");
 
`ifdef GPIO_IMPLEMENTED
 
$display;
$display("I. Testing correct operation of RGPIO_CTRL control bits");
$display;
 
 
$write(" Testing control bit RGPIO_CTRL[ECLK] ...");
local_errs = 0;
#1
 
gpio_testbench.text = "Test INTS";
test_ints;
 
$display;
$display("II. Testing modes of operation ...");
$display;
 
gpio_testbench.text = "Test simple";
test_simple;
gpio_testbench.text = "Test ptrig";
test_ptrig;
 
 
$display;
$display("III. Testing registers external clock");
$display;
 
`ifdef GPIO_CLKPAD
$write(" Testing control register ECLK ...");
gpio_testbench.text = "Test ECLK";
for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1)
test_eclk;
if (local_errs == 0)
1057,9 → 1112,9
else
failed;
 
 
$write(" Testing control bit RGPIO_CTRL[NEC] ...");
$write(" Testing control register NEC ...");
local_errs = 0;
gpio_testbench.text = "Test NEC";
for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1)
test_nec;
if (local_errs == 0)
1066,21 → 1121,24
$display(" OK");
else
failed;
`else
$display(" External clock not enabled!!");
`endif // GPIO_CLKPAD
 
test_ints;
 
$display;
$display("II. Testing modes of operation ...");
$display("###");
$display("### FAILED TESTS: %d ###", nr_failed);
$display("###");
$display;
 
test_simple;
test_ptrig;
`else
 
$display;
$display("###");
$display("### FAILED TESTS: %d ###", nr_failed);
$display("### GPIO not implemented ");
$display("###");
$display;
nr_failed = 1;
 
`endif // GPIO_IMPLEMENTED
// $finish;
if ( nr_failed == 0 )
begin

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