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    from Rev 64 to Rev 65
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Rev 64 → Rev 65

/trunk/rtl/verilog/mgmt/manage_registers.v
68,7 → 68,7
output[1:0] mdio_opcode; //MDIO Opcode, equals mgmt_opcode
output mdio_out_valid; //Indicate mdio_data_out is valid
output[41:0] mdio_data_out; //Data to be writen to MDIO, {addr, data}
input[31:0] mdio_data_in; //Data read from MDIO
input[15:0] mdio_data_in; //Data read from MDIO
input mdio_in_valid; //Indicate mdio_data_in read from MDIO is valid
output[31:0] mgmt_config; //management configuration data, mainly used to set mdc frequency
 
503,7 → 503,7
else begin
case (state)
IDLE: begin
mgmt_rd_data <=#TP 0;
mgmt_rd_data <=#TP mgmt_rd_data;
data_sel <=#TP 1'b0;
read_done <=#TP 0;
mgmt_miim_rdy <=#TP 1;
535,11 → 535,12
end
MDIO_OPERATE: begin
if(~mdio_in_valid & mdio_in_valid_d1) begin
mgmt_rd_data <=#TP mdio_data_in;
mgmt_rd_data[15:0] <=#TP mdio_data_in;
mgmt_rd_data[31:16] <=#TP 0;
mgmt_miim_rdy <=#TP 1'b1;
end
else begin
mgmt_rd_data <=#TP 0;
mgmt_rd_data <=#TP mgmt_rd_data;
mgmt_miim_rdy <=#TP 1'b0;
end
end
621,15 → 622,28
mdio_opcode <=#TP mgmt_opcode;
end
 
reg[4:0] tmp_cnt;
always@(posedge mgmt_clk or posedge reset) begin
if(reset)
tmp_cnt <=#TP 0;
else if(mgmt_req & mgmt_miim_sel)
tmp_cnt <=#TP 0;
else if(tmp_cnt == 30)
tmp_cnt <=#TP tmp_cnt;
else
tmp_cnt <=#TP tmp_cnt + 1;
end
 
reg mdio_out_valid;
 
always@(posedge mgmt_clk or posedge reset) begin
if(reset)
mdio_out_valid <=#TP 0;
else if(mgmt_req & mgmt_miim_sel)
mdio_out_valid <=#TP 1'b1;
else if(tmp_cnt ==30)
mdio_out_valid <=#TP 1'b0;
else
mdio_out_valid <=#TP 1'b0;
mdio_out_valid <= #TP mdio_out_valid;
end
 
endmodule
/trunk/rtl/verilog/mgmt/mdio.v
48,7 → 48,7
//////////////////////////////////////////////////////////////////////
 
`define PRE 31'h7fffffff
`define ST 2'b00
`define ST 2'b01
`define TA 2'b10
 
module mdio(mgmt_clk, reset, mdc, mdio_t, mdio_i, mdio_o, mdio_opcode, mdio_in_valid, mdio_data_in, mdio_out_valid, mdio_data_out, mgmt_config);
188,7 → 188,7
always@(posedge mdc or posedge reset)begin
if(reset) begin
mdio_o <=#TP 0;
mdio_t <=#TP 1;
mdio_t <=#TP 0;
transmitting <=#TP 0;
receiving <=#TP 0;
end
195,8 → 195,8
else begin
case (state)
IDLE:begin
mdio_o <=#TP 0;
mdio_t <=#TP 1;
mdio_o <=#TP 1'b1;
mdio_t <=#TP 0;
receiving <=#TP 0;
transmitting <=#TP 0;
end
211,7 → 211,9
end
MDIO_READ:begin
mdio_o <=#TP mdio_data_reg[62];
mdio_t <=#TP 1'b0;
transmitting <=#TP 1'b1;
receiving <=#TP 0;
if (trans_cnt <45) begin //transmitting PRE, ST, OP, ADDR
mdio_t <=#TP 1'b0;
receiving <=#TP 1'b0;
220,11 → 222,18
mdio_t <=#TP 1'b1;
receiving <=#TP 1'b0;
end
// else if (trans_cnt == 46)begin //transmitting TA
// mdio_t <=#TP 1'b0;
// receiving <=#TP 1'b0;
// end
else if (trans_cnt == 63)begin //all data received
receiving <=#TP 0;
transmitting <=#TP 1'b0;
mdio_t <=#TP 1'b0;
mdio_o <=#TP 1'b1;
end
else if(trans_cnt >= 46)begin //receiving Data
mdio_t <=#TP 1'b0;
mdio_t <=#TP 1'b1;
receiving <=#TP 1'b1;
end
end

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