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URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

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    from Rev 65 to Rev 66
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Rev 65 → Rev 66

/trunk/rtl/verilog/uart_regs.v
62,6 → 62,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.35 2001/12/19 08:03:34 mohor
// Warnings cleared.
//
// Revision 1.34 2001/12/19 07:33:54 mohor
// Synplicity was having troubles with the comment.
//
331,7 → 334,7
 
// Receiver Instance
uart_receiver receiver(clk, wb_rst_i, lcr, rf_pop, srx_pad_i, enable,
counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push);
counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse);
 
 
// Asynchronous reading here because the outputs are sampled in uart_wb.v file
524,7 → 527,7
// Line Status Register
 
// activation conditions
assign lsr0 = (rf_count==0 && rf_push); // data in receiver fifo available set condition
assign lsr0 = (rf_count==0 && rf_push_pulse); // data in receiver fifo available set condition
assign lsr1 = rf_overrun; // Receiver overrun error
assign lsr2 = rf_data_out[1]; // parity error bit
assign lsr3 = rf_data_out[0]; // framing error bit
/trunk/rtl/verilog/uart_fifo.v
64,6 → 64,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.15 2001/12/18 09:01:07 mohor
// Bug that was entered in the last update fixed (rx state machine).
//
// Revision 1.14 2001/12/17 14:46:48 mohor
// overrun signal was moved to separate block because many sequential lsr
// reads were preventing data from being written to rx fifo.
168,35 → 171,8
reg [fifo_counter_w-1:0] count;
reg overrun;
 
// These registers and signals are to detect rise of of the signals.
// Not that it slows the maximum rate by 2, meaning you must reset the signals and then
// assert them again for the operation to repeat
// This is done to accomodate wait states
reg push_delay;
reg pop_delay;
 
wire push_rise = push_delay & push;
wire pop_rise = pop_delay & pop;
 
wire [fifo_pointer_w-1:0] top_plus_1 = top + 1'b1;
 
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
push_delay <= #1 1'b0;
else
push_delay <= #1 ~push;
end
 
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
pop_delay <= #1 1'b0;
else
pop_delay <= #1 ~pop;
end
 
 
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
begin
if (wb_rst_i)
229,7 → 205,7
end
else
begin
case ({push_rise, pop_rise})
case ({push, pop})
2'b10 : if (count<fifo_depth) // overrun condition
begin
top <= #1 top_plus_1;
261,7 → 237,7
if(fifo_reset | reset_status)
overrun <= #1 1'b0;
else
if(push_rise & (count==fifo_depth))
if(push & (count==fifo_depth))
overrun <= #1 1'b1;
end // always
 
/trunk/rtl/verilog/uart_receiver.v
63,6 → 63,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.24 2001/12/19 08:03:34 mohor
// Warnings cleared.
//
// Revision 1.23 2001/12/19 07:33:54 mohor
// Synplicity was having troubles with the comment.
//
164,7 → 167,7
`include "uart_defines.v"
 
module uart_receiver (clk, wb_rst_i, lcr, rf_pop, srx_pad_i, enable,
counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push);
counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse);
 
input clk;
input wb_rst_i;
181,7 → 184,7
output rf_overrun;
output rf_error_bit;
output [3:0] rstate;
output rf_push;
output rf_push_pulse;
 
reg [3:0] rstate;
reg [3:0] rcounter16;
197,6 → 200,7
// RX FIFO signals
reg [`UART_FIFO_REC_WIDTH-1:0] rf_data_in;
wire [`UART_FIFO_REC_WIDTH-1:0] rf_data_out;
wire rf_push_pulse;
reg rf_push;
wire rf_pop;
wire rf_overrun;
210,7 → 214,7
.wb_rst_i( wb_rst_i ),
.data_in( rf_data_in ),
.data_out( rf_data_out ),
.push( rf_push ),
.push( rf_push_pulse ),
.pop( rf_pop ),
.overrun( rf_overrun ),
.count( rf_count ),
392,6 → 396,17
end // if (enable)
end // always of receiver
 
always @ (posedge clk or posedge wb_rst_i)
begin
if(wb_rst_i)
rf_push_q <= 0;
else
rf_push_q <= #1 rf_push;
end
 
assign rf_push_pulse = rf_push & ~rf_push_q;
 
//
// Break condition detection.
// Works in conjuction with the receiver state machine
438,7 → 453,7
if (wb_rst_i)
counter_t <= #1 10'd639; // 10 bits for the default 8N1
else
if(rf_push || rf_pop || rf_count == 0) // counter is reset when RX FIFO is empty, accessed or above trigger level
if(rf_push_pulse || rf_pop || rf_count == 0) // counter is reset when RX FIFO is empty, accessed or above trigger level
counter_t <= #1 toc_value;
else
if (enable && counter_t != 10'b0) // we don't want to underflow

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