URL
https://opencores.org/ocsvn/ac97/ac97/trunk
Subversion Repositories ac97
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- This comparison shows the changes necessary to convert path
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- from Rev 7 to Rev 8
- ↔ Reverse comparison
Rev 7 → Rev 8
/trunk/sim/rtl_sim/bin/Makefile
0,0 → 1,133
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all: sim |
SHELL = /bin/sh |
MS="-s" |
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########################################################################## |
# |
# DUT Sources |
# |
########################################################################## |
DUT_SRC_DIR=../../../rtl/verilog |
_TARGETS_= $(DUT_SRC_DIR)/ac97_top.v \ |
$(DUT_SRC_DIR)/ac97_sout.v \ |
$(DUT_SRC_DIR)/ac97_sin.v \ |
$(DUT_SRC_DIR)/ac97_soc.v \ |
$(DUT_SRC_DIR)/ac97_out_fifo.v \ |
$(DUT_SRC_DIR)/ac97_in_fifo.v \ |
$(DUT_SRC_DIR)/ac97_wb_if.v \ |
$(DUT_SRC_DIR)/ac97_rf.v \ |
$(DUT_SRC_DIR)/ac97_prc.v \ |
$(DUT_SRC_DIR)/ac97_fifo_ctrl.v \ |
$(DUT_SRC_DIR)/ac97_cra.v \ |
$(DUT_SRC_DIR)/ac97_dma_if.v \ |
$(DUT_SRC_DIR)/ac97_dma_req.v \ |
$(DUT_SRC_DIR)/ac97_int.v \ |
$(DUT_SRC_DIR)/ac97_rst.v |
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########################################################################## |
# |
# Test Bench Sources |
# |
########################################################################## |
_TOP_=test |
TB_SRC_DIR=../../../bench/verilog |
_TB_= $(TB_SRC_DIR)/ac97_codec_sout.v \ |
$(TB_SRC_DIR)/ac97_codec_sin.v \ |
$(TB_SRC_DIR)/ac97_codec_top.v \ |
$(TB_SRC_DIR)/test_bench_top.v \ |
$(TB_SRC_DIR)/wb_mast_model.v |
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########################################################################## |
# |
# Misc Variables |
# |
########################################################################## |
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INCDIR="-INCDIR ./$(DUT_SRC_DIR)/ -INCDIR ./$(TB_SRC_DIR)/" |
LOGF=-LOGFILE .nclog |
NCCOMMON=-CDSLIB ncwork/cds.lib -HDLVAR ncwork/hdl.var -NOCOPYRIGHT |
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########################################################################## |
# |
# Make Targets |
# |
########################################################################## |
simw: |
@$(MAKE) -s sim ACCESS="-ACCESS +r " WAVES="-DEFINE WAVES" |
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ss: |
signalscan -do waves/waves.do -waves waves/waves.trn & |
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simxl: |
verilog +incdir+$(DUT_SRC_DIR) +incdir+$(TB_SRC_DIR) \ |
$(_TARGETS_) $(_TB_) |
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sim: |
@echo "" |
@echo "----- Running NCVLOG ... ----------" |
@$(MAKE) $(MS) vlog \ |
TARGETS="$(_TARGETS_)" \ |
TB="$(_TB_)" \ |
INCDIR=$(INCDIR) \ |
WAVES="$(WAVES)" |
@echo "" |
@echo "----- Running NCELAB ... ----------" |
@$(MAKE) $(MS) elab \ |
ACCESS="$(ACCESS)" TOP=$(_TOP_) |
@echo "" |
@echo "----- Running NCSIM ... ----------" |
@$(MAKE) $(MS) ncsim TOP=$(_TOP_) |
@echo "" |
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hal: |
@echo "" |
@echo "----- Running HAL ... ----------" |
@hal +incdir+$(DUT_SRC_DIR) \ |
-NOP -NOS -nocheck STYVAL:USEPRT:NOBLKN:DLNBLK \ |
$(_TARGETS_) |
@echo "----- DONE ... ----------" |
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clean: |
rm -rf ./waves/*.dsn ./waves/*.trn \ |
ncwork/.inc* ncwork/inc* \ |
./verilog.* .nclog hal.log |
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########################################################################## |
# |
# NCVLOG |
# |
########################################################################## |
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vhdl: |
ncvhdl $(NCCOMMON) $(LOGF) -APPEND_LOG \ |
-WORK count -V93 hdl/counter.vhd |
ncvhdl $(NCCOMMON) $(LOGF) -APPEND_LOG \ |
-WORK work -V93 $(TARGETS) |
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vlog: |
ncvlog $(NCCOMMON) $(LOGF) \ |
-WORK work $(WAVES) $(TB) $(TARGETS) $(INCDIR) |
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########################################################################## |
# |
# NCELAB |
# |
########################################################################## |
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elab: |
ncelab $(NCCOMMON) $(LOGF) -APPEND_LOG \ |
-WORK work $(ACCESS) -NOTIMINGCHECKS \ |
work.$(TOP) |
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########################################################################## |
# |
# NCSIM |
# |
########################################################################## |
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ncsim: |
ncsim $(NCCOMMON) $(LOGF) -APPEND_LOG \ |
-EXIT -ERRORMAX 10 work.$(TOP) |
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trunk/sim/rtl_sim/bin/Makefile
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property