OpenCores
URL https://opencores.org/ocsvn/camellia-vhdl/camellia-vhdl/trunk

Subversion Repositories camellia-vhdl

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 7 to Rev 8
    ↔ Reverse comparison
  •

Rev 7 → Rev 8

/trunk/pipelining/vcom.do File deleted
/trunk/pipelining/sbox4.vhd
3,7 → 3,7
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 09/14/2007
-- Last Update: 04/09/2008
-- Last Update: 04/14/2008
-- Project Name: camellia-vhdl
-- Description: Dual-port SBOX4
--
63,8 → 63,8
port map(s1_clk, s1_addra, s1_addrb, s1_douta, s1_doutb);
 
s1_clk <= clk;
s1_addra <= addra;
s1_addrb <= addrb;
s1_addra <= addra(1 to 7) & addra(0);
s1_addrb <= addrb(1 to 7) & addrb(0);
 
douta <= s1_douta;
doutb <= s1_doutb;
/trunk/pipelining/camellia128.vhd
3,7 → 3,7
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 09/14/2007
-- Last Update: 04/09/2008
-- Last Update: 04/14/2008
-- Project Name: camellia-vhdl
-- Description: Camellia top level module, only for 128-bit key en/decryption
--
454,80 → 454,32
reg_k <= (others=>'0');
reg_dec <= '0';
reg_rdy <= '0';
--reg_a1_m <= (others=>'0');
--reg_a1_dec <= '0';
reg_a1_rdy <= '0';
--reg_a2_m <= (others=>'0');
--reg_a2_dec <= '0';
reg_a2_rdy <= '0';
--reg_a3_m <= (others=>'0');
--reg_a3_dec <= '0';
reg_a3_rdy <= '0';
--reg_a4_m <= (others=>'0');
--reg_a4_dec <= '0';
reg_a4_rdy <= '0';
--reg_b1_dec <= '0';
--reg_b1_k <= (others=>'0');
reg_b1_rdy <= '0';
--reg_b2_dec <= '0';
--reg_b2_k <= (others=>'0');
reg_b2_rdy <= '0';
--reg_b3_dec <= '0';
--reg_b3_k <= (others=>'0');
reg_b3_rdy <= '0';
--reg_b4_dec <= '0';
--reg_b4_k <= (others=>'0');
reg_b4_rdy <= '0';
--reg_b5_dec <= '0';
--reg_b5_k <= (others=>'0');
reg_b5_rdy <= '0';
--reg_b6_dec <= '0';
--reg_b6_k <= (others=>'0');
reg_b6_rdy <= '0';
--reg_b7_dec <= '0';
--reg_b7_k <= (others=>'0');
reg_b7_rdy <= '0';
--reg_b8_dec <= '0';
--reg_b8_k <= (others=>'0');
reg_b8_rdy <= '0';
--reg_b9_dec <= '0';
--reg_b9_k <= (others=>'0');
reg_b9_rdy <= '0';
--reg_b10_dec <= '0';
--reg_b10_k <= (others=>'0');
reg_b10_rdy <= '0';
--reg_b11_dec <= '0';
--reg_b11_k <= (others=>'0');
reg_b11_rdy <= '0';
--reg_b12_dec <= '0';
--reg_b12_k <= (others=>'0');
reg_b12_rdy <= '0';
--reg_b13_dec <= '0';
--reg_b13_k <= (others=>'0');
reg_b13_rdy <= '0';
--reg_b14_dec <= '0';
--reg_b14_k <= (others=>'0');
reg_b14_rdy <= '0';
--reg_b15_dec <= '0';
--reg_b15_k <= (others=>'0');
reg_b15_rdy <= '0';
--reg_b16_dec <= '0';
--reg_b16_k <= (others=>'0');
reg_b16_rdy <= '0';
--reg_b17_dec <= '0';
--reg_b17_k <= (others=>'0');
reg_b17_rdy <= '0';
--reg_b18_dec <= '0';
--reg_b18_k <= (others=>'0');
reg_b18_rdy <= '0';
--reg_b19_dec <= '0';
--reg_b19_k <= (others=>'0');
reg_b19_rdy <= '0';
--reg_b20_dec <= '0';
--reg_b20_k <= (others=>'0');
reg_b20_rdy <= '0';
output_rdy <= '0';
elsif( rising_edge(clk)) then
elsif(rising_edge(clk)) then
reg_m <= input;
reg_k <= key;
reg_dec <= enc_dec;
/trunk/pipelining/camellia256.vhd
3,7 → 3,7
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 09/15/2007
-- Last Update: 04/09/2008
-- Last Update: 06/23/2008
-- Project Name: camellia-vhdl
-- Description: Camellia top level module, for 128/192/256-bit keys
--
31,13 → 31,15
 
entity CAMELLIA256 is
port(
reset : in STD_LOGIC;
clk : in STD_LOGIC;
m : in STD_LOGIC_VECTOR (0 to 127); -- input data
k : in STD_LOGIC_VECTOR (0 to 255); -- key
k_len : in STD_LOGIC_VECTOR (0 to 1); -- key lenght
dec : in STD_LOGIC; -- dec=0 enc, dec=1 dec
c : out STD_LOGIC_VECTOR (0 to 127) -- en/decrypted data
reset : in STD_LOGIC;
clk : in STD_LOGIC;
input : in STD_LOGIC_VECTOR (0 to 127); -- input data
input_en : in STD_LOGIC; -- input enable
key : in STD_LOGIC_VECTOR (0 to 255); -- key
key_len : in STD_LOGIC_VECTOR (0 to 1); -- key lenght
enc_dec : in STD_LOGIC; -- dec=0 enc, dec=1 dec
output : out STD_LOGIC_VECTOR (0 to 127); -- en/decrypted data
output_rdy : out STD_LOGIC -- output ready
);
end CAMELLIA256;
 
174,6 → 176,7
signal reg_kr_int : STD_LOGIC_VECTOR (0 to 127);
signal reg_k_len : STD_LOGIC_VECTOR (0 to 1);
signal reg_dec : STD_LOGIC;
signal reg_rdy : STD_LOGIC;
 
-- used by pre-whitening
signal kw1_enc : STD_LOGIC_VECTOR (0 to 63);
207,104 → 210,137
signal reg_a1_m : STD_LOGIC_VECTOR (0 to 127);
signal reg_a1_dec : STD_LOGIC;
signal reg_a1_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_a1_rdy : STD_LOGIC;
signal reg_a2_m : STD_LOGIC_VECTOR (0 to 127);
signal reg_a2_dec : STD_LOGIC;
signal reg_a2_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_a2_rdy : STD_LOGIC;
signal reg_a3_m : STD_LOGIC_VECTOR (0 to 127);
signal reg_a3_dec : STD_LOGIC;
signal reg_a3_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_a3_rdy : STD_LOGIC;
signal reg_a4_m : STD_LOGIC_VECTOR (0 to 127);
signal reg_a4_dec : STD_LOGIC;
signal reg_a4_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_a4_rdy : STD_LOGIC;
signal reg_a5_m : STD_LOGIC_VECTOR (0 to 127);
signal reg_a5_dec : STD_LOGIC;
signal reg_a5_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_a5_rdy : STD_LOGIC;
signal reg_a6_m : STD_LOGIC_VECTOR (0 to 127);
signal reg_a6_dec : STD_LOGIC;
signal reg_a6_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_a6_rdy : STD_LOGIC;
 
-- registers used during 6-rounds and fls
signal reg_b1_dec : STD_LOGIC;
signal reg_b1_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b1_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b2_dec : STD_LOGIC;
signal reg_b2_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b2_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b3_dec : STD_LOGIC;
signal reg_b3_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b3_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b4_dec : STD_LOGIC;
signal reg_b4_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b4_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b5_dec : STD_LOGIC;
signal reg_b5_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b5_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b6_dec : STD_LOGIC;
signal reg_b6_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b6_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b7_dec : STD_LOGIC;
signal reg_b7_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b7_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b8_dec : STD_LOGIC;
signal reg_b8_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b8_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b9_dec : STD_LOGIC;
signal reg_b9_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b9_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b1_dec : STD_LOGIC;
signal reg_b1_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b1_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b1_rdy : STD_LOGIC;
signal reg_b2_dec : STD_LOGIC;
signal reg_b2_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b2_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b2_rdy : STD_LOGIC;
signal reg_b3_dec : STD_LOGIC;
signal reg_b3_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b3_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b3_rdy : STD_LOGIC;
signal reg_b4_dec : STD_LOGIC;
signal reg_b4_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b4_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b4_rdy : STD_LOGIC;
signal reg_b5_dec : STD_LOGIC;
signal reg_b5_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b5_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b5_rdy : STD_LOGIC;
signal reg_b6_dec : STD_LOGIC;
signal reg_b6_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b6_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b6_rdy : STD_LOGIC;
signal reg_b7_dec : STD_LOGIC;
signal reg_b7_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b7_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b7_rdy : STD_LOGIC;
signal reg_b8_dec : STD_LOGIC;
signal reg_b8_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b8_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b8_rdy : STD_LOGIC;
signal reg_b9_dec : STD_LOGIC;
signal reg_b9_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b9_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b9_rdy : STD_LOGIC;
signal reg_b10_dec : STD_LOGIC;
signal reg_b10_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b10_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b10_rdy : STD_LOGIC;
signal reg_b11_dec : STD_LOGIC;
signal reg_b11_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b11_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b11_rdy : STD_LOGIC;
signal reg_b12_dec : STD_LOGIC;
signal reg_b12_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b12_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b12_rdy : STD_LOGIC;
signal reg_b13_dec : STD_LOGIC;
signal reg_b13_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b13_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b13_rdy : STD_LOGIC;
signal reg_b14_dec : STD_LOGIC;
signal reg_b14_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b14_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b14_rdy : STD_LOGIC;
signal reg_b15_dec : STD_LOGIC;
signal reg_b15_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b15_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b15_rdy : STD_LOGIC;
signal reg_b16_dec : STD_LOGIC;
signal reg_b16_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b16_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b16_rdy : STD_LOGIC;
signal reg_b17_dec : STD_LOGIC;
signal reg_b17_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b17_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b17_rdy : STD_LOGIC;
signal reg_b18_dec : STD_LOGIC;
signal reg_b18_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b18_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b18_rdy : STD_LOGIC;
signal reg_b19_dec : STD_LOGIC;
signal reg_b19_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b19_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b19_rdy : STD_LOGIC;
signal reg_b20_dec : STD_LOGIC;
signal reg_b20_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b20_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b20_rdy : STD_LOGIC;
signal reg_b21_dec : STD_LOGIC;
signal reg_b21_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b21_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b21_rdy : STD_LOGIC;
signal reg_b22_dec : STD_LOGIC;
signal reg_b22_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b22_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b22_rdy : STD_LOGIC;
signal reg_b23_dec : STD_LOGIC;
signal reg_b23_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b23_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b23_rdy : STD_LOGIC;
signal reg_b24_dec : STD_LOGIC;
signal reg_b24_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b24_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b24_rdy : STD_LOGIC;
signal reg_b25_dec : STD_LOGIC;
signal reg_b25_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b25_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b25_rdy : STD_LOGIC;
signal reg_b26_dec : STD_LOGIC;
signal reg_b26_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b26_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b26_rdy : STD_LOGIC;
signal reg_b27_dec : STD_LOGIC;
signal reg_b27_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b27_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b27_rdy : STD_LOGIC;
 
-- registers used for 128bit key encryptions
signal reg_l128_1 : STD_LOGIC_VECTOR (0 to 63);
350,7 → 386,7
 
begin
 
KEY: KEYSCHED256
KEY_SCHED: KEYSCHED256
PORT MAP (
reset => reset,
clk => clk,
775,228 → 811,184
reg_kl <= (others=>'0');
reg_kr_int <= (others=>'0');
reg_k_len <= (others=>'0');
 
reg_dec <= '0';
c <= (others=>'0');
reg_a1_m <= (others=>'0');
reg_a1_dec <= '0';
reg_a1_klen <= "00";
reg_a2_m <= (others=>'0');
reg_a2_dec <= '0';
reg_a2_klen <= "00";
reg_a3_m <= (others=>'0');
reg_a3_dec <= '0';
reg_a3_klen <= "00";
reg_a4_m <= (others=>'0');
reg_a4_dec <= '0';
reg_a4_klen <= "00";
reg_a5_m <= (others=>'0');
reg_a5_dec <= '0';
reg_a5_klen <= "00";
reg_a6_m <= (others=>'0');
reg_a6_dec <= '0';
reg_a6_klen <= "00";
reg_b1_dec <= '0';
reg_b1_k <= (others=>'0');
reg_b1_klen <= "00";
reg_b2_dec <= '0';
reg_b2_k <= (others=>'0');
reg_b2_klen <= "00";
reg_b3_dec <= '0';
reg_b3_k <= (others=>'0');
reg_b3_klen <= "00";
reg_b4_dec <= '0';
reg_b4_k <= (others=>'0');
reg_b4_klen <= "00";
reg_b5_dec <= '0';
reg_b5_k <= (others=>'0');
reg_b5_klen <= "00";
reg_b6_dec <= '0';
reg_b6_k <= (others=>'0');
reg_b6_klen <= "00";
reg_b7_dec <= '0';
reg_b7_k <= (others=>'0');
reg_b7_klen <= "00";
reg_b8_dec <= '0';
reg_b8_k <= (others=>'0');
reg_b8_klen <= "00";
reg_b9_dec <= '0';
reg_b9_k <= (others=>'0');
reg_b9_klen <= "00";
reg_b10_dec <= '0';
reg_b10_k <= (others=>'0');
reg_b10_klen <= "00";
reg_b11_dec <= '0';
reg_b11_k <= (others=>'0');
reg_b11_klen <= "00";
reg_b12_dec <= '0';
reg_b12_k <= (others=>'0');
reg_b12_klen <= "00";
reg_b13_dec <= '0';
reg_b13_k <= (others=>'0');
reg_b13_klen <= "00";
reg_b14_dec <= '0';
reg_b14_k <= (others=>'0');
reg_b14_klen <= "00";
reg_b15_dec <= '0';
reg_b15_k <= (others=>'0');
reg_b15_klen <= "00";
reg_b16_dec <= '0';
reg_b16_k <= (others=>'0');
reg_b16_klen <= "00";
reg_b17_dec <= '0';
reg_b17_k <= (others=>'0');
reg_b17_klen <= "00";
reg_b18_dec <= '0';
reg_b18_k <= (others=>'0');
reg_b18_klen <= "00";
reg_b19_dec <= '0';
reg_b19_k <= (others=>'0');
reg_b19_klen <= "00";
reg_b20_dec <= '0';
reg_b20_k <= (others=>'0');
reg_b20_klen <= "00";
reg_b21_dec <= '0';
reg_b21_k <= (others=>'0');
reg_b21_klen <= "00";
reg_b22_dec <= '0';
reg_b22_k <= (others=>'0');
reg_b22_klen <= "00";
reg_b23_dec <= '0';
reg_b23_k <= (others=>'0');
reg_b23_klen <= "00";
reg_b24_dec <= '0';
reg_b24_k <= (others=>'0');
reg_b24_klen <= "00";
reg_b25_dec <= '0';
reg_b25_k <= (others=>'0');
reg_b25_klen <= "00";
reg_b26_dec <= '0';
reg_b26_k <= (others=>'0');
reg_b26_klen <= "00";
reg_b27_dec <= '0';
reg_b27_k <= (others=>'0');
reg_b27_klen <= "00";
reg_l128_1 <= (others=>'0');
reg_r128_1 <= (others=>'0');
reg_l128_2 <= (others=>'0');
reg_r128_2 <= (others=>'0');
reg_l128_3 <= (others=>'0');
reg_r128_3 <= (others=>'0');
reg_l128_4 <= (others=>'0');
reg_r128_4 <= (others=>'0');
reg_l128_5 <= (others=>'0');
reg_r128_5 <= (others=>'0');
reg_l128_6 <= (others=>'0');
reg_r128_6 <= (others=>'0');
reg_l128_7 <= (others=>'0');
reg_r128_7 <= (others=>'0');
elsif( rising_edge(clk)) then
reg_m <= m;
reg_kl <= k(0 to 127);
reg_rdy <= '0';
reg_a1_rdy <= '0';
reg_a2_rdy <= '0';
reg_a3_rdy <= '0';
reg_a4_rdy <= '0';
reg_a5_rdy <= '0';
reg_a6_rdy <= '0';
reg_b1_rdy <= '0';
reg_b2_rdy <= '0';
reg_b3_rdy <= '0';
reg_b4_rdy <= '0';
reg_b5_rdy <= '0';
reg_b6_rdy <= '0';
reg_b7_rdy <= '0';
reg_b8_rdy <= '0';
reg_b9_rdy <= '0';
reg_b10_rdy <= '0';
reg_b11_rdy <= '0';
reg_b12_rdy <= '0';
reg_b13_rdy <= '0';
reg_b14_rdy <= '0';
reg_b15_rdy <= '0';
reg_b16_rdy <= '0';
reg_b17_rdy <= '0';
reg_b18_rdy <= '0';
reg_b19_rdy <= '0';
reg_b20_rdy <= '0';
reg_b21_rdy <= '0';
reg_b22_rdy <= '0';
reg_b23_rdy <= '0';
reg_b24_rdy <= '0';
reg_b25_rdy <= '0';
reg_b26_rdy <= '0';
reg_b27_rdy <= '0';
output_rdy <= '0';
elsif(rising_edge(clk)) then
reg_m <= input;
reg_kl <= key(0 to 127);
reg_kr_int <= kr_int;
reg_dec <= dec;
reg_k_len <= k_len;
reg_dec <= enc_dec;
reg_k_len <= key_len;
reg_rdy <= input_en;
 
reg_a1_m <= reg_m;
reg_a1_dec <= reg_dec;
reg_a1_klen <= reg_k_len;
reg_a1_rdy <= reg_rdy;
reg_a2_m <= reg_a1_m;
reg_a2_dec <= reg_a1_dec;
reg_a2_klen <= reg_a1_klen;
reg_a2_rdy <= reg_a1_rdy;
reg_a3_m <= reg_a2_m;
reg_a3_dec <= reg_a2_dec;
reg_a3_klen <= reg_a2_klen;
reg_a3_rdy <= reg_a2_rdy;
reg_a4_m <= reg_a3_m;
reg_a4_dec <= reg_a3_dec;
reg_a4_klen <= reg_a3_klen;
reg_a4_rdy <= reg_a3_rdy;
reg_a5_m <= reg_a4_m;
reg_a5_dec <= reg_a4_dec;
reg_a5_klen <= reg_a4_klen;
reg_a5_rdy <= reg_a4_rdy;
reg_a6_m <= reg_a5_m;
reg_a6_dec <= reg_a5_dec;
reg_a6_klen <= reg_a5_klen;
reg_a6_rdy <= reg_a5_rdy;
 
reg_b1_dec <= reg_a6_dec;
reg_b1_k <= out_ksched;
reg_b1_klen <= reg_a6_klen;
reg_b1_rdy <= reg_a6_rdy;
reg_b2_dec <= reg_b1_dec;
reg_b2_k <= reg_b1_k;
reg_b2_klen <= reg_b1_klen;
reg_b2_rdy <= reg_b1_rdy;
reg_b3_dec <= reg_b2_dec;
reg_b3_k <= reg_b2_k;
reg_b3_klen <= reg_b2_klen;
reg_b3_rdy <= reg_b2_rdy;
reg_b4_dec <= reg_b3_dec;
reg_b4_k <= reg_b3_k;
reg_b4_klen <= reg_b3_klen;
reg_b4_rdy <= reg_b3_rdy;
reg_b5_dec <= reg_b4_dec;
reg_b5_k <= reg_b4_k;
reg_b5_klen <= reg_b4_klen;
reg_b5_rdy <= reg_b4_rdy;
reg_b6_dec <= reg_b5_dec;
reg_b6_k <= reg_b5_k;
reg_b6_klen <= reg_b5_klen;
reg_b6_rdy <= reg_b5_rdy;
reg_b7_dec <= reg_b6_dec;
reg_b7_k <= reg_b6_k;
reg_b7_klen <= reg_b6_klen;
reg_b7_rdy <= reg_b6_rdy;
reg_b8_dec <= reg_b7_dec;
reg_b8_k <= reg_b7_k;
reg_b8_klen <= reg_b7_klen;
reg_b8_rdy <= reg_b7_rdy;
reg_b9_dec <= reg_b8_dec;
reg_b9_k <= reg_b8_k;
reg_b9_klen <= reg_b8_klen;
reg_b9_rdy <= reg_b8_rdy;
reg_b10_dec <= reg_b9_dec;
reg_b10_k <= reg_b9_k;
reg_b10_klen <= reg_b9_klen;
reg_b10_rdy <= reg_b9_rdy;
reg_b11_dec <= reg_b10_dec;
reg_b11_k <= reg_b10_k;
reg_b11_klen <= reg_b10_klen;
reg_b11_rdy <= reg_b10_rdy;
reg_b12_dec <= reg_b11_dec;
reg_b12_k <= reg_b11_k;
reg_b12_klen <= reg_b11_klen;
reg_b12_rdy <= reg_b11_rdy;
reg_b13_dec <= reg_b12_dec;
reg_b13_k <= reg_b12_k;
reg_b13_klen <= reg_b12_klen;
reg_b13_rdy <= reg_b12_rdy;
reg_b14_dec <= reg_b13_dec;
reg_b14_k <= reg_b13_k;
reg_b14_klen <= reg_b13_klen;
reg_b14_rdy <= reg_b13_rdy;
reg_b15_dec <= reg_b14_dec;
reg_b15_k <= reg_b14_k;
reg_b15_klen <= reg_b14_klen;
reg_b15_rdy <= reg_b14_rdy;
reg_b16_dec <= reg_b15_dec;
reg_b16_k <= reg_b15_k;
reg_b16_klen <= reg_b15_klen;
reg_b16_rdy <= reg_b15_rdy;
reg_b17_dec <= reg_b16_dec;
reg_b17_k <= reg_b16_k;
reg_b17_klen <= reg_b16_klen;
reg_b17_rdy <= reg_b16_rdy;
reg_b18_dec <= reg_b17_dec;
reg_b18_k <= reg_b17_k;
reg_b18_klen <= reg_b17_klen;
reg_b18_rdy <= reg_b17_rdy;
reg_b19_dec <= reg_b18_dec;
reg_b19_k <= reg_b18_k;
reg_b19_klen <= reg_b18_klen;
reg_b19_rdy <= reg_b18_rdy;
reg_b20_dec <= reg_b19_dec;
reg_b20_k <= reg_b19_k;
reg_b20_klen <= reg_b19_klen;
reg_b20_rdy <= reg_b19_rdy;
reg_b21_dec <= reg_b20_dec;
reg_b21_k <= reg_b20_k;
reg_b21_klen <= reg_b20_klen;
reg_b21_rdy <= reg_b20_rdy;
reg_b22_dec <= reg_b21_dec;
reg_b22_k <= reg_b21_k;
reg_b22_klen <= reg_b21_klen;
reg_b22_rdy <= reg_b21_rdy;
reg_b23_dec <= reg_b22_dec;
reg_b23_k <= reg_b22_k;
reg_b23_klen <= reg_b22_klen;
reg_b23_rdy <= reg_b22_rdy;
reg_b24_dec <= reg_b23_dec;
reg_b24_k <= reg_b23_k;
reg_b24_klen <= reg_b23_klen;
reg_b24_rdy <= reg_b23_rdy;
reg_b25_dec <= reg_b24_dec;
reg_b25_k <= reg_b24_k;
reg_b25_klen <= reg_b24_klen;
reg_b25_rdy <= reg_b24_rdy;
reg_b26_dec <= reg_b25_dec;
reg_b26_k <= reg_b25_k;
reg_b26_klen <= reg_b25_klen;
reg_b26_rdy <= reg_b25_rdy;
reg_b27_dec <= reg_b26_dec;
reg_b27_k <= reg_b26_k;
reg_b27_klen <= reg_b26_klen;
reg_b27_rdy <= reg_b26_rdy;
 
reg_l128_1 <= out_r3l;
reg_r128_1 <= out_r3r;
1014,15 → 1006,16
reg_r128_7 <= reg_r128_6;
 
-- output
c <= w3 & w4;
output <= w3 & w4;
output_rdy <= reg_b27_rdy;
 
end if;
end process;
 
--kr depends on key lenght
kr_int <= (others=>'0') when k_len(0)='0' else
k(128 to 191) & not k(128 to 191) when k_len="10" else
k(128 to 255);
kr_int <= (others=>'0') when key_len(0)='0' else
key(128 to 191) & not key(128 to 191) when key_len="10" else
key(128 to 255);
 
-- pre-whitening
kw1_enc <= out_ksched(KL_OFFSET to KL_OFFSET+63);
/trunk/pipelining/camellia256_tb.do
10,11 → 10,10
vcom -quiet camellia256_tb.vhd
vsim camellia256_tb
view wave
add wave -U clk_count
add wave -divider "camellia256"
add wave -HEX -ports /uut/*
add wave -divider "key"
add wave -HEX -ports /uut/key/*
add wave -HEX -ports /uut/key_sched/*
add wave -divider "six1"
add wave -HEX -ports /uut/six1/*
add wave -divider "fl1"
29,4 → 28,4
add wave -HEX -ports /uut/fl3/*
add wave -divider "six4"
add wave -HEX -ports /uut/six4/*
run 1400 ns
run 250 ns
/trunk/pipelining/camellia256_tb.vhd
3,7 → 3,7
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 09/14/2007
-- Last Update: 01/16/2007
-- Last Update: 06/23/2008
-- Project Name: camellia-vhdl
-- Description: VHDL Test Bench for module CAMELLIA256
--
26,8 → 26,6
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_textio.all;
use STD.textio.all;
 
entity camellia256_tb is
end camellia256_tb;
37,33 → 35,34
-- Component Declaration for the Unit Under Test (UUT)
component CAMELLIA256 is
port(
reset : in STD_LOGIC;
clk : in STD_LOGIC;
m : in STD_LOGIC_VECTOR (0 to 127);
k : in STD_LOGIC_VECTOR (0 to 255);
k_len : in STD_LOGIC_VECTOR (0 to 1);
dec : in STD_LOGIC;
c : out STD_LOGIC_VECTOR (0 to 127)
reset : in STD_LOGIC;
clk : in STD_LOGIC;
input : in STD_LOGIC_VECTOR (0 to 127);
input_en : in STD_LOGIC;
key : in STD_LOGIC_VECTOR (0 to 255);
key_len : in STD_LOGIC_VECTOR (0 to 1);
enc_dec : in STD_LOGIC;
output : out STD_LOGIC_VECTOR (0 to 127);
output_rdy : out STD_LOGIC
);
end component;
 
--Inputs
signal reset : STD_LOGIC;
signal clk : STD_LOGIC;
signal m : STD_LOGIC_VECTOR(0 to 127) := (others=>'0');
signal k : STD_LOGIC_VECTOR(0 to 255) := (others=>'0');
signal k_len : STD_LOGIC_VECTOR(0 to 1) := "00";
signal dec : STD_LOGIC;
signal reset : STD_LOGIC;
signal clk : STD_LOGIC;
signal input : STD_LOGIC_VECTOR(0 to 127) := (others=>'0');
signal input_en : STD_LOGIC := '0';
signal key : STD_LOGIC_VECTOR(0 to 255) := (others=>'0');
signal key_len : STD_LOGIC_VECTOR(0 to 1) := "00";
signal enc_dec : STD_LOGIC;
 
--Output
signal c : STD_LOGIC_VECTOR(0 to 127);
signal output : STD_LOGIC_VECTOR(0 to 127);
signal output_rdy : STD_LOGIC;
 
-- Time constants
constant ClockPeriod : TIME := 30 ns;
constant InitReset : TIME := 20 ns;
constant ClockPeriod : TIME := 5 ns;
 
-- Misc
signal clk_count : INTEGER range 0 to 44;
 
 
begin
73,11 → 72,13
port map(
reset => reset,
clk => clk,
m => m,
k => k,
k_len => k_len,
dec => dec,
c => c
input => input,
input_en => input_en,
key => key,
key_len => key_len,
enc_dec => enc_dec,
output => output,
output_rdy => output_rdy
);
 
ck : process
91,55 → 92,49
process
begin
reset <= '1';
clk_count <= 0;
wait for InitReset;
wait for ClockPeriod*2; --falling clock edge
reset <= '0';
m <= X"0123456789ABCDEFFEDCBA9876543210";
k <= X"0123456789ABCDEFFEDCBA9876543210" &
X"00000000000000000000000000000000";
k_len <= "00";
dec <= '0';
wait for ClockPeriod;
m <= X"67673138549669730857065648EABE43";
k <= X"0123456789ABCDEFFEDCBA9876543210" &
X"00000000000000000000000000000000";
k_len <= "00";
dec <= '1';
clk_count <= clk_count + 1;
wait for ClockPeriod;
m <= X"0123456789ABCDEFFEDCBA9876543210";
k <= X"0123456789ABCDEFFEDCBA9876543210" &
X"00112233445566770000000000000000";
k_len <= "10";
dec <= '0';
clk_count <= clk_count + 1;
wait for ClockPeriod;
m <= X"B4993401B3E996F84EE5CEE7D79B09B9";
k <= X"0123456789ABCDEFFEDCBA9876543210" &
X"00112233445566770000000000000000";
k_len <= "10";
dec <= '1';
clk_count <= clk_count + 1;
wait for ClockPeriod;
m <= X"0123456789ABCDEFFEDCBA9876543210";
k <= X"0123456789ABCDEFFEDCBA9876543210" &
X"00112233445566778899AABBCCDDEEFF";
k_len <= "11";
dec <= '0';
clk_count <= clk_count + 1;
wait for ClockPeriod;
m <= X"9ACC237DFF16D76C20EF7C919E3A7509";
k <= X"0123456789ABCDEFFEDCBA9876543210" &
X"00112233445566778899AABBCCDDEEFF";
k_len <= "11";
dec <= '1';
clk_count <= clk_count + 1;
for I in 0 to 35 loop
wait for ClockPeriod;
clk_count <= clk_count + 1;
end loop;
reset <= '1';
wait until clk = '1';
input <= X"0123456789ABCDEFFEDCBA9876543210";
key <= X"0123456789ABCDEFFEDCBA9876543210" &
X"00112233445566778899AABBCCDDEEFF";
key_len <= "00";
enc_dec <= '0';
input_en <= '1';
wait until clk = '1';
input <= X"67673138549669730857065648EABE43";
key <= X"0123456789ABCDEFFEDCBA9876543210" &
X"00112233445566778899AABBCCDDEEFF";
key_len <= "00";
enc_dec <= '1';
wait until clk = '1';
input <= X"0123456789ABCDEFFEDCBA9876543210";
key <= X"0123456789ABCDEFFEDCBA9876543210" &
X"00112233445566778899AABBCCDDEEFF";
key_len <= "10";
enc_dec <= '0';
wait until clk = '1';
input <= X"B4993401B3E996F84EE5CEE7D79B09B9";
key <= X"0123456789ABCDEFFEDCBA9876543210" &
X"00112233445566778899AABBCCDDEEFF";
key_len <= "10";
enc_dec <= '1';
wait until clk = '1';
input <= X"0123456789ABCDEFFEDCBA9876543210";
key <= X"0123456789ABCDEFFEDCBA9876543210" &
X"00112233445566778899AABBCCDDEEFF";
key_len <= "11";
enc_dec <= '0';
wait until clk = '1';
input <= X"9ACC237DFF16D76C20EF7C919E3A7509";
key <= X"0123456789ABCDEFFEDCBA9876543210" &
X"00112233445566778899AABBCCDDEEFF";
key_len <= "11";
enc_dec <= '1';
wait until clk = '1';
input_en <= '0';
wait;
end process;
 
 
end;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.