URL
https://opencores.org/ocsvn/dirac/dirac/trunk
Subversion Repositories dirac
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 7 to Rev 8
- ↔ Reverse comparison
Rev 7 → Rev 8
/trunk/src/encoder/arithmeticcoder.prj
1,6 → 1,9
vhdl work ../common/FIFO.vhd |
vhdl work ../common/INPUT_CONTROL.vhd |
vhdl work LIMIT_REGISTER.vhd |
vhdl work ../common/HALVING_MANAGER.vhd |
vhdl work ../common/UPDATER.vhd |
vhdl work ../common/Divider.vhd |
vhdl work ../common/CONTEXT_MANAGER.vhd |
vhdl work ../common/ARITHMETIC_UNIT.vhd |
vhdl work ../common/CONVERGENCE_CHECK.vhd |
/trunk/src/encoder/ARITHMETICCODER.vhd
1,38 → 1,37
-- ***** BEGIN LICENSE BLOCK ***** |
-- |
-- $Id: ARITHMETICCODER.vhd,v 1.2 2005-05-27 16:00:30 petebleackley Exp $ $Name: not supported by cvs2svn $ |
-- * |
-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1 |
-- * |
-- * The contents of this file are subject to the Mozilla Public License |
-- * Version 1.1 (the "License"); you may not use this file except in compliance |
-- * with the License. You may obtain a copy of the License at |
-- * http://www.mozilla.org/MPL/ |
-- * |
-- * Software distributed under the License is distributed on an "AS IS" basis, |
-- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for |
-- * the specific language governing rights and limitations under the License. |
-- * |
-- * The Original Code is BBC Research and Development code. |
-- * |
-- * The Initial Developer of the Original Code is the British Broadcasting |
-- * Corporation. |
-- * Portions created by the Initial Developer are Copyright (C) 2004. |
-- * All Rights Reserved. |
-- * |
-- * Contributor(s): Peter Bleackley (Original author) |
-- * |
-- * Alternatively, the contents of this file may be used under the terms of |
-- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser |
-- * Public License Version 2.1 (the "LGPL"), in which case the provisions of |
-- * the GPL or the LGPL are applicable instead of those above. If you wish to |
-- * allow use of your version of this file only under the terms of the either |
-- * the GPL or LGPL and not to allow others to use your version of this file |
-- * under the MPL, indicate your decision by deleting the provisions above |
-- * and replace them with the notice and other provisions required by the GPL |
-- * or LGPL. If you do not delete the provisions above, a recipient may use |
-- * your version of this file under the terms of any one of the MPL, the GPL |
-- * or the LGPL. |
-- |
-- Version: MPL 1.1/GPL 2.0/LGPL 2.1 |
-- |
-- The contents of this file are subject to the Mozilla Public License |
-- Version 1.1 (the "License"); you may not use this file except in compliance |
-- with the License. You may obtain a copy of the License at |
-- http://www.mozilla.org/MPL/ |
-- |
-- Software distributed under the License is distributed on an "AS IS" basis, |
-- WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for |
-- the specific language governing rights and limitations under the License. |
-- |
-- The Original Code is BBC Research and Development code. |
-- |
-- The Initial Developer of the Original Code is the British Broadcasting |
-- Corporation. |
-- Portions created by the Initial Developer are Copyright (C) 2006. |
-- All Rights Reserved. |
-- |
-- Contributor(s): Peter Bleackley (Original author) |
-- |
-- Alternatively, the contents of this file may be used under the terms of |
-- the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser |
-- Public License Version 2.1 (the "LGPL"), in which case the provisions of |
-- the GPL or the LGPL are applicable instead of those above. If you wish to |
-- allow use of your version of this file only under the terms of the either |
-- the GPL or LGPL and not to allow others to use your version of this file |
-- under the MPL, indicate your decision by deleting the provisions above |
-- and replace them with the notice and other provisions required by the GPL |
-- or LGPL. If you do not delete the provisions above, a recipient may use |
-- your version of this file under the terms of any one of the MPL, the GPL |
-- or the LGPL. |
-- * ***** END LICENSE BLOCK ***** */ |
|
library IEEE; |
50,10 → 49,13
DATA_IN : in std_logic; |
CONTEXT_ENABLE : in std_logic; |
CONTEXT_IN : in std_logic_vector (5 downto 0); |
HALVECOUNTS_IN : in std_logic; |
FLUSH : in std_logic; |
RESET : in std_logic; |
CLOCK : in std_logic; |
SENDING : out std_logic; |
DATA_OUT : out std_logic); |
DATA_OUT : out std_logic; |
FLUSH_COMPLETE : out std_logic); |
end ARITHMETICCODER; |
|
architecture RTL of ARITHMETICCODER is |
121,12 → 123,18
end component INPUT_CONTROL; |
component CONTEXT_MANAGER |
port ( CONTEXT_NUMBER : in std_logic_vector(5 downto 0); |
SET : in std_logic; |
UPDATE : in std_logic; |
DATA_IN : in std_logic; |
HALVECOUNTS : in std_logic; |
RESET : in std_logic; |
CLOCK : in std_logic; |
PROB : out std_logic_vector(9 downto 0)); |
PROB : out std_logic_vector(9 downto 0); |
READY : out std_logic); |
end component CONTEXT_MANAGER; |
signal HIGH_SET : std_logic; |
signal LOW_SET : std_logic; |
signal TRIGGER_SHIFT : std_logic; |
signal SHIFT_ALL : std_logic; |
signal DIFFERENCE_SHIFT_ALL : std_logic; |
signal SHIFT_MOST : std_logic; |
159,7 → 167,22
signal BUFFERCONTEXT : std_logic; |
signal DATA_IN2 : std_logic_vector(0 downto 0); |
signal BUFFERED_DATA2 : std_logic_vector(0 downto 0); |
|
signal CONTEXT_BUFFER_DATA_IN : std_logic_vector(7 downto 0); |
signal CONTEXT_BUFFER_DATA_OUT : std_logic_vector(7 downto 0); |
-- signal LAST_FIVE_TRIGGERS : std_logic_vector(4 downto 0); |
signal HALVECOUNTS : std_logic; |
signal BUFFERED_FLUSH : std_logic; |
signal FLUSH_ENCODER : std_logic; |
signal SWITCHED_DATA : std_logic; |
signal CONVERGED : std_logic; |
signal INCREMENT_FOLLOW : std_logic; |
signal ALLOWHALVING : std_logic; |
signal RELEASE_CONTEXT : std_logic; |
-- signal FETCH_FLUSH : std_logic; |
signal DEMAND_CONTEXT : std_logic; |
signal LOCK : std_logic; |
signal DEMAND_DATA : std_logic; |
signal HOLDCONTEXT : std_logic; |
begin |
-- input buffering |
INBUFFER: INPUT_CONTROL |
167,7 → 190,7
port map(ENABLE => ENABLE, |
DATA_IN => DATA_IN2, |
BUFFER_CONTROL => BUFFER_INPUT, |
DEMAND => ARITHMETIC_UNIT_DATA_LOAD, |
DEMAND => DEMAND_DATA, |
RESET => RESET, |
CLOCK => CLOCK, |
SENDING => DATA_AVAILABLE, |
175,17 → 198,28
|
DATA_IN2(0) <= DATA_IN; |
BUFFERED_DATA <= BUFFERED_DATA2(0); |
DEMAND_DATA <= ARITHMETIC_UNIT_DATA_LOAD and not LOCK; |
|
CONTEXT_BUFFER: INPUT_CONTROL |
generic map(WIDTH => 6) |
generic map(WIDTH => 8) |
port map(ENABLE => CONTEXT_ENABLE, |
DATA_IN => CONTEXT_IN, |
DATA_IN => CONTEXT_BUFFER_DATA_IN, |
BUFFER_CONTROL => BUFFERCONTEXT, |
DEMAND => DATA_LOAD, |
DEMAND => DEMAND_CONTEXT, |
RESET => RESET, |
CLOCK => CLOCK, |
SENDING => NEWCONTEXT, |
DATA_OUT => CONTEXT_SELECT); |
DATA_OUT => CONTEXT_BUFFER_DATA_OUT); |
|
CONTEXT_BUFFER_DATA_IN <= (CONTEXT_IN & HALVECOUNTS_IN & FLUSH); |
|
CONTEXT_SELECT <= CONTEXT_BUFFER_DATA_OUT(7 downto 2); |
HALVECOUNTS <= CONTEXT_BUFFER_DATA_OUT(1) and ALLOWHALVING; |
BUFFERED_FLUSH <= CONTEXT_BUFFER_DATA_OUT(0) and CONVERGENCE_TEST and (CONVERGED nor SHIFT_MOST) and not LOCK; |
|
|
|
|
-- Specify the registers |
HIGH: LIMIT_REGISTER |
generic map(CONST => '1') |
240,23 → 274,24
HIGH_SECONDBIT => HIGH_OUT(14), |
LOW_SECONDBIT => LOW_OUT(14), |
CHECK => CONVERGENCE_TEST, |
TRIGGER_OUTPUT => TRIGGER_OUTPUT, |
TRIGGER_OUTPUT => CONVERGED, |
TRIGGER_FOLLOW => SHIFT_MOST); |
|
TRIGGER_OUTPUT <= CONVERGED or FLUSH_ENCODER; |
--The Follow Counter |
|
FC: FOLLOW_COUNTER |
port map( INCREMENT => SHIFT_MOST, |
port map( INCREMENT => INCREMENT_FOLLOW, |
TEST => FOLLOW_COUNTER_TEST, |
RESET => RESET, |
CLOCK => CLOCK, |
OUTPUT => FOLLOW); |
|
INCREMENT_FOLLOW <= SHIFT_MOST or BUFFERED_FLUSH; |
--The output unit |
|
OUTPUT: OUTPUT_UNIT |
port map(ENABLE => TRIGGER_OUTPUT, |
DATA => HIGH_OUT(15), |
DATA => SWITCHED_DATA, |
FOLLOW => FOLLOW, |
RESET => RESET, |
CLOCK => CLOCK, |
263,10 → 298,12
SENDING => OUTPUT_ACTIVE, |
DATA_OUT => DATA_OUT, |
FOLLOW_COUNTER_TEST => FOLLOW_COUNTER_TEST, |
SHIFT => SHIFT_ALL); |
SHIFT => TRIGGER_SHIFT); |
|
SENDING <= OUTPUT_ACTIVE; |
|
SHIFT_ALL <= TRIGGER_SHIFT and not FLUSH_ENCODER; |
|
-- Input logic |
|
DATA_LOAD <= DATA_AVAILABLE and ARITHMETIC_UNIT_DATA_LOAD; |
274,6 → 311,15
ZERO_INPUT <= not BUFFERED_DATA; |
LOW_SET <= BUFFERED_DATA and DATA_LOAD; |
|
FLUSH_SWITCH : process (FLUSH_ENCODER,LOW_OUT,HIGH_OUT) |
begin |
if FLUSH_ENCODER = '1' then |
SWITCHED_DATA <= LOW_OUT(14); |
else |
SWITCHED_DATA <= HIGH_OUT(15); |
end if; |
end process FLUSH_SWITCH; |
|
-- Control logic for DIFFERENCE register |
|
DIFFERENCE_SHIFT_ALL <= SHIFT_ALL or SHIFT_MOST; |
314,25 → 360,97
|
PROBABILITY : CONTEXT_MANAGER |
port map(CONTEXT_NUMBER => CONTEXT_SELECT, |
SET => NEWCONTEXT, |
UPDATE => DATA_LOAD, |
DATA_IN => BUFFERED_DATA, |
HALVECOUNTS => HALVECOUNTS, |
RESET => RESET, |
CLOCK => CLOCK, |
PROB => PROB); |
PROB => PROB, |
READY => PROB_AVAILABLE); |
|
ISPROBAVAILABLE : process (CLOCK) |
begin |
if (CLOCK'event and CLOCK = '1') then |
if (RESET = '1' or (DATA_LOAD = '1' and NEWCONTEXT = '0')) then |
PROB_AVAILABLE <= '0'; |
elsif (NEWCONTEXT = '1') then |
PROB_AVAILABLE <= '1'; |
|
|
FLUSH_CONTROL : process (CLOCK) |
begin |
if CLOCK'event and CLOCK = '1' then |
if RESET = '1' then |
FLUSH_ENCODER <= '0'; |
elsif BUFFERED_FLUSH = '1' then |
FLUSH_ENCODER <= '1'; |
elsif TRIGGER_SHIFT = '1' then |
FLUSH_ENCODER <= '0'; |
end if; |
end if; |
end process FLUSH_CONTROL; |
|
FLUSH_COMPLETE <= FLUSH_ENCODER and TRIGGER_SHIFT; |
|
LIMITHALVING : process (CLOCK) |
begin |
if CLOCK'event and CLOCK='1' then |
if RESET='1' then |
ALLOWHALVING <= '1'; |
else |
ALLOWHALVING <= not CONTEXT_BUFFER_DATA_OUT(1); |
end if; |
end if; |
end process ISPROBAVAILABLE; |
end process LIMITHALVING; |
|
BUFFERCONTEXT <= PROB_AVAILABLE and not ARITHMETIC_UNIT_DATA_LOAD; |
RELEASE_CONTEXT <= RESET or DEMAND_CONTEXT; |
|
CONTEXTS_SHOULD_BE_BUFFERED : process (RELEASE_CONTEXT,CLOCK) |
begin |
if CLOCK'event and CLOCK = '1' then |
if NEWCONTEXT = '1' then |
HOLDCONTEXT <= '1'; |
elsif RELEASE_CONTEXT = '1' then |
HOLDCONTEXT <= '0'; |
end if; |
end if; |
end process CONTEXTS_SHOULD_BE_BUFFERED; |
|
BUFFERCONTEXT <= HOLDCONTEXT and not RELEASE_CONTEXT; |
|
--STORE_TRIGGERS : process (CLOCK) |
--begin |
-- if CLOCK'event and CLOCK='1' then |
-- if RESET='1' then |
-- LAST_FIVE_TRIGGERS <= "11111"; |
-- else |
-- LAST_FIVE_TRIGGERS <= LAST_FIVE_TRIGGERS(3 downto 0) & (DATA_AVAILABLE or OUTPUT_ACTIVE or DIFFERENCE_SHIFT_ALL); |
-- end if; |
-- end if; |
--end process STORE_TRIGGERS; |
|
--GET_FLUSH_SIGNAL : process (LAST_FIVE_TRIGGERS) |
--begin |
-- if LAST_FIVE_TRIGGERS = "00000" then |
-- FETCH_FLUSH <= '1'; |
-- else |
-- FETCH_FLUSH <= '0'; |
-- end if; |
--end process GET_FLUSH_SIGNAL; |
|
LOCK_ENCODER : process (CLOCK) |
begin |
if CLOCK'event and CLOCK='1' then |
if RESET = '1' then |
LOCK <= '0'; |
elsif BUFFERED_FLUSH='1' then |
LOCK <= '1'; |
end if; |
end if; |
end process LOCK_ENCODER; |
|
DEMAND_CONTEXT <= DATA_LOAD; -- or FETCH_FLUSH;--DATA_LOAD or FETCH_FLUSH or AFTER_RESET; |
|
--DELAY_RESET: process (CLOCK) |
--begin |
-- if CLOCK'event and CLOCK='1' then |
-- AFTER_RESET <= RESET; |
-- end if; |
--end process DELAY_RESET; |
-- |
|
end RTL; |
|
|
/trunk/src/testbench/ArithmeticCoderTestbench.prj
3,11 → 3,12
vhdl work ../encoder/LIMIT_REGISTER.vhd |
vhdl work ../common/ARITHMETIC_UNIT.vhd |
vhdl work ../common/CONVERGENCE_CHECK.vhd |
vhdl work ../common/UPDATER.vhd |
vhdl work ../common/HALVING_MANAGER.vhd |
vhdl work ../common/Divider.vhd |
vhdl work ../common/CONTEXT_MANAGER.vhd |
vhdl work ../encoder/FOLLOW_COUNTER.vhd |
vhdl work ../encoder/OUTPUT_UNIT.vhd |
vhdl work ../encoder.ARITHMETICCODER.vhd |
vhdl work ../decoder/STORAGE_REGISTER.vhd |
vhdl work ../decoder/SYMBOL_DETECTOR.vhd |
vhdl work ../decoder/ARITHMETICDECODER.vhd |
vhdl work ../expgolomb/EXP_GOLOMB_COUNTER.vhd |
vhdl work ArithmeticCoderTestbench.vhd |
/trunk/src/testbench/test1.dr0
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
trunk/src/testbench/test1.dr0
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/src/testbench/test1.dr1
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/src/testbench/test1.dr1
===================================================================
--- trunk/src/testbench/test1.dr1 (nonexistent)
+++ trunk/src/testbench/test1.dr1 (revision 8)
trunk/src/testbench/test1.dr1
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/src/testbench/ArithmeticCoderTestbench.vhd
===================================================================
--- trunk/src/testbench/ArithmeticCoderTestbench.vhd (revision 7)
+++ trunk/src/testbench/ArithmeticCoderTestbench.vhd (revision 8)
@@ -1,49 +1,39 @@
-- ***** BEGIN LICENSE BLOCK *****
--
--- $Id: ArithmeticCoderTestbench.vhd,v 1.3 2005-05-27 16:00:30 petebleackley Exp $ $Name: not supported by cvs2svn $
--- *
--- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
--- *
--- * The contents of this file are subject to the Mozilla Public License
--- * Version 1.1 (the "License"); you may not use this file except in compliance
--- * with the License. You may obtain a copy of the License at
--- * http://www.mozilla.org/MPL/
--- *
--- * Software distributed under the License is distributed on an "AS IS" basis,
--- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
--- * the specific language governing rights and limitations under the License.
--- *
--- * The Original Code is BBC Research and Development code.
--- *
--- * The Initial Developer of the Original Code is the British Broadcasting
--- * Corporation.
--- * Portions created by the Initial Developer are Copyright (C) 2004.
--- * All Rights Reserved.
--- *
--- * Contributor(s): Peter Bleackley (Original author)
--- *
--- * Alternatively, the contents of this file may be used under the terms of
--- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
--- * Public License Version 2.1 (the "LGPL"), in which case the provisions of
--- * the GPL or the LGPL are applicable instead of those above. If you wish to
--- * allow use of your version of this file only under the terms of the either
--- * the GPL or LGPL and not to allow others to use your version of this file
--- * under the MPL, indicate your decision by deleting the provisions above
--- * and replace them with the notice and other provisions required by the GPL
--- * or LGPL. If you do not delete the provisions above, a recipient may use
--- * your version of this file under the terms of any one of the MPL, the GPL
--- * or the LGPL.
+--
+-- Version: MPL 1.1/GPL 2.0/LGPL 2.1
+--
+-- The contents of this file are subject to the Mozilla Public License
+-- Version 1.1 (the "License"); you may not use this file except in compliance
+-- with the License. You may obtain a copy of the License at
+-- http://www.mozilla.org/MPL/
+--
+-- Software distributed under the License is distributed on an "AS IS" basis,
+-- WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
+-- the specific language governing rights and limitations under the License.
+--
+-- The Original Code is BBC Research and Development code.
+--
+-- The Initial Developer of the Original Code is the British Broadcasting
+-- Corporation.
+-- Portions created by the Initial Developer are Copyright (C) 2006.
+-- All Rights Reserved.
+--
+-- Contributor(s): Peter Bleackley (Original author)
+--
+-- Alternatively, the contents of this file may be used under the terms of
+-- the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
+-- Public License Version 2.1 (the "LGPL"), in which case the provisions of
+-- the GPL or the LGPL are applicable instead of those above. If you wish to
+-- allow use of your version of this file only under the terms of the either
+-- the GPL or LGPL and not to allow others to use your version of this file
+-- under the MPL, indicate your decision by deleting the provisions above
+-- and replace them with the notice and other provisions required by the GPL
+-- or LGPL. If you do not delete the provisions above, a recipient may use
+-- your version of this file under the terms of any one of the MPL, the GPL
+-- or the LGPL.
-- * ***** END LICENSE BLOCK ***** */
--- VHDL Test Bench Created from source file arithmeticcoder.vhd -- 13:44:22 01/05/2005
---
--- Notes:
--- This testbench has been automatically generated using types std_logic and
--- std_logic_vector for the ports of the unit under test. Xilinx recommends
--- that these types always be used for the top-level I/O of a design in order
--- to guarantee that the testbench will bind correctly to the post-implementation
--- simulation model.
---
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
@@ -58,222 +48,397 @@
ARCHITECTURE behavior OF arithmeticcoder_ArithmeticCoderTestbench_vhd_tb IS
COMPONENT arithmeticcoder
--- generic(
--- PROB : std_logic_vector (9 downto 0));
PORT(
ENABLE : IN std_logic;
DATA_IN : IN std_logic;
CONTEXT_ENABLE : in std_logic;
CONTEXT_IN : in std_logic_vector (5 downto 0);
+ HALVECOUNTS_IN : in std_logic;
+ FLUSH : in std_logic;
RESET : IN std_logic;
CLOCK : IN std_logic;
SENDING : OUT std_logic;
- DATA_OUT : OUT std_logic
+ DATA_OUT : OUT std_logic;
+ FLUSH_COMPLETE : out std_logic
);
END COMPONENT;
- component ARITHMETICDECODER
- port (ENABLE : in std_logic;
- DATA_IN : in std_logic;
- NEWCONTEXT : in std_logic;
- CONTEXT_SELECT : in std_logic_vector (5 downto 0);
- RESET : in std_logic;
- CLOCK : in std_logic;
- SENDING : out std_logic;
- DATA_OUT : out std_logic);
- end component ARITHMETICDECODER;
- component FIFO
- generic (RANK : integer range 0 to 16;
- WIDTH : integer range 1 to 16);
- port ( WRITE_ENABLE : in std_logic;
- DATA_IN: in std_logic_vector (WIDTH - 1 downto 0);
- READ_ENABLE : in std_logic;
- RESET : in std_logic;
- CLOCK : in std_logic;
- DATA_OUT : out std_logic_vector (WIDTH - 1 downto 0);
- EMPTY : out std_logic);
- end component FIFO;
+ component EXP_GOLOMB_COUNTER
+ port( DATA_IN : in std_logic_vector (31 downto 0);
+ TEST : in std_logic;
+ RESET : in std_logic;
+ CLOCK : in std_logic;
+ COUNTING : out std_logic;
+ DATA_OUT : out std_logic);
+ end component EXP_GOLOMB_COUNTER;
+
SIGNAL ENABLE : std_logic;
SIGNAL DATA_IN : std_logic := '0';
- SIGNAL RESET : std_logic;
+ SIGNAL RESET : std_logic := '1';
SIGNAL CLOCK : std_logic := '0';
+ signal FLUSH : std_logic := '0';
+ signal HALVECOUNTS : std_logic := '0';
SIGNAL SENDING : std_logic;
SIGNAL DATA_OUT : std_logic;
signal TRANSMIT : std_logic;
signal DATA_TRANSFER : std_logic;
+ signal FLUSH_COMPLETE : std_logic;
signal DATA_IN2 : std_logic_vector (0 downto 0);
signal BUFFERED2 : std_logic_vector (0 downto 0);
--- signal FINISHED : std_logic := '0';
signal FIFO_EMPTY : std_logic;
signal BUFFERED : std_logic;
- constant PERIOD : time := 10 ns;
+ constant PERIOD : time := 16 ns;
signal CONTEXT_ENABLE : std_logic;
signal DECODER_CONTEXT_ENABLE : std_logic;
- signal CONTEXT : std_logic_vector (5 downto 0) := "000000";
+ signal NUMBITS : std_logic_vector (31 downto 0) := "00000000000000000000000000000000";
+ signal NEXTNUMBITS : std_logic_vector (31 downto 0);
+ signal NUMBYTES : std_logic_vector (28 downto 0);
+ signal CONTEXT_IN : std_logic_vector (5 downto 0) := "000000";
signal DECODER_CONTEXT : std_logic_vector (5 downto 0) := "000000";
- file TESTDATA : text open read_mode is "testseq";
- file RESULTS : text open write_mode is "results";
- type TABLE is array (30 downto 0) of std_logic_vector (5 downto 0);
- constant NCONTEXT0 : TABLE := ("111101","111011","111001","110111",
- "110101","110011","110001","101111","101101","101011","101001",
- "100111","100101","100011","100001","011111","011101","011011",
- "011001","010111","010101","010011","010001","001111","001101",
- "001011","001001","000111","000101","000011","000001");
- constant NCONTEXT1 : TABLE := ("111110","111100","111010","111000",
- "110110","110100","110010","110000","101110","101100","101010",
- "101000","100110","100100","100010","100000","011110","011100",
- "011010","011000","010110","010100","010010","010000","001110",
- "001100","001010","001000","000110","000100","000010");
-
+ signal BYTECOUNT : std_logic_vector (31 downto 0);
+ signal EXP_GOLOMB_READY : std_logic;
+ signal EXP_GOLOMB_DATA : std_logic;
+ signal BYTE_INSERT : std_logic := '0';
+ signal COMPVAL : character;
+ signal SUPPRESS_READ : std_logic := '0';
+ type ENCODER_STATUS is (INIT, INIT2, HEADERS, CODING, FLUSHING, EXP_GOLOMB, WRITE_DATA, FINISHED);
+ signal STATE : ENCODER_STATUS := INIT;
+ type RAM is array (65535 downto 0) of integer;
+ signal STORAGE : RAM;
+ type CHARFILE is file of character;
+ file raw_data : CHARFILE open read_mode is "test1.dr0";
+ file contexts : CHARFILE open read_mode is "test1.ctx";
+ file coded_stream : CHARFILE open write_mode is "test1.drc";
+ file comparison_data : CHARFILE open read_mode is "test1.dr1";
+ type INTARRAY is array (7 downto 0) of integer;
+ function CONTEXT_INTERPRET(CONTEXT : integer) return std_logic_vector is
+ variable VALUE : std_logic_vector(5 downto 0);
+ begin
+ if CONTEXT >= 128 then
+ VALUE(5) := '1';
+ else
+ VALUE(5) := '0';
+ end if;
+ if (CONTEXT mod 128) >= 64 then
+ VALUE(4) := '1';
+ else
+ VALUE(4) := '0';
+ end if;
+ if (CONTEXT mod 64) >= 32 then
+ VALUE(3) := '1';
+ else
+ VALUE(3) := '0';
+ end if;
+ if (CONTEXT mod 32) >= 16 then
+ VALUE(2) := '1';
+ else
+ VALUE(2) := '0';
+ end if;
+ if (CONTEXT mod 16) >= 8 then
+ VALUE(1) := '1';
+ else
+ VALUE(1) := '0';
+ end if;
+ if (CONTEXT mod 8) >= 4 then
+ VALUE(0) := '1';
+ else
+ VALUE(0) := '0';
+ end if;
+ return VALUE;
+ end function CONTEXT_INTERPRET;
BEGIN
uut: arithmeticcoder
--- generic map(
--- PROB => "1110010000")
PORT MAP(
ENABLE => ENABLE,
DATA_IN => DATA_IN,
CONTEXT_ENABLE => CONTEXT_ENABLE,
- CONTEXT_IN => CONTEXT,
+ CONTEXT_IN => CONTEXT_IN,
+ HALVECOUNTS_IN => HALVECOUNTS,
+ FLUSH => FLUSH,
RESET => RESET,
CLOCK => CLOCK,
SENDING => TRANSMIT,
- DATA_OUT => DATA_TRANSFER
+ DATA_OUT => DATA_TRANSFER,
+ FLUSH_COMPLETE => FLUSH_COMPLETE
);
+
+ EGC: EXP_GOLOMB_COUNTER
+ port map(
+ DATA_IN => BYTECOUNT,
+ TEST => FLUSH_COMPLETE,
+ RESET => RESET,
+ CLOCK => CLOCK,
+ COUNTING => EXP_GOLOMB_READY,
+ DATA_OUT => EXP_GOLOMB_DATA);
+
+
CLOCK <= not CLOCK after PERIOD/2;
- DECODER: ARITHMETICDECODER
- port map( ENABLE => TRANSMIT,
- DATA_IN => DATA_TRANSFER,
- NEWCONTEXT => DECODER_CONTEXT_ENABLE,
- CONTEXT_SELECT => DECODER_CONTEXT,
- RESET => RESET,
- CLOCK => CLOCK,
- SENDING => SENDING,
- DATA_OUT => DATA_OUT);
--*** Test Bench - User Defined Section ***
- tb : PROCESS
- variable GETLINE : line;
- variable INDATA : std_logic;
+ tb : PROCESS (CLOCK)
+ variable POSITION : integer;
+ variable EGPOSITION : integer;
+ variable PLACE : integer;
+ variable READVAL : character;
+ variable WRITEVAL : integer;
+ variable CONTEXT : integer;
+ variable DATA : integer;
+ variable COMPDATA : integer;
+ variable THRESHOLD : integer;
+ variable INDEX : integer range 0 to 536870911;
+ variable READ_DATA : INTARRAY := (0,0,0,0,0,0,0,0);
+ variable DUMMY : character;
+
BEGIN
- for COUNT in 0 to 5242880 loop
- wait until CLOCK'event and CLOCK = '1';
- if (COUNT < 5242900) then
- if COUNT = 0 then
- RESET <= '1';
- ENABLE <= '0';
- DATA_IN <= '0';
- CONTEXT_ENABLE <='0';
- elsif COUNT = 1 then
- RESET <= '0';
- CONTEXT_ENABLE <= '1';
- elsif COUNT mod 5 = 0 then
- CONTEXT_ENABLE <= '1';
- ENABLE <= '0';
- elsif (COUNT - 4) mod 5 = 0 then
-
- if (COUNT - 4) mod 160 = 0 then
- if not endfile(TESTDATA) then
- readline(TESTDATA,GETLINE);
+ if CLOCK'event and CLOCK = '1' then
+ if STATE = INIT then
+ if READ_DATA = ( 16#4B#, 16#57#, 16#2D#, 16#44#, 16#49#, 16#52#, 16#41#, 16#43#) then
+ STATE <= INIT2;
+ RESET <= '0';
+ else
+ READ_DATA(7 downto 1) := READ_DATA(6 downto 0);
+ read(raw_data,READVAL);
+ READ_DATA(0) := character'pos(READVAL);
+ end if;
+ elsif STATE = INIT2 then
+ if READ_DATA (7 downto 3) = ( 16#44#, 16#49#, 16#52#, 16#41#, 16#43#) then
+ STATE <= HEADERS;
+ WRITEVAL := 0;
+ EGPOSITION := 128;
+ else
+ WRITEVAL := READ_DATA(7);
+ write(coded_stream,character'val(WRITEVAL));
+ READ_DATA(7 downto 1) := READ_DATA (6 downto 0);
+ end if;
+ elsif STATE = HEADERS then
+ if READ_DATA (7 downto 3) = ( 16#42#, 16#42#, 16#43#, 16#44#, 16#AC# ) then
+ STATE <= CODING;
+ PLACE := 0;
+ POSITION := 0;
+ RESET <= '1';
+ ENABLE <= '0';
+ DATA_IN <= '0';
+ CONTEXT_ENABLE <= '0';
+ CONTEXT_IN <= "000000";
+ HALVECOUNTS <= '0';
+ FLUSH <= '0';
+ if SUPPRESS_READ = '0' then
+ read(comparison_data,DUMMY);
+ COMPVAL <= DUMMY;
end if;
+ elsif READ_DATA (7 downto 3) = (16#42#, 16#42#, 16#43#, 16#44#, 16#D0# ) then
+ STATE <= FINISHED;
+ else
+ if EGPOSITION = 128 then
+ read(raw_data,READVAL);
+ READ_DATA(2) := character'pos(READVAL);
+ end if;
+ if READ_DATA(7) > 127 then
+ WRITEVAL := WRITEVAL + EGPOSITION;
+ end if;
+
+ for I in 7 downto 2 loop
+ if READ_DATA(I) > 127 then
+ READ_DATA(I) := (READ_DATA(I) -128) * 2;
+ else
+ READ_DATA(I) := READ_DATA(I) * 2;
+ end if;
+ if READ_DATA(I-1) > 127 then
+ READ_DATA(I) := READ_DATA(I) + 1;
+ end if;
+ end loop;
+ if EGPOSITION = 1 then
+ write(coded_stream,character'val(WRITEVAL));
+ EGPOSITION := 128;
+ WRITEVAL := 0;
+ else
+ EGPOSITION := EGPOSITION / 2;
+ end if;
end if;
- read(GETLINE,INDATA);
- DATA_IN <= INDATA;
- ENABLE <= '1';
- if (CONTEXT > "011110") then
- CONTEXT <= "000000";
+ elsif STATE = CODING then
+ if PLACE = 0 then
+ RESET <= '0';
+ end if;
+ if PLACE mod 5 = 0 then
+ read(contexts,READVAL);
+ CONTEXT := character'pos(READVAL);
+ CONTEXT_ENABLE <= '1';
+ if CONTEXT mod 2 = 1 then
+ CONTEXT_IN <= "000000";
+ HALVECOUNTS <= '0';
+ STATE <= FLUSHING;
+ FLUSH <= '1';
+ else
+ CONTEXT_IN <= CONTEXT_INTERPRET(CONTEXT);
+ if (CONTEXT mod 4) > 1 then
+ HALVECOUNTS <= '1';
+ else
+ HALVECOUNTS <= '0';
+ end if;
+ FLUSH <= '0';
+ end if;
+ elsif PLACE mod 5 = 3 then
+ if POSITION = 0 then
+ POSITION := 128;
+ READ(raw_data,READVAL);
+ DATA := character'pos(READVAL);
+ end if;
+ if (DATA / POSITION) mod 2 = 1 then
+ DATA_IN <= '1';
+ else
+ DATA_IN <= '0';
+ end if;
+ ENABLE <= '1';
+ POSITION := POSITION / 2;
else
- if (INDATA = '1') then
- CONTEXT <= NCONTEXT1(conv_integer(CONTEXT));
+ CONTEXT_ENABLE <= '0';
+ ENABLE <= '0';
+ end if;
+ PLACE := PLACE + 1;
+ elsif STATE = FLUSHING then
+ if FLUSH = '1' then
+ FLUSH <= '0';
+ CONTEXT_ENABLE <= '0';
+ end if;
+ if FLUSH_COMPLETE = '1' then
+ STATE <= EXP_GOLOMB;
+ PLACE := 7;
+ POSITION := 128;
+ READ_DATA(7) := 0;
+ end if;
+ elsif STATE = EXP_GOLOMB then
+ if EXP_GOLOMB_READY = '0' then
+ STATE <= WRITE_DATA;
+ INDEX := 0;
+ write(coded_stream,character'val(WRITEVAL));
+ PLACE := 7;
+ else
+ if EXP_GOLOMB_DATA = '1' then
+ WRITEVAL := WRITEVAL + EGPOSITION;
+ end if;
+ if EGPOSITION = 1 then
+ EGPOSITION := 128;
+ write(coded_stream,character'val(WRITEVAL));
+ WRITEVAL := 0;
else
- CONTEXT <= NCONTEXT0(conv_integer(CONTEXT));
+ EGPOSITION := EGPOSITION / 2;
end if;
end if;
- else
- ENABLE <= '0';
- CONTEXT_ENABLE <= '0';
+
+ elsif STATE = WRITE_DATA then
+ if INDEX = (conv_integer(NUMBYTES)-1) then
+ STATE <= HEADERS;
+ WRITEVAL := 0;
+ else
+ if PLACE < 3 then
+ WRITEVAL := READ_DATA(7);
+ write(coded_stream,character'val(WRITEVAL));
+ READ_DATA (7 downto 3) := READ_DATA (6 downto 2);
+ READ_DATA (2) := STORAGE(INDEX);
+ else
+ READ_DATA (PLACE) := STORAGE(INDEX);
+ PLACE := PLACE - 1;
+ end if;
+ INDEX := INDEX + 1;
+ end if;
+ else --STATE = FINISHED
+ if READ_DATA (7 downto 3) = (0, 0, 0, 0, 0) then
+ report ("finished") severity failure;
+ else
+ WRITEVAL := READ_DATA(7);
+ write(coded_stream,character'val(WRITEVAL));
+ READ_DATA (7 downto 3) := READ_DATA (6 downto 3) & 0;
+ end if;
end if;
- elsif (COUNT = 5242900) then
- ENABLE <= '1';
- DATA_IN <= '1';
- else
- wait; -- will wait forever
- end if;
- end loop;
+ end if;
+
+
+
END PROCESS;
- OUTPUT : process
- variable OUTLINE : line;
+
+COUNT_BITS: process (CLOCK)
begin
- for WRITTEN in 0 to 1048576 loop
- wait until CLOCK'event and CLOCK = '1' and SENDING = '1';
- if WRITTEN = 1048576 then
- report "Process Complete" severity failure;
- wait;
+ if (CLOCK'event and CLOCK='1') then
+ if RESET = '1' then
+ NUMBITS <= "00000000000000000000000000000000";
else
- write(OUTLINE,DATA_OUT);
- if (WRITTEN mod 32) = 31 then
- writeline(RESULTS,OUTLINE);
+ if TRANSMIT = '1' then
+ NUMBITS <= NUMBITS + "00000000000000000000000000000001";
end if;
-
-
+ if BYTE_INSERT = '1' then
+ NUMBITS <= NUMBITS + "00000000000000000000000000001000";
+ end if;
end if;
- end loop;
+ end if;
end process;
-TESTBUFFER : FIFO
- generic map(RANK => 11,
- WIDTH => 1)
- port map (WRITE_ENABLE => ENABLE,
- DATA_IN => DATA_IN2,
- READ_ENABLE => SENDING,
- RESET => RESET,
- CLOCK => CLOCK,
- DATA_OUT => BUFFERED2,
- EMPTY => FIFO_EMPTY);
+NEXTNUMBITS <= NUMBITS + "00000000000000000000000000000111";
+
+NUMBYTES <= NEXTNUMBITS (31 downto 3);
- DATA_IN2(0) <= DATA_IN;
- BUFFERED <= BUFFERED2(0);
+ BYTECOUNT <= "0000000000000000" & NUMBYTES(15 downto 0);
-FIND_ERROR : postponed process (SENDING, DATA_OUT, BUFFERED)
- begin
- assert (( SENDING /= '1') or (DATA_OUT = BUFFERED))
- report "DIVERGENGE!!!" severity failure;
- end process FIND_ERROR;
--- *** End Test Bench - User Defined Section ***
-
-COUNT_BITS: process (CLOCK, TRANSMIT)
- variable BITS_SENT : integer range 0 to 1048576 := 0;
- begin
- if (CLOCK'event and CLOCK='1' and TRANSMIT='1') then
- BITS_SENT := BITS_SENT+1;
- end if;
- end process;
-
-
-
-CHOOSE_DECODER_CONTEXT: process(CLOCK)
- begin
+WRITE_MEMORY: process(CLOCK)
+ variable INCREMENT: integer;
+ variable DATA : integer;
+ variable COMPARISON : character;
+ variable COMPDATA : integer;
+ variable COMPDATA2 : integer;
+begin
if CLOCK'event and CLOCK = '1' then
if RESET = '1' then
- DECODER_CONTEXT <= "000000";
- DECODER_CONTEXT_ENABLE <= '1';
- elsif SENDING = '1' then
- if DECODER_CONTEXT > "011110" then
- DECODER_CONTEXT <= "000000";
- elsif DATA_OUT = '1' then
- DECODER_CONTEXT <= NCONTEXT1(conv_integer(DECODER_CONTEXT));
+ INCREMENT := 128;
+ BYTE_INSERT <= '0';
+ if SUPPRESS_READ = '0' then
+ COMPDATA := character'pos(COMPVAL);
+ end if;
+ COMPDATA2 := 0;
+ DATA := 0;
+ elsif TRANSMIT = '1' then
+ if (COMPDATA rem (INCREMENT*2)) >= INCREMENT then
+ COMPDATA2 := COMPDATA2 + INCREMENT;
+ end if;
+ if DATA_TRANSFER = '1' then
+ DATA := DATA + INCREMENT;
+ end if;
+ assert COMPDATA2 = DATA report "ENCODER HAS DIVERGED" severity failure;
+ if INCREMENT = 1 then
+ STORAGE(conv_integer(NUMBYTES)-1) <= DATA;
+ DATA := 0;
+ INCREMENT := 128;
+ read(comparison_data,COMPARISON);
+ COMPDATA := character'pos(COMPARISON);
+ COMPDATA2 := 0;
+ if NUMBYTES >= "00000000000000000000000000100" then
+ if STORAGE((conv_integer(NUMBYTES) -4) downto (conv_integer(NUMBYTES) - 1)) = (16#42#, 16#42#, 16#43#, 16#44#) then
+ STORAGE(conv_integer(NUMBYTES)) <= 16#FF#;
+ BYTE_INSERT <= '1';
+ end if;
+ end if;
else
- DECODER_CONTEXT <= NCONTEXT0(conv_integer(DECODER_CONTEXT));
+ INCREMENT := INCREMENT/2;
end if;
- DECODER_CONTEXT_ENABLE <= '1';
- else
- DECODER_CONTEXT_ENABLE <= '0';
+ elsif FLUSH_COMPLETE = '1' then
+ if INCREMENT /= 128 then
+ STORAGE(conv_integer(NUMBYTES)) <= DATA;
+ if NUMBYTES >= "00000000000000000000000000100" then
+ if STORAGE((conv_integer(NUMBYTES) -3) downto (conv_integer(NUMBYTES))) = (16#42#, 16#42#, 16#43#, 16#44#) then
+ STORAGE(conv_integer(NUMBYTES)+1) <= 16#FF#;
+ BYTE_INSERT <= '1';
+ end if;
+ end if;
+ SUPPRESS_READ <= '0';
+ else
+ SUPPRESS_READ <= '1';
+ end if;
end if;
+ if BYTE_INSERT = '1' then
+ BYTE_INSERT <= '0';
+ end if;
end if;
-end process CHOOSE_DECODER_CONTEXT;
+end process WRITE_MEMORY;
-
-
END;
/trunk/src/testbench/test1.ctx.bz2
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
trunk/src/testbench/test1.ctx.bz2
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/src/common/UPDATER.vhd
===================================================================
--- trunk/src/common/UPDATER.vhd (nonexistent)
+++ trunk/src/common/UPDATER.vhd (revision 8)
@@ -0,0 +1,177 @@
+-- ***** BEGIN LICENSE BLOCK *****
+--
+--
+-- Version: MPL 1.1/GPL 2.0/LGPL 2.1
+--
+-- The contents of this file are subject to the Mozilla Public License
+-- Version 1.1 (the "License"); you may not use this file except in compliance
+-- with the License. You may obtain a copy of the License at
+-- http://www.mozilla.org/MPL/
+--
+-- Software distributed under the License is distributed on an "AS IS" basis,
+-- WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
+-- the specific language governing rights and limitations under the License.
+--
+-- The Original Code is BBC Research and Development code.
+--
+-- The Initial Developer of the Original Code is the British Broadcasting
+-- Corporation.
+-- Portions created by the Initial Developer are Copyright (C) 2006.
+-- All Rights Reserved.
+--
+-- Contributor(s): Peter Bleackley (Original author)
+--
+-- Alternatively, the contents of this file may be used under the terms of
+-- the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
+-- Public License Version 2.1 (the "LGPL"), in which case the provisions of
+-- the GPL or the LGPL are applicable instead of those above. If you wish to
+-- allow use of your version of this file only under the terms of the either
+-- the GPL or LGPL and not to allow others to use your version of this file
+-- under the MPL, indicate your decision by deleting the provisions above
+-- and replace them with the notice and other provisions required by the GPL
+-- or LGPL. If you do not delete the provisions above, a recipient may use
+-- your version of this file under the terms of any one of the MPL, the GPL
+-- or the LGPL.
+-- * ***** END LICENSE BLOCK ***** */
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+-- Uncomment the following lines to use the declarations that are
+-- provided for instantiating Xilinx primitive components.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity UPDATER is
+ Port ( NUMERATOR : in std_logic_vector(9 downto 0);
+ DENOMINATOR : in std_logic_vector(9 downto 0);
+ ENABLE : in std_logic;
+ DATA_IN : in std_logic;
+ RESET : in std_logic;
+ CLOCK : in std_logic;
+ NUMERATOR_OUT : out std_logic_vector(9 downto 0);
+ DENOMINATOR_OUT : out std_logic_vector(9 downto 0);
+ UPDATE : out std_logic);
+end UPDATER;
+
+architecture RTL of UPDATER is
+ signal NUMERATOR1 : std_logic_vector(9 downto 0);
+ signal NUMERATOR2 : std_logic_vector(9 downto 0);
+ signal NUMERATOR3 : std_logic_vector(9 downto 0);
+ signal NUMERATOR4 : std_logic_vector(9 downto 0);
+ signal DENOMINATOR2 : std_logic_vector(9 downto 0);
+ signal HALVE_VALUES : std_logic;
+ signal HALVING_ALLOWED : std_logic;
+ signal UPDATE_SWITCH : std_logic;
+begin
+
+DELAY_NUMERATOR : process (CLOCK)
+begin
+ if CLOCK'event and CLOCK='1' then
+ if RESET='1' then
+ NUMERATOR1<="0000000001";
+ else
+ NUMERATOR1<=NUMERATOR;
+ end if;
+ end if;
+end process DELAY_NUMERATOR;
+
+INCREMENT_NUMERATOR : process (CLOCK)
+begin
+ if CLOCK'event and CLOCK = '1' then
+ if RESET = '1' then
+ NUMERATOR2 <= "0000000001";
+ else
+ NUMERATOR2 <= NUMERATOR + "0000000001";
+ end if;
+ end if;
+end process INCREMENT_NUMERATOR;
+
+HALVE_NUMERATOR : process (CLOCK)
+begin
+ if CLOCK'event and CLOCK='1' then
+ if RESET='1' then
+ NUMERATOR3 <= "0000000001";
+ else
+ NUMERATOR3 <= ('0' & NUMERATOR(9 downto 1)) + "0000000001";
+ end if;
+ end if;
+end process HALVE_NUMERATOR;
+
+INCREMENT_AND_HALVE_NUMERATOR : process (CLOCK)
+begin
+ if CLOCK'event and CLOCK='1' then
+ if RESET='1' then
+ NUMERATOR4 <= "0000000001";
+ else
+ NUMERATOR4 <= ('0' & NUMERATOR(9 downto 1)) + "0000000001" + ("000000000" & NUMERATOR(0));
+ end if;
+ end if;
+end process INCREMENT_AND_HALVE_NUMERATOR;
+
+INCREMENT_DENOMINATOR : process (CLOCK)
+begin
+ if CLOCK'event and CLOCK='1' then
+ if RESET='1' then
+ DENOMINATOR2 <= "0000000010";
+ else
+ DENOMINATOR2 <= DENOMINATOR + "0000000001";
+ end if;
+ end if;
+end process INCREMENT_DENOMINATOR;
+
+HALVE_DENOMINATOR : process (DENOMINATOR)
+begin
+ if (DENOMINATOR = "1111111111") then
+ HALVE_VALUES <= '1';
+ else
+ HALVE_VALUES <= '0';
+ end if;
+end process HALVE_DENOMINATOR;
+
+OUTPUT_NUMERATOR : process(NUMERATOR1,NUMERATOR2,NUMERATOR3,NUMERATOR4,DENOMINATOR,DATA_IN,HALVE_VALUES)
+begin
+ if HALVE_VALUES='1' then
+ if DATA_IN='1' then
+ NUMERATOR_OUT <= NUMERATOR3;
+ else
+ NUMERATOR_OUT <= NUMERATOR4;
+ end if;
+ else
+ if DATA_IN='1' then
+ NUMERATOR_OUT <= NUMERATOR1;
+ else
+ NUMERATOR_OUT <= NUMERATOR2;
+ end if;
+ end if;
+end process OUTPUT_NUMERATOR;
+
+UPDATE_SWITCH <= DATA_IN xor NUMERATOR(0);
+
+OUTPUT_DENOMINATOR : process(HALVING_ALLOWED,DENOMINATOR,DENOMINATOR2,UPDATE_SWITCH,HALVE_VALUES,NUMERATOR)
+begin
+ if HALVE_VALUES='1' then
+ if UPDATE_SWITCH = '1' then
+ DENOMINATOR_OUT <= "1000000010";
+ else
+ DENOMINATOR_OUT <= "1000000001";
+ end if;
+ else
+ DENOMINATOR_OUT<=DENOMINATOR2;
+ end if;
+end process OUTPUT_DENOMINATOR;
+
+OUTPUT_READY : process (CLOCK)
+begin
+ if CLOCK'event and CLOCK='1' then
+ if RESET='1' then
+ UPDATE <= '0';
+ else
+ UPDATE <= ENABLE;
+ end if;
+ end if;
+end process OUTPUT_READY;
+
+end RTL;
trunk/src/common/UPDATER.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/src/common/CONTEXT_MANAGER.vhd
===================================================================
--- trunk/src/common/CONTEXT_MANAGER.vhd (revision 7)
+++ trunk/src/common/CONTEXT_MANAGER.vhd (revision 8)
@@ -1,6 +1,6 @@
-- ***** BEGIN LICENSE BLOCK *****
--
--- $Id: CONTEXT_MANAGER.vhd,v 1.1 2005-05-27 16:00:28 petebleackley Exp $ $Name: not supported by cvs2svn $
+-- $Id: CONTEXT_MANAGER.vhd,v 1.2 2006-08-18 14:29:32 petebleackley Exp $ $Name: not supported by cvs2svn $
-- *
-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
-- *
@@ -47,31 +47,172 @@
entity CONTEXT_MANAGER is
Port ( CONTEXT_NUMBER : in std_logic_vector(5 downto 0);
+ SET : in std_logic;
+ UPDATE : in std_logic;
+ DATA_IN : in std_logic;
+ HALVECOUNTS : in std_logic;
RESET : in std_logic;
CLOCK : in std_logic;
- PROB : out std_logic_vector(9 downto 0));
+ PROB : out std_logic_vector(9 downto 0);
+ READY : out std_logic);
end CONTEXT_MANAGER;
architecture RTL of CONTEXT_MANAGER is
- type MATRIX is array (63 downto 0) of std_logic_vector(9 downto 0);
- signal PROBABILITY : MATRIX := ("1111111111","0011011010","1111000000",
- "1100110000","0111110000","1001111100","0000010000","0000110011","1100110011",
- "1101110111","0110011010","1000111000","0000001010","0000110011","1000110011",
- "0101011011","1110000000","0100111101","1000001010","1110011011","0000001010",
- "0101111000","1111000000","1111001101","0111001101","1101011100","0111110110",
- "0110000011","1111110110","0101000110","1110011010","1110101110","0111000011",
- "0110010110","1111001101","0011001101","1001100110","1100100101","0001100110",
- "1110011010","0100110011","1111001101","0111001101","0011101111","1110011010",
- "1111100011","0011001101","0101000000","1110000000","0011000000","1100000000",
- "0110101011","1010101011","1110011010","0110011010","1001110010","0101010101",
- "1000111001","0101010101","1100110011","0110011010","0100000000","1100000000",
- "1000000000");
+
+ type MATRIX is array (45 downto 0) of std_logic_vector(19 downto 0);
+ signal PROBABILITY : MATRIX;
+ constant HALF : std_logic_vector(19 downto 0) := "00000000010000000010";
+ signal FRACTION : std_logic_vector(19 downto 0);
+ signal FRACTION2 : std_logic_vector(19 downto 0);
+ signal RESET_FLAGS : std_logic_vector (63 downto 0);
+ signal NEWPROB : std_logic_vector(19 downto 0);
+ signal RATIO : std_logic_vector(19 downto 0);
+ signal UPDATE_PROB : std_logic;
+ signal PROB_CHANGED : std_logic;
+ signal LOAD_DATA : std_logic;
+ signal OLD_CONTEXT : std_logic_vector (5 downto 0);
+ signal READ_ADDRESS : std_logic_vector (5 downto 0);
+ signal DATA_FETCHED : std_logic;
+ signal CONTEXT_VALID : std_logic;
+ signal DATA_READY : std_logic_vector (1 downto 0);
+
+ component DIVIDER
+ port ( NUMERATOR : in std_logic_vector(9 downto 0);
+ DENOMINATOR : in std_logic_vector(9 downto 0);
+ RESET : in std_logic;
+ CLOCK : in std_logic;
+ QUOTIENT : out std_logic_vector(9 downto 0));
+ end component DIVIDER;
+ component UPDATER
+ port ( NUMERATOR : in std_logic_vector(9 downto 0);
+ DENOMINATOR : in std_logic_vector(9 downto 0);
+ ENABLE : in std_logic;
+ DATA_IN : in std_logic;
+ RESET : in std_logic;
+ CLOCK : in std_logic;
+ NUMERATOR_OUT : out std_logic_vector(9 downto 0);
+ DENOMINATOR_OUT : out std_logic_vector(9 downto 0);
+ UPDATE : out std_logic);
+ end component UPDATER;
+ component HALVING_MANAGER
+ port ( TRIGGER_HALVING : in std_logic;
+ INPUT_READY : in std_logic;
+ NUMERATOR_IN : in std_logic_vector(9 downto 0);
+ DENOMINATOR_IN : in std_logic_vector(9 downto 0);
+ CONTEXT : in std_logic_vector(5 downto 0);
+ RESET : in std_logic;
+ CLOCK : in std_logic;
+ NUMERATOR_OUT : out std_logic_vector(9 downto 0);
+ DENOMINATOR_OUT : out std_logic_vector(9 downto 0);
+ OUTPUT_READY : out std_logic);
+ end component HALVING_MANAGER;
+
begin
- OUTPUT : process (CLOCK)
- begin
- if CLOCK'event and CLOCK = '1' then
- PROB <= PROBABILITY(conv_integer(CONTEXT_NUMBER));
+
+FLAGS: process(CLOCK)
+begin
+ if (CLOCK'event and CLOCK='1') then
+ if (RESET='1') then
+ RESET_FLAGS <= (others => '1');
+ elsif LOAD_DATA = '1' then
+ RESET_FLAGS(conv_integer(OLD_CONTEXT)) <= '0';
+ end if;
end if;
- end process OUTPUT;
+end process FLAGS;
+LOAD_DATA <= UPDATE_PROB and UPDATE;
+
+
+MEMORY: process(CLOCK)
+begin
+ if (CLOCK'event and CLOCK='1') then
+ if SET='1' then
+ READ_ADDRESS <= CONTEXT_NUMBER;
+ end if;
+ if (LOAD_DATA = '1') then
+ PROBABILITY(conv_integer(OLD_CONTEXT)) <= NEWPROB;
+ end if;
+ end if;
+end process MEMORY;
+RATIO <= PROBABILITY(conv_integer(READ_ADDRESS));
+
+CHOOSE_FRACTION : process (READ_ADDRESS,RESET_FLAGS,RATIO)
+begin
+ if (RESET_FLAGS(conv_integer(READ_ADDRESS))='1') then
+ FRACTION <= HALF;
+ else
+ FRACTION <= RATIO;
+ end if;
+end process CHOOSE_FRACTION;
+
+
+DIVISION : DIVIDER
+ port map (NUMERATOR => FRACTION2(19 downto 10),
+ DENOMINATOR => FRACTION2(9 downto 0),
+ RESET => RESET,
+ CLOCK => CLOCK,
+ QUOTIENT => PROB);
+
+PROBUPDATE : UPDATER
+ port map (NUMERATOR => FRACTION2(19 downto 10),
+ DENOMINATOR => FRACTION2(9 downto 0),
+ ENABLE => PROB_CHANGED,
+ DATA_IN => DATA_IN,
+ RESET => RESET,
+ CLOCK => CLOCK,
+ NUMERATOR_OUT => NEWPROB(19 downto 10),
+ DENOMINATOR_OUT => NEWPROB(9 downto 0),
+ UPDATE => UPDATE_PROB);
+
+REFRESH: HALVING_MANAGER
+ port map (TRIGGER_HALVING => HALVECOUNTS,
+ INPUT_READY => DATA_FETCHED,
+ NUMERATOR_IN => FRACTION(19 downto 10),
+ DENOMINATOR_IN => FRACTION(9 downto 0),
+ CONTEXT => CONTEXT_NUMBER,
+ RESET => RESET,
+ CLOCK => CLOCK,
+ NUMERATOR_OUT => FRACTION2(19 downto 10),
+ DENOMINATOR_OUT => FRACTION2(9 downto 0),
+ OUTPUT_READY => PROB_CHANGED);
+
+
+DELAY_CONTEXT : process (CLOCK)
+begin
+ if CLOCK'event and CLOCK = '1' then
+ OLD_CONTEXT <= CONTEXT_NUMBER;
+ end if;
+end process DELAY_CONTEXT;
+
+
+IS_DATA_READY : process (CLOCK)
+begin
+ if CLOCK'event and CLOCK='1' then
+ if RESET='1' then
+ DATA_READY <= "00";
+ else
+ DATA_READY <= DATA_READY(0) & PROB_CHANGED;
+ end if;
+ end if;
+end process IS_DATA_READY;
+
+CONTEXT_LOADED : process (CLOCK)
+begin
+ if CLOCK'event and CLOCK='1' then
+ if RESET='1' then
+ CONTEXT_VALID <= '0';
+ elsif SET = '1' then
+ CONTEXT_VALID <= '1';
+ elsif UPDATE = '1' then
+ CONTEXT_VALID <= '0';
+ end if;
+ end if;
+end process CONTEXT_LOADED;
+
+DATA_FETCHED <= CONTEXT_VALID and not SET;
+
+
+READY <= (DATA_READY(1) and DATA_READY (0));-- and not SET;
+
+
end RTL;
/trunk/src/common/HALVING_MANAGER.vhd
0,0 → 1,169
-- ***** BEGIN LICENSE BLOCK ***** |
-- |
-- |
-- Version: MPL 1.1/GPL 2.0/LGPL 2.1 |
-- |
-- The contents of this file are subject to the Mozilla Public License |
-- Version 1.1 (the "License"); you may not use this file except in compliance |
-- with the License. You may obtain a copy of the License at |
-- http://www.mozilla.org/MPL/ |
-- |
-- Software distributed under the License is distributed on an "AS IS" basis, |
-- WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for |
-- the specific language governing rights and limitations under the License. |
-- |
-- The Original Code is BBC Research and Development code. |
-- |
-- The Initial Developer of the Original Code is the British Broadcasting |
-- Corporation. |
-- Portions created by the Initial Developer are Copyright (C) 2006. |
-- All Rights Reserved. |
-- |
-- Contributor(s): Peter Bleackley (Original author) |
-- |
-- Alternatively, the contents of this file may be used under the terms of |
-- the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser |
-- Public License Version 2.1 (the "LGPL"), in which case the provisions of |
-- the GPL or the LGPL are applicable instead of those above. If you wish to |
-- allow use of your version of this file only under the terms of the either |
-- the GPL or LGPL and not to allow others to use your version of this file |
-- under the MPL, indicate your decision by deleting the provisions above |
-- and replace them with the notice and other provisions required by the GPL |
-- or LGPL. If you do not delete the provisions above, a recipient may use |
-- your version of this file under the terms of any one of the MPL, the GPL |
-- or the LGPL. |
-- * ***** END LICENSE BLOCK ***** */ |
|
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_ARITH.ALL; |
use IEEE.STD_LOGIC_UNSIGNED.ALL; |
|
---- Uncomment the following library declaration if instantiating |
---- any Xilinx primitives in this code. |
--library UNISIM; |
--use UNISIM.VComponents.all; |
|
entity HALVING_MANAGER is |
Port ( TRIGGER_HALVING : in std_logic; |
INPUT_READY : in std_logic; |
NUMERATOR_IN : in std_logic_vector(9 downto 0); |
DENOMINATOR_IN : in std_logic_vector(9 downto 0); |
CONTEXT : in std_logic_vector(5 downto 0); |
RESET : in std_logic; |
CLOCK : in std_logic; |
NUMERATOR_OUT : out std_logic_vector(9 downto 0); |
DENOMINATOR_OUT : out std_logic_vector(9 downto 0); |
OUTPUT_READY : out std_logic); |
end HALVING_MANAGER; |
|
architecture RTL of HALVING_MANAGER is |
type COUNTARRAY is array(45 downto 0) of std_logic_vector(2 downto 0); |
signal SHIFTS : COUNTARRAY; |
signal NUMERATOR : std_logic_vector (9 downto 0); |
signal DENOMINATOR : std_logic_vector (9 downto 0); |
signal NUMERATOR2 : std_logic_vector (9 downto 0); |
signal DENOMINATOR2 : std_logic_vector (9 downto 0); |
signal DENOMINATOR_INCREMENT : std_logic_vector (9 downto 0); |
signal GREATER_THAN_16 : std_logic; |
signal PERFORM_HALVING : std_logic; |
signal AFTER_TRIGGER : std_logic; |
signal LOAD : std_logic; |
signal CALCULATE_VALUES : std_logic; |
|
begin |
|
COUNT_HALVING_EVENTS : process (CLOCK) |
begin |
if CLOCK'event and CLOCK = '1' then |
if RESET = '1' then |
SHIFTS <= (others => "000"); |
elsif TRIGGER_HALVING = '1' then |
for I in 0 to 45 loop |
if SHIFTS(I) /= "111" then |
SHIFTS(I) <= SHIFTS(I) + "001"; |
end if; |
end loop; |
elsif CALCULATE_VALUES = '1' then |
SHIFTS(conv_integer(CONTEXT)) <= SHIFTS(conv_integer(CONTEXT)) - "001"; |
elsif GREATER_THAN_16 = '0' and LOAD = '0' and INPUT_READY = '1' then |
SHIFTS(conv_integer(CONTEXT)) <= "000"; |
end if; |
end if; |
end process COUNT_HALVING_EVENTS; |
|
NUMERATOR2 <= ('0' & NUMERATOR (9 downto 1)) + "0000000001"; |
DENOMINATOR2 <= ('0' & DENOMINATOR(9 downto 1)) + DENOMINATOR_INCREMENT; |
|
HALVE_COUNTS : process (CLOCK) |
begin |
if CLOCK'event and CLOCK='1' then |
if RESET = '1' then |
NUMERATOR <= "0000000001"; |
DENOMINATOR <= "0000000010"; |
elsif CALCULATE_VALUES = '1' then |
NUMERATOR <= NUMERATOR2; |
DENOMINATOR <= DENOMINATOR2; |
elsif LOAD = '1' then |
NUMERATOR <= NUMERATOR_IN; |
DENOMINATOR <= DENOMINATOR_IN; |
end if; |
end if; |
end process HALVE_COUNTS; |
|
HALVING_PERMITTED : process (DENOMINATOR) |
begin |
if DENOMINATOR > "0000010000" then |
GREATER_THAN_16 <= '1'; |
else |
GREATER_THAN_16 <= '0'; |
end if; |
end process HALVING_PERMITTED; |
|
HALVING_ACTIVE : process (INPUT_READY, SHIFTS, CONTEXT, GREATER_THAN_16) |
begin |
if INPUT_READY = '1' and (SHIFTS(conv_integer(CONTEXT)) > "000") then |
PERFORM_HALVING <= GREATER_THAN_16; |
else |
PERFORM_HALVING <= '0'; |
end if; |
end process HALVING_ACTIVE; |
|
SELECT_OUTPUT : process (NUMERATOR_IN, DENOMINATOR_IN, NUMERATOR, DENOMINATOR, TRIGGER_HALVING, PERFORM_HALVING, LOAD) |
begin |
if (LOAD and (TRIGGER_HALVING nor PERFORM_HALVING)) = '1' then |
NUMERATOR_OUT <= NUMERATOR_IN; |
DENOMINATOR_OUT <= DENOMINATOR_IN; |
else |
NUMERATOR_OUT <= NUMERATOR; |
DENOMINATOR_OUT <= DENOMINATOR; |
end if; |
end process SELECT_OUTPUT; |
|
DELAY_TRIGGER : process (CLOCK) |
begin |
if CLOCK'event and CLOCK = '1' then |
if RESET = '1' then |
AFTER_TRIGGER <= '0'; |
else |
AFTER_TRIGGER <= INPUT_READY; |
end if; |
end if; |
end process DELAY_TRIGGER; |
|
CHOOSE_DENOMINATOR_INCREMENT : process (NUMERATOR, DENOMINATOR) |
begin |
if (NUMERATOR (0) = '1') and (DENOMINATOR (0) = '0') then |
DENOMINATOR_INCREMENT <= "0000000001"; |
else |
DENOMINATOR_INCREMENT <= "0000000010"; |
end if; |
end process CHOOSE_DENOMINATOR_INCREMENT; |
|
LOAD <= INPUT_READY and not AFTER_TRIGGER; |
|
CALCULATE_VALUES <= PERFORM_HALVING and AFTER_TRIGGER; |
|
OUTPUT_READY <= INPUT_READY and (PERFORM_HALVING nor TRIGGER_HALVING); |
|
end RTL; |
trunk/src/common/HALVING_MANAGER.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/src/common/Divider.vhd
===================================================================
--- trunk/src/common/Divider.vhd (nonexistent)
+++ trunk/src/common/Divider.vhd (revision 8)
@@ -0,0 +1,1137 @@
+-- ***** BEGIN LICENSE BLOCK *****
+--
+--
+-- Version: MPL 1.1/GPL 2.0/LGPL 2.1
+--
+-- The contents of this file are subject to the Mozilla Public License
+-- Version 1.1 (the "License"); you may not use this file except in compliance
+-- with the License. You may obtain a copy of the License at
+-- http://www.mozilla.org/MPL/
+--
+-- Software distributed under the License is distributed on an "AS IS" basis,
+-- WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
+-- the specific language governing rights and limitations under the License.
+--
+-- The Original Code is BBC Research and Development code.
+--
+-- The Initial Developer of the Original Code is the British Broadcasting
+-- Corporation.
+-- Portions created by the Initial Developer are Copyright (C) 2006.
+-- All Rights Reserved.
+--
+-- Contributor(s): Peter Bleackley (Original author)
+--
+-- Alternatively, the contents of this file may be used under the terms of
+-- the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
+-- Public License Version 2.1 (the "LGPL"), in which case the provisions of
+-- the GPL or the LGPL are applicable instead of those above. If you wish to
+-- allow use of your version of this file only under the terms of the either
+-- the GPL or LGPL and not to allow others to use your version of this file
+-- under the MPL, indicate your decision by deleting the provisions above
+-- and replace them with the notice and other provisions required by the GPL
+-- or LGPL. If you do not delete the provisions above, a recipient may use
+-- your version of this file under the terms of any one of the MPL, the GPL
+-- or the LGPL.
+-- * ***** END LICENSE BLOCK ***** */
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+-- Uncomment the following lines to use the declarations that are
+-- provided for instantiating Xilinx primitive components.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity Divider is
+ Port ( NUMERATOR : in std_logic_vector(9 downto 0);
+ DENOMINATOR : in std_logic_vector(9 downto 0);
+ RESET : in std_logic;
+ CLOCK : in std_logic;
+ QUOTIENT : out std_logic_vector(9 downto 0));
+end Divider;
+
+architecture RTL of Divider is
+ signal NUMERATOR2 : std_logic_vector(9 downto 0);
+ signal DENOMINATOR2 : std_logic_vector( 9 downto 0);
+ signal RECIPROCAL : std_logic_vector(31 downto 0);
+ signal PRODUCT1 : std_logic_vector(25 downto 0);
+ signal PRODUCT2 : std_logic_vector(25 downto 0);
+ signal TOTAL : std_logic_vector(41 downto 0);
+ signal INDEX : std_logic_vector (9 downto 0);
+ type ROM is array (1021 downto 0) of std_logic_vector(31 downto 0);
+ constant LUT : ROM := ("00000000010000000001000000000100",
+"00000000010000000010000000010000",
+"00000000010000000011000000100100",
+"00000000010000000100000001000000",
+"00000000010000000101000001100100",
+"00000000010000000110000010010000",
+"00000000010000000111000011000101",
+"00000000010000001000000100000010",
+"00000000010000001001000101000110",
+"00000000010000001010000110010011",
+"00000000010000001011000111101001",
+"00000000010000001100001001000110",
+"00000000010000001101001010101100",
+"00000000010000001110001100011010",
+"00000000010000001111001110010001",
+"00000000010000010000010000010000",
+"00000000010000010001010010010111",
+"00000000010000010010010100100111",
+"00000000010000010011010110111111",
+"00000000010000010100011001011111",
+"00000000010000010101011100001000",
+"00000000010000010110011110111010",
+"00000000010000010111100001110100",
+"00000000010000011000100100110111",
+"00000000010000011001101000000010",
+"00000000010000011010101011010110",
+"00000000010000011011101110110010",
+"00000000010000011100110010011000",
+"00000000010000011101110110000110",
+"00000000010000011110111001111100",
+"00000000010000011111111101111100",
+"00000000010000100001000010000100",
+"00000000010000100010000110010101",
+"00000000010000100011001010101110",
+"00000000010000100100001111010001",
+"00000000010000100101010011111100",
+"00000000010000100110011000110001",
+"00000000010000100111011101101110",
+"00000000010000101000100010110100",
+"00000000010000101001101000000100",
+"00000000010000101010101101011100",
+"00000000010000101011110010111101",
+"00000000010000101100111000101000",
+"00000000010000101101111110011011",
+"00000000010000101111000100011000",
+"00000000010000110000001010011110",
+"00000000010000110001010000101101",
+"00000000010000110010010111000101",
+"00000000010000110011011101100110",
+"00000000010000110100100100010001",
+"00000000010000110101101011000101",
+"00000000010000110110110010000010",
+"00000000010000110111111001001001",
+"00000000010000111001000000011001",
+"00000000010000111010000111110010",
+"00000000010000111011001111010101",
+"00000000010000111100010111000010",
+"00000000010000111101011110110111",
+"00000000010000111110100110110111",
+"00000000010000111111101111000000",
+"00000000010001000000110111010010",
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+"00000000010001000011001000010100",
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+"00000000010001000101011001111101",
+"00000000010001000110100011000000",
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+"00000000010001001000110101100011",
+"00000000010001001001111111000011",
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+"00000000010001001101011100100000",
+"00000000010001001110100110101000",
+"00000000010001001111110000111010",
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+"00000000010001010010000101111100",
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+"00000000010001010111111101010010",
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+"00000000010001011010010100100010",
+"00000000010001011011100000011010",
+"00000000010001011100101100011100",
+"00000000010001011101111000101000",
+"00000000010001011111000100111111",
+"00000000010001100000010001100000",
+"00000000010001100001011110001011",
+"00000000010001100010101011000010",
+"00000000010001100011111000000010",
+"00000000010001100101000101001110",
+"00000000010001100110010010100011",
+"00000000010001100111100000000100",
+"00000000010001101000101101101111",
+"00000000010001101001111011100101",
+"00000000010001101011001001100110",
+"00000000010001101100010111110001",
+"00000000010001101101100110000111",
+"00000000010001101110110100101001",
+"00000000010001110000000011010101",
+"00000000010001110001010010001011",
+"00000000010001110010100001001101",
+"00000000010001110011110000011010",
+"00000000010001110100111111110010",
+"00000000010001110110001111010101",
+"00000000010001110111011111000011",
+"00000000010001111000101110111100",
+"00000000010001111001111111000001",
+"00000000010001111011001111010000",
+"00000000010001111100011111101011",
+"00000000010001111101110000010001",
+"00000000010001111111000001000011",
+"00000000010010000000010010000000",
+"00000000010010000001100011001000",
+"00000000010010000010110100011100",
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+"00000010110110000010110110000010",
+"00000010111000000101110000001011",
+"00000010111010001011101000101110",
+"00000010111100010100100110010000",
+"00000010111110100000101111101000",
+"00000011000000110000001100000011",
+"00000011000011000011000011000011",
+"00000011000101011001011100100001",
+"00000011000111110011100000110001",
+"00000011001010010001011000011111",
+"00000011001100110011001100110011",
+"00000011001111011001000111010010",
+"00000011010010000011010010000011",
+"00000011010100110001110111101100",
+"00000011010111100101000011010111",
+"00000011011010011101000000110110",
+"00000011011101011001111100100010",
+"00000011100000011100000011100000",
+"00000011100011100011100011100011",
+"00000011100110110000101011010001",
+"00000011101010000011101010000011",
+"00000011101101011100110000001110",
+"00000011110000111100001111000011",
+"00000011110100100010011000110101",
+"00000011111000001111100000111110",
+"00000011111100000011111100000011",
+"00000100000000000000000000000000",
+"00000100000100000100000100000100",
+"00000100001000010000100001000010",
+"00000100001100100101110001010011",
+"00000100010001000100010001000100",
+"00000100010101101100011110010111",
+"00000100011010011110111001011000",
+"00000100011111011100000100011111",
+"00000100100100100100100100100100",
+"00000100101001111001000001001010",
+"00000100101111011010000100101111",
+"00000100110101001000011100111110",
+"00000100111011000100111011000100",
+"00000101000001010000010100000101",
+"00000101000111101011100001010001",
+"00000101001110010111100000101001",
+"00000101010101010101010101010101",
+"00000101011100100110001000001010",
+"00000101100100001011001000010110",
+"00000101101100000101101100000101",
+"00000101110100010111010001011101",
+"00000101111101000001011111010000",
+"00000110000110000110000110000110",
+"00000110001111100111000001100011",
+"00000110011001100110011001100110",
+"00000110100100000110100100000110",
+"00000110101111001010000110101111",
+"00000110111010110011111001000101",
+"00000111000111000111000111000111",
+"00000111010100000111010100000111",
+"00000111100001111000011110000111",
+"00000111110000011111000001111100",
+"00001000000000000000000000000000",
+"00001000010000100001000010000100",
+"00001000100010001000100010001000",
+"00001000110100111101110010110000",
+"00001001001001001001001001001001",
+"00001001011110110100001001011110",
+"00001001110110001001110110001001",
+"00001010001111010111000010100011",
+"00001010101010101010101010101010",
+"00001011001000010110010000101100",
+"00001011101000101110100010111010",
+"00001100001100001100001100001100",
+"00001100110011001100110011001100",
+"00001101011110010100001101011110",
+"00001110001110001110001110001110",
+"00001111000011110000111100001111",
+"00010000000000000000000000000000",
+"00010001000100010001000100010001",
+"00010010010010010010010010010010",
+"00010011101100010011101100010011",
+"00010101010101010101010101010101",
+"00010111010001011101000101110100",
+"00011001100110011001100110011001",
+"00011100011100011100011100011100",
+"00100000000000000000000000000000",
+"00100100100100100100100100100100",
+"00101010101010101010101010101010",
+"00110011001100110011001100110011",
+"01000000000000000000000000000000",
+"01010101010101010101010101010101",
+"10000000000000000000000000000000"
+ );
+begin
+
+INIT : process(DENOMINATOR,RESET)
+begin
+ if RESET = '1' then
+ DENOMINATOR2 <= "0000000010";
+ else
+ DENOMINATOR2 <= DENOMINATOR;
+ end if;
+end process INIT;
+
+SETNUMERATOR : process (CLOCK)
+begin
+ if CLOCK'event and CLOCK = '1' then
+ if RESET = '1' then
+ NUMERATOR2 <= "0000000001";
+ else
+ NUMERATOR2 <= NUMERATOR;
+ end if;
+ end if;
+end process SETNUMERATOR;
+
+
+INDEX <= DENOMINATOR2 - "0000000010";
+
+LOOKUP: process(CLOCK)
+begin
+ if CLOCK'event and CLOCK = '1' then
+ RECIPROCAL <= LUT(conv_integer(INDEX));
+ end if;
+end process LOOKUP;
+
+DIVIDE1: process(CLOCK)
+begin
+ if CLOCK'event and CLOCK='1' then
+ PRODUCT1<=NUMERATOR2*RECIPROCAL(31 downto 16);
+ end if;
+end process DIVIDE1;
+
+DIVIDE2: process(CLOCK)
+begin
+ if CLOCK'event and CLOCK='1' then
+ PRODUCT2<=NUMERATOR2*RECIPROCAL(15 downto 0);
+ end if;
+end process DIVIDE2;
+
+TOTAL<=((PRODUCT1 & "0000000000000000") + ("0000000000000000" & PRODUCT2));
+QUOTIENT <= TOTAL(31 downto 22);
+
+
+end RTL;
trunk/src/common/Divider.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/src/common/context_manager.prj
===================================================================
--- trunk/src/common/context_manager.prj (revision 7)
+++ trunk/src/common/context_manager.prj (revision 8)
@@ -1 +1,4 @@
+vhdl work HALVING_MANAGER.vhd
+vhdl work UPDATER.vhd
+vhdl work DIVIDER.vhd
vhdl work CONTEXT_MANAGER.vhd