OpenCores
URL https://opencores.org/ocsvn/hpc-16/hpc-16/trunk

Subversion Repositories hpc-16

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Rev 7 → Rev 8

/trunk/impl0/rtl/vhdl/con1.vhd
92,8 → 92,9
marin_mux_sel : out std_logic_vector(1 downto 0);
mar_ce : out std_logic;
mdroin_mux_sel : out std_logic_vector(2 downto 0);
mdro_ce : out std_logic; -- mdro rst are removed
mdro_oe : out std_logic
mdro_ce : out std_logic;
mdro_oe : out std_logic;
rst2 : out std_logic -- @new
);
end con1;
architecture rtl of con1 is
103,29 → 104,68
signal cur_state , nxt_state : state;
signal cur_ic : ic;
signal asopsel : std_logic_vector(3 downto 0);
 
signal rsync_stage0 : std_logic;
 
signal isync_stage0 : std_logic;
signal isync_stage1 : std_logic;
signal isync_stage2 : std_logic;
signal isync : std_logic;
signal intr_sync_rst : std_logic;
signal isync_status : std_logic_vector(1 downto 0);
begin
rsync : sync
port map
(
d => RST_I, clk => CLK_I, q => rst_sync
);
async : sync
port map
(
d => ACK_I, clk => CLK_I, q => ack_sync
);
isync : sync
port map
(
d => INTR_I, clk => CLK_I, q => intr_sync
);
process(CLK_I)
begin
if rising_edge(CLK_I) then
rsync_stage0 <= RST_I;
rst_sync <= rsync_stage0;
end if;
end process;
 
process(CLK_I, rst_sync)
begin
if rst_sync = '1' then
ack_sync <= '0';
elsif rising_edge(CLK_I)then
ack_sync <= ACK_I;
end if;
end process;
process(CLK_I, rst_sync)
begin
if rst_sync = '1' then
isync_stage0 <= '0';
isync_stage1 <= '0';
isync_stage2 <= '0';
elsif rising_edge(CLK_I)then
isync_stage0 <= INTR_I;
isync_stage1 <= isync_stage0;
isync_stage2 <= isync_stage1;
end if;
end process;
isync <= isync_stage0 and isync_stage1 and not isync_stage2;
isync_status <= intr_sync_rst & isync;
process(CLK_I, rst_sync)
begin
if rst_sync = '1' then
intr_sync <= '0';
elsif rising_edge(CLK_I) then
case isync_status is
when "10" | "00"=> intr_sync <= '0';
when "11" | "01"=> intr_sync <= '1';
when others => intr_sync <= '0';
end case;
end if;
end process;
process(CLK_I, rst_sync)
begin
if rst_sync = '1' then
cur_state <= reset;
elsif rising_edge(CLK_I) then
cur_state <= nxt_state;
188,7 → 228,7
ic_hlt when ir_high(7 downto 3) = hlt else
ic_invalid;
 
process(cur_state, cur_ic, jcc_ok, int_flag, pc0, sp0, tr20, mar0, ir_high(2 downto 0),
process(cur_state, cur_ic, jcc_ok, int_flag, pc0, sp0, tr20, mar0, ir_high,
ack_sync, intr_sync, rst_sync)
begin
SEL_O <= "00";
231,12 → 271,18
dfh_ce <= '0';
mdroin_mux_sel <= "000";
mdro_ce <= '0';
mdro_oe <= '0';
mdro_oe <= '0';
rst2 <= '0'; -- @new
case cur_state is
--//////////////////////////////////////
when reset =>
pc_pre <= '1'; flags_rst <= '1';
pc_pre <= '1';
flags_rst <= '1';
-- @new start
sp_pre <= '1';
rst2 <= '1';
-- @new end
if rst_sync = '0' then
nxt_state <= fetch0;
else
261,7 → 307,7
end if;
--///////////////////////////////////////
when fetch1 =>
-- read instruction
-- read instruction; note STB_O is one shot
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; I_CYC_O <= '1';
-- prepare ir
ir_ce <= '1';
273,8 → 319,8
-- read end
nxt_state <= exec0;
else
-- continue read & prepare ir
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; I_CYC_O <= '1';
-- continue read & prepare ir
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; I_CYC_O <= '1';
ir_ce <= '1';
--
nxt_state <= fetch2;
780,7 → 826,7
nxt_state <= int_chk;
----------------------------------------------
when ic_hlt =>
flags_sti <= '1';
--flags_sti <= '1';
nxt_state <= halted;
----------------------------------------------
when ic_invalid =>
856,7 → 902,7
nxt_state <= int_chk;
--------------------------------------------
when others =>
null;
nxt_state <= halted; -- @new
end case;
--///////////////////////////////////////
when exec2 =>
871,7 → 917,7
nxt_state <= int_chk;
else
-- try reading data word
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; D_CYC_O <= '1';
-- prepare mdri
mdri_ce <= '1';
--
891,7 → 937,7
nxt_state <= exec3;
else
-- try reading const word data
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; C_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; C_CYC_O <= '1';
-- prepare mdri
mdri_ce <= '1';
--
910,7 → 956,7
nxt_state <= exec3;
else
-- try reading const word data
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; C_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; C_CYC_O <= '1';
-- prepare mdri
mdri_ce <= '1';
--
933,7 → 979,7
nxt_state <= exec3;
else
-- try reading const word data
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; C_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; C_CYC_O <= '1';
-- prepare mdri
mdri_ce <= '1';
--
956,7 → 1002,7
nxt_state <= exec3;
else
-- try reading const word data
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; C_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; C_CYC_O <= '1';
-- prepare mdri
mdri_ce <= '1';
--
969,7 → 1015,7
else
mdro_oe <= '1';
-- try write data word
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
--
nxt_state <= exec2;
end if;
992,7 → 1038,7
else
SEL_O <= "01";
end if;
STB_O <= '1'; CYC_O <= '1'; D_CYC_O <= '1';
STB_O <= '0'; CYC_O <= '1'; D_CYC_O <= '1';
--
mdri_ce <= '1';
--
1017,7 → 1063,7
else
SEL_O <= "01";
end if;
STB_O <= '1'; CYC_O <= '1'; D_CYC_O <= '1';
STB_O <= '0'; CYC_O <= '1'; D_CYC_O <= '1';
--
mdri_ce <= '1';
--
1035,7 → 1081,7
else
SEL_O <= "01";
end if;
STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
STB_O <= '0'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
--
nxt_state <= exec2;
end if;
1051,7 → 1097,7
nxt_state <= exec3;
else
-- try reading const word data
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; C_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; C_CYC_O <= '1';
-- prepare mdri
mdri_ce <= '1';
--
1067,7 → 1113,7
nxt_state <= int_chk;
else
-- try reading const word
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; C_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; C_CYC_O <= '1';
-- prepare mdri
mdri_ce <= '1';
--
1083,7 → 1129,7
nxt_state <= int_chk;
else
-- try reading const word
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; C_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; C_CYC_O <= '1';
-- prepare mdri
mdri_ce <= '1';
--
1121,7 → 1167,7
nxt_state <= exec3;
else
-- try reading const word
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; C_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; C_CYC_O <= '1';
-- prepare mdri
mdri_ce <= '1';
--
1142,7 → 1188,7
nxt_state <= int_chk;
else
-- try reading const word
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; C_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; C_CYC_O <= '1';
-- prepare mdri
mdri_ce <= '1';
--
1163,7 → 1209,7
nxt_state <= int_chk;
else
-- try reading const word
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; C_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; C_CYC_O <= '1';
-- prepare mdri
mdri_ce <= '1';
--
1182,7 → 1228,7
nxt_state <= int_chk;
else
-- try reading const word
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; C_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; C_CYC_O <= '1';
-- prepare mdri
mdri_ce <= '1';
--
1201,7 → 1247,7
nxt_state <= int_chk;
else
-- try reading const word
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; C_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; C_CYC_O <= '1';
-- prepare mdri
mdri_ce <= '1';
--
1214,7 → 1260,7
else
mdro_oe <= '1';
-- try writing data word
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
--
nxt_state <= exec2;
end if;
1227,7 → 1273,7
nxt_state <= int_chk;
else
-- try reading data word
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; D_CYC_O <= '1';
--
mdri_ce <= '1';
--
1245,7 → 1291,7
nxt_state <= int_chk;
else
-- try reading word data
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; D_CYC_O <= '1';
--
mdri_ce <= '1';
--
1265,7 → 1311,7
else
mdro_oe <= '1';
-- try writing data word
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
--
nxt_state <= exec2;
end if;
1283,7 → 1329,7
else
mdro_oe <= '1';
-- try writing data word
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
--
nxt_state <= exec2;
end if;
1301,7 → 1347,7
else
mdro_oe <= '1';
-- try writing data word
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
--
nxt_state <= exec2;
end if;
1315,7 → 1361,7
nxt_state <= int_chk;
else
-- try reading data word
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; D_CYC_O <= '1';
--
mdri_ce <= '1';
--
1342,7 → 1388,7
else
mdro_oe <= '1';
-- try writing data word
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
--
nxt_state <= exec2;
end if;
1364,7 → 1410,7
nxt_state <= exec3;
else
-- try reading data word
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; D_CYC_O <= '1';
--
mdri_ce <= '1';
--
1372,7 → 1418,7
end if;
--------------------------------------------
when others =>
null;
nxt_state <= halted; -- @new
-------------------------------------------
end case;
--///////////////////////////////////////
1447,7 → 1493,7
nxt_state <= exec4;
----------------------------------------------
when others =>
null;
nxt_state <= halted; -- @new
----------------------------------------------
end case;
--///////////////////////////////////////
1463,7 → 1509,7
else
mdri_ce <= '1';
-- read data word
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; D_CYC_O <= '1';
--
nxt_state <= exec4;
end if;
1474,7 → 1520,7
else
mdro_oe <= '1';
-- write data word
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
--
nxt_state <= exec4;
end if;
1497,7 → 1543,7
else
SEL_O <= "01";
end if;
STB_O <= '1'; CYC_O <= '1'; D_CYC_O <= '1';
STB_O <= '0'; CYC_O <= '1'; D_CYC_O <= '1';
--
nxt_state <= exec4;
end if;
1520,7 → 1566,7
else
SEL_O <= "01";
end if;
STB_O <= '1'; CYC_O <= '1'; D_CYC_O <= '1';
STB_O <= '0'; CYC_O <= '1'; D_CYC_O <= '1';
--
nxt_state <= exec4;
end if;
1548,7 → 1594,7
else
mdro_oe <= '1';
-- write word
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
--
nxt_state <= exec4;
end if;
1565,13 → 1611,13
else
mdri_ce <= '1';
-- try reading word
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; D_CYC_O <= '1';
--
nxt_state <= exec4;
end if;
----------------------------------------------
when others =>
null;
nxt_state <= halted; -- @new
----------------------------------------------
end case;
--///////////////////////////////////////
1588,12 → 1634,12
else
SEL_O <= "01";
end if;
STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
STB_O <= '0'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
--
nxt_state <= exec5;
end if;
when others =>
null;
nxt_state <= halted; -- @new
end case;
--///////////////////////////////////////
when int_chk =>
1603,6 → 1649,10
SEL_O <= "10"; STB_O <= '1'; CYC_O <= '1'; INTA_CYC_O <= '1';
-- prepare intr
intr_ce <= '1';
-- clear intr_sync
intr_sync_rst <= '1';
-- clear IF
flags_cli <= '1';
--
nxt_state <= int0;
else
1643,7 → 1693,7
end if;
else
-- try reading vector number
SEL_O <= "10"; STB_O <= '1'; CYC_O <= '1'; INTA_CYC_O <= '1';
SEL_O <= "10"; STB_O <= '0'; CYC_O <= '1'; INTA_CYC_O <= '1';
--
intr_ce <= '1';
--
1677,7 → 1727,7
nxt_state <= int3;
else
-- try writing data word (flags)
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
--
mdro_oe <= '1';
--
1701,7 → 1751,7
nxt_state <= fetch0;
else
-- writing pc
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
--
mdro_oe <= '1';
--
1766,7 → 1816,7
nxt_state <= invalid3;
else
-- try writing data word (flags)
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
--
mdro_oe <= '1';
--
1790,7 → 1840,7
nxt_state <= fetch0;
else
-- writing pc
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
--
mdro_oe <= '1';
--
1855,7 → 1905,7
nxt_state <= align3;
else
-- try writing data word (flags)
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
--
mdro_oe <= '1';
--
1879,7 → 1929,7
nxt_state <= fetch0;
else
-- writing pc
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
--
mdro_oe <= '1';
--
1930,7 → 1980,7
--
nxt_state <= stkerr4;
else
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
mdro_oe <= '1';
nxt_state <= stkerr3;
end if;
1958,7 → 2008,7
--
nxt_state <= stkerr6;
else
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
mdro_oe <= '1';
nxt_state <= stkerr5;
end if;
1977,7 → 2027,7
nxt_state <= fetch0;
else
-- writing pc
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
--
mdro_oe <= '1';
--
2024,7 → 2074,7
--
nxt_state <= df4;
else
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
mdro_oe <= '1';
nxt_state <= df3;
end if;
2052,7 → 2102,7
--
nxt_state <= df6;
else
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
mdro_oe <= '1';
nxt_state <= df5;
end if;
2080,7 → 2130,7
--
nxt_state <= df8;
else
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
mdro_oe <= '1';
nxt_state <= df7;
end if;
2099,7 → 2149,7
nxt_state <= fetch0;
else
-- writing pc
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
--
mdro_oe <= '1';
--
/trunk/impl0/rtl/vhdl/nontri/con1.vhd
97,7 → 97,8
marin_mux_sel : out std_logic_vector(1 downto 0);
mar_ce : out std_logic;
mdroin_mux_sel : out std_logic_vector(2 downto 0);
mdro_ce : out std_logic
mdro_ce : out std_logic;
rst2 : out std_logic -- @new
);
end con1;
architecture rtl of con1 is
107,25 → 108,63
signal cur_state , nxt_state : state;
signal cur_ic : ic;
signal asopsel : std_logic_vector(3 downto 0);
signal rsync_stage0 : std_logic;
 
signal isync_stage0 : std_logic;
signal isync_stage1 : std_logic;
signal isync_stage2 : std_logic;
signal isync : std_logic;
signal intr_sync_rst : std_logic;
signal isync_status : std_logic_vector(1 downto 0);
begin
rsync : sync
port map
(
d => RST_I, clk => CLK_I, q => rst_sync
);
async : sync
port map
(
d => ACK_I, clk => CLK_I, q => ack_sync
);
process(CLK_I)
begin
if rising_edge(CLK_I) then
rsync_stage0 <= RST_I;
rst_sync <= rsync_stage0;
end if;
end process;
 
process(CLK_I, rst_sync)
begin
if rst_sync = '1' then
ack_sync <= '0';
elsif rising_edge(CLK_I)then
ack_sync <= ACK_I;
end if;
end process;
isync : sync
port map
(
d => INTR_I, clk => CLK_I, q => intr_sync
);
process(CLK_I, rst_sync)
begin
if rst_sync = '1' then
isync_stage0 <= '0';
isync_stage1 <= '0';
isync_stage2 <= '0';
elsif rising_edge(CLK_I)then
isync_stage0 <= INTR_I;
isync_stage1 <= isync_stage0;
isync_stage2 <= isync_stage1;
end if;
end process;
isync <= isync_stage0 and isync_stage1 and not isync_stage2;
isync_status <= intr_sync_rst & isync;
process(CLK_I, rst_sync)
begin
if rst_sync = '1' then
intr_sync <= '0';
elsif rising_edge(CLK_I) then
case isync_status is
when "10" | "00"=> intr_sync <= '0';
when "11" | "01"=> intr_sync <= '1';
when others => intr_sync <= '0';
end case;
end if;
end process;
 
process(CLK_I, rst_sync)
begin
234,12 → 273,18
mar_ce <= '0';
dfh_ce <= '0';
mdroin_mux_sel <= "000";
mdro_ce <= '0';
mdro_ce <= '0';
rst2 <= '0'; -- @new
case cur_state is
--//////////////////////////////////////
when reset =>
pc_pre <= '1'; flags_rst <= '1';
pc_pre <= '1';
flags_rst <= '1';
-- @new start
sp_pre <= '1';
rst2 <= '1';
-- @new end
if rst_sync = '0' then
nxt_state <= fetch0;
else
264,7 → 309,7
end if;
--///////////////////////////////////////
when fetch1 =>
-- read instruction
-- read instruction; note STB_O is one shot
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; I_CYC_O <= '1';
-- prepare ir
ir_ce <= '1';
277,7 → 322,7
nxt_state <= exec0;
else
-- continue read & prepare ir
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; I_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; I_CYC_O <= '1';
ir_ce <= '1';
--
nxt_state <= fetch2;
773,7 → 818,7
nxt_state <= int_chk;
----------------------------------------------
when ic_hlt =>
flags_sti <= '1';
--flags_sti <= '1';
nxt_state <= halted;
----------------------------------------------
when ic_invalid =>
847,7 → 892,7
nxt_state <= int_chk;
--------------------------------------------
when others =>
null;
nxt_state <= halted; -- @new
end case;
--///////////////////////////////////////
when exec2 =>
862,7 → 907,7
nxt_state <= int_chk;
else
-- try reading data word
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; D_CYC_O <= '1';
-- prepare mdri
mdri_ce <= '1';
--
882,7 → 927,7
nxt_state <= exec3;
else
-- try reading const word data
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; C_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; C_CYC_O <= '1';
-- prepare mdri
mdri_ce <= '1';
--
901,7 → 946,7
nxt_state <= exec3;
else
-- try reading const word data
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; C_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; C_CYC_O <= '1';
-- prepare mdri
mdri_ce <= '1';
--
923,7 → 968,7
nxt_state <= exec3;
else
-- try reading const word data
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; C_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; C_CYC_O <= '1';
-- prepare mdri
mdri_ce <= '1';
--
945,7 → 990,7
nxt_state <= exec3;
else
-- try reading const word data
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; C_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; C_CYC_O <= '1';
-- prepare mdri
mdri_ce <= '1';
--
957,7 → 1002,7
nxt_state <= int_chk;
else
-- try write data word
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
--
nxt_state <= exec2;
end if;
980,7 → 1025,7
else
SEL_O <= "01";
end if;
STB_O <= '1'; CYC_O <= '1'; D_CYC_O <= '1';
STB_O <= '0'; CYC_O <= '1'; D_CYC_O <= '1';
--
mdri_ce <= '1';
--
1005,7 → 1050,7
else
SEL_O <= "01";
end if;
STB_O <= '1'; CYC_O <= '1'; D_CYC_O <= '1';
STB_O <= '0'; CYC_O <= '1'; D_CYC_O <= '1';
--
mdri_ce <= '1';
--
1022,7 → 1067,7
else
SEL_O <= "01";
end if;
STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
STB_O <= '0'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
--
nxt_state <= exec2;
end if;
1038,7 → 1083,7
nxt_state <= exec3;
else
-- try reading const word data
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; C_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; C_CYC_O <= '1';
-- prepare mdri
mdri_ce <= '1';
--
1054,7 → 1099,7
nxt_state <= int_chk;
else
-- try reading const word
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; C_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; C_CYC_O <= '1';
-- prepare mdri
mdri_ce <= '1';
--
1070,7 → 1115,7
nxt_state <= int_chk;
else
-- try reading const word
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; C_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; C_CYC_O <= '1';
-- prepare mdri
mdri_ce <= '1';
--
1108,7 → 1153,7
nxt_state <= exec3;
else
-- try reading const word
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; C_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; C_CYC_O <= '1';
-- prepare mdri
mdri_ce <= '1';
--
1129,7 → 1174,7
nxt_state <= int_chk;
else
-- try reading const word
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; C_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; C_CYC_O <= '1';
-- prepare mdri
mdri_ce <= '1';
--
1150,7 → 1195,7
nxt_state <= int_chk;
else
-- try reading const word
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; C_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; C_CYC_O <= '1';
-- prepare mdri
mdri_ce <= '1';
--
1169,7 → 1214,7
nxt_state <= int_chk;
else
-- try reading const word
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; C_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; C_CYC_O <= '1';
-- prepare mdri
mdri_ce <= '1';
--
1188,7 → 1233,7
nxt_state <= int_chk;
else
-- try reading const word
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; C_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; C_CYC_O <= '1';
-- prepare mdri
mdri_ce <= '1';
--
1200,7 → 1245,7
nxt_state <= int_chk;
else
-- try writing data word
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
--
nxt_state <= exec2;
end if;
1213,7 → 1258,7
nxt_state <= int_chk;
else
-- try reading data word
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; D_CYC_O <= '1';
--
mdri_ce <= '1';
--
1231,7 → 1276,7
nxt_state <= int_chk;
else
-- try reading word data
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; D_CYC_O <= '1';
--
mdri_ce <= '1';
--
1250,7 → 1295,7
nxt_state <= int_chk;
else
-- try writing data word
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
--
nxt_state <= exec2;
end if;
1267,7 → 1312,7
nxt_state <= int_chk;
else
-- try writing data word
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
--
nxt_state <= exec2;
end if;
1284,7 → 1329,7
nxt_state <= int_chk;
else
-- try writing data word
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
--
nxt_state <= exec2;
end if;
1298,7 → 1343,7
nxt_state <= int_chk;
else
-- try reading data word
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; D_CYC_O <= '1';
--
mdri_ce <= '1';
--
1323,7 → 1368,7
nxt_state <= exec3;
else
-- try writing data word
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
--
nxt_state <= exec2;
end if;
1345,7 → 1390,7
nxt_state <= exec3;
else
-- try reading data word
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; D_CYC_O <= '1';
--
mdri_ce <= '1';
--
1353,7 → 1398,7
end if;
--------------------------------------------
when others =>
null;
nxt_state <= halted; -- @new
-------------------------------------------
end case;
--///////////////////////////////////////
1425,7 → 1470,7
nxt_state <= exec4;
----------------------------------------------
when others =>
null;
nxt_state <= halted; -- @new
----------------------------------------------
end case;
--///////////////////////////////////////
1441,7 → 1486,7
else
mdri_ce <= '1';
-- read data word
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; D_CYC_O <= '1';
--
nxt_state <= exec4;
end if;
1451,7 → 1496,7
nxt_state <= int_chk;
else
-- write data word
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
--
nxt_state <= exec4;
end if;
1474,7 → 1519,7
else
SEL_O <= "01";
end if;
STB_O <= '1'; CYC_O <= '1'; D_CYC_O <= '1';
STB_O <= '0'; CYC_O <= '1'; D_CYC_O <= '1';
--
nxt_state <= exec4;
end if;
1497,7 → 1542,7
else
SEL_O <= "01";
end if;
STB_O <= '1'; CYC_O <= '1'; D_CYC_O <= '1';
STB_O <= '0'; CYC_O <= '1'; D_CYC_O <= '1';
--
nxt_state <= exec4;
end if;
1523,7 → 1568,7
nxt_state <= int_chk;
else
-- write word
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
--
nxt_state <= exec4;
end if;
1540,13 → 1585,13
else
mdri_ce <= '1';
-- try reading word
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; D_CYC_O <= '1';
--
nxt_state <= exec4;
end if;
----------------------------------------------
when others =>
null;
nxt_state <= halted; -- @new;
----------------------------------------------
end case;
--///////////////////////////////////////
1562,12 → 1607,12
else
SEL_O <= "01";
end if;
STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
STB_O <= '0'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
--
nxt_state <= exec5;
end if;
when others =>
null;
nxt_state <= halted; -- @new
end case;
--///////////////////////////////////////
when int_chk =>
1577,6 → 1622,10
SEL_O <= "10"; STB_O <= '1'; CYC_O <= '1'; INTA_CYC_O <= '1';
-- prepare intr
intr_ce <= '1';
-- clear intr_sync
intr_sync_rst <= '1';
-- clear IF
flags_cli <= '1';
--
nxt_state <= int0;
else
1615,7 → 1664,7
end if;
else
-- try reading vector number
SEL_O <= "10"; STB_O <= '1'; CYC_O <= '1'; INTA_CYC_O <= '1';
SEL_O <= "10"; STB_O <= '0'; CYC_O <= '1'; INTA_CYC_O <= '1';
--
intr_ce <= '1';
--
1647,7 → 1696,7
nxt_state <= int3;
else
-- try writing data word (flags)
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
--
--
nxt_state <= int2;
1669,7 → 1718,7
nxt_state <= fetch0;
else
-- writing pc
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
--
--
nxt_state <= int4;
1729,7 → 1778,7
nxt_state <= invalid3;
else
-- try writing data word (flags)
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
--
--
nxt_state <= invalid2;
1751,7 → 1800,7
nxt_state <= fetch0;
else
-- writing pc
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
--
--
nxt_state <= invalid4;
1811,7 → 1860,7
nxt_state <= align3;
else
-- try writing data word (flags)
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
--
--
nxt_state <= align2;
1833,7 → 1882,7
nxt_state <= fetch0;
else
-- writing pc
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
--
--
nxt_state <= align4;
1880,7 → 1929,7
--
nxt_state <= stkerr4;
else
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
nxt_state <= stkerr3;
end if;
--///////////////////////////////////////
1905,7 → 1954,7
--
nxt_state <= stkerr6;
else
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
nxt_state <= stkerr5;
end if;
--///////////////////////////////////////
1922,7 → 1971,7
nxt_state <= fetch0;
else
-- writing pc
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
--
--
nxt_state <= stkerr7;
1966,7 → 2015,7
--
nxt_state <= df4;
else
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
nxt_state <= df3;
end if;
--///////////////////////////////////////
1991,7 → 2040,7
--
nxt_state <= df6;
else
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
nxt_state <= df5;
end if;
--///////////////////////////////////////
2016,7 → 2065,7
--
nxt_state <= df8;
else
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
nxt_state <= df7;
end if;
--///////////////////////////////////////
2033,7 → 2082,7
nxt_state <= fetch0;
else
-- writing pc
SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
SEL_O <= "11"; STB_O <= '0'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
--
--
nxt_state <= df9;
/trunk/impl0/rtl/vhdl/arith_arch_neutral.vhd
0,0 → 1,84
--------------------------------------------------------------
-- arith_arch_neutral.vhd
--------------------------------------------------------------
-- project: HPC-16 Microprocessor
--
-- usage: Generic Arithmetic unit of hpc-16 ALU
--
-- dependency: con_pkg.vhd
--
-- Author: M. Umair Siddiqui (umairsiddiqui@opencores.org)
---------------------------------------------------------------
------------------------------------------------------------------------------------
-- --
-- Copyright (c) 2005, M. Umair Siddiqui all rights reserved --
-- --
-- This file is part of HPC-16. --
-- --
-- HPC-16 is free software; you can redistribute it and/or modify --
-- it under the terms of the GNU Lesser General Public License as published by --
-- the Free Software Foundation; either version 2.1 of the License, or --
-- (at your option) any later version. --
-- --
-- HPC-16 is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU Lesser General Public License for more details. --
-- --
-- You should have received a copy of the GNU Lesser General Public License --
-- along with HPC-16; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
------------------------------------------------------------------------------------
library IEEE;
 
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity arith is
PORT( c_out : OUT STD_LOGIC;
ofl_out : OUT STD_LOGIC;
s0 : IN STD_LOGIC;
c_in : IN STD_LOGIC;
s1 : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
b : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
end arith;
 
--(s1,s0)---|--Operation--
---00-------|--sub--------
---01-------|--add--------
---10-------|--sbb--------
---11-------|--adc--------
 
architecture rtl of arith is
signal ci : std_logic;
signal sum : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal temp : std_logic_vector(17 downto 0);
begin
ci <= c_in when s1 = '1' else
'0';
process (a, b, s0, ci)
begin
if(s0 = '1') then
temp <= ("0" & a & ci) + ("0" & b & "1");
else
temp <= ("0" & a & ci) - ("0" & b & "1");
end if;
end process;
sum <= temp(16 downto 1);
c_out <= temp(17) when s0 = '1' else
not temp(17);
ofl_out <= temp(17) xor sum(15) xor a(15) xor b(15);
result <= sum;
 
end rtl;

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