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URL https://opencores.org/ocsvn/sd_card_controller/sd_card_controller/trunk

Subversion Repositories sd_card_controller

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Rev 7 → Rev 8

/sd_card_controller/trunk/bench/verilog/monostable_domain_cross_tb.sv
6,7 → 6,7
//// ////
//// This file is part of the WISHBONE SD Card ////
//// Controller IP Core project ////
//// http://www.opencores.org/cores/xxx/ ////
//// http://opencores.org/project,sd_card_controller ////
//// ////
//// Description ////
//// testbench for monostable_domain_cross module ////
/sd_card_controller/trunk/bench/verilog/sd_cmd_master_tb.sv
6,7 → 6,7
//// ////
//// This file is part of the WISHBONE SD Card ////
//// Controller IP Core project ////
//// http://www.opencores.org/cores/xxx/ ////
//// http://opencores.org/project,sd_card_controller ////
//// ////
//// Description ////
//// testbench for sd_cmd_master module ////
/sd_card_controller/trunk/bench/verilog/sd_fifo_filler_tb.sv
6,7 → 6,7
//// ////
//// This file is part of the WISHBONE SD Card ////
//// Controller IP Core project ////
//// http://www.opencores.org/cores/xxx/ ////
//// http://opencores.org/project,sd_card_controller ////
//// ////
//// Description ////
//// testbench for sd_fifo_filler module ////
/sd_card_controller/trunk/bench/verilog/sd_data_xfer_trig_tb.sv
6,7 → 6,7
//// ////
//// This file is part of the WISHBONE SD Card ////
//// Controller IP Core project ////
//// http://www.opencores.org/cores/xxx/ ////
//// http://opencores.org/project,sd_card_controller ////
//// ////
//// Description ////
//// testbench for sd_data_xfer_trig module ////
/sd_card_controller/trunk/bench/verilog/sd_data_master_tb.sv
6,7 → 6,7
//// ////
//// This file is part of the WISHBONE SD Card ////
//// Controller IP Core project ////
//// http://www.opencores.org/cores/xxx/ ////
//// http://opencores.org/project,sd_card_controller ////
//// ////
//// Description ////
//// testbench for sd_data_master module ////
/sd_card_controller/trunk/bench/verilog/bistable_domain_cross_tb.sv
6,7 → 6,7
//// ////
//// This file is part of the WISHBONE SD Card ////
//// Controller IP Core project ////
//// http://www.opencores.org/cores/xxx/ ////
//// http://opencores.org/project,sd_card_controller ////
//// ////
//// Description ////
//// testbench for bistable_domain_cross module ////
/sd_card_controller/trunk/bench/verilog/sd_cmd_serial_host_tb.sv
6,7 → 6,7
//// ////
//// This file is part of the WISHBONE SD Card ////
//// Controller IP Core project ////
//// http://www.opencores.org/cores/xxx/ ////
//// http://opencores.org/project,sd_card_controller ////
//// ////
//// Description ////
//// testbench for sd_cmd_serial_host module ////
/sd_card_controller/trunk/bench/verilog/sd_data_serial_host_tb.sv
6,7 → 6,7
//// ////
//// This file is part of the WISHBONE SD Card ////
//// Controller IP Core project ////
//// http://www.opencores.org/cores/xxx/ ////
//// http://opencores.org/project,sd_card_controller ////
//// ////
//// Description ////
//// testbench for sd_data_serial_host module ////
/sd_card_controller/trunk/bench/verilog/edge_detect_tb.sv
6,7 → 6,7
//// ////
//// This file is part of the WISHBONE SD Card ////
//// Controller IP Core project ////
//// http://www.opencores.org/cores/xxx/ ////
//// http://opencores.org/project,sd_card_controller ////
//// ////
//// Description ////
//// testbench for edge_detect module ////
/sd_card_controller/trunk/bench/verilog/sd_controller_wb_tb.sv
6,7 → 6,7
//// ////
//// This file is part of the WISHBONE SD Card ////
//// Controller IP Core project ////
//// http://www.opencores.org/cores/xxx/ ////
//// http://opencores.org/project,sd_card_controller ////
//// ////
//// Description ////
//// testbench for sd_controller_wb module ////
/sd_card_controller/trunk/rtl/verilog/sdc_controller.v
6,15 → 6,15
//// ////
//// This file is part of the WISHBONE SD Card ////
//// Controller IP Core project ////
//// http://www.opencores.org/cores/xxx/ ////
//// http://opencores.org/project,sd_card_controller ////
//// ////
//// Description ////
//// Top level entity. ////
//// This core is based on SD Card IP core project from ////
//// This core is based on the "sd card controller" project from ////
//// http://opencores.org/project,sdcard_mass_storage_controller ////
//// and is a major rewrite of original work. Effort was put to ////
//// make the core more generic and be able to be used with ////
//// OS's like Linux. ////
//// but has been largely rewritten. A lot of effort has been ////
//// made to make the core more generic and easily usable ////
//// with OSs like Linux. ////
//// - data transfer commands are not fixed ////
//// - data transfer block size is configurable ////
//// - multiple block transfer support ////
/sd_card_controller/trunk/rtl/verilog/bistable_domain_cross.v
6,7 → 6,7
//// ////
//// This file is part of the WISHBONE SD Card ////
//// Controller IP Core project ////
//// http://www.opencores.org/cores/xxx/ ////
//// http://opencores.org/project,sd_card_controller ////
//// ////
//// Description ////
//// Clock synchronisation beetween two clock domains. ////
/sd_card_controller/trunk/rtl/verilog/sd_cmd_serial_host.v
6,7 → 6,7
//// ////
//// This file is part of the WISHBONE SD Card ////
//// Controller IP Core project ////
//// http://www.opencores.org/cores/xxx/ ////
//// http://opencores.org/project,sd_card_controller ////
//// ////
//// Description ////
//// Module resposible for sending and receiving commands ////
/sd_card_controller/trunk/rtl/verilog/sd_defines.h
6,7 → 6,7
//// ////
//// This file is part of the WISHBONE SD Card ////
//// Controller IP Core project ////
//// http://www.opencores.org/cores/xxx/ ////
//// http://opencores.org/project,sd_card_controller ////
//// ////
//// Description ////
//// Header file with common definitions ////
/sd_card_controller/trunk/rtl/verilog/sd_clock_divider.v
6,7 → 6,7
//// ////
//// This file is part of the WISHBONE SD Card ////
//// Controller IP Core project ////
//// http://www.opencores.org/cores/xxx/ ////
//// http://opencores.org/project,sd_card_controller ////
//// ////
//// Description ////
//// Control of sd card clock rate ////
/sd_card_controller/trunk/rtl/verilog/sd_data_serial_host.v
6,7 → 6,7
//// ////
//// This file is part of the WISHBONE SD Card ////
//// Controller IP Core project ////
//// http://www.opencores.org/cores/xxx/ ////
//// http://opencores.org/project,sd_card_controller ////
//// ////
//// Description ////
//// Module resposible for sending and receiving data through ////
/sd_card_controller/trunk/rtl/verilog/edge_detect.v
6,7 → 6,7
//// ////
//// This file is part of the WISHBONE SD Card ////
//// Controller IP Core project ////
//// http://www.opencores.org/cores/xxx/ ////
//// http://opencores.org/project,sd_card_controller ////
//// ////
//// Description ////
//// Signal edge detection. If input signal transitions between ////
/sd_card_controller/trunk/rtl/verilog/sd_controller_wb.v
6,7 → 6,7
//// ////
//// This file is part of the WISHBONE SD Card ////
//// Controller IP Core project ////
//// http://www.opencores.org/cores/xxx/ ////
//// http://opencores.org/project,sd_card_controller ////
//// ////
//// Description ////
//// Wishbone interface responsible for comunication with core ////
/sd_card_controller/trunk/rtl/verilog/monostable_domain_cross.v
6,7 → 6,7
//// ////
//// This file is part of the WISHBONE SD Card ////
//// Controller IP Core project ////
//// http://www.opencores.org/cores/xxx/ ////
//// http://opencores.org/project,sd_card_controller ////
//// ////
//// Description ////
//// Clock synchronisation beetween two clock domains. ////
/sd_card_controller/trunk/rtl/verilog/sd_cmd_master.v
6,7 → 6,7
//// ////
//// This file is part of the WISHBONE SD Card ////
//// Controller IP Core project ////
//// http://www.opencores.org/cores/xxx/ ////
//// http://opencores.org/project,sd_card_controller ////
//// ////
//// Description ////
//// State machine resposible for controlling command transfers ////
/sd_card_controller/trunk/rtl/verilog/sd_fifo_filler.v
6,7 → 6,7
//// ////
//// This file is part of the WISHBONE SD Card ////
//// Controller IP Core project ////
//// http://www.opencores.org/cores/xxx/ ////
//// http://opencores.org/project,sd_card_controller ////
//// ////
//// Description ////
//// Fifo interface between sd card and wishbone clock domains ////
/sd_card_controller/trunk/rtl/verilog/sd_data_xfer_trig.v
6,7 → 6,7
//// ////
//// This file is part of the WISHBONE SD Card ////
//// Controller IP Core project ////
//// http://www.opencores.org/cores/xxx/ ////
//// http://opencores.org/project,sd_card_controller ////
//// ////
//// Description ////
//// Module resposible for triggering data transfer based on ////
/sd_card_controller/trunk/rtl/verilog/sd_data_master.v
6,7 → 6,7
//// ////
//// This file is part of the WISHBONE SD Card ////
//// Controller IP Core project ////
//// http://www.opencores.org/cores/xxx/ ////
//// http://opencores.org/project,sd_card_controller ////
//// ////
//// Description ////
//// State machine resposible for controlling data transfers ////
/sd_card_controller/trunk/doc/src/specification.tex
6,7 → 6,7
%%%% %%%%
%%%% This file is part of the WISHBONE SD Card %%%%
%%%% Controller IP Core project %%%%
%%%% http://www.opencores.org/cores/xxx/ %%%%
%%%% http://opencores.org/project,sd_card_controller %%%%
%%%% %%%%
%%%% Description %%%%
%%%% documentation main document %%%%
/sd_card_controller/trunk/doc/src/introduction.tex
1,4 → 1,45
 
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%% %%%%
%%%% WISHBONE SD Card Controller IP Core %%%%
%%%% %%%%
%%%% introduction.tex %%%%
%%%% %%%%
%%%% This file is part of the WISHBONE SD Card %%%%
%%%% Controller IP Core project %%%%
%%%% http://opencores.org/project,sd_card_controller %%%%
%%%% %%%%
%%%% Description %%%%
%%%% documentation 'Introduction' chapter %%%%
%%%% %%%%
%%%% Author(s): %%%%
%%%% - Marek Czerski, ma.czerski@gmail.com %%%%
%%%% %%%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%% %%%%
%%%% Copyright (C) 2013 Authors %%%%
%%%% %%%%
%%%% This source file may be used and distributed without %%%%
%%%% restriction provided that this copyright statement is not %%%%
%%%% removed from the file and that any derivative work contains %%%%
%%%% the original copyright notice and the associated disclaimer. %%%%
%%%% %%%%
%%%% This source file is free software; you can redistribute it %%%%
%%%% and/or modify it under the terms of the GNU Lesser General %%%%
%%%% Public License as published by the Free Software Foundation; %%%%
%%%% either version 2.1 of the License, or (at your option) any %%%%
%%%% later version. %%%%
%%%% %%%%
%%%% This source is distributed in the hope that it will be %%%%
%%%% useful, but WITHOUT ANY WARRANTY; without even the implied %%%%
%%%% warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR %%%%
%%%% PURPOSE. See the GNU Lesser General Public License for more %%%%
%%%% details. %%%%
%%%% %%%%
%%%% You should have received a copy of the GNU Lesser General %%%%
%%%% Public License along with this source; if not, download it %%%%
%%%% from http://www.opencores.org/lgpl.shtml %%%%
%%%% %%%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\section{Introduction}
\label{sec:introduction}
 
/sd_card_controller/trunk/doc/src/usage.tex
6,7 → 6,7
%%%% %%%%
%%%% This file is part of the WISHBONE SD Card %%%%
%%%% Controller IP Core project %%%%
%%%% http://www.opencores.org/cores/xxx/ %%%%
%%%% http://opencores.org/project,sd_card_controller %%%%
%%%% %%%%
%%%% Description %%%%
%%%% documentation 'Usage' chapter %%%%
/sd_card_controller/trunk/doc/src/hdl_if.tex
6,7 → 6,7
%%%% %%%%
%%%% This file is part of the WISHBONE SD Card %%%%
%%%% Controller IP Core project %%%%
%%%% http://www.opencores.org/cores/xxx/ %%%%
%%%% http://opencores.org/project,sd_card_controller %%%%
%%%% %%%%
%%%% Description %%%%
%%%% documentation 'HDL interface' chapter %%%%
/sd_card_controller/trunk/doc/src/sw_if.tex
6,7 → 6,7
%%%% %%%%
%%%% This file is part of the WISHBONE SD Card %%%%
%%%% Controller IP Core project %%%%
%%%% http://www.opencores.org/cores/xxx/ %%%%
%%%% http://opencores.org/project,sd_card_controller %%%%
%%%% %%%%
%%%% Description %%%%
%%%% documentation 'Software interface' chapter %%%%
/sd_card_controller/trunk/doc/src/Makefile
6,7 → 6,7
#### ####
#### This file is part of the WISHBONE SD Card ####
#### Controller IP Core project ####
#### http://www.opencores.org/cores/xxx/ ####
#### http://opencores.org/project,sd_card_controller ####
#### ####
#### Description ####
#### Documentation makefile ####
/sd_card_controller/trunk/sim/rtl_sim/bin/Makefile
6,7 → 6,7
#### ####
#### This file is part of the WISHBONE SD Card ####
#### Controller IP Core project ####
#### http://www.opencores.org/cores/xxx/ ####
#### http://opencores.org/project,sd_card_controller ####
#### ####
#### Description ####
#### Simulation makefile ####
/sd_card_controller/trunk/sw/example/src/sdc_example.c
5,7 → 5,7
*
* This file is part of the WISHBONE SD Card
* Controller IP Core project
* http://www.opencores.org/cores/xxx/
* http://opencores.org/project,sd_card_controller
*
* Description
* Example application using WISHBONE SD Card Controller
/sd_card_controller/trunk/sw/example/src/ocsdc.c
5,7 → 5,7
*
* This file is part of the WISHBONE SD Card
* Controller IP Core project
* http://www.opencores.org/cores/xxx/
* http://opencores.org/project,sd_card_controller
*
* Description
* Driver for the WISHBONE SD Card Controller IP Core.
/sd_card_controller/trunk/syn/quartus/src/sdc_controller_top.v
6,7 → 6,7
//// ////
//// This file is part of the WISHBONE SD Card ////
//// Controller IP Core project ////
//// http://www.opencores.org/cores/xxx/ ////
//// http://opencores.org/project,sd_card_controller ////
//// ////
//// Description ////
//// Top level entity of synthesis test project. ////
/sd_card_controller/trunk/syn/quartus/bin/Makefile
6,7 → 6,7
#### ####
#### This file is part of the WISHBONE SD Card ####
#### Controller IP Core project ####
#### http://www.opencores.org/cores/xxx/ ####
#### http://opencores.org/project,sd_card_controller ####
#### ####
#### Description ####
#### Altera synthesis makefile ####
/sd_card_controller/trunk/README.md
7,6 → 7,18
bus. The communication between the MMC/SD card controller and MMC/SD card is performed
according to the MMC/SD protocol.
 
Introduction
------------
This core is based on the "sd card controller" project from
http://opencores.org/project,sdcard_mass_storage_controller
but has been largely rewritten. A lot of effort has been made
to make the core more generic and easily usable
with OSs like Linux.
- data transfer commands are not fixed
- data transfer block size is configurable
- multiple block transfer support
- R2 responses (136 bit) support
 
Features
--------
 

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