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URL https://opencores.org/ocsvn/wbscope/wbscope/trunk

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    from Rev 7 to Rev 8
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Rev 7 → Rev 8

/wbscope/trunk/rtl/wbscopc.v
117,10 → 117,10
// data changes, but increment it on all other clocks. Should the
// address difference get to our maximum value, we let it saturate
// rather than overflow.
reg [(BUSW-2):0] ck_addr;
reg [(BUSW-2):0] ck_addr, lst_dat;
initial ck_addr = 0;
always @(posedge i_clk)
if ((lcl_reset)||((i_ce)&&(i_data != lst_data)))
if ((lcl_reset)||((i_ce)&&(i_data != lst_dat)))
ck_addr <= 0;
else if (&ck_addr)
; // Saturated (non-overflowing) address diff
133,8 → 133,7
// clock ago. This allows us to suppress writes to the scope which
// would otherwise be two address writes in a row.
reg imm_adr, lst_adr; // Is this an address (1'b1) or data value?
reg [(BUSW-2):0] lst_dat, // The data associated with t-1
lst_val, // Data for the scope, delayed by one
reg [(BUSW-2):0] lst_val, // Data for the scope, delayed by one
imm_val; // Data to write to the scope
initial lst_dat = 0;
initial lst_adr = 1'b1;

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