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URL https://opencores.org/ocsvn/wisbone_2_ahb/wisbone_2_ahb/trunk

Subversion Repositories wisbone_2_ahb

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Rev 7 → Rev 8

/branches/toomuch/svtb/avm_svtb/wb_ahb_responder.svh
3,7 → 3,8
 
 
//File name : wb_ahb_responder.svh
//Date : Aug, 2007
//Designer : Ravi S Gupta
//Date : 4 Sept, 2007
//Description : Response from AHB to the Inputs from Wishbone
//Revision : 1.0
 
16,6 → 17,13
class wb_ahb_responder extends avm_threaded_component;
 
int cnt;
// local memory in AHB slave model
logic [DWIDTH-1 : 0] ahb_mem [AWIDTH-1 : 0];
 
logic [AWIDTH-1:0] haddr_temp;
logic [DWIDTH-1 :0] hrdata_temp;
logic hwrite_temp;
 
virtual wb_ahb_if pin_if;
 
function new(string name ,avm_named_component parent);
23,61 → 31,48
pin_if =null;
endfunction
 
task run;
// local memory in AHB slave model
logic [DWIDTH-1 : 0] ahb_mem [AWIDTH-1 : 0];
logic [AWIDTH-1:0] haddr_temp;
logic [DWIDTH-1 :0] hrdata_temp;
logic hwrite_temp;
 
forever
begin
@(pin_if.slave_ba.haddr or pin_if.slave_ba.hwrite);
// task to sample address
task samp_addr;
forever
begin
@(posedge pin_if.master_wb.clk_i);
if(pin_if.master_wb.rst_i)
begin
pin_if.slave_ba.hready='b0;
pin_if.slave_ba.hwdata='bx;
pin_if.slave_ba.hresp='b00;
 
end
else
@(posedge pin_if.master_wb.clk_i)
if(pin_if.slave_ba.hready)
else if(!pin_if.slave_ba.hwrite)
begin
haddr_temp = #2 pin_if.slave_ba.haddr;
hwrite_temp=#2 pin_if.slave_ba.hwrite;
$display("@ %0d,temp addr=%0d",$time,haddr_temp);
if(hwrite_temp)
begin
ahb_mem[haddr_temp] = #2 pin_if.slave_ba.hwdata;// data stored in ahb slave
$display("@ %0d,temp data=%0d",$time,pin_if.slave_ba.hwdata);
end
else if (!pin_if.slave_ba.hwrite) //Read Operation
begin
pin_if.slave_ba.hrdata = #2 ahb_mem[pin_if.slave_ba.haddr];
end
pin_if.slave_ba.hrdata= #2 pin_if.slave_ba.haddr+1;
end
end
endtask
 
task response;
forever
begin
@(posedge pin_if.master_wb.clk_i);
end
endtask
 
//*****************************************
//Write operations with no wait states
//*****************************************
task wait_state_by_slave;
pin_if.slave_ba.hready='b1;
$display("\n@%0d Block Write operations \n",$time);
do
begin
@(posedge pin_if.master_wb.clk_i);
cnt++;
end
while (cnt <= 6);//Write operations with no wait states for 7 clk cycles
while (cnt <= 9);//Write operations with no wait states for 10 clk cycles
//************************************************
//Write operations with wait states from AHB Slave
//************************************************
#2 pin_if.slave_ba.hready='b0;
$display("\n@%0d Write operations with wait states from AHB Slave \n",$time);
cnt=0;
do
begin
84,12 → 79,11
@(posedge pin_if.master_wb.clk_i);
++cnt;
end
while (cnt <= 1);// 2 clock cycle asserted AHB Master is in Wait State
while (cnt <= 4);// 5 clock cycle asserted AHB Master is in Wait State
//*****************************************
//Write operations with no wait states
//*****************************************
#2 pin_if.slave_ba.hready='b1;
$display("\n@%0d Block Write operations \n",$time);
cnt=0;
do
begin
96,12 → 90,11
@(posedge pin_if.master_wb.clk_i);
cnt++;
end
while (cnt <= 3);//Write operations with no wait states for 4 clk cycles
while (cnt <= 4);//Write operations with no wait states for 5 clk cycles
//***********************************************
//Write operations with wait states from WB Master
//***********************************************
#2 pin_if.slave_ba.hready='b1;
$display("\n@%0d Write operations with wait states from WB Master \n",$time);
cnt=0;
do
begin
108,12 → 101,11
@(posedge pin_if.master_wb.clk_i);
++cnt;
end
while (cnt <= 1);// 2 clock cycle deasserted WB Master is in Wait State
while (cnt <= 4);// 5 clock cycle deasserted WB Master is in Wait State
//*****************************************
//Write operations with no wait states
//*****************************************
#2 pin_if.slave_ba.hready='b1;
$display("\n@%0d Block Write operations \n",$time);
cnt=0;
do
begin
120,13 → 112,12
@(posedge pin_if.master_wb.clk_i);
cnt++;
end
while (cnt <= 3);//Write operations with no wait states for 4 clk cycles
while (cnt <= 4);//Write operations with no wait states for 5 clk cycles
 
//*************************************
//Read operations without wait states
//*************************************
#2 pin_if.slave_ba.hready='b1;
$display("\n@%0d Block Read operations \n",$time);
cnt=0;
do
begin
133,13 → 124,12
@(posedge pin_if.master_wb.clk_i);
cnt++;
end
while (cnt <= 5);// Read operations with no wait states for 6 clk cycles
while (cnt <= 9);// Read operations with no wait states for 10 clk cycles
 
//**********************************************
//Read operations with wait states from AHB Slave
//**********************************************
#2 pin_if.slave_ba.hready='b0; // 25 clock cycle asserted AHB Master is in Wait State
$display("\n@%0d Read operations with wait states from AHB Slave\n",$time);
#2 pin_if.slave_ba.hready='b0;
cnt=0;
do
begin
146,13 → 136,12
@(posedge pin_if.master_wb.clk_i);
++cnt;
end
while (cnt <= 1);// 2 clock cycle asserted AHB Master is in Wait State
while (cnt <= 9);// 10 clock cycle asserted AHB Master is in Wait State
 
//*************************************
//Read operations without wait states
//*************************************
#2 pin_if.slave_ba.hready='b1;
$display("\n@%0d Block Read operations \n",$time);
cnt=0;
do
begin
159,12 → 148,11
@(posedge pin_if.master_wb.clk_i);
cnt++;
end
while (cnt <= 3);// Read operations with no wait states for 4 clk cycles
while (cnt <= 9);// Read operations with no wait states for 10 clk cycles
//**********************************************
//Read operations with wait states from WB Master
//**********************************************
#2 pin_if.slave_ba.hready='b1; // 5 clock cycle deasserted WB Master in in Wait state
$display("\n@%0d Read operations with wait states from WB Master\n",$time);
#2 pin_if.slave_ba.hready='b1;
cnt=0;
do
begin
171,9 → 159,15
@(posedge pin_if.master_wb.clk_i);
++cnt;
end
while (cnt <= 4);// 5 clock cycle asserted WB Master in in Wait state
while (cnt <= 9);// 10 clock cycle asserted WB Master in in Wait state
 
endtask
// run all task
task run;
fork
samp_addr;
response;
join
endtask
 
 
endclass
/branches/toomuch/svtb/avm_svtb/wb_ahb_master.sv
3,7 → 3,8
 
 
//File name : wb_ahb_master.sv
//Date : Aug, 2007
//Designer : Ravi S Gupta
//Date : 4 Sept, 2007
//Description : Master for initializing values during Reset State of Device
//Revision : 1.0
 
34,8 → 35,6
m_wb.sel_i='bx;
m_wb.addr_i='bx;
m_wb.data_i='bx;
$display("Values of various signals at Reset State of the Device");
$display("%0b, %0b, %0b, %0d, %0d" ,m_wb.cyc_i , m_wb.stb_i , m_wb.sel_i,m_wb.addr_i,m_wb.data_i );
end
 
//******************************************
50,15 → 49,10
m_wb.we_i='bx;
m_wb.addr_i='bx;
m_wb.data_i='bx;
$display("Initial signal setups values");
$display("%0b, %0b, %0b, %0b, %0d, %0d" ,m_wb.cyc_i , m_wb.stb_i , m_wb.sel_i,m_wb.we_i,m_wb.addr_i,m_wb.data_i);
#20 m_wb.cyc_i='b1;
# 20 m_wb.cyc_i='b1;
m_wb.stb_i='b1;
m_wb.sel_i='b0;
m_wb.we_i='b1;//Write operation
$display("Initial signal setups values to start working");
$display("at %0d ,%0b, %0b, %0b, %0b",$time,m_wb.cyc_i , m_wb.stb_i , m_wb.sel_i,m_wb.we_i );
 
end
endtask
 
/branches/toomuch/svtb/avm_svtb/wb_ahb_scoreboard.svh
3,7 → 3,8
 
 
//File name : wb_ahb_scoreboard.svh
//Date : Aug, 2007
//Designer : Ravi S Gupta
//Date : 4 Sept, 2007
//Description : Stimulus Generation for WISHBONE_AHB Bridge
//Revision : 1.0
 
18,10 → 19,12
analysis_fifo#(monitor_pkt) ap_fifo; // analysis port fifo
analysis_if#(monitor_pkt) ap_if; // analysis port interface
// local variables
logic [AWIDTH-1:0]adr1;
logic [AWIDTH-1:0]adr2;
logic [DWIDTH-1:0]dat1;
logic [DWIDTH-1:0]dat2;
 
logic [AWIDTH-1:0]adr1; //WB ADDR
logic [DWIDTH-1:0]dat1; //WB DATA
logic [AWIDTH-1:0]adr2; //AHB ADDR
logic [DWIDTH-1:0]dat2; //WB DATA
 
// monitor packet
monitor_pkt m_pkt;
 
34,63 → 37,69
pin_if =null;
endfunction
 
// connecting analysis fifo to the analysis interface
// connecting analysis fifo to the analysis interface
function void export_connections();
ap_if = ap_fifo.analysis_export;
endfunction
 
task run;
forever
forever
begin
ap_fifo.get(m_pkt);
if(m_pkt.stb) //No wait state
if(m_pkt.stb && m_pkt.ack) //No wait state
if(m_pkt.wr) //write mode
if(m_pkt.flag1) // first clock no comaprison only sampling the values
if(m_pkt.flag1) // first clock comparison only between addresses
begin
adr1=m_pkt.adr1;
else
dat1=m_pkt.dat1;
adr2=m_pkt.adr2;
if(m_pkt.flag2) // first clock after after wait state
begin
if((( adr1==m_pkt.adr1) && (dat1==m_pkt.dat1) && (adr2==m_pkt.adr2) && (dat2==m_pkt.dat2)) || (( adr1 === m_pkt.adr2 ) && (m_pkt.dat1 === m_pkt.dat2)));
if((( adr1==m_pkt.adr1) && (dat1==m_pkt.dat1) && (adr2==m_pkt.adr2) && (dat2==m_pkt.dat2))|| (( m_pkt.adr1 === m_pkt.adr2 ) && (m_pkt.dat1 === dat2)));
//avm_report_message("Scoreboard: Write Passed","after wait state");
else
avm_report_warning("Scoreboard: Error in write after wait state",display_pkt(m_pkt));
adr1=m_pkt.adr1; // Holding the previous address
adr1=m_pkt.adr1; // Holding the previous WB address
dat1=m_pkt.dat1; // Holding the previous WB data
adr2=m_pkt.adr2; // Holding the previous AHB Addr
end
else
begin
if(( adr1 === m_pkt.adr2 ) && (m_pkt.dat1 === m_pkt.dat2));
begin
if(( m_pkt.adr1 === m_pkt.adr2 ) && (m_pkt.dat1 === dat2));
//avm_report_message("Scoreboard: Write Passed","without wait state");
else
begin
else
avm_report_warning("Scoreboard: Error in write without wait state",display_pkt(m_pkt));
end
adr1=m_pkt.adr1;
end
else// read mode
if(m_pkt.flag1) // first clock no comaprison only sampling the values
adr1=m_pkt.adr1;
else
end
else //READ Mode
if(m_pkt.flag1) // first clock comaprison between addresses
begin
adr1=m_pkt.adr1;// Holding the previous WB address
adr2=m_pkt.adr2;// Holding the previous AHB Addr
if(m_pkt.flag2) // first clock after after wait state
begin
if((( adr1==m_pkt.adr1) && (dat1==m_pkt.dat1) && (adr2==m_pkt.adr2) && (dat2==m_pkt.dat2)) || (( adr1 === m_pkt.adr2 ) && (m_pkt.dat1 === m_pkt.dat2)));
if((( adr1==m_pkt.adr1) && (dat1==m_pkt.dat1) && (adr2==m_pkt.adr2) && (dat2==m_pkt.dat2))|| (( adr1 === m_pkt.adr2 ) && (m_pkt.dat1 === m_pkt.dat2)));
//avm_report_message("Scoreboard: Read Passed","after wait state");
else
avm_report_warning("Scoreboard: Error in read after wait state",display_pkt(m_pkt));
adr1=m_pkt.adr1;
adr1=m_pkt.adr1;
adr2=m_pkt.adr2;
end
 
else
else
begin
if(( adr1 === m_pkt.adr2 ) && (m_pkt.dat1 === m_pkt.dat2)); // comparing unknown values too
//avm_report_message("Scoreboard: Read Passed","without wait state");
else
begin
avm_report_warning("Scoreboard: Error in read without wait state",display_pkt(m_pkt));
end
adr1=m_pkt.adr1;
adr1=m_pkt.adr1;
adr2=m_pkt.adr2;
end
else // wait state by slave or master
end
else // wait state by slave or master
begin
if(m_pkt.flag2) // latch the value
begin
adr1=m_pkt.adr1;
99,18 → 108,19
dat2=m_pkt.dat2;
end
else
begin
if(( adr1==m_pkt.adr1) && (dat1==m_pkt.dat1) && (adr2==m_pkt.adr2) && (dat2==m_pkt.dat2));
//$display("Passed wait");
//avm_report_message("Scoreboard: Passed","with wait state");
else
begin
avm_report_warning("Scoreboard: Error in with wait state",display_pkt(m_pkt));
end
end
end
end
endtask
 
// function to display values at any instant :
 
// function to display values at any instant
function string display_pkt(input monitor_pkt m);
string s;
$sformat(s,"current_adr1=%0d,adr1=%0d,adr2=%0d,dat1=%0d,dat2=%0d,wr=%0b,stb=%0b,f1=%b,f2=%b",adr1,m.adr1,m.adr2,m.dat1,m.dat2,m.wr,m.stb,m.flag1,m.flag2);
/branches/toomuch/svtb/avm_svtb/wb_ahb_stim_gen.svh
3,7 → 3,8
 
 
//File name : wb_ahb_stim_gen.svh
//Date : Aug, 2007
//Designaer : Ravi S Gupta
//Date : 4 Sept, 2007
//Description : Stimulus Generation for WISHBONE_AHB Bridge
//Revision : 1.0
 
30,7 → 31,7
//*****************************************
//Write operations with no wait states
//*****************************************
for(int i=0; i<8 ;i++)
for(int i=0; i<11 ;i++)
begin
p.wr='b1;
p.adr=i+1;
42,7 → 43,7
//************************************************
//Write operations with wait states from AHB Slave
//************************************************
for(int i=8;i<10;i++)
for(int i=10;i<16;i++)
begin
p.wr='b1;//Wait state from AHB SLAVE
p.stb='b1;
52,7 → 53,7
//*****************************************
//Write operations with no wait states
//*****************************************
for(int i=10; i<14 ;i++)
for(int i=15; i<21 ;i++)
begin
p.wr='b1;
p.adr=i+1;
64,7 → 65,7
//***********************************************
//Write operations with wait states from WB Master
//***********************************************
for(int i=14;i<16;i++)
for(int i=20;i<26;i++)
begin
p.stb='b0;
p.wr='b1;//Wait state from AHB SLAVE
74,7 → 75,7
//*****************************************
//Write operations with no wait states
//*****************************************
for(int i=15; i<19 ;i++)
for(int i=25; i<31 ;i++)
begin
p.wr='b1;
p.adr=i+1;
86,8 → 87,9
//*************************************
//Read operations without wait states
//*************************************
for(int i=19; i<25 ;i++)
for(int i=30; i<41 ;i++)
begin
p.wr='b0;
p.adr=i+1;
p.stb='b1;
97,49 → 99,51
//**********************************************
//Read operations with wait states from AHB Slave
//**********************************************
for(int i=25; i<27 ;i++)
for(int i=40; i<51 ;i++)
begin
p.wr='b0;
write_to_pipe(p);
p.stb='b1;
write_to_pipe(p);
end
//*************************************
//Read operations without wait states
//*************************************
for(int i=27; i<31 ;i++)
for(int i=50; i<61 ;i++)
begin
p.wr='b0;
p.adr=$random;
$display("%0d, %0d", p.wr, p.adr );
write_to_pipe(p);
p.stb='b1;
p.adr=i+1;
write_to_pipe(p);
end
//**********************************************
//Read operations with wait states from WB Master
//**********************************************
for(int i=31; i<33 ;i++)
for(int i=60; i<71 ;i++)
begin
p.wr='b0;
write_to_pipe(p);
p.stb='b0;
write_to_pipe(p);
end
//*************************************
//Read operations without wait states
//*************************************
for(int i=33; i<38 ;i++)
for(int i=70; i<81 ;i++)
begin
p.wr='b0;
p.adr=$random;
$display("%0d, %0d",p.wr, p.adr );
write_to_pipe(p);
p.stb='b1;
p.adr=i+1;
write_to_pipe(p);
end
//*****************************************
//Write operations with no wait states
//*****************************************
for(int i=38; i<41 ;i++)
for(int i=80; i<91 ;i++)
begin
p.wr='b1;
p.adr=$random;
p.dat=$random;
$display("%0d, %0d", p.adr , p.dat );
write_to_pipe(p);
p.stb='b1;
p.adr=i+1;
p.dat=i;
write_to_pipe(p);
end
 
endtask
/branches/toomuch/svtb/avm_svtb/global.sv
3,7 → 3,8
 
 
//File name : global.sv
//Date : Aug, 2007
//Designer : Ravi S Gupta
//Date : 4 Sept, 2007
//Description : Gloabl Declaration for WISHBONE_AHB Bridge used within Driver, Stimulus Generator and Monitor
//Revision : 1.0
 
/branches/toomuch/svtb/avm_svtb/wb_ahb_monitor.svh
3,7 → 3,8
 
 
//File name : wb_ahb_monitor.svh
//Date : Aug, 2007
//Designer : Ravi S Gupta
//Date : 4 Sept, 2007
//Description : Monitor for WISHBONE_AHB Bridge
//Revision : 1.0
 
32,7 → 33,6
forever
begin
@(pin_if.monitor.we_i);
$display("Event on Read/Write");
flag1='b1;
end
endtask
49,7 → 49,6
forever
begin
@(posedge pin_if.monitor.clk_i);
$display("At %0d,Values at ahb :%0d, %0d",$time,pin_if.monitor.haddr,pin_if.monitor.hwdata);
if(pin_if.monitor.stb_i)//No wait state
begin
if(pin_if.monitor.we_i) //write mode
56,9 → 55,12
begin
if(flag1) // first clock
begin
m_pkt.adr1=pin_if.monitor.addr_i;
m_pkt.adr1=pin_if.monitor.addr_i;// Get WB addr and Data along with AHB addr
m_pkt.dat1=pin_if.monitor.data_i;
m_pkt.adr2=pin_if.monitor.haddr;
m_pkt.wr='b1;
m_pkt.stb=pin_if.monitor.stb_i;
m_pkt.ack=pin_if.monitor.ack_o;
m_pkt.flag1='b1;
// write packet to scoreboard
ap_sb.write(m_pkt);
72,6 → 74,7
m_pkt.dat2=pin_if.monitor.hwdata;
m_pkt.wr='b1;
m_pkt.stb=pin_if.monitor.stb_i;
m_pkt.ack=pin_if.monitor.ack_o;
m_pkt.flag1='b0;
m_pkt.flag2=flag2;
ap_sb.write(m_pkt);
81,9 → 84,11
begin
if(flag1) // first clock
begin
m_pkt.adr1=pin_if.monitor.addr_i;
m_pkt.adr1=pin_if.monitor.addr_i;//Get addr from both WB and AHB
m_pkt.adr2=pin_if.monitor.haddr;
m_pkt.wr='b0;
m_pkt.stb=pin_if.monitor.stb_i;
m_pkt.ack=pin_if.monitor.ack_o;
m_pkt.flag1='b1;
//write packet to scoreboard
ap_sb.write(m_pkt);
92,11 → 97,12
else
begin
m_pkt.adr1=pin_if.monitor.addr_i;
m_pkt.dat1=pin_if.monitor.data_i;
m_pkt.dat1=pin_if.monitor.data_o;
m_pkt.adr2=pin_if.monitor.haddr;
m_pkt.dat2=pin_if.monitor.hrdata;
m_pkt.wr='b0;
m_pkt.stb=pin_if.monitor.stb_i;
m_pkt.ack=pin_if.monitor.ack_o;
m_pkt.flag1='b0;
m_pkt.flag2=flag2;
// write packet to scoreboard
116,6 → 122,7
m_pkt.dat2=pin_if.monitor.hwdata;
m_pkt.wr='b1;
m_pkt.stb=pin_if.monitor.stb_i;
m_pkt.ack=pin_if.monitor.ack_o;
m_pkt.flag2='b1;
ap_sb.write(m_pkt);
flag2='b0;
128,6 → 135,7
m_pkt.dat2=pin_if.monitor.hwdata;
m_pkt.wr='b1;
m_pkt.stb=pin_if.monitor.stb_i;
m_pkt.ack=pin_if.monitor.ack_o;
m_pkt.flag2='b0;
ap_sb.write(m_pkt);
end
142,6 → 150,7
m_pkt.dat2=pin_if.monitor.hrdata;
m_pkt.wr='b0;
m_pkt.stb=pin_if.monitor.stb_i;
m_pkt.ack=pin_if.monitor.ack_o;
m_pkt.flag2='b1;
ap_sb.write(m_pkt);
flag2='b0;
154,6 → 163,7
m_pkt.dat2=pin_if.monitor.hrdata;
m_pkt.wr='b0;
m_pkt.stb=pin_if.monitor.stb_i;
m_pkt.ack=pin_if.monitor.ack_o;
m_pkt.flag2='b0;
ap_sb.write(m_pkt);
end
/branches/toomuch/svtb/avm_svtb/wb_ahb_env.svh
1,3 → 1,15
//******************************************************************************************************
// Copyright (c) 2007 TooMuch Semiconductor Solutions Pvt Ltd.
 
 
//File name : wb_ahb_env.svh
//Designer : Ravi S Gupta
//Date : 4 Sept, 2007
//Description : Environment for WISHBONE_AHB Bridge
//Revision : 1.0
 
//******************************************************************************************************
 
// env class
import avm_pkg::*;
import wb_ahb_pkg::*;
15,7 → 27,7
// analysis components
wb_ahb_monitor monitor;
wb_ahb_coverage coverage;
//wb_ahb_scoreboard scoreboard;
wb_ahb_scoreboard scoreboard;
 
tlm_fifo #(wb_req_pkt) fifo;
 
27,7 → 39,7
responder =new("responder",this);
monitor =new("monitor",this);
coverage =new("coverage", this);
// scoreboard =new("scoreboard", this);
scoreboard =new("scoreboard", this);
fifo =new("fifo",this);
e_ap =new("e_ap",this);
pin_if =pin;
38,7 → 50,7
function void connect();
stim_gen.initiator_port.connect(fifo.blocking_put_export);
driver.request_port.connect(fifo.nonblocking_get_export);
//monitor.ap_sb.register(scoreboard.ap_if);
monitor.ap_sb.register(scoreboard.ap_if);
monitor.ap_sb.register(coverage.ap_if);
endfunction
 
52,7 → 64,7
fork
stim_gen.stimulus();
responder.wait_state_by_slave();
#525;
#700;
join
endtask
/branches/toomuch/svtb/avm_svtb/wb_ahb_interface.sv
3,7 → 3,8
 
 
//File name : wb_ahb_interface.sv
//Date : Aug, 2007
//Designer : Ravi S Gupta
//Date : 4 Sept, 2007
//Description : Interface for WISHBONE_AHB Bridge
//Revision : 1.0
 
/branches/toomuch/svtb/avm_svtb/wb_ahb_top.sv
1,3 → 1,16
//******************************************************************************************************
// Copyright (c) 2007 TooMuch Semiconductor Solutions Pvt Ltd.
 
 
//File name : wb_ahb_top.svh
//Designer : Ravi S Gupta
//Date : 4 Sept, 2007
//Description : Top for WISHBONE_AHB Bridge
//Revision : 1.0
 
//******************************************************************************************************
 
 
// top module
`include "../../src/ahbmas_wbslv_top.v"
 
40,15 → 53,11
initial
begin
env = new(inf1);
$display ("\n@%0d:Testcase begin",$time);
#2 reset='b1;
#23 reset ='b0;
$display ("\n@%0d:Reset done",$time);
TB_M.initial_setup();
$display ("\n@%0d:Initial setup done",$time);
env.do_test();
$display ("\n@%0d do_test over",$time);
$finish;
#2 reset='b1;
#23 reset ='b0;
TB_M.initial_setup();
env.do_test();
$finish;
end
 
/branches/toomuch/svtb/avm_svtb/wb_ahb_coverage.svh
3,7 → 3,8
 
 
//File name : wb_ahb_coverage.svh
//Date : Aug, 2007
//Designaer : Ravi S Gupta
//Date : 4 Sept, 2007
//Description : Coverage Status for WISHBONE_AHB Bridge
//Revision : 1.0
 
/branches/toomuch/svtb/avm_svtb/wb_ahb_driver.svh
3,7 → 3,8
 
 
//File name : wb_ahb_driver.svh
//Date : Aug, 2007
//Designer : Ravi S Gupta
//Date : 4 Sept, 2007
//Description : Drivers for WISHBONE_AHB Bridge
//Revision : 1.0
 
34,8 → 35,18
@(posedge pin_if.master_wb.clk_i);
if(pin_if.master_wb.cyc_i && !pin_if.master_wb.rst_i)
begin
if(request_port.try_get(req))
write_to_bus(req);
if(pin_if.master_wb.we_i)
begin
if(request_port.try_get(req))
write_to_bus(req);
end
else
begin
@(posedge pin_if.master_wb.clk_i);
if(request_port.try_get(req))
write_to_bus(req);
end
end
end
endtask
46,7 → 57,7
pin_if.master_wb.addr_i =req.adr;
pin_if.master_wb.data_i=req.dat;
pin_if.master_wb.stb_i=req.stb;
$display("driver write;at%0d,%0d , %0d ",$time ,pin_if.master_wb.addr_i, pin_if.master_wb.data_i);
endtask
 
endclass
/branches/toomuch/svtb/sim_svtb/wb_run.all
1,5 → 1,5
rm -rf ./work
vlib work
vlog -f compile_sv.f
vsim -c -suppress 4025 -suppress 4029 -novopt wb_ahb_top -do "run 500ns; exit"
vsim -c -suppress 4025 -suppress 4029 -novopt wb_ahb_top -do "run 1000ns; exit"
 
/branches/toomuch/svtb/sim_svtb/wb_coverage.all
2,6 → 2,6
vlib work
vlog -f compile_sv.f
rm cover_rpt.ucdb cover_rpt.out
vsim -c wb_ahb_top -do "run 570ns ; fcover save cover_rpt.ucdb; vcover report -cvg -details cover_rpt.ucdb | tee cover_rpt.out; exit"
vsim -c wb_ahb_top -do "run 1200ns ; fcover save cover_rpt.ucdb; vcover report -cvg -details cover_rpt.ucdb | tee cover_rpt.out; exit"
gvim cover_rpt.out
 

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