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/neorv32/trunk/docs/datasheet/cpu.adoc
1,7 → 1,7
:sectnums:
== NEORV32 Central Processing Unit (CPU)
 
image::riscv_logo.png[width=350,align=center]
image::neorv32_cpu_block.png[width=600,align=center]
 
**Key Features**
 
20,8 → 20,9
** `Zihpm` - hardware performance monitors
** `Zifencei` - instruction stream synchronization
** `Zmmul` - integer multiplication hardware
** `Zxcfu` - custom instructions extension
** `PMP` - physical memory protection
** `Debug` - debug mode
** `Debug` - debug mode (part of the on.chip debugger) including hardware trigger module
* Compatible to the RISC-V user specifications and a subset of the RISC-V privileged architecture specifications - passes the official RISC-V Architecture Tests (v2+)
* Official RISC-V open-source architecture ID
* Standard RISC-V interrupts (_external_, _timer_, _software_) plus 16 _fast_ interrupts
89,13 → 90,13
:sectnums:
=== Full Virtualization
 
Just like the RISC-V ISA the NEORV32 aims to provide _maximum virtualization_ capabilities on CPU _and_ SoC level to
Just like the RISC-V ISA the NEORV32 aims to provide _maximum virtualization_ capabilities on CPU and SoC level to
allow a high standard of **execution safety**. The CPU supports **all** traps specified by the official RISC-V specifications.
footnote:[If the `Zicsr` CPU extension is enabled (implementing the full set of the privileged architecture).]
Thus, the CPU provides defined hardware fall-backs via traps for any expected and unexpected situation (e.g. executing an
malformed instruction word or accessing a not-allocated memory address). For any kind of trap the core is always in a
Thus, the CPU provides defined hardware fall-backs via traps for any expected and unexpected situation (e.g. executing a
malformed instruction or accessing a non-allocated memory address). For any kind of trap the core is always in a
defined and fully synchronized state throughout the whole architecture (i.e. there are no out-of-order operations that
might have to reverted). This allows predictable execution behavior at any time improving overall _execution safety_.
might have to be reverted). This allows a defined and predictable execution behavior at any time improving overall execution safety.
 
**Execution Safety - NEORV32 Virtualization Features**
 
102,7 → 103,7
* Due to the acknowledged memory accesses the CPU is _always_ sync with the memory system
(i.e. there is no speculative execution / no out-of-order states).
* The CPU supports _all_ RISC-V compatible bus exceptions including access exceptions, which are triggered if an
accessed address does not respond or encounters an internal error during access.
accessed address does not respond or encounters an internal device error during access.
* Accessed memory addresses (plain memory, but also memory-mapped devices) need to respond within a fixed time
window. Otherwise a bus access exception is raised.
* The RISC-V specs. state that executing an malformed instruction results in unpredictable behavior. As an additional
255,7 → 256,7
 
.Read-Only "Read-Write" CSRs
[IMPORTANT]
The `misa` and `mtval` CSRs in the NEORV32 are _read-only_.
The <<_misa>> and <<_mtval>> CSRs in the NEORV32 are _read-only_.
Any machine-mode write access to them is ignored and will _not_ cause any exceptions or side-effects to maintain
RISC-V compatibility.
 
338,7 → 339,7
[cols="4,4,2"]
[frame="all",grid="none"]
|======
| **CPU_BOOT_ADDR** | _std_ulogic_vector(31 downto 0)_ | 0x00000000
| **CPU_BOOT_ADDR** | _std_ulogic_vector(31 downto 0)_ | -
3+| This address defines the reset address at which the CPU starts fetching instructions after reset. In terms of the NEORV32 processor, this
generic is configured with the base address of the bootloader ROM (default) or with the base address of the processor-internal instruction
memory (IMEM) if the bootloader is disabled (_INT_BOOTLOADER_EN_ = _false_). See section <<_address_space>> for more information.
347,7 → 348,7
[cols="4,4,2"]
[frame="all",grid="none"]
|======
| **CPU_DEBUG_ADDR** | _std_ulogic_vector(31 downto 0)_ | 0x00000000
| **CPU_DEBUG_ADDR** | _std_ulogic_vector(31 downto 0)_ | -
3+| This address defines the entry address for the "execution based" on-chip debugger. By default, this generic is configured with the base address
of the debugger memory. See section <<_on_chip_debugger_ocd>> for more information.
|======
355,7 → 356,7
[cols="4,4,2"]
[frame="all",grid="none"]
|======
| **CPU_EXTENSION_RISCV_DEBUG** | _boolean_ | false
| **CPU_EXTENSION_RISCV_DEBUG** | _boolean_ | -
3+| Implement RISC-V-compatible "debug" CPU operation mode. See section <<_cpu_debug_mode>> for more information.
|======
 
370,14 → 371,14
see the the _RISC-V Instruction Set Manual - Volume I: Unprivileged ISA_ and _The RISC-V Instruction Set Manual
Volume II: Privileged Architecture_, which are available in the projects `docs/references` folder.
 
.Discovering ISA Extensions
[TIP]
The CPU can discover available ISA extensions via the <<_misa>> CSR and the
`CPU` <<_system_configuration_information_memory_sysinfo, SYSINFO>> register
or by executing an instruction and checking for an _illegal instruction exception_.
 
[NOTE]
The CPU can discover available ISA extensions via the <<_misa>> & <<_mxisa>> CSRs
or by executing an instruction and checking for an _illegal instruction exception_
(-> <<_full_virtualization>>). +
+
Executing an instruction from an extension that is not supported yet or that is currently not enabled
(via the according top entity generic) will raise an _illegal instruction_ exception.
(via the according top entity generic) will raise an illegal instruction exception.
 
 
==== **`A`** - Atomic Memory Access
384,7 → 385,7
 
Atomic memory access instructions allow more sophisticated memory operations like implementing semaphores and mutexes.
The RICS-C specs. defines a specific _atomic_ extension that provides instructions for atomic memory accesses. The `A`
ISA extension is enabled if the `CPU_EXTENSION_RISCV_A` configuration generic is _true_.
ISA extension is enabled if the <<_cpu_extension_riscv_a>> configuration generic is _true_.
In this case the following additional instructions are available:
 
* `lr.w`: load-reservate
414,7 → 415,7
==== **`B`** - Bit-Manipulation Operations
 
The `B` ISA extension adds instructions for bit-manipulation operations. This extension is enabled if the
`CPU_EXTENSION_RISCV_B` configuration generic is _true_.
<<_cpu_extension_riscv_b>> configuration generic is _true_.
The official RISC-V specifications can be found here: https://github.com/riscv/riscv-bitmanip
A copy of the spec is also available in `docs/references`.
 
454,7 → 455,7
==== **`C`** - Compressed Instructions
 
The _compressed_ ISA extension provides 16-bit encodings of commonly used instructions to reduce code space size.
The `C` extension is available when the `CPU_EXTENSION_RISCV_C` configuration generic is _true_.
The `C` extension is available when the <<_cpu_extension_riscv_c>> configuration generic is _true_.
In this case the following instructions are available:
 
* `c.addi4spn` `c.lw` `c.sw` `c.nop` `c.addi` `c.jal` `c.li` `c.addi16sp` `c.lui` `c.srli` `c.srai` `c.andi` `c.sub`
470,7 → 471,7
==== **`E`** - Embedded CPU
 
The embedded CPU extensions reduces the size of the general purpose register file from 32 entries to 16 entries to
decrease physical hardware requirements (for example block RAM). This extensions is enabled when the `CPU_EXTENSION_RISCV_E`
decrease physical hardware requirements (for example block RAM). This extensions is enabled when the <<_cpu_extension_riscv_e>>
configuration generic is _true_. Accesses to registers beyond `x15` will raise and _illegal instruction exception_.
This extension does not add any additional instructions or features.
 
506,7 → 507,7
==== **`M`** - Integer Multiplication and Division
 
Hardware-accelerated integer multiplication and division operations are available when the
`CPU_EXTENSION_RISCV_M` configuration generic is _true_. In this case the following instructions are
<<_cpu_extension_riscv_m>> configuration generic is _true_. In this case the following instructions are
available:
 
* multiplication: `mul` `mulh` `mulhsu` `mulhu`
525,6 → 526,7
of the `M` extensions and is intended for size-constrained setups that require hardware-based
integer multiplications but not hardware-based divisions, which will be computed entirely in software.
This extension requires only ~50% of the hardware utilization of the "full" `M` extension.
It is implemented if the <<_cpu_extension_riscv_zmmul>> configuration generic is _true_.
 
* multiplication: `mul` `mulh` `mulhsu` `mulhu`
 
542,21 → 544,22
==== **`U`** - Less-Privileged User Mode
 
In addition to the basic (and highest-privileged) machine-mode, the _user-mode_ ISA extensions adds a second less-privileged
operation mode. It is implemented if the `CPU_EXTENSION_RISCV_U` configuration generic is _true_.
operation mode. It is implemented if the <<_cpu_extension_riscv_u>> configuration generic is _true_.
Code executed in user-mode cannot access machine-mode CSRs. Furthermore, user-mode access to the address space (like
peripheral/IO devices) can be constrained via the physical memory protection (_PMP_).
Any kind of privilege rights violation will raise an exception to allow full virtualization.
Any kind of privilege rights violation will raise an exception to allow <<_full_virtualization>>.
 
 
==== **`X`** - NEORV32-Specific (Custom) Extensions
 
The NEORV32-specific extensions are always enabled and are indicated by the set `X` bit in the `misa` CSR.
The NEORV32-specific extensions are always enabled and are indicated by the set `X` bit in the <<_misa>> CSR.
 
The most important points of the NEORV32-specific extensions are:
* The CPU provides 16 _fast interrupt_ interrupts (`FIRQ)`, which are controlled via custom bits in the `mie`
and `mip` CSR. This extension is mapped to CSR bits, that are available for custom use (according to the
RISC-V specs). Also, custom trap codes for `mcause` are implemented.
and <<_mip>> CSR. This extension is mapped to CSR bits, that are available for custom use (according to the
RISC-V specs). Also, custom trap codes for <<_mcause>> are implemented.
* All undefined/unimplemented/malformed/illegal instructions do raise an illegal instruction exception (see <<_full_virtualization>>).
* There are <<_neorv32_specific_csrs>>.
 
 
==== **`Zfinx`** Single-Precision Floating-Point Operations
572,7 → 575,7
The NEORV32 floating-point unit used by the `Zfinx` extension is compatible to the _IEEE-754_ specifications.
 
The `Zfinx` extensions only supports single-precision (`.s` instruction suffix), so it is a direct alternative
to the `F` extension. The `Zfinx` extension is implemented when the `CPU_EXTENSION_RISCV_Zfinx` configuration
to the `F` extension. The `Zfinx` extension is implemented when the <<_cpu_extension_riscv_zfinx>> configuration
generic is _true_. In this case the following instructions and CSRs are available:
 
* conversion: `fcvt.s.w` `fcvt.s.wu` `fcvt.w.s` `fcvt.wu.s`
581,7 → 584,7
* sign-injection: `fsgnj.s` `fsgnjn.s` `fsgnjx.s`
* number classification: `fclass.s`
 
* additional CSRs: `fcsr` `frm` `fflags`
* additional CSRs: <<_fcsr>>, <<_frm>>, <<_fflags>>
 
[WARNING]
Fused multiply-add instructions `f[n]m[add/sub].s` are not supported!
603,7 → 606,7
==== **`Zicsr`** Control and Status Register Access / Privileged Architecture
 
The CSR access instructions as well as the exception and interrupt system (= the privileged architecture)
is implemented when the `CPU_EXTENSION_RISCV_Zicsr` configuration generic is _true_.
is implemented when the <<_cpu_extension_riscv_zicsr>> configuration generic is _true_.
 
[IMPORTANT]
If the `Zicsr` extension is disabled the CPU does not provide any _privileged architecture_ features at all!
623,7 → 626,7
[NOTE]
The "wait for interrupt instruction" `wfi` acts like a sleep command. When executed, the CPU is
halted until a valid interrupt request occurs. To wake up again, the according interrupt source has to
be enabled via the `mie` CSR and the global interrupt enable flag in `mstatus` has to be set.
be enabled via the <<_mie>> CSR and the global interrupt enable flag in <<_mstatus>> has to be set.
The `wfi` instruction may also be executed in user-mode without causing an exception as <<_mstatus>> bit
`TW` (timeout wait) is _hardwired_ to zero.
 
648,7 → 651,7
In additions to the base cycle, instructions-retired and time counters the NEORV32 CPU provides
up to 29 hardware performance monitors (HPM 3..31), which can be used to benchmark applications. Each HPM consists of an
N-bit wide counter (split in a high-word 32-bit CSR and a low-word 32-bit CSR), where N is defined via the top's
`HPM_CNT_WIDTH` generic (0..64-bit) and a corresponding event configuration CSR. The event configuration
<<_hpm_cnt_width>> generic (0..64-bit) and a corresponding event configuration CSR. The event configuration
CSR defines the architectural events that lead to an increment of the associated HPM counter.
 
The HPM counters are available if the `Zihpm` ISA extensions is enabled via the <<_cpu_extension_riscv_zihpm>> generic.
659,12 → 662,12
* event configuration: `mhpmevent*` (3..31, depending on `HPM_NUM_CNTS`)
 
[IMPORTANT]
The HPM counter CSR can only be accessed in machine-mode. Hence, the according `mcounteren` CSR bits
The HPM counter CSR can only be accessed in machine-mode. Hence, the according <<_mcounteren>> CSR bits
are always zero and read-only. Any access from less-privileged modes will raise an illegal instruction
exception.
 
[TIP]
Auto-increment of the HPMs can be individually deactivated via the `mcountinhibit` CSR.
Auto-increment of the HPMs can be individually deactivated via the <<_mcountinhibit>> CSR.
 
[TIP]
For a list of all HPM-related CSRs and all provided event configurations
673,7 → 676,7
 
==== **`Zifencei`** Instruction Stream Synchronization
 
The `Zifencei` CPU extension is implemented if the `CPU_EXTENSION_RISCV_Zifencei` configuration
The `Zifencei` CPU extension is implemented if the <<_cpu_extension_riscv_zifencei>> configuration
generic is _true_. It allows manual synchronization of the instruction stream via the following instruction:
 
* `fence.i`
684,6 → 687,30
Any additional flags within the `fence.i` instruction word are ignore by the hardware.
 
 
==== **`Zxcfu`** Custom Instructions Extension (CFU)
 
The `Zxcfu` presents a NEORV32-specific _custom RISC-V_ ISA extension (`Z` = sub-extension, `x` = platform-specific
custom extension, `cfu` = name of the custom extension). When enabled via the <<_cpu_extension_riscv_zxcfu>> configuration
generic, this ISA extensions adds the <<_custom_functions_unit_cfu>> to the CPU core. The CFU is a module that
allows to add **custom RISC-V instructions** to the processor core.
 
The CPU is implemented as ALU co-processor and is integrated right into the CPU's pipeline providing minimal data
transfer latency as it has direct access to the core's register file. Up to 1024 custom instructions can be
implemented within the CFU. These instructions are mapped to an OPCODE space that has been explicitly reserved by
the RISC-V spec for custom extensions.
 
Software can utilize the custom instructions by using _intrinsic functions_, which are inline assembly functions that
behave like "regular" C functions.
 
[TIP]
For more information regarding the CFU see section <<_custom_functions_unit_cfu>>.
 
[TIP]
The CFU / `Zxcfu` ISA extension is intended for application-specific _instructions_.
If you like to add more complex accelerators or interfaces that can also operate independently of
the CPU take a look at the memory-mapped <<_custom_functions_subsystem_cfs>>.
 
 
==== **`PMP`** Physical Memory Protection
 
The NEORV32 physical memory protection (PMP) is compatible to the RISC-V PMP specifications. It can be used
796,6 → 823,7
| Bit-manipulation - single-bit | `B(Zbs)` | `sbset[i]` `sbclr[i]` `sbinv[i]` `sbext[i]` | 3
| Bit-manipulation - shifted-add | `B(Zba)` | `sh1add` `sh2add` `sh3add` | 3
| Bit-manipulation - carry-less multiply | `B(Zbc)` | `clmul` `clmulh` `clmulr` | 3 + 32
| CFU: custom instructions | `Zxcfu` | - | min. 4
|=======================
 
[NOTE]
820,10 → 848,10
* _exceptions_ = synchronous exceptions
* _traps_ = exceptions + interrupts (synchronous or asynchronous exceptions)
 
Whenever an exception or interrupt is triggered, the CPU transfers control to the address stored in `mtvec`
CSR. The cause of the according interrupt or exception can be determined via the content of `mcause`
CSR. The address that reflects the current program counter when a trap was taken is stored to `mepc` CSR.
Additional information regarding the cause of the trap can be retrieved from `mtval` CSR and the processor's
Whenever an exception or interrupt is triggered, the CPU transfers control to the address stored in <<_mtvec>>
CSR. The cause of the according interrupt or exception can be determined via the content of <<_mcause>>
CSR. The address that reflects the current program counter when a trap was taken is stored to <<_mepc>> CSR.
Additional information regarding the cause of the trap can be retrieved from <<_mtval>> CSR and the processor's
<<_internal_bus_monitor_buskeeper>> (for memory access exceptions)
 
The traps are prioritized. If several _synchronous exceptions_ occur at once only the one with highest priority is triggered
839,8 → 867,8
.Interrupt Signal Requirements - Fast Interrupt Requests
[IMPORTANT]
The NEORV32-specific FIRQ request lines are triggered by a one-shot high-level (i.e. rising edge). Each request is buffered in the CPU control
unit until the channel is either disabled (by clearing the according `mie` CSR bit) or the request is explicitly cleared (by setting
the according `mip` CSR bit).
unit until the channel is either disabled (by clearing the according <<_mie>> CSR bit) or the request is explicitly cleared (by setting
the according <<_mip>> CSR bit).
 
.Instruction Atomicity
[NOTE]
862,8 → 890,8
==== Custom Fast Interrupt Request Lines
 
As a custom extension, the NEORV32 CPU features 16 fast interrupt request (FIRQ) lines via the `firq_i` CPU top
entity signals. These interrupts have custom configuration and status flags in the `mie` and `mip` CSRs and also
provide custom trap codes in `mcause`. These FIRQs are reserved for NEORV32 processor-internal usage only.
entity signals. These interrupts have custom configuration and status flags in the <<_mie>> and <<_mip>> CSRs and also
provide custom trap codes in <<_mcause>>. These FIRQs are reserved for NEORV32 processor-internal usage only.
 
 
 
876,16 → 904,16
and the CSR side-effects. A more detailed description of the actual trap triggering events is provided in a further table.
 
[NOTE]
_Asynchronous exceptions_ (= interrupts) set the MSB of `mcause` while _synchronous exception_ (= "software exception")
_Asynchronous exceptions_ (= interrupts) set the MSB of <<_mcause>> while _synchronous exception_ (= "software exception")
clear the MSB.
 
**Table Annotations**
 
The "Prio." column shows the priority of each trap. The highest priority is 1. The "`mcause`" column shows the
cause ID of the according trap that is written to `mcause` CSR. The "[RISC-V]" columns show the interrupt/exception code value from the
cause ID of the according trap that is written to <<_mcause>> CSR. The "[RISC-V]" columns show the interrupt/exception code value from the
official RISC-V privileged architecture manual. The "[C]" names are defined by the NEORV32 core library (the runtime environment _RTE_) and can
be used in plain C code. The "`mepc`" and "`mtval`" columns show the value written to
`mepc` and `mtval` CSRs when a trap is triggered:
<<_mepc>> and <<_mtval>> CSRs when a trap is triggered:
 
* _I-PC_ - address of interrupted instruction (instruction has not been execute/completed yet)
* _B-ADR_- bad memory access address that cause the trap
953,12 → 981,12
| _TRAP_CODE_MTI_ | processor-internal machine timer overflow OR user-defined processor-external source (via dedicated top-entity signal)
|=======================
 
.Instruction Address Misaligned Exception
.Misaligned Instruction Address Exception
[NOTE]
For 32-bit-only instructions (= no `C` extension) the misaligned instruction exception
is raised if bit 1 of the fetch address is set (i.e. not on a 32-bit boundary). If the `C` extension is implemented
there will never be a misaligned instruction exception _at all_.
In both cases bit 0 of the program counter (and all related registers) is hardwired to zero.
In both cases bit 0 of the program counter (and all related CSRs) is hardwired to zero.
 
 
<<<
966,72 → 994,75
:sectnums:
==== Bus Interface
 
The CPU provides two independent bus interfaces: One for fetching instructions (`i_bus_*`) and one for
accessing data (`d_bus_*`) via load and store operations. Both interfaces use the same interface protocol.
The NEORV32 CPU implements a 32-bit machine with separated instruction and data interfaces making the CPU a
**Harvard Architecture**: the _instruction fetch interface_ (`i_bus_*`) is used for fetching instruction and the
_data access interface_ (`d_bus_*`) is used to access data via load and store operations.
Each of this interfaces can access an address space of up to 2^32^ bytes (4GB).
The following table shows the signals of the data and instruction interfaces as seen from the CPU (`*_o` signals are driven
by the CPU / outputs, `*_i` signals are read by the CPU / inputs). Both interfaces use the same protocol.
 
:sectnums:
===== Address Space
 
The CPU is a 32-bit architecture with separated instruction and data interfaces making it a Harvard
Architecture. Each of this interfaces can access an address space of up to 2^32^ bytes (4GB). The memory
system is based on 32-bit words with a minimal granularity of 1 byte. Please note, that the NEORV32 CPU
does not support unaligned memory accesses _in hardware_ - however, a software-based handling can be
implemented as any unaligned memory access will trigger an according exception.
 
:sectnums:
===== Interface Signals
 
The following table shows the signals of the data and instruction interfaces seen from the CPU
(`*_o` signals are driven by the CPU / outputs, `*_i` signals are read by the CPU / inputs).
 
.CPU bus interface
[cols="<2,^1,<7"]
.CPU bus interfaces ()
[cols="<2,^1,^1,<6"]
[options="header",grid="rows"]
|=======================
| Signal | Size | Function
| `bus_addr_o` | 32 | access address
| `bus_rdata_i` | 32 | data input for read operations
| `bus_wdata_o` | 32 | data output for write operations
| `bus_ben_o` | 4 | byte enable signal for write operations
| `bus_we_o` | 1 | bus write access
| `bus_re_o` | 1 | bus read access
| `bus_lock_o` | 1 | exclusive access request
| `bus_ack_i` | 1 | accessed peripheral indicates a successful completion of the bus transaction
| `bus_err_i` | 1 | accessed peripheral indicates an error during the bus transaction
| `bus_fence_o` | 1 | this signal is set for one cycle when the CPU executes a data/instruction fence operation
| `bus_priv_o` | 2 | current CPU privilege level
| Signal | Width | Direction | Description
| `i/d_bus_addr_o` | 32 | out | access address
| `i/d_bus_rdata_i` | 32 | in | data input for read operations
| `i/d_bus_wdata_o` | 32 | out | data output for write operations
| `i/d_bus_ben_o` | 4 | out | byte enable signal for write operations
| `i/d_bus_we_o` | 1 | out | bus write access (always zero for instruction fetches)
| `i/d_bus_re_o` | 1 | out | bus read access
| `i/d_bus_lock_o` | 1 | out | exclusive access request
| `i/d_bus_ack_i` | 1 | in | accessed peripheral indicates a successful completion of the bus transaction
| `i/d_bus_err_i` | 1 | in | accessed peripheral indicates an error during the bus transaction
| `i/d_bus_fence_o` | 1 | out | this signal is set for one cycle when the CPU executes an instruction/data fence operation
| `i/d_bus_priv_o` | 2 | out | current CPU privilege level
|=======================
 
.Pipelined Transfers
[NOTE]
Currently, there a no pipelined or overlapping operations implemented within the same bus interface.
So only a single transfer request can be "on the fly" (pending) at once.
So only a single transfer request can be "on the fly" (pending) at once. However, this is no real drawback. The
minimal possible latency for a single access is two cycles, which equals the CPU's minimal execution latency
for a single instruction.
 
.Unaligned Memory Accesses
[NOTE]
Please note, that the NEORV32 CPU does not support the handling of unaligned memory accesses _in hardware_. Any
unaligned memory access will raise an exception that can can be used to handle such accesses in _software_.
 
 
:sectnums:
===== Protocol
 
A bus request is triggered either by the `bus_re_o` signal (for reading data) or by the `bus_we_o` signal (for
writing data). These signals are active for exactly one cycle and initiate either a read or a write transaction. The transaction is
completed when the accessed peripheral either sets the `bus_ack_i` signal (-> successful completion) or the
`bus_err_i` signal is set (-> failed completion). All these control signals are only active (= high) for one
single cycle. An error indicated via the `bus_err_i` signal during a transfer will trigger the according instruction bus
access fault or load/store bus access fault exception.
An actual bus request is triggered either by the `*_bus_re_o` signal (for reading data) or by the `*_bus_we_o` signal
(for writing data). In case of a request, one of these signals is high for exactly one cycle. The transaction is
completed when the accessed peripheral/memory either sets the `*_bus_ack_i` signal (-> successful completion) or the
`*_bus_err_i` signal (-> failed completion). These bus response signal are also set only for one cycle active.
An error indicated by the `*_bus_err_i` signal will raise the according "instruction bus access fault" or
"load/store bus access fault" exception.
 
[NOTE]
The transfer can be completed directly in the same cycle as it was initiated (via the `bus_re_o` or `bus_we_o`
signal) if the peripheral sets `bus_ack_i` or `bus_err_i` high for one cycle. However, in order to shorten the critical path such "asynchronous"
completion should be avoided. The default processor-internal module provide exactly **one cycle delay** between initiation and completion of transfers.
**Minimal Response Latency**
 
.Bus Keeper: Processor-internal memories and memory-mapped devices with variable / high latency
[IMPORTANT]
Processor-internal peripherals or memories do not have to respond within one cycle after the transfer initiation (= latency > 1 cycle).
However, the bus transaction has to be completed (= acknowledged) within a certain **response time window**. This time window is defined
by the global `max_proc_int_response_time_c` constant (default = 15 cycles) from the processor's VHDL package file (`rtl/neorv32_package.vhd`).
It defines the maximum number of cycles after which an _unacknowledged_ processor-internal bus transfer will timeout and raise a **bus fault exception**.
The _BUSKEEPER_ hardware module (see section <<_internal_bus_monitor_buskeeper>>) keeps track of all _internal_ bus transactions. If any bus operations times out
(for example when accessing "address space holes") this unit will issue a bus error to the CPU that will raise the according instruction fetch or data access bus exception.
Note that **the bus keeper does not track external accesses via the external memory bus interface**. However, the external memory bus interface also provides
an _optional_ bus timeout (see section <<_processor_external_memory_interface_wishbone_axi4_lite>>).
The transfer can be completed directly in the same cycle as it was initiated (via the `*_bus_re_o` or `*_bus_we_o`
signal) if the peripheral sets `*_bus_ack_i` or `*_bus_err_i` high for one cycle. However, in order to shorten the
critical path such "asynchronous" completion should be avoided. The default NEORV32 processor-internal modules provide
exactly **one cycle delay** between initiation and completion of transfers.
 
**Maximal Response Latency**
 
Processor-internal peripherals or memories do not have to respond within one cycle after a bus request has been initiated.
However, the bus transaction has to be completed (= acknowledged) within a certain **response time window**. This time window
is defined by the global `max_proc_int_response_time_c` constant (default = 15 cycles; processor's VHDL package file `rtl/neorv32_package.vhd`).
It defines the maximum number of cycles after which an _unacknowledged_ (`*_bus_ack_i` or `*_bus_err_i` both not set) processor-internal bus
transfer will time out and raises a **bus fault exception**. The <<_internal_bus_monitor_buskeeper>> keeps track of all _internal_ bus
transactions to enforce this time window.
 
If any bus operations times out (for example when accessing "address space holes") the BUSKEEPER will issue a bus
error to the CPU that will raise the according instruction fetch or data access bus exception.
Note that **the bus keeper does not track external accesses via the external memory bus interface**. However,
the external memory bus interface also provides an _optional_ bus timeout (see section <<_processor_external_memory_interface_wishbone_axi4_lite>>).
 
**Exemplary Bus Accesses**
 
.Example bus accesses: see read/write access description below
1045,7 → 1076,7
 
**Write Access**
 
For a write access, the accessed address (`bus_addr_o`), the data to be written (`bus_wdata_o`) and the byte
For a write access, the access address (`bus_addr_o`), the data to be written (`bus_wdata_o`) and the byte
enable signals (`bus_ben_o`) are set when bus_we_o goes high. These three signals are kept stable until the
transaction is completed. In the example the accessed peripheral cannot answer directly in the next
cycle after issuing. Here, the transaction is successful and the peripheral sets the `bus_ack_i` signal several
1092,9 → 1123,9
 
**Memory Barriers**
 
Whenever the CPU executes a fence instruction, the according interface signal is set high for one cycle
(`d_bus_fence_o` for a _fence_ instruction; `i_bus_fence_o` for a _fencei_ instruction). It is the task of the
memory system to perform the necessary operations (like a cache flush and refill).
Whenever the CPU executes a _fence_ instruction, the according interface signal is set high for one cycle
(`d_bus_fence_o` for a `fence` instruction; `i_bus_fence_o` for a `fencei` instruction). It is the task of the
memory system to perform the necessary operations (for example a cache flush and refill).
 
 
 
1128,7 → 1159,7
interrupt control) is done by the software (to be more specific, this is done by the `crt0.S` start-up code).
 
During the very early boot process (where `crt0.S` is running) there is no chance for undefined behavior due to
the lack of dedicated hardware resets of certain CSRs. For example the machine interrupt-enable CSR (`mie`)
the lack of dedicated hardware resets of certain CSRs. For example the machine interrupt-enable CSR <<_mie>>
does not provide a dedicated reset. The value after reset of this register is uncritical as interrupts cannot fire
because the global interrupt enabled flag in the status register (`mstatsus(mie)`) _do_ provide a dedicated
hardware reset setting this bit to low (globally disabling interrupts).
1139,10 → 1170,17
(VHDL `'-'`) is used for initialization of all uncritical registers, effectively generating a flip-flop without a
reset. However, certain applications or situations (like advanced gate-level / timing simulations) might
require a more deterministic reset state. For this case, a defined reset level (reset-to-low) of all CPU registers can
be enabled ba enabling a constant in the main VHDL package file (`rtl/core/neorv32_package.vhd`):
be enabled by enabling a constant in the main VHDL package file (`rtl/core/neorv32_package.vhd`):
 
[source,vhdl]
----
-- "critical" number of PMP regions --
constant dedicated_reset_c : boolean := false; -- use dedicated hardware reset value for UNCRITICAL registers (FALSE=reset value is irrelevant (might simplify HW), default; TRUE=defined LOW reset value)
-- use dedicated hardware reset value for UNCRITICAL registers --
-- FALSE=reset value is irrelevant (might simplify HW), default; TRUE=defined LOW reset value
constant dedicated_reset_c : boolean := false;
----
 
 
<<<
// ####################################################################################################################
 
include::cpu_cfu.adoc[]
/neorv32/trunk/docs/datasheet/cpu_cfu.adoc
0,0 → 1,154
<<<
:sectnums:
=== Custom Functions Unit (CFU)
 
The Custom Functions Unit is the central part of the <<_zxcfu_custom_instructions_extension_cfu>> and represents
the actual hardware module, which is used to implement _custom RISC-V instructions_. The concept of the NEORV32
CFU has been highly inspired by https://github.com/google/CFU-Playground[google's CFU-Playground].
 
The CFU is intended for operations that are inefficient in terms of performance, latency, energy consumption or
program memory requirements when implemented in pure software. Some potential application fields and exemplary
use-cases might include:
 
* **AI:** sub-word / vector / SIMD operations like adding all four bytes of a 32-bit data word
* **Cryptographic:** bit substitution and permutation
* **Communication:** conversions like binary to gray-code
* **Image processing:** look-up-tables for color space transformations
* implementing instructions from other RISC-V ISA extensions that are not yet supported by the NEORV32
 
[NOTE]
The CFU is not intended for complex and autonomous functional units that implement complete accelerators
like block-based AES de-/encoding). Such accelerator can be implemented within the <<_custom_functions_subsystem_cfs>>.
A comparison of all chip-internal hardware extension options is provided in the user guide section
https://stnolting.github.io/neorv32/ug/#_adding_custom_hardware_modules[Adding Custom Hardware Modules].
 
 
:sectnums:
==== Custom CFU Instructions - General
 
The custom instruction utilize a specific instruction space that has been explicitly reserved for user-defined
extensions by the RISC-V specifications ("_Guaranteed Non-Standard Encoding Space_"). The NEORV32 CFU uses the
_CUSTOM0_ opcode to identify custom instructions. The binary encoding of this opcode is `0001011`.
 
The custom instructions processed by the CFU use the 32-bit **R2-type** RISC-V instruction format, which consists
of six bit-fields:
 
* `funct7`: 7-bit immediate
* `rs2`: address of second source register
* `rs1`: address of first source register
* `funct3`: 3-bit immediate
* `rd`: address of destination register
* `opcode`: always `0001011` to identify custom instructions
 
.CFU instruction format (RISC-V R2-type)
image::cfu_r2type_instruction.png[align=center]
 
[NOTE]
Obviously, all bit-fields including the immediates have to be static at compile time.
 
.Custom Instructions - Exceptions
[NOTE]
The CPU control logic can only check the _CUSTOM0_ opcode of the custom instructions to check if the
instruction word is valid. It cannot check the `funct3` and `funct7` bit-fields since they are
implementation-defined. Hence, a custom CFU instruction can never raise an illegal instruction exception.
However, custom will raise an illegal instruction exception if the CFU is not enabled/implemented
(i.e. `Zxcfu` ISA extension is not enabled).
 
The CFU operates on the two source operands and return the processing result to the destination register.
The actual instruction to be performed can be defined by using the `funct7` and `funct3` bit fields.
These immediate bit-fields can also be used to pass additional data to the CFU like offsets, look-up-tables
addresses or shift-amounts. However, the actual functionality is completely user-defined.
 
 
:sectnums:
==== Using Custom Instructions in Software
 
The custom instructions provided by the CFU are included into plain C code by using **intrinsics**. Intrinsics
behave like "normal" functions but under the hood they are a set of macros that hide the complexity of inline assembly.
Using such intrinsics removes the need to modify the compiler, built-in libraries and the assembler when including custom
instructions.
 
The NEORV32 software framework provides 8 pre-defined custom instructions macros, which are defined in
`sw/lib/include/neorv32_cpu_cfu.h`. Each intrinsic provides an implicit definition of the instruction word's
`funct3` bit-field:
 
.CFU instruction prototypes
[source,c]
----
neorv32_cfu_cmd0(funct7, rs1, rs2) // funct3 = 000
neorv32_cfu_cmd1(funct7, rs1, rs2) // funct3 = 001
neorv32_cfu_cmd2(funct7, rs1, rs2) // funct3 = 010
neorv32_cfu_cmd3(funct7, rs1, rs2) // funct3 = 011
neorv32_cfu_cmd4(funct7, rs1, rs2) // funct3 = 100
neorv32_cfu_cmd5(funct7, rs1, rs2) // funct3 = 101
neorv32_cfu_cmd6(funct7, rs1, rs2) // funct3 = 110
neorv32_cfu_cmd7(funct7, rs1, rs2) // funct3 = 111
----
 
Each intrinsic functions always returns a 32-bit value (the processing result). Furthermore,
each intrinsic function requires three arguments:
 
* `funct7` - 7-bit immediate
* `rs2` - source operand 2, 32-bit
* `rs1` - source operand 1, 32-bit
 
The `funct7` bit-field is used to pass a 7-bit literal to the CFU. The `rs1` and `rs2` arguments to pass the
actual data to the CFU. These arguments can be populated with variables or literals. The following example
show how to pass arguments when executing `neorv32_cfu_cmd6`: `funct7` is set to all-zero, `rs1` is given
the literal _2751_ and `rs2` is given a variable that contains the return value from `some_function()`.
 
.CFU instruction usage example
[source,c]
----
uint32_t opb = some_function();
uint32_t res = neorv32_cfu_cmd6(0b0000000, 2751, opb);
----
 
.CFU Example Program
[TIP]
There is a simple example program for the CFU, which shows how to use the _default_ CFU hardware module.
The example program is located in `sw/example/demo_cfu`.
 
 
:sectnums:
==== Custom Instructions Hardware
 
The actual functionality of the CFU's custom instruction is defined by the logic in the CFU itself.
It is the responsibility of the designer to implement this logic within the CFU hardware module
`rtl/core/neorv32_cpu_cp_cfu.vhd`.
 
The CFU hardware module receives the data from instruction word's immediate bit-fields and also
the operation data, which is fetched from the CPU's register file.
 
.CFU instruction data passing example
[source,c]
----
uint32_t opb = 0x12345678;
uint32_t res = neorv32_cfu_cmd6(0b0100111, 0x00cafe00, opb);
----
 
In this example the CFU hardware module receives the two source operands as 32-bit signal
and the immediate values as 7-bit and 3-bit signals:
 
* `rs1_i` (32-bit) contains the data from the `rs1` register (here = `0x00cafe00`)
* `rs2_i` (32-bit) contains the data from the `rs2` register (here = 0x12345678)
* `control.funct3` (3-bit) contains the immediate value from the `funct3` bit-field (here = `0b110`; "cmd6")
* `control.funct7` (7-bit) contains the immediate value from the `funct7` bit-field (here = `0b0100111`)
 
The CFU executes the according instruction (for example this is selected by the `control.funct3` signal)
and provides the operation result in the 32-bit `control.result` signal. The processing can be entirely
combinatorial, so the result is available at the end of the current clock cycle. Processing can also
take several clock cycles and may also include internal states and memories. As soon as the CFU has
completed operations it sets the `control.done` signal high.
 
.CFU Hardware Example & More Details
[TIP]
The default CFU module already implement some exemplary instructions that are used for illustration
by the CFU example program. See the CFU's VHDL source file (`rtl/core/neorv32_cpu_cp_cfu.vhd`), which
is highly commented to explain the available signals and the handshake with the CPU pipeline.
 
.CFU Execution Time
[NOTE]
The CFU is not required to finish processing within a bound time.
However, the designer should keep in mind that the CPU is **stalled** until the CFU has finished processing.
This also means the CPU cannot react to pending interrupts. Nevertheless, interrupt requests will still be queued.
/neorv32/trunk/docs/datasheet/cpu_csr.adoc
30,11 → 30,11
.CSR description
[cols="4,27,>7"]
[frame="topbot",grid="none"]
|======
|=======================
| _Address_ | _Description_ | _ASM alias_
3+| Reset value: _CSR content after hardware reset_ (also see <<_cpu_hardware_reset>>)
3+| _Detailed description_
|======
|=======================
 
.Not Implemented CSRs / CSR Bits
[IMPORTANT]
110,6 → 110,8
| 0xf13 | <<_mimpid>> | _CSR_MIMPID_ | r/- | Machine implementation ID / version |
| 0xf14 | <<_mhartid>> | _CSR_MHARTID_ | r/- | Machine thread ID |
| 0xf15 | <<_mconfigptr>> | _CSR_MCONFIGPTR_ | r/- | Machine configuration pointer register |
6+^| **<<_neorv32_specific_csrs>>**
| 0xfc0 | <<_mxisa>> | _CSR_MXISA_ | r/- | NEORV32-specific "extended" machine CPU ISA and extensions |
|=======================
 
 
128,13 → 130,13
 
[cols="4,27,>7"]
[frame="topbot",grid="none"]
|======
|=======================
| 0x001 | **Floating-point accrued exceptions** | `fflags`
3+| Reset value: _UNDEFINED_
3+| The `fflags` CSR is compatible to the RISC-V specifications. It shows the accrued ("accumulated")
exception flags in the lowest 5 bits. This CSR is only available if a floating-point CPU extension is enabled.
See the RISC-V ISA spec for more information.
|======
|=======================
 
 
:sectnums!:
142,13 → 144,13
 
[cols="4,27,>7"]
[frame="topbot",grid="none"]
|======
|=======================
| 0x002 | **Floating-point dynamic rounding mode** | `frm`
3+| Reset value: _UNDEFINED_
3+| The `frm` CSR is compatible to the RISC-V specifications and is used to configure the rounding modes using
the lowest 3 bits. This CSR is only available if a floating-point CPU extension is enabled. See the RISC-V
ISA spec for more information.
|======
|=======================
 
 
:sectnums!:
156,13 → 158,13
 
[cols="4,27,>7"]
[frame="topbot",grid="none"]
|======
|=======================
| 0x003 | **Floating-point control and status register** | `fcsr`
3+| Reset value: _UNDEFINED_
3+| The `fcsr` CSR is compatible to the RISC-V specifications. It provides combined read/write access to the
`fflags` and `frm` CSRs. This CSR is only available if a floating-point CPU extension is enabled. See the
RISC-V ISA spec for more information.
|======
|=======================
 
 
<<<
175,12 → 177,12
 
[cols="4,27,>7"]
[frame="topbot",grid="none"]
|======
|=======================
| 0x30a | **Machine environment configuration register** | `menvcfg`
3+| Reset value: _0x00000000_
3+| The features of this CSR are not implemented yet. The register is read-only. NOTE: This register
only exists if the `U` ISA extensions is enabled.
|======
|=======================
 
 
:sectnums!:
188,12 → 190,12
 
[cols="4,27,>7"]
[frame="topbot",grid="none"]
|======
|=======================
| 0x31a | **Machine environment configuration register - high word** | `menvcfgh`
3+| Reset value: _0x00000000_
3+| The features of this CSR are not implemented yet. The register is read-only. NOTE: This register
only exists if the `U` ISA extensions is enabled.
|======
|=======================
 
 
<<<
206,12 → 208,12
 
[cols="4,27,>7"]
[frame="topbot",grid="none"]
|======
|=======================
| 0x300 | **Machine status register** | `mstatus`
3+| Reset value: _0x00000000_
3+| The `mstatus` CSR is compatible to the RISC-V specifications. It shows the CPU's current execution state.
The following bits are implemented (all remaining bits are always zero and are read-only).
|======
|=======================
 
.Machine status register
[cols="^1,<3,^1,<5"]
232,12 → 234,12
 
[cols="4,27,>7"]
[frame="topbot",grid="none"]
|======
|=======================
| 0x301 | **ISA and extensions** | `misa`
3+| Reset value: _configuration dependant_
3+| Reset value: _defined_
3+| The `misa` CSR gives information about the actual CPU features. The lowest 26 bits show the implemented
CPU extensions. The following bits are implemented (all remaining bits are always zero and are read-only).
|======
|=======================
 
[IMPORTANT]
The `misa` CSR is not fully RISC-V-compatible as it is read-only. Hence, implemented CPU
260,8 → 262,8
|=======================
 
[TIP]
Information regarding the implemented RISC-V `Z*` _sub-extensions_ (like `Zicsr` or `Zfinx`) can be found
in the `CPU` <<_system_configuration_information_memory_sysinfo, SYSINFO>> register.
Machine-mode software can discover available `Z*` _sub-extensions_ (like `Zicsr` or `Zfinx`) by checking the NEORV32-specific
<<_mxisa>> CSR.
 
 
:sectnums!:
269,7 → 271,7
 
[cols="4,27,>7"]
[frame="topbot",grid="none"]
|======
|=======================
| 0x304 | **Machine interrupt-enable register** | `mie`
3+| Reset value: _UNDEFINED_
3+| The `mie` CSR is compatible to the RISC-V specifications and features custom extensions for the fast
276,7 → 278,7
interrupt channels. It is used to enabled specific interrupts sources. Please note that interrupts also have to be
globally enabled via the `CSR_MSTATUS_MIE` flag of the `mstatus` CSR. The following bits are implemented
(all remaining bits are always zero and are read-only):
|======
|=======================
 
.Machine ISA and extension register
[cols="^1,<3,^1,<5"]
295,13 → 297,13
 
[cols="4,27,>7"]
[frame="topbot",grid="none"]
|======
|=======================
| 0x305 | **Machine trap-handler base address** | `mtvec`
3+| Reset value: _UNDEFINED_
3+| The `mtvec` CSR is compatible to the RISC-V specifications. It stores the base address for ALL machine
traps. Thus, it defines the main entry point for exception/interrupt handling regardless of the actual trap
source. The lowest two bits of this register are always zero and cannot be modified (= address mode only).
|======
|=======================
 
.Machine trap-handler base address
[cols="^1,^1,<8"]
318,7 → 320,7
 
[cols="4,27,>7"]
[frame="topbot",grid="none"]
|======
|=======================
| 0x306 | **Machine counter enable** | `mcounteren`
3+| Reset value: _UNDEFINED_
3+| The `mcounteren` CSR is compatible to the RISC-V specifications. The bits of this CSR define which
325,7 → 327,7
counter/timer CSR can be accessed (read) from code running in a less-privileged modes. For example,
if user-level code tries to read from a counter/timer CSR without enabled access, an illegal instruction
exception is raised. NOTE: If the `U` ISA extension is not enabled this CSR does not exist.
|======
|=======================
 
.Machine counter enable register
[cols="^1,<3,^1,<5"]
344,12 → 346,12
 
[cols="4,27,>7"]
[frame="topbot",grid="none"]
|======
|=======================
| 0x310 | **Machine status register - high word** | `mstatush`
3+| Reset value: _0x00000000_
3+| The `mstatush` CSR is compatible to the RISC-V specifications. In combination with <<_mstatus>> it shows additional
execution state information. The NEORV32 `mstatush` CSR is read-only and all bits are hardwired to zero.
|======
|=======================
 
[NOTE]
The NEORV32 `mstatush` CSR is not a physical register. All write access are ignored and all read accesses will always
368,12 → 370,12
 
[cols="4,27,>7"]
[frame="topbot",grid="none"]
|======
|=======================
| 0x340 | **Scratch register for machine trap handlers** | `mscratch`
3+| Reset value: _UNDEFINED_
3+| The `mscratch` CSR is compatible to the RISC-V specifications. It is a general purpose scratch register that
can be used by the exception/interrupt handler. The content pf this register after reset is undefined.
|======
|=======================
 
:sectnums!:
===== **`mepc`**
380,13 → 382,13
 
[cols="4,27,>7"]
[frame="topbot",grid="none"]
|======
|=======================
| 0x341 | **Machine exception program counter** | `mepc`
3+| Reset value: _UNDEFINED_
3+| The `mepc` CSR is compatible to the RISC-V specifications. For exceptions (like an illegal instruction) this
register provides the address of the exception-causing instruction. For Interrupt (like a machine timer
interrupt) this register provides the address of the next not-yet-executed instruction.
|======
|=======================
 
:sectnums!:
===== **`mcause`**
393,11 → 395,11
 
[cols="4,27,>7"]
[frame="topbot",grid="none"]
|======
|=======================
| 0x342 | **Machine trap cause** | `mcause`
3+| Reset value: _UNDEFINED_
3+| The `mcause` CSR is compatible to the RISC-V specifications. It show the cause ID for a taken exception.
|======
|=======================
 
.Machine trap cause register
[cols="^1,^1,<8"]
414,13 → 416,13
 
[cols="4,27,>7"]
[frame="topbot",grid="none"]
|======
|=======================
| 0x343 | **Machine bad address or instruction** | `mtval`
3+| Reset value: _UNDEFINED_
3+| The `mtval` CSR is compatible to the RISC-V specifications. When a trap is triggered, the CSR shows either
the faulting address (for misaligned/faulting load/stores/fetch) or the faulting instruction itself (for illegal
instructions). For interrupts the CSR is set to zero.
|======
|=======================
 
.Machine bad address or instruction register
[cols="^5,^5"]
442,7 → 444,7
 
[cols="4,27,>7"]
[frame="topbot",grid="none"]
|======
|=======================
| 0x344 | **Machine interrupt Pending** | `mip`
3+| Reset value: _0x00000000_
3+| The `mip` CSR is compatible to the RISC-V specifications and also provides custom extensions. It shows currently _pending_ interrupts.
450,7 → 452,7
be cleared/acknowledged within the according interrupt-generating device.
The upper 16 bits represent the status of the CPU's fast interrupt request lines (FIRQ). Once triggered, these _have to be cleared_ again by setting
the according `mip` bit in the interrupt handler routine to clear the current interrupt request.
|======
|=======================
 
.Machine interrupt pending register
[cols="^1,<3,^1,<5"]
487,13 → 489,13
 
[cols="4,27,>7"]
[frame="topbot",grid="none"]
|======
|=======================
| 0x3a0 - 0x3af| **Physical memory protection configuration registers** | `pmpcfg0` - `pmpcfg15`
3+| Reset value: _0x00000000_
3+| The `pmpcfg*` CSRs are compatible to the RISC-V specifications. They are used to configure the protected
regions, where each `pmpcfg*` CSR provides configuration bits for four regions. The following bits (for the
first PMP configuration entry) are implemented (all remaining bits are always zero and are read-only):
|======
|=======================
 
.Physical memory protection configuration register entry
[cols="^1,^3,^1,<11"]
514,12 → 516,12
 
[cols="4,27,>7"]
[frame="topbot",grid="none"]
|======
|=======================
| 0x3b0 - 0x3ef| **Physical memory protection address registers** | `pmpaddr0` - `pmpaddr63`
3+| Reset value: _UNDEFINED_
3+| The `pmpaddr*` CSRs are compatible to the RISC-V specifications. They are used to configure the PMP region's base
address and the region size.
|======
|=======================
 
[NOTE]
When configuring PMP make sure to set `pmpaddr*` before activating the according region via
545,30 → 547,34
[IMPORTANT]
If _CPU_CNT_WIDTH_ is less than 64 (the default value) and greater than or equal 32, the according
MSBs of `[m]cycleh` and `[m]instreth` are read-only and always read as zero. This configuration
will also set the _SYSINFO_CPU_ZXSCNT_ flag ("small counters") in the `CPU`
<<_system_configuration_information_memory_sysinfo, SYSINFO>> register. +
will also set the _CSR_MXISA_ZXSCNT_ flag ("small counters") in the <<_mxisa>> CSR. +
+
If _CPU_CNT_WIDTH_ is less than 32 and greater than 0, the `[m]cycleh` and `[m]instreth` CSRs are hardwired to zero
and any write access to them is ignored. Furthermore, the according MSBs of `[m]cycle` and `[m]instret` are read-only
and always read as zero. This configuration will also set the _SYSINFO_CPU_ZXSCNT_ flag ("small counters") in
the `CPU` <<_system_configuration_information_memory_sysinfo, SYSINFO>> register. +
and always read as zero. This configuration will also set the _CSR_MXISA_ZXSCNT_ flag ("small counters") in
the <<_mxisa>> CSR. +
+
If _CPU_CNT_WIDTH_ is 0, the <<_cycleh>> and <<_instreth>> / <<_mcycleh>> and <<_minstreth>> CSRs are hardwired to zero
and any write access to them is ignored.
 
.Counter Increment During Debugging
[NOTE]
The `[m]cycle[h]` and `[m]instret[h]` counters do not increment when the CPU is in debug mode.
See section <<_cpu_debug_mode>> for more information.
 
 
:sectnums!:
===== **`cycle[h]`**
 
[cols="4,27,>7"]
[frame="topbot",grid="none"]
|======
|=======================
| 0xc00 | **Cycle counter - low word** | `cycle`
| 0xc80 | **Cycle counter - high word** | `cycleh`
3+| Reset value: _UNDEFINED_
3+| The `cycle[h]` CSR is compatible to the RISC-V specifications. It shows the lower/upper 32-bit of the 64-bit cycle
counter. The `cycle[h]` CSR is a read-only shadowed copy of the `mcycle[h]` CSR.
|======
|=======================
 
 
:sectnums!:
576,7 → 582,7
 
[cols="4,27,>7"]
[frame="topbot",grid="none"]
|======
|=======================
| 0xc01 | **System time - low word** | `time`
| 0xc81 | **System time - high word** | `timeh`
3+| Reset value: _UNDEFINED_
584,7 → 590,7
time. The system time is either generated by the processor-internal _MTIME_ system timer unit (if _IO_MTIME_EN_ = _true_) or can be provided by an
external timer unit via the processor's `mtime_i` signal (if _IO_MTIME_EN_ = _false_).
CSR is read-only. Change the system time via the _MTIME_ unit.
|======
|=======================
 
 
:sectnums!:
592,13 → 598,13
 
[cols="4,27,>7"]
[frame="topbot",grid="none"]
|======
|=======================
| 0xc02 | **Instructions-retired counter - low word** | `instret`
| 0xc82 | **Instructions-retired counter - high word** | `instreth`
3+| Reset value: _UNDEFINED_
3+| The `instret[h]` CSR is compatible to the RISC-V specifications. It shows the lower/upper 32-bit of the 64-bit retired
instructions counter. The `instret[h]` CSR is a read-only shadowed copy of the `minstret[h]` CSR.
|======
|=======================
 
 
:sectnums!:
606,13 → 612,13
 
[cols="4,27,>7"]
[frame="topbot",grid="none"]
|======
|=======================
| 0xb00 | **Machine cycle counter - low word** | `mcycle`
| 0xb80 | **Machine cycle counter - high word** | `mcycleh`
3+| Reset value: _UNDEFINED_
3+| The `mcycle[h]` CSR is compatible to the RISC-V specifications. It shows the lower/upper 32-bit of the 64-bit cycle
counter. The `mcycle[h]` CSR can also be written when in machine mode and is mirrored to the `cycle[h]` CSR.
|======
|=======================
 
 
:sectnums!:
620,13 → 626,13
 
[cols="4,27,>7"]
[frame="topbot",grid="none"]
|======
|=======================
| 0xb02 | **Machine instructions-retired counter - low word** | `minstret`
| 0xb82 | **Machine instructions-retired counter - high word** | `minstreth`
3+| Reset value: _UNDEFINED_
3+| The `minstret[h]` CSR is compatible to the RISC-V specifications. It shows the lower/upper 32-bit of the 64-bit retired
instructions counter. The `minstret[h]` CSR also be written when in machine mode and is mirrored to the `instret[h]` CSR.
|======
|=======================
 
 
 
660,12 → 666,18
bits are hardwired to zero.
 
 
.Counter Increment During Debugging
[NOTE]
All HPM counters do not increment when the CPU is in debug mode.
See section <<_cpu_debug_mode>> for more information.
 
 
:sectnums!:
===== **`mhpmevent`**
 
[cols="4,27,>7"]
[frame="topbot",grid="none"]
|======
|=======================
| 0x232 -0x33f | **Machine hardware performance monitor event selector** | `mhpmevent3` - `mhpmevent31`
3+| Reset value: _UNDEFINED_
3+| The `mhpmevent*` CSRs are compatible to the RISC-V specifications. The configuration of these CSR define
674,7 → 686,7
the enabled events is observed (logical OR). Note that the counter will only increment by 1 step per clock
cycle even if more than one event is observed. If the CPU is in sleep mode, no HPM counter will increment
at all.
|======
|=======================
 
The available hardware performance logic is configured via the _HPM_NUM_CNTS_ top entity generic.
_HPM_NUM_CNTS_ defines the number of implemented performance monitors and thus, the availability of the
708,7 → 720,7
 
[cols="4,27,>7"]
[frame="topbot",grid="none"]
|======
|=======================
| 0xb03 - 0xb1f | **Machine hardware performance monitor - counter low** | `mhpmcounter3` - `mhpmcounter31`
| 0xb83 - 0xb9f | **Machine hardware performance monitor - counter high** | `mhpmcounter3h` - `mhpmcounter31h`
3+| Reset value: _UNDEFINED_
715,7 → 727,7
3+| The `mhpmcounter*[h]` CSRs are compatible to the RISC-V specifications. These CSRs provide the lower/upper 32-
bit of arbitrary event counters. The event(s) that trigger an increment of theses counters are selected via the according
`mhpmevent*` CSRs bits.
|======
|=======================
 
 
<<<
728,7 → 740,7
 
[cols="4,27,>7"]
[frame="topbot",grid="none"]
|======
|=======================
| 0x320 | **Machine counter-inhibit register** | `mcountinhibit`
3+| Reset value: _UNDEFINED_
3+| The `mcountinhibit` CSR is compatible to the RISC-V specifications. The bits in this register define which
735,7 → 747,7
counter/timer CSR are allowed to perform an automatic increment. Automatic update is enabled if the
according bit in `mcountinhibit` is cleared. The following bits are implemented (all remaining bits are
always zero and are read-only).
|======
|=======================
 
.Machine counter-inhibit register
[cols="^1,<3,^1,<5"]
761,11 → 773,11
 
[cols="4,27,>7"]
[frame="topbot",grid="none"]
|======
|=======================
| 0xf11 | **Machine vendor ID** | `mvendorid`
3+| Reset value: _0x00000000_
3+| The `mvendorid` CSR is compatible to the RISC-V specifications. It is read-only and always reads zero.
|======
|=======================
 
 
:sectnums!:
773,12 → 785,12
 
[cols="4,27,>7"]
[frame="topbot",grid="none"]
|======
|=======================
| 0xf12 | **Machine architecture ID** | `marchid`
3+| Reset value: _0x00000013_
3+| The `marchid` CSR is compatible to the RISC-V specifications. It is read-only and shows the NEORV32
official _RISC-V open-source architecture ID_ (decimal: 19, 32-bit hexadecimal: 0x00000013).
|======
|=======================
 
 
:sectnums!:
786,12 → 798,12
 
[cols="4,27,>7"]
[frame="topbot",grid="none"]
|======
|=======================
| 0xf13 | **Machine implementation ID** | `mimpid`
3+| Reset value: _HW version number_
3+| Reset value: _defined_
3+| The `mimpid` CSR is compatible to the RISC-V specifications. It is read-only and shows the version of the
NEORV32 as BCD-coded number (example: `mimpid` = _0x01020312_ → 01.02.03.12 → version 1.2.3.12).
|======
|=======================
 
 
:sectnums!:
799,12 → 811,12
 
[cols="4,27,>7"]
[frame="topbot",grid="none"]
|======
|=======================
| 0xf14 | **Machine hardware thread ID** | `mhartid`
3+| Reset value: _HW_THREAD_ID_ generic
3+| Reset value: _defined_
3+| The `mhartid` CSR is compatible to the RISC-V specifications. It is read-only and shows the core's hart ID,
which is assigned via the CPU's _HW_THREAD_ID_ generic.
|======
|=======================
 
 
:sectnums!:
812,10 → 824,54
 
[cols="4,27,>7"]
[frame="topbot",grid="none"]
|======
|=======================
| 0xf15 | **Machine configuration pointer register** | `mconfigptr`
3+| Reset value: `0x00000000`
3+| Reset value: _0x00000000_
3+| This register holds a physical address (if not zero) that points to the base address of an architecture configuration structure.
Software can traverse this data structure to discover information about the harts, the platform, and their configuration.
**NOTE: Not assigned yet.**
|======
|=======================
 
 
<<<
// ####################################################################################################################
:sectnums:
==== NEORV32-Specific CSRs
 
[NOTE]
All NEORV32-specific CSRs are mapped to addresses that are explicitly reserved for custom **Machine-Mode, read-only** CSRs
(assured by the RISC-V privileged specifications). Hence, these CSRs can only be accessed when in machine-mode. Any access
outside of machine-mode will raise an illegal instruction exception.
 
:sectnums!:
===== **`mxisa`**
 
[cols="4,27,>7"]
[frame="topbot",grid="none"]
|=======================
| 0x7c0 | **Machine EXTENDED ISA and Extensions register** | `mxisa`
3+| Reset value: _defined_
3+| NEORV32-specific read-only CSR that helps machine-mode software to discover `Z*` sub-extensions and CPU options.
|=======================
 
 
.Machine _EXTENDED_ ISA and Extensions register bits
[cols="^1,<3,^1,<5"]
[options="header",grid="rows"]
|=======================
| Bit | Name [C] | R/W | Function
| 31 | _CSR_MXISA_FASTSHIFT_ | r/- | fast shifts available when set (via top's <<_fast_shift_en>> generic)
| 30 | _CSR_MXISA_FASTMUL_ | r/- | fast multiplication available when set (via top's <<_fast_mul_en>> generic)
| 31:11 | - | r/- | _reserved_, read as zero
| 10 | _CSR_MXISA_DEBUGMODE_ | r/- | RISC-V CPU `debug_mode` available when set (via top's <<_on_chip_debugger_en>> generic)
| 9 | _CSR_MXISA_ZIHPM_ | r/- | `Zihpm` (hardware performance monitors) extension available when set (via top's <<_cpu_extension_riscv_zihpm>> generic)
| 8 | _CSR_MXISA_PMP_ | r/- | PMP` (physical memory protection) extension available when set (via top's <<_pmp_num_regions>> generic)
| 7 | _CSR_MXISA_ZICNTR_ | r/- | `Zicntr` extension (`I` sub-extension) available when set - `[m]cycle`, `[m]instret` and `[m]time` CSRs available when set (via top's <<_cpu_extension_riscv_zicntr>> generic)
| 6 | _CSR_MXISA_ZXSCNT_ | r/- | Custom extension - _Small_ CPU counters: `[m]cycle` & `[m]instret` CSRs have less than 64-bit when set (via top's <<_cpu_cnt_width>> generic)
| 5 | _CSR_MXISA_ZFINX_ | r/- | `Zfinx` extension (`F` sub-/alternative-extension: FPU using `x` registers) available when set (via top's <<_cpu_extension_riscv_zfinx>> generic)
| 4 | - | r/- | _reserved_, read as zero
| 3 | _CSR_MXISA_ZXCFU_ | r/- | `Zxcfu` extension (custom functions unit for custom RISC-V instructions) available when set (via top's <<_cpu_extension_riscv_zxcfu>> generic)
| 2 | _CSR_MXISA_ZMMUL_ | r/- | `Zmmul` extension (`M` sub-extension) available when set (via top's <<_cpu_extension_riscv_zmmul>> generic)
| 1 | _CSR_MXISA_ZIFENCEI_ | r/- | `Zifencei` extension (`I` sub-extension) available when set (via top's <<_cpu_extension_riscv_zifencei>> generic)
| 0 | _CSR_MXISA_ZICSR_ | r/- | `Zicsr` extension (`I` sub-extension) available when set (via top's <<_cpu_extension_riscv_zicsr>> generic)
|=======================
/neorv32/trunk/docs/datasheet/index.adoc
13,7 → 13,7
 
[.text-center]
https://github.com/stnolting/neorv32[image:https://img.shields.io/badge/GitHub-stnolting%2Fneorv32-ffbd00?style=flat-square&logo=github&[title='homepage']]
https://github.com/stnolting/neorv32/blob/master/LICENSE[image:https://img.shields.io/github/license/stnolting/neorv32?longCache=true&style=flat-square[title='license']]
https://github.com/stnolting/neorv32/blob/main/LICENSE[image:https://img.shields.io/github/license/stnolting/neorv32?longCache=true&style=flat-square[title='license']]
https://gitter.im/neorv32/community[image:https://img.shields.io/badge/Chat-on%20gitter-4db797.svg?longCache=true&style=flat-square&logo=gitter&logoColor=e8ecef[title='chat on gitter']]
https://github.com/stnolting/neorv32/releases/tag/nightly[image:https://img.shields.io/badge/data%20sheet-PDF-ffbd00?longCache=true&style=flat-square&logo=asciidoctor[title='datasheet (pdf)']]
https://github.com/stnolting/neorv32/releases/tag/nightly[image:https://img.shields.io/badge/user%20guide-PDF-ffbd00?longCache=true&style=flat-square&logo=asciidoctor[title='userguide (pdf)']]
/neorv32/trunk/docs/datasheet/on_chip_debugger.adoc
3,38 → 3,33
== On-Chip Debugger (OCD)
 
The NEORV32 Processor features an _on-chip debugger_ (OCD) implementing **execution-based debugging** that is compatible
to the **Minimal RISC-V Debug Specification Version 0.13.2**.
Please refer to this spec for in-deep information.
to the **Minimal RISC-V Debug Specification Version 0.13.2**. Please refer to this spec for in-deep information.
A copy of the specification is available in `docs/references/riscv-debug-release.pdf`.
 
The NEORV32 OCD provides the following key features:
 
* JTAG test access port
* JTAG access port
* run-control of the CPU: halting, single-stepping and resuming
* executing arbitrary programs during debugging
* accessing core registers (direct access to GPRs, indirect access to CSRs via program buffer)
* indirect access to the whole processor address space (via program buffer))
* compatible to the https://github.com/riscv/riscv-openocd[RISC-V port of OpenOCD];
pre-built binaries can be obtained for example from https://www.sifive.com/software[SiFive]
* accessing core registers
* indirect access to the whole processor address space (via program buffer)
* trigger module for hardware breakpoints
* compatible with upstream OpenOCD
 
.OCD Security Note
[IMPORTANT]
[NOTE]
Access via the OCD is _always authenticated_ (`dmstatus.authenticated` == `1`). Hence, the
_whole system_ can always be accessed via the on-chip debugger. Currently, there is no option
to disable the OCD via software. The OCD can only be disabled by disabling implementation
(setting _ON_CHIP_DEBUGGER_EN_ generic to _false_).
 
[NOTE]
The OCD requires additional resources for implementation and _might_ also increase the critical path resulting in less
performance. If the OCD is not really required for the _final_ implementation, it can be disabled and thus,
discarded from implementation. In this case all circuitry of the debugger is completely removed (no impact
on area, energy or timing at all).
 
.Hands-On Tutorial
[TIP]
A simple example on how to use NEORV32 on-chip debugger in combination with `OpenOCD` and `gdb`
A simple example on how to use NEORV32 on-chip debugger in combination with OpenOCD and the GNU debugger
is shown in section https://stnolting.github.io/neorv32/ug/#_debugging_using_the_on_chip_debugger[Debugging using the On-Chip Debugger]
of the User Guide.
 
The NEORV32 on-chip debugger complex is based on three hardware modules:
The NEORV32 on-chip debugger complex is based on four hardware modules:
 
.NEORV32 on-chip debugger complex
image::neorv32_ocd_complex.png[align=center]
51,6 → 46,8
. CPU <<_cpu_debug_mode>> extension (part of`rtl/core/neorv32_cpu_control.vhd`):
This extension provides the "debug execution mode" which executes the "park loop" code from the DM.
The mode also provides additional CSRs.
. (CPU <<_trigger_module>> (also part of`rtl/core/neorv32_cpu_control.vhd`):
This module provides a single _hardware_ breakpoint, which allows to debug code executed from ROM.)
 
**Theory of Operation**
 
306,7 → 303,7
| 23:20 | `nscratch` | `0001`, number of `dscratch*` CPU registers = 1
| 19:17 | _reserved_ | reserved; always zero
| 16 | `dataccess` | `0`, the `data` registers are shadowed in the hart's address space
| 15:12 | `datasize` | `0001`, number of 32-bit words in the address space dedicated to shadowing the `data` registers = 1
| 15:12 | `datasize` | `0001`, number of 32-bit words in the address space dedicated to shadowing the `data` registers (1 register)
| 11:0 | `dataaddr` | = `dm_data_base_c(11:0)`, signed base address of `data` words (see address map in <<_dm_cpu_access>>)
|=======================
 
363,7 → 360,7
hart's GPRs (abstract command register index `0x1000` - `0x101f`).
 
.`command` - abstract command register - "access register" commands only
[cols="^1,^2,<8"]
[cols="^1,^2,^1,<8"]
[options="header",grid="rows"]
|=======================
| Bit | Name [RISC-V] | R/W | Description / required value
373,7 → 370,7
| 21 | `aarpostincrement` | -/w | `0`, post-increment is not supported
| 18 | `postexec` | -/w | if set the program buffer is executed _after_ the command
| 17 | `transfer` | -/w | if set the operation in `write` is conducted
| 16 | `write` | -/w | `1`: copy `data0` to `[regno]`; `0` copy `[regno]` to `data0`
| 16 | `write` | -/w | `1`: copy `data0` to `[regno]`, `0`: copy `[regno]` to `data0`
| 15:0 | `regno` | -/w | GPR-access only; has to be `0x1000` - `0x101f`
|=======================
 
409,7 → 406,7
| 0x20 | **Program buffer 0** | `progbuf0`
| 0x21 | **Program buffer 1** | `progbuf1`
3+| Reset value: `NOP`-instruction
3+| General purpose program buffer for the DM.
3+| General purpose program buffer (two entries) for the DM.
|======
 
 
502,65 → 499,59
:sectnums:
=== CPU Debug Mode
 
The NEORV32 CPU Debug Mode `DB` (part of `rtl/core/neorv32_cpu_control.vhd`) is compatible to the "Minimal RISC-V Debug Specification 0.13.2".
The NEORV32 CPU Debug Mode `DB` or `DEBUG` (part of `rtl/core/neorv32_cpu_control.vhd`) is compatible to the
"Minimal RISC-V Debug Specification 0.13.2".
It is enabled/implemented by setting the CPU generic _CPU_EXTENSION_RISCV_DEBUG_ to "true" (done by setting processor
generic _ON_CHIP_DEBUGGER_EN_).
It provides a new operation mode called "debug mode".
When enabled, three additional CSRs are available (section <<_cpu_debug_mode_csrs>>) and also the "return from debug mode"
instruction `dret` is available when the CPU is "in" debug mode.
It provides a new operation mode called "debug mode". When enabled, three additional CSRs are available
(section <<_cpu_debug_mode_csrs>>) and the "return from debug mode" instruction `dret` are available.
 
[IMPORTANT]
The CPU _debug mode_ requires the `Zicsr` and `Zifencei` CPU extension to be implemented (top generics _CPU_EXTENSION_RISCV_Zicsr_
and _CPU_EXTENSION_RISCV_Zifencei_ = true).
 
.Hardware Watchpoints and Breakpoints
[NOTE]
The NEORV32 CPU _debug mode_ does not provide a hardware "trigger module" (which is optional in the RISC-V debug spec). However, gdb
provides a native _emulation_ for code (breakpoints using `break` instruction) and data (polling data watchpoints in automated
single-stepping) triggers.
 
The CPU debug-mode is entered when one of the following events appear:
 
[start=1]
. executing `ebreak` instruction (when `dcsr.ebreakm` is set and in machine mode OR when `dcsr.ebreaku` is set and in user mode)
. executing the `ebreak` instruction (when in machine-mode and `dcsr.ebreakm` is set OR when in user-mode and `dcsr.ebreaku` is set)
. debug halt request from external DM (via CPU signal `db_halt_req_i`, high-active, triggering on rising-edge)
. finished executing of a single instruction while in single-step debugging mode (enabled via `dcsr.step`)
. hardware trigger by the <<_trigger_module>>
 
From a hardware point of view, these "entry conditions" are special synchronous (`ebreak` instruction) or asynchronous
(single-stepping "interrupt"; halt request "interrupt") traps, that are handled invisibly by the control logic.
From a hardware point of view, these "entry conditions" are special synchronous (e.g. `ebreak` instruction) and asynchronous
(e.g. halt request "interrupt") traps, that are handled invisibly by the control logic.
 
.WFI instruction
[WARNING]
The wait-for-interrupt instruction `wfi` puts the CPU into sleep mode. The CPU will resume normale operation
when at least one interrupt source becomes pending (= at least one bit in `mip` CSR is set).
However, the CPU will _also resume_ from sleep mode if there is a halt request from the debug module (DM).
**Whenever the CPU enters debug-mode it performs the following operations:**
 
Whenever the CPU **enters debug-mode** it performs the following operations:
 
* move `pc` to `dpcs`
* wake-up CPU if it was send to sleep mode by the `wfi` instruction
* move `pc` to `dpc`
* copy the hart's current privilege level to `dcsr.prv`
* set `dcrs.cause` according to the cause why debug mode is entered
* **no update** of `mtval`, `mcause`, `mtval` and `mstatus` CSRs
* load the address configured via the CPU _CPU_DEBUG_ADDR_ generic to the `pc` to jump to "debugger park loop" code in the debug module (DM)
* load the address configured via the CPU's _CPU_DEBUG_ADDR_ generic to the `pc` to jump to the "debugger park loop" code stored in the debug module (DM)
 
When the CPU **is in debug-mode** the following things are important:
**When the CPU is in debug-mode the following things are important:**
 
* while in debug mode, the CPU executes the parking loop and the program buffer provided by the DM if requested
* effective CPU privilege level is `machine` mode, any PMP configuration is bypassed
* effective CPU privilege level is `machine` mode, any active physical memory protection (PMP) configuration is bypassed
* the `wfi` instruction acts as a `nop` (also during single-stepping)
* if an exception occurs:
** if the exception was caused by any debug-mode entry action the CPU jumps to the _normal entry point_
(= _CPU_DEBUG_ADDR_) of the park loop again (for example when executing `ebreak` _in_ debug-mode)
** for all other exception sources the CPU jumps to the _exception entry point_ ( = _CPU_DEBUG_ADDR_ + 4)
to signal an exception to the DM and restarts the park loop again afterwards
to signal an exception to the DM; the CPU restarts the park loop again afterwards
* interrupts are disabled; however, they will remain pending and will get executed after the CPU has left debug mode
* if the DM makes a resume request, the park loop exits and the CPU leaves debug mode (executing `dret`)
* the standard counters <<_machine_counter_and_timer_csrs>> `[m]cycle[h]` and `[m]instret[h]` are stopped; note that the
<<_machine_system_timer_mtime>> keep running as well as it's shadowed copies in the `[m]time[h]` CSRs
* all <<_hardware_performance_monitors_hpm_csrs>> are stopped
 
Debug mode is left either by executing the `dret` instruction footnote:[`dret` should only be executed _inside_ the debugger
"park loop" code (-> code ROM in the debug module (DM).)] (_in_ debug mode) or by performing
a hardware reset of the CPU. Executing `dret` outside of debug mode will raise an illegal instruction exception.
Whenever the CPU **leaves debug mode** the following things happen:
 
**Whenever the CPU leaves debug mode it performs the following operations:**
 
* set the hart's current privilege level according to `dcsr.prv`
* restore `pc` from `dpcs`
* resume normal operation at `pc`
587,34 → 578,41
[frame="topbot",grid="none"]
|======
| 0x7b0 | **Debug control and status register** | `dcsr`
3+| Reset value: 0x00000000
3+| Reset value: 0x40000000
3+| The `dcsr` CSR is compatible to the RISC-V debug spec. It is used to configure debug mode and provides additional status information.
The following bits are implemented. The reaming bits are read-only and always read as zero.
|======
 
.Debug control and status register bits
.Debug control and status register `dcsr` bits
[cols="^1,^2,^1,<8"]
[options="header",grid="rows"]
|=======================
| Bit | Name [RISC-V] | R/W | Event
| 31:28 | `xdebugver` | r/- | always `0100` - indicates external debug support exists
| 27:16 | - | r/- | _reserved_, read as zero
| 15 | `ebereakm` | r/w | `ebreak` instructions in `machine` mode will _enter_ debug mode when set
| 14 | [line-through]#`ebereakh`# | r/- | `0` - hypervisor mode not supported
| 13 | [line-through]#`ebereaks`# | r/- | `0` - supervisor mode not supported
| 12 | `ebereaku` | r/w | `ebreak` instructions in `user` mode will _enter_ debug mode when set
| 11 | [line-through]#`stepie`# | r/- | `0` - IRQs are disabled during single-stepping
| 10 | [line-through]#`stopcount`# | r/- | `0` - counters increment as usual
| 9 | [line-through]#`stoptime`# | r/- | `0` - timers increment as usual
| 8:6 | `cause` | r/- | cause identifier - why debug mode was entered
| 5 | - | r/- | _reserved_, read as zero
| 4 | [line-through]#`mprven`# | r/- | `0` - `mstatus.mprv` is ignored when in debug mode
| 3 | [line-through]#`nmip`# | r/- | `0` - non-maskable interrupt is pending
| 2 | `step` | r/w | enable single-stepping when set
| 1:0 | `prv` | r/w | CPU privilege level before/after debug mode
| Bit | Name [RISC-V] | R/W | Description
| 31:28 | `xdebugver` | r/- | `0100` - indicates external debug support exists
| 27:16 | - | r/- | `000000000000` - _reserved_
| 15 | `ebereakm` | r/w | `ebreak` instructions in `machine` mode will _enter_ debug mode when set
| 14 | `ebereakh` | r/- | `0` - hypervisor mode not supported
| 13 | `ebereaks` | r/- | `0` - supervisor mode not supported
| 12 | `ebereaku` | r/w | `ebreak` instructions in `user` mode will _enter_ debug mode when set
| 11 | `stepie` | r/- | `0` - IRQs are disabled during single-stepping
| 10 | `stopcount` | r/- | `1` - standard counters and HPMs are stopped when in debug mode
| 9 | `stoptime` | r/- | `0` - timers increment as usual
| 8:6 | `cause` | r/- | cause identifier - why debug mode was entered (see below)
| 5 | - | r/- | `0` - _reserved_
| 4 | `mprven` | r/- | `0` - `mstatus.mprv` is ignored when in debug mode
| 3 | `nmip` | r/- | `0` - non-maskable interrupt is pending
| 2 | `step` | r/w | enable single-stepping when set
| 1:0 | `prv` | r/w | CPU privilege level before/after debug mode
|=======================
 
Cause codes in `dcsr.cause` (highest priority first):
 
* `010` - trigger by hardware <<_trigger_module>>
* `001` - executed EBREAK instruction
* `011` - external halt request (from DM)
* `100` - return from single-stepping
 
 
:sectnums!:
===== **`dpc`**
 
640,3 → 638,152
|======
 
 
<<<
// ####################################################################################################################
:sectnums:
=== Trigger Module
 
The NEORV32 trigger module implements a subset of the features described in the "RISC-V Debug Specification / Trigger Module".
It is always implemented when the CPU debug mode / the on-chip debugger is implemented.
 
[IMPORTANT]
The trigger module only provides a single trigger of _instruction address match_ type. This trigger will fire
**after** the instruction at the specific address has been executed.
 
The trigger module only provides a single trigger supporting only the "instruction address match" type. This limitation
is granted by the RISC-V specs. and is sufficient to **debug code executed from read-only memory (ROM)**.
"Normal" _software_ breakpoints (using gdb's `b`/`break` command) are implemented by temporarily replacing the according
instruction word by a BREAK instruction. This is not possible when debugging code that is executed from read-only memory
(for example when debugging programs that are executed via the <<_execute_in_place_module_xip>>).
Therefore, the NEORV32 trigger module provides a single "instruction address match" trigger to enter debug mode when
executing the instruction at a specific address. These "hardware-assisted breakpoints" are used by gdb's `hb`/`hbreak` command.
 
 
:sectnums:
==== Trigger Module CSRs
 
The trigger module provides 8 additional CSRs, which accessible in debug mode and also in machine-mode. Since the
trigger module does not support _native mode_ writes from machine-mode software to those CSRs are ignored.
Hence, the CSRs of this module are only relevant for the debugger.
 
 
:sectnums!:
===== **`tselect`**
 
[cols="4,27,>7"]
[frame="topbot",grid="none"]
|======
| 0x7a0 | **Trigger select register** | `tselect`
3+| Reset value: 0x00000000
3+| This CSR is hardwired to zero indicating there is only one trigger available. Any write access is ignored.
|======
 
 
:sectnums!:
===== **`tdata1`**
 
[cols="4,27,>7"]
[frame="topbot",grid="none"]
|======
| 0x7a1 | **Trigger data register 1 / match control register** | `tdata1` / `mcontrol`
3+| Reset value: 0x28041048
3+| This CSR is used to configure the address match trigger. Only one bit is writable, the remaining bits are hardwired (see table below).
Write attempts to the hardwired bits are ignored.
|======
 
.Match control CSR (`tdata1`) bits
[cols="^1,^2,^1,<8"]
[options="header",grid="rows"]
|=======================
| Bit | Name [RISC-V] | R/W | Description
| 31:28 | `type` | r/- | `0010` - address match trigger
| 27 | `dmode` | r/- | `1` - only debug-mode can write to the `tdata*` CSRs
| 26:21 | `maskmax` | r/- | `000000` - only exact values
| 20 | `hit` | r/- | `0` - feature not supported
| 19 | `select` | r/- | `0` - fire trigger on address match
| 18 | `timing` | r/- | `1` - trigger **after** executing the triggering instruction
| 17:16 | `sizelo` | r/- | `00` - match against an access of any size
| 15:12 | `action` | r/- | `0001` - enter debug mode on trigger fire
| 11 | `chain` | r/- | `0` - chaining is not supported - there is only one trigger
| 10:6 | `match` | r/- | `0000` - only full-address match
| 6 | `m` | r/- | `1` - trigger enabled when in machine-mode
| 5 | `h` | r/- | `0` - hypervisor-mode not supported
| 4 | `s` | r/- | `0` - supervisor-mode not supported
| 3 | `u` | r/- | trigger enabled when in user-mode, set when `U` ISA extension is enabled
| 2 | `exe` | r/w | set to enable trigger
| 1 | `store` | r/- | `0` - store address/data matching not supported
| 0 | `load` | r/- | `0` - load address/data matching not supported
|=======================
 
 
:sectnums!:
===== **`tdata2`**
 
[cols="4,27,>7"]
[frame="topbot",grid="none"]
|======
| 0x7a2 | **Trigger data register 2** | `tdata2`
3+| Reset value: _UNDEFINED_
3+| Since only the "address match trigger" type is supported, this r/w CSR is used to store the address of the triggering instruction.
|======
 
 
:sectnums!:
===== **`tdata3`**
 
[cols="4,27,>7"]
[frame="topbot",grid="none"]
|======
| 0x7a3 | **Trigger data register 3** | `tdata3`
3+| Reset value: 0x00000000
3+| This CSR is not required for the NEORV32 trigger module. Hence, it is hardwired to zero and any write access is ignored.
|======
 
 
:sectnums!:
===== **`tinfo`**
 
[cols="4,27,>7"]
[frame="topbot",grid="none"]
|======
| 0x7a4 | **Trigger information register** | `tinfo`
3+| Reset value: 0x00000004
3+| This CSR is hardwired to "4" indicating there is only an "address match trigger" available. Any write access is ignored.
|======
 
 
:sectnums!:
===== **`tcontrol`**
 
[cols="4,27,>7"]
[frame="topbot",grid="none"]
|======
| 0x7a5 | **Trigger control register** | `tcontrol`
3+| Reset value: 0x00000000
3+| This CSR is not required for the NEORV32 trigger module. Hence, it is hardwired to zero and any write access is ignored.
|======
 
 
:sectnums!:
===== **`mcontext`**
 
[cols="4,27,>7"]
[frame="topbot",grid="none"]
|======
| 0x7a8 | **Machine context register** | `mcontext`
3+| Reset value: 0x00000000
3+| This CSR is not required for the NEORV32 trigger module. Hence, it is hardwired to zero and any write access is ignored.
|======
 
 
:sectnums!:
===== **`scontext`**
 
[cols="4,27,>7"]
[frame="topbot",grid="none"]
|======
| 0x7aa | **Supervisor context register** | `scontext`
3+| Reset value: 0x00000000
3+| This CSR is not required for the NEORV32 trigger module. Hence, it is hardwired to zero and any write access is ignored.
|======
 
/neorv32/trunk/docs/datasheet/overview.adoc
22,7 → 22,7
[TIP]
Check out the processor's **https://stnolting.github.io/neorv32/ug[online User Guide]**
that provides hands-on tutorials to get you started.
The project's change log is available in https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md[CHANGELOG.md]
The project's change log is available in https://github.com/stnolting/neorv32/blob/main/CHANGELOG.md[CHANGELOG.md]
in the root directory of the NEORV32 repository. Please also check out the <<_legal>> section.
 
 
54,6 → 54,7
* **NEORV32 CPU**: 32-bit `rv32i` RISC-V CPU
** RISC-V compatibility: passes the official architecture tests
** base architecture + privileged architecture (optional) + ISA extensions (optional)
** option to add custom RISC-V instructions (as custom ISA extension)
** rich set of customization options (ISA extensions, design goal: performance / area (/ energy), ...)
** aims to support <<_full_virtualization>> capabilities (CPU _and_ SoC) to increase execution safety
** official https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md[RISC-V open source architecture ID]
65,7 → 66,7
** optional embedded memories / caches for data, instructions and bootloader
** optional external memory interface (Wishbone / AXI4-Lite) and stream link interface (AXI4-Stream) for custom connectivity
** optional execute in place (XIP) module
** on-chip debugger compatible with OpenOCD and gdb
** on-chip debugger compatible with OpenOCD and gdb including hardware trigger module
* **Software framework**
** GCC-based toolchain - prebuilt toolchains available; application compilation based on GNU makefiles
** internal bootloader with serial user interface
78,7 → 79,22
For more in-depth details regarding the feature provided by he hardware see the according sections:
<<_neorv32_central_processing_unit_cpu>> and <<_neorv32_processor_soc>>.
 
**Extensibility and Customization**
 
The NEORV32 processor was designed to ease customization and extensibility and provides several options for adding
application-specific custom hardware modules and accelerators. The three most common options for adding custom
on-chip modules are listed below.
 
* <<_processor_external_memory_interface_wishbone_axi4_lite>> for processor-external modules
* <<_custom_functions_subsystem_cfs>> for tightly-coupled processor-internal co-processors
* <<_custom_functions_unit_cfu>> for custom RISC-V instructions
 
[TIP]
A more detailed comparison of the extension/customization options can be found in section
https://stnolting.github.io/neorv32/ug/#_adding_custom_hardware_modules[Adding Custom Hardware Modules]
of the user guide.
 
 
<<<
// ####################################################################################################################
:sectnums:
143,6 → 159,7
├neorv32_cpu.vhd - NEORV32 CPU top entity
│├neorv32_cpu_alu.vhd - Arithmetic/logic unit
││├neorv32_cpu_cp_bitmanip.vhd - Bit-manipulation co-processor (B ext.)
││├neorv32_cpu_cp_cfu.vhd - Custom functions (instruction) co-processor (Zxcfu ext.)
││├neorv32_cpu_cp_fpu.vhd - Floating-point co-processor (Zfinx ext.)
││├neorv32_cpu_cp_muldiv.vhd - Mul/Div co-processor (M extension)
││└neorv32_cpu_cp_shifter.vhd - Bit-shift co-processor
/neorv32/trunk/docs/datasheet/rationale.adoc
31,6 → 31,8
 
**Why RISC-V?**
 
image::riscv_logo.png[width=250,align=left]
 
[quote, RISC-V International, https://riscv.org/about/]
____
RISC-V is a free and open ISA enabling a new era of processor innovation through open standard collaboration.
60,7 → 62,7
 
The project aims to provide _another option_ in the RISC-V / soft-core design space with a different performance
vs. size trade-off and a different focus: _embrace_ concepts like documentation, platform-independence / portability,
RISC-V compatibility, _customization_ and _ease of use_ (see the <<_project_key_features>> below).
RISC-V compatibility, _ extensibility & customization_ and _ease of use_ (see the <<_project_key_features>> below).
 
Furthermore, the NEORV32 pays special focus on _execution safety_ using <<_full_virtualization>>. The CPU aims to
provide fall-backs for _everything that could go wrong_. This includes malformed instruction words, privilege escalations
/neorv32/trunk/docs/datasheet/soc.adoc
41,7 → 41,7
The type of all signals is `std_ulogic` or `std_ulogic_vector`, respectively.
 
.Default Values of Ports
[IMPORTANT]
[NOTE]
All _input signals_ provide default values in case they are not explicitly assigned during instantiation.
For control signals the value `L` (weak pull-down) is used. For serial and parallel data signals
the value `U` (unknown) is used. Pulled-down signals will not cause "accidental" system crashes
48,7 → 48,7
since all control signals have defined level.
 
.Configurable Amount of Channels
[IMPORTANT]
[NOTE]
Some peripherals allow to configure the number of channels to-be-implemented by a generic (for example the number
of PWM or SLINK channels). The according input/output signals have a fixed sized regardless of the actually configured
amount of channels. If less than the maximum number of channels is configured, only the LSB-aligned channels are used:
63,10 → 63,10
| `clk_i` | 1 | in | global clock line, all registers triggering on rising edge
| `rstn_i` | 1 | in | global reset, asynchronous, **low-active**
4+^| **JTAG Access Port for <<_on_chip_debugger_ocd>>**
| `jtag_trst_i` | 1 | in | TAP reset, low-active (optionalfootnote:[Pull high if not used.])
| `jtag_trst_i` | 1 | in | TAP reset, low-active (optional footnote:[Pull high if not used.])
| `jtag_tck_i` | 1 | in | serial clock
| `jtag_tdi_i` | 1 | in | serial data input
| `jtag_tdo_o` | 1 | out | serial data outputfootnote:[If the on-chip debugger is not implemented (_ON_CHIP_DEBUGGER_EN_ = false) `jtag_tdi_i` is directly forwarded to `jtag_tdo_o` to maintain the JTAG chain.]
| `jtag_tdo_o` | 1 | out | serial data output footnote:[If the on-chip debugger is not implemented (_ON_CHIP_DEBUGGER_EN_ = false) `jtag_tdi_i` is directly forwarded to `jtag_tdo_o` to maintain the JTAG chain.]
| `jtag_tms_i` | 1 | in | mode select
4+^| **External Bus Interface (<<_processor_external_memory_interface_wishbone_axi4_lite,WISHBONE>>)**
| `wb_tag_o` | 3 | out | tag (access type identifier)
148,12 → 148,13
The NEORV32 generics allow to configure the system according to your needs. The generics are
used to control implementation of certain CPU extensions and peripheral modules and even allow to
optimize the system for certain design goals like minimal area or maximum performance. +
**More information can be found in the user guides' section
https://stnolting.github.io/neorv32/ug/#_application_specific_processor_configuration[Application-Specific Processor Configuration]**.
+
More information can be found in the user guides' section
https://stnolting.github.io/neorv32/ug/#_application_specific_processor_configuration[Application-Specific Processor Configuration].
 
[TIP]
Privileged software can determine the actual CPU and processor configuration via the `misa` and the
<<_system_configuration_information_memory_sysinfo, SYSINFO>> registers.
Privileged software can determine the actual CPU and processor configuration via the <<_misa>> and <<_mxisa>> CSRs (CPU)
and the <<_system_configuration_information_memory_sysinfo, SYSINFO>> (processor) memory-mapped registers.
 
[TIP]
Run a quick simulation using the provided simulation/GHDL scripts (https://stnolting.github.io/neorv32/ug/#_hello_world)
219,7 → 220,7
[frame="all",grid="none"]
|======
| **HW_THREAD_ID** | _natural_ | 0
3+| The hart ID of the CPU. Software can retrieve this value from the `mhartid` CSR.
3+| The hart ID of the CPU. Software can retrieve this value from the <<_mhartid>> CSR.
Note that hart IDs must be unique within a system.
|======
 
240,10 → 241,11
:sectnums:
==== RISC-V CPU Extensions
 
.Discovering ISA Extensions
[TIP]
See section <<_instruction_sets_and_extensions>> for more information. The configuration of the RISC-V _main_ ISA extensions
(like `M`) can be determined via the <<_misa>> CSR. The configuration of ISA _sub-extensions_ (like `Zicsr`) and _extension options_
can be determined via memory-mapped registers of the <<_system_configuration_information_memory_sysinfo>> module.
(like `M`) can be determined via the <<_misa>> CSR. The configuration of ISA _sub-extensions_ (like `Zicsr`) and _tuning options_
can be determined via the NEORV32-specific <<_mxisa>> CSR.
 
 
:sectnums!:
355,8 → 357,7
[frame="all",grid="none"]
|======
| **CPU_EXTENSION_RISCV_Zicntr** | _boolean_ | true
3+| Implement the basic CPU counter CSRs (`time[h]`, `[m]cycle[h]`, `[m]instret[h]`) when true.
Enabling this extension will set the _SYSINFO_CPU_ZICNTR_ flag in the `CPU` <<_system_configuration_information_memory_sysinfo, SYSINFO>> register.
3+| Implement the basic CPU <<_machine_counter_and_timer_csrs>> (`time[h]`, `[m]cycle[h]`, `[m]instret[h]`) when true.
See section <<_zicntr_cpu_base_counters>> for more information.
|======
 
369,7 → 370,6
|======
| **CPU_EXTENSION_RISCV_Zihpm** | _boolean_ | false
3+| Implement hardware performance monitor CSRs when true.
Enabling this extension will set the _SYSINFO_CPU_ZIHPM_ flag in the `CPU` <<_system_configuration_information_memory_sysinfo, SYSINFO>> register.
See section <<_zihpm_hardware_performance_monitors>> for more information.
|======
 
399,10 → 399,23
|======
 
 
:sectnums!:
===== _CPU_EXTENSION_RISCV_Zxcfu_
 
[cols="4,4,2"]
[frame="all",grid="none"]
|======
| **CPU_EXTENSION_RISCV_Zxcfu** | _boolean_ | false
3+| NEORV32-specific "custom RISC-V" ISA extensions: Implement the <<_custom_functions_unit_cfu>> for user-defined
custom instruction when _true_. See section <<_zxcfu_custom_instructions_extension_cfu>> for more information.
|======
 
 
// ####################################################################################################################
:sectnums:
==== Extension Options
==== Tuning Options
 
These are generics to fine-tune certain ISA extensions and CPU features.
See section <<_instruction_sets_and_extensions>> for more information.
 
 
478,8 → 491,7
|======
| **PMP_NUM_REGIONS** | _natural_ | 0
3+| Total number of implemented protections regions (0..64). If this generics is zero no physical memory
protection logic will be implemented at all. Setting <<_pmp_num_regions>>_ > 0 will set the _SYSINFO_CPU_PMP_ flag
in the `CPU` <<_system_configuration_information_memory_sysinfo, SYSINFO>> register.
protection logic will be implemented at all.
|======
 
 
1089,7 → 1101,7
.Trigger type
[IMPORTANT]
The fast interrupt request channels become pending after being triggering by **a rising edge**. A pending FIRQ has to
be explicitly cleared by setting the according `mip` CSR bit.
be explicitly cleared by setting the according <<_mip>> CSR bit.
 
 
:sectnums:
1148,7 → 1160,7
.Trigger type
[IMPORTANT]
The fast interrupt request channels become pending after being triggering by **a rising edge**. A pending FIRQ has to
be explicitly cleared by setting the according `mip` CSR bit.
be explicitly cleared by setting the according <<_mip>> CSR bit.
 
 
 
1172,7 → 1184,12
.NEORV32 processor - address space (default configuration)
image::address_space.png[900]
 
.RAM Layout - Usage of the Data Address Space
[TIP]
The actual usage of the data address space by the software/executables (stack, heap, ...) is
illustrated in section <<_ram_layout>>.
 
 
:sectnums:
==== CPU Data and Instruction Access
 
/neorv32/trunk/docs/datasheet/soc_bootrom.adoc
30,6 → 30,9
determined via synthesis and expanded to the next power of two. For example, if the bootloader code requires
10kB of storage, a ROM with 16kB will be generated. The maximum size must not exceed 32kB.
 
[NOTE]
Any write access to the BOOTROM will raise a _store access fault_ exception.
 
.Bootloader - Software
[TIP]
See section <<_bootloader>> for more information regarding the actual bootloader software/executable itself.
/neorv32/trunk/docs/datasheet/soc_cfs.adoc
35,7 → 35,11
(CNNs) as well as custom IO systems like fast memory interfaces (DDR) and mass storage (SDIO), networking (CAN)
or real-time data transport (I2S).
 
[INFO]
[TIP]
If you like to implement _custom instructions_ that are executed right within the CPU's ALU
see the <<_zxcfu_custom_instructions_extension_cfu>> and the according <<_custom_functions_unit_cfu>>.
 
[TIP]
Take a look at the template CFS VHDL source file (`rtl/core/neorv32_cfs.vhd`). The file is highly
commented to illustrate all aspects that are relevant for implementing custom CFS-based co-processor designs.
 
/neorv32/trunk/docs/datasheet/soc_imem.adoc
11,7 → 11,7
| Top entity port: | none |
| Configuration generics: | _MEM_INT_IMEM_EN_ | implement processor-internal IMEM when _true_
| | _MEM_INT_IMEM_SIZE_ | IMEM size in bytes
| | _INT_BOOTLOADER_EN_ | use internal bootloader when _true_ (implements IMEM as _uninitialized_ RAM)
| | _INT_BOOTLOADER_EN_ | use internal bootloader when _true_ (implements IMEM as _uninitialized_ RAM, otherwise the IMEM is implemented an _pre-intialized_ ROM)
| CPU interrupts: | none |
|=======================
 
37,3 → 37,6
_platform independent_ memory design that (should) infers embedded memory block. You can replace/modify the architecture
source file in order to use platform-specific features (like advanced memory resources) or to improve technology mapping
and/or timing.
 
[NOTE]
If the IMEM is implemented as true ROM any write attempt to it will raise a _store access fault_ exception.
/neorv32/trunk/docs/datasheet/soc_sysinfo.adoc
32,7 → 32,7
|=======================
| Address | Name [C] | Function
| `0xffffffe0` | `NEORV32_SYSINFO.CLK` | clock speed in Hz (via top's <<_clock_frequency>> generic)
| `0xffffffe4` | `NEORV32_SYSINFO.CPU` | specific CPU configuration (see <<_sysinfo_cpu_configuration>>)
| `0xffffffe4` | - | _reserved_, read as zero
| `0xffffffe8` | `NEORV32_SYSINFO.SOC` | specific SoC configuration (see <<_sysinfo_soc_configuration>>)
| `0xffffffec` | `NEORV32_SYSINFO.CACHE` | cache configuration information (see <<_sysinfo_cache_configuration>>)
| `0xfffffff0` | `NEORV32_SYSINFO.ISPACE_BASE` | instruction address space base (via package's `ispace_base_c` constant)
42,27 → 42,6
|=======================
 
 
===== SYSINFO - CPU Configuration
 
._SYSINFO_CPU_ bits
[cols="^1,<10,<11"]
[options="header",grid="all"]
|=======================
| Bit | Name [C] | Function
| `0` | _SYSINFO_CPU_ZICSR_ | `Zicsr` extension (`I` sub-extension) available when set (via top's <<_cpu_extension_riscv_zicsr>> generic)
| `1` | _SYSINFO_CPU_ZIFENCEI_ | `Zifencei` extension (`I` sub-extension) available when set (via top's <<_cpu_extension_riscv_zifencei>> generic)
| `2` | _SYSINFO_CPU_ZMMUL_ | `Zmmul` extension (`M` sub-extension) available when set (via top's <<_cpu_extension_riscv_zmmul>> generic)
| `5` | _SYSINFO_CPU_ZFINX_ | `Zfinx` extension (`F` sub-/alternative-extension) available when set (via top's <<_cpu_extension_riscv_zfinx>> generic)
| `6` | _SYSINFO_CPU_ZXSCNT_ | Custom extension - _Small_ CPU counters: `[m]cycle` & `[m]instret` CSRs have less than 64-bit when set (via top's <<_cpu_cnt_width>> generic)
| `7` | _SYSINFO_CPU_ZXNOCNT_ | Custom extension - _NO_ CPU counters: `[m]cycle` & `[m]instret` CSRs are NOT available at all when set (via top's <<_cpu_cnt_width>> generic)
| `8` | _SYSINFO_CPU_PMP_ | `PMP` (physical memory protection) extension available when set (via top's <<_pmp_num_regions>> generic)
| `9` | _SYSINFO_CPU_HPM_ | `HPM` (hardware performance monitors) extension available when set (via top's <<_cpu_extension_riscv_zihpm>> generic)
| `10` | _SYSINFO_CPU_DEBUGMODE_ | RISC-V CPU `debug_mode` available when set (via top's <<_on_chip_debugger_en>> generic)
| `30 | _SYSINFO_CPU_FASTMUL_ | fast multiplication available when set (via top's <<_fast_mul_en>> generic)
| `31` | _SYSINFO_CPU_FASTSHIFT_ | fast shifts available when set (via top's <<_fast_shift_en>> generic)
|=======================
 
 
===== SYSINFO - SoC Configuration
 
._SYSINFO_SOC_ bits
/neorv32/trunk/docs/datasheet/soc_uart.adoc
30,10 → 30,12
The UART features two memory-mapped registers `CTRL` and `DATA`, which are used for configuration, status
check and data transfer.
 
.Standard Console(s)
[NOTE]
Please note that ALL default example programs and software libraries of the NEORV32 software
Please note that _all_ default example programs and software libraries of the NEORV32 software
framework (including the bootloader and the runtime environment) use the primary UART
(_UART0_) as default user console interface.
(_UART0_) as default user console interface. Furthermore, UART0 is used to implement all the standard
input, output and error consoles (`STDIN`, `STDOUT` and `STDERR`).
 
 
**Theory of Operation**
/neorv32/trunk/docs/datasheet/soc_xip.adoc
37,10 → 37,6
[TIP]
An example program for the XIP module is available in `sw/example/demo_xip`.
 
[WARNING]
Debugging XIP code execution using the on-chip debugger is constrained. The debugger cannot insert breakpoints
(`ebreak` instructions) into XIP code as the XIP access is read-only.
 
[NOTE]
Quad-SPI (QSPI) support, which is about 4x times faster, is planned for the future. 😉
 
120,7 → 116,15
control register bits. Any access within `0x20000000 .. 0x2fffffff` will be forwarded to the XIP flash.
Note that the SPI access address might wrap around.
 
.Using the FPGA Bitstream Flash also for XIP
[TIP]
You can also use the FPGA's bitstream SPI flash for storing XIP programs. To prevent overriding the bitstream,
a certain offset needs to be added to the executable (which might require linker script modifications).
To execute the program stored in the SPI flash simply jump to the according base address. For example
if the executable starts at flash offset `0x8000` and the XIP flash is mapped to the base address `0x20000000`
then add the offset to the base address and use that as jump/call destination (=`0x20008000`).
 
 
**Using the XIP Mode**
 
The XIP module is globally enabled by setting the _XIP_CTRL_EN_ bit in the device's `CTRL` control register.
/neorv32/trunk/docs/datasheet/software.adoc
1,23 → 1,44
:sectnums:
== Software Framework
 
To make actual use of the NEORV32 processor, the project comes with a complete software eco-system. This
To make actual use of the NEORV32 processor, the project comes with a complete software ecosystem. This
ecosystem is based on the RISC-V port of the GCC GNU Compiler Collection and consists of the following elementary parts:
 
* <<_compiler_toolchain>>
* <<_core_libraries>>
* <<_application_makefile>>
* <<_executable_image_format>>
** <<_linker_script>>
** <<_ram_layout>>
** <<_c_standard_library>>
** <<_start_up_code_crt0>>
* <<_bootloader>>
* <<_neorv32_runtime_environment>>
 
A summarizing list of the most important elements of the software framework and their according
files and folders is shown below:
 
[cols="<6,<4"]
[grid="none"]
|=======================
| Application/bootloader start-up code | `sw/common/crt0.S`
| Application/bootloader linker script | `sw/common/neorv32.ld`
| Core hardware driver libraries | `sw/lib/include/` & `sw/lib/source/`
| Central makefile | `sw/common/common.mk`
| Auxiliary tool for generating NEORV32 executables | `sw/image_gen/`
| Default bootloader | `sw/bootloader/bootloader.c`
| Application start-up code | `sw/common/crt0.S`
| Application linker script | `sw/common/neorv32.ld`
| Core hardware driver libraries ("HAL") | `sw/lib/include/` & `sw/lib/source/`
| Central application makefile | `sw/common/common.mk`
| Tool for generating NEORV32 executables | `sw/image_gen/`
| Default bootloader | `sw/bootloader/bootloader.c`
| Example programs | `sw/example`
|=======================
 
Last but not least, the NEORV32 ecosystem provides some example programs for testing the hardware, for
illustrating the usage of peripherals and for general getting in touch with the project (`sw/example`).
.Software Documentation
[TIP]
All core libraries and example programs are highly documented using **Doxygen**.
See section <<Building the Software Framework Documentation>>.
The documentation is automatically built and deployed to GitHub pages and is available online
at https://stnolting.github.io/neorv32/sw/files.html .
 
 
 
// ####################################################################################################################
:sectnums:
=== Compiler Toolchain
25,12 → 46,16
The toolchain for this project is based on the free RISC-V GCC-port. You can find the compiler sources and
build instructions on the official RISC-V GNU toolchain GitHub page: https://github.com/riscv/riscv-gnutoolchain.
 
The NEORV32 implements a 32-bit base integer architecture (`rv32i`) and a 32-bit integer and soft-float ABI
(ilp32), so make sure you build an according toolchain.
The NEORV32 implements a 32-bit RISC-V architecture and uses a 32-bit integer and soft-float ABI by default.
Make sure the toolchain / toolchain build is configured accordingly.
 
* MARCH = `rv32i`
* MABI = `ilp32`
 
Alternatively, you can download my prebuilt `rv32i/e` toolchains for 64-bit x86 Linux from: https://github.com/stnolting/riscv-gcc-prebuilt
 
The default toolchain prefix used by the project's makefiles is (can be changed in the makefiles): **`riscv32-unknown-elf`**
The default toolchain prefix used by the project's makefiles is **`riscv32-unknown-elf`**, which can be changes
using makefile flags at any time.
 
[TIP]
More information regarding the toolchain (building from scratch or downloading the prebuilt ones)
43,54 → 68,48
:sectnums:
=== Core Libraries
 
The NEORV32 project provides a set of C libraries that allows an easy usage of the processor/CPU features.
Just include the main NEORV32 library file in your application's source file(s):
The NEORV32 project provides a set of C libraries that allows an easy usage of the processor/CPU features
(also called "HAL" - hardware abstraction layer). All driver and runtime-related files are located in
`sw/lib`. These are automatically included and linked by adding the following _include statement_:
 
[source,c]
----
#include <neorv32.h>
#include <neorv32.h> // add NEORV32 HAL and runtime libraries
----
 
[TIP]
A CMSIS-SVD-compatible **System View Description (SVD)** file including all peripherals is available in `sw/svd`.
 
Together with the makefile, this will automatically include all the processor's header files located in
`sw/lib/include` into your application. The actual source files of the core libraries are located in
`sw/lib/source` and are automatically included into the source list of your software project. The following
files are currently part of the NEORV32 core library:
 
[cols="<3,<4,<8"]
[options="header",grid="rows"]
|=======================
| C source file | C header file | Description
| - | `neorv32.h` | main NEORV32 definitions and library file
| `neorv32_cfs.c` | `neorv32_cfs.h` | HW driver (stub)footnote:[This driver file only represents a stub, since the real CFS drivers are defined by the actual CFS implementation.] functions for the custom functions subsystem
| `neorv32_cpu.c` | `neorv32_cpu.h` | HW driver functions for the NEORV32 **CPU**
| `neorv32_gpio.c` | `neorv32_gpio.h` | HW driver functions for the **GPIO**
| `neorv32_gptmr.c` | `neorv32_gptmr.h` | HW driver functions for the **GPTRM**
| - | `neorv32_intrinsics.h` | macros for (custom) intrinsics/instructions
| `neorv32_mtime.c` | `neorv32_mtime.h` | HW driver functions for the **MTIME**
| `neorv32_neoled.c` | `neorv32_neoled.h` | HW driver functions for the **NEOLED**
| `neorv32_pwm.c` | `neorv32_pwm.h` | HW driver functions for the **PWM**
| `neorv32_rte.c` | `neorv32_rte.h` | NEORV32 **runtime environment** and helpers
| `neorv32_slink.c` | `neorv32_slink.h` | HW driver functions for the **SLINK**
| `neorv32_spi.c` | `neorv32_spi.h` | HW driver functions for the **SPI**
| `neorv32_trng.c` | `neorv32_trng.h` | HW driver functions for the **TRNG**
| `neorv32_twi.c` | `neorv32_twi.h` | HW driver functions for the **TWI**
| `neorv32_uart.c` | `neorv32_uart.h` | HW driver functions for the **UART0** and **UART1**
| `neorv32_wdt.c` | `neorv32_wdt.h` | HW driver functions for the **WDT**
| `neorv32_xip.c` | `neorv32_xip.h` | HW driver functions for the **XIP**
| `neorv32_xirq.c` | `neorv32_xirq.h` | HW driver functions for the **XIRQ**
| - | `neorv32.h` | main NEORV32 definitions and library file
| `neorv32_cfs.c` | `neorv32_cfs.h` | HW driver (stubs) functions for the custom functions subsystem
footnote:[This driver file only represents a stub, since the real CFS drivers are defined by the actual CFS implementation.]
| `neorv32_cpu.c` | `neorv32_cpu.h` | HW driver functions for the NEORV32 **CPU**
| `neorv32_cpu_cfu.c` | `neorv32_cpu_cfu.h` | HW driver functions for the NEORV32 **CFU** (custom instructions)
| `neorv32_gpio.c` | `neorv32_gpio.h` | HW driver functions for the **GPIO**
| `neorv32_gptmr.c` | `neorv32_gptmr.h` | HW driver functions for the **GPTRM**
| - | `neorv32_intrinsics.h` | macros for custom intrinsics & instructions
| `neorv32_mtime.c` | `neorv32_mtime.h` | HW driver functions for the **MTIME**
| `neorv32_neoled.c` | `neorv32_neoled.h` | HW driver functions for the **NEOLED**
| `neorv32_pwm.c` | `neorv32_pwm.h` | HW driver functions for the **PWM**
| `neorv32_rte.c` | `neorv32_rte.h` | NEORV32 **runtime environment** and helper functions
| `neorv32_slink.c` | `neorv32_slink.h` | HW driver functions for the **SLINK**
| `neorv32_spi.c` | `neorv32_spi.h` | HW driver functions for the **SPI**
| `neorv32_trng.c` | `neorv32_trng.h` | HW driver functions for the **TRNG**
| `neorv32_twi.c` | `neorv32_twi.h` | HW driver functions for the **TWI**
| `neorv32_uart.c` | `neorv32_uart.h` | HW driver functions for the **UART0** and **UART1**
| `neorv32_wdt.c` | `neorv32_wdt.h` | HW driver functions for the **WDT**
| `neorv32_xip.c` | `neorv32_xip.h` | HW driver functions for the **XIP**
| `neorv32_xirq.c` | `neorv32_xirq.h` | HW driver functions for the **XIRQ**
| `syscalls.c` | - | newlib system calls
|=======================
 
.Documentation
[TIP]
All core library software sources are highly documented using _doxygen_. See section <<Building the Software Framework Documentation>>.
The documentation is automatically built and deployed to GitHub pages by the CI workflow (:https://stnolting.github.io/neorv32/sw/files.html).
A CMSIS-SVD-compatible **System View Description (SVD)** file including all peripherals is available in `sw/svd`.
`sw/lib/include`. Currently, the following library files are available:
 
 
 
 
<<<
// ####################################################################################################################
:sectnums:
97,17 → 116,17
=== Application Makefile
 
Application compilation is based on a single, centralized **GNU makefiles** `sw/common/common.mk`. Each project in the
`sw/example` folder features a makefile that just includes this central makefile. When creating a new project, copy an existing project folder or
at least the makefile to your new project folder. I suggest to create new projects also in `sw/example` to keep
the file dependencies. Of course, these dependencies can be manually configured via makefiles variables
when your project is located somewhere else.
`sw/example` folder features a makefile that just includes this central makefile. When creating a new project copy an
existing project folder or at least the makefile to the new project folder. It is suggested to create new projects also
in `sw/example` to keep the file dependencies. However, these dependencies can be manually configured via makefiles
variables when the new project is located somewhere else.
 
[NOTE]
Before you can use the makefiles, you need to install the RISC-V GCC toolchain. Also, you have to add the
installation folder of the compiler to your system's `PATH` variable. More information can be found in
Before the makefile can be used to compile applications, the RISC-V GCC toolchain needs to be installed. Furthermore,
the `bin` folder of the compiler needs to be added to the system's `PATH` variable. More information can be found in
https://stnolting.github.io/neorv32/ug/#_software_toolchain_setup[User Guide: Software Toolchain Setup].
 
The makefile is invoked by simply executing make in your console:
The makefile is invoked by simply executing `make` in the console. For example:
 
[source,bash]
----
156,14 → 175,16
:sectnums:
==== Configuration
 
The compilation flow is configured via variables right at the beginning of the **central**
The compilation flow is configured via variables right at the beginning of the central
makefile (`sw/common/common.mk`):
 
[TIP]
The makefile configuration variables can be (re-)defined directly when invoking the makefile. For
example via `$ make MARCH=rv32ic clean_all exe`. You can also make project-specific definitions
of all variables inside the project's actual makefile (e.g., `sw/example/blink_led/makefile`).
The makefile configuration variables can be overridden or extended directly when invoking the makefile. For
example `$ make MARCH=rv32ic clean_all exe` overrides the default `MARCH` variable definitions.
Permanent modifications/definitions can be made in the project-local makefile
(e.g., `sw/example/blink_led/makefile`).
 
.Default Makefile Configuration
[source,makefile]
----
# *****************************************************************************
190,18 → 211,23
# *****************************************************************************
----
 
.Variables Description
[cols="<3,<10"]
[grid="none"]
|=======================
| _APP_SRC_ | The source files of the application (`*.c`, `*.cpp`, `*.S` and `*.s` files are allowed; file of these types in the project folder are automatically added via wildcards). Additional files can be added; separated by white spaces
| _APP_INC_ | Include file folders; separated by white spaces; must be defined with `-I` prefix
| _ASM_INC_ | Include file folders that are used only for the assembly source files (`*.S`/`*.s`).
| _EFFORT_ | Optimization level, optimize for size (`-Os`) is default; legal values: `-O0`, `-O1`, `-O2`, `-O3`, `-Os`
| _RISCV_PREFIX_ | The toolchain prefix to be used; follows the naming convention "architecture-vendor-output-"
| _MARCH_ | The targeted RISC-V architecture/ISA. Only `rv32` is supported by the NEORV32. Enable compiler support of optional CPU extension by adding the according extension letter (e.g. `rv32im` for _M_ CPU extension). See https://stnolting.github.io/neorv32/ug/#_enabling_risc_v_cpu_extensions[User Guide: Enabling RISC-V CPU Extensions] for more information.
| _MABI_ | The default 32-bit integer ABI.
| _USER_FLAGS_ | Additional flags that will be forwarded to the compiler tools
| _NEORV32_HOME_ | Relative or absolute path to the NEORV32 project home folder. Adapt this if the makefile/project is not in the project's `sw/example folder`.
| `APP_SRC` | The source files of the application (`*.c`, `*.cpp`, `*.S` and `*.s` files are allowed;
files of these types in the project folder are automatically added via wild cards). Additional files can be added separated by white spaces
| `APP_INC` | Include file folders; separated by white spaces; must be defined with `-I` prefix
| `ASM_INC` | Include file folders that are used only for the assembly source files (`*.S`/`*.s`).
| `EFFORT` | Optimization level, optimize for size (`-Os`) is default; legal values: `-O0`, `-O1`, `-O2`, `-O3`, `-Os`, `-Ofast`, ...
| `RISCV_PREFIX` | The toolchain prefix to be used; follows the triplet naming convention `[architecture]-[host_system]-[output]-...`
| `MARCH` | The targeted RISC-V architecture/ISA; enable compiler support of optional CPU extension by adding the according extension
name (e.g. `rv32im` for `M` CPU extension; see https://stnolting.github.io/neorv32/ug/#_enabling_risc_v_cpu_extensions[User Guide: Enabling RISC-V CPU Extensions]
for more information
| `MABI` | Application binary interface (default: 32-bit integer ABI `ilp32`)
| `USER_FLAGS` | Additional flags that will be forwarded to the compiler tools
| `NEORV32_HOME` | Relative or absolute path to the NEORV32 project home folder; adapt this if the makefile/project is not in the project's
default `sw/example` folder
|=======================
 
:sectnums:
208,19 → 234,19
==== Default Compiler Flags
 
The following default compiler flags are used for compiling an application. These flags are defined via the
`CC_OPTS` variable. Custom flags can be appended via the `USER_FLAGS` variable to the `CC_OPTS` variable.
`CC_OPTS` variable. Custom flags can be _appended_ to it using the `USER_FLAGS` variable.
 
[cols="<3,<9"]
[grid="none"]
|=======================
| `-Wall` | Enable all compiler warnings.
| `-ffunction-sections` | Put functions and data segment in independent sections. This allows a code optimization as dead code and unused data can be easily removed.
| `-nostartfiles` | Do not use the default start code. The makefiles use the NEORV32-specific start-up code instead (`sw/common/crt0.S`).
| `-Wl,--gc-sections` | Make the linker perform dead code elimination.
| `-lm` | Include/link with `math.h`.
| `-lc` | Search for the standard C library when linking.
| `-lgcc` | Make sure we have no unresolved references to internal GCC library subroutines.
| `-mno-fdiv` | Use built-in software functions for floating-point divisions and square roots (since the according instructions are not supported yet).
| `-Wall` | Enable all compiler warnings.
| `-ffunction-sections` | Put functions and data segment in independent sections. This allows a code optimization as dead code and unused data can be easily removed.
| `-nostartfiles` | Do not use the default start code. Instead, use the NEORV32-specific start-up code (`sw/common/crt0.S`).
| `-Wl,--gc-sections` | Make the linker perform dead code elimination.
| `-lm` | Include/link with `math.h`.
| `-lc` | Search for the standard C library when linking.
| `-lgcc` | Make sure we have no unresolved references to internal GCC library subroutines.
| `-mno-fdiv` | Use built-in software functions for floating-point divisions and square roots (since the according instructions are not supported yet).
| `-falign-functions=4` .4+| Force a 32-bit alignment of functions and labels (branch/jump/call targets). This increases performance as it simplifies instruction fetch when using the C extension. As a drawback this will also slightly increase the program code.
| `-falign-labels=4`
| `-falign-loops=4`
271,19 → 297,16
----
 
Each memory section provides a _base address_ `ORIGIN` and a _size_ `LENGTH`. The base address and size of the `iodev` section is
fixed and must not be altered. The base addresses and sizes of the `ram` and `rom` regions correspond to the total available instruction
and data memory address space (see section <<_address_space_layout>>).
fixed and should not be altered. The base addresses and sizes of the `ram` and `rom` regions correspond to the total available instruction
and data memory address space (see section <<_address_space_layout>>) as defined in `rtl/core/neorv32_package.vhd`.
 
[IMPORTANT]
`ORIGIN` of the `ram` section has to be always identical to the processor's `dspace_base_c` hardware configuration. Additionally,
`ORIGIN` of the `ram` section has to be always identical to the processor's `dspace_base_c` hardware configuration. +
+
`ORIGIN` of the `rom` section has to be always identical to the processor's `ispace_base_c` hardware configuration.
 
The sizes of `ram` section has to be equal to the size of the **physical available data instruction memory**. For example, if the processor
setup only uses processor-internal DMEM (<<_mem_int_dmem_en>> = _true_ and no external data memory attached) the `LENGTH` parameter of
this memory section has to be equal to the size configured by the <<_mem_int_dmem_size>> generic.
 
The sizes of `rom` section is a little bit more complicated. The default linker script configuration assumes a _maximum_ of 2GB _logical_
memory space, which is also the default configuration of the processor's hardware instruction memory address space. This size _does not_ have
memory space, which is also the default configuration of the processor's hardware instruction memory address space. This size does not have
to reflect the _actual_ physical size of the instruction memory (internal IMEM and/or processor-external memory). It just provides a maximum
limit. When uploading new executable via the bootloader, the bootloader itself checks if sufficient _physical_ instruction memory is available.
If a new executable is embedded right into the internal-IMEM the synthesis tool will check, if the configured instruction memory size
297,8 → 320,8
(`make_bootloader` symbol is set) the generated bootloader will only use the _first_ 512 bytes of the data address space. This is
a fall-back to ensure the bootloader can operate independently of the actual _physical_ data memory size.
 
The linker maps all the regions from the compiled object files into four final sections: `.text`, `.rodata`, `.data` and `.bss`.
These four regions contain everything required for the application to run:
The linker maps all the regions from the compiled object files into five final sections: `.text`, `.rodata`, `.data`, `.bss` and `.heap`.
These regions contain everything required for the application to run:
 
.Linker memory regions
[cols="<1,<9"]
309,14 → 332,80
| `.rodata` | Constants (like strings) from the application; also the initial data for initialized variables.
| `.data` | This section is required for the address generation of fixed (= global) variables only.
| `.bss` | This section is required for the address generation of dynamic memory constructs only.
| `.heap` | This section is required for the address generation of dynamic memory constructs only.
|=======================
 
The `.text` and `.rodata` sections are mapped to processor's instruction memory space and the `.data` and
`.bss` sections are mapped to the processor's data memory space. Finally, the `.text`, `.rodata` and `.data`
The `.text` and `.rodata` sections are mapped to processor's instruction memory space and the `.data`,
`.bss` and `heap` sections are mapped to the processor's data memory space. Finally, the `.text`, `.rodata` and `.data`
sections are extracted and concatenated into a single file `main.bin`.
 
 
:sectnums:
==== RAM Layout
 
The default NEORV32 linker script uses all of the defined RAM (linker script memory section `ram`) to create four areas.
Note that depending on the application some areas might not be existent at all.
 
.Default RAM Layout
image::ram_layout.png[400]
 
[start=1]
. **Constant data (`.data`)**: The constant data section is placed right at the beginning of the RAM. For example, this section
contains _explicitly initialized_ global variables. This section is initialized by the executable.
. **Dynamic data (`.bss`)**: The constant data section is followed by the dynamic data section, which contains _uninitialized_ data
like global variables without explicit initialization. This section is cleared by the start-up code `crt0.S`.
. **Heap (`.heap`)**: The heap is used for dynamic memory that is managed by functions like `malloc()` and `free()`. The heap
grows upwards. This section is not initialized at all.
. **Stack**: The stack starts at the very end of the RAM at address `ORIGIN(ram) + LENGTH(ram) - 4`. The stack grows downwards.
 
There is _no explicit limit_ for the maximum stack size as this is hard to check. However, a physical memory protection rule could
be used to configure a maximum size by adding a "protection area" between stack and heap (a PMP region without any access rights).
 
The maximum size of the heap is defined by the linker script's `__heap_size` symbol. This symbol can be overridden at any time.
By default, the maximum heap size is 1/4 of the total RAM size.
 
.Heap-Stack Collisions
[WARNING]
Take care when using dynamic memory to avoid collision of the heap and stack memory areas. There is no compile-time protection
mechanism available as the actual heap and stack size are defined by _runtime_ data. Also beware of fragmentation when
using dynamic memory allocation.
 
 
:sectnums:
==== C Standard Library
 
.Constructors and Deconstructors
[IMPORTANT]
The NEORV32 processor is an embedded system intended for running bare-metal or RTOS applications. To simplify this setup
explicit constructors and deconstructors are not supported by default. However, a minimal "deconstructor-alike" support is
provided by the <<_after_main_handler>>.
 
The NEORV32 is a processor for _embedded_ applications. Hence, it is not capable of running desktop OSs like Linux
(at least not without emulation). Hence, the software framework relies on a "bare-metal" setup that uses **newlib**
as default C standard library.
 
.RTOS Support
[NOTE]
The NEORV32 CPU and processor **do support** embedded RTOS like FreeRTOS and Zephyr. See the User guide section
https://stnolting.github.io/neorv32/ug/#_zephyr_rtos_support[Zephyr RTOS Support] and
https://stnolting.github.io/neorv32/ug/#_freertos_support[FreeRTOS Support]
for more information.
 
Newlib provides stubs for common "system calls" (like file handling and standard input/output) that are used by other
C libraries like `stdio`. These stubs are available in `sw/source/syscalls.c` and were adapted for the NEORV32 processor.
 
.Standard Console(s)
[NOTE]
<<_primary_universal_asynchronous_receiver_and_transmitter_uart0, UART0>>
is used to implement all the standard input, output and error consoles (`STDIN`, `STDOUT` and `STDERR`).
 
.Newlib Test/Demo Program
[TIP]
A simple test and demo program, which uses some of newlib's core functions (like `malloc`/`free` and `read`/`write`)
is available in `sw/example_newlib_demo`
 
 
:sectnums:
==== Executable Image Generator
 
The `main.bin` file is packed by the NEORV32 image generator (`sw/image_gen`) to generate the final executable file.
384,309 → 473,29
`__neorv32_crt0_after_main` function is irrelevant as there is no further "software instance" executed afterwards that can check this.
However, the on-chip debugger could still evaluate the return value of the after-main handler.
 
A simple `printf` can be used to inform the user when the application's main function returns
A simple UARt output can be used to inform the user when the application's main function returns
(this example assumes that UART0 has been already properly configured in the actual application):
 
.After-main handler - example
.After-main handler - simple example
[source,c]
----
int __neorv32_crt0_after_main(int32_t return_code) {
 
neorv32_uart0_printf("Main returned with code: %i\n", return_code);
neorv32_uart0_printf("\n<RTE> main function returned with exit code %i. </RTE>\n", return_code); <1>
return 0;
}
----
<1> Use `<RTE>` here to make clear this is a message comes from the runtime environment.
 
 
<<<
// ####################################################################################################################
:sectnums:
=== Bootloader
 
[NOTE]
This section illustrated the **default** bootloader from the repository. The bootloader can be customized
to target application-specific scenarios. See User Guide section
https://stnolting.github.io/neorv32/ug/#_customizing_the_internal_bootloader[Customizing the Internal Bootloader]
for more information.
include::software_bootloader.adoc[]
 
The default NEORV32 bootloader (source code `sw/bootloader/bootloader.c`) provides a build-in firmware that
allows to upload new application executables via UART at every time and to optionally store/boot them to/from
an external SPI flash. It features a simple "automatic boot" feature that will try to fetch an executable
from SPI flash if there is _no_ UART user interaction. This allows to build processor setup with
non-volatile application storage, which can be updated at any time.
 
The bootloader is only implemented if the <<_int_bootloader_en>> generic is _true_. This will
select the <<_indirect_boot>> boot configuration.
 
.Hardware requirements of the _default_ NEORV32 bootloader
[IMPORTANT]
**REQUIRED**: The bootloader requires the CSR access CPU extension (<<_cpu_extension_riscv_zicsr>> generic is _true_)
and at least 512 bytes of data memory (processor-internal DMEM or external DMEM). +
+
_RECOMMENDED_: For user interaction via UART (like uploading executables) the primary UART (UART0) has to be
implemented (<<_io_uart0_en>> generic is _true_). Without UART the bootloader does not make much sense. However, auto-boot
via SPI is still supported but the bootloader should be customized (see User Guide) for this purpose. +
+
_OPTIONAL_: The default bootloader uses bit 0 of the GPIO output port as "heart beat" and status LED if the
GPIO controller is implemented (<<_io_gpio_en>> generic is _true_). +
+
_OPTIONAL_: The MTIME machine timer (<<_io_mtime_en>> generic is _true_) and the SPI controller
(<<_io_spi_en>> generic is _true_) are required in order to use the bootloader's auto-boot feature
(automatic boot from external SPI flash if there is no user interaction via UART).
 
To interact with the bootloader, connect the primary UART (UART0) signals (`uart0_txd_o` and
`uart0_rxd_o`) of the processor's top entity via a serial port (-adapter) to your computer (hardware flow control is
not used so the according interface signals can be ignored.), configure your
terminal program using the following settings and perform a reset of the processor.
 
Terminal console settings (`19200-8-N-1`):
 
* 19200 Baud
* 8 data bits
* no parity bit
* 1 stop bit
* newline on `\r\n` (carriage return, newline)
* no transfer protocol / control flow protocol - just the raw byte stuff
 
[IMPORTANT]
_Any_ terminal program that can connect to a serial port should work. However, make sure the program
can transfer data in _raw_ byte mode without any protocol overhead around it. Some terminal programs struggle with
transmitting files larger than 4kB (see https://github.com/stnolting/neorv32/pull/215). Try a different program
if uploading a binary does not work (terminal stall).
 
The bootloader uses the LSB of the top entity's `gpio_o` output port as high-active status LED (all other
output pin are set to low level by the bootloader). After reset, this LED will start blinking at ~2Hz and the
following intro screen should show up in your terminal:
 
[source]
----
<< NEORV32 Bootloader >>
 
BLDV: Mar 23 2021
HWV: 0x01050208
CLK: 0x05F5E100
MISA: 0x40901105
CPU: 0x00000023
SOC: 0x0EFF0037
IMEM: 0x00004000 bytes @ 0x00000000
DMEM: 0x00002000 bytes @ 0x80000000
 
Autoboot in 8s. Press key to abort.
----
 
This start-up screen also gives some brief information about the bootloader and several system configuration parameters:
 
[cols="<2,<15"]
[grid="none"]
|=======================
| `BLDV` | Bootloader version (built date).
| `HWV` | Processor hardware version (from the `mimpid` CSR) in BCD format (example: `0x01040606` = v1.4.6.6).
| `CLK` | Processor clock speed in Hz (via the SYSINFO module, from the _CLOCK_FREQUENCY_ generic).
| `MISA` | CPU extensions (from the `misa` CSR).
| `CPU` | CPU sub-extensions (via the `CPU` register in the SYSINFO module)
| `SOC` | Processor configuration (via the `SOC` register in the SYSINFO module / from the IO_* and MEM_* configuration generics).
| `IMEM` | IMEM memory base address and size in byte (from the _MEM_INT_IMEM_SIZE_ generic).
| `DMEM` | DMEM memory base address and size in byte (from the _MEM_INT_DMEM_SIZE_ generic).
|=======================
 
Now you have 8 seconds to press any key. Otherwise, the bootloader starts the auto boot sequence. When
you press any key within the 8 seconds, the actual bootloader user console starts:
 
[source]
----
<< NEORV32 Bootloader >>
 
BLDV: Mar 23 2021
HWV: 0x01050208
CLK: 0x05F5E100
USER: 0x10000DE0
MISA: 0x40901105
CPU: 0x00000023
SOC: 0x0EFF0037
IMEM: 0x00004000 bytes @ 0x00000000
DMEM: 0x00002000 bytes @ 0x80000000
 
Autoboot in 8s. Press key to abort.
Aborted.
 
Available commands:
h: Help
r: Restart
u: Upload
s: Store to flash
l: Load from flash
e: Execute
CMD:>
----
 
The auto-boot countdown is stopped and now you can enter a command from the list to perform the
corresponding operation:
 
* `h`: Show the help text (again)
* `r`: Restart the bootloader and the auto-boot sequence
* `u`: Upload new program executable (`neorv32_exe.bin`) via UART into the instruction memory
* `s`: Store executable to SPI flash at `spi_csn_o(0)` (little-endian byte order)
* `l`: Load executable from SPI flash at `spi_csn_o(0)` (little-endian byte order)
* `e`: Start the application, which is currently stored in the instruction memory (IMEM)
 
A new executable can be uploaded via UART by executing the `u` command. After that, the executable can be directly
executed via the `e` command. To store the recently uploaded executable to an attached SPI flash press `s`. To
directly load an executable from the SPI flash press `l`. The bootloader and the auto-boot sequence can be
manually restarted via the `r` command.
 
[TIP]
The CPU is in machine level privilege mode after reset. When the bootloader boots an application,
this application is also started in machine level privilege mode.
 
[TIP]
For detailed information on using an SPI flash for application storage see User Guide section
https://stnolting.github.io/neorv32/ug/#_programming_an_external_spi_flash_via_the_bootloader[Programming an External SPI Flash via the Bootloader].
 
 
:sectnums:
==== Auto Boot Sequence
When you reset the NEORV32 processor, the bootloader waits 8 seconds for a UART console input before it
starts the automatic boot sequence. This sequence tries to fetch a valid boot image from the external SPI
flash, connected to SPI chip select `spi_csn_o(0)`. If a valid boot image is found that can be successfully
transferred into the instruction memory, it is automatically started. If no SPI flash is detected or if there
is no valid boot image found, and error code will be shown.
 
 
:sectnums:
==== Bootloader Error Codes
 
If something goes wrong during bootloader operation, an error code is shown. In this case the processor
stalls, a bell command and one of the following error codes are send to the terminal, the bootloader status
LED is permanently activated and the system must be manually reset.
 
[cols="<2,<13"]
[grid="rows"]
|=======================
| **`ERROR_0`** | If you try to transfer an invalid executable (via UART or from the external SPI flash), this error message shows up. There might be a transfer protocol configuration error in the terminal program. Also, if no SPI flash was found during an auto-boot attempt, this message will be displayed.
| **`ERROR_1`** | Your program is way too big for the internal processor’s instructions memory. Increase the memory size or reduce your application code.
| **`ERROR_2`** | This indicates a checksum error. Something went wrong during the transfer of the program image (upload via UART or loading from the external SPI flash). If the error was caused by a UART upload, just try it again. When the error was generated during a flash access, the stored image might be corrupted.
| **`ERROR_3`** | This error occurs if the attached SPI flash cannot be accessed. Make sure you have the right type of flash and that it is properly connected to the NEORV32 SPI port using chip select #0.
| **`ERR 0x???????? 0x???????? 0x????????`** | The bootloader encountered an exception during operation. This might be caused when it tries to access peripherals that were not implemented during synthesis. Example: executing `l` or `s` (SPI flash operations) without the SPI module beeing implemented.
|=======================
 
 
 
<<<
// ####################################################################################################################
:sectnums:
=== NEORV32 Runtime Environment
 
The NEORV32 provides a minimal runtime environment (RTE) that takes care of a stable
and _safe_ execution environment by handling _all_ traps (including interrupts).
 
[NOTE]
Using the RTE is **optional**. The RTE provides a simple and comfortable way of delegating traps while making sure that all traps (even though they are not
explicitly used by the application) are handled correctly. Performance-optimized applications or embedded operating systems should not use the RTE for delegating traps.
 
When execution enters the application's `main` function, the actual runtime environment is responsible for catching all implemented exceptions
and interrupts. To activate the NEORV32 RTE execute the following function:
 
[source,c]
----
void neorv32_rte_setup(void);
----
 
This setup initializes the `mtvec` CSR, which provides the base entry point for all trap
handlers. The address stored to this register reflects the first-level exception handler provided by the
NEORV32 RTE. Whenever an exception or interrupt is triggered, this first-level handler is called.
 
The first-level handler performs a complete context save, analyzes the source of the exception/interrupt and
calls the according second-level exception handler, which actually takes care of the exception/interrupt
handling. For this, the RTE manages a private look-up table to store the addresses of the according trap
handlers.
 
After the initial setup of the RTE, each entry in the trap handler's look-up table is initialized with a debug
handler, that outputs detailed hardware information via the **primary UART (UART0)** when triggered. This
is intended as a fall-back for debugging or for accidentally-triggered exceptions/interrupts.
For instance, an illegal instruction exception caught by the RTE debug handler might look like this in the UART0 output:
 
[source]
----
<RTE> Illegal instruction @ PC=0x000002d6, MTVAL=0x00001537 </RTE>
----
 
For bus access faults the RTE also outputs the error code from the <<_internal_bus_monitor_buskeeper>>
to show the cause of the access fault. Two example are shown below.
 
[source]
----
<RTE> Load access fault [TIMEOUT_ERR] @ PC=0x00000150, MTVAL=0xFFFFFF70 </RTE>
<RTE> Store access fault [DEVICE_ERR] @ PC=0x00000162, MTVAL=0xF0000000 </RTE>
----
 
To install the **actual application's trap handlers** the NEORV32 RTE provides functions for installing and
un-installing trap handler for each implemented exception/interrupt source.
 
[source,c]
----
int neorv32_rte_exception_install(uint8_t id, void (*handler)(void));
----
 
[cols="<5,<12"]
[options="header",grid="rows"]
|=======================
| ID name [C] | Description / trap causing entry
| `RTE_TRAP_I_MISALIGNED` | instruction address misaligned
| `RTE_TRAP_I_ACCESS` | instruction (bus) access fault
| `RTE_TRAP_I_ILLEGAL` | illegal instruction
| `RTE_TRAP_BREAKPOINT` | breakpoint (`ebreak` instruction)
| `RTE_TRAP_L_MISALIGNED` | load address misaligned
| `RTE_TRAP_L_ACCESS` | load (bus) access fault
| `RTE_TRAP_S_MISALIGNED` | store address misaligned
| `RTE_TRAP_S_ACCESS` | store (bus) access fault
| `RTE_TRAP_MENV_CALL` | environment call from machine mode (`ecall` instruction)
| `RTE_TRAP_UENV_CALL` | environment call from user mode (`ecall` instruction)
| `RTE_TRAP_MTI` | machine timer interrupt
| `RTE_TRAP_MEI` | machine external interrupt
| `RTE_TRAP_MSI` | machine software interrupt
| `RTE_TRAP_FIRQ_0` : `RTE_TRAP_FIRQ_15` | fast interrupt channel 0..15
|=======================
 
When installing a custom handler function for any of these exception/interrupts, make sure the function uses
**no attributes** (especially no interrupt attribute!), has no arguments and no return value like in the following
example:
 
[source,c]
----
void handler_xyz(void) {
 
// handle exception/interrupt...
}
----
 
[WARNING]
Do NOT use the `((interrupt))` attribute for the application exception handler functions! This
will place an `mret` instruction to the end of it making it impossible to return to the first-level
exception handler of the RTE, which will cause stack corruption.
 
Example: Installation of the MTIME interrupt handler:
 
[source,c]
----
neorv32_rte_exception_install(EXC_MTI, handler_xyz);
----
 
To remove a previously installed exception handler call the according un-install function from the NEORV32
runtime environment. This will replace the previously installed handler by the initial debug handler, so even
un-installed exceptions and interrupts are further captured.
 
[source,c]
----
int neorv32_rte_exception_uninstall(uint8_t id);
----
 
Example: Removing the MTIME interrupt handler:
 
[source,c]
----
neorv32_rte_exception_uninstall(EXC_MTI);
----
 
[TIP]
More information regarding the NEORV32 runtime environment can be found in the doxygen
software documentation (also available online at https://stnolting.github.io/neorv32/sw/files.html[GitHub pages]).
include::software_rte.adoc[]
/neorv32/trunk/docs/datasheet/software_bootloader.adoc
0,0 → 1,174
:sectnums:
=== Bootloader
 
[NOTE]
This section refers to the **default** bootloader from the repository. The bootloader can be customized
to target application-specific scenarios. See User Guide section
https://stnolting.github.io/neorv32/ug/#_customizing_the_internal_bootloader[Customizing the Internal Bootloader]
for more information.
 
The NEORV32 bootloader (source code `sw/bootloader/bootloader.c`) provides an optional build-in firmware that
allows to upload new application executables without the need to re-synthesize the FPGA's bitstream.
A UART connection is used to provide a simple text-based user interface that allows to upload executables.
 
Furthermore, the bootloader provides options to program executable to a processor-external SPI flash.
An "auto boot" feature can optionally fetch this executable
right after reset if there is no user interaction via UART. This allows to build processor setup with
non-volatile application storage, which can still be updated at any time.
 
The bootloader is implemented if the <<_int_bootloader_en>> generic is _true_ (default). This will automatically
select the CPU's <<_indirect_boot>> boot configuration.
 
.Hardware Requirements for the _Default_ NEORV32 Bootloader
[IMPORTANT]
**REQUIRED**: The bootloader requires the privileged architecture CPU extension
(<<_zicsr_control_and_status_register_access_privileged_architecture>>)
and at least 512 bytes of data memory (processor-internal DMEM or external DMEM). +
+
**RECOMMENDED**: For user interaction via UART (like uploading executables) the primary UART
(<<_primary_universal_asynchronous_receiver_and_transmitter_uart0>>) has to be implemented.
Without UART0 the auto-boot via SPI is still supported but the bootloader should be customized
(see User Guide) for this purpose. +
+
**RECOMMENDED**: The default bootloader uses bit 0 of the GPIO controller's
(<<_general_purpose_input_and_output_port_gpio>>) output port to drive a high-active "heart beat" status LED. +
+
**RECOMMENDED**: The MTIME machine timer (<<_machine_system_timer_mtime>> generic is _true_) is used to control
blinking of the status LED and also to automatically trigger the auto-boot sequence. +
+
**OPTIONAL**: The SPI controller (<<_serial_peripheral_interface_controller_spi>>) is required
to store/load executable from external flash (for the auto boot feature).
 
To interact with the bootloader, connect the primary UART (UART0) signals (`uart0_txd_o` and
`uart0_rxd_o`) of the processor's top entity via a serial port (-adapter) to your computer (hardware flow control is
not used so the according interface signals can be ignored.), configure your
terminal program using the following settings and perform a reset of the processor.
 
Terminal console settings (`19200-8-N-1`):
 
* 19200 Baud
* 8 data bits
* no parity bit
* 1 stop bit
* newline on `\r\n` (carriage return, newline)
* no transfer protocol / control flow protocol - just raw bytes
 
[IMPORTANT]
_Any_ terminal program that can connect to a serial port should work. However, make sure the program
can transfer data in _raw_ byte mode without any protocol overhead around it. Some terminal programs struggle with
transmitting files larger than 4kB (see https://github.com/stnolting/neorv32/pull/215). Try a different program
if uploading a binary does not work.
 
The bootloader uses the LSB of the top entity's `gpio_o` output port as high-active **status LED** (all other
output pin are set to low level). After reset, this LED will start blinking at ~2Hz and the
following intro screen should show up in your terminal:
 
[source]
----
<< NEORV32 Bootloader >>
 
BLDV: Feb 16 2022
HWV: 0x01060709
CLK: 0x05f5e100
ISA: 0x40901107 + 0xc000068b
SOC: 0x7b7f402f
IMEM: 0x00008000 bytes @0x00000000
DMEM: 0x00004000 bytes @0x80000000
 
Autoboot in 8s. Press any key to abort.
----
 
This start-up screen also gives some brief information about the bootloader and several system configuration parameters:
 
[cols="<2,<15"]
[grid="none"]
|=======================
| `BLDV` | Bootloader version (built date).
| `HWV` | Processor hardware version (the <<_mimpid>> CSR); in BCD format; example: `0x01040606` = v1.4.6.6).
| `CLK` | Processor clock speed in Hz (via the `CLK` register from <<_system_configuration_information_memory_sysinfo>>; defined by the <<_clock_frequency>> generic).
| `ISA` | CPU extensions (<<_misa>> CSR + <<_mxisa>> CSR).
| `SOC` | Processor configuration (via the `SOC` register from the <<_system_configuration_information_memory_sysinfo>>; defined by the `IO_*` and `MEM_*` configuration generics).
| `IMEM` | IMEM memory base address and size in byte (via the `IMEM_SIZE` and `ISPACE_BASE` registers from the <<_system_configuration_information_memory_sysinfo>>; defined by the <<_mem_int_imem_size>> generic).
| `DMEM` | DMEM memory base address and size in byte (via the `DMEM_SIZE` and `DSPACE_BASE` registers from the <<_system_configuration_information_memory_sysinfo>>; defined by the <<_mem_int_dmem_size>> generic).
|=======================
 
Now you have 8 seconds to press _any_ key. Otherwise, the bootloader starts the <<_auto_boot_sequence>>. When
you press any key within the 8 seconds, the actual bootloader user console starts:
 
[source]
----
<< NEORV32 Bootloader >>
 
BLDV: Feb 16 2022
HWV: 0x01060709
CLK: 0x05f5e100
ISA: 0x40901107 + 0xc000068b
SOC: 0x7b7f402f
IMEM: 0x00008000 bytes @0x00000000
DMEM: 0x00004000 bytes @0x80000000
 
Autoboot in 8s. Press any key to abort.
Aborted. <1>
 
Available commands:
h: Help
r: Restart
u: Upload
s: Store to flash
l: Load from flash
e: Execute
CMD:>
----
<1> Auto boot sequence aborted due to user console input.
 
The auto boot countdown is stopped and the bootloader's user console is ready to receive one of the following commands:
 
* `h`: Show the help text (again)
* `r`: Restart the bootloader and the auto-boot sequence
* `u`: Upload new program executable (`neorv32_exe.bin`) via UART into the instruction memory
* `s`: Store executable to SPI flash at `spi_csn_o(0)` (little-endian byte order)
* `l`: Load executable from SPI flash at `spi_csn_o(0)` (little-endian byte order)
* `e`: Start the application, which is currently stored in the instruction memory (IMEM)
 
A new executable can be uploaded via UART by executing the `u` command. After that, the executable can be directly
executed via the `e` command. To store the recently uploaded executable to an attached SPI flash press `s`. To
directly load an executable from the SPI flash press `l`. The bootloader and the auto-boot sequence can be
manually restarted via the `r` command.
 
[TIP]
The CPU is in machine level privilege mode after reset. When the bootloader boots an application,
this application is also started in machine level privilege mode.
 
[TIP]
For detailed information on using an SPI flash for application storage see User Guide section
https://stnolting.github.io/neorv32/ug/#_programming_an_external_spi_flash_via_the_bootloader[Programming an External SPI Flash via the Bootloader].
 
 
:sectnums:
==== Auto Boot Sequence
 
When you reset the NEORV32 processor, the bootloader waits 8 seconds for a UART console input before it
starts the automatic boot sequence. This sequence tries to fetch a valid boot image from the external SPI
flash, connected to SPI chip select `spi_csn_o(0)`. If a valid boot image is found that can be successfully
transferred into the instruction memory, it is automatically started. If no SPI flash is detected or if there
is no valid boot image found, and error code will be shown.
 
 
:sectnums:
==== Bootloader Error Codes
 
If something goes wrong during bootloader operation, an error code and a short message is shown. In this case the processor
stalls,, the bootloader status LED is permanently activated and the processor must be reset manually.
 
[TIP]
In many cases the error source is just _temporary_ (like some HF spike during an UART upload). Just try again.
 
[cols="<2,<8"]
[grid="rows"]
|=======================
| **`ERROR_0`** | If you try to transfer an invalid executable (via UART or from the external SPI flash), this error message shows up. There might be a transfer protocol configuration error in the terminal program. Also, if no SPI flash was found during an auto-boot attempt, this message will be displayed.
| **`ERROR_1`** | Your program is way too big for the internal processor’s instructions memory. Increase the memory size or reduce your application code.
| **`ERROR_2`** | This indicates a checksum error. Something went wrong during the transfer of the program image (upload via UART or loading from the external SPI flash). If the error was caused by a UART upload, just try it again. When the error was generated during a flash access, the stored image might be corrupted.
| **`ERROR_3`** | This error occurs if the attached SPI flash cannot be accessed. Make sure you have the right type of flash and that it is properly connected to the NEORV32 SPI port using chip select #0.
| **`ERROR - Unexpected exception!`** | The bootloader encountered an exception during operation. This might be caused when it tries to access peripherals that were not implemented during synthesis. Example: executing commands `l` or `s` (SPI flash operations) without the SPI module beeing implemented.
|=======================
/neorv32/trunk/docs/datasheet/software_rte.adoc
0,0 → 1,243
:sectnums:
=== NEORV32 Runtime Environment
 
The NEORV32 software framework provides a minimal runtime environment (**RTE**) that takes care of a stable
and _safe_ execution environment by handling _all_ traps (= exceptions & interrupts). The RTE simplifies trap handling
by wrapping the CPU's _privileged architecture_ (i.e. trap-related CSRs) into a unified software API.
The NEORV32 RTE is a software library (`sw/lib/source/neorv32_rte.c`) that is part of the default processor library set.
It provides public functions via `sw/lib/include/neorv32_rte.h` for application interaction.
 
Once initialized, the RTE provides <<_default_rte_trap_handlers>> that catch all possible exceptions. These
default handlers just output a message via UART to inform the user when a certain trap has been triggered. The
default handlers can be overridden by the application code to install application-specific handler functions for each trap.
 
[IMPORTANT]
Using the RTE is **optional but highly recommended**. The RTE provides a simple and comfortable way of delegating
traps to application-specific handlers while making sure that all traps (even though they are not explicitly used
by the application) are handled correctly. Performance-optimized applications or embedded operating systems should
not use the RTE for delegating traps.
 
[NOTE]
For the **C standard runtime library** see section <<c_standard_library>>.
 
 
==== RTE Operation
 
The RTE handles the trap-related CSRs of the CPU's privileged architecture (<<_machine_trap_handling_csrs>>).
It initializes the <<_mtvec>> CSR, which provides the base entry point for all trap
handlers. The address stored to this register reflects the **first-level exception handler**, which is provided by the
NEORV32 RTE. Whenever an exception or interrupt is triggered this first-level handler is executed.
 
The first-level handler performs a complete context save, analyzes the source of the exception/interrupt and
calls the according **second-level exception handler**, which takes care of the actual exception/interrupt
handling. For this, the RTE manages a private look-up table to store the addresses of the according trap
handlers.
 
After the initial RTE setup, each entry in the RTE's trap handler's look-up table is initialized with a
<<_default_rte_trap_handlers>>. These default handler do not execute any trap-related operations - they
just output a message via the *primary UART (UART0)* to inform the user that a trap has occurred, that is not
handled by the actual application. After sending this message, the RTE tries to continue executing the user program.
 
 
==== Using the RTE
 
The NEORV32 is enabled by calling the RTE's setup function:
 
.Function Prototype: RTE Setup
[source,c]
----
void neorv32_rte_setup(void);
----
 
[NOTE]
The RTE should be enabled right at the beginning of the application's `main` function.
 
As mentioned above, _all_ traps will only trigger execution of the RTE's <<_default_rte_trap_handlers>>.
To use application-specific handlers, which actually _handle_ a trap, the default handlers can be overridden
by installing user-defined ones:
 
.Function Prototype: Installing an Application-Specific Trap Handler
[source,c]
----
int neorv32_rte_exception_install(uint8_t id, void (*handler)(void));
----
 
The first argument `id` defines the "trap ID" (for example a certain interrupt request) that shall be handled
by the user-defined handler. The second argument `*handler` is the actual function that implements the trap
handler. The function return zero on success and a non-zero value if an error occurred (invalid `id`). In this
case no modifications to the RTE's trap look-up-table will be made.
 
The custom handler functions need to have a specific format without any arguments an with no return value:
 
.Function Prototype: Custom Trap Handler
[source,c]
----
void custom_trap_handler_xyz(void) {
 
// handle exception/interrupt...
}
----
 
.Custom Trap Handler Attributes
[WARNING]
Do NOT use the `((interrupt))` attribute for the application exception handler functions! This
will place a `mret` instruction to the end of it making it impossible to return to the first-level
exception handler of the RTE core, which will cause stack corruption.
 
The trap identifier `id` specifies the according trap cause. These can be an _asynchronous trap_ like
an interrupt from one of the processor modules or a _synchronous trap_ triggered by software-caused events
like an illegal instruction or an environment call instruction. The `sw/lib/include/neorv32_rte.h` library files
provides aliases for trap events supported by the CPU (see <<_neorv32_trap_listing>>) that can be used when
installing custom trap handler functions:
 
.RTE Trap ID List
[cols="<5,<12"]
[options="header",grid="rows"]
|=======================
| ID alias [C] | Description / trap causing event
| `RTE_TRAP_I_MISALIGNED` | instruction address misaligned
| `RTE_TRAP_I_ACCESS` | instruction (bus) access fault
| `RTE_TRAP_I_ILLEGAL` | illegal instruction
| `RTE_TRAP_BREAKPOINT` | breakpoint (`ebreak` instruction)
| `RTE_TRAP_L_MISALIGNED` | load address misaligned
| `RTE_TRAP_L_ACCESS` | load (bus) access fault
| `RTE_TRAP_S_MISALIGNED` | store address misaligned
| `RTE_TRAP_S_ACCESS` | store (bus) access fault
| `RTE_TRAP_MENV_CALL` | environment call from machine mode (`ecall` instruction)
| `RTE_TRAP_UENV_CALL` | environment call from user mode (`ecall` instruction)
| `RTE_TRAP_MTI` | machine timer interrupt
| `RTE_TRAP_MEI` | machine external interrupt
| `RTE_TRAP_MSI` | machine software interrupt
| `RTE_TRAP_FIRQ_0` | fast interrupt channel 0
| `RTE_TRAP_FIRQ_1` | fast interrupt channel 1
| `RTE_TRAP_FIRQ_2` | fast interrupt channel 2
| `RTE_TRAP_FIRQ_3` | fast interrupt channel 3
| `RTE_TRAP_FIRQ_4` | fast interrupt channel 4
| `RTE_TRAP_FIRQ_5` | fast interrupt channel 5
| `RTE_TRAP_FIRQ_6` | fast interrupt channel 6
| `RTE_TRAP_FIRQ_7` | fast interrupt channel 7
| `RTE_TRAP_FIRQ_8` | fast interrupt channel 8
| `RTE_TRAP_FIRQ_9` | fast interrupt channel 9
| `RTE_TRAP_FIRQ_10` | fast interrupt channel 10
| `RTE_TRAP_FIRQ_11` | fast interrupt channel 11
| `RTE_TRAP_FIRQ_12` | fast interrupt channel 12
| `RTE_TRAP_FIRQ_13` | fast interrupt channel 13
| `RTE_TRAP_FIRQ_14` | fast interrupt channel 14
| `RTE_TRAP_FIRQ_15` | fast interrupt channel 15
|=======================
 
The following example shows how to install a custom handler (`custom_mtime_irq_handler`) for handling
the RISC-V machine timer (MTIME) interrupt:
 
.Example: Installing the MTIME IRQ Handler
[source,c]
----
neorv32_rte_exception_install(RTE_TRAP_MTI, custom_mtime_irq_handler);
----
 
User-defined trap handlers can also be un-installed. This will remove the users trap handler from the RTE core
and will re-install the <<_default_rte_trap_handlers>> for the specific trap.
 
.Function Prototype: Installing an Application-Specific Trap Handler
[source,c]
----
int neorv32_rte_exception_uninstall(uint8_t id);
----
 
The argument `id` defines the identifier of the according trap that shall be un-installed. The function return zero
on success and a non-zero value if an error occurred (invalid `id`). In this case no modifications to the RTE's trap
look-up-table will be made.
 
The following example shows how to un-install the custom handler `custom_mtime_irq_handler` from the
RISC-V machine timer (MTIME) interrupt:
 
.Example: Removing the Custom MTIME IRQ Handler
[source,c]
----
neorv32_rte_exception_uninstall(RTE_TRAP_MTI);
----
 
 
==== Default RTE Trap Handlers
 
The default RTE trap handlers are executed when a certain trap is triggered that is not handled by a user-defined
application-specific trap handler. These default handler will just output a message giving additional debug information
via UART0 to inform the user and will try to resume normal execution of the application.
 
.Continuing Execution
[IMPORTAN]
In most cases the RTE can successfully continue operation when it catches an interrupt request, which is not handled
by the actual application program. However, if the RTE catches an un_handled exception like a bus access fault
continuing execution will most likely fail and the CPU will crash.
 
.RTE Default Trap Handler Output Example (Illegal Instruction)
[source]
----
<RTE> Illegal instruction @ PC=0x000002d6, MTVAL=0x00001537 </RTE>
----
 
In this example the "Illegal instruction" _message_ describes the cause of the trap, which is an illegal instruction
exception here. `PC` shows the current program counter value when the trap occurred and `MTVAL` shows additional
debug information from the <<_mtval>> CSR. In this case it shows the encoding of the illegal instruction.
 
The specific _message_ corresponds to the trap code from the <<_mcause>> CSR (see <<_neorv32_trap_listing>>).
A full list of all messages and the according `mcause` trap codes are shown below.
 
.RTE Default Trap Handler Messages and According `mcause` Values
[cols="<5,^5"]
[options="header",grid="rows"]
|=======================
| Trap identifier | According `mcause` CSR value
| "Instruction address misaligned" | `0x00000000`
| "Instruction access fault" | `0x00000001`
| "Illegal instruction" | `0x00000002`
| "Breakpoint" | `0x00000003`
| "Load address misaligned" | `0x00000004`
| "Load access fault" | `0x00000005`
| "Store address misaligned" | `0x00000006`
| "Store access fault" | `0x00000007`
| "Environment call from U-mode" | `0x00000008`
| "Environment call from M-mode" | `0x0000000b`
| "Machine software interrupt" | `0x80000003`
| "Machine timer interrupt" | `0x80000007`
| "Machine external interrupt" | `0x8000000b`
| "Fast interrupt 0" | `0x80000010`
| "Fast interrupt 1" | `0x80000011`
| "Fast interrupt 2" | `0x80000012`
| "Fast interrupt 3" | `0x80000013`
| "Fast interrupt 4" | `0x80000014`
| "Fast interrupt 5" | `0x80000015`
| "Fast interrupt 6" | `0x80000016`
| "Fast interrupt 7" | `0x80000017`
| "Fast interrupt 8" | `0x80000018`
| "Fast interrupt 9" | `0x80000019`
| "Fast interrupt a" | `0x8000001a`
| "Fast interrupt b" | `0x8000001b`
| "Fast interrupt c" | `0x8000001c`
| "Fast interrupt d" | `0x8000001d`
| "Fast interrupt e" | `0x8000001e`
| "Fast interrupt f" | `0x8000001f`
| "Unknown trap cause" | _not defined_
|=======================
 
===== Bus Access Faults
 
For bus access faults the RTE default trap handlers also output the error code from the
<<_internal_bus_monitor_buskeeper>> to show the cause of the bus fault. One example is shown below.
 
.RTE Default Trap Handler Output Example (Load Access Bus Fault)
[source]
----
<RTE> Load access fault [TIMEOUT_ERR] @ PC=0x00000150, MTVAL=0xFFFFFF70 </RTE>
----
 
The additional message encapsulated in `[ ]` shows the actual cause of the bus access fault.
Three different messages are possible here:
 
* `[TIMEOUT_ERR]`: The accessed memory-mapped module did not respond within the valid access time window.
In Most cases this is caused by accessing a module that has not been implemented or when accessing
"address space holes" (unused/unmapped addresses).
* `[DEVICE_ERR]`: The accesses memory-mapped module asserted it's error signal to indicate an invalid access.
For example this can be caused by trying to write to read-only registers or by writing data quantities (like a byte)
to devices that do not support sub-word write accesses.
* `[PMP_ERR]`: This indicates an access right violation caused by the <<_pmp_physical_memory_protection>>.
/neorv32/trunk/docs/figures/cfu_r2type_instruction.png Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/neorv32/trunk/docs/figures/cfu_r2type_instruction.png
neorv32/trunk/docs/figures/cfu_r2type_instruction.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: neorv32/trunk/docs/figures/license.md =================================================================== --- neorv32/trunk/docs/figures/license.md (revision 71) +++ neorv32/trunk/docs/figures/license.md (revision 72) @@ -1,6 +1,6 @@ # :copyright: -Figures are own work if not otherwise stated. License: https://github.com/stnolting/neorv32/blob/master/LICENSE +Figures are own work if not otherwise stated. License: https://github.com/stnolting/neorv32/blob/main/LICENSE No copyright infringement intended.
/neorv32/trunk/docs/figures/neorv32_cpu.png Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/neorv32/trunk/docs/figures/neorv32_cpu_block.png Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/neorv32/trunk/docs/figures/neorv32_cpu_block.png
neorv32/trunk/docs/figures/neorv32_cpu_block.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: neorv32/trunk/docs/figures/neorv32_ocd_complex.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: neorv32/trunk/docs/figures/neorv32_processor.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: neorv32/trunk/docs/figures/ram_layout.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: neorv32/trunk/docs/figures/ram_layout.png =================================================================== --- neorv32/trunk/docs/figures/ram_layout.png (nonexistent) +++ neorv32/trunk/docs/figures/ram_layout.png (revision 72)
neorv32/trunk/docs/figures/ram_layout.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: neorv32/trunk/docs/userguide/adding_custom_hw_modules.adoc =================================================================== --- neorv32/trunk/docs/userguide/adding_custom_hw_modules.adoc (revision 71) +++ neorv32/trunk/docs/userguide/adding_custom_hw_modules.adoc (revision 72) @@ -4,8 +4,16 @@ In resemblance to the RISC-V ISA, the NEORV32 processor was designed to ease customization and _extensibility_. The processor provides several predefined options to add application-specific custom hardware modules and accelerators. +A <<_comparative_summary>> is given at the end of this section. +.Debugging/Testing Custom Hardware Modules +[TIP] +Custom hardware IP modules connected via the external bus interface or integrated as CFU can be debugged "in-system" using the +"bus explorer" example program (`sw/example_bus_explorer`). This program provides an interactive console (via UART0) +that allows to perform arbitrary read and write access from/to any memory-mapped register. + + === Standard (_External_) Interfaces The processor already provides a set of standard interfaces that are intended to connect _chip-external_ devices. @@ -15,47 +23,94 @@ https://stnolting.github.io/neorv32/#_serial_peripheral_interface_controller_spi[SPI] and https://stnolting.github.io/neorv32/#_two_wire_serial_interface_controller_twi[TWI]. -The SPI and (especially) the GPIO interfaces might be the most straightforward approaches since they -have a minimal protocol overhead. Device-specific interrupt capabilities can be added using the +The SPI and especially the GPIO interfaces might be the most straightforward approaches since they +have a minimal protocol overhead. Device-specific interrupt capabilities could be added using the https://stnolting.github.io/neorv32/#_external_interrupt_controller_xirq[External Interrupt Controller (XIRQ)]. + Beyond simplicity, these interface only provide a very limited bandwidth and require more sophisticated -software handling ("bit-banging" for the GPIO). +software handling ("bit-banging" for the GPIO). Hence, i is not recommend to use them for _chip-internal_ communication. === External Bus Interface The https://stnolting.github.io/neorv32/#_processor_external_memory_interface_wishbone_axi4_lite[External Bus Interface] -provides the classic approach to connect to custom IP. By default, the bus interface implements the widely adopted -Wishbone interface standard. However, this project also includes wrappers to bridge to other protocol standards like ARM's -AXI4-Lite or Intel's Avalon. By using a full-featured bus protocol, complex SoC structures can be implemented (including -several modules and even multi-core architectures). Many FPGA EDA tools provide graphical editors to build and customize -whole SoC architectures and even include pre-defined IP libraries. +provides the classic approach for attaching custom IP. By default, the bus interface implements the widely adopted +Wishbone interface standard. This project also includes wrappers to convert to other protocol standards like ARM's +AXI4-Lite or Intel's Avalon protocols. By using a full-featured bus protocol, complex SoC designs can be implemented +including several modules and even multi-core architectures. Many FPGA EDA tools provide graphical editors to build +and customize whole SoC architectures and even include pre-defined IP libraries. .Example AXI SoC using Xilinx Vivado image::neorv32_axi_soc.png[] +Custom hardware modules attached to the processor's bus interface have no limitations regarding their functionality. +User-defined interfaces (like DDR memory access) can be implemented and the hardware module can operate completely +independent of the CPU. + The bus interface uses a memory-mapped approach. All data transfers are handled by simple load/store operations since the external bus interface is mapped into the processor's https://stnolting.github.io/neorv32/#_address_space[address space]. -This allows a very simple still high-bandwidth communications. +This allows a very simple still high-bandwidth communications. However, high bus traffic may increase access latencies. === Stream Link Interface -The NEORV32 https://stnolting.github.io/neorv32/#_stream_link_interface_slink[Stream Link Interface] provides -point-to-point, unidirectional and parallel data channels that can be used to transfer streaming data. In -contrast to the external bus interface, the streaming data does not provide any kind of "direction" control, -so it can be seen as "constant address bursts". The stream link interface provides less protocol overhead -and less latency than the bus interface. Furthermore, FIFOs can be be configured to each direction (RX/TX) to -allow more CPU-independent operation. +The https://stnolting.github.io/neorv32/#_stream_link_interface_slink[Stream Link Interface (SLINK)] provides a +point-to-point, unidirectional and parallel data interface that can be used to transfer _streaming_ data. In +contrast to the external bus interface, the streaming interface does not provide any kind of advanced control, +so it can be seen as "constant address bursts" where data is transmitted _sequentially_ (no random accesses). +While the CPU needs to "feed" the stream link interfaces with data (and read back incoming data), the actual +processor-external processing of the data run independently of the CPU. +The stream link interface provides less protocol overhead and less latency than the bus interface. Furthermore, +FIFOs can be be configured to each direction (RX/TX) to allow more CPU-independent operation. + === Custom Functions Subsystem -The NEORV32 https://stnolting.github.io/neorv32/#_custom_functions_subsystem_cfs[Custom Functions Subsystem] is -an "empty" template for a processor-internal module. It provides 32 32-bit memory-mapped interface -registers that can be used to communicate with any arbitrary custom design logic. The intentions of this -subsystem is to provide a simple base, where the user can concentrate on implementing the actual design logic -rather than taking care of the communication between the CPU/software and the design logic. The interface -registers are already allocated within the processor's address space and are supported by the software framework -via low-level hardware access mechanisms. Additionally, the CFS provides a direct pre-defined interrupt channel to -the CPU, which is also supported by the NEORV32 runtime environment. +The https://stnolting.github.io/neorv32/#_custom_functions_subsystem_cfs[Custom Functions Subsystem (CFS)] is +an "empty" template for a memory-mapped, processor-internal module. + +The basic idea of this subsystem is to provide a convenient, simple and flexible platform, where the user can +concentrate on implementing the actual design logic rather than taking care of the communication between the +CPU/software and the design logic. Note that the CFS does not have direct access to memory. All data (and control +instruction) have to be send by the CPU. + +The use-cases for the CFS include medium-scale hardware accelerators that need to be tightly-coupled to the CPU. +Potential use cases could be DSP modules like CORDIC, cryptographic accelerators or custom interfaces (like IIS). + + +=== Custom Functions Unit + +The https://stnolting.github.io/neorv32/#_custom_functions_unit_cfu[Custom Functions Unit (CFU)] is a functional +unit that is integrated right into the CPU's pipeline. It allows to implement custom RISC-V instructions. +This extension option is intended for rather small logic that implements operations, which cannot be emulated +in pure software in an efficient way. Since the CFU has direct access to the core's register file it can operate +with minimal data latency. + + +=== Comparative Summary + +The following table gives a comparative summary of the most important factors when choosing one of the +chip-internal extension options: + +* https://stnolting.github.io/neorv32/#_custom_functions_unit_cfu[Custom Functions Unit] for CPU-internal custom RISC-V instructions +* https://stnolting.github.io/neorv32/#_custom_functions_subsystem_cfs[Custom Functions Subsystem] for tightly-coupled processor-internal co-processors +* https://stnolting.github.io/neorv32/#_stream_link_interface_slink[Stream Link Interface] for processor-external streaming modules +* https://stnolting.github.io/neorv32/#_processor_external_memory_interface_wishbone_axi4_lite[External Bus Interface] for processor-external memory-mapped modules + +.Comparison of On-Chip Extension Options +[cols="<1,^1,^1,^1,^1"] +[options="header",grid="rows"] +|======================= +| | Custom Functions Unit | Custom Functions Subsystem | Stream Link Interface | External Bus Interface +| **SoC location** | CPU-internal | processor-internal | processor-external | processor-external +| **HW complexity/size** | small | medium | unlimited | unlimited +| **CPU-independent operation** | no | partly | partly | completely +| **CPU interface** | register-file access | memory-mapped | memory-mapped | memory-mapped +| **Low-level CPU access scheme** | custom instructions | load/store | load/store | load/store +| **Random access** | - | yes | no, only sequential | yes +| **Access latency** | minimal | low | low | medium to high +| **External IO interfaces** | no | yes, but limited | yes | yes +| **Interrupt-capable** | no | yes | yes | user-defined +|======================= +
/neorv32/trunk/docs/userguide/debugging_with_ocd.adoc
4,27 → 4,27
 
The NEORV32 on-chip debugger allows _online_ in-system debugging via an external JTAG access port from a
host machine. The general flow is independent of the host machine's operating system. However, this tutorial uses
Windows and Linux (Ubuntu on Windows) in parallel.
Windows and Linux (Ubuntu on Windows / WSL) in parallel running the upstream version of OpenOCD and the
RISC-V _GNU debugger_ `gdb`.
 
[TIP]
[NOTE]
See datasheet section https://stnolting.github.io/neorv32/#_on_chip_debugger_ocd[On Chip Debugger (OCD)]
for more information.
for more information regarding the actual hardware.
 
[NOTE]
This tutorial uses `gdb` to **directly upload an executable** to the processor. If you are using the default
processor setup _with_ internal instruction memory (IMEM) make sure it is implemented as RAM
(_INT_BOOTLOADER_EN_ generic = true).
 
[IMPORTANT]
The on-chip debugger is only implemented if the _ON_CHIP_DEBUGGER_EN_ generic is set _true_. Furthermore, it requires
the `Zicsr` and `Zifencei` CPU extension to be implemented (top generics _CPU_EXTENSION_RISCV_Zicsr_
and _CPU_EXTENSION_RISCV_Zifencei_ = true).
the `Zicsr` and `Zifencei` CPU extension to be implemented (top generics _CPU_EXTENSION_RISCV_Zicsr_ = _true_
and _CPU_EXTENSION_RISCV_Zifencei_ = _true_).
 
 
:sectnums:
=== Hardware Requirements
 
Make sure the on-chip debugger of your NEORV32 setups is implemented (_ON_CHIP_DEBUGGER_EN_ generic = true).
Make sure the on-chip debugger of your NEORV32 setup is implemented (_ON_CHIP_DEBUGGER_EN_ generic = true). This
tutorial uses `gdb` to **directly upload an executable** to the processor. If you are using the default
processor setup _with_ internal instruction memory (IMEM) make sure it is implemented as RAM
(_INT_BOOTLOADER_EN_ generic = true).
 
Connect a JTAG adapter to the NEORV32 `jtag_*` interface signals. If you do not have a full-scale JTAG adapter, you can
also use a FTDI-based adapter like the "FT2232H-56Q Mini Module", which is a simple and inexpensive FTDI breakout board.
 
41,19 → 41,18
|=======================
 
[TIP]
The low-active JTAG _test reset_ (TRST) signals is _optional_ as a reset can also be triggered via the TAP controller.
If TRST is not used make sure to pull the signal _high_.
The low-active JTAG tap reset `jtag_trst_i` signals is _optional_ as a reset can also be triggered via the TAP controller
issuing special commands. If `jtag_trst_i` is not connected make sure to pull the signal _high_.
 
 
:sectnums:
=== OpenOCD
 
The NEORV32 on-chip debugger can be accessed using the https://github.com/riscv/riscv-openocd[RISC-V port of OpenOCD].
Prebuilt binaries can be obtained - for example - from https://www.sifive.com/software[SiFive]. A pre-configured
OpenOCD configuration file (`sw/openocd/openocd_neorv32.cfg`) is available that allows easy access to the NEORV32 CPU.
The NEORV32 on-chip debugger can be accessed using the upstream version of OpenOCD. A pre-configured OpenOCD configuration
file is provided (`sw/openocd/openocd_neorv32.cfg`) that allows an easy access to the NEORV32 CPU.
 
[NOTE]
You might need to adapt `ftdi_vid_pid`, `ftdi_channel` and `ftdi_layout_init` in `sw/openocd/openocd_neorv32.cfg`
You might need to adapt `ftdi vid_pid`, `ftdi channel` and `ftdi layout_init` in `sw/openocd/openocd_neorv32.cfg`
according to your interface chip and your operating system.
 
[TIP]
62,29 → 61,31
 
To access the processor using OpenOCD, open a terminal and start OpenOCD with the pre-configured configuration file.
 
.Connecting via OpenOCD (on Windows)
.Connecting via OpenOCD (on Windows) using the default `openocd_neorv32.cfg` script
[source, bash]
--------------------------
N:\Projects\neorv32\sw\openocd>openocd -f openocd_neorv32.cfg
Open On-Chip Debugger 0.11.0-rc1+dev (SiFive OpenOCD 0.10.0-2020.12.1)
Open On-Chip Debugger 0.11.0 (2021-11-18) [https://github.com/sysprogs/openocd]
Licensed under GNU GPL v2
For bug reports:
https://github.com/sifive/freedom-tools/issues
1
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
libusb1 09e75e98b4d9ea7909e8837b7a3f00dda4589dc3
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
Info : clock speed 1000 kHz
Info : JTAG tap: neorv32.cpu tap/device found: 0x0cafe001 (mfg: 0x000 (<invalid>), part: 0xcafe, ver: 0x0)
Info : datacount=1 progbufsize=2
Info : Disabling abstract command reads from CSRs.
Info : Examined RISC-V core; found 1 harts
Info : hart 0: XLEN=32, misa=0x40801105
Info : hart 0: XLEN=32, misa=0x40901107
Info : starting gdb server for neorv32.cpu.0 on 3333
Info : Listening on port 3333 for gdb connections
Target HALTED.
Ready for remote connections.
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
--------------------------
 
OpenOCD has successfully connected to the NEORV32 on-chip debugger and has examined the CPU (showing the content of
the `misa` CSRs). Now you can use `gdb` to connect via port 3333.
the `misa` CSRs). The processor is halted and OpenOCD waits fot `gdb` to connect via port 3333.
 
 
:sectnums:
106,7 → 107,7
.Adding debug symbols to the executable
[NOTE]
`USER_FLAGS+=-g` passes the `-g` flag to the compiler so it adds debug information/symbols
to the generated ELF file. This is optional but will provide more sophisticated information for debugging
to the generated ELF file. This is optional but will provide more sophisticated debugging information
(like source file line numbers).
 
This will generate an ELF file `main.elf` that contains all the symbols required for debugging.
176,7 → 177,7
 
 
:sectnums:
==== Breakpoint Example
==== Software Breakpoints
 
The following steps are just a small showcase that illustrate a simple debugging scheme.
 
204,22 → 205,26
The address might be different if you use a different version of the software framework or
if different ISA options are configured.
 
.Adding a GDB breakpoint
.Adding a GDB software breakpoint
[source, bash]
--------------------------
(gdb) b * 0x690
(gdb) b * 0x690 <1>
Breakpoint 1 at 0x690
--------------------------
<1> `b` is an alias for `break`, which adds a _software_ breakpoint.
 
.How do breakpoints work?
.How do _software_ breakpoints work?
[TIP]
The NEORV32 on-chip debugger does not provide any hardware breakpoints (RISC-V "trigger modules") that compare an address like the PC
with a predefined value. Instead, gdb will modify the actual executable in IMEM: the actual instruction at the address
of the specified breakpoint is replaced by a `break` / `c.break` instruction. Whenever execution reaches this instruction, debug mode is
re-entered and the debugger restores the original instruction at this address to maintain original program behavior.
Software breakpoints are used for debugging programs that are accessed from read/write memory (RAM) like IMEM. The debugger
temporarily replaces the instruction word of the instruction, where the breakpoint shall be inserted, by a `ebreak` / `c.ebreak`
instruction. Whenever execution reaches this instruction, debug mode is entered and the debugger restores the original
instruction at this address to maintain original program behavior. +
+
When debugging programs executed from ROM _hardware-assisted_ breakpoints using the core's trigger module have to be used.
See section <<_hardware_breakpoints>> for more information.
 
Now execute `c` (= continue). The CPU will resume operation until it hits the break-point.
By this we can "step" from increment to increment.
By this we can move from one counter increment to another.
 
.Iterating from breakpoint to breakpoint
[source, bash]
236,3 → 241,31
(gdb) c
Continuing.
--------------------------
 
.BREAK instructions in your program code
[TIP]
If your original application code uses the BREAK instruction (for example for some OS calls/signaling) this
instruction will cause an enter to debug mode when executed. These situation cannot be continued using gdb's
`c` command and have to be "stepped-over" using the single-step command `s`.
 
 
:sectnums:
==== Hardware Breakpoints
 
Hardware-assisted breakpoints using the CPU's trigger module are required when debugging code that is executed from
read-only memory (ROM) as GDB cannot temporarily replace instructions by BREAK instructions.
 
From a user point of view hardware breakpoints behave like software breakpoints. GDB provides a command to setup
a hardware-assisted breakpoint:
 
.Adding a GDB hardware breakpoint
[source, bash]
--------------------------
(gdb) hb * 0x690 <1>
Breakpoint 1 at 0x690
--------------------------
<1> `hb` is an alias for `hbreak`, which adds a _hardware_ breakpoint.
 
[NOTE]
The CPU's trigger module only provides a single _instruction address match_ type trigger. Hence, only
a single `hb` hardware-assisted breakpoint can be used.
/neorv32/trunk/docs/userguide/executable_upload.adoc
16,8 → 16,8
[start=1]
. Connect the primary UART (UART0) interface of your FPGA board to a serial port of your host computer.
. Start a terminal program. In this tutorial, I am using TeraTerm for Windows. You can download it for free
from https://ttssh2.osdn.jp/index.html.en . On Linux you could use GTKTerm, which you can get here
https://github.com/Jeija/gtkterm.git (or install via your package manager).
from https://ttssh2.osdn.jp/index.html.en . On Linux you could use `cutecom` (recommended) or `GTKTerm`,
which you can get here https://github.com/Jeija/gtkterm.git (or install via your package manager).
 
[IMPORTANT]
_Any_ terminal program that can connect to a serial port should work. However, make sure the program
49,25 → 49,24
----
<< NEORV32 Bootloader >>
 
BLDV: Mar 23 2021
HWV: 0x01050208
CLK: 0x05F5E100
MISA: 0x40901105
ZEXT: 0x00000023
PROC: 0x0EFF0037
IMEM: 0x00004000 bytes @ 0x00000000
DMEM: 0x00002000 bytes @ 0x80000000
BLDV: Feb 16 2022
HWV: 0x01060709
CLK: 0x05f5e100
ISA: 0x40901107 + 0xc000068b
SOC: 0x7b7f402f
IMEM: 0x00008000 bytes @0x00000000
DMEM: 0x00004000 bytes @0x80000000
 
Autoboot in 8s. Press key to abort.
Autoboot in 8s. Press any key to abort.
Aborted.
 
Available commands:
h: Help
r: Restart
u: Upload
s: Store to flash
l: Load from flash
e: Execute
h: Help
r: Restart
u: Upload
s: Store to flash
l: Load from flash
e: Execute
CMD:>
----
 
/neorv32/trunk/docs/userguide/general_hw_setup.adoc
12,7 → 12,7
`setups` folder, which provides example setups for various FPGA, boards and toolchains.
 
The NEORV32 project features two minimalistic pre-configured test setups in
https://github.com/stnolting/neorv32/blob/master/rtl/test_setups[`rtl/test_setups`].
https://github.com/stnolting/neorv32/blob/main/rtl/test_setups[`rtl/test_setups`].
Both test setups only implement very basic processor and CPU features.
The main difference between the two setups is the processor boot concept - so how to get a software executable
_into_ the processor:
/neorv32/trunk/docs/userguide/index.adoc
13,7 → 13,7
 
[.text-center]
https://github.com/stnolting/neorv32[image:https://img.shields.io/badge/GitHub-stnolting%2Fneorv32-ffbd00?style=flat-square&logo=github&[title='homepage']]
https://github.com/stnolting/neorv32/blob/master/LICENSE[image:https://img.shields.io/github/license/stnolting/neorv32?longCache=true&style=flat-square[title='license']]
https://github.com/stnolting/neorv32/blob/main/LICENSE[image:https://img.shields.io/github/license/stnolting/neorv32?longCache=true&style=flat-square[title='license']]
https://gitter.im/neorv32/community[image:https://img.shields.io/badge/Chat-on%20gitter-4db797.svg?longCache=true&style=flat-square&logo=gitter&logoColor=e8ecef[title='chat on gitter']]
https://github.com/stnolting/neorv32/releases/tag/nightly[image:https://img.shields.io/badge/data%20sheet-PDF-ffbd00?longCache=true&style=flat-square&logo=asciidoctor[title='datasheet (pdf)']]
https://stnolting.github.io/neorv32[image:https://img.shields.io/badge/-HTML-ffbd00?longCache=true&style=flat-square[title='datasheet (html)']]
/neorv32/trunk/docs/userguide/riscv_architecture_tests.adoc
8,5 → 8,5
All files required for executing the test framework on a simulated instance of the processor (including port
files) are located in the `sw/isa-test` folder of the NEORV32 repository. The test framework is executed via the
`sim/run_riscv_arch_test.sh` script. Take a look at the provided `sim/README.md`
(https://github.com/stnolting/neorv32/tree/master/sim[online at GitHub])
(https://github.com/stnolting/neorv32/tree/main/sim[online at GitHub])
file for more information on how to run the tests and how testing is conducted in detail.
/neorv32/trunk/docs/userguide/sw_toolchain_setup.adoc
34,7 → 34,10
compressed (`C`) and `mul`/`div` instructions (`M`)! Hence, this code cannot be executed (without
emulation) on an architecture without these extensions!
 
[IMPORTANT]
Make sure to use "newlib" as C standard library as the NEORV32 has no native support for Linus-like operating systems.
 
 
:sectnums:
=== Downloading and Installing a Prebuilt Toolchain
 
/neorv32/trunk/docs/README.md
1,29 → 1,29
## Project Documentation
 
 
### [`datasheet`](https://github.com/stnolting/neorv32/tree/master/docs/datasheet)
### [`datasheet`](https://github.com/stnolting/neorv32/tree/main/docs/datasheet)
 
AsciiDoc sources for the NEORV32 data sheet. The online version of the data sheet is
available at [https://stnolting.github.io/neorv32](https://stnolting.github.io/neorv32).
 
 
### [`figures`](https://github.com/stnolting/neorv32/tree/master/docs/figures`)
### [`figures`](https://github.com/stnolting/neorv32/tree/main/docs/figures`)
 
Figures and images used by the data sheet, user guide and the webpage(s). The according
license(s) are listed in [`figures/license.md`](https://github.com/stnolting/neorv32/blob/master/docs/figures/license.md).
license(s) are listed in [`figures/license.md`](https://github.com/stnolting/neorv32/blob/main/docs/figures/license.md).
 
 
### [`icons`](https://github.com/stnolting/neorv32/tree/master/docs/icons`)
### [`icons`](https://github.com/stnolting/neorv32/tree/main/docs/icons`)
 
Icons used by the data sheet and the user guide.
 
 
### [`references`](https://github.com/stnolting/neorv32/tree/master/docs/references`)
### [`references`](https://github.com/stnolting/neorv32/tree/main/docs/references`)
 
Reference material like RISC-V and Wishbone specifications.
 
 
### [`userguide`](https://github.com/stnolting/neorv32/tree/master/docs/userguide)
### [`userguide`](https://github.com/stnolting/neorv32/tree/main/docs/userguide)
 
AsciiDoc sources for the NEORV32 user guide. The online version of the user guide is
available at [https://stnolting.github.io/neorv32/ug](https://stnolting.github.io/neorv32/ug).
/neorv32/trunk/docs/attrs.adoc
2,7 → 2,7
:email: stnolting@gmail.com
:keywords: neorv32, risc-v, riscv, fpga, soft-core, vhdl, microcontroller, cpu, soc, processor, gcc, openocd, gdb
:description: A size-optimized, customizable and open-source full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.
:revnumber: v1.6.7
:revnumber: v1.6.8
:doctype: book
:sectnums:
:stem:
/neorv32/trunk/docs/legal.adoc
127,4 → 127,4
 
=== Impressum (Imprint)
 
See https://github.com/stnolting/neorv32/blob/master/docs/impressum.md[`docs/impressum.md`].
See https://github.com/stnolting/neorv32/blob/main/docs/impressum.md[`docs/impressum.md`].
/neorv32/trunk/rtl/core/mem/neorv32_imem.default.vhd
6,7 → 6,7
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
166,8 → 166,10
rden <= acc_en and rden_i;
if (IMEM_AS_IROM = true) then
ack_o <= acc_en and rden_i;
err_o <= acc_en and wren_i;
else
ack_o <= acc_en and (rden_i or wren_i);
err_o <= '0';
end if;
end if;
end process bus_feedback;
/neorv32/trunk/rtl/core/mem/neorv32_imem.legacy.vhd
6,7 → 6,7
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
163,8 → 163,10
rden <= acc_en and rden_i;
if (IMEM_AS_IROM = true) then
ack_o <= acc_en and rden_i;
err_o <= acc_en and wren_i;
else
ack_o <= acc_en and (rden_i or wren_i);
err_o <= '0';
end if;
end if;
end process bus_feedback;
/neorv32/trunk/rtl/core/neorv32_application_image.vhd
1,6 → 1,6
-- The NEORV32 RISC-V Processor, https://github.com/stnolting/neorv32
-- Auto-generated memory init file (for APPLICATION) from source file <blink_led/main.bin>
-- Size: 3424 bytes
-- Size: 3400 bytes
 
library ieee;
use ieee.std_logic_1164.all;
67,7 → 67,7
00000053 => x"00158593",
00000054 => x"ff5ff06f",
00000055 => x"00001597",
00000056 => x"c8458593",
00000056 => x"c6c58593",
00000057 => x"80000617",
00000058 => x"f1c60613",
00000059 => x"80000697",
113,17 → 113,17
00000099 => x"00000593",
00000100 => x"b0050513",
00000101 => x"00112623",
00000102 => x"088000ef",
00000103 => x"750000ef",
00000102 => x"57c000ef",
00000103 => x"694000ef",
00000104 => x"00050c63",
00000105 => x"6fc000ef",
00000105 => x"500000ef",
00000106 => x"00001537",
00000107 => x"a9850513",
00000108 => x"134000ef",
00000107 => x"a8050513",
00000108 => x"628000ef",
00000109 => x"020000ef",
00000110 => x"00001537",
00000111 => x"a7450513",
00000112 => x"124000ef",
00000111 => x"a5c50513",
00000112 => x"618000ef",
00000113 => x"00c12083",
00000114 => x"00100513",
00000115 => x"01010113",
133,740 → 133,734
00000119 => x"00000593",
00000120 => x"00112623",
00000121 => x"00812423",
00000122 => x"714000ef",
00000122 => x"658000ef",
00000123 => x"00000513",
00000124 => x"00150413",
00000125 => x"00000593",
00000126 => x"0ff57513",
00000127 => x"700000ef",
00000127 => x"644000ef",
00000128 => x"0c800513",
00000129 => x"14c000ef",
00000129 => x"64c000ef",
00000130 => x"00040513",
00000131 => x"fe5ff06f",
00000132 => x"fe802503",
00000133 => x"01255513",
00000134 => x"00157513",
00000135 => x"00008067",
00000136 => x"ff010113",
00000137 => x"00812423",
00000138 => x"00912223",
00000139 => x"00112623",
00000140 => x"fa002023",
00000141 => x"fe002783",
00000142 => x"00058413",
00000143 => x"00151593",
00000144 => x"00078513",
00000145 => x"00060493",
00000146 => x"780000ef",
00000147 => x"01051513",
00000148 => x"000017b7",
00000149 => x"01055513",
00000150 => x"00000713",
00000151 => x"ffe78793",
00000152 => x"04a7e463",
00000153 => x"0034f793",
00000154 => x"00347413",
00000155 => x"fff50513",
00000156 => x"01479793",
00000157 => x"01641413",
00000158 => x"00f567b3",
00000159 => x"0087e7b3",
00000160 => x"01871713",
00000161 => x"00c12083",
00000162 => x"00812403",
00000163 => x"00e7e7b3",
00000164 => x"10000737",
00000165 => x"00e7e7b3",
00000166 => x"faf02023",
00000167 => x"00412483",
00000168 => x"01010113",
00000169 => x"00008067",
00000170 => x"ffe70693",
00000171 => x"0fd6f693",
00000172 => x"00069a63",
00000173 => x"00355513",
00000174 => x"00170713",
00000175 => x"0ff77713",
00000176 => x"fa1ff06f",
00000177 => x"00155513",
00000178 => x"ff1ff06f",
00000179 => x"00040737",
00000180 => x"fa002783",
00000181 => x"00e7f7b3",
00000182 => x"fe079ce3",
00000183 => x"faa02223",
00000184 => x"00008067",
00000185 => x"ff010113",
00000186 => x"00812423",
00000187 => x"01212023",
00000188 => x"00112623",
00000189 => x"00912223",
00000190 => x"00050413",
00000191 => x"00a00913",
00000192 => x"00044483",
00000193 => x"00140413",
00000194 => x"00049e63",
00000195 => x"00c12083",
00000196 => x"00812403",
00000197 => x"00412483",
00000198 => x"00012903",
00000199 => x"01010113",
00000200 => x"00008067",
00000201 => x"01249663",
00000202 => x"00d00513",
00000203 => x"fa1ff0ef",
00000204 => x"00048513",
00000205 => x"f99ff0ef",
00000206 => x"fc9ff06f",
00000207 => x"c81027f3",
00000208 => x"c0102573",
00000209 => x"c81025f3",
00000210 => x"fef59ae3",
00000211 => x"00008067",
00000212 => x"fd010113",
00000213 => x"00a12623",
00000214 => x"fe002503",
00000215 => x"3e800593",
00000216 => x"02112623",
00000217 => x"02812423",
00000218 => x"02912223",
00000219 => x"03212023",
00000220 => x"01312e23",
00000221 => x"654000ef",
00000222 => x"00c12603",
00000223 => x"00000693",
00000224 => x"00000593",
00000225 => x"5ac000ef",
00000226 => x"00050413",
00000227 => x"00058993",
00000228 => x"fadff0ef",
00000229 => x"00058913",
00000230 => x"00050493",
00000231 => x"fa1ff0ef",
00000232 => x"00b96663",
00000233 => x"05259263",
00000234 => x"04a4f063",
00000235 => x"008484b3",
00000236 => x"0084b433",
00000237 => x"01390933",
00000238 => x"01240433",
00000239 => x"f81ff0ef",
00000240 => x"fe85eee3",
00000241 => x"00b41463",
00000242 => x"fe956ae3",
00000243 => x"02c12083",
00000244 => x"02812403",
00000245 => x"02412483",
00000246 => x"02012903",
00000247 => x"01c12983",
00000248 => x"03010113",
00000249 => x"00008067",
00000250 => x"01c99913",
00000251 => x"00445413",
00000252 => x"00896433",
00000253 => x"00040a63",
00000254 => x"00040863",
00000255 => x"fff40413",
00000256 => x"00000013",
00000257 => x"ff1ff06f",
00000258 => x"fc5ff06f",
00000259 => x"fc010113",
00000260 => x"02112e23",
00000261 => x"02512c23",
00000262 => x"02612a23",
00000263 => x"02712823",
00000264 => x"02a12623",
00000265 => x"02b12423",
00000266 => x"02c12223",
00000267 => x"02d12023",
00000268 => x"00e12e23",
00000269 => x"00f12c23",
00000270 => x"01012a23",
00000271 => x"01112823",
00000272 => x"01c12623",
00000273 => x"01d12423",
00000274 => x"01e12223",
00000275 => x"01f12023",
00000276 => x"34102773",
00000277 => x"34071073",
00000278 => x"342027f3",
00000279 => x"0407c463",
00000280 => x"00071683",
00000281 => x"00300593",
00000282 => x"0036f693",
00000283 => x"00270613",
00000284 => x"00b69463",
00000285 => x"00470613",
00000286 => x"34161073",
00000287 => x"00b00713",
00000288 => x"00f77663",
00000289 => x"67800793",
00000290 => x"0500006f",
00000291 => x"00001737",
00000292 => x"00279793",
00000293 => x"ab470713",
00000294 => x"00e787b3",
00000295 => x"0007a783",
00000296 => x"00078067",
00000297 => x"80000737",
00000298 => x"ffd74713",
00000299 => x"00e787b3",
00000300 => x"01c00713",
00000301 => x"fcf768e3",
00000302 => x"00001737",
00000303 => x"00279793",
00000304 => x"ae470713",
00000305 => x"00e787b3",
00000306 => x"0007a783",
00000307 => x"00078067",
00000308 => x"800007b7",
00000309 => x"0007a783",
00000310 => x"000780e7",
00000311 => x"03c12083",
00000312 => x"03812283",
00000313 => x"03412303",
00000314 => x"03012383",
00000315 => x"02c12503",
00000316 => x"02812583",
00000317 => x"02412603",
00000318 => x"02012683",
00000319 => x"01c12703",
00000320 => x"01812783",
00000321 => x"01412803",
00000322 => x"01012883",
00000323 => x"00c12e03",
00000324 => x"00812e83",
00000325 => x"00412f03",
00000326 => x"00012f83",
00000327 => x"04010113",
00000328 => x"30200073",
00000329 => x"800007b7",
00000330 => x"0047a783",
00000331 => x"fadff06f",
00000332 => x"8081a783",
00000333 => x"fa5ff06f",
00000334 => x"80c1a783",
00000335 => x"f9dff06f",
00000336 => x"8101a783",
00000337 => x"f95ff06f",
00000338 => x"8141a783",
00000339 => x"f8dff06f",
00000340 => x"8181a783",
00000341 => x"f85ff06f",
00000342 => x"81c1a783",
00000343 => x"f7dff06f",
00000344 => x"8201a783",
00000345 => x"f75ff06f",
00000346 => x"8241a783",
00000347 => x"f6dff06f",
00000348 => x"8281a783",
00000349 => x"f65ff06f",
00000350 => x"82c1a783",
00000351 => x"f5dff06f",
00000352 => x"8301a783",
00000353 => x"f55ff06f",
00000354 => x"8341a783",
00000355 => x"f4dff06f",
00000356 => x"8381a783",
00000357 => x"f45ff06f",
00000358 => x"83c1a783",
00000359 => x"f3dff06f",
00000360 => x"8401a783",
00000361 => x"f35ff06f",
00000362 => x"8441a783",
00000363 => x"f2dff06f",
00000364 => x"8481a783",
00000365 => x"f25ff06f",
00000366 => x"84c1a783",
00000367 => x"f1dff06f",
00000368 => x"8501a783",
00000369 => x"f15ff06f",
00000370 => x"8541a783",
00000371 => x"f0dff06f",
00000372 => x"8581a783",
00000373 => x"f05ff06f",
00000374 => x"85c1a783",
00000375 => x"efdff06f",
00000376 => x"8601a783",
00000377 => x"ef5ff06f",
00000378 => x"8641a783",
00000379 => x"eedff06f",
00000380 => x"8681a783",
00000381 => x"ee5ff06f",
00000382 => x"86c1a783",
00000383 => x"eddff06f",
00000384 => x"8701a783",
00000385 => x"ed5ff06f",
00000386 => x"fe010113",
00000387 => x"01212823",
00000388 => x"00050913",
00000389 => x"00001537",
00000390 => x"00912a23",
00000391 => x"b5850513",
00000392 => x"000014b7",
00000393 => x"00812c23",
00000394 => x"01312623",
00000395 => x"00112e23",
00000396 => x"01c00413",
00000397 => x"cb1ff0ef",
00000398 => x"d5048493",
00000399 => x"ffc00993",
00000400 => x"008957b3",
00000401 => x"00f7f793",
00000402 => x"00f487b3",
00000403 => x"0007c503",
00000404 => x"ffc40413",
00000405 => x"c79ff0ef",
00000406 => x"ff3414e3",
00000407 => x"01c12083",
00000408 => x"01812403",
00000409 => x"01412483",
00000410 => x"01012903",
00000411 => x"00c12983",
00000412 => x"02010113",
00000413 => x"00008067",
00000414 => x"ff010113",
00000415 => x"00112623",
00000416 => x"00812423",
00000417 => x"00912223",
00000418 => x"b89ff0ef",
00000419 => x"1c050863",
00000420 => x"00001537",
00000421 => x"b5c50513",
00000422 => x"c4dff0ef",
00000423 => x"34202473",
00000424 => x"00900713",
00000425 => x"00f47793",
00000426 => x"03078493",
00000427 => x"00f77463",
00000428 => x"05778493",
00000429 => x"00b00793",
00000430 => x"0087ee63",
00000431 => x"00001737",
00000432 => x"00241793",
00000433 => x"d2070713",
00000434 => x"00e787b3",
00000435 => x"0007a783",
00000436 => x"00078067",
00000437 => x"800007b7",
00000438 => x"00b78713",
00000439 => x"14e40e63",
00000440 => x"02876a63",
00000441 => x"00378713",
00000442 => x"12e40c63",
00000443 => x"00778793",
00000444 => x"12f40e63",
00000445 => x"00001537",
00000446 => x"cbc50513",
00000447 => x"be9ff0ef",
00000448 => x"00040513",
00000449 => x"f05ff0ef",
00000450 => x"00100793",
00000451 => x"08f40c63",
00000452 => x"0280006f",
00000453 => x"ff07c793",
00000454 => x"00f407b3",
00000455 => x"00f00713",
00000456 => x"fcf76ae3",
00000457 => x"00001537",
00000458 => x"cac50513",
00000459 => x"bb9ff0ef",
00000460 => x"00048513",
00000461 => x"b99ff0ef",
00000462 => x"ffd47413",
00000463 => x"00500793",
00000464 => x"06f40263",
00000465 => x"00001537",
00000466 => x"d0050513",
00000467 => x"b99ff0ef",
00000468 => x"34002573",
00000469 => x"eb5ff0ef",
00000470 => x"00001537",
00000471 => x"d0850513",
00000472 => x"b85ff0ef",
00000473 => x"34302573",
00000474 => x"ea1ff0ef",
00000475 => x"00812403",
00000476 => x"00c12083",
00000477 => x"00412483",
00000478 => x"00001537",
00000479 => x"d1450513",
00000480 => x"01010113",
00000481 => x"b61ff06f",
00000482 => x"00001537",
00000483 => x"b6450513",
00000484 => x"b55ff0ef",
00000485 => x"fb1ff06f",
00000486 => x"00001537",
00000487 => x"b8450513",
00000488 => x"b45ff0ef",
00000489 => x"f7c02783",
00000490 => x"0a07d463",
00000491 => x"0017f793",
00000492 => x"08078a63",
00000493 => x"00001537",
00000494 => x"cd450513",
00000495 => x"fd5ff06f",
00000496 => x"00001537",
00000497 => x"ba050513",
00000498 => x"fc9ff06f",
00000499 => x"00001537",
00000500 => x"bb450513",
00000501 => x"fbdff06f",
00000502 => x"00001537",
00000503 => x"bc050513",
00000504 => x"fb1ff06f",
00000505 => x"00001537",
00000506 => x"bd850513",
00000507 => x"fb5ff06f",
00000508 => x"00001537",
00000509 => x"bec50513",
00000510 => x"f99ff06f",
00000511 => x"00001537",
00000512 => x"c0850513",
00000513 => x"f9dff06f",
00000514 => x"00001537",
00000515 => x"c1c50513",
00000516 => x"f81ff06f",
00000517 => x"00001537",
00000518 => x"c3c50513",
00000519 => x"f75ff06f",
00000520 => x"00001537",
00000521 => x"c5c50513",
00000522 => x"f69ff06f",
00000523 => x"00001537",
00000524 => x"c7850513",
00000525 => x"f5dff06f",
00000526 => x"00001537",
00000527 => x"c9050513",
00000528 => x"f51ff06f",
00000529 => x"00001537",
00000530 => x"ce450513",
00000531 => x"f45ff06f",
00000532 => x"00001537",
00000533 => x"cf450513",
00000534 => x"f39ff06f",
00000535 => x"00c12083",
00000536 => x"00812403",
00000537 => x"00412483",
00000538 => x"01010113",
00000539 => x"00008067",
00000540 => x"01f00793",
00000541 => x"02a7e263",
00000542 => x"800007b7",
00000543 => x"00078793",
00000544 => x"00251513",
00000545 => x"00a78533",
00000546 => x"67800793",
00000547 => x"00f52023",
00000548 => x"00000513",
00000549 => x"00008067",
00000550 => x"00100513",
00000551 => x"00008067",
00000552 => x"ff010113",
00000553 => x"00112623",
00000554 => x"00812423",
00000555 => x"00912223",
00000556 => x"40c00793",
00000557 => x"30579073",
00000558 => x"00000413",
00000559 => x"01d00493",
00000560 => x"00040513",
00000561 => x"00140413",
00000562 => x"0ff47413",
00000563 => x"fa5ff0ef",
00000564 => x"fe9418e3",
00000565 => x"00c12083",
00000566 => x"00812403",
00000567 => x"f6002e23",
00000568 => x"00412483",
00000569 => x"01010113",
00000570 => x"00008067",
00000571 => x"fe802503",
00000572 => x"01055513",
00000573 => x"00157513",
00000574 => x"00008067",
00000575 => x"fc000793",
00000576 => x"00a7a423",
00000577 => x"00b7a623",
00000578 => x"00008067",
00000579 => x"00050613",
00000580 => x"00000513",
00000581 => x"0015f693",
00000582 => x"00068463",
00000583 => x"00c50533",
00000584 => x"0015d593",
00000585 => x"00161613",
00000586 => x"fe0596e3",
00000587 => x"00008067",
00000588 => x"00050313",
00000589 => x"ff010113",
00000590 => x"00060513",
00000591 => x"00068893",
00000592 => x"00112623",
00000593 => x"00030613",
00000594 => x"00050693",
00000595 => x"00000713",
00000596 => x"00000793",
00000597 => x"00000813",
00000598 => x"0016fe13",
00000599 => x"00171e93",
00000600 => x"000e0c63",
00000601 => x"01060e33",
00000602 => x"010e3833",
00000603 => x"00e787b3",
00000604 => x"00f807b3",
00000605 => x"000e0813",
00000606 => x"01f65713",
00000607 => x"0016d693",
00000608 => x"00eee733",
00000609 => x"00161613",
00000610 => x"fc0698e3",
00000611 => x"00058663",
00000612 => x"f7dff0ef",
00000613 => x"00a787b3",
00000614 => x"00088a63",
00000615 => x"00030513",
00000616 => x"00088593",
00000617 => x"f69ff0ef",
00000618 => x"00f507b3",
00000619 => x"00c12083",
00000620 => x"00080513",
00000621 => x"00078593",
00000622 => x"01010113",
00000623 => x"00008067",
00000624 => x"06054063",
00000625 => x"0605c663",
00000626 => x"00058613",
00000627 => x"00050593",
00000628 => x"fff00513",
00000629 => x"02060c63",
00000630 => x"00100693",
00000631 => x"00b67a63",
00000632 => x"00c05863",
00000633 => x"00161613",
00000634 => x"00169693",
00000635 => x"feb66ae3",
00000636 => x"00000513",
00000637 => x"00c5e663",
00000638 => x"40c585b3",
00000639 => x"00d56533",
00000640 => x"0016d693",
00000641 => x"00165613",
00000642 => x"fe0696e3",
00000643 => x"00008067",
00000644 => x"00008293",
00000645 => x"fb5ff0ef",
00000646 => x"00058513",
00000647 => x"00028067",
00000648 => x"40a00533",
00000649 => x"00b04863",
00000650 => x"40b005b3",
00000651 => x"f9dff06f",
00000652 => x"40b005b3",
00000653 => x"00008293",
00000654 => x"f91ff0ef",
00000655 => x"40a00533",
00000132 => x"fc010113",
00000133 => x"02112e23",
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00000734 => x"65636361",
00000735 => x"66207373",
00000736 => x"746c7561",
00000737 => x"00000000",
00000738 => x"656c6c49",
00000739 => x"206c6167",
00000740 => x"74736e69",
00000741 => x"74637572",
00000742 => x"006e6f69",
00000743 => x"61657242",
00000744 => x"696f706b",
00000745 => x"0000746e",
00000746 => x"64616f4c",
00000747 => x"64646120",
00000748 => x"73736572",
00000749 => x"73696d20",
00000750 => x"67696c61",
00000751 => x"0064656e",
00000752 => x"64616f4c",
00000753 => x"64646120",
00000754 => x"73736572",
00000755 => x"73696d20",
00000756 => x"67696c61",
00000757 => x"0064656e",
00000758 => x"64616f4c",
00000759 => x"63636120",
00000760 => x"20737365",
00000761 => x"6c756166",
00000762 => x"00000074",
00000763 => x"726f7453",
00000764 => x"64612065",
00000765 => x"73657264",
00000766 => x"696d2073",
00000767 => x"696c6173",
00000768 => x"64656e67",
00000769 => x"00000000",
00000770 => x"726f7453",
00000771 => x"63612065",
00000772 => x"73736563",
00000773 => x"75616620",
00000774 => x"0000746c",
00000775 => x"69766e45",
00000776 => x"6d6e6f72",
00000777 => x"20746e65",
00000778 => x"6c6c6163",
00000779 => x"6f726620",
00000780 => x"2d55206d",
00000781 => x"65646f6d",
00000782 => x"00000000",
00000783 => x"69766e45",
00000784 => x"6d6e6f72",
00000785 => x"20746e65",
00000786 => x"6c6c6163",
00000787 => x"6f726620",
00000788 => x"2d4d206d",
00000789 => x"65646f6d",
00000790 => x"00000000",
00000791 => x"6863614d",
00000792 => x"20656e69",
00000793 => x"74666f73",
00000794 => x"65726177",
00000795 => x"746e6920",
00000796 => x"75727265",
00000797 => x"00007470",
00000753 => x"63636120",
00000754 => x"20737365",
00000755 => x"6c756166",
00000756 => x"00000074",
00000757 => x"726f7453",
00000758 => x"64612065",
00000759 => x"73657264",
00000760 => x"696d2073",
00000761 => x"696c6173",
00000762 => x"64656e67",
00000763 => x"00000000",
00000764 => x"726f7453",
00000765 => x"63612065",
00000766 => x"73736563",
00000767 => x"75616620",
00000768 => x"0000746c",
00000769 => x"69766e45",
00000770 => x"6d6e6f72",
00000771 => x"20746e65",
00000772 => x"6c6c6163",
00000773 => x"6f726620",
00000774 => x"2d55206d",
00000775 => x"65646f6d",
00000776 => x"00000000",
00000777 => x"69766e45",
00000778 => x"6d6e6f72",
00000779 => x"20746e65",
00000780 => x"6c6c6163",
00000781 => x"6f726620",
00000782 => x"2d4d206d",
00000783 => x"65646f6d",
00000784 => x"00000000",
00000785 => x"6863614d",
00000786 => x"20656e69",
00000787 => x"74666f73",
00000788 => x"65726177",
00000789 => x"746e6920",
00000790 => x"75727265",
00000791 => x"00007470",
00000792 => x"6863614d",
00000793 => x"20656e69",
00000794 => x"656d6974",
00000795 => x"6e692072",
00000796 => x"72726574",
00000797 => x"00747075",
00000798 => x"6863614d",
00000799 => x"20656e69",
00000800 => x"656d6974",
00000801 => x"6e692072",
00000802 => x"72726574",
00000803 => x"00747075",
00000804 => x"6863614d",
00000805 => x"20656e69",
00000806 => x"65747865",
00000807 => x"6c616e72",
00000808 => x"746e6920",
00000809 => x"75727265",
00000810 => x"00007470",
00000811 => x"74736146",
00000812 => x"746e6920",
00000813 => x"75727265",
00000814 => x"00207470",
00000815 => x"6e6b6e55",
00000816 => x"206e776f",
00000817 => x"70617274",
00000818 => x"75616320",
00000819 => x"203a6573",
00000820 => x"00000000",
00000821 => x"49545b20",
00000822 => x"554f454d",
00000823 => x"52455f54",
00000824 => x"00005d52",
00000825 => x"45445b20",
00000826 => x"45434956",
00000827 => x"5252455f",
00000828 => x"0000005d",
00000829 => x"4d505b20",
00000830 => x"52455f50",
00000831 => x"00005d52",
00000832 => x"50204020",
00000833 => x"00003d43",
00000834 => x"544d202c",
00000835 => x"3d4c4156",
00000836 => x"00000000",
00000837 => x"522f3c20",
00000838 => x"0a3e4554",
00000839 => x"00000000",
00000840 => x"00000788",
00000841 => x"00000798",
00000842 => x"000007c0",
00000843 => x"000007cc",
00000844 => x"000007d8",
00000845 => x"000007e4",
00000846 => x"000007f0",
00000847 => x"000007fc",
00000848 => x"00000808",
00000849 => x"000006f4",
00000850 => x"000006f4",
00000851 => x"00000814",
00000852 => x"33323130",
00000853 => x"37363534",
00000854 => x"42413938",
00000855 => x"46454443"
00000800 => x"65747865",
00000801 => x"6c616e72",
00000802 => x"746e6920",
00000803 => x"75727265",
00000804 => x"00007470",
00000805 => x"74736146",
00000806 => x"746e6920",
00000807 => x"75727265",
00000808 => x"00207470",
00000809 => x"6e6b6e55",
00000810 => x"206e776f",
00000811 => x"70617274",
00000812 => x"75616320",
00000813 => x"203a6573",
00000814 => x"00000000",
00000815 => x"49545b20",
00000816 => x"554f454d",
00000817 => x"52455f54",
00000818 => x"00005d52",
00000819 => x"45445b20",
00000820 => x"45434956",
00000821 => x"5252455f",
00000822 => x"0000005d",
00000823 => x"4d505b20",
00000824 => x"52455f50",
00000825 => x"00005d52",
00000826 => x"50204020",
00000827 => x"00003d43",
00000828 => x"544d202c",
00000829 => x"3d4c4156",
00000830 => x"00000000",
00000831 => x"522f3c20",
00000832 => x"0a3e4554",
00000833 => x"00000000",
00000834 => x"0000058c",
00000835 => x"0000059c",
00000836 => x"000005c4",
00000837 => x"000005d0",
00000838 => x"000005dc",
00000839 => x"000005e8",
00000840 => x"000005f4",
00000841 => x"00000600",
00000842 => x"0000060c",
00000843 => x"000004f8",
00000844 => x"000004f8",
00000845 => x"00000618",
00000846 => x"33323130",
00000847 => x"37363534",
00000848 => x"42413938",
00000849 => x"46454443"
);
 
end neorv32_application_image;
/neorv32/trunk/rtl/core/neorv32_boot_rom.vhd
3,7 → 3,7
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
47,9 → 47,11
port (
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
addr_i : in std_ulogic_vector(31 downto 0); -- address
data_o : out std_ulogic_vector(31 downto 0); -- data out
ack_o : out std_ulogic -- transfer acknowledge
ack_o : out std_ulogic; -- transfer acknowledge
err_o : out std_ulogic -- transfer error
);
end neorv32_boot_rom;
 
91,7 → 93,8
mem_file_access: process(clk_i)
begin
if rising_edge(clk_i) then
rden <= rden_i and acc_en;
rden <= acc_en and rden_i;
err_o <= acc_en and wren_i;
if (acc_en = '1') then -- reduce switching activity when not accessed
rdata <= mem_rom(to_integer(unsigned(addr)));
end if;
/neorv32/trunk/rtl/core/neorv32_bootloader_image.vhd
1,6 → 1,6
-- The NEORV32 RISC-V Processor, https://github.com/stnolting/neorv32
-- Auto-generated memory init file (for BOOTLOADER) from source file <bootloader/main.bin>
-- Size: 4016 bytes
-- Size: 3924 bytes
 
library ieee;
use ieee.std_logic_1164.all;
51,7 → 51,7
00000037 => x"00158593",
00000038 => x"ff5ff06f",
00000039 => x"00001597",
00000040 => x"f1458593",
00000040 => x"eb858593",
00000041 => x"80010617",
00000042 => x"f5c60613",
00000043 => x"80010697",
88,933 → 88,910
00000074 => x"00412483",
00000075 => x"00810113",
00000076 => x"30200073",
00000077 => x"fd010113",
00000078 => x"02912223",
00000077 => x"fb010113",
00000078 => x"04912223",
00000079 => x"800004b7",
00000080 => x"00048793",
00000081 => x"02112623",
00000082 => x"02812423",
00000083 => x"03212023",
00000084 => x"01312e23",
00000085 => x"01412c23",
00000086 => x"01512a23",
00000087 => x"01612823",
00000088 => x"01712623",
00000089 => x"01812423",
00000090 => x"01912223",
00000091 => x"0007a023",
00000092 => x"8001a223",
00000093 => x"ffff07b7",
00000094 => x"4ac78793",
00000095 => x"30579073",
00000096 => x"00000693",
00000097 => x"00000613",
00000098 => x"00000593",
00000099 => x"00200513",
00000100 => x"351000ef",
00000101 => x"3e5000ef",
00000102 => x"00048493",
00000103 => x"00050863",
00000104 => x"00100513",
00000105 => x"00000593",
00000106 => x"411000ef",
00000107 => x"00005537",
00000108 => x"00000613",
00000109 => x"00000593",
00000110 => x"b0050513",
00000111 => x"1d9000ef",
00000112 => x"19d000ef",
00000113 => x"02050663",
00000114 => x"305000ef",
00000115 => x"fe002783",
00000116 => x"0027d793",
00000117 => x"00a78533",
00000118 => x"00f537b3",
00000119 => x"00b785b3",
00000120 => x"18d000ef",
00000121 => x"08000793",
00000122 => x"30479073",
00000123 => x"30046073",
00000124 => x"ffff1537",
00000125 => x"ee050513",
00000126 => x"27d000ef",
00000127 => x"f1302573",
00000128 => x"23c000ef",
00000129 => x"ffff1537",
00000130 => x"f1850513",
00000131 => x"269000ef",
00000132 => x"fe002503",
00000133 => x"228000ef",
00000134 => x"ffff1537",
00000135 => x"f2050513",
00000136 => x"255000ef",
00000137 => x"30102573",
00000138 => x"214000ef",
00000139 => x"ffff1537",
00000140 => x"f2850513",
00000141 => x"241000ef",
00000142 => x"fe402503",
00000143 => x"ffff1437",
00000144 => x"1fc000ef",
00000145 => x"ffff1537",
00000146 => x"f3050513",
00000147 => x"229000ef",
00000148 => x"fe802503",
00000149 => x"1e8000ef",
00000150 => x"ffff1537",
00000151 => x"f3850513",
00000152 => x"215000ef",
00000153 => x"ff802503",
00000154 => x"1d4000ef",
00000155 => x"f4040513",
00000156 => x"205000ef",
00000157 => x"ff002503",
00000158 => x"1c4000ef",
00000159 => x"ffff1537",
00000160 => x"f4c50513",
00000161 => x"1f1000ef",
00000162 => x"ffc02503",
00000163 => x"1b0000ef",
00000164 => x"f4040513",
00000165 => x"1e1000ef",
00000166 => x"ff402503",
00000167 => x"1a0000ef",
00000168 => x"0bd000ef",
00000169 => x"06050663",
00000170 => x"ffff1537",
00000171 => x"f5450513",
00000172 => x"1c5000ef",
00000173 => x"219000ef",
00000174 => x"fe002403",
00000175 => x"00341413",
00000176 => x"00a40933",
00000177 => x"00893433",
00000178 => x"00b40433",
00000179 => x"0b9000ef",
00000180 => x"02051663",
00000181 => x"1f9000ef",
00000182 => x"fe85eae3",
00000183 => x"00b41463",
00000184 => x"ff2566e3",
00000185 => x"00100513",
00000186 => x"4c8000ef",
00000187 => x"ffff1537",
00000188 => x"f7c50513",
00000189 => x"181000ef",
00000190 => x"0d4000ef",
00000191 => x"16d000ef",
00000192 => x"fc050ae3",
00000193 => x"ffff1537",
00000194 => x"f8050513",
00000195 => x"169000ef",
00000196 => x"0b0000ef",
00000197 => x"ffff19b7",
00000198 => x"ffff1a37",
00000199 => x"07200a93",
00000200 => x"06800b13",
00000201 => x"07500b93",
00000202 => x"07300c13",
00000203 => x"ffff1937",
00000204 => x"ffff1cb7",
00000205 => x"f8c98513",
00000206 => x"13d000ef",
00000207 => x"11d000ef",
00000208 => x"00050413",
00000209 => x"0e1000ef",
00000210 => x"f7ca0513",
00000211 => x"129000ef",
00000212 => x"0ed000ef",
00000213 => x"fe051ee3",
00000214 => x"01541863",
00000215 => x"ffff02b7",
00000216 => x"00028067",
00000217 => x"fd1ff06f",
00000218 => x"01641663",
00000219 => x"054000ef",
00000220 => x"fc5ff06f",
00000221 => x"01741663",
00000222 => x"438000ef",
00000223 => x"fb9ff06f",
00000224 => x"01841663",
00000225 => x"65c000ef",
00000226 => x"fadff06f",
00000227 => x"06c00793",
00000228 => x"00f41663",
00000229 => x"00100513",
00000230 => x"fe1ff06f",
00000231 => x"06500793",
00000232 => x"00f41c63",
00000233 => x"0004a783",
00000234 => x"f40798e3",
00000235 => x"e88c8513",
00000236 => x"0c5000ef",
00000237 => x"f81ff06f",
00000238 => x"f9490513",
00000239 => x"ff5ff06f",
00000240 => x"ffff1537",
00000241 => x"dc850513",
00000242 => x"0ad0006f",
00000243 => x"ff010113",
00000244 => x"00112623",
00000245 => x"30047073",
00000246 => x"ffff1537",
00000247 => x"e2c50513",
00000248 => x"095000ef",
00000249 => x"059000ef",
00000250 => x"fe051ee3",
00000251 => x"ff002783",
00000252 => x"00078067",
00000253 => x"0000006f",
00000254 => x"ff010113",
00000255 => x"00812423",
00000256 => x"00050413",
00000257 => x"ffff1537",
00000258 => x"e3c50513",
00000259 => x"00112623",
00000260 => x"065000ef",
00000261 => x"03040513",
00000262 => x"0ff57513",
00000263 => x"009000ef",
00000264 => x"30047073",
00000265 => x"155000ef",
00000266 => x"00050863",
00000267 => x"00100513",
00000268 => x"00000593",
00000269 => x"185000ef",
00000270 => x"0000006f",
00000271 => x"fe010113",
00000272 => x"01212823",
00000273 => x"00050913",
00000274 => x"ffff1537",
00000275 => x"00912a23",
00000276 => x"e4850513",
00000277 => x"ffff14b7",
00000278 => x"00812c23",
00000279 => x"01312623",
00000280 => x"00112e23",
00000281 => x"01c00413",
00000282 => x"00d000ef",
00000283 => x"fa048493",
00000284 => x"ffc00993",
00000285 => x"008957b3",
00000286 => x"00f7f793",
00000287 => x"00f487b3",
00000288 => x"0007c503",
00000289 => x"ffc40413",
00000290 => x"79c000ef",
00000291 => x"ff3414e3",
00000292 => x"01c12083",
00000293 => x"01812403",
00000294 => x"01412483",
00000295 => x"01012903",
00000296 => x"00c12983",
00000297 => x"02010113",
00000298 => x"00008067",
00000299 => x"fb010113",
00000300 => x"04112623",
00000301 => x"04512423",
00000302 => x"04612223",
00000303 => x"04712023",
00000304 => x"02812e23",
00000305 => x"02912c23",
00000306 => x"02a12a23",
00000307 => x"02b12823",
00000308 => x"02c12623",
00000309 => x"02d12423",
00000310 => x"02e12223",
00000311 => x"02f12023",
00000312 => x"01012e23",
00000313 => x"01112c23",
00000314 => x"01c12a23",
00000315 => x"01d12823",
00000316 => x"01e12623",
00000317 => x"01f12423",
00000318 => x"342024f3",
00000319 => x"800007b7",
00000320 => x"00778793",
00000321 => x"08f49463",
00000322 => x"071000ef",
00000323 => x"00050663",
00000324 => x"00000513",
00000325 => x"075000ef",
00000326 => x"644000ef",
00000327 => x"02050063",
00000328 => x"7ac000ef",
00000329 => x"fe002783",
00000330 => x"0027d793",
00000331 => x"00a78533",
00000332 => x"00f537b3",
00000333 => x"00b785b3",
00000334 => x"634000ef",
00000335 => x"03c12403",
00000336 => x"04c12083",
00000337 => x"04812283",
00000338 => x"04412303",
00000339 => x"04012383",
00000340 => x"03812483",
00000341 => x"03412503",
00000342 => x"03012583",
00000343 => x"02c12603",
00000344 => x"02812683",
00000345 => x"02412703",
00000346 => x"02012783",
00000347 => x"01c12803",
00000348 => x"01812883",
00000349 => x"01412e03",
00000350 => x"01012e83",
00000351 => x"00c12f03",
00000352 => x"00812f83",
00000353 => x"05010113",
00000354 => x"30200073",
00000355 => x"00700793",
00000356 => x"00f49a63",
00000357 => x"8041a783",
00000358 => x"00078663",
00000359 => x"00100513",
00000360 => x"e59ff0ef",
00000361 => x"34102473",
00000362 => x"5dc000ef",
00000363 => x"04050263",
00000364 => x"ffff1537",
00000365 => x"e4c50513",
00000366 => x"6bc000ef",
00000367 => x"00048513",
00000368 => x"e7dff0ef",
00000369 => x"02000513",
00000370 => x"65c000ef",
00000371 => x"00040513",
00000372 => x"e6dff0ef",
00000373 => x"02000513",
00000374 => x"64c000ef",
00000375 => x"34302573",
00000376 => x"e5dff0ef",
00000377 => x"ffff1537",
00000378 => x"e5450513",
00000379 => x"688000ef",
00000380 => x"00440413",
00000381 => x"34141073",
00000382 => x"f45ff06f",
00000383 => x"ff010113",
00000384 => x"00000513",
00000081 => x"04112623",
00000082 => x"04812423",
00000083 => x"05212023",
00000084 => x"03312e23",
00000085 => x"03412c23",
00000086 => x"03512a23",
00000087 => x"03612823",
00000088 => x"03712623",
00000089 => x"03812423",
00000090 => x"03912223",
00000091 => x"03a12023",
00000092 => x"01b12e23",
00000093 => x"0007a023",
00000094 => x"800007b7",
00000095 => x"0007a223",
00000096 => x"ffff07b7",
00000097 => x"77078793",
00000098 => x"30579073",
00000099 => x"000017b7",
00000100 => x"fa002423",
00000101 => x"90078793",
00000102 => x"faf02423",
00000103 => x"fe802783",
00000104 => x"00010737",
00000105 => x"00048493",
00000106 => x"00e7f7b3",
00000107 => x"00078863",
00000108 => x"00100793",
00000109 => x"fcf02423",
00000110 => x"fc002623",
00000111 => x"fa002023",
00000112 => x"fe002683",
00000113 => x"000097b7",
00000114 => x"ffff7637",
00000115 => x"00000713",
00000116 => x"5ff78793",
00000117 => x"a0060613",
00000118 => x"1ed7e463",
00000119 => x"000016b7",
00000120 => x"00000793",
00000121 => x"ffe68693",
00000122 => x"1ee6e663",
00000123 => x"fff70713",
00000124 => x"01879793",
00000125 => x"00e7e7b3",
00000126 => x"10000737",
00000127 => x"00e7e7b3",
00000128 => x"faf02023",
00000129 => x"fe802783",
00000130 => x"00020737",
00000131 => x"00e7f7b3",
00000132 => x"02078463",
00000133 => x"fe002783",
00000134 => x"fff00713",
00000135 => x"f8e02c23",
00000136 => x"0027d793",
00000137 => x"f8002e23",
00000138 => x"f8f02c23",
00000139 => x"08000793",
00000140 => x"30479073",
00000141 => x"30046073",
00000142 => x"ffff1537",
00000143 => x"d2c50513",
00000144 => x"3b8000ef",
00000145 => x"f1302573",
00000146 => x"4b8000ef",
00000147 => x"ffff1537",
00000148 => x"d6450513",
00000149 => x"3a4000ef",
00000150 => x"fe002503",
00000151 => x"4a4000ef",
00000152 => x"ffff1537",
00000153 => x"d6c50513",
00000154 => x"390000ef",
00000155 => x"30102573",
00000156 => x"490000ef",
00000157 => x"ffff1537",
00000158 => x"d7450513",
00000159 => x"37c000ef",
00000160 => x"fc002573",
00000161 => x"47c000ef",
00000162 => x"ffff1537",
00000163 => x"d7850513",
00000164 => x"368000ef",
00000165 => x"fe802503",
00000166 => x"ffff1437",
00000167 => x"464000ef",
00000168 => x"ffff1537",
00000169 => x"d8050513",
00000170 => x"350000ef",
00000171 => x"ff802503",
00000172 => x"450000ef",
00000173 => x"d8840513",
00000174 => x"340000ef",
00000175 => x"ff002503",
00000176 => x"440000ef",
00000177 => x"ffff1537",
00000178 => x"d9450513",
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00000929 => x"20296e2f",
00000930 => x"00000000",
00000931 => x"616c460a",
00000932 => x"6e696873",
00000933 => x"2e2e2e67",
00000934 => x"00000020",
00000935 => x"20296328",
00000936 => x"53207962",
00000937 => x"68706574",
00000938 => x"4e206e61",
00000939 => x"69746c6f",
00000940 => x"680a676e",
00000941 => x"73707474",
00000942 => x"672f2f3a",
00000943 => x"75687469",
00000944 => x"6f632e62",
00000945 => x"74732f6d",
00000946 => x"746c6f6e",
00000947 => x"2f676e69",
00000948 => x"726f656e",
00000949 => x"00323376",
00000950 => x"61766e49",
00000951 => x"2064696c",
00000952 => x"00444d43",
00000953 => x"20657865",
00000954 => x"6e676973",
00000955 => x"72757461",
00000956 => x"61662065",
00000957 => x"00006c69",
00000958 => x"00000000",
00000959 => x"65637865",
00000960 => x"6e696465",
00000961 => x"4d492067",
00000962 => x"63204d45",
00000963 => x"63617061",
00000964 => x"00797469",
00000965 => x"63656863",
00000966 => x"6d75736b",
00000967 => x"69616620",
00000968 => x"0000006c",
00000969 => x"00000000",
00000970 => x"00000000",
00000971 => x"20495053",
00000972 => x"73616c66",
00000973 => x"63612068",
00000974 => x"73736563",
00000975 => x"69616620",
00000976 => x"0064656c",
00000977 => x"33323130",
00000978 => x"37363534",
00000979 => x"62613938",
00000980 => x"66656463"
);
 
end neorv32_bootloader_image;
/neorv32/trunk/rtl/core/neorv32_cpu.vhd
5,6 → 5,7
-- # * neorv32_cpu.vhd - CPU top entity #
-- # * neorv32_cpu_alu.vhd - Arithmetic/logic unit #
-- # * neorv32_cpu_cp_bitmanip.vhd - Bit-manipulation co-processor #
-- # * neorv32_cpu_cp_cfu.vhd - Custom instructions co-processor #
-- # * neorv32_cpu_cp_fpu.vhd - Single-precision FPU co-processor #
-- # * neorv32_cpu_cp_muldiv.vhd - Integer multiplier/divider co-processor #
-- # * neorv32_cpu_cp_shifter.vhd - Base ISA shifter unit #
76,6 → 77,7
CPU_EXTENSION_RISCV_Zihpm : boolean; -- implement hardware performance monitors?
CPU_EXTENSION_RISCV_Zifencei : boolean; -- implement instruction stream sync.?
CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension?
CPU_EXTENSION_RISCV_Zxcfu : boolean; -- implement custom (instr.) functions unit?
CPU_EXTENSION_RISCV_DEBUG : boolean; -- implement CPU debug mode?
-- Extension Options --
FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier
182,6 → 184,7
cond_sel_string_f(CPU_EXTENSION_RISCV_Zifencei, "_Zifencei", "") &
cond_sel_string_f(CPU_EXTENSION_RISCV_Zfinx, "_Zfinx", "") &
cond_sel_string_f(CPU_EXTENSION_RISCV_Zmmul, "_Zmmul", "") &
cond_sel_string_f(CPU_EXTENSION_RISCV_Zxcfu, "_Zxcfu", "") &
cond_sel_string_f(CPU_EXTENSION_RISCV_DEBUG, "_DEBUG", "") &
""
severity note;
225,6 → 228,9
-- Mul-extension --
assert not ((CPU_EXTENSION_RISCV_Zmmul = true) and (CPU_EXTENSION_RISCV_M = true)) report "NEORV32 CPU CONFIG ERROR! <M> and <Zmmul> extensions cannot co-exist!" severity error;
 
-- Custom Functions Unit --
assert not (CPU_EXTENSION_RISCV_Zxcfu = true) report "NEORV32 CPU CONFIG NOTE: Implementing Custom Functions Unit (CFU) as <Zxcfu> ISA extension." severity note;
 
-- Debug mode --
assert not ((CPU_EXTENSION_RISCV_DEBUG = true) and (CPU_EXTENSION_RISCV_Zicsr = false)) report "NEORV32 CPU CONFIG ERROR! Debug mode requires <CPU_EXTENSION_RISCV_Zicsr> extension to be enabled." severity error;
assert not ((CPU_EXTENSION_RISCV_DEBUG = true) and (CPU_EXTENSION_RISCV_Zifencei = false)) report "NEORV32 CPU CONFIG ERROR! Debug mode requires <CPU_EXTENSION_RISCV_Zifencei> extension to be enabled." severity error;
257,8 → 263,11
CPU_EXTENSION_RISCV_Zihpm => CPU_EXTENSION_RISCV_Zihpm, -- implement hardware performance monitors?
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
CPU_EXTENSION_RISCV_Zmmul => CPU_EXTENSION_RISCV_Zmmul, -- implement multiply-only M sub-extension?
CPU_EXTENSION_RISCV_Zxcfu => CPU_EXTENSION_RISCV_Zxcfu, -- implement custom (instr.) functions unit?
CPU_EXTENSION_RISCV_DEBUG => CPU_EXTENSION_RISCV_DEBUG, -- implement CPU debug mode?
-- Extension Options --
-- Tuning Options --
FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier
FAST_SHIFT_EN => FAST_SHIFT_EN, -- use barrel shifter for shift operations
CPU_CNT_WIDTH => CPU_CNT_WIDTH, -- total width of CPU cycle and instret counters (0..64)
CPU_IPB_ENTRIES => CPU_IPB_ENTRIES, -- entries is instruction prefetch buffer, has to be a power of 2
-- Physical memory protection (PMP) --
349,6 → 358,7
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement mul/div extension?
CPU_EXTENSION_RISCV_Zmmul => CPU_EXTENSION_RISCV_Zmmul, -- implement multiply-only M sub-extension?
CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, -- implement 32-bit floating-point extension (using INT reg!)
CPU_EXTENSION_RISCV_Zxcfu => CPU_EXTENSION_RISCV_Zxcfu, -- implement custom (instr.) functions unit?
-- Extension Options --
FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier
FAST_SHIFT_EN => FAST_SHIFT_EN -- use barrel shifter for shift operations
/neorv32/trunk/rtl/core/neorv32_cpu_alu.vhd
1,7 → 1,7
-- #################################################################################################
-- # << NEORV32 - Arithmetical/Logical Unit >> #
-- # ********************************************************************************************* #
-- # Main data and address ALU and co-processor interface/arbiter. #
-- # Main data/address ALU and ALU co-processor (= multi-cycle function units). #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
48,6 → 48,7
CPU_EXTENSION_RISCV_M : boolean; -- implement mul/div extension?
CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension?
CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT reg!)
CPU_EXTENSION_RISCV_Zxcfu : boolean; -- implement custom (instr.) functions unit?
-- Extension Options --
FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier
FAST_SHIFT_EN : boolean -- use barrel shifter for shift operations
334,12 → 335,33
end generate;
 
 
-- Co-Processor 4: Reserved ---------------------------------------------------------------
-- Co-Processor 4: Custom (Instructions) Functions Unit ('Zxcfu' Extension) ---------------
-- -------------------------------------------------------------------------------------------
cp_result(4) <= (others => '0');
cp_valid(4) <= '0';
neorv32_cpu_cp_cfu_inst_true:
if (CPU_EXTENSION_RISCV_Zxcfu = true) generate
neorv32_cpu_cp_cfu_inst: neorv32_cpu_cp_cfu
port map (
-- global control --
clk_i => clk_i, -- global clock, rising edge
rstn_i => rstn_i, -- global reset, low-active, async
ctrl_i => ctrl_i, -- main control bus
start_i => cp_start(4), -- trigger operation
-- data input --
rs1_i => rs1_i, -- rf source 1
rs2_i => rs2_i, -- rf source 2
-- result and status --
res_o => cp_result(4), -- operation result
valid_o => cp_valid(4) -- data output valid
);
end generate;
 
neorv32_cpu_cp_cfu_inst_false:
if (CPU_EXTENSION_RISCV_Zxcfu = false) generate
cp_result(4) <= (others => '0');
cp_valid(4) <= '0';
end generate;
 
 
-- Co-Processor 5: Reserved ---------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
cp_result(5) <= (others => '0');
/neorv32/trunk/rtl/core/neorv32_cpu_control.vhd
7,8 → 7,9
-- # + Issue engine: Decodes compressed instructions, aligns and queues instruction words #
-- # + Execute engine: Multi-cycle execution of instructions (generate control signals) #
-- # + Trap engine: Handles interrupts and exceptions #
-- # + CSR module: Read/write accesses to CSRs & HW counters #
-- # + CSR module: Read/write access to control and status registers #
-- # + Debug module: CPU debug mode handling (on-chip debugger) #
-- # + Trigger module: Hardware-assisted breakpoints (on-chip debugger) #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
67,8 → 68,11
CPU_EXTENSION_RISCV_Zihpm : boolean; -- implement hardware performance monitors?
CPU_EXTENSION_RISCV_Zifencei : boolean; -- implement instruction stream sync.?
CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension?
CPU_EXTENSION_RISCV_Zxcfu : boolean; -- implement custom (instr.) functions unit?
CPU_EXTENSION_RISCV_DEBUG : boolean; -- implement CPU debug mode?
-- Extension Options --
-- Tuning Options --
FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier
FAST_SHIFT_EN : boolean; -- use barrel shifter for shift operations
CPU_CNT_WIDTH : natural; -- total width of CPU cycle and instret counters (0..64)
CPU_IPB_ENTRIES : natural; -- entries is instruction prefetch buffer, has to be a power of 2
-- Physical memory protection (PMP) --
344,6 → 348,10
dcsr_rd : std_ulogic_vector(data_width_c-1 downto 0); -- dcsr (R/(W)): debug mode control and status register
dpc : std_ulogic_vector(data_width_c-1 downto 0); -- dpc (R/W): debug mode program counter
dscratch0 : std_ulogic_vector(data_width_c-1 downto 0); -- dscratch0 (R/W): debug mode scratch register 0
--
tdata1_exe : std_ulogic; -- enable (match) trigger
tdata1_rd : std_ulogic_vector(data_width_c-1 downto 0); -- tdata1 (R/(W)): trigger register read-back
tdata2 : std_ulogic_vector(data_width_c-1 downto 0); -- tdata2 (R/W): address-match register
end record;
signal csr : csr_t;
 
355,6 → 363,7
running : std_ulogic; -- debug mode active
pending : std_ulogic; -- waiting to start debug mode
-- entering triggers --
trig_hw : std_ulogic; -- hardware trigger
trig_break : std_ulogic; -- ebreak instruction
trig_halt : std_ulogic; -- external request
trig_step : std_ulogic; -- single-stepping mode
378,6 → 387,9
-- access (privilege) check --
signal csr_acc_valid : std_ulogic; -- valid CSR access (implemented and valid access rights)
 
-- hardware trigger module --
signal hw_trigger_fire : std_ulogic;
 
begin
 
-- ****************************************************************************************************************************
681,11 → 693,6
execute_engine_fsm_sync: process(rstn_i, clk_i)
begin
if (rstn_i = '0') then
-- registers that DO require a specific reset state --
execute_engine.pc <= CPU_BOOT_ADDR(data_width_c-1 downto 2) & "00"; -- 32-bit aligned!
execute_engine.state <= SYS_WAIT;
execute_engine.sleep <= '0';
execute_engine.branched <= '1'; -- reset is a branch from "somewhere"
-- no dedicated RESET required --
execute_engine.state_prev <= SYS_WAIT; -- actual reset value is not relevant
execute_engine.i_reg <= (others => def_rst_val_c);
695,6 → 702,11
execute_engine.i_reg_last <= (others => def_rst_val_c);
execute_engine.next_pc <= (others => def_rst_val_c);
ctrl <= (others => def_rst_val_c);
-- registers that DO require a specific reset state --
execute_engine.pc <= CPU_BOOT_ADDR(data_width_c-1 downto 2) & "00"; -- 32-bit aligned!
execute_engine.state <= SYS_WAIT;
execute_engine.sleep <= '0';
execute_engine.branched <= '1'; -- reset is a branch from "somewhere"
ctrl(ctrl_bus_rd_c) <= '0';
ctrl(ctrl_bus_wr_c) <= '0';
elsif rising_edge(clk_i) then
983,9 → 995,9
execute_engine.is_ici_nxt <= cmd_issue.data(35); -- invalid decompressed instruction
-- any reason to go to trap state? --
if (execute_engine.sleep = '1') or -- enter sleep state
(trap_ctrl.exc_fire = '1') or -- exception during LAST instruction (illegal instruction)
(trap_ctrl.exc_fire = '1') or -- exception during LAST instruction (e.g. illegal instruction)
(trap_ctrl.env_start = '1') or -- pending trap (IRQ or exception)
((cmd_issue.data(33) = '1') and (CPU_EXTENSION_RISCV_C = false)) or -- misaligned instruction fetch address, if C disabled
((cmd_issue.data(33) = '1') and (CPU_EXTENSION_RISCV_C = false)) or -- misaligned instruction fetch address (if C disabled)
(cmd_issue.data(34) = '1') then -- bus access fault during instruction fetch
execute_engine.state_nxt <= TRAP_ENTER;
else
1127,6 → 1139,17
end if;
 
 
when opcode_cust0_c => -- CFU: custom RISC-V instructions (CUSTOM0 OPCODE space)
-- ------------------------------------------------------------
if (CPU_EXTENSION_RISCV_Zxcfu = true) then
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_cfu_c; -- trigger CFU CP
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_copro_c;
execute_engine.state_nxt <= ALU_WAIT;
else
execute_engine.state_nxt <= SYS_WAIT;
end if;
 
 
when others => -- system/csr access OR illegal opcode - nothing bad (= no commits) will happen here if there is an illegal opcode
-- ------------------------------------------------------------
if (CPU_EXTENSION_RISCV_Zicsr = true) then
1188,7 → 1211,7
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_copro_c;
-- wait for completion or abort on illegal instruction exception (the co-processor will also terminate operations)
if (alu_idone_i = '1') or (trap_ctrl.exc_buf(exception_iillegal_c) = '1') then
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back (won't happen in case of an illegal instruction)
execute_engine.state_nxt <= DISPATCH;
end if;
 
1296,8 → 1319,8
-- Machine-level code should read-back those CSRs after writing them to realize they are read-only.
csr_acc_valid <= csr.priv_m_mode; -- M-mode only
 
-- machine information registers, read-only --
when csr_mvendorid_c | csr_marchid_c | csr_mimpid_c | csr_mhartid_c | csr_mconfigptr_c =>
-- machine information registers & NEORV32-specific registers, read-only --
when csr_mvendorid_c | csr_marchid_c | csr_mimpid_c | csr_mhartid_c | csr_mconfigptr_c | csr_mxisa_c =>
csr_acc_valid <= (not csr_wacc_v) and csr.priv_m_mode; -- M-mode only, read-only
 
-- user-mode registers --
1348,6 → 1371,11
when csr_dcsr_c | csr_dpc_c | csr_dscratch0_c =>
csr_acc_valid <= debug_ctrl.running and bool_to_ulogic_f(CPU_EXTENSION_RISCV_DEBUG); -- access only in debug-mode
 
-- trigger module CSRs --
when csr_tselect_c | csr_tdata1_c | csr_tdata2_c | csr_tdata3_c | csr_tinfo_c | csr_tcontrol_c | csr_mcontext_c | csr_scontext_c =>
-- access in debug-mode or M-mode (M-mode: writes are ignored as DMODE is hardwired to 1)
csr_acc_valid <= (debug_ctrl.running or csr.priv_m_mode) and bool_to_ulogic_f(CPU_EXTENSION_RISCV_DEBUG);
 
-- undefined / not implemented --
when others =>
csr_acc_valid <= '0'; -- invalid access
1556,8 → 1584,18
end if;
-- illegal E-CPU register? --
-- FIXME: rs2 is not checked!
illegal_register <= execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c);
illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zfinx) and (execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c));
 
when opcode_cust0_c => -- CFU: custom instructions
-- ------------------------------------------------------------
if (CPU_EXTENSION_RISCV_Zxcfu = true) then -- CFU extension implemented
illegal_instruction <= '0';
else
illegal_instruction <= '1';
end if;
-- illegal E-CPU register? --
illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zxcfu) and (execute_engine.i_reg(instr_rs2_msb_c) or execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c));
 
when others => -- undefined instruction -> illegal!
-- ------------------------------------------------------------
illegal_instruction <= '1';
1620,8 → 1658,9
trap_ctrl.exc_buf(exception_break_c) <= (trap_ctrl.exc_buf(exception_break_c) or trap_ctrl.break_point) and (not trap_ctrl.exc_clr);
end if;
 
-- exception/interrupt buffer: enter debug mode --
-- exception queue / interrupt buffer: enter debug mode --
trap_ctrl.exc_buf(exception_db_break_c) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_DEBUG) and (trap_ctrl.exc_buf(exception_db_break_c) or debug_ctrl.trig_break) and (not trap_ctrl.exc_clr);
trap_ctrl.exc_buf(exception_db_hw_c) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_DEBUG) and (trap_ctrl.exc_buf(exception_db_hw_c) or debug_ctrl.trig_hw) and (not trap_ctrl.exc_clr);
trap_ctrl.irq_buf(interrupt_db_halt_c) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_DEBUG) and debug_ctrl.trig_halt;
trap_ctrl.irq_buf(interrupt_db_step_c) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_DEBUG) and debug_ctrl.trig_step;
 
1630,7 → 1669,7
trap_ctrl.irq_buf(interrupt_mext_irq_c) <= csr.mie_meie and mext_irq_i;
trap_ctrl.irq_buf(interrupt_mtime_irq_c) <= csr.mie_mtie and mtime_irq_i;
 
-- interrupt queue: NEORV32-specific fast interrupts (FIRQ) --
-- interrupt *queue*: NEORV32-specific fast interrupts (FIRQ) - require manual ACK/clear --
trap_ctrl.irq_buf(interrupt_firq_15_c downto interrupt_firq_0_c) <= (trap_ctrl.irq_buf(interrupt_firq_15_c downto interrupt_firq_0_c) or (csr.mie_firqe and firq_i)) and (not csr.mip_clr);
 
-- trap environment control --
1718,6 → 1757,10
-- even if other IRQs are pending right now
-- ----------------------------------------------------------------------------------------
 
-- hardware trigger (sync) --
elsif (trap_ctrl.exc_buf(exception_db_hw_c) = '1') then
trap_ctrl.cause_nxt <= trap_db_hw_c;
 
-- break instruction (sync) --
elsif (trap_ctrl.exc_buf(exception_db_break_c) = '1') then
trap_ctrl.cause_nxt <= trap_db_break_c;
1891,6 → 1934,9
csr.dcsr_cause <= (others => def_rst_val_c);
csr.dpc <= (others => def_rst_val_c);
csr.dscratch0 <= (others => def_rst_val_c);
--
csr.tdata1_exe <= '0';
csr.tdata2 <= (others => def_rst_val_c);
 
elsif rising_edge(clk_i) then
-- write access? --
2061,7 → 2107,24
end if;
end if;
 
-- trigger module CSRs - only writable in DEBUG MODE (dmode == 1) --
-- --------------------------------------------------------------------
if (CPU_EXTENSION_RISCV_DEBUG = true) then
if (csr.addr(11 downto 4) = csr_class_trigger_c) then -- trigger CSR class
if (debug_ctrl.running = '1') then -- actual write only in debug mode
-- R/W: tdata1 - match control --
if (csr.addr(3 downto 0) = csr_tdata1_c(3 downto 0)) then
csr.tdata1_exe <= csr.wdata(2);
end if;
-- R/W: tdata2 - address compare --
if (csr.addr(3 downto 0) = csr_tdata2_c(3 downto 0)) then
csr.tdata2 <= csr.wdata(data_width_c-1 downto 1) & '0';
end if;
end if;
end if;
end if;
 
 
-- --------------------------------------------------------------------------------
-- CSR access by hardware
-- --------------------------------------------------------------------------------
2214,6 → 2277,12
csr.dscratch0 <= (others => '0');
end if;
 
-- trigger module disabled --
if (CPU_EXTENSION_RISCV_DEBUG = false) then
csr.tdata1_exe <= '0';
csr.tdata2 <= (others => '0');
end if;
 
end if;
end process csr_write_access;
 
2270,7 → 2339,7
csr.mcycle_ovfl(0) <= csr.mcycle_nxt(csr.mcycle_nxt'left) and (not csr.mcountinhibit_cy);
if (csr.we = '1') and (csr.addr = csr_mcycle_c) then -- write access
csr.mcycle(cpu_cnt_lo_width_c-1 downto 0) <= csr.wdata(cpu_cnt_lo_width_c-1 downto 0);
elsif (csr.mcountinhibit_cy = '0') and (cnt_event(hpmcnt_event_cy_c) = '1') then -- non-inhibited automatic update
elsif (csr.mcountinhibit_cy = '0') and (cnt_event(hpmcnt_event_cy_c) = '1') and (debug_ctrl.running = '0') then -- non-inhibited automatic update and not in debug mode
csr.mcycle(cpu_cnt_lo_width_c-1 downto 0) <= csr.mcycle_nxt(cpu_cnt_lo_width_c-1 downto 0);
end if;
else
2295,7 → 2364,7
csr.minstret_ovfl(0) <= csr.minstret_nxt(csr.minstret_nxt'left) and (not csr.mcountinhibit_ir);
if (csr.we = '1') and (csr.addr = csr_minstret_c) then -- write access
csr.minstret(cpu_cnt_lo_width_c-1 downto 0) <= csr.wdata(cpu_cnt_lo_width_c-1 downto 0);
elsif (csr.mcountinhibit_ir = '0') and (cnt_event(hpmcnt_event_ir_c) = '1') then -- non-inhibited automatic update
elsif (csr.mcountinhibit_ir = '0') and (cnt_event(hpmcnt_event_ir_c) = '1') and (debug_ctrl.running = '0') then -- non-inhibited automatic update and not in debug mode
csr.minstret(cpu_cnt_lo_width_c-1 downto 0) <= csr.minstret_nxt(cpu_cnt_lo_width_c-1 downto 0);
end if;
else
2389,7 → 2458,8
hpmcnt_trigger <= (others => '0'); -- default
if (HPM_NUM_CNTS /= 0) then
for i in 0 to HPM_NUM_CNTS-1 loop
hpmcnt_trigger(i) <= or_reduce_f(cnt_event and csr.mhpmevent(i)(cnt_event'left downto 0));
-- do not increment if CPU is in debug mode --
hpmcnt_trigger(i) <= or_reduce_f(cnt_event and csr.mhpmevent(i)(cnt_event'left downto 0)) and (not debug_ctrl.running);
end loop; -- i
end if;
end if;
2716,6 → 2786,38
when csr_dpc_c => if (CPU_EXTENSION_RISCV_DEBUG = true) then csr.rdata <= csr.dpc; else NULL; end if; -- dpc (r/w): debug mode program counter
when csr_dscratch0_c => if (CPU_EXTENSION_RISCV_DEBUG = true) then csr.rdata <= csr.dscratch0; else NULL; end if; -- dscratch0 (r/w): debug mode scratch register 0
 
-- trigger module CSRs --
-- --------------------------------------------------------------------
-- when csr_tselect_c => if (CPU_EXTENSION_RISCV_DEBUG = true) then csr.rdata <= (others => '0'); else NULL; end if; -- tselect (r/w): always zero = only 1 trigger available
when csr_tdata1_c => if (CPU_EXTENSION_RISCV_DEBUG = true) then csr.rdata <= csr.tdata1_rd; else NULL; end if; -- tdata1 (r/w): match control
when csr_tdata2_c => if (CPU_EXTENSION_RISCV_DEBUG = true) then csr.rdata <= csr.tdata2; else NULL; end if; -- tdata2 (r/w): address-compare
-- when csr_tdata3_c => if (CPU_EXTENSION_RISCV_DEBUG = true) then csr.rdata <= (others => '0'); else NULL; end if; -- tdata3 (r/w): implemented but always zero
when csr_tinfo_c => if (CPU_EXTENSION_RISCV_DEBUG = true) then csr.rdata <= x"00000004"; else NULL; end if; -- tinfo (r/w): address-match trigger only
-- when csr_tcontrol_c => if (CPU_EXTENSION_RISCV_DEBUG = true) then csr.rdata <= (others => '0'); else NULL; end if; -- tcontrol (r/w): implemented but always zero
-- when csr_mcontext_c => if (CPU_EXTENSION_RISCV_DEBUG = true) then csr.rdata <= (others => '0'); else NULL; end if; -- mcontext (r/w): implemented but always zero
-- when csr_scontext_c => if (CPU_EXTENSION_RISCV_DEBUG = true) then csr.rdata <= (others => '0'); else NULL; end if; -- scontext (r/w): implemented but always zero
 
-- NEORV32-specific (RISC-V "custom") read-only CSRs --
-- --------------------------------------------------------------------
-- machine extended ISA extensions information --
when csr_mxisa_c =>
-- ISA (sub-)extensions --
csr.rdata(00) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicsr); -- Zicsr: privileged architecture (!!!)
csr.rdata(01) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zifencei); -- Zifencei: instruction stream sync.
csr.rdata(02) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zmmul); -- Zmmul: mul/div
csr.rdata(03) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zxcfu); -- Zxcfu: custom RISC-V instructions
csr.rdata(04) <= '0'; -- reserved
csr.rdata(05) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zfinx); -- Zfinx: FPU using x registers, "F-alternative"
csr.rdata(06) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicntr) and
bool_to_ulogic_f(boolean(CPU_CNT_WIDTH /= 64)); -- Zxscnt: reduced-size CPU counters (from Zicntr)
csr.rdata(07) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicntr); -- Zicntr: base instructions, cycle and time CSRs
csr.rdata(08) <= bool_to_ulogic_f(boolean(PMP_NUM_REGIONS > 0)); -- PMP: physical memory protection (Zspmp)
csr.rdata(09) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zihpm); -- Zihpm: hardware performance monitors
csr.rdata(10) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_DEBUG); -- RISC-V debug mode
-- ISA options --
csr.rdata(30) <= bool_to_ulogic_f(FAST_MUL_EN); -- DSP-based multiplication (M extensions only)
csr.rdata(31) <= bool_to_ulogic_f(FAST_SHIFT_EN); -- parallel logic for shifts (barrel shifters)
 
-- undefined/unavailable --
-- --------------------------------------------------------------------
when others =>
2751,8 → 2853,9
case debug_ctrl.state is
 
when DEBUG_OFFLINE => -- not in debug mode, waiting for entering request
if (debug_ctrl.trig_halt = '1') or -- external request (from DM)
(debug_ctrl.trig_break = '1') or -- ebreak instruction
if (debug_ctrl.trig_halt = '1') or -- external request (from DM)
(debug_ctrl.trig_break = '1') or -- ebreak instruction
(debug_ctrl.trig_hw = '1') or -- hardware trigger module
(debug_ctrl.trig_step = '1') then -- single-stepping mode
debug_ctrl.state <= DEBUG_PENDING;
end if;
2788,11 → 2891,12
debug_ctrl.running <= '1' when ((debug_ctrl.state = DEBUG_ONLINE) or (debug_ctrl.state = DEBUG_EXIT)) and (CPU_EXTENSION_RISCV_DEBUG = true) else '0';
 
-- entry debug mode triggers --
debug_ctrl.trig_break <= trap_ctrl.break_point and (debug_ctrl.running or -- we are in debug mode: re-enter debug mode
debug_ctrl.trig_hw <= hw_trigger_fire and (not debug_ctrl.running); -- enter debug mode by HW trigger module request
debug_ctrl.trig_break <= trap_ctrl.break_point and (debug_ctrl.running or -- re-enter debug mode
(csr.priv_m_mode and csr.dcsr_ebreakm and (not debug_ctrl.running)) or -- enabled goto-debug-mode in machine mode on "ebreak"
(csr.priv_u_mode and csr.dcsr_ebreaku and (not debug_ctrl.running))); -- enabled goto-debug-mode in user mode on "ebreak"
debug_ctrl.trig_halt <= debug_ctrl.ext_halt_req and (not debug_ctrl.running); -- external halt request (if not halted already)
debug_ctrl.trig_step <= csr.dcsr_step and (not debug_ctrl.running); -- single-step mode (trigger when NOT CURRENTLY in debug mode)
debug_ctrl.trig_halt <= debug_ctrl.ext_halt_req and (not debug_ctrl.running); -- external halt request (if not halted already)
debug_ctrl.trig_step <= csr.dcsr_step and (not debug_ctrl.running); -- single-step mode (trigger when NOT CURRENTLY in debug mode)
 
 
-- Debug Control and Status Register (dcsr) - Read-Back -----------------------------------
2799,19 → 2903,49
-- -------------------------------------------------------------------------------------------
csr.dcsr_rd(31 downto 28) <= "0100"; -- xdebugver: external debug support compatible to spec
csr.dcsr_rd(27 downto 16) <= (others => '0'); -- reserved
csr.dcsr_rd(15) <= csr.dcsr_ebreakm; -- ebreakm: what happens on ebreak in m-mode? (normal trap OR debug-enter)
csr.dcsr_rd(14) <= '0'; -- ebreakh: hypervisor mode not implemented
csr.dcsr_rd(13) <= '0'; -- ebreaks: supervisor mode not implemented
csr.dcsr_rd(12) <= csr.dcsr_ebreaku when (CPU_EXTENSION_RISCV_U = true) else '0'; -- ebreaku: what happens on ebreak in u-mode? (normal trap OR debug-enter)
csr.dcsr_rd(11) <= '0'; -- stepie: interrupts are disabled during single-stepping
csr.dcsr_rd(10) <= '0'; -- stopcount: counters increment as usual FIXME/TODO ???
csr.dcsr_rd(09) <= '0'; -- stoptime: timers increment as usual FIXME/TODO ???
csr.dcsr_rd(15) <= csr.dcsr_ebreakm; -- ebreakm: what happens on ebreak in m-mode? (normal trap OR debug-enter)
csr.dcsr_rd(14) <= '0'; -- ebreakh: hypervisor mode not implemented
csr.dcsr_rd(13) <= '0'; -- ebreaks: supervisor mode not implemented
csr.dcsr_rd(12) <= csr.dcsr_ebreaku when (CPU_EXTENSION_RISCV_U = true) else '0'; -- ebreaku: what happens on ebreak in u-mode? (normal trap OR debug-enter)
csr.dcsr_rd(11) <= '0'; -- stepie: interrupts are disabled during single-stepping
csr.dcsr_rd(10) <= '1'; -- stopcount: standard counters and HPMs are stopped when in debug mode
csr.dcsr_rd(09) <= '0'; -- stoptime: timers increment as usual
csr.dcsr_rd(08 downto 06) <= csr.dcsr_cause; -- debug mode entry cause
csr.dcsr_rd(05) <= '0'; -- reserved
csr.dcsr_rd(04) <= '0'; -- mprven: mstatus.mprv is ignored in debug mode
csr.dcsr_rd(03) <= '0'; -- nmip: no pending non-maskable interrupt
csr.dcsr_rd(02) <= csr.dcsr_step; -- step: single-step mode
csr.dcsr_rd(05) <= '0'; -- reserved
csr.dcsr_rd(04) <= '0'; -- mprven: mstatus.mprv is ignored in debug mode
csr.dcsr_rd(03) <= '0'; -- nmip: no pending non-maskable interrupt
csr.dcsr_rd(02) <= csr.dcsr_step; -- step: single-step mode
csr.dcsr_rd(01 downto 00) <= csr.dcsr_prv; -- prv: privilege mode when debug mode was entered
 
 
-- ****************************************************************************************************************************
-- Hardware Trigger Module (Part of the On-Chip Debugger)
-- ****************************************************************************************************************************
 
-- trigger to enter debug-mode: instruction address match (fire AFTER execution) --
hw_trigger_fire <= '1' when (CPU_EXTENSION_RISCV_DEBUG = true) and (csr.tdata1_exe = '1') and
(csr.tdata2(data_width_c-1 downto 1) = execute_engine.pc(data_width_c-1 downto 1)) else '0';
 
 
-- Match Control CSR (mcontrol @ tdata1) - Read-Back --------------------------------------
-- -------------------------------------------------------------------------------------------
csr.tdata1_rd(31 downto 28) <= "0010"; -- type: address(/data) match trigger
csr.tdata1_rd(27) <= '1'; -- dmode: only debug-mode can write tdata* registers
csr.tdata1_rd(26 downto 21) <= "000000"; -- maskmax: only exact values
csr.tdata1_rd(20) <= '0'; -- hit: feature not implemented
csr.tdata1_rd(19) <= '0'; -- select: fire on address match
csr.tdata1_rd(18) <= '1'; -- timing: trigger **after** executing the triggering instruction
csr.tdata1_rd(17 downto 16) <= "00"; -- sizelo: match against an access of any size
csr.tdata1_rd(15 downto 12) <= "0001"; -- action: enter debug mode on trigger
csr.tdata1_rd(11) <= '0'; -- chain: chaining not supported - there is only one trigger
csr.tdata1_rd(10 downto 07) <= "0000"; -- match: only full-address-match
csr.tdata1_rd(6) <= '1'; -- m: trigger enabled when in machine mode
csr.tdata1_rd(5) <= '0'; -- h: hypervisor mode not supported
csr.tdata1_rd(4) <= '0'; -- s: supervisor mode not supported
csr.tdata1_rd(3) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_U); -- u: trigger enabled when in user mode
csr.tdata1_rd(2) <= csr.tdata1_exe; -- execute: enable trigger
csr.tdata1_rd(1) <= '0'; -- store: store address or data matching not supported
csr.tdata1_rd(0) <= '0'; -- load: load address or data matching not supported
 
 
end neorv32_cpu_control_rtl;
/neorv32/trunk/rtl/core/neorv32_cpu_cp_cfu.vhd
0,0 → 1,189
-- #################################################################################################
-- # << NEORV32 - CPU Co-Processor: Custom (Instructions) Functions Unit >> #
-- # ********************************************************************************************* #
-- # Intended for user-defined custom RISC-V instructions (R2-type format only). See the CPU's #
-- # documentation for more information. #
-- # #
-- # NOTE: Take a look at the "software-counterpart" of this CFU example in 'sw/example/demo_cfu'. #
-- # #
-- # TODO: Maybe turn this into a wrapper for CFU-playground templates. #
-- # -> https://github.com/google/CFU-Playground #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
-- #################################################################################################
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
library neorv32;
use neorv32.neorv32_package.all;
 
entity neorv32_cpu_cp_cfu is
port (
-- global control --
clk_i : in std_ulogic; -- global clock, rising edge
rstn_i : in std_ulogic; -- global reset, low-active, async
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
start_i : in std_ulogic; -- trigger operation
-- data input --
rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
-- result and status --
res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
valid_o : out std_ulogic -- data output valid
);
end neorv32_cpu_cp_cfu;
 
architecture neorv32_cpu_cp_cfu_rtl of neorv32_cpu_cp_cfu is
 
-- CFU controller - do not modify --
type control_t is record
busy : std_ulogic; -- CFU is busy
done : std_ulogic; -- set to '1' when processing is done
result : std_ulogic_vector(data_width_c-1 downto 0); -- user's processing result (for write-back to register file)
funct3 : std_ulogic_vector(2 downto 0); -- "funct3" bit-field from custom instruction
funct7 : std_ulogic_vector(6 downto 0); -- "funct7" bit-field from custom instruction
end record;
signal control : control_t;
 
begin
 
-- CFU Controller -------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- This controller is required to handle the CPU/pipeline interface. Do not modify!
cfu_control: process(rstn_i, clk_i)
begin
if (rstn_i = '0') then
res_o <= (others => '0');
control.busy <= '0';
elsif rising_edge(clk_i) then
res_o <= (others => '0'); -- default
if (control.busy = '0') then -- idle
if (start_i = '1') then
control.busy <= '1';
end if;
else -- busy
if (control.done = '1') or (ctrl_i(ctrl_trap_c) = '1') then -- processing done? abort if trap
res_o <= control.result; -- actual output for only one cycle
control.busy <= '0';
end if;
end if;
end if;
end process cfu_control;
 
-- CPU feedback --
valid_o <= control.busy and control.done; -- set one cycle before result data
 
-- pack user-defined instruction function bits --
control.funct3 <= ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c);
control.funct7 <= ctrl_i(ctrl_ir_funct12_11_c downto ctrl_ir_funct12_5_c);
 
 
-- ****************************************************************************************************************************
-- Actual CFU user logic - Add your custom logic below
-- ****************************************************************************************************************************
 
-- The CFU only supports the R2-type RISC-V instruction format. This format consists of two source registers (rs1 and rs2),
-- a destination register (rd) and two "immediate" bit-fields (funct7 and funct3). It is up to the user to decide which
-- of these fields are actually used by the CFU logic.
--
-- The user logic of the CFU has access to the following pre-defined signals:
--
-- -------------------------------------------------------------------------------------------
-- Input Operands
-- -------------------------------------------------------------------------------------------
-- > rs1_i (input, 32-bit): source register 1
-- > rs2_i (input, 32-bit): source register 2
-- > control.funct3 (input, 3-bit): 3-bit function select / immediate, driven by instruction word's funct3 bit field
-- > control.funct7 (input, 7-bit): 7-bit function select / immediate, driven by instruction word's funct7 bit field
--
-- The two signal rs1_i and rs2_i provide the data read from the CPU's register file, which is adressed by the
-- instruction word's rs1 and rs2 bit-fields.
--
-- The actual CFU operation can be defined by using the funct3 and funct7 signals. Both signals are directly driven by
-- the according bit-fields of the custom instruction. Note that these signals represent "immediates" that have to be
-- static already at compile time. These immediates can be used to select the actual function to be executed or they
-- can be used as immediates for certain operations (like shift amounts, addresses or offsets).
--
-- [NOTE]: rs1_i and rs2_i are directly driven by the register file (block RAM). It is recommended to buffer these signals
-- using CFU-internal registers before using them for computations as the rs1 and rs2 nets need to drive a lot of logic
-- in the CPU.
--
-- [NOTE]: It is not possible for the CFU and it's according instruction words to cause any kind of exception. The CPU
-- control logic only verifies the custom instructions OPCODE and checks if the CFU is implemented at all. No combination
-- of funct7 and funct3 will cause an exception.
--
-- -------------------------------------------------------------------------------------------
-- Result output
-- -------------------------------------------------------------------------------------------
-- > control.result (output, 32-bit): processing result
--
-- When the CFU has finished computation, the data in the control.result signal will be written to the CPU's register
-- file. The destination register is addressed by the rd bit-field in the instruction. The CFU result output is
-- registered in the CFU controller (see above) so do not worry too much about increasing the CPU's critical path. ;)
--
-- -------------------------------------------------------------------------------------------
-- Control
-- -------------------------------------------------------------------------------------------
-- > rstn_i (input, 1-bit): asynchronous reset, low-active
-- > clk_i (input, 1-bit): main clock, triggering on rising edge
-- > start_i (input, 1-bit): operation trigger (start processing, high for one cycle)
-- > control.done (output, 1-bit): set high when processing is done
--
-- For pure-combinatorial instructions (without internal state) a subset of those signals is sufficient; see the minimal
-- example below. If the CFU shall also include states (like memories, registers or "buffers") the start_i signal can be
-- used to trigger a new CFU operation. As soon as all internal computations have completed, the control.done signal has
-- to be set to indicate completion. This will write the result data (control.result) to the CPU register file.
--
-- [IMPORTANT]: The control.done *has to be set at some time*, otherwise the CPU will be halted forever.
 
 
-- User Logic Example ---------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
user_logic_function_select: process(control, rs1_i, rs2_i)
begin
-- This is a simple ALU that implements four pure-combinatorial instructions.
-- The actual function to-be-executed is selected by the "funct3" bit-field of the custom instruction.
case control.funct3 is
when "000" => control.result <= bin_to_gray_f(rs1_i); -- funct3 = "000": convert rs1 from binary to gray
when "001" => control.result <= gray_to_bin_f(rs1_i); -- funct3 = "001": convert rs1 from gray to binary
when "010" => control.result <= bit_rev_f(rs1_i); -- funct3 = "010": bit-reversal of rs1
when "011" => control.result <= rs1_i xnor rs2_i; -- funct3 = "011": XNOR input operands
when others => control.result <= (others => '0'); -- not implemented, set to zero
end case;
end process user_logic_function_select;
 
-- processing done? --
control.done <= '1'; -- we are just doing pure-combinatorial data processing here, which is done "immediately"
 
 
end neorv32_cpu_cp_cfu_rtl;
/neorv32/trunk/rtl/core/neorv32_imem.entity.vhd
6,7 → 6,7
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
53,6 → 53,7
addr_i : in std_ulogic_vector(31 downto 0); -- address
data_i : in std_ulogic_vector(31 downto 0); -- data in
data_o : out std_ulogic_vector(31 downto 0); -- data out
ack_o : out std_ulogic -- transfer acknowledge
ack_o : out std_ulogic; -- transfer acknowledge
err_o : out std_ulogic -- transfer error
);
end neorv32_imem;
/neorv32/trunk/rtl/core/neorv32_package.vhd
44,8 → 44,9
constant ispace_base_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- default instruction memory address space base address
constant dspace_base_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- default data memory address space base address
 
-- CPU core --
constant dedicated_reset_c : boolean := false; -- use dedicated hardware reset value for UNCRITICAL registers (FALSE=reset value is irrelevant (might simplify HW), default; TRUE=defined LOW reset value)
-- use dedicated hardware reset value for UNCRITICAL registers --
-- FALSE=reset value is irrelevant (might simplify HW), default; TRUE=defined LOW reset value
constant dedicated_reset_c : boolean := false;
 
-- "critical" number of implemented PMP regions --
-- if more PMP regions (> pmp_num_regions_critical_c) are defined, another register stage is automatically inserted into the memory interfaces
53,7 → 54,8
constant pmp_num_regions_critical_c : natural := 8; -- default=8
 
-- "response time window" for processor-internal modules --
constant max_proc_int_response_time_c : natural := 15; -- cycles after which an *unacknowledged* internal bus access will timeout and trigger a bus fault exception (min 2)
-- = cycles after which an *unacknowledged* internal bus access will timeout and trigger a bus fault exception (min 2)
constant max_proc_int_response_time_c : natural := 15;
 
-- jtag tap - identifier --
constant jtag_tap_idcode_version_c : std_ulogic_vector(03 downto 0) := x"0"; -- version
63,7 → 65,7
-- Architecture Constants (do not modify!) ------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant data_width_c : natural := 32; -- native data path width - do not change!
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01060700"; -- no touchy!
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01060800"; -- no touchy!
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
 
-- Check if we're inside the Matrix -------------------------------------------------------
82,8 → 84,8
 
-- External Interface Types ---------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
type sdata_8x32_t is array (0 to 7) of std_ulogic_vector(31 downto 0);
type sdata_8x32r_t is array (0 to 7) of std_logic_vector(31 downto 0); -- resolved type
type sdata_8x32_t is array (0 to 7) of std_ulogic_vector(31 downto 0);
type sdata_8x32r_t is array (0 to 7) of std_logic_vector(31 downto 0); -- resolved type
 
-- Internal Interface Types ---------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
408,7 → 410,7
constant cmp_equal_c : natural := 0;
constant cmp_less_c : natural := 1; -- for signed and unsigned comparisons
 
-- RISC-V Opcode Layout -------------------------------------------------------------------
-- RISC-V 32-Bit Instruction Word Layout --------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant instr_opcode_lsb_c : natural := 0; -- opcode bit 0
constant instr_opcode_msb_c : natural := 6; -- opcode bit 6
454,6 → 456,9
constant opcode_atomic_c : std_ulogic_vector(6 downto 0) := "0101111"; -- atomic operations (A extension)
-- floating point operations (Zfinx-only) (F/D/H/Q) --
constant opcode_fop_c : std_ulogic_vector(6 downto 0) := "1010011"; -- dual/single operand instruction
-- official "custom0/1" RISC-V opcodes - free for custom instructions --
constant opcode_cust0_c : std_ulogic_vector(6 downto 0) := "0001011"; -- custom instructions 0
--constant opcode_cust1_c : std_ulogic_vector(6 downto 0) := "0101011"; -- custom instructions 1
 
-- RISC-V Funct3 --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
484,12 → 489,12
constant funct3_and_c : std_ulogic_vector(2 downto 0) := "111"; -- and
-- system/csr --
constant funct3_env_c : std_ulogic_vector(2 downto 0) := "000"; -- ecall, ebreak, mret, wfi, ...
constant funct3_csrrw_c : std_ulogic_vector(2 downto 0) := "001"; -- atomic r/w
constant funct3_csrrs_c : std_ulogic_vector(2 downto 0) := "010"; -- atomic read & set bit
constant funct3_csrrc_c : std_ulogic_vector(2 downto 0) := "011"; -- atomic read & clear bit
constant funct3_csrrwi_c : std_ulogic_vector(2 downto 0) := "101"; -- atomic r/w immediate
constant funct3_csrrsi_c : std_ulogic_vector(2 downto 0) := "110"; -- atomic read & set bit immediate
constant funct3_csrrci_c : std_ulogic_vector(2 downto 0) := "111"; -- atomic read & clear bit immediate
constant funct3_csrrw_c : std_ulogic_vector(2 downto 0) := "001"; -- csr r/w
constant funct3_csrrs_c : std_ulogic_vector(2 downto 0) := "010"; -- csr read & set bit
constant funct3_csrrc_c : std_ulogic_vector(2 downto 0) := "011"; -- csr read & clear bit
constant funct3_csrrwi_c : std_ulogic_vector(2 downto 0) := "101"; -- csr r/w immediate
constant funct3_csrrsi_c : std_ulogic_vector(2 downto 0) := "110"; -- csr read & set bit immediate
constant funct3_csrrci_c : std_ulogic_vector(2 downto 0) := "111"; -- csr read & clear bit immediate
-- fence --
constant funct3_fence_c : std_ulogic_vector(2 downto 0) := "000"; -- fence - order IO/memory access (->NOP)
constant funct3_fencei_c : std_ulogic_vector(2 downto 0) := "001"; -- fencei - instruction stream sync
497,25 → 502,25
-- RISC-V Funct12 -------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- system --
constant funct12_ecall_c : std_ulogic_vector(11 downto 0) := x"000"; -- ECALL
constant funct12_ebreak_c : std_ulogic_vector(11 downto 0) := x"001"; -- EBREAK
constant funct12_mret_c : std_ulogic_vector(11 downto 0) := x"302"; -- MRET
constant funct12_wfi_c : std_ulogic_vector(11 downto 0) := x"105"; -- WFI
constant funct12_dret_c : std_ulogic_vector(11 downto 0) := x"7b2"; -- DRET
constant funct12_ecall_c : std_ulogic_vector(11 downto 0) := x"000"; -- ecall
constant funct12_ebreak_c : std_ulogic_vector(11 downto 0) := x"001"; -- ebreak
constant funct12_mret_c : std_ulogic_vector(11 downto 0) := x"302"; -- mret
constant funct12_wfi_c : std_ulogic_vector(11 downto 0) := x"105"; -- wfi
constant funct12_dret_c : std_ulogic_vector(11 downto 0) := x"7b2"; -- dret
 
-- RISC-V Funct5 --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- atomic operations --
constant funct5_a_lr_c : std_ulogic_vector(4 downto 0) := "00010"; -- LR
constant funct5_a_sc_c : std_ulogic_vector(4 downto 0) := "00011"; -- SC
constant funct5_a_lr_c : std_ulogic_vector(4 downto 0) := "00010"; -- lr.w
constant funct5_a_sc_c : std_ulogic_vector(4 downto 0) := "00011"; -- sc.w
 
-- RISC-V Floating-Point Stuff ------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- formats --
constant float_single_c : std_ulogic_vector(1 downto 0) := "00"; -- single-precision (32-bit)
constant float_double_c : std_ulogic_vector(1 downto 0) := "01"; -- double-precision (64-bit)
constant float_half_c : std_ulogic_vector(1 downto 0) := "10"; -- half-precision (16-bit)
constant float_quad_c : std_ulogic_vector(1 downto 0) := "11"; -- quad-precision (128-bit)
--constant float_double_c : std_ulogic_vector(1 downto 0) := "01"; -- double-precision (64-bit)
--constant float_half_c : std_ulogic_vector(1 downto 0) := "10"; -- half-precision (16-bit)
--constant float_quad_c : std_ulogic_vector(1 downto 0) := "11"; -- quad-precision (128-bit)
 
-- number class flags --
constant fp_class_neg_inf_c : natural := 0; -- negative infinity
687,6 → 692,16
constant csr_pmpaddr61_c : std_ulogic_vector(11 downto 0) := x"3ed";
constant csr_pmpaddr62_c : std_ulogic_vector(11 downto 0) := x"3ee";
constant csr_pmpaddr63_c : std_ulogic_vector(11 downto 0) := x"3ef";
-- trigger module registers --
constant csr_class_trigger_c : std_ulogic_vector(07 downto 0) := x"7a"; -- trigger registers
constant csr_tselect_c : std_ulogic_vector(11 downto 0) := x"7a0";
constant csr_tdata1_c : std_ulogic_vector(11 downto 0) := x"7a1";
constant csr_tdata2_c : std_ulogic_vector(11 downto 0) := x"7a2";
constant csr_tdata3_c : std_ulogic_vector(11 downto 0) := x"7a3";
constant csr_tinfo_c : std_ulogic_vector(11 downto 0) := x"7a4";
constant csr_tcontrol_c : std_ulogic_vector(11 downto 0) := x"7a5";
constant csr_mcontext_c : std_ulogic_vector(11 downto 0) := x"7a8";
constant csr_scontext_c : std_ulogic_vector(11 downto 0) := x"7aa";
-- debug mode registers --
constant csr_class_debug_c : std_ulogic_vector(09 downto 0) := x"7b" & "00"; -- debug registers
constant csr_dcsr_c : std_ulogic_vector(11 downto 0) := x"7b0";
774,13 → 789,17
constant csr_mhartid_c : std_ulogic_vector(11 downto 0) := x"f14";
constant csr_mconfigptr_c : std_ulogic_vector(11 downto 0) := x"f15";
 
-- Co-Processor IDs -----------------------------------------------------------------------
-- <<< NEORV32-specific (custom) read-only CSRs >>> ---
-- machine extended ISA extensionss information --
constant csr_mxisa_c : std_ulogic_vector(11 downto 0) := x"fc0";
 
-- CPU Co-Processor IDs -------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant cp_sel_shifter_c : std_ulogic_vector(2 downto 0) := "000"; -- CP0: shift operations (base ISA)
constant cp_sel_muldiv_c : std_ulogic_vector(2 downto 0) := "001"; -- CP1: multiplication/division operations ('M' extensions)
constant cp_sel_bitmanip_c : std_ulogic_vector(2 downto 0) := "010"; -- CP2: bit manipulation ('B' extensions)
constant cp_sel_fpu_c : std_ulogic_vector(2 downto 0) := "011"; -- CP3: floating-point unit ('Zfinx' extension)
--constant cp_sel_res0_c : std_ulogic_vector(2 downto 0) := "100"; -- CP4: reserved
constant cp_sel_cfu_c : std_ulogic_vector(2 downto 0) := "100"; -- CP4: custom instructions CFU ('Zxcfu' extension)
--constant cp_sel_res1_c : std_ulogic_vector(2 downto 0) := "101"; -- CP5: reserved
--constant cp_sel_res2_c : std_ulogic_vector(2 downto 0) := "110"; -- CP6: reserved
--constant cp_sel_res3_c : std_ulogic_vector(2 downto 0) := "111"; -- CP7: reserved
806,7 → 825,7
-- -------------------------------------------------------------------------------------------
-- MSB: 1 = async exception (IRQ), 0 = sync exception (e.g. ebreak)
-- MSB-1: 1 = entry to debug mode, 0 = normal trapping
-- RISC-V compliant sync. exceptions --
-- RISC-V compliant synchronous exceptions --
constant trap_ima_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00000"; -- 0.0: instruction misaligned
constant trap_iba_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00001"; -- 0.1: instruction access fault
constant trap_iil_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00010"; -- 0.2: illegal instruction
816,12 → 835,20
constant trap_sma_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00110"; -- 0.6: store address misaligned
constant trap_sbe_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00111"; -- 0.7: store access fault
constant trap_uenv_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "01000"; -- 0.8: environment call from u-mode
--constant trap_senv_c x : std_ulogic_vector(6 downto 0) := "0" & "0" & "01001"; -- 0.9: environment call from s-mode
--constant trap_henv_c x : std_ulogic_vector(6 downto 0) := "0" & "0" & "01010"; -- 0.10: environment call from h-mode
constant trap_menv_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "01011"; -- 0.11: environment call from m-mode
-- RISC-V compliant interrupts (async. exceptions) --
--constant trap_ipf_c x : std_ulogic_vector(6 downto 0) := "0" & "0" & "01100"; -- 0.12: instruction page fault
--constant trap_lpf_c x : std_ulogic_vector(6 downto 0) := "0" & "0" & "01101"; -- 0.13: load page fault
--constant trap_???_c x : std_ulogic_vector(6 downto 0) := "0" & "0" & "01110"; -- 0.14: reserved
--constant trap_lpf_c x : std_ulogic_vector(6 downto 0) := "0" & "0" & "01111"; -- 0.15: store page fault
-- NEORV32-specific (custom) synchronous exceptions --
-- none implemented yet
-- RISC-V compliant asynchronous exceptions (interrupts) --
constant trap_msi_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "00011"; -- 1.3: machine software interrupt
constant trap_mti_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "00111"; -- 1.7: machine timer interrupt
constant trap_mei_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "01011"; -- 1.11: machine external interrupt
-- NEORV32-specific (custom) interrupts (async. exceptions) --
-- NEORV32-specific (custom) asynchronous exceptions (interrupts) --
constant trap_firq0_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "10000"; -- 1.16: fast interrupt 0
constant trap_firq1_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "10001"; -- 1.17: fast interrupt 1
constant trap_firq2_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "10010"; -- 1.18: fast interrupt 2
838,10 → 865,11
constant trap_firq13_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "11101"; -- 1.29: fast interrupt 13
constant trap_firq14_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "11110"; -- 1.30: fast interrupt 14
constant trap_firq15_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "11111"; -- 1.31: fast interrupt 15
-- entering debug mode - cause --
constant trap_db_break_c : std_ulogic_vector(6 downto 0) := "0" & "1" & "00010"; -- break instruction (sync / EXCEPTION)
constant trap_db_halt_c : std_ulogic_vector(6 downto 0) := "1" & "1" & "00011"; -- external halt request (async / IRQ)
constant trap_db_step_c : std_ulogic_vector(6 downto 0) := "1" & "1" & "00100"; -- single-stepping (async / IRQ)
-- entering debug mode (sync./async. exceptions) --
constant trap_db_break_c : std_ulogic_vector(6 downto 0) := "0" & "1" & "00001"; -- break instruction (sync)
constant trap_db_hw_c : std_ulogic_vector(6 downto 0) := "0" & "1" & "00010"; -- hardware trigger (sync)
constant trap_db_halt_c : std_ulogic_vector(6 downto 0) := "1" & "1" & "00011"; -- external halt request (async)
constant trap_db_step_c : std_ulogic_vector(6 downto 0) := "1" & "1" & "00100"; -- single-stepping (async)
 
-- CPU Control Exception System -----------------------------------------------------------
-- -------------------------------------------------------------------------------------------
858,8 → 886,9
constant exception_laccess_c : natural := 9; -- load access fault
-- for debug mode only --
constant exception_db_break_c : natural := 10; -- enter debug mode via ebreak instruction ("sync EXCEPTION")
constant exception_db_hw_c : natural := 11; -- enter debug mode via hw trigger ("sync EXCEPTION")
--
constant exception_width_c : natural := 11; -- length of this list in bits
constant exception_width_c : natural := 12; -- length of this list in bits
-- interrupt source bits --
constant interrupt_msw_irq_c : natural := 0; -- machine software interrupt
constant interrupt_mtime_irq_c : natural := 1; -- machine timer interrupt
911,7 → 940,7
--
constant hpmcnt_event_size_c : natural := 15; -- length of this list
 
-- Clock Generator ------------------------------------------------------------------------
-- SoC Clock Generator --------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant clk_div2_c : natural := 0;
constant clk_div4_c : natural := 1;
945,7 → 974,8
CPU_EXTENSION_RISCV_Zihpm : boolean := false; -- implement hardware performance monitors?
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
CPU_EXTENSION_RISCV_Zmmul : boolean := false; -- implement multiply-only M sub-extension?
-- Extension Options --
CPU_EXTENSION_RISCV_Zxcfu : boolean := false; -- implement custom (instr.) functions unit?
-- Tuning Options --
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
CPU_CNT_WIDTH : natural := 64; -- total width of CPU cycle and instret counters (0..64)
1062,8 → 1092,8
spi_sdi_i : in std_ulogic := 'U'; -- controller data in, peripheral data out
spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS
-- TWI (available if IO_TWI_EN = true) --
twi_sda_io : inout std_logic := 'U'; -- twi serial data line
twi_scl_io : inout std_logic := 'U'; -- twi serial clock line
twi_sda_io : inout std_logic; -- twi serial data line
twi_scl_io : inout std_logic; -- twi serial clock line
-- PWM (available if IO_PWM_NUM_CH > 0) --
pwm_o : out std_ulogic_vector(59 downto 0); -- pwm channels
-- Custom Functions Subsystem IO --
1104,8 → 1134,9
CPU_EXTENSION_RISCV_Zihpm : boolean; -- implement hardware performance monitors?
CPU_EXTENSION_RISCV_Zifencei : boolean; -- implement instruction stream sync.?
CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension?
CPU_EXTENSION_RISCV_Zxcfu : boolean; -- implement custom (instr.) functions unit?
CPU_EXTENSION_RISCV_DEBUG : boolean; -- implement CPU debug mode?
-- Extension Options --
-- Tuning Options --
FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier
FAST_SHIFT_EN : boolean; -- use barrel shifter for shift operations
CPU_CNT_WIDTH : natural; -- total width of CPU cycle and instret counters (0..64)
1181,8 → 1212,11
CPU_EXTENSION_RISCV_Zihpm : boolean; -- implement hardware performance monitors?
CPU_EXTENSION_RISCV_Zifencei : boolean; -- implement instruction stream sync.?
CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension?
CPU_EXTENSION_RISCV_Zxcfu : boolean; -- implement custom (instr.) functions unit?
CPU_EXTENSION_RISCV_DEBUG : boolean; -- implement CPU debug mode?
-- Extension Options --
FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier
FAST_SHIFT_EN : boolean; -- use barrel shifter for shift operations
CPU_CNT_WIDTH : natural; -- total width of CPU cycle and instret counters (0..64)
CPU_IPB_ENTRIES : natural; -- entries is instruction prefetch buffer, has to be a power of 2
-- Physical memory protection (PMP) --
1267,6 → 1301,7
CPU_EXTENSION_RISCV_M : boolean; -- implement mul/div extension?
CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension?
CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT reg!)
CPU_EXTENSION_RISCV_Zxcfu : boolean; -- implement custom (instr.) functions unit?
-- Extension Options --
FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier
FAST_SHIFT_EN : boolean -- use barrel shifter for shift operations
1379,6 → 1414,24
);
end component;
 
-- Component: CPU Co-Processor Custom (Instr.) Functions Unit ('Zxcfu' extension) ---------
-- -------------------------------------------------------------------------------------------
component neorv32_cpu_cp_cfu
port (
-- global control --
clk_i : in std_ulogic; -- global clock, rising edge
rstn_i : in std_ulogic; -- global reset, low-active, async
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
start_i : in std_ulogic; -- trigger operation
-- data input --
rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
-- result and status --
res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
valid_o : out std_ulogic -- data output valid
);
end component;
 
-- Component: CPU Bus Interface -----------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component neorv32_cpu_bus
1574,7 → 1627,8
addr_i : in std_ulogic_vector(31 downto 0); -- address
data_i : in std_ulogic_vector(31 downto 0); -- data in
data_o : out std_ulogic_vector(31 downto 0); -- data out
ack_o : out std_ulogic -- transfer acknowledge
ack_o : out std_ulogic; -- transfer acknowledge
err_o : out std_ulogic -- transfer error
);
end component;
 
1606,9 → 1660,11
port (
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
addr_i : in std_ulogic_vector(31 downto 0); -- address
data_o : out std_ulogic_vector(31 downto 0); -- data out
ack_o : out std_ulogic -- transfer acknowledge
ack_o : out std_ulogic; -- transfer acknowledge
err_o : out std_ulogic -- transfer error
);
end component;
 
2017,54 → 2073,42
component neorv32_sysinfo
generic (
-- General --
CLOCK_FREQUENCY : natural; -- clock frequency of clk_i in Hz
INT_BOOTLOADER_EN : boolean; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT reg!)
CPU_EXTENSION_RISCV_Zicsr : boolean; -- implement CSR system?
CPU_EXTENSION_RISCV_Zicntr : boolean; -- implement base counters?
CPU_EXTENSION_RISCV_Zihpm : boolean; -- implement hardware performance monitors?
CPU_EXTENSION_RISCV_Zifencei : boolean; -- implement instruction stream sync.?
CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension?
CPU_EXTENSION_RISCV_DEBUG : boolean; -- implement CPU debug mode?
-- Extension Options --
FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier
FAST_SHIFT_EN : boolean; -- use barrel shifter for shift operations
CPU_CNT_WIDTH : natural; -- total width of CPU cycle and instret counters (0..64)
CLOCK_FREQUENCY : natural; -- clock frequency of clk_i in Hz
INT_BOOTLOADER_EN : boolean; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
-- Physical memory protection (PMP) --
PMP_NUM_REGIONS : natural; -- number of regions (0..64)
PMP_NUM_REGIONS : natural; -- number of regions (0..64)
-- Internal Instruction memory --
MEM_INT_IMEM_EN : boolean; -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE : natural; -- size of processor-internal instruction memory in bytes
MEM_INT_IMEM_EN : boolean; -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE : natural; -- size of processor-internal instruction memory in bytes
-- Internal Data memory --
MEM_INT_DMEM_EN : boolean; -- implement processor-internal data memory
MEM_INT_DMEM_SIZE : natural; -- size of processor-internal data memory in bytes
MEM_INT_DMEM_EN : boolean; -- implement processor-internal data memory
MEM_INT_DMEM_SIZE : natural; -- size of processor-internal data memory in bytes
-- Internal Cache memory --
ICACHE_EN : boolean; -- implement instruction cache
ICACHE_NUM_BLOCKS : natural; -- i-cache: number of blocks (min 2), has to be a power of 2
ICACHE_BLOCK_SIZE : natural; -- i-cache: block size in bytes (min 4), has to be a power of 2
ICACHE_ASSOCIATIVITY : natural; -- i-cache: associativity (min 1), has to be a power 2
ICACHE_EN : boolean; -- implement instruction cache
ICACHE_NUM_BLOCKS : natural; -- i-cache: number of blocks (min 2), has to be a power of 2
ICACHE_BLOCK_SIZE : natural; -- i-cache: block size in bytes (min 4), has to be a power of 2
ICACHE_ASSOCIATIVITY : natural; -- i-cache: associativity (min 1), has to be a power 2
-- External memory interface --
MEM_EXT_EN : boolean; -- implement external memory bus interface?
MEM_EXT_BIG_ENDIAN : boolean; -- byte order: true=big-endian, false=little-endian
MEM_EXT_EN : boolean; -- implement external memory bus interface?
MEM_EXT_BIG_ENDIAN : boolean; -- byte order: true=big-endian, false=little-endian
-- On-Chip Debugger --
ON_CHIP_DEBUGGER_EN : boolean; -- implement OCD?
ON_CHIP_DEBUGGER_EN : boolean; -- implement OCD?
-- Processor peripherals --
IO_GPIO_EN : boolean; -- implement general purpose input/output port unit (GPIO)?
IO_MTIME_EN : boolean; -- implement machine system timer (MTIME)?
IO_UART0_EN : boolean; -- implement primary universal asynchronous receiver/transmitter (UART0)?
IO_UART1_EN : boolean; -- implement secondary universal asynchronous receiver/transmitter (UART1)?
IO_SPI_EN : boolean; -- implement serial peripheral interface (SPI)?
IO_TWI_EN : boolean; -- implement two-wire interface (TWI)?
IO_PWM_NUM_CH : natural; -- number of PWM channels to implement
IO_WDT_EN : boolean; -- implement watch dog timer (WDT)?
IO_TRNG_EN : boolean; -- implement true random number generator (TRNG)?
IO_CFS_EN : boolean; -- implement custom functions subsystem (CFS)?
IO_SLINK_EN : boolean; -- implement stream link interface?
IO_NEOLED_EN : boolean; -- implement NeoPixel-compatible smart LED interface (NEOLED)?
IO_XIRQ_NUM_CH : natural; -- number of external interrupt (XIRQ) channels to implement
IO_GPTMR_EN : boolean; -- implement general purpose timer (GPTMR)?
IO_XIP_EN : boolean -- implement execute in place module (XIP)?
IO_GPIO_EN : boolean; -- implement general purpose input/output port unit (GPIO)?
IO_MTIME_EN : boolean; -- implement machine system timer (MTIME)?
IO_UART0_EN : boolean; -- implement primary universal asynchronous receiver/transmitter (UART0)?
IO_UART1_EN : boolean; -- implement secondary universal asynchronous receiver/transmitter (UART1)?
IO_SPI_EN : boolean; -- implement serial peripheral interface (SPI)?
IO_TWI_EN : boolean; -- implement two-wire interface (TWI)?
IO_PWM_NUM_CH : natural; -- number of PWM channels to implement
IO_WDT_EN : boolean; -- implement watch dog timer (WDT)?
IO_TRNG_EN : boolean; -- implement true random number generator (TRNG)?
IO_CFS_EN : boolean; -- implement custom functions subsystem (CFS)?
IO_SLINK_EN : boolean; -- implement stream link interface?
IO_NEOLED_EN : boolean; -- implement NeoPixel-compatible smart LED interface (NEOLED)?
IO_XIRQ_NUM_CH : natural; -- number of external interrupt (XIRQ) channels to implement
IO_GPTMR_EN : boolean; -- implement general purpose timer (GPTMR)?
IO_XIP_EN : boolean -- implement execute in place module (XIP)?
);
port (
-- host access --
/neorv32/trunk/rtl/core/neorv32_sysinfo.vhd
45,54 → 45,42
entity neorv32_sysinfo is
generic (
-- General --
CLOCK_FREQUENCY : natural; -- clock frequency of clk_i in Hz
INT_BOOTLOADER_EN : boolean; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT reg!)
CPU_EXTENSION_RISCV_Zicsr : boolean; -- implement CSR system?
CPU_EXTENSION_RISCV_Zicntr : boolean; -- implement base counters?
CPU_EXTENSION_RISCV_Zihpm : boolean; -- implement hardware performance monitors?
CPU_EXTENSION_RISCV_Zifencei : boolean; -- implement instruction stream sync.?
CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension?
CPU_EXTENSION_RISCV_DEBUG : boolean; -- implement CPU debug mode?
-- Extension Options --
FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier
FAST_SHIFT_EN : boolean; -- use barrel shifter for shift operations
CPU_CNT_WIDTH : natural; -- total width of CPU cycle and instret counters (0..64)
CLOCK_FREQUENCY : natural; -- clock frequency of clk_i in Hz
INT_BOOTLOADER_EN : boolean; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
-- Physical memory protection (PMP) --
PMP_NUM_REGIONS : natural; -- number of regions (0..64)
PMP_NUM_REGIONS : natural; -- number of regions (0..64)
-- Internal Instruction memory --
MEM_INT_IMEM_EN : boolean; -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE : natural; -- size of processor-internal instruction memory in bytes
MEM_INT_IMEM_EN : boolean; -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE : natural; -- size of processor-internal instruction memory in bytes
-- Internal Data memory --
MEM_INT_DMEM_EN : boolean; -- implement processor-internal data memory
MEM_INT_DMEM_SIZE : natural; -- size of processor-internal data memory in bytes
MEM_INT_DMEM_EN : boolean; -- implement processor-internal data memory
MEM_INT_DMEM_SIZE : natural; -- size of processor-internal data memory in bytes
-- Internal Cache memory --
ICACHE_EN : boolean; -- implement instruction cache
ICACHE_NUM_BLOCKS : natural; -- i-cache: number of blocks (min 2), has to be a power of 2
ICACHE_BLOCK_SIZE : natural; -- i-cache: block size in bytes (min 4), has to be a power of 2
ICACHE_ASSOCIATIVITY : natural; -- i-cache: associativity (min 1), has to be a power 2
ICACHE_EN : boolean; -- implement instruction cache
ICACHE_NUM_BLOCKS : natural; -- i-cache: number of blocks (min 2), has to be a power of 2
ICACHE_BLOCK_SIZE : natural; -- i-cache: block size in bytes (min 4), has to be a power of 2
ICACHE_ASSOCIATIVITY : natural; -- i-cache: associativity (min 1), has to be a power 2
-- External memory interface --
MEM_EXT_EN : boolean; -- implement external memory bus interface?
MEM_EXT_BIG_ENDIAN : boolean; -- byte order: true=big-endian, false=little-endian
MEM_EXT_EN : boolean; -- implement external memory bus interface?
MEM_EXT_BIG_ENDIAN : boolean; -- byte order: true=big-endian, false=little-endian
-- On-Chip Debugger --
ON_CHIP_DEBUGGER_EN : boolean; -- implement OCD?
ON_CHIP_DEBUGGER_EN : boolean; -- implement OCD?
-- Processor peripherals --
IO_GPIO_EN : boolean; -- implement general purpose input/output port unit (GPIO)?
IO_MTIME_EN : boolean; -- implement machine system timer (MTIME)?
IO_UART0_EN : boolean; -- implement primary universal asynchronous receiver/transmitter (UART0)?
IO_UART1_EN : boolean; -- implement secondary universal asynchronous receiver/transmitter (UART1)?
IO_SPI_EN : boolean; -- implement serial peripheral interface (SPI)?
IO_TWI_EN : boolean; -- implement two-wire interface (TWI)?
IO_PWM_NUM_CH : natural; -- number of PWM channels to implement
IO_WDT_EN : boolean; -- implement watch dog timer (WDT)?
IO_TRNG_EN : boolean; -- implement true random number generator (TRNG)?
IO_CFS_EN : boolean; -- implement custom functions subsystem (CFS)?
IO_SLINK_EN : boolean; -- implement stream link interface?
IO_NEOLED_EN : boolean; -- implement NeoPixel-compatible smart LED interface (NEOLED)?
IO_XIRQ_NUM_CH : natural; -- number of external interrupt (XIRQ) channels to implement
IO_GPTMR_EN : boolean; -- implement general purpose timer (GPTMR)?
IO_XIP_EN : boolean -- implement execute in place module (XIP)?
IO_GPIO_EN : boolean; -- implement general purpose input/output port unit (GPIO)?
IO_MTIME_EN : boolean; -- implement machine system timer (MTIME)?
IO_UART0_EN : boolean; -- implement primary universal asynchronous receiver/transmitter (UART0)?
IO_UART1_EN : boolean; -- implement secondary universal asynchronous receiver/transmitter (UART1)?
IO_SPI_EN : boolean; -- implement serial peripheral interface (SPI)?
IO_TWI_EN : boolean; -- implement two-wire interface (TWI)?
IO_PWM_NUM_CH : natural; -- number of PWM channels to implement
IO_WDT_EN : boolean; -- implement watch dog timer (WDT)?
IO_TRNG_EN : boolean; -- implement true random number generator (TRNG)?
IO_CFS_EN : boolean; -- implement custom functions subsystem (CFS)?
IO_SLINK_EN : boolean; -- implement stream link interface?
IO_NEOLED_EN : boolean; -- implement NeoPixel-compatible smart LED interface (NEOLED)?
IO_XIRQ_NUM_CH : natural; -- number of external interrupt (XIRQ) channels to implement
IO_GPTMR_EN : boolean; -- implement general purpose timer (GPTMR)?
IO_XIP_EN : boolean -- implement execute in place module (XIP)?
);
port (
-- host access --
137,24 → 125,8
-- SYSINFO(0): Processor (primary) clock frequency --
sysinfo_mem(0) <= std_ulogic_vector(to_unsigned(CLOCK_FREQUENCY, 32));
 
-- SYSINFO(1): CPU configuration --
sysinfo_mem(1)(00) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicsr); -- Zicsr
sysinfo_mem(1)(01) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zifencei); -- Zifencei
sysinfo_mem(1)(02) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zmmul); -- Zmmul
--
sysinfo_mem(1)(04 downto 03) <= (others => '0'); -- reserved
--
sysinfo_mem(1)(05) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zfinx); -- Zfinx ("F-alternative")
sysinfo_mem(1)(06) <= bool_to_ulogic_f(boolean(CPU_CNT_WIDTH /= 64)); -- reduced-size CPU counters (Zxscnt)
sysinfo_mem(1)(07) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicntr); -- base CPU counter
sysinfo_mem(1)(08) <= bool_to_ulogic_f(boolean(PMP_NUM_REGIONS > 0)); -- PMP (physical memory protection)
sysinfo_mem(1)(09) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zihpm); -- HPM (hardware performance monitors)
sysinfo_mem(1)(10) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_DEBUG); -- RISC-V debug mode
--
sysinfo_mem(1)(29 downto 11) <= (others => '0'); -- reserved
-- misc --
sysinfo_mem(1)(30) <= bool_to_ulogic_f(FAST_MUL_EN); -- DSP-based multiplication (M extension only)
sysinfo_mem(1)(31) <= bool_to_ulogic_f(FAST_SHIFT_EN); -- parallel logic for shifts (like barrel shifters)
-- SYSINFO(1): reserved --
sysinfo_mem(1) <= (others => '0'); -- reserved
 
-- SYSINFO(2): Implemented processor devices/features --
-- Memory --
/neorv32/trunk/rtl/core/neorv32_top.vhd
67,8 → 67,9
CPU_EXTENSION_RISCV_Zihpm : boolean := false; -- implement hardware performance monitors?
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
CPU_EXTENSION_RISCV_Zmmul : boolean := false; -- implement multiply-only M sub-extension?
CPU_EXTENSION_RISCV_Zxcfu : boolean := false; -- implement custom (instr.) functions unit?
 
-- Extension Options --
-- Tuning Options --
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
CPU_CNT_WIDTH : natural := 64; -- total width of CPU cycle and instret counters (0..64)
205,8 → 206,8
spi_csn_o : out std_ulogic_vector(07 downto 0); -- chip-select
 
-- TWI (available if IO_TWI_EN = true) --
twi_sda_io : inout std_logic := 'U'; -- twi serial data line
twi_scl_io : inout std_logic := 'U'; -- twi serial clock line
twi_sda_io : inout std_logic; -- twi serial data line
twi_scl_io : inout std_logic; -- twi serial clock line
 
-- PWM (available if IO_PWM_NUM_CH > 0) --
pwm_o : out std_ulogic_vector(59 downto 0); -- pwm channels
492,6 → 493,7
CPU_EXTENSION_RISCV_Zihpm => CPU_EXTENSION_RISCV_Zihpm, -- implement hardware performance monitors?
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
CPU_EXTENSION_RISCV_Zmmul => CPU_EXTENSION_RISCV_Zmmul, -- implement multiply-only M sub-extension?
CPU_EXTENSION_RISCV_Zxcfu => CPU_EXTENSION_RISCV_Zxcfu, -- implement custom (instr.) functions unit?
CPU_EXTENSION_RISCV_DEBUG => ON_CHIP_DEBUGGER_EN, -- implement CPU debug mode?
-- Extension Options --
FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier
746,9 → 748,9
addr_i => p_bus.addr, -- address
data_i => p_bus.wdata, -- data in
data_o => resp_bus(RESP_IMEM).rdata, -- data out
ack_o => resp_bus(RESP_IMEM).ack -- transfer acknowledge
ack_o => resp_bus(RESP_IMEM).ack, -- transfer acknowledge
err_o => resp_bus(RESP_IMEM).err -- transfer error
);
resp_bus(RESP_IMEM).err <= '0'; -- no access error possible
end generate;
 
neorv32_int_imem_inst_false:
796,11 → 798,12
port map (
clk_i => clk_i, -- global clock line
rden_i => p_bus.re, -- read enable
wren_i => p_bus.we, -- write enable
addr_i => p_bus.addr, -- address
data_o => resp_bus(RESP_BOOTROM).rdata, -- data out
ack_o => resp_bus(RESP_BOOTROM).ack -- transfer acknowledge
ack_o => resp_bus(RESP_BOOTROM).ack, -- transfer acknowledge
err_o => resp_bus(RESP_BOOTROM).err -- transfer error
);
resp_bus(RESP_BOOTROM).err <= '0'; -- no access error possible
end generate;
 
neorv32_boot_rom_inst_false:
1494,54 → 1497,42
neorv32_sysinfo_inst: neorv32_sysinfo
generic map (
-- General --
CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz
INT_BOOTLOADER_EN => INT_BOOTLOADER_EN, -- implement processor-internal bootloader?
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, -- implement 32-bit floating-point extension (using INT reg!)
CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
CPU_EXTENSION_RISCV_Zicntr => CPU_EXTENSION_RISCV_Zicntr, -- implement base counters?
CPU_EXTENSION_RISCV_Zihpm => CPU_EXTENSION_RISCV_Zihpm, -- implement hardware performance monitors?
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
CPU_EXTENSION_RISCV_Zmmul => CPU_EXTENSION_RISCV_Zmmul, -- implement multiply-only M sub-extension?
CPU_EXTENSION_RISCV_DEBUG => ON_CHIP_DEBUGGER_EN, -- implement CPU debug mode?
-- Extension Options --
FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier
FAST_SHIFT_EN => FAST_SHIFT_EN, -- use barrel shifter for shift operations
CPU_CNT_WIDTH => CPU_CNT_WIDTH, -- total width of CPU cycle and instret counters (0..64)
CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz
INT_BOOTLOADER_EN => INT_BOOTLOADER_EN, -- implement processor-internal bootloader?
-- Physical memory protection (PMP) --
PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..64)
PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..64)
-- internal Instruction memory --
MEM_INT_IMEM_EN => MEM_INT_IMEM_EN, -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes
MEM_INT_IMEM_EN => MEM_INT_IMEM_EN, -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes
-- Internal Data memory --
MEM_INT_DMEM_EN => MEM_INT_DMEM_EN, -- implement processor-internal data memory
MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes
MEM_INT_DMEM_EN => MEM_INT_DMEM_EN, -- implement processor-internal data memory
MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes
-- Internal Cache memory --
ICACHE_EN => ICACHE_EN, -- implement instruction cache
ICACHE_NUM_BLOCKS => ICACHE_NUM_BLOCKS, -- i-cache: number of blocks (min 2), has to be a power of 2
ICACHE_BLOCK_SIZE => ICACHE_BLOCK_SIZE, -- i-cache: block size in bytes (min 4), has to be a power of 2
ICACHE_ASSOCIATIVITY => ICACHE_ASSOCIATIVITY, -- i-cache: associativity (min 1), has to be a power 2
ICACHE_EN => ICACHE_EN, -- implement instruction cache
ICACHE_NUM_BLOCKS => ICACHE_NUM_BLOCKS, -- i-cache: number of blocks (min 2), has to be a power of 2
ICACHE_BLOCK_SIZE => ICACHE_BLOCK_SIZE, -- i-cache: block size in bytes (min 4), has to be a power of 2
ICACHE_ASSOCIATIVITY => ICACHE_ASSOCIATIVITY, -- i-cache: associativity (min 1), has to be a power 2
-- External memory interface --
MEM_EXT_EN => MEM_EXT_EN, -- implement external memory bus interface?
MEM_EXT_BIG_ENDIAN => MEM_EXT_BIG_ENDIAN, -- byte order: true=big-endian, false=little-endian
MEM_EXT_EN => MEM_EXT_EN, -- implement external memory bus interface?
MEM_EXT_BIG_ENDIAN => MEM_EXT_BIG_ENDIAN, -- byte order: true=big-endian, false=little-endian
-- On-Chip Debugger --
ON_CHIP_DEBUGGER_EN => ON_CHIP_DEBUGGER_EN, -- implement OCD?
ON_CHIP_DEBUGGER_EN => ON_CHIP_DEBUGGER_EN, -- implement OCD?
-- Processor peripherals --
IO_GPIO_EN => IO_GPIO_EN, -- implement general purpose input/output port unit (GPIO)?
IO_MTIME_EN => IO_MTIME_EN, -- implement machine system timer (MTIME)?
IO_UART0_EN => IO_UART0_EN, -- implement primary universal asynchronous receiver/transmitter (UART0)?
IO_UART1_EN => IO_UART1_EN, -- implement secondary universal asynchronous receiver/transmitter (UART1)?
IO_SPI_EN => IO_SPI_EN, -- implement serial peripheral interface (SPI)?
IO_TWI_EN => IO_TWI_EN, -- implement two-wire interface (TWI)?
IO_PWM_NUM_CH => IO_PWM_NUM_CH, -- number of PWM channels to implement
IO_WDT_EN => IO_WDT_EN, -- implement watch dog timer (WDT)?
IO_TRNG_EN => IO_TRNG_EN, -- implement true random number generator (TRNG)?
IO_CFS_EN => IO_CFS_EN, -- implement custom functions subsystem (CFS)?
IO_SLINK_EN => io_slink_en_c, -- implement stream link interface?
IO_NEOLED_EN => IO_NEOLED_EN, -- implement NeoPixel-compatible smart LED interface (NEOLED)?
IO_XIRQ_NUM_CH => XIRQ_NUM_CH, -- number of external interrupt (XIRQ) channels to implement
IO_GPTMR_EN => IO_GPTMR_EN, -- implement general purpose timer (GPTMR)?
IO_XIP_EN => IO_XIP_EN -- implement execute in place module (XIP)?
IO_GPIO_EN => IO_GPIO_EN, -- implement general purpose input/output port unit (GPIO)?
IO_MTIME_EN => IO_MTIME_EN, -- implement machine system timer (MTIME)?
IO_UART0_EN => IO_UART0_EN, -- implement primary universal asynchronous receiver/transmitter (UART0)?
IO_UART1_EN => IO_UART1_EN, -- implement secondary universal asynchronous receiver/transmitter (UART1)?
IO_SPI_EN => IO_SPI_EN, -- implement serial peripheral interface (SPI)?
IO_TWI_EN => IO_TWI_EN, -- implement two-wire interface (TWI)?
IO_PWM_NUM_CH => IO_PWM_NUM_CH, -- number of PWM channels to implement
IO_WDT_EN => IO_WDT_EN, -- implement watch dog timer (WDT)?
IO_TRNG_EN => IO_TRNG_EN, -- implement true random number generator (TRNG)?
IO_CFS_EN => IO_CFS_EN, -- implement custom functions subsystem (CFS)?
IO_SLINK_EN => io_slink_en_c, -- implement stream link interface?
IO_NEOLED_EN => IO_NEOLED_EN, -- implement NeoPixel-compatible smart LED interface (NEOLED)?
IO_XIRQ_NUM_CH => XIRQ_NUM_CH, -- number of external interrupt (XIRQ) channels to implement
IO_GPTMR_EN => IO_GPTMR_EN, -- implement general purpose timer (GPTMR)?
IO_XIP_EN => IO_XIP_EN -- implement execute in place module (XIP)?
)
port map (
-- host access --
/neorv32/trunk/rtl/processor_templates/README.md
3,13 → 3,13
This folder provides exemplary templates that wrap the processor top entity and provide a simplified
set of configuration generics and IOs. These setups are intended to allow beginner an easy start by
hiding much of the processor's configuration complexity. Furthermore, these setups are used by many
of the provided [example setups](https://github.com/stnolting/neorv32/tree/master/setups).
of the provided [example setups](https://github.com/stnolting/neorv32/tree/main/setups).
 
Alternatively, you can directly instantiate the processor's top entity
[`rtl/core/neorv32_top.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd)
[`rtl/core/neorv32_top.vhd`](https://github.com/stnolting/neorv32/blob/main/rtl/core/neorv32_top.vhd)
to have full access to _all_ features.
 
### [`neorv32_ProcessorTop_Minimal.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/processor_templates/neorv32_ProcessorTop_Minimal.vhd)
### [`neorv32_ProcessorTop_Minimal.vhd`](https://github.com/stnolting/neorv32/blob/main/rtl/processor_templates/neorv32_ProcessorTop_Minimal.vhd)
 
This setup used the ["Direct Boot Configuration"](https://stnolting.github.io/neorv32/#_boot_configuration).
Application software is installed directly into the processor-internal instruction memory (IMEM) during
18,7 → 18,7
 
The setup only provides 3 PWM channels as IO.
 
### [`neorv32_ProcessorTop_MinimalBoot.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/processor_templates/neorv32_ProcessorTop_MinimalBoot.vhd)
### [`neorv32_ProcessorTop_MinimalBoot.vhd`](https://github.com/stnolting/neorv32/blob/main/rtl/processor_templates/neorv32_ProcessorTop_MinimalBoot.vhd)
 
This setup used the ["Indirect Boot Configuration"](https://stnolting.github.io/neorv32/#_boot_configuration).
The NEORV32 bootloader is enabled in this setup allowing to upload new application software at any time
26,7 → 26,7
 
The setup provides 8 GPIO outputs and the UART communication lines as IO.
 
### [`neorv32_ProcessorTop_UP5KDemo.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/processor_templates/neorv32_ProcessorTop_UP5KDemo.vhd)
### [`neorv32_ProcessorTop_UP5KDemo.vhd`](https://github.com/stnolting/neorv32/blob/main/rtl/processor_templates/neorv32_ProcessorTop_UP5KDemo.vhd)
 
This is a more complex template that implements a small microcontroller-like NEORV32.
It was originally designed for _UPDuino V3_ board, which features a Lattice iCE40up5k FPGA, but has
/neorv32/trunk/rtl/system_integration/neorv32_ProcessorTop_stdlogic.vhd
59,6 → 59,8
CPU_EXTENSION_RISCV_Zicntr : boolean := true; -- implement base counters?
CPU_EXTENSION_RISCV_Zihpm : boolean := false; -- implement hardware performance monitors?
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
CPU_EXTENSION_RISCV_Zmmul : boolean := false; -- implement multiply-only M sub-extension?
CPU_EXTENSION_RISCV_Zxcfu : boolean := false; -- implement custom (instr.) functions unit?
-- Extension Options --
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
296,6 → 298,8
CPU_EXTENSION_RISCV_Zicntr => CPU_EXTENSION_RISCV_Zicntr, -- implement base counters?
CPU_EXTENSION_RISCV_Zihpm => CPU_EXTENSION_RISCV_Zihpm, -- implement hardware performance monitors?
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
CPU_EXTENSION_RISCV_Zmmul => CPU_EXTENSION_RISCV_Zmmul, -- implement multiply-only M sub-extension?
CPU_EXTENSION_RISCV_Zxcfu => CPU_EXTENSION_RISCV_Zxcfu, -- implement custom (instr.) functions unit?
-- Extension Options --
FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier
FAST_SHIFT_EN => FAST_SHIFT_EN, -- use barrel shifter for shift operations
/neorv32/trunk/rtl/system_integration/neorv32_SystemTop_AvalonMM.vhd
65,6 → 65,7
CPU_EXTENSION_RISCV_Zihpm : boolean := false; -- implement hardware performance monitors?
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
CPU_EXTENSION_RISCV_Zmmul : boolean := false; -- implement multiply-only M sub-extension?
CPU_EXTENSION_RISCV_Zxcfu : boolean := false; -- implement custom (instr.) functions unit?
 
-- Extension Options --
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
259,6 → 260,7
CPU_EXTENSION_RISCV_Zihpm => CPU_EXTENSION_RISCV_Zihpm,
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei,
CPU_EXTENSION_RISCV_Zmmul => CPU_EXTENSION_RISCV_Zmmul,
CPU_EXTENSION_RISCV_Zxcfu => CPU_EXTENSION_RISCV_Zxcfu,
 
-- Extension Options --
FAST_MUL_EN => FAST_MUL_EN,
/neorv32/trunk/rtl/system_integration/neorv32_SystemTop_axi4lite.vhd
65,6 → 65,8
CPU_EXTENSION_RISCV_Zicntr : boolean := true; -- implement base counters?
CPU_EXTENSION_RISCV_Zihpm : boolean := false; -- implement hardware performance monitors?
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
CPU_EXTENSION_RISCV_Zmmul : boolean := false; -- implement multiply-only M sub-extension?
CPU_EXTENSION_RISCV_Zxcfu : boolean := false; -- implement custom (instr.) functions unit?
-- Extension Options --
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
303,6 → 305,8
CPU_EXTENSION_RISCV_Zicntr => CPU_EXTENSION_RISCV_Zicntr, -- implement base counters?
CPU_EXTENSION_RISCV_Zihpm => CPU_EXTENSION_RISCV_Zihpm, -- implement hardware performance monitors?
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
CPU_EXTENSION_RISCV_Zmmul => CPU_EXTENSION_RISCV_Zmmul, -- implement multiply-only M sub-extension?
CPU_EXTENSION_RISCV_Zxcfu => CPU_EXTENSION_RISCV_Zxcfu, -- implement custom (instr.) functions unit?
-- Extension Options --
FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier
FAST_SHIFT_EN => FAST_SHIFT_EN, -- use barrel shifter for shift operations
/neorv32/trunk/rtl/test_setups/README.md
27,7 → 27,7
Note that this might require adaption of the NEORV32 linker script.
 
 
### [`neorv32_test_setup_approm.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_approm.vhd)
### [`neorv32_test_setup_approm.vhd`](https://github.com/stnolting/neorv32/blob/main/rtl/test_setups/neorv32_test_setup_approm.vhd)
 
This setup configures a `rv32imc_Zicsr` CPU with 16kB IMEM (as pre-initialized ROM),
8kB DMEM and includes the GPIO module to drive 8 external signals (`gpio_o`)
39,7 → 39,7
:books: See User Guide section [_Installing an Executable Directly Into Memory_](https://stnolting.github.io/neorv32/ug/#_installing_an_executable_directly_into_memory).
 
 
### [`neorv32_test_setup_bootloader.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd)
### [`neorv32_test_setup_bootloader.vhd`](https://github.com/stnolting/neorv32/blob/main/rtl/test_setups/neorv32_test_setup_bootloader.vhd)
 
This setup configures a `rv32imc_Zicsr` CPU with 16kB IMEM (as RAM), 8kB DMEM
and includes the GPIO module to drive 8 external signals (`gpio_o`), the MTIME
/neorv32/trunk/rtl/README.md
1,24 → 1,24
## HArdware RTL Sources
 
 
### [`core`](https://github.com/stnolting/neorv32/tree/master/rtl/core)
### [`core`](https://github.com/stnolting/neorv32/tree/main/rtl/core)
 
This folder contains the core VHDL files for the NEORV32 CPU and the NEORV32 Processor.
When creating a new synthesis/simulation project make sure that all `*.vhd` files from this folder are added to a
*new design library* called `neorv32`.
 
:warning: The sub-folder [`core/mem`](https://github.com/stnolting/neorv32/tree/master/rtl/core/mem)
:warning: The sub-folder [`core/mem`](https://github.com/stnolting/neorv32/tree/main/rtl/core/mem)
contains the _platform-agnostic_ VHDL architectures of the processor-internal memories.
You can _replace_ inclusion of these files by platform-optimized memory architectures.
 
 
### [`processor_templates`](https://github.com/stnolting/neorv32/tree/master/rtl/processor_templates`)
### [`processor_templates`](https://github.com/stnolting/neorv32/tree/main/rtl/processor_templates`)
 
Contains pre-configured "SoC" templates that instantiate the processor's top entity from `core`.
These templates can be instantiated directly within a FPGA-specific board wrapper.
 
 
### [`system_integration`](https://github.com/stnolting/neorv32/tree/master/rtl/system_integration`)
### [`system_integration`](https://github.com/stnolting/neorv32/tree/main/rtl/system_integration`)
 
Top entities in this folder provide the same peripheral/IO signals and configuration generics as the default
processor top entity from `core`, but feature a different interface type.
26,9 → 26,9
or a top entity with _resolved_ port signal types.
 
 
### [`test_setups`](https://github.com/stnolting/neorv32/tree/master/rtl/test_setups`)
### [`test_setups`](https://github.com/stnolting/neorv32/tree/main/rtl/test_setups`)
 
Minimal test setups (FPGA- and board-independent) for the processor. See the
[README](https://github.com/stnolting/neorv32/tree/master/rtl/test_setups)
[README](https://github.com/stnolting/neorv32/tree/main/rtl/test_setups)
in that folder for more information. Note that these test setups are used in the
[NEORV32 USer Guide](https://stnolting.github.io/neorv32/ug).
/neorv32/trunk/sim/simple/neorv32_imem.iram.simple.vhd
6,7 → 6,7
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
125,6 → 125,7
begin
if rising_edge(clk_i) then
rden <= acc_en and rden_i;
err_o <= '0';
ack_o <= acc_en and (rden_i or wren_i);
end if;
end process bus_feedback;
/neorv32/trunk/sim/simple/neorv32_imem.simple.vhd
78,7 → 78,8
begin
if rising_edge(clk_i) then
rden <= acc_en and rden_i;
ack_o <= acc_en and (rden_i or wren_i);
ack_o <= acc_en and rden_i;
err_o <= acc_en and wren_i;
addr_v := to_integer(unsigned(addr));
--
rdata <= (others => '0');
/neorv32/trunk/sim/simple/neorv32_tb.simple.vhd
187,6 → 187,7
CPU_EXTENSION_RISCV_Zihpm => true, -- implement hardware performance monitors?
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
CPU_EXTENSION_RISCV_Zmmul => false, -- implement multiply-only M sub-extension?
CPU_EXTENSION_RISCV_Zxcfu => true, -- implement custom (instr.) functions unit?
-- Extension Options --
FAST_MUL_EN => false, -- use DSPs for M extension's multiplier
FAST_SHIFT_EN => false, -- use barrel shifter for shift operations
/neorv32/trunk/sim/neorv32_tb.vhd
294,6 → 294,8
CPU_EXTENSION_RISCV_Zicntr => true, -- implement base counters?
CPU_EXTENSION_RISCV_Zihpm => true, -- implement hardware performance monitors?
CPU_EXTENSION_RISCV_Zifencei => true, -- implement instruction stream sync.?
CPU_EXTENSION_RISCV_Zmmul => false, -- implement multiply-only M sub-extension?
CPU_EXTENSION_RISCV_Zxcfu => true, -- implement custom (instr.) functions unit?
-- Extension Options --
FAST_MUL_EN => false, -- use DSPs for M extension's multiplier
FAST_SHIFT_EN => false, -- use barrel shifter for shift operations
/neorv32/trunk/sw/bootloader/bootloader.c
3,7 → 3,7
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
// # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
// # #
// # Redistribution and use in source and binary forms, with or without modification, are #
// # permitted provided that the following conditions are met: #
144,7 → 144,17
ERROR_FLASH = 3 /**< 3: SPI flash access error */
};
 
/**********************************************************************//**
* Error messages
**************************************************************************/
const char error_message[4][24] = {
"exe signature fail",
"exceeding IMEM capacity",
"checksum fail",
"SPI flash access failed"
};
 
 
/**********************************************************************//**
* SPI flash commands
**************************************************************************/
170,7 → 180,7
 
 
/**********************************************************************//**
* Valid executable identification signature.
* Valid executable identification signature
**************************************************************************/
#define EXE_SIGNATURE 0x4788CAFE
 
331,9 → 341,9
neorv32_uart0_setup(UART_BAUD, PARITY_NONE, FLOW_CONTROL_NONE);
#endif
 
// Configure machine system timer interrupt for ~2Hz
// Configure machine system timer interrupt
if (neorv32_mtime_available()) {
neorv32_mtime_set_timecmp(neorv32_cpu_get_systime() + (NEORV32_SYSINFO.CLK/4));
neorv32_mtime_set_timecmp(0 + (NEORV32_SYSINFO.CLK/4));
// active timer IRQ
neorv32_cpu_csr_write(CSR_MIE, 1 << CSR_MIE_MTIE); // activate MTIME IRQ source only!
neorv32_cpu_eint(); // enable global interrupts
348,15 → 358,14
PRINT_XNUM(neorv32_cpu_csr_read(CSR_MIMPID));
PRINT_TEXT("\nCLK: ");
PRINT_XNUM(NEORV32_SYSINFO.CLK);
PRINT_TEXT("\nMISA: ");
PRINT_TEXT("\nISA: ");
PRINT_XNUM(neorv32_cpu_csr_read(CSR_MISA));
PRINT_TEXT("\nCPU: ");
PRINT_XNUM(NEORV32_SYSINFO.CPU);
PRINT_TEXT(" + ");
PRINT_XNUM(neorv32_cpu_csr_read(CSR_MXISA));
PRINT_TEXT("\nSOC: ");
PRINT_XNUM(NEORV32_SYSINFO.SOC);
PRINT_TEXT("\nIMEM: ");
PRINT_XNUM(NEORV32_SYSINFO.IMEM_SIZE);
PRINT_TEXT(" bytes @");
PRINT_XNUM(NEORV32_SYSINFO.IMEM_SIZE); PRINT_TEXT(" bytes @");
PRINT_XNUM(NEORV32_SYSINFO.ISPACE_BASE);
PRINT_TEXT("\nDMEM: ");
PRINT_XNUM(NEORV32_SYSINFO.DMEM_SIZE);
371,8 → 380,8
#if (AUTO_BOOT_TIMEOUT != 0)
if (neorv32_mtime_available()) {
 
PRINT_TEXT("\n\nAutoboot in "xstr(AUTO_BOOT_TIMEOUT)"s. Press key to abort.\n");
uint64_t timeout_time = neorv32_cpu_get_systime() + (uint64_t)(AUTO_BOOT_TIMEOUT * NEORV32_SYSINFO.CLK);
PRINT_TEXT("\n\nAutoboot in "xstr(AUTO_BOOT_TIMEOUT)"s. Press any key to abort.\n");
uint64_t timeout_time = neorv32_mtime_get_time() + (uint64_t)(AUTO_BOOT_TIMEOUT * NEORV32_SYSINFO.CLK);
 
while(1){
 
382,7 → 391,7
}
}
 
if (neorv32_cpu_get_systime() >= timeout_time) { // timeout? start auto boot sequence
if (neorv32_mtime_get_time() >= timeout_time) { // timeout? start auto boot sequence
get_exe(EXE_STREAM_FLASH); // try booting from flash
PRINT_TEXT("\n");
start_app();
438,6 → 447,9
start_app();
}
}
else if (c == '?') {
PRINT_TEXT("(c) by Stephan Nolting\nhttps://github.com/stnolting/neorv32");
}
else { // unknown command
PRINT_TEXT("Invalid CMD");
}
504,7 → 516,7
#endif
// set time for next IRQ
if (neorv32_mtime_available()) {
neorv32_mtime_set_timecmp(neorv32_cpu_get_systime() + (NEORV32_SYSINFO.CLK/4));
neorv32_mtime_set_timecmp(neorv32_mtime_get_timecmp() + (NEORV32_SYSINFO.CLK/4));
}
}
 
518,13 → 530,13
register uint32_t epc = neorv32_cpu_csr_read(CSR_MEPC);
#if (UART_EN != 0)
if (neorv32_uart0_available()) {
PRINT_TEXT("\n[ERR ");
PRINT_TEXT("\n[ERROR - Unexpected exception! mcause=");
PRINT_XNUM(cause); // MCAUSE
PRINT_PUTC(' ');
PRINT_TEXT(" mepc=");
PRINT_XNUM(epc); // MEPC
PRINT_PUTC(' ');
PRINT_TEXT(" mtval=");
PRINT_XNUM(neorv32_cpu_csr_read(CSR_MTVAL)); // MTVAL
PRINT_TEXT("]\n");
PRINT_TEXT("] trying to resume...\n");
}
#endif
neorv32_cpu_csr_write(CSR_MEPC, epc + 4); // advance to next instruction
699,12 → 711,15
/**********************************************************************//**
* Output system error ID and stall.
*
* @param[in] err_code Error code. See #ERROR_CODES.
* @param[in] err_code Error code. See #ERROR_CODES and #error_message.
**************************************************************************/
void system_error(uint8_t err_code) {
 
PRINT_TEXT("\a\nERROR_"); // output error code with annoying bell sound
PRINT_PUTC('0' + ((char)err_code));
PRINT_PUTC(':');
PRINT_PUTC(' ');
PRINT_TEXT(error_message[err_code]);
 
neorv32_cpu_dint(); // deactivate IRQs
#if (STATUS_LED_EN != 0)
/neorv32/trunk/sw/bootloader/makefile
5,7 → 5,7
# ********************************************************************************************* #
# BSD 3-Clause License #
# #
# Copyright (c) 2021, Stephan Nolting. All rights reserved. #
# Copyright (c) 2022, Stephan Nolting. All rights reserved. #
# #
# Redistribution and use in source and binary forms, with or without modification, are #
# permitted provided that the following conditions are met: #
37,4 → 37,11
# Modify this variable to fit your NEORV32 setup (neorv32 home folder)
NEORV32_HOME ?= ../..
 
# Set ISA to minimal rv32i to allow bootloader to run on any processor ISA configuration
MARCH=rv32i
 
# Enable link-time-optimization and add debug symbols
USER_FLAGS="-flto"
USER_FLAGS+="-g"
 
include $(NEORV32_HOME)/sw/common/common.mk
/neorv32/trunk/sw/common/crt0.S
3,7 → 3,7
/* # ********************************************************************************************* # */
/* # BSD 3-Clause License # */
/* # # */
/* # Copyright (c) 2021, Stephan Nolting. All rights reserved. # */
/* # Copyright (c) 2022, Stephan Nolting. All rights reserved. # */
/* # # */
/* # Redistribution and use in source and binary forms, with or without modification, are # */
/* # permitted provided that the following conditions are met: # */
32,10 → 32,11
/* # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # */
/* ################################################################################################# */
 
.file "crt0.S"
.section .text.boot
.file "crt0.S"
.section .text.crt0
.balign 4
.global _start
.global __crt0_main_exit
 
 
_start:
139,11 → 140,11
// ************************************************************************************************
// Reset/deactivate IO/peripheral devices
// Devices, that are not implemented, will cause a store bus access fault
// which is captured (but actually ignored) by the dummy trap handler.
// that is catched (but not further processed) by the dummy trap handler.
// ************************************************************************************************
__crt0_reset_io:
la x8, __ctr0_io_space_begin // start of processor-internal IO region
la x9, __ctr0_io_space_end // end of processor-internal IO region
la x8, __crt0_io_space_begin // start of processor-internal IO region
la x9, __crt0_io_space_end // end of processor-internal IO region
 
__crt0_reset_io_loop:
sw zero, 0(x8)
168,7 → 169,7
 
 
// ************************************************************************************************
// Copy initialized .data section from ROM to RAM (byte-wise) using linker script symbols
// Copy initialized .data section from ROM to RAM (byte-wise)
// ************************************************************************************************
__crt0_copy_data:
la x11, __crt0_copy_data_src_begin // start of data area (copy source)
190,22 → 191,27
// Setup arguments and call main function
// ************************************************************************************************
__crt0_main_entry:
addi x10, zero, 0 // a0 = argc = 0
addi x11, zero, 0 // a1 = argv = 0
jal ra, main // call actual app's main function, this "should" not return
addi a0, zero, 0 // a0 = argc = 0
addi a1, zero, 0 // a1 = argv = 0
jal ra, main // call actual app's main function, this "should" not return
 
__crt0_main_exit: // main's "return" and "exit" will arrive here
csrw mscratch, a0 // backup main's return code to mscratch (for debugger)
 
 
// ************************************************************************************************
// call "after main" handler (if there is any) if main really returns
// ************************************************************************************************
#ifndef make_bootloader // after_main handler not supported for bootloader
 
__crt0_main_aftermath:
csrw mscratch, a0 // copy main's return code in mscratch for debugger
 
#ifndef make_bootloader // after_main handler not supported for bootloader
.weak __neorv32_crt0_after_main
la ra, __neorv32_crt0_after_main
beqz ra, __crt0_main_aftermath_end // check if an aftermath handler has been specified
jalr ra // execute handler, main's return code in a0
jalr ra // execute handler with main's return code still in a0
 
__crt0_main_aftermath_end:
 
#endif
 
 
212,23 → 218,23
// ************************************************************************************************
// go to endless sleep mode
// ************************************************************************************************
__crt0_main_aftermath_end:
csrci mstatus, 8 // mstatus: disable global IRQs (mstatus.mie)
__crt0_main_aftermath_end_loop:
wfi // try to go to sleep mode
j __crt0_main_aftermath_end_loop // endless loop
__crt0_shutdown:
csrci mstatus, 8 // disable global IRQs (clear mstatus.mie)
__crt0_shutdown_loop:
wfi // go to sleep mode
j __crt0_shutdown_loop // endless loop
 
 
// ************************************************************************************************
// dummy trap handler (for exceptions & IRQs during very early boot stage)
// does nothing but tries to move on to next instruction
// does nothing but trying to move on to the next instruction
// ************************************************************************************************
.balign 4
__crt0_dummy_trap_handler:
 
addi sp, sp, -8
sw x8, 0(sp)
sw x9, 4(sp)
addi sp, sp, -8
sw x8, 0(sp)
sw x9, 4(sp)
 
csrr x8, mcause
blt x8, zero, __crt0_dummy_trap_handler_irq // skip mepc modification if interrupt
/neorv32/trunk/sw/common/neorv32.ld
3,7 → 3,7
/* # ********************************************************************************************* # */
/* # BSD 3-Clause License # */
/* # # */
/* # Copyright (c) 2021, Stephan Nolting. All rights reserved. # */
/* # Copyright (c) 2022, Stephan Nolting. All rights reserved. # */
/* # # */
/* # Redistribution and use in source and binary forms, with or without modification, are # */
/* # permitted provided that the following conditions are met: # */
46,23 → 46,23
ENTRY(_start)
SEARCH_DIR("/opt/riscv/riscv32-unknown-elf/lib"); SEARCH_DIR("=/opt/riscv/riscv64-unknown-linux-gnu/lib"); SEARCH_DIR("=/usr/local/lib"); SEARCH_DIR("=/lib"); SEARCH_DIR("=/usr/lib");
 
/* ************************************************************************** */
/* NEORV32 memory section configuration. */
/* ************************************************************************** */
/* "ram" : data memory (int/ext DMEM) - make sure this is sync with the HW! */
/* "rom" : instruction memory (int/ext IMEM or bootloader ROM) */
/* "iodev" : peripheral/IO devices */
/* ************************************************************************** */
/* **************************************************************************
* NEORV32 memory section configuration.
* **************************************************************************
* "ram" : data memory (int/ext DMEM) - make sure this is sync with the HW!
* "rom" : instruction memory (int/ext IMEM or bootloader ROM)
* "iodev" : peripheral/IO devices
* ************************************************************************** */
MEMORY
{
/* section base addresses and sizes have to be a multiple of 4 bytes */
/* ram section: first value of LENGTH => data memory used by bootloader (fixed!); second value of LENGTH => *physical* size of data memory */
/* adapt the right-most value to match the *total physical data memory size* of your setup */
/* section base addresses and sizes have to be a multiple of 4 bytes
* ram section: first value of LENGTH => data memory used by bootloader (fixed!); second value of LENGTH => *physical* size of data memory
* adapt the right-most value to match the *total physical data memory size* of your setup */
 
ram (rwx) : ORIGIN = 0x80000000, LENGTH = DEFINED(make_bootloader) ? 512 : 8*1024
 
/* rom and iodev sections should NOT be modified by the user at all! */
/* rom section: first value of ORIGIN/LENGTH => bootloader ROM; second value of ORIGIN/LENGTH => maximum *logical* size of instruction memory */
/* rom and iodev sections should NOT be modified by the user at all!
* rom section: first value of ORIGIN/LENGTH => bootloader ROM; second value of ORIGIN/LENGTH => maximum *logical* size of instruction memory */
 
rom (rx) : ORIGIN = DEFINED(make_bootloader) ? 0xFFFF0000 : 0x00000000, LENGTH = DEFINED(make_bootloader) ? 32K : 2048M
iodev (rw) : ORIGIN = 0xFFFFFE00, LENGTH = 512
75,23 → 75,19
/* start section on WORD boundary */
. = ALIGN(4);
 
/* default heap size: we can use up to 1/4 of available data memory (RAM) by default
* WARNING! the heap will collide with the stack if allocating too much memory! */
__heap_size = DEFINED(__heap_size) ? __heap_size : LENGTH(ram) / 4;
 
/* Actual instructions */
 
/* First part of the actual executable file: actual instructions */
.text :
{
PROVIDE(__text_start = .);
PROVIDE(__textstart = .);
 
PROVIDE_HIDDEN (__rela_iplt_start = .);
*(.rela.iplt)
PROVIDE_HIDDEN (__rela_iplt_end = .);
KEEP(*(.text.crt0)); /* keep start-up code crt0 right at the beginning of rom */
 
*(.rela.plt)
 
KEEP(*(.text.boot)); /* keep start-up code at the beginning of rom */
 
KEEP (*(SORT_NONE(.init)))
 
*(.text.unlikely .text.*_unlikely .text.unlikely.*)
*(.text.exit .text.exit.*)
*(.text.startup .text.startup.*)
101,33 → 97,6
/* .gnu.warning sections are handled specially by elf.em. */
*(.gnu.warning)
 
KEEP (*(SORT_NONE(.fini)))
 
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
/* We don't want to include the .ctor section from
the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
 
KEEP (*crtbegin.o(.dtors))
KEEP (*crtbegin?.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
 
/* finish section on WORD boundary */
. = ALIGN(4);
 
137,28 → 106,48
} > rom
 
 
/* read-only data, appended to .text */
/* Second part of the actual executable: read-only data, placed right next to .text */
.rodata :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
PROVIDE_HIDDEN (__init_array_end = .);
/* these are a list of 32-bit pointers that point to functions
* that are called before/after executing "main". */
 
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
PROVIDE_HIDDEN (__fini_array_end = .);
 
/* constructors are not supported by default. */
 
/* __init_array_start = .;
* KEEP (*(.preinit_array))
* KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
* KEEP (*(.rodata EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
* __init_array_end = .;
*/
 
 
/* main should never return, hence there is no default support for deconstructors!
* however, if main return, the "after_main_handler" will be called by crt0, which can be used to implement
* _minimal_ deconstructor support or to call __libc_fini_array is really really required. */
 
/*
* __fini_array_start = .;
* KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
* KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
* __fini_array_end = .;
*/
 
 
/* constant data like strings */
 
*(.rodata .rodata.* .gnu.linkonce.r.*)
*(.rodata1)
 
 
/* finish section on WORD boundary */
. = ALIGN(4);
} > rom
 
 
/* initialized read/write data, accessed in RAM, placed in ROM, copied during boot */
/* initialized read/write data, accessed in RAM, placed in ROM, copied during boot
* not part of the final executable */
.data :
{
__DATA_BEGIN__ = .;
178,8 → 167,8
*(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*)
*(.sdata .sdata.* .gnu.linkonce.s.*)
 
PROVIDE_HIDDEN (__tdata_start = .);
*(.tdata .tdata.* .gnu.linkonce.td.*)
PROVIDE_HIDDEN (__tdata_start = .);
*(.tdata .tdata.* .gnu.linkonce.td.*)
 
 
/* finish section on WORD boundary */
187,14 → 176,17
 
_edata = .; PROVIDE (edata = .);
. = .;
__DATA_END__ = .;
__global_pointer$ = __DATA_END__ + 0x800;
 
} > ram AT > rom
 
 
/* zero/non-initialized read/write data placed in RAM */
/* zero/non-initialized read/write data placed in RAM - not part of the final executable */
.bss (NOLOAD):
{
__bss_start = .;
. = ALIGN(4);
__BSS_START__ = .;
*(.dynsbss)
*(.sbss .sbss.* .gnu.linkonce.sb.*)
*(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)
215,13 → 207,21
pad the .data section. */
. = ALIGN(. != 0 ? 32 / 8 : 1);
 
. = ALIGN(32 / 8);
. = ALIGN(4);
__BSS_END__ = .;
__global_pointer$ = MIN(__SDATA_BEGIN__ + 0x800, MAX(__DATA_BEGIN__ + 0x800, __BSS_END__ - 0x800));
_end = .; PROVIDE (end = .);
} > ram
 
 
/* heap for dynamic memory allocation (use carefully!) - not part of the final executable */
.heap :
{
PROVIDE(__heap_start = .);
. = __heap_size;
PROVIDE(__heap_end = .);
} > ram
 
 
/* Yet unused */
.jcr : { KEEP (*(.jcr)) }
.got : { *(.got.plt) *(.igot.plt) *(.got) *(.igot) } .interp : { *(.interp) }
295,15 → 295,15
/DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }
 
 
/* Provide symbols for neorv32 crt0 start-up code */
PROVIDE(__ctr0_imem_begin = ORIGIN(rom));
PROVIDE(__ctr0_dmem_begin = ORIGIN(ram));
/* Export symbols for neorv32 crt0 start-up code */
PROVIDE(__crt0_imem_begin = ORIGIN(rom));
PROVIDE(__crt0_dmem_begin = ORIGIN(ram));
PROVIDE(__crt0_stack_begin = (ORIGIN(ram) + LENGTH(ram)) - 4);
PROVIDE(__crt0_bss_start = __bss_start);
PROVIDE(__crt0_bss_start = __BSS_START__);
PROVIDE(__crt0_bss_end = __BSS_END__);
PROVIDE(__crt0_copy_data_src_begin = __etext + SIZEOF(.rodata));
PROVIDE(__crt0_copy_data_dst_begin = __DATA_BEGIN__);
PROVIDE(__crt0_copy_data_dst_end = __DATA_BEGIN__ + SIZEOF(.data));
PROVIDE(__ctr0_io_space_begin = ORIGIN(iodev));
PROVIDE(__ctr0_io_space_end = ORIGIN(iodev) + LENGTH(iodev));
PROVIDE(__crt0_io_space_begin = ORIGIN(iodev));
PROVIDE(__crt0_io_space_end = ORIGIN(iodev) + LENGTH(iodev));
}
/neorv32/trunk/sw/example/demo_cfu/main.c
0,0 → 1,183
// #################################################################################################
// # << NEORV32 - CFU Custom Instructions Example Program >> #
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
// # #
// # Redistribution and use in source and binary forms, with or without modification, are #
// # permitted provided that the following conditions are met: #
// # #
// # 1. Redistributions of source code must retain the above copyright notice, this list of #
// # conditions and the following disclaimer. #
// # #
// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
// # conditions and the following disclaimer in the documentation and/or other materials #
// # provided with the distribution. #
// # #
// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
// # endorse or promote products derived from this software without specific prior written #
// # permission. #
// # #
// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
// # OF THE POSSIBILITY OF SUCH DAMAGE. #
// # ********************************************************************************************* #
// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
// #################################################################################################
 
 
/**********************************************************************//**
* @file demo_cfu/main.c
* @author Stephan Nolting
* @brief Example program showing how to use the CFU's custom instructions.
**************************************************************************/
#include <neorv32.h>
 
 
/**********************************************************************//**
* @name User configuration
**************************************************************************/
/**@{*/
/** UART BAUD rate */
#define BAUD_RATE 19200
/** Number of test cases per CFU instruction */
#define TESTCASES 4
/**@}*/
 
 
/**********************************************************************//**
* @name Prototypes
**************************************************************************/
uint32_t xorshift32(void);
 
 
/**********************************************************************//**
* Main function
*
* @note This program requires the CFU and UART0.
*
* @return 0 if execution was successful
**************************************************************************/
int main() {
 
// initialize NEORV32 run-time environment
neorv32_rte_setup();
 
// setup UART0 at default baud rate, no parity bits, no HW flow control
neorv32_uart0_setup(BAUD_RATE, PARITY_NONE, FLOW_CONTROL_NONE);
 
// check if UART0 is implemented
if (neorv32_uart0_available() == 0) {
return 1; // UART0 not available, exit
}
 
// check if the CFU is implemented at all
// note that the CFU is wrapped in the core's "Zxcfu" ISA extension
if (neorv32_cpu_cfu_available() == 0) {
neorv32_uart0_printf("ERROR! CFU ('Zxcfu' ISA extensions) not implemented!\n");
return 1;
}
 
 
// intro
neorv32_uart0_printf("\n<<< NEORV32 Custom Functions Unit (CFU) 'Custom Instructions' Example Program >>>\n\n");
 
neorv32_uart0_printf("NOTE: This program assumes the _default_ CFU hardware module, which implements\n"
" four simple data conversion instructions.\n\n");
 
neorv32_uart0_printf("NOTE: This program (and it's comments) just shows how to USE the CFU's custom\n"
" instructions. The actual implementation of these instructions is done\n"
" in the CFU hardware module (-> rtl/core/neorv32_cpu_cp_cfu.vhd).\n\n");
 
 
// custom instructions usage examples
uint32_t i, opa, opb;
 
neorv32_uart0_printf("\n--- CFU 'binary to gray' instruction (funct3 = 000) ---\n");
for (i=0; i<TESTCASES; i++) {
opa = xorshift32(); // get random test data
opb = 0;
neorv32_uart0_printf("%u: neorv32_cfu_cmd0 - OPA = 0x%x, OPB = 0x%x, ", i, opa, opb);
 
// The CFU custom instruction can be used as plain C functions!
//
// There are 8 "prototypes" for the CFU instructions:
// - neorv32_cfu_cmd0(funct7, rs1, rs2) - sets the instruction's "funct3" bit field to 000
// - neorv32_cfu_cmd1(funct7, rs1, rs2) - sets the instruction's "funct3" bit field to 001
// - ...
// - neorv32_cfu_cmd7(funct7, rs1, rs2) - sets the instruction's "funct3" bit field to 111
//
// These functions are turned into 32-bit instruction words resembling a R2-type RISC-V instruction
// (=> "intrinsics").
//
// Each neorv32_cfu_cmd* function requires three arguments:
// - funct7: a compile-time static 7-bit immediate (put in the instruction's "funct7" bit field)
// - rs1: a 32-bit operand A (this is the first register file source rs1)
// - rs2: a 32-bit operand B (this is the first register second source rs2)
//
// The operands can be literals, variables, function return values, ... you name it.
//
// Each neorv32_cfu_cmd* function returns a 32-bit uint32_t data word, which represents
// the result of the according instruction.
//
// The 7-bit immediate ("funct7") can be used to pass small _static_ literals to the CFU
// or to do a more fine-grained function selection - it all depends on your hardware implementation! ;)
neorv32_uart0_printf("Result = 0x%x\n", neorv32_cfu_cmd0(0b0000000, opa, opb));
}
 
neorv32_uart0_printf("\n--- CFU 'gray to binary' instruction (funct3 = 001) ---\n");
for (i=0; i<TESTCASES; i++) {
opa = xorshift32();
neorv32_uart0_printf("%u: neorv32_cfu_cmd1 - OPA = 0x%x, OPB = 0x%x, ", i, opa, 0);
// you can also pass literals instead of variables to the intrinsics (0 instead of opb):
neorv32_uart0_printf("Result = 0x%x\n", neorv32_cfu_cmd1(0b0000000, opa, 0));
}
 
neorv32_uart0_printf("\n--- CFU 'bit reversal' instruction (funct3 = 010) ---\n");
for (i=0; i<TESTCASES; i++) {
opa = xorshift32();
neorv32_uart0_printf("%u: neorv32_cfu_cmd2 - OPA = 0x%x, OPB = 0x%x, ", i, opa, 0);
// here we are setting the funct7 bit-field to all-one; however, this is not
// used at all by the default CFU hardware module
// note that all funct3/funct7 combinations are treated as "valid" by the CPU
// - so there is no chance of causing an illegal instruction exception by using the CFU intrinsics
neorv32_uart0_printf("Result = 0x%x\n", neorv32_cfu_cmd2(0b1111111, opa, 0));
}
 
neorv32_uart0_printf("\n--- CFU 'XNOR' instruction (funct3 = 011) ---\n");
for (i=0; i<TESTCASES; i++) {
opa = xorshift32();
opb = xorshift32();
neorv32_uart0_printf("%u: neorv32_cfu_cmd3 - OPA = 0x%x, OPB = 0x%x, ", i, opa, opb);
neorv32_uart0_printf("Result = 0x%x\n", neorv32_cfu_cmd3(0b0000000, opa, opb));
}
 
 
neorv32_uart0_printf("\nCFU demo program completed.\n");
 
return 0;
}
 
 
/**********************************************************************//**
* Pseudo-random number generator (to generate deterministic test data).
*
* @return Random data (32-bit).
**************************************************************************/
uint32_t xorshift32(void) {
 
static uint32_t x32 = 314159265;
 
x32 ^= x32 << 13;
x32 ^= x32 >> 17;
x32 ^= x32 << 5;
 
return x32;
}
/neorv32/trunk/sw/example/demo_cfu/makefile
0,0 → 1,40
#################################################################################################
# << NEORV32 - Application Makefile >> #
# ********************************************************************************************* #
# Make sure to add the RISC-V GCC compiler's bin folder to your PATH environment variable. #
# ********************************************************************************************* #
# BSD 3-Clause License #
# #
# Copyright (c) 2021, Stephan Nolting. All rights reserved. #
# #
# Redistribution and use in source and binary forms, with or without modification, are #
# permitted provided that the following conditions are met: #
# #
# 1. Redistributions of source code must retain the above copyright notice, this list of #
# conditions and the following disclaimer. #
# #
# 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
# conditions and the following disclaimer in the documentation and/or other materials #
# provided with the distribution. #
# #
# 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
# endorse or promote products derived from this software without specific prior written #
# permission. #
# #
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
# OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
# COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
# GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
# OF THE POSSIBILITY OF SUCH DAMAGE. #
# ********************************************************************************************* #
# The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
#################################################################################################
 
# Modify this variable to fit your NEORV32 setup (neorv32 home folder)
NEORV32_HOME ?= ../../..
 
include $(NEORV32_HOME)/sw/common/common.mk
/neorv32/trunk/sw/example/demo_gptmr/main.c
3,7 → 3,7
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
// # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
// # #
// # Redistribution and use in source and binary forms, with or without modification, are #
// # permitted provided that the following conditions are met: #
58,7 → 58,7
/**********************************************************************//**
* This program blinks an LED at GPIO.output(0) at 1Hz using the general purpose timer interrupt.
*
* @note This program requires the GPTMR unit to be synthesized.
* @note This program requires the GPTMR unit to be synthesized (and UART0 and GPIO).
*
* @return Should not return;
**************************************************************************/
67,13 → 67,13
// capture all exceptions and give debug info via UART
neorv32_rte_setup();
 
// init UART at default baud rate, no parity bits, ho hw flow control
// init UART at default baud rate, no parity bits, no HW flow control
neorv32_uart0_setup(BAUD_RATE, PARITY_NONE, FLOW_CONTROL_NONE);
 
 
// check if GPTMR unit is implemented at all
if (neorv32_gptmr_available() == 0) {
neorv32_uart0_print("General purpose timer not implemented!\n");
neorv32_uart0_print("ERROR! General purpose timer not implemented!\n");
return 1;
}
 
89,18 → 89,18
// install GPTMR interrupt handler
neorv32_rte_exception_install(GPTMR_RTE_ID, gptmr_firq_handler);
 
// configure timer for 1Hz in continuous mode
uint32_t soc_clock = NEORV32_SYSINFO.CLK;
soc_clock = soc_clock / 2; // divide by two as we are using the 1/2 clock prescaler
neorv32_gptmr_setup(CLK_PRSC_2, 1, soc_clock);
// configure timer for 1Hz ticks in continuous mode (with clock divisor = 8)
neorv32_gptmr_setup(CLK_PRSC_8, 1, NEORV32_SYSINFO.CLK / (8 * 2));
 
// enable interrupt
neorv32_cpu_irq_enable(GPTMR_FIRQ_ENABLE); // enable GPTRM FIRQ channel
neorv32_cpu_irq_enable(GPTMR_FIRQ_ENABLE); // enable GPTMR FIRQ channel
neorv32_cpu_eint(); // enable global interrupt flag
 
 
// do nothing, wait for interrupt
while(1);
// go to sleep mode and wait for interrupt
while(1) {
neorv32_cpu_sleep();
}
 
return 0;
}
115,6 → 115,6
 
neorv32_cpu_csr_write(CSR_MIP, 1<<GPTMR_FIRQ_PENDING); // clear/ack pending FIRQ
 
neorv32_uart0_putc('.'); // send tick symbol via UART
neorv32_uart0_putc('.'); // send tick symbol via UART0
neorv32_gpio_pin_toggle(0); // toggle output port bit 0
}
/neorv32/trunk/sw/example/demo_mtime/main.c
0,0 → 1,124
// #################################################################################################
// # << NEORV32 - RISC-V Machine Timer (MTIME) Demo Program >> #
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
// # #
// # Redistribution and use in source and binary forms, with or without modification, are #
// # permitted provided that the following conditions are met: #
// # #
// # 1. Redistributions of source code must retain the above copyright notice, this list of #
// # conditions and the following disclaimer. #
// # #
// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
// # conditions and the following disclaimer in the documentation and/or other materials #
// # provided with the distribution. #
// # #
// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
// # endorse or promote products derived from this software without specific prior written #
// # permission. #
// # #
// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
// # OF THE POSSIBILITY OF SUCH DAMAGE. #
// # ********************************************************************************************* #
// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
// #################################################################################################
 
 
/**********************************************************************//**
* @file demo_mtime/main.c
* @author Stephan Nolting
* @brief Simple machine timer (MTIME) usage example.
**************************************************************************/
 
#include <neorv32.h>
 
 
/**********************************************************************//**
* @name User configuration
**************************************************************************/
/**@{*/
/** UART BAUD rate */
#define BAUD_RATE 19200
/**@}*/
 
 
// Prototypes
void mtime_irq_handler(void);
 
 
/**********************************************************************//**
* This program blinks an LED at GPIO.output(0) at 1Hz using the machine timer interrupt.
*
* @note This program requires the MTIME unit to be synthesized (and UART0 and GPIO).
*
* @return Should not return;
**************************************************************************/
int main() {
// capture all exceptions and give debug info via UART
neorv32_rte_setup();
 
// init UART at default baud rate, no parity bits, no hw flow control
neorv32_uart0_setup(BAUD_RATE, PARITY_NONE, FLOW_CONTROL_NONE);
 
 
// check if MTIME unit is implemented at all
if (neorv32_mtime_available() == 0) {
neorv32_uart0_print("ERROR! MTIME timer not implemented!\n");
return 1;
}
 
// Intro
neorv32_uart0_print("RISC-V Machine System Timer (MTIME) demo Program.\n"
"Toggles GPIO.output(0) at 1Hz using the RISC-V 'MTI' interrupt.\n\n");
 
 
// clear GPIO output port
neorv32_gpio_port_set(0);
 
 
// install MTIME interrupt handler to RTE
neorv32_rte_exception_install(RTE_TRAP_MTI, mtime_irq_handler);
 
// configure MTIME timer's first interrupt to appear after SYSTEM_CLOCK / 2 cycles (toggle at 2Hz)
// starting from _now_
neorv32_mtime_set_timecmp(neorv32_mtime_get_time() + (NEORV32_SYSINFO.CLK / 2));
 
// enable interrupt
neorv32_cpu_irq_enable(CSR_MIE_MTIE); // enable MTIME interrupt
neorv32_cpu_eint(); // enable global interrupt flag
 
 
// go to sleep mode and wait for interrupt
while(1) {
neorv32_cpu_sleep();
}
 
return 0;
}
 
 
/**********************************************************************//**
* MTIME IRQ handler.
*
* @warning This function has to be of type "void xyz(void)" and must not use any interrupt attributes!
**************************************************************************/
void mtime_irq_handler(void) {
 
// update MTIMECMP value for next IRQ (in SYSTEM_CLOCK / 2 cycles)
// this will also ack/clear the current MTIME interrupt request
neorv32_mtime_set_timecmp(neorv32_mtime_get_timecmp() + (NEORV32_SYSINFO.CLK / 2));
 
 
neorv32_uart0_putc('.'); // send tick symbol via UART
neorv32_gpio_pin_toggle(0); // toggle output port bit 0
}
/neorv32/trunk/sw/example/demo_mtime/makefile
0,0 → 1,40
#################################################################################################
# << NEORV32 - Application Makefile >> #
# ********************************************************************************************* #
# Make sure to add the RISC-V GCC compiler's bin folder to your PATH environment variable. #
# ********************************************************************************************* #
# BSD 3-Clause License #
# #
# Copyright (c) 2021, Stephan Nolting. All rights reserved. #
# #
# Redistribution and use in source and binary forms, with or without modification, are #
# permitted provided that the following conditions are met: #
# #
# 1. Redistributions of source code must retain the above copyright notice, this list of #
# conditions and the following disclaimer. #
# #
# 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
# conditions and the following disclaimer in the documentation and/or other materials #
# provided with the distribution. #
# #
# 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
# endorse or promote products derived from this software without specific prior written #
# permission. #
# #
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
# OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
# COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
# GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
# OF THE POSSIBILITY OF SUCH DAMAGE. #
# ********************************************************************************************* #
# The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
#################################################################################################
 
# Modify this variable to fit your NEORV32 setup (neorv32 home folder)
NEORV32_HOME ?= ../../..
 
include $(NEORV32_HOME)/sw/common/common.mk
/neorv32/trunk/sw/example/dhrystone/README.md
18,7 → 18,7
 
### Exemplary Output
 
Output generated for processor HW version [v1.5.9.1](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md)
Output generated for processor HW version [v1.5.9.1](https://github.com/stnolting/neorv32/blob/main/CHANGELOG.md)
using performance-optimized configuration options.
 
```
/neorv32/trunk/sw/example/floating_point_test/main.c
3,7 → 3,7
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
// # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
// # #
// # Redistribution and use in source and binary forms, with or without modification, are #
// # permitted provided that the following conditions are met: #
123,7 → 123,7
neorv32_rte_check_isa(0); // silent = 0 -> show message if isa mismatch
 
// check if Zfinx extension is implemented at all
if ((NEORV32_SYSINFO.CPU & (1<<SYSINFO_CPU_ZFINX)) == 0) {
if ((neorv32_cpu_csr_read(CSR_MXISA) & (1<<CSR_MXISA_ZFINX)) == 0) {
neorv32_uart0_print("Error! <Zfinx> extension not synthesized!\n");
return 1;
}
/neorv32/trunk/sw/example/newlib_demo/main.c
0,0 → 1,139
// #################################################################################################
// # << NEORV32 - Newlib Demo/Test Program >> #
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
// # #
// # Redistribution and use in source and binary forms, with or without modification, are #
// # permitted provided that the following conditions are met: #
// # #
// # 1. Redistributions of source code must retain the above copyright notice, this list of #
// # conditions and the following disclaimer. #
// # #
// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
// # conditions and the following disclaimer in the documentation and/or other materials #
// # provided with the distribution. #
// # #
// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
// # endorse or promote products derived from this software without specific prior written #
// # permission. #
// # #
// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
// # OF THE POSSIBILITY OF SUCH DAMAGE. #
// # ********************************************************************************************* #
// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
// #################################################################################################
 
 
/**********************************************************************//**
* @file newlib_demo/main.c
* @author Stephan Nolting
* @brief Demo/test program for NEORV32's newlib C standard library support.
**************************************************************************/
#include <neorv32.h>
#include <unistd.h>
#include <stdlib.h>
 
 
/**********************************************************************//**
* @name User configuration
**************************************************************************/
/**@{*/
/** UART BAUD rate */
#define BAUD_RATE 19200
/**@}*/
 
 
/**********************************************************************//**
* Main function: Check some of newlib's core functions.
*
* @note This program requires UART.
*
* @return 0 if execution was successful
**************************************************************************/
int main() {
 
// setup NEORV32 runtime environment to keep us safe
// -> catch all traps and give debug information via UART0
neorv32_rte_setup();
 
// setup UART0 at default baud rate, no parity bits, no HW flow control
neorv32_uart0_setup(BAUD_RATE, PARITY_NONE, FLOW_CONTROL_NONE);
 
// check if UART0 is implemented at all
if (neorv32_uart0_available() == 0) {
neorv32_uart0_printf("Error! UART0 not synthesized!\n");
return 1;
}
 
 
// say hello
neorv32_uart0_printf("<<< Newlib demo/test program >>>\n\n");
 
 
// check if newlib is really available
#ifndef __NEWLIB__
neorv32_uart0_printf("ERROR! Seems like the compiler toolchain does not support newlib...\n");
return -1;
#endif
 
neorv32_uart0_printf("newlib version %i.%i\n\n", (int32_t)__NEWLIB__, (int32_t)__NEWLIB_MINOR__);
 
 
char *char_buffer; // pointer for dynamic memory allocation
 
neorv32_uart0_printf("<malloc> test... ");
char_buffer = (char *) malloc(4 * sizeof(char)); // 4 bytes
neorv32_uart0_printf("ok\n");
 
// do not test read & write in simulation as there would be no UART RX input
if (NEORV32_SYSINFO.SOC & (1<<SYSINFO_SOC_IS_SIM)) {
neorv32_uart0_printf("Skipping <read> & <write> tests as this seems to be a simulation.\n");
}
else {
neorv32_uart0_printf("<read> test (waiting for 4 chars via UART0)... ");
read((int)STDIN_FILENO, char_buffer, 4 * sizeof(char)); // get 4 chars from "STDIN" (UART0.RX)
neorv32_uart0_printf("ok\n");
 
neorv32_uart0_printf("<write> test to 'STDOUT'... (outputting the chars you have send)\n");
write((int)STDOUT_FILENO, char_buffer, 4 * sizeof(char)); // send 4 chars to "STDOUT" (UART0.TX)
neorv32_uart0_printf("\nok\n");
 
neorv32_uart0_printf("<write> test to 'STDERR'... (outputting the chars you have send)\n");
write((int)STDERR_FILENO, char_buffer, 4 * sizeof(char)); // send 4 chars to "STDERR" (UART0.TX)
neorv32_uart0_printf("\nok\n");
}
 
neorv32_uart0_printf("<free> test... ");
free(char_buffer);
neorv32_uart0_printf("ok\n");
 
 
// NOTE: exit is highly oversized as it also includes clean-up functions (destructors), which
// is not required for bare-metal or RTOS applications... better use the simple 'return' or even better
// make sure main never returns. however, let's test that 'exit' works.
neorv32_uart0_printf("<exit> test...");
exit(0);
 
return 0; // should never be reached
}
 
 
/**********************************************************************//**
* "after-main" handler that is executed after the application's
* main function returns (called by crt0.S start-up code)
**************************************************************************/
int __neorv32_crt0_after_main(int32_t return_code) {
 
neorv32_uart0_printf("\n<RTE> main function returned with exit code %i. </RTE>\n", return_code);
 
return 0;
}
/neorv32/trunk/sw/example/newlib_demo/makefile
0,0 → 1,40
#################################################################################################
# << NEORV32 - Application Makefile >> #
# ********************************************************************************************* #
# Make sure to add the RISC-V GCC compiler's bin folder to your PATH environment variable. #
# ********************************************************************************************* #
# BSD 3-Clause License #
# #
# Copyright (c) 2022, Stephan Nolting. All rights reserved. #
# #
# Redistribution and use in source and binary forms, with or without modification, are #
# permitted provided that the following conditions are met: #
# #
# 1. Redistributions of source code must retain the above copyright notice, this list of #
# conditions and the following disclaimer. #
# #
# 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
# conditions and the following disclaimer in the documentation and/or other materials #
# provided with the distribution. #
# #
# 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
# endorse or promote products derived from this software without specific prior written #
# permission. #
# #
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
# OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
# COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
# GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
# OF THE POSSIBILITY OF SUCH DAMAGE. #
# ********************************************************************************************* #
# The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
#################################################################################################
 
# Modify this variable to fit your NEORV32 setup (neorv32 home folder)
NEORV32_HOME ?= ../../..
 
include $(NEORV32_HOME)/sw/common/common.mk
/neorv32/trunk/sw/lib/include/neorv32.h
52,6 → 52,8
#include <stdint.h>
#include <inttypes.h>
#include <limits.h>
#include <unistd.h>
#include <stdlib.h>
 
 
/**********************************************************************//**
194,6 → 196,19
CSR_PMPADDR62 = 0x3ee, /**< 0x3ee - pmpaddr62 (r/w): Physical memory protection address register 62 */
CSR_PMPADDR63 = 0x3ef, /**< 0x3ef - pmpaddr63 (r/w): Physical memory protection address register 63 */
 
CSR_TSELECT = 0x7a0, /**< 0x7a0 - tselect (r/(w)): Trigger select */
CSR_TDATA1 = 0x7a1, /**< 0x7a1 - tdata1 (r/(w)): Trigger data register 0 */
CSR_TDATA2 = 0x7a2, /**< 0x7a2 - tdata2 (r/(w)): Trigger data register 1 */
CSR_TDATA3 = 0x7a3, /**< 0x7a3 - tdata3 (r/(w)): Trigger data register 2 */
CSR_TINFO = 0x7a4, /**< 0x7a4 - tinfo (r/(w)): Trigger info */
CSR_TCONTROL = 0x7a5, /**< 0x7a5 - tcontrol (r/(w)): Trigger control */
CSR_MCONTEXT = 0x7a8, /**< 0x7a8 - mcontext (r/(w)): Machine context register */
CSR_SCONTEXT = 0x7aa, /**< 0x7aa - scontext (r/(w)): Supervisor context register */
 
//CSR_DCSR = 0x7b0, /**< 0x7b0 - dcsr (-/-): Debug status and control register */
//CSR_DPC = 0x7b1, /**< 0x7b1 - dpc (-/-): Debug program counter */
//CSR_DSCRATCHC = 0x7b2, /**< 0x7b2 - dscratch (-/-): Debug scratch register */
 
CSR_MCYCLE = 0xb00, /**< 0xb00 - mcycle (r/w): Machine cycle counter low word */
CSR_MINSTRET = 0xb02, /**< 0xb02 - minstret (r/w): Machine instructions-retired counter low word */
 
272,7 → 287,9
CSR_MARCHID = 0xf12, /**< 0xf12 - marchid (r/-): Architecture ID */
CSR_MIMPID = 0xf13, /**< 0xf13 - mimpid (r/-): Implementation ID/version */
CSR_MHARTID = 0xf14, /**< 0xf14 - mhartid (r/-): Hardware thread ID (always 0) */
CSR_MCONFIGPTR = 0xf15 /**< 0xf15 - mconfigptr (r/-): Machine configuration pointer register */
CSR_MCONFIGPTR = 0xf15, /**< 0xf15 - mconfigptr (r/-): Machine configuration pointer register */
 
CSR_MXISA = 0xfc0 /**< 0xfc0 - xisa (r/-): NEORV32-specific machine "extended CPU ISA and extensions" */
};
 
 
410,6 → 427,29
 
 
/**********************************************************************//**
* CPU <b>mxisa</b> CSR (r/-): Machine _extended_ instruction set extensions (NEORV32-spec.)
**************************************************************************/
enum NEORV32_CSR_XISA_enum {
// ISA (sub-)extensions
CSR_MXISA_ZICSR = 0, /**< CPU mxisa CSR (0): privileged architecture (r/-)*/
CSR_MXISA_ZIFENCEI = 1, /**< CPU mxisa CSR (1): instruction stream sync (r/-)*/
CSR_MXISA_ZMMUL = 2, /**< CPU mxisa CSR (2): hardware mul/div (r/-)*/
CSR_MXISA_ZXCFU = 3, /**< CPU mxisa CSR (3): custom RISC-V instructions (r/-)*/
 
CSR_MXISA_ZFINX = 5, /**< CPU mxisa CSR (5): FPU using x registers, "F-alternative" (r/-)*/
CSR_MXISA_ZXSCNT = 6, /**< CPU mxisa CSR (6): reduced-size CPU counters (from Zicntr) (r/-)*/
CSR_MXISA_ZICNTR = 7, /**< CPU mxisa CSR (7): base instructions, cycle and time CSRs (r/-)*/
CSR_MXISA_PMP = 8, /**< CPU mxisa CSR (8): physical memory protection (also "Smpmp") (r/-)*/
CSR_MXISA_ZIHPM = 9, /**< CPU mxisa CSR (9): hardware performance monitors (r/-)*/
CSR_MXISA_DEBUGMODE = 10, /**< CPU mxisa CSR (10): RISC-V debug mode (r/-)*/
 
// Tuning options
CSR_MXISA_FASTMUL = 30, /**< CPU mxisa CSR (30): DSP-based multiplication (M extensions only) (r/-)*/
CSR_MXISA_FASTSHIFT = 31 /**< CPU mxisa CSR (31): parallel logic for shifts (barrel shifters) (r/-)*/
};
 
 
/**********************************************************************//**
* CPU <b>mhpmevent</b> hardware performance monitor events
**************************************************************************/
enum NEORV32_HPMCNT_EVENT_enum {
1237,7 → 1277,7
/** SYSINFO module prototype - whole module is read-only */
typedef struct __attribute__((packed,aligned(4))) {
const uint32_t CLK; /**< offset 0: clock speed in Hz */
const uint32_t CPU; /**< offset 4: CPU core features (#NEORV32_SYSINFO_CPU_enum) */
const uint32_t reserved; /**< offset 4: reserved */
const uint32_t SOC; /**< offset 8: SoC features (#NEORV32_SYSINFO_SOC_enum) */
const uint32_t CACHE; /**< offset 12: cache configuration (#NEORV32_SYSINFO_CACHE_enum) */
const uint32_t ISPACE_BASE; /**< offset 16: instruction memory address space base */
1249,23 → 1289,6
/** SYSINFO module hardware access (#neorv32_sysinfo_t) */
#define NEORV32_SYSINFO (*((volatile neorv32_sysinfo_t*) (0xFFFFFFE0UL)))
 
/** NEORV32_SYSINFO.CPU (r/-): Implemented CPU sub-extensions/features */
enum NEORV32_SYSINFO_CPU_enum {
SYSINFO_CPU_ZICSR = 0, /**< SYSINFO_CPU (0): Zicsr extension (I sub-extension) available when set (r/-) */
SYSINFO_CPU_ZIFENCEI = 1, /**< SYSINFO_CPU (1): Zifencei extension (I sub-extension) available when set (r/-) */
SYSINFO_CPU_ZMMUL = 2, /**< SYSINFO_CPU (2): Zmmul extension (M sub-extension) available when set (r/-) */
 
SYSINFO_CPU_ZFINX = 5, /**< SYSINFO_CPU (5): Zfinx extension (F sub-/alternative-extension) available when set (r/-) */
SYSINFO_CPU_ZXSCNT = 6, /**< SYSINFO_CPU (6): Custom extension - Small CPU counters: "cycle" & "instret" CSRs have less than 64-bit when set (r/-) */
SYSINFO_CPU_ZICNTR = 7, /**< SYSINFO_CPU (7): Basic CPU counters available when set (r/-) */
SYSINFO_CPU_PMP = 8, /**< SYSINFO_CPU (8): PMP (physical memory protection) extension available when set (r/-) */
SYSINFO_CPU_ZIHPM = 9, /**< SYSINFO_CPU (9): HPM (hardware performance monitors) extension available when set (r/-) */
SYSINFO_CPU_DEBUGMODE = 10, /**< SYSINFO_CPU (10): RISC-V CPU debug mode available when set (r/-) */
 
SYSINFO_CPU_FASTMUL = 30, /**< SYSINFO_CPU (30): fast multiplications (via FAST_MUL_EN generic) available when set (r/-) */
SYSINFO_CPU_FASTSHIFT = 31 /**< SYSINFO_CPU (31): fast shifts (via FAST_SHIFT_EN generic) available when set (r/-) */
};
 
/** NEORV32_SYSINFO.SOC (r/-): Implemented processor devices/features */
enum NEORV32_SYSINFO_SOC_enum {
SYSINFO_SOC_BOOTLOADER = 0, /**< SYSINFO_FEATURES (0) (r/-): Bootloader implemented when 1 (via INT_BOOTLOADER_EN generic) */
1322,14 → 1345,15
 
 
// ----------------------------------------------------------------------------
// Include all IO driver headers
// Include all system header files
// ----------------------------------------------------------------------------
// intrinsics
#include "neorv32_intrinsics.h"
 
// cpu core
#include "neorv32_cpu.h"
#include "neorv32_cpu_cfu.h"
 
// intrinsics
#include "neorv32_intrinsics.h"
 
// neorv32 runtime environment
#include "neorv32_rte.h"
 
/neorv32/trunk/sw/lib/include/neorv32_cpu_cfu.h
0,0 → 1,71
// #################################################################################################
// # << NEORV32: neorv32_cfu.h - CPU Core - CFU Co-Processor Hardware Driver >> #
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
// # #
// # Redistribution and use in source and binary forms, with or without modification, are #
// # permitted provided that the following conditions are met: #
// # #
// # 1. Redistributions of source code must retain the above copyright notice, this list of #
// # conditions and the following disclaimer. #
// # #
// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
// # conditions and the following disclaimer in the documentation and/or other materials #
// # provided with the distribution. #
// # #
// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
// # endorse or promote products derived from this software without specific prior written #
// # permission. #
// # #
// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
// # OF THE POSSIBILITY OF SUCH DAMAGE. #
// # ********************************************************************************************* #
// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
// #################################################################################################
 
 
/**********************************************************************//**
* @file neorv32_cpu_cfu.h
* @author Stephan Nolting
* @brief CPU Core custom functions unit HW driver header file.
**************************************************************************/
 
#ifndef neorv32_cpu_cfu_h
#define neorv32_cpu_cfu_h
 
// prototypes
int neorv32_cpu_cfu_available(void);
 
 
/**********************************************************************//**
* @name CFU custom instructions (intrinsic)
**************************************************************************/
/**@{*/
/** CFU custom instruction 0 (funct3 = 000) */
#define neorv32_cfu_cmd0(funct7, rs1, rs2) CUSTOM_INSTR_R2_TYPE(funct7, rs2, rs1, 0, RISCV_OPCODE_CUSTOM0)
/** CFU custom instruction 1 (funct3 = 001) */
#define neorv32_cfu_cmd1(funct7, rs1, rs2) CUSTOM_INSTR_R2_TYPE(funct7, rs2, rs1, 1, RISCV_OPCODE_CUSTOM0)
/** CFU custom instruction 2 (funct3 = 010) */
#define neorv32_cfu_cmd2(funct7, rs1, rs2) CUSTOM_INSTR_R2_TYPE(funct7, rs2, rs1, 2, RISCV_OPCODE_CUSTOM0)
/** CFU custom instruction 3 (funct3 = 011) */
#define neorv32_cfu_cmd3(funct7, rs1, rs2) CUSTOM_INSTR_R2_TYPE(funct7, rs2, rs1, 3, RISCV_OPCODE_CUSTOM0)
/** CFU custom instruction 4 (funct3 = 100) */
#define neorv32_cfu_cmd4(funct7, rs1, rs2) CUSTOM_INSTR_R2_TYPE(funct7, rs2, rs1, 4, RISCV_OPCODE_CUSTOM0)
/** CFU custom instruction 5 (funct3 = 101) */
#define neorv32_cfu_cmd5(funct7, rs1, rs2) CUSTOM_INSTR_R2_TYPE(funct7, rs2, rs1, 5, RISCV_OPCODE_CUSTOM0)
/** CFU custom instruction 6 (funct3 = 110) */
#define neorv32_cfu_cmd6(funct7, rs1, rs2) CUSTOM_INSTR_R2_TYPE(funct7, rs2, rs1, 6, RISCV_OPCODE_CUSTOM0)
/** CFU custom instruction 7 (funct3 = 111) */
#define neorv32_cfu_cmd7(funct7, rs1, rs2) CUSTOM_INSTR_R2_TYPE(funct7, rs2, rs1, 7, RISCV_OPCODE_CUSTOM0)
/**@}*/
 
#endif // neorv32_cpu_cfu_h
/neorv32/trunk/sw/lib/include/neorv32_intrinsics.h
154,6 → 154,10
asm(".set regnum_t4 , 29");
asm(".set regnum_t5 , 30");
asm(".set regnum_t6 , 31");
 
/** Official RISC-V opcodes for custom extensions (CUSTOM0, CUSTOM1) */
asm(".set RISCV_OPCODE_CUSTOM0 , 0b0001011");
asm(".set RISCV_OPCODE_CUSTOM1 , 0b0101011");
/**@}*/
 
 
193,7 → 197,8
asm volatile ( \
"" \
: [output] "=r" (__return) \
: [input_i] "r" (rs1), [input_j] "r" (rs2) \
: [input_i] "r" (rs1), \
[input_j] "r" (rs2) \
); \
asm volatile ( \
".word ( \
205,7 → 210,8
(((" #opcode ") & 0x7f) << 0) \
);" \
: [rd] "=r" (__return) \
: "r" (rs1), "r" (rs2) \
: "r" (rs1), \
"r" (rs2) \
); \
__return; \
})
220,7 → 226,9
asm volatile ( \
"" \
: [output] "=r" (__return) \
: [input_i] "r" (rs1), [input_j] "r" (rs2), [input_k] "r" (rs3) \
: [input_i] "r" (rs1), \
[input_j] "r" (rs2), \
[input_k] "r" (rs3) \
); \
asm volatile ( \
".word ( \
232,7 → 240,9
(((" #opcode ") & 0x7f) << 0) \
);" \
: [rd] "=r" (__return) \
: "r" (rs1), "r" (rs2), "r" (rs3) \
: "r" (rs1), \
"r" (rs2), \
"r" (rs3) \
); \
__return; \
})
/neorv32/trunk/sw/lib/source/neorv32_cfs.c
3,7 → 3,7
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
// # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
// # #
// # Redistribution and use in source and binary forms, with or without modification, are #
// # permitted provided that the following conditions are met: #
49,7 → 49,7
 
 
/**********************************************************************//**
* Check if custom functions unit 0 was synthesized.
* Check if custom functions subsystem was synthesized.
*
* @return 0 if CFS was not synthesized, 1 if CFS is available.
**************************************************************************/
/neorv32/trunk/sw/lib/source/neorv32_cpu.c
46,10 → 46,6
/**********************************************************************//**
* Unavailable extensions warning.
**************************************************************************/
#if defined __riscv_f || (__riscv_flen == 32)
#warning Single-precision floating-point extension <F/Zfinx> is WORK-IN-PROGRESS and there is NO NATIVE SUPPORT BY THE COMPILER yet!
#endif
 
#if defined __riscv_d || (__riscv_flen == 64)
#error Double-precision floating-point extension <D/Zdinx> is NOT supported!
#endif
58,10 → 54,6
#error Only 32-bit <rv32> is supported!
#endif
 
#ifdef __riscv_b
#warning Bit-manipulation extension <B> is still experimental (non-ratified) and does not support all <Zb*> subsets yet.
#endif
 
#ifdef __riscv_fdiv
#warning Floating-point division instruction <FDIV> is NOT supported yet!
#endif
273,8 → 265,8
/**********************************************************************//**
* Delay function using busy wait.
*
* @note This function uses the time CSRs (from int./ext. MTIME). A simple ASM loop
* is used as fall back if system timer is not advancing (no MTIME available).
* @note This function uses MTIME as time base. A simple ASM loop
* is used as fall back if system timer is not implemented.
*
* @warning Delay time might be less precise if M extensions is not available
* (especially if MTIME unit is not available).
286,15 → 278,16
uint32_t clock = NEORV32_SYSINFO.CLK; // clock ticks per second
clock = clock / 1000; // clock ticks per ms
 
uint64_t wait_cycles = ((uint64_t)clock) * ((uint64_t)time_ms);
register uint64_t wait_cycles = ((uint64_t)clock) * ((uint64_t)time_ms);
register uint64_t tmp = 0;
 
register uint64_t tmp = neorv32_cpu_get_systime();
if (neorv32_cpu_get_systime() > tmp) { // system time advancing (MTIME available and running)?
// MTIME available?
if (NEORV32_SYSINFO.SOC & (1 << SYSINFO_SOC_IO_MTIME)) {
 
// use MTIME machine timer
tmp += wait_cycles;
tmp = neorv32_mtime_get_time() + wait_cycles;
while(1) {
if (neorv32_cpu_get_systime() >= tmp) {
if (neorv32_mtime_get_time() >= tmp) {
break;
}
}
304,7 → 297,7
// warning! not really precise (especially if M extensions is not available)!
 
const uint32_t loop_cycles_c = 16; // clock cycles per iteration of the ASM loop
uint32_t iterations = (uint32_t)(wait_cycles / loop_cycles_c);
register uint32_t iterations = (uint32_t)(wait_cycles / loop_cycles_c); // M (div) extension would be nice here!
 
asm volatile (" .balign 4 \n" // make sure this is 32-bit aligned
" __neorv32_cpu_delay_ms_start: \n"
347,7 → 340,7
uint32_t neorv32_cpu_pmp_get_num_regions(void) {
 
// PMP implemented at all?
if ((NEORV32_SYSINFO.CPU & (1<<SYSINFO_CPU_PMP)) == 0) {
if ((neorv32_cpu_csr_read(CSR_MXISA) & (1<<CSR_MXISA_PMP)) == 0) {
return 0;
}
 
612,7 → 605,7
uint32_t neorv32_cpu_hpm_get_counters(void) {
 
// HPMs implemented at all?
if ((NEORV32_SYSINFO.CPU & (1<<SYSINFO_CPU_ZIHPM)) == 0) {
if ((neorv32_cpu_csr_read(CSR_MXISA) & (1<<CSR_MXISA_ZIHPM)) == 0) {
return 0;
}
 
695,7 → 688,7
uint32_t neorv32_cpu_hpm_get_size(void) {
 
// HPMs implemented at all?
if ((NEORV32_SYSINFO.CPU & (1<<SYSINFO_CPU_ZIHPM)) == 0) {
if ((neorv32_cpu_csr_read(CSR_MXISA) & (1<<CSR_MXISA_ZIHPM)) == 0) {
return 0;
}
 
/neorv32/trunk/sw/lib/source/neorv32_cpu_cfu.c
0,0 → 1,60
// #################################################################################################
// # << NEORV32: neorv32_cfu.c - CPU Core - CFU Co-Processor Hardware Driver >> #
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
// # #
// # Redistribution and use in source and binary forms, with or without modification, are #
// # permitted provided that the following conditions are met: #
// # #
// # 1. Redistributions of source code must retain the above copyright notice, this list of #
// # conditions and the following disclaimer. #
// # #
// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
// # conditions and the following disclaimer in the documentation and/or other materials #
// # provided with the distribution. #
// # #
// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
// # endorse or promote products derived from this software without specific prior written #
// # permission. #
// # #
// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
// # OF THE POSSIBILITY OF SUCH DAMAGE. #
// # ********************************************************************************************* #
// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
// #################################################################################################
 
 
/**********************************************************************//**
* @file neorv32_cpu_cfu.c
* @author Stephan Nolting
* @brief CPU Core custom functions unit HW driver source file.
**************************************************************************/
 
#include "neorv32.h"
#include "neorv32_cpu_cfu.h"
 
 
/**********************************************************************//**
* Check if custom functions unit was synthesized.
*
* @return 0 if CFU was not synthesized, 1 if CFU is available.
**************************************************************************/
int neorv32_cpu_cfu_available(void) {
 
// this is an ISA extension - not a SoC module
if (neorv32_cpu_csr_read(CSR_MXISA) & (1 << CSR_MXISA_ZXCFU)) {
return 1;
}
else {
return 0;
}
}
/neorv32/trunk/sw/lib/source/neorv32_rte.c
336,38 → 336,41
}
// Z* CPU extensions
tmp = NEORV32_SYSINFO.CPU;
if (tmp & (1<<SYSINFO_CPU_ZICSR)) {
tmp = neorv32_cpu_csr_read(CSR_MXISA);
if (tmp & (1<<CSR_MXISA_ZICSR)) {
neorv32_uart0_printf("Zicsr ");
}
if (tmp & (1<<SYSINFO_CPU_ZICNTR)) {
if (tmp & (1<<CSR_MXISA_ZICNTR)) {
neorv32_uart0_printf("Zicntr ");
}
if (tmp & (1<<SYSINFO_CPU_ZIHPM)) {
if (tmp & (1<<CSR_MXISA_ZIHPM)) {
neorv32_uart0_printf("Zihpm ");
}
if (tmp & (1<<SYSINFO_CPU_ZIFENCEI)) {
if (tmp & (1<<CSR_MXISA_ZIFENCEI)) {
neorv32_uart0_printf("Zifencei ");
}
if (tmp & (1<<SYSINFO_CPU_ZMMUL)) {
if (tmp & (1<<CSR_MXISA_ZMMUL)) {
neorv32_uart0_printf("Zmmul ");
}
if (tmp & (1<<SYSINFO_CPU_ZFINX)) {
if (tmp & (1<<CSR_MXISA_ZFINX)) {
neorv32_uart0_printf("Zfinx ");
}
if (tmp & (1<<SYSINFO_CPU_ZXSCNT)) {
if (tmp & (1<<CSR_MXISA_ZXCFU)) {
neorv32_uart0_printf("Zxcfu ");
}
if (tmp & (1<<CSR_MXISA_ZXSCNT)) {
neorv32_uart0_printf("Zxscnt(!) ");
}
if (tmp & (1<<SYSINFO_CPU_DEBUGMODE)) {
neorv32_uart0_printf("Debug ");
if (tmp & (1<<CSR_MXISA_DEBUGMODE)) {
neorv32_uart0_printf("DebugMode ");
}
 
// CPU extension options
neorv32_uart0_printf("\nExtension options: ");
if (tmp & (1<<SYSINFO_CPU_FASTMUL)) {
if (tmp & (1<<CSR_MXISA_FASTMUL)) {
neorv32_uart0_printf("FAST_MUL ");
}
if (tmp & (1<<SYSINFO_CPU_FASTSHIFT)) {
if (tmp & (1<<CSR_MXISA_FASTSHIFT)) {
neorv32_uart0_printf("FAST_SHIFT ");
}
 
/neorv32/trunk/sw/lib/source/neorv32_uart.c
3,7 → 3,7
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
// # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
// # #
// # Redistribution and use in source and binary forms, with or without modification, are #
// # permitted provided that the following conditions are met: #
52,6 → 52,7
// Private functions
static void __neorv32_uart_itoa(uint32_t x, char *res) __attribute__((unused)); // GCC: do not output a warning when this variable is unused
static void __neorv32_uart_tohex(uint32_t x, char *res) __attribute__((unused)); // GCC: do not output a warning when this variable is unused
static void __neorv32_uart_touppercase(uint32_t len, char *ptr) __attribute__((unused)); // GCC: do not output a warning when this variable is unused
/// \endcond
 
 
97,6 → 98,7
 
// raw clock prescaler
#ifndef make_bootloader
// use div instructions
i = (uint16_t)(clock / (2*baudrate));
#else
// division via repeated subtraction (minimal size, only for bootloader)
324,9 → 326,11
* <TABLE>
* <TR><TD>%s</TD><TD>String (array of chars, zero-terminated)</TD></TR>
* <TR><TD>%c</TD><TD>Single char</TD></TR>
* <TR><TD>%i</TD><TD>32-bit signed number, printed as decimal</TD></TR>
* <TR><TD>%d/%i</TD><TD>32-bit signed number, printed as decimal</TD></TR>
* <TR><TD>%u</TD><TD>32-bit unsigned number, printed as decimal</TD></TR>
* <TR><TD>%x</TD><TD>32-bit number, printed as 8-char hexadecimal</TD></TR>
* <TR><TD>%x</TD><TD>32-bit number, printed as 8-char hexadecimal - lower-case</TD></TR>
* <TR><TD>%X</TD><TD>32-bit number, printed as 8-char hexadecimal - upper-case</TD></TR>
* <TR><TD>%p</TD><TD>32-bit pointer, printed as 8-char hexadecimal - lower-case</TD></TR>
* </TABLE>
**************************************************************************/
void neorv32_uart0_printf(const char *format, ...) {
348,6 → 352,7
neorv32_uart0_putc((char)va_arg(a, int));
break;
case 'i': // 32-bit signed
case 'd':
n = (int32_t)va_arg(a, int32_t);
if (n < 0) {
n = -n;
361,7 → 366,12
neorv32_uart0_print(string_buf);
break;
case 'x': // 32-bit hexadecimal
case 'p':
case 'X':
__neorv32_uart_tohex(va_arg(a, uint32_t), string_buf);
if (c == 'X') {
__neorv32_uart_touppercase(11, string_buf);
}
neorv32_uart0_print(string_buf);
break;
default: // unsupported format
465,7 → 475,7
uint8_t p = 0; // initial prsc = CLK/2
 
// raw clock prescaler
#ifdef make_bootloader
#ifndef make_bootloader
// use div instructions
i = (uint16_t)(clock / (2*baudrate));
#else
691,9 → 701,11
* <TABLE>
* <TR><TD>%s</TD><TD>String (array of chars, zero-terminated)</TD></TR>
* <TR><TD>%c</TD><TD>Single char</TD></TR>
* <TR><TD>%i</TD><TD>32-bit signed number, printed as decimal</TD></TR>
* <TR><TD>%d/%i</TD><TD>32-bit signed number, printed as decimal</TD></TR>
* <TR><TD>%u</TD><TD>32-bit unsigned number, printed as decimal</TD></TR>
* <TR><TD>%x</TD><TD>32-bit number, printed as 8-char hexadecimal</TD></TR>
* <TR><TD>%x</TD><TD>32-bit number, printed as 8-char hexadecimal - lower-case</TD></TR>
* <TR><TD>%X</TD><TD>32-bit number, printed as 8-char hexadecimal - upper-case</TD></TR>
* <TR><TD>%p</TD><TD>32-bit pointer, printed as 8-char hexadecimal - lower-case</TD></TR>
* </TABLE>
**************************************************************************/
void neorv32_uart1_printf(const char *format, ...) {
715,6 → 727,7
neorv32_uart1_putc((char)va_arg(a, int));
break;
case 'i': // 32-bit signed
case 'd':
n = (int32_t)va_arg(a, int32_t);
if (n < 0) {
n = -n;
728,7 → 741,12
neorv32_uart1_print(string_buf);
break;
case 'x': // 32-bit hexadecimal
case 'p':
case 'X':
__neorv32_uart_tohex(va_arg(a, uint32_t), string_buf);
if (c == 'X') {
__neorv32_uart_touppercase(11, string_buf);
}
neorv32_uart1_print(string_buf);
break;
default: // unsupported format
853,3 → 871,24
 
res[8] = '\0'; // terminate result string
}
 
 
/**********************************************************************//**
* Private function to cast a string to UPPERCASE.
*
* @param[in] len Total length of input string.
* @param[in,out] ptr Pointer for input/output string.
**************************************************************************/
static void __neorv32_uart_touppercase(uint32_t len, char *ptr) {
 
char tmp;
 
while (len > 0) {
tmp = *ptr;
if ((tmp >= 'a') && (tmp <= 'z')) {
*ptr = tmp - 32;
}
ptr++;
len--;
}
}
/neorv32/trunk/sw/lib/source/syscalls.c
0,0 → 1,297
/* An extremely minimalist syscalls.c for newlib
* Based on riscv newlib libgloss/riscv/sys_*.c
*
* Copyright 2019 Clifford Wolf
* Copyright 2019 ETH Zürich and University of Bologna
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
* REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
* INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
* LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
 
/**********************************************************************//**
* @file syscalls.c
* @author Modified for the NEORV32 RISC-V Processor by Stephan Nolting
* @brief Newlib system calls
*
* @warning UART0 (if available) is used to read/write console data (STDIN, STDOUT, STDERR, ...).
*
* @note Original source file: https://github.com/openhwgroup/cv32e40p/blob/master/example_tb/core/custom/syscalls.c
* @note Original license: SOLDERPAD HARDWARE LICENSE version 0.51
* @note More information was derived from: https://interrupt.memfault.com/blog/boostrapping-libc-with-newlib#implementing-newlib
**************************************************************************/
 
#include <sys/stat.h>
#include <sys/timeb.h>
#include <sys/times.h>
#include <utime.h>
#include <newlib.h>
#include <unistd.h>
#include <errno.h>
#include <neorv32.h>
 
#undef errno
extern int errno;
 
// defined in sw/common/crt0.S
extern const volatile unsigned int __crt0_main_exit;
 
/* It turns out that older newlib versions use different symbol names which goes
* against newlib recommendations. Anyway this is fixed in later version.
*/
#if __NEWLIB__ <= 2 && __NEWLIB_MINOR__ <= 5
# define _sbrk sbrk
# define _write write
# define _close close
# define _lseek lseek
# define _read read
# define _fstat fstat
# define _isatty isatty
#endif
 
void unimplemented_syscall()
{
if (neorv32_uart0_available()) {
neorv32_uart0_print("<syscalls.c> Unimplemented system call called!\n");
}
}
 
int nanosleep(const struct timespec *rqtp, struct timespec *rmtp)
{
errno = ENOSYS;
return -1;
}
 
int _access(const char *file, int mode)
{
errno = ENOSYS;
return -1;
}
 
int _chdir(const char *path)
{
errno = ENOSYS;
return -1;
}
 
int _chmod(const char *path, mode_t mode)
{
errno = ENOSYS;
return -1;
}
 
int _chown(const char *path, uid_t owner, gid_t group)
{
errno = ENOSYS;
return -1;
}
 
int _close(int file)
{
return -1;
}
 
int _execve(const char *name, char *const argv[], char *const env[])
{
errno = ENOMEM;
return -1;
}
 
void _exit(int exit_status)
{
// jump to crt0's shutdown code
asm volatile ("la t0, __crt0_main_exit \n"
"jr t0 \n");
 
while(1); // will never be reached
}
 
int _faccessat(int dirfd, const char *file, int mode, int flags)
{
errno = ENOSYS;
return -1;
}
 
int _fork(void)
{
errno = EAGAIN;
return -1;
}
 
int _fstat(int file, struct stat *st)
{
st->st_mode = S_IFCHR; // all files are "character special files"
return 0;
}
 
int _fstatat(int dirfd, const char *file, struct stat *st, int flags)
{
errno = ENOSYS;
return -1;
}
 
int _ftime(struct timeb *tp)
{
errno = ENOSYS;
return -1;
}
 
char *_getcwd(char *buf, size_t size)
{
errno = -ENOSYS;
return NULL;
}
 
int _getpid()
{
return 1;
}
 
int _gettimeofday(struct timeval *tp, void *tzp)
{
errno = -ENOSYS;
return -1;
}
 
int _isatty(int file)
{
return (file == STDOUT_FILENO);
}
 
int _kill(int pid, int sig)
{
errno = EINVAL;
return -1;
}
 
int _link(const char *old_name, const char *new_name)
{
errno = EMLINK;
return -1;
}
 
off_t _lseek(int file, off_t ptr, int dir)
{
return 0;
}
 
int _lstat(const char *file, struct stat *st)
{
errno = ENOSYS;
return -1;
}
 
int _open(const char *name, int flags, int mode)
{
return -1;
}
 
int _openat(int dirfd, const char *name, int flags, int mode)
{
errno = ENOSYS;
return -1;
}
 
ssize_t _read(int file, void *ptr, size_t len)
{
int read_cnt = 0;
 
// read everything (STDIN, ...) from NEORV32.UART0 (if available)
if (neorv32_uart0_available()) {
char *char_ptr;
char_ptr = (char *)ptr;
while (len > 0) {
*char_ptr++ = (char)neorv32_uart0_getc();
read_cnt++;
len--;
}
}
 
return read_cnt;
}
 
int _stat(const char *file, struct stat *st)
{
st->st_mode = S_IFCHR;
return 0;
// errno = ENOSYS;
// return -1;
}
 
long _sysconf(int name)
{
 
return -1;
}
 
clock_t _times(struct tms *buf)
{
return -1;
}
 
int _unlink(const char *name)
{
errno = ENOENT;
return -1;
}
 
int _utime(const char *path, const struct utimbuf *times)
{
errno = ENOSYS;
return -1;
}
 
int _wait(int *status)
{
errno = ECHILD;
return -1;
}
 
ssize_t _write(int file, const void *ptr, size_t len)
{
// write everything (STDOUT, STDERR, ...) to NEORV32.UART0 (if available)
const void *eptr = ptr + len;
if (neorv32_uart0_available()) {
while (ptr != eptr) {
neorv32_uart0_putc(*(char *)(ptr++));
}
return len;
}
else {
return (size_t)0; // nothing sent
}
}
 
extern char __heap_start[];
extern char __heap_end[];
static char *brk = __heap_start;
 
int _brk(void *addr)
{
brk = addr;
return 0;
}
 
void *_sbrk(ptrdiff_t incr)
{
char *old_brk = brk;
 
if (__heap_start == __heap_end) {
return NULL;
}
 
if ((brk += incr) < __heap_end) {
brk += incr;
} else {
brk = __heap_end;
}
return old_brk;
}
/neorv32/trunk/sw/openocd/openocd_neorv32.cfg
2,7 → 2,7
# references: https://mcuoneclipse.com/2019/10/20/jtag-debugging-the-esp32-with-ft2232-and-openocd/
 
# ----------------------------------------------
# Interface configuration
# Interface/adapter configuration
# ----------------------------------------------
 
# FT2232H pinout:
13,12 → 13,12
# TRST: D4 (low-active, optional - pull input pin high if not used)
 
adapter driver ftdi
ftdi_vid_pid 0x0403 0x6010
ftdi_channel 0
ftdi_layout_init 0x0038 0x003b
ftdi vid_pid 0x0403 0x6010
ftdi channel 0
ftdi layout_init 0x0038 0x003b
 
adapter speed 1000
ftdi_layout_signal nTRST -ndata 0x0010 -noe 0x0040
ftdi layout_signal nTRST -ndata 0x0010 -noe 0x0040
transport select jtag
 
# ----------------------------------------------
34,8 → 34,30
target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
 
# ----------------------------------------------
# Access memory via program buffer
# ----------------------------------------------
 
riscv set_mem_access progbuf
 
# ----------------------------------------------
# Scratch pad RAM
# ----------------------------------------------
 
# work area ("scratch pad RAM"): beginning of (internal) DMEM, 256 bytes, requires(!) backup
$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 256 -work-area-backup 1
 
# ----------------------------------------------
# Expose NEORV32-specific CSRs
# ----------------------------------------------
 
riscv expose_csrs 4032=mxisa
 
# ----------------------------------------------
# Start session
# ----------------------------------------------
 
init
halt
 
echo "Target HALTED."
echo "Ready for remote connections."
/neorv32/trunk/sw/svd/neorv32.svd
1208,25 → 1208,6
<access>read-only</access>
</register>
<register>
<name>CPU</name>
<description>CPU core features</description>
<addressOffset>0x04</addressOffset>
<access>read-only</access>
<fields>
<field><name>SYSINFO_CPU_ZICSR</name><bitRange>[0:0]</bitRange><description>Zicsr extension (I sub-extension) available when set</description></field>
<field><name>SYSINFO_CPU_ZIFENCEI</name><bitRange>[1:1]</bitRange><description>Zifencei extension (I sub-extension) available when set</description></field>
<field><name>SYSINFO_CPU_ZMMUL</name><bitRange>[2:2]</bitRange><description>Zmmul extension (M sub-extension) available when set</description></field>
<field><name>SYSINFO_CPU_ZFINX</name><bitRange>[5:5]</bitRange><description>Zfinx extension (F sub-/alternative-extension) available when set</description></field>
<field><name>SYSINFO_CPU_ZXSCNT</name><bitRange>[6:6]</bitRange><description>Custom extension - Small CPU counters</description></field>
<field><name>SYSINFO_CPU_ZICNTR</name><bitRange>[7:7]</bitRange><description>Basic CPU counters available when set</description></field>
<field><name>SYSINFO_CPU_PMP</name><bitRange>[8:8]</bitRange><description>PMP (physical memory protection) extension available when set</description></field>
<field><name>SYSINFO_CPU_ZIHPM</name><bitRange>[9:9]</bitRange><description>HPM (hardware performance monitors) extension available when set</description></field>
<field><name>SYSINFO_CPU_DEBUGMODE</name><bitRange>[10:10]</bitRange><description>RISC-V CPU debug mode available when set</description></field>
<field><name>SYSINFO_CPU_FASTMUL</name><bitRange>[30:30]</bitRange><description>fast multiplications (via FAST_MUL_EN generic) available when set</description></field>
<field><name>SYSINFO_CPU_FASTSHIFT</name><bitRange>[31:31]</bitRange><description>fast shifts (via FAST_SHIFT_EN generic) available when set</description></field>
</fields>
</register>
<register>
<name>SOC</name>
<description>SoC features</description>
<addressOffset>0x08</addressOffset>
/neorv32/trunk/CHANGELOG.md
10,15 → 10,22
The _hardware version identifier_ uses an additional custom version element (i.e. `MAJOR.MINOR.PATCH.individual`) to track _individual_ changes.
The identifier number is incremented with every core RTL modification and also by major framework modifications.
 
:information_source: The processor can determine its version from the `mimpid` CSR (at CSR address 0xf13). A 8x4-bit BCD representation is used.
Leading zeros are optional. Example: `CSR(mimpid) = 0x01040312 => 01.04.03.12 = Version 01.04.03.12 = v1.4.3.12`. The version number is globally
defined by the `hw_version_c` constant in the main VHDL package file [`rtl/core/neorv32_package.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_package.vhd).
:information_source: The processor can determine its version from the `mimpid` CSR.
A 8x4-bit BCD representation is used. Leading zeros are optional. Example:
 
```
mimpid (@0xf13) = 0x01040312 => 01.04.03.12 => Version 01.04.03.12 => v1.4.3.12
```
 
The version number is globally defined by the `hw_version_c` constant in the main VHDL package file
[`rtl/core/neorv32_package.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_package.vhd).
 
 
### Version History
 
* :bug: = bug-fix
* :sparkles: = new feature
* :test_tube: = new (experimental) feature
* :warning: = (major) change that might impact compatibility with previous versions
* :lock: = security issue
* :rocket: = release
26,6 → 33,17
 
| Date (*dd.mm.yyyy*) | Version | Comment |
|:----------:|:-------:|:--------|
| 17.02.2022 |[**:rocket:1.6.8**](https://github.com/stnolting/neorv32/releases/tag/v1.6.8) | **New release** |
| 17.02.2022 | 1.6.7.10 | hardwired `dcsr.stopcount` to `1`: all standard counters (`[m]cycle[h]` and `[m]instret[h]`, but **NOT** `[m]time[h]`!!) and all hardware performance monitor (HPM) counters are _stopped_ when the CPU is in debug mode; [PR #277](https://github.com/stnolting/neorv32/pull/277) |
| 16.02.2022 | 1.6.7.9 | :warning: **added custom `mxisa` CSR replacing SYSINFO's `NEORV32_SYSINFO.CPU` memory-mapped register**: bit-positions remain but names and the actual access mechanism (CSR vs. memory-mapped) have changed! see [PR #276](https://github.com/stnolting/neorv32/pull/276) |
| 11.02.2022 | 1.6.7.8 | :test_tube: added newlib's system calls (stubs) and linker script symbols for heap memory to support **dynamic memory allocation** (e.g. `malloc`) and even **standard IO functions** like `printf`; see [PR #275](https://github.com/stnolting/neorv32/pull/275) |
| 10.02.2022 | 1.6.7.7 | :sparkles: added **RISC-V hardware trigger module** to CPU - allows to set _hardware breakpoints_ (via gdb's `hb`/`hbreak` command) to debug code from ROM; see [PR #274](https://github.com/stnolting/neorv32/pull/274); :bug: minor bug fix in `ebreak` instruction's `dcsr.cause` value (was 0b010 but has to be 0b001) |
| 08.02.2022 | 1.6.7.6 | :warning: renamed default branch of repository to `main` |
| 07.02.2022 | 1.6.7.5 | removed default values for bi-directional top entity ports `twi_sda_io` and `twi_scl_io` |
| 05.02.2022 | 1.6.7.4 | added `err_o` signal to **IMEM** module; if the IMEM is implemented as true ROM any write attempt will raise a _store access fault_ exception (with a `[DEVICE_ERR]` error); see [PR #273](https://github.com/stnolting/neorv32/pull/273) |
| 03.02.2022 | 1.6.7.3 | :test_tube: using `LTO` (link-time-optimization) option for **bootloader**; improved bootloader user console; see [PR #268](https://github.com/stnolting/neorv32/pull/268) |
| 31.01.2022 | 1.6.7.2 | :bug: fixed minor bug in **bootloader's MTIME handling** (bootloader crashed if `Zicntr` ISA extension not enabled), fixed minor issues in MTIME and `time` CSRs handling; added MTIME example program; see [PR #267](https://github.com/stnolting/neorv32/pull/267) |
| 30.01.2022 | 1.6.7.1 | :sparkles: added **`Zxcfu` ISA extension for user-defined custom RISC-V instructions**; see [PR #264](https://github.com/stnolting/neorv32/pull/264) |
| 28.01.2022 |[**:rocket:1.6.7**](https://github.com/stnolting/neorv32/releases/tag/v1.6.7) | **New release** |
| 28.01.2022 | 1.6.6.10 | :bug: fixed bug in **bit-manipulation co-processor**: decoding collision between `cpop` and `rol` instructions; :bug: fixed bug in co-processor arbitration when an illegal instruction is detected; added four additional (yet unused) **CPU** co-processor slots; [PR #262](https://github.com/stnolting/neorv32/pull/262) |
| 27.01.2022 | 1.6.6.9 | reworked **CFS** "user" logic; added CFS demo program; see [PR #261](https://github.com/stnolting/neorv32/pull/261) |
/neorv32/trunk/README.md
1,4 → 1,4
[![NEORV32](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/neorv32_logo_dark.png)](https://github.com/stnolting/neorv32)
[![NEORV32](https://raw.githubusercontent.com/stnolting/neorv32/main/docs/figures/neorv32_logo_dark.png)](https://github.com/stnolting/neorv32)
 
# The NEORV32 RISC-V Processor
 
25,7 → 25,7
 
## 1. Overview
 
![neorv32 Overview](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/neorv32_processor.png)
![neorv32 Overview](https://raw.githubusercontent.com/stnolting/neorv32/main/docs/figures/neorv32_processor.png)
 
The NEORV32 Processor is a **customizable microcontroller-like system on chip (SoC)** that is based on the
[RISC-V](https://riscv.org/) NEORV32 CPU.
38,9 → 38,10
 
:interrobang: Want to know more? Check out the [project's rationale](https://stnolting.github.io/neorv32/#_rationale).
 
:books: For detailed information take a look at the [NEORV32 documentation](https://stnolting.github.io/neorv32/) (online at GitHub-pages).
:books: For detailed information take a look at the [NEORV32 online documentation](https://stnolting.github.io/neorv32/).
The latest _pdf_ versions can be found [here](https://github.com/stnolting/neorv32/releases/tag/nightly).
 
:label: The project's change log is available in [`CHANGELOG.md`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
:label: The project's change log is available in [`CHANGELOG.md`](https://github.com/stnolting/neorv32/blob/main/CHANGELOG.md).
To see the changes between _official releases_ visit the project's [release page](https://github.com/stnolting/neorv32/releases).
 
:package: [**Exemplary setups**](https://github.com/stnolting/neorv32-setups) targeting
51,7 → 52,7
:bulb: Feel free to open a [new issue](https://github.com/stnolting/neorv32/issues) or start a
[new discussion](https://github.com/stnolting/neorv32/discussions) if you have questions, comments, ideas or if something is
not working as expected. Or have a chat on our [gitter channel](https://gitter.im/neorv32/community).
See how to [contribute](https://github.com/stnolting/neorv32/blob/master/CONTRIBUTING.md).
See how to [contribute](https://github.com/stnolting/neorv32/blob/main/CONTRIBUTING.md).
 
:rocket: Check out the [quick links below](#5-Getting-Started) or directly jump to the
[*User Guide*](https://stnolting.github.io/neorv32/ug/) to get started
72,9 → 73,9
[![release](https://img.shields.io/github/v/release/stnolting/neorv32?longCache=true&style=flat-square&logo=GitHub)](https://github.com/stnolting/neorv32/releases)
[![GitHub Pages](https://img.shields.io/website.svg?label=stnolting.github.io%2Fneorv32&longCache=true&style=flat-square&url=http%3A%2F%2Fstnolting.github.io%2Fneorv32%2Findex.html&logo=GitHub)](https://stnolting.github.io/neorv32)
\
[![Documentation](https://img.shields.io/github/workflow/status/stnolting/neorv32/Documentation/master?longCache=true&style=flat-square&label=Documentation&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32/actions?query=workflow%3ADocumentation)
[![riscv-arch-test](https://img.shields.io/github/workflow/status/stnolting/neorv32/riscv-arch-test/master?longCache=true&style=flat-square&label=riscv-arch-test&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32/actions?query=workflow%3Ariscv-arch-test)
[![Processor](https://img.shields.io/github/workflow/status/stnolting/neorv32/Processor/master?longCache=true&style=flat-square&label=Processor&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32/actions?query=workflow%3AProcessor)
[![Documentation](https://img.shields.io/github/workflow/status/stnolting/neorv32/Documentation/main?longCache=true&style=flat-square&label=Documentation&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32/actions?query=workflow%3ADocumentation)
[![riscv-arch-test](https://img.shields.io/github/workflow/status/stnolting/neorv32/riscv-arch-test/main?longCache=true&style=flat-square&label=riscv-arch-test&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32/actions?query=workflow%3Ariscv-arch-test)
[![Processor](https://img.shields.io/github/workflow/status/stnolting/neorv32/Processor/main?longCache=true&style=flat-square&label=Processor&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32/actions?query=workflow%3AProcessor)
 
[[back to top](#The-NEORV32-RISC-V-Processor)]
 
112,8 → 113,8
 
* 32-bit external bus interface, Wishbone b4 compatible
([WISHBONE](https://stnolting.github.io/neorv32/#_processor_external_memory_interface_wishbone_axi4_lite))
* [wrapper](https://github.com/stnolting/neorv32/blob/master/rtl/system_integration/neorv32_SystemTop_axi4lite.vhd) for AXI4-Lite master interface
* [wrapper](https://github.com/stnolting/neorv32/blob/master/rtl/system_integration/neorv32_SystemTop_AvalonMM.vhd) for Avalon-MM master interface
* [wrapper](https://github.com/stnolting/neorv32/blob/main/rtl/system_integration/neorv32_SystemTop_axi4lite.vhd) for AXI4-Lite host interface
* [wrapper](https://github.com/stnolting/neorv32/blob/main/rtl/system_integration/neorv32_SystemTop_AvalonMM.vhd) for Avalon-MM host interface
* 32-bit stream link interface with up to 8 independent RX and TX links
([SLINK](https://stnolting.github.io/neorv32/#_stream_link_interface_slink))
* AXI4-Stream compatible
122,12 → 123,15
 
**Advanced**
 
* on-chip debugger ([OCD](https://stnolting.github.io/neorv32/#_on_chip_debugger_ocd)) accessible via JTAG interface - implementing
the "Minimal RISC-V Debug Specification Version 0.13.2" and compatible with **OpenOCD** + **gdb** and **Segger Embedded Studio**
* on-chip debugger ([OCD](https://stnolting.github.io/neorv32/#_on_chip_debugger_ocd)) accessible via JTAG interface - compliant to
the "Minimal RISC-V Debug Specification Version 0.13.2" and compatible with **OpenOCD** + **gdb** and **Segger Embedded Studio**;
includes RISC-V _hardware trigger module_
* _true random_ number generator ([TRNG](https://stnolting.github.io/neorv32/#_true_random_number_generator_trng))
* execute in place module ([XIP](https://stnolting.github.io/neorv32/#_execute_in_place_module_xip)) to directly execute code from SPI flash
* custom functions subsystem ([CFS](https://stnolting.github.io/neorv32/#_custom_functions_subsystem_cfs))
for tightly-coupled custom co-processor extensions and interfaces
for tightly-coupled custom accelerators and interfaces
* custom functions unit ([CFU](https://stnolting.github.io/neorv32/#_custom_functions_unit_cfu)) for up to 1024
_custom RISC-V instructions_
 
[[back to top](#The-NEORV32-RISC-V-Processor)]
 
141,9 → 145,8
estimation of the actual setup's hardware requirements.
 
:bulb: The [`neorv32-setups`](https://github.com/stnolting/neorv32-setups) repository provides exemplary FPGA
setups targeting various FPGA boards and toolchains. These setups also provide resource utilization reports for different
SoC configurations. The latest utilization reports for those setups can be found in the report of the
[Implementation Workflow](https://github.com/stnolting/neorv32-setups/actions/workflows/Implementation.yml).
setups targeting various FPGA boards and toolchains. The latest bitstreams and utilization reports for those setups
can be found in the assets of the [Implementation Workflow](https://github.com/stnolting/neorv32-setups/actions/workflows/Implementation.yml).
 
[[back to top](#The-NEORV32-RISC-V-Processor)]
 
152,14 → 155,14
## 3. NEORV32 CPU Features
 
The NEORV32 CPU implements the RISC-V 32-bit `rv32i` ISA with optional extensions (see below). It is compatible to subsets of the
*Unprivileged ISA Specification* [(Version 2.2)](https://github.com/stnolting/neorv32/blob/master/docs/references/riscv-spec.pdf)
and the *Privileged Architecture Specification* [(Version 1.12-draft)](https://github.com/stnolting/neorv32/blob/master/docs/references/riscv-privileged.pdf).
*Unprivileged ISA Specification* [(Version 2.2)](https://github.com/stnolting/neorv32/blob/main/docs/references/riscv-spec.pdf)
and the *Privileged Architecture Specification* [(Version 1.12-draft)](https://github.com/stnolting/neorv32/blob/main/docs/references/riscv-privileged.pdf).
Compatibility is checked by passing the [official RISC-V architecture tests](https://github.com/riscv/riscv-arch-test).
 
The core is a little-endian Von-Neumann machine implemented as multi-cycle architecture.
However, the CPU's _front end_ (instruction fetch) and _back end_ (instruction execution) can work independently to increase performance.
Currently, three privilege levels (`machine` and optional `user` and `debug_mode`) are supported. The CPU implements all three standard RISC-V machine
interrupts (`MTI`, `MEI`, `MSI`) plus 16 _fast interrupt requests_ as custom extensions.
However, the CPU's_front end (instruction fetch) and back end (instruction execution) can work independently to increase performance.
Currently, two privilege levels "machine-mode" and optional "user-mode" are supported. The CPU implements all three standard RISC-V machine
interrupts (MTI, MEI, MSI) plus 16 _fast interrupt requests_ as custom extensions.
It also supports **all** standard RISC-V exceptions (instruction/load/store misaligned address & bus access fault, illegal
instruction, breakpoint, environment calls).
 
187,6 → 190,7
[[`Zihpm`](https://stnolting.github.io/neorv32/#_zihpm_hardware_performance_monitors)]
[[`Zifencei`](https://stnolting.github.io/neorv32/#_zifencei_instruction_stream_synchronization)]
[[`Zmmul`](https://stnolting.github.io/neorv32/#_zmmul_integer_multiplication)]
[[`Zxcfu`](https://stnolting.github.io/neorv32/#_zxcfu_custom_instructions_extension_cfu)]
[[`PMP`](https://stnolting.github.io/neorv32/#_pmp_physical_memory_protection)]
[[`DEBUG`](https://stnolting.github.io/neorv32/#_cpu_debug_mode)]**
 
202,7 → 206,7
Implementation results for _exemplary_ CPU configuration generated for an **Intel Cyclone IV EP4CE22F17C6N FPGA**
using **Intel Quartus Prime Lite 20.1** ("balanced implementation, Slow 1200mV 0C Model").
 
| CPU Configuration (version [1.5.7.10](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md)) | LEs | FFs | Memory bits | DSPs | f_max |
| CPU Configuration (version [1.5.7.10](https://github.com/stnolting/neorv32/blob/main/CHANGELOG.md)) | LEs | FFs | Memory bits | DSPs | f_max |
|:------------------------|:----:|:----:|:----:|:-:|:-------:|
| `rv32i` | 806 | 359 | 1024 | 0 | 125 MHz |
| `rv32i_Zicsr_Zicntr` | 1729 | 813 | 1024 | 0 | 124 MHz |
221,10 → 225,10
available CPU extensions.
 
The following table shows the performance results (scores and average CPI) for exemplary CPU configurations executing
2000 iterations of the [CoreMark](https://github.com/stnolting/neorv32/blob/master/sw/example/coremark) CPU benchmark
(using plain rv32i built-in libraries only!).
2000 iterations of the [CoreMark](https://github.com/stnolting/neorv32/blob/main/sw/example/coremark) CPU benchmark
(using plain GCC10 rv32i built-in libraries only!).
 
| CPU Configuration (version [1.5.7.10](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md)) | CoreMark Score | CoreMarks/MHz | Average CPI |
| CPU Configuration (version [1.5.7.10](https://github.com/stnolting/neorv32/blob/main/CHANGELOG.md)) | CoreMark Score | CoreMarks/MHz | Average CPI |
|:------------------------------------------------|:-----:|:----------:|:--------:|
| _small_ (`rv32i_Zicsr`) | 33.89 | **0.3389** | **4.04** |
| _medium_ (`rv32imc_Zicsr`) | 62.50 | **0.6250** | **5.34** |
239,13 → 243,13
 
## 4. Software Framework and Tooling
 
* [core libraries](https://github.com/stnolting/neorv32/tree/master/sw/lib) for high-level usage of the provided functions and peripherals
* [core libraries](https://github.com/stnolting/neorv32/tree/main/sw/lib) for high-level usage of the provided functions and peripherals
* application compilation based on GNU makefiles
* gcc-based toolchain ([pre-compiled toolchains available](https://github.com/stnolting/riscv-gcc-prebuilt))
* [SVD file](https://github.com/stnolting/neorv32/tree/master/sw/svd) for advanced debugging and IDE integration
* [SVD file](https://github.com/stnolting/neorv32/tree/main/sw/svd) for advanced debugging and IDE integration
* bootloader with UART interface console
* runtime environment for handling traps
* several [example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) to get started including CoreMark, FreeRTOS and Conway's Game of Life
* several [example programs](https://github.com/stnolting/neorv32/tree/main/sw/example) to get started including CoreMark, FreeRTOS and Conway's Game of Life
* doxygen-based documentation, available on [GitHub pages](https://stnolting.github.io/neorv32/sw/files.html)
* supports implementation using open source tooling ([GHDL](https://github.com/ghdl/ghdl), Yosys, nextpnr, ...) - both, software and hardware can be
developed and debugged with open source tooling
269,7 → 273,7
 
### :electric_plug: Hardware Overview
 
* [Rationale](https://stnolting.github.io/neorv32/#_rationale) - NEORV32: why, how come, what for
* [Rationale](https://stnolting.github.io/neorv32/#_rationale) - NEORV32: why? how come? what for?
 
* [NEORV32 Processor](https://stnolting.github.io/neorv32/#_neorv32_processor_soc) - the SoC
* [Top Entity - Signals](https://stnolting.github.io/neorv32/#_processor_top_entity_signals) - how to connect to the processor
287,9 → 291,9
 
### :floppy_disk: Software Overview
 
* [Example Programs](https://github.com/stnolting/neorv32/tree/master/sw/example) - test program execution on your setup
* [Example Programs](https://github.com/stnolting/neorv32/tree/main/sw/example) - test program execution on your setup
* [Core Libraries](https://stnolting.github.io/neorv32/#_core_libraries) - high-level functions for accessing the processor's peripherals
* [Software Framework Documentation](https://stnolting.github.io/neorv32/sw/files.html) - `doxygen`-based documentation
* [Software Framework Documentation](https://stnolting.github.io/neorv32/sw/files.html) - _doxygen_-based documentation
* [Application Makefiles](https://stnolting.github.io/neorv32/#_application_makefile) - turning your application into an executable
* [Bootloader](https://stnolting.github.io/neorv32/#_bootloader) - the build-in NEORV32 bootloader
 
298,7 → 302,7
* [Toolchain Setup](https://stnolting.github.io/neorv32/ug/#_software_toolchain_setup) - install and setup RISC-V gcc
* [General Hardware Setup](https://stnolting.github.io/neorv32/ug/#_general_hardware_setup) - setup a new NEORV32 EDA project
* [General Software Setup](https://stnolting.github.io/neorv32/ug/#_general_software_framework_setup) - configure the software framework
* [Application Compilation](https://stnolting.github.io/neorv32/ug/#_application_program_compilation) - compile an application using `make`
* [Application Compilation](https://stnolting.github.io/neorv32/ug/#_application_program_compilation) - compile an application using "make"
* [Upload via Bootloader](https://stnolting.github.io/neorv32/ug/#_uploading_and_starting_of_a_binary_executable_image_via_uart) - upload and execute executables
* [Application-Specific Processor Configuration](https://stnolting.github.io/neorv32/ug/#_application_specific_processor_configuration) - tailor the processor to your needs
* [Adding Custom Hardware Modules](https://stnolting.github.io/neorv32/ug/#_adding_custom_hardware_modules) - add _your_ custom hardware
308,15 → 312,15
 
### :copyright: Legal
 
[![license](https://img.shields.io/github/license/stnolting/neorv32?longCache=true&style=flat)](https://github.com/stnolting/neorv32/blob/master/LICENSE)
[![license](https://img.shields.io/github/license/stnolting/neorv32?longCache=true&style=flat)](https://github.com/stnolting/neorv32/blob/main/LICENSE)
[![DOI](https://zenodo.org/badge/DOI/10.5281/zenodo.5018888.svg)](https://doi.org/10.5281/zenodo.5018888)
 
* [Overview](https://stnolting.github.io/neorv32/#_legal) - license, disclaimer, limitation of liability for external links, proprietary notice, ...
* [Citing](https://stnolting.github.io/neorv32/#_citing) - citing information
* [Impressum](https://github.com/stnolting/neorv32/blob/master/docs/impressum.md) - imprint
* [Impressum](https://github.com/stnolting/neorv32/blob/main/docs/impressum.md) - imprint
 
This is an open-source project that is free of charge. Use this project in any way you like
(as long as it complies to the permissive [license](https://github.com/stnolting/neorv32/blob/master/LICENSE)).
(as long as it complies to the permissive [license](https://github.com/stnolting/neorv32/blob/main/LICENSE)).
Please quote it appropriately. :+1:
 
[[back to top](#The-NEORV32-RISC-V-Processor)]

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