URL
https://opencores.org/ocsvn/uart16550/uart16550/trunk
Subversion Repositories uart16550
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- This comparison shows the changes necessary to convert path
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- from Rev 74 to Rev 75
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Rev 74 → Rev 75
/trunk/rtl/verilog/uart_wb.v
64,6 → 64,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.13 2002/02/07 16:20:20 gorban |
// major bug in 32-bit mode that prevented register access fixed. |
// |
// Revision 1.12 2001/12/19 08:03:34 mohor |
// Warnings cleared. |
// |
262,10 → 265,17
reg [1:0] adr2 ; // lower 2 bits of regenerated address |
always @(wb_sel_is) |
case (wb_sel_is) |
`ifdef BIG_BYTE_ENDIAN |
4'b0001 : adr2 = 2'b11; |
4'b0010 : adr2 = 2'b10; |
4'b0100 : adr2 = 2'b01; |
4'b1000 : adr2 = 2'b00; |
`else |
4'b0001 : adr2 = 2'b00; |
4'b0010 : adr2 = 2'b01; |
4'b0100 : adr2 = 2'b10; |
4'b1000 : adr2 = 2'b11; |
`endif |
default : adr2 = 2'b0; |
endcase // case(wb_sel_is) |
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/trunk/rtl/verilog/uart_defines.v
63,6 → 63,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.10 2001/12/11 08:55:40 mohor |
// Scratch register define added. |
// |
// Revision 1.9 2001/12/03 21:44:29 gorban |
// Updated specification documentation. |
// Added full 32-bit data bus interface, now as default. |
111,6 → 114,8
// also, in 8-bit version there'll be no debugging features included |
// `define DATA_BUS_WIDTH_8 |
|
`define BIG_BYTE_ENDIAN // Defines endian |
|
`ifdef DATA_BUS_WIDTH_8 |
`define UART_ADDR_WIDTH 3 |
`define UART_DATA_WIDTH 8 |