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Rev 8 → Rev 9

/trunk/pipelining/f.vhd File deleted
/trunk/pipelining/camellia128_tb.vhd File deleted
/trunk/pipelining/camellia256_tb.vhd File deleted
/trunk/pipelining/keysched128.vhd File deleted
/trunk/pipelining/sbox1.vhd File deleted
/trunk/pipelining/fl128.vhd File deleted
/trunk/pipelining/keysched256.vhd File deleted
/trunk/pipelining/sbox2.vhd File deleted
/trunk/pipelining/sbox3.vhd File deleted
/trunk/pipelining/fl256.vhd File deleted
/trunk/pipelining/sbox4.vhd File deleted
/trunk/pipelining/camellia128.vhd File deleted
/trunk/pipelining/camellia256.vhd File deleted
/trunk/pipelining/6round128.vhd File deleted
/trunk/pipelining/camellia128_tb.do File deleted
/trunk/pipelining/6round256.vhd File deleted
/trunk/pipelining/f_tb.vhd File deleted
/trunk/pipelining/camellia256_tb.do File deleted
/trunk/LICENSE File deleted
/trunk/looping/control.vhd File deleted
/trunk/looping/fl.vhd File deleted
/trunk/looping/f.vhd File deleted
/trunk/looping/camellia_if.vhd File deleted
/trunk/looping/datapath.vhd File deleted
/trunk/looping/camellia.vhd File deleted
/trunk/looping/f_tb.vhd File deleted
/trunk/looping/f_tb.do File deleted
/trunk/looping/sbox1.vhd File deleted
/trunk/looping/camellia_tb.vhd File deleted
/trunk/looping/sbox2.vhd File deleted
/trunk/looping/camellia_tb.do File deleted
/trunk/looping/sbox3.vhd File deleted
/trunk/looping/sbox4.vhd File deleted
/camellia-vhdl/trunk/pipelining/sbox4.vhd
0,0 → 1,72
 
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 09/14/2007
-- Last Update: 04/14/2008
-- Project Name: camellia-vhdl
-- Description: Dual-port SBOX4
--
-- Copyright (C) 2007 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
 
 
entity SBOX4 is
port (
clk : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(0 to 7);
addrb : IN STD_LOGIC_VECTOR(0 to 7);
douta : OUT STD_LOGIC_VECTOR(0 to 7);
doutb : OUT STD_LOGIC_VECTOR(0 to 7)
);
end SBOX4;
 
architecture RTL of SBOX4 is
 
component SBOX1 is
port (
clk : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(0 to 7);
addrb : IN STD_LOGIC_VECTOR(0 to 7);
douta : OUT STD_LOGIC_VECTOR(0 to 7);
doutb : OUT STD_LOGIC_VECTOR(0 to 7)
);
end component;
 
-- SBOX1 signals
signal s1_addra : STD_LOGIC_VECTOR(0 to 7);
signal s1_addrb : STD_LOGIC_VECTOR(0 to 7);
signal s1_clk : STD_LOGIC;
signal s1_douta : STD_LOGIC_VECTOR(0 to 7);
signal s1_doutb : STD_LOGIC_VECTOR(0 to 7);
 
begin
 
S1 : SBOX1
port map(s1_clk, s1_addra, s1_addrb, s1_douta, s1_doutb);
 
s1_clk <= clk;
s1_addra <= addra(1 to 7) & addra(0);
s1_addrb <= addrb(1 to 7) & addrb(0);
 
douta <= s1_douta;
doutb <= s1_doutb;
 
end RTL;
/camellia-vhdl/trunk/pipelining/camellia128.vhd
0,0 → 1,600
 
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 09/14/2007
-- Last Update: 04/14/2008
-- Project Name: camellia-vhdl
-- Description: Camellia top level module, only for 128-bit key en/decryption
--
-- Copyright (C) 2007 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
 
 
entity CAMELLIA128 is
port(
reset : in STD_LOGIC;
clk : in STD_LOGIC;
input : in STD_LOGIC_VECTOR (0 to 127); -- input data
input_en : in STD_LOGIC; -- input enable
key : in STD_LOGIC_VECTOR (0 to 127); -- key
enc_dec : in STD_LOGIC; -- dec=0 enc, dec=1 dec
output : out STD_LOGIC_VECTOR (0 to 127); -- en/decrypted data
output_rdy : out STD_LOGIC -- output ready
);
end CAMELLIA128;
 
architecture RTL of CAMELLIA128 is
 
component KEYSCHED128 is
port (
reset : in STD_LOGIC;
clk : in STD_LOGIC;
kl_in : in STD_LOGIC_VECTOR (0 to 127);
kl_out : out STD_LOGIC_VECTOR (0 to 127);
ka_out : out STD_LOGIC_VECTOR (0 to 127)
);
end component;
 
component SIXROUND128 is
generic (
k1e_offset : INTEGER;
k1e_shift : INTEGER;
k2e_offset : INTEGER;
k2e_shift : INTEGER;
k3e_offset : INTEGER;
k3e_shift : INTEGER;
k4e_offset : INTEGER;
k4e_shift : INTEGER;
k5e_offset : INTEGER;
k5e_shift : INTEGER;
k6e_offset : INTEGER;
k6e_shift : INTEGER;
k1d_offset : INTEGER;
k1d_shift : INTEGER;
k2d_offset : INTEGER;
k2d_shift : INTEGER;
k3d_offset : INTEGER;
k3d_shift : INTEGER;
k4d_offset : INTEGER;
k4d_shift : INTEGER;
k5d_offset : INTEGER;
k5d_shift : INTEGER;
k6d_offset : INTEGER;
k6d_shift : INTEGER
);
port(
reset : in STD_LOGIC;
clk : in STD_LOGIC;
dec1 : in STD_LOGIC;
k1 : in STD_LOGIC_VECTOR (0 to 255);
dec2 : in STD_LOGIC;
k2 : in STD_LOGIC_VECTOR (0 to 255);
dec3 : in STD_LOGIC;
k3 : in STD_LOGIC_VECTOR (0 to 255);
dec4 : in STD_LOGIC;
k4 : in STD_LOGIC_VECTOR (0 to 255);
dec5 : in STD_LOGIC;
k5 : in STD_LOGIC_VECTOR (0 to 255);
dec6 : in STD_LOGIC;
k6 : in STD_LOGIC_VECTOR (0 to 255);
l_in : in STD_LOGIC_VECTOR (0 to 63);
r_in : in STD_LOGIC_VECTOR (0 to 63);
l_out : out STD_LOGIC_VECTOR (0 to 63);
r_out : out STD_LOGIC_VECTOR (0 to 63)
);
end component;
 
component FL128 is
generic (
fl_ke_offset : INTEGER;
fl_ke_shift : INTEGER;
fli_ke_offset : INTEGER;
fli_ke_shift : INTEGER;
fl_kd_offset : INTEGER;
fl_kd_shift : INTEGER;
fli_kd_offset : INTEGER;
fli_kd_shift : INTEGER
);
port(
reset : in STD_LOGIC;
clk : in STD_LOGIC;
fl_in : in STD_LOGIC_VECTOR (0 to 63);
fli_in : in STD_LOGIC_VECTOR (0 to 63);
k : in STD_LOGIC_VECTOR (0 to 255);
dec : in STD_LOGIC;
fl_out : out STD_LOGIC_VECTOR (0 to 63);
fli_out : out STD_LOGIC_VECTOR (0 to 63)
);
end component;
 
 
-- input registers
signal reg_m : STD_LOGIC_VECTOR (0 to 127);
signal reg_k : STD_LOGIC_VECTOR (0 to 127);
signal reg_dec : STD_LOGIC;
signal reg_rdy : STD_LOGIC;
 
-- used by pre-whitening
signal kw1_enc : STD_LOGIC_VECTOR (0 to 63);
signal kw2_enc : STD_LOGIC_VECTOR (0 to 63);
signal ka_s111_dec : STD_LOGIC_VECTOR (0 to 127);
signal kw1_dec : STD_LOGIC_VECTOR (0 to 63);
signal kw2_dec : STD_LOGIC_VECTOR (0 to 63);
signal kw1 : STD_LOGIC_VECTOR (0 to 63);
signal kw2 : STD_LOGIC_VECTOR (0 to 63);
signal w1 : STD_LOGIC_VECTOR (0 to 63);
signal w2 : STD_LOGIC_VECTOR (0 to 63);
 
-- used by post-whitening
signal ka_s111_enc : STD_LOGIC_VECTOR (0 to 127);
signal kw3_enc : STD_LOGIC_VECTOR (0 to 63);
signal kw4_enc : STD_LOGIC_VECTOR (0 to 63);
signal kw3_dec : STD_LOGIC_VECTOR (0 to 63);
signal kw4_dec : STD_LOGIC_VECTOR (0 to 63);
signal kw3 : STD_LOGIC_VECTOR (0 to 63);
signal kw4 : STD_LOGIC_VECTOR (0 to 63);
signal w3 : STD_LOGIC_VECTOR (0 to 63);
signal w4 : STD_LOGIC_VECTOR (0 to 63);
 
-- registers used during key schedule
signal reg_a1_m : STD_LOGIC_VECTOR (0 to 127);
signal reg_a1_dec : STD_LOGIC;
signal reg_a1_rdy : STD_LOGIC;
signal reg_a2_m : STD_LOGIC_VECTOR (0 to 127);
signal reg_a2_dec : STD_LOGIC;
signal reg_a2_rdy : STD_LOGIC;
signal reg_a3_m : STD_LOGIC_VECTOR (0 to 127);
signal reg_a3_dec : STD_LOGIC;
signal reg_a3_rdy : STD_LOGIC;
signal reg_a4_m : STD_LOGIC_VECTOR (0 to 127);
signal reg_a4_dec : STD_LOGIC;
signal reg_a4_rdy : STD_LOGIC;
 
-- registers used during 6-rounds and fls
signal reg_b1_dec : STD_LOGIC;
signal reg_b1_k : STD_LOGIC_VECTOR (0 to 255);
signal reg_b1_rdy : STD_LOGIC;
signal reg_b2_dec : STD_LOGIC;
signal reg_b2_k : STD_LOGIC_VECTOR (0 to 255);
signal reg_b2_rdy : STD_LOGIC;
signal reg_b3_dec : STD_LOGIC;
signal reg_b3_k : STD_LOGIC_VECTOR (0 to 255);
signal reg_b3_rdy : STD_LOGIC;
signal reg_b4_dec : STD_LOGIC;
signal reg_b4_k : STD_LOGIC_VECTOR (0 to 255);
signal reg_b4_rdy : STD_LOGIC;
signal reg_b5_dec : STD_LOGIC;
signal reg_b5_k : STD_LOGIC_VECTOR (0 to 255);
signal reg_b5_rdy : STD_LOGIC;
signal reg_b6_dec : STD_LOGIC;
signal reg_b6_k : STD_LOGIC_VECTOR (0 to 255);
signal reg_b6_rdy : STD_LOGIC;
signal reg_b7_dec : STD_LOGIC;
signal reg_b7_k : STD_LOGIC_VECTOR (0 to 255);
signal reg_b7_rdy : STD_LOGIC;
signal reg_b8_dec : STD_LOGIC;
signal reg_b8_k : STD_LOGIC_VECTOR (0 to 255);
signal reg_b8_rdy : STD_LOGIC;
signal reg_b9_dec : STD_LOGIC;
signal reg_b9_k : STD_LOGIC_VECTOR (0 to 255);
signal reg_b9_rdy : STD_LOGIC;
signal reg_b10_dec : STD_LOGIC;
signal reg_b10_k : STD_LOGIC_VECTOR (0 to 255);
signal reg_b10_rdy : STD_LOGIC;
signal reg_b11_dec : STD_LOGIC;
signal reg_b11_k : STD_LOGIC_VECTOR (0 to 255);
signal reg_b11_rdy : STD_LOGIC;
signal reg_b12_dec : STD_LOGIC;
signal reg_b12_k : STD_LOGIC_VECTOR (0 to 255);
signal reg_b12_rdy : STD_LOGIC;
signal reg_b13_dec : STD_LOGIC;
signal reg_b13_k : STD_LOGIC_VECTOR (0 to 255);
signal reg_b13_rdy : STD_LOGIC;
signal reg_b14_dec : STD_LOGIC;
signal reg_b14_k : STD_LOGIC_VECTOR (0 to 255);
signal reg_b14_rdy : STD_LOGIC;
signal reg_b15_dec : STD_LOGIC;
signal reg_b15_k : STD_LOGIC_VECTOR (0 to 255);
signal reg_b15_rdy : STD_LOGIC;
signal reg_b16_dec : STD_LOGIC;
signal reg_b16_k : STD_LOGIC_VECTOR (0 to 255);
signal reg_b16_rdy : STD_LOGIC;
signal reg_b17_dec : STD_LOGIC;
signal reg_b17_k : STD_LOGIC_VECTOR (0 to 255);
signal reg_b17_rdy : STD_LOGIC;
signal reg_b18_dec : STD_LOGIC;
signal reg_b18_k : STD_LOGIC_VECTOR (0 to 255);
signal reg_b18_rdy : STD_LOGIC;
signal reg_b19_dec : STD_LOGIC;
signal reg_b19_k : STD_LOGIC_VECTOR (0 to 255);
signal reg_b19_rdy : STD_LOGIC;
signal reg_b20_dec : STD_LOGIC;
signal reg_b20_k : STD_LOGIC_VECTOR (0 to 255);
signal reg_b20_rdy : STD_LOGIC;
 
-- components outputs
signal out_ksched : STD_LOGIC_VECTOR (0 to 255); -- key schedule
signal out_r1l : STD_LOGIC_VECTOR (0 to 63); -- first six-round
signal out_r1r : STD_LOGIC_VECTOR (0 to 63);
signal out_r2l : STD_LOGIC_VECTOR (0 to 63); -- second six-round
signal out_r2r : STD_LOGIC_VECTOR (0 to 63);
signal out_r3l : STD_LOGIC_VECTOR (0 to 63); -- third six-round
signal out_r3r : STD_LOGIC_VECTOR (0 to 63);
signal out_fl1l : STD_LOGIC_VECTOR (0 to 63); -- first fl
signal out_fl1r : STD_LOGIC_VECTOR (0 to 63);
signal out_fl2l : STD_LOGIC_VECTOR (0 to 63); -- second fl
signal out_fl2r : STD_LOGIC_VECTOR (0 to 63);
 
-- constants
constant KL_OFFSET : integer := 0;
constant KA_OFFSET : integer := 128;
 
begin
 
KEY_SCHED: KEYSCHED128
PORT MAP (
reset => reset,
clk => clk,
kl_in => reg_k,
kl_out => out_ksched(KL_OFFSET to KL_OFFSET+127),
ka_out => out_ksched(KA_OFFSET to KA_OFFSET+127)
);
 
SIX1: SIXROUND128
GENERIC MAP(
k1e_offset => KA_OFFSET,
k1e_shift => 0,
k2e_offset => KA_OFFSET,
k2e_shift => 0,
k3e_offset => KL_OFFSET,
k3e_shift => 15,
k4e_offset => KL_OFFSET,
k4e_shift => 15,
k5e_offset => KA_OFFSET,
k5e_shift => 15,
k6e_offset => KA_OFFSET,
k6e_shift => 15,
k1d_offset => KL_OFFSET,
k1d_shift => 111,
k2d_offset => KL_OFFSET,
k2d_shift => 111,
k3d_offset => KA_OFFSET,
k3d_shift => 94,
k4d_offset => KA_OFFSET,
k4d_shift => 94,
k5d_offset => KL_OFFSET,
k5d_shift => 94,
k6d_offset => KL_OFFSET,
k6d_shift => 94
)
PORT MAP(
reset => reset,
clk => clk,
dec1 => reg_a4_dec,
k1 => out_ksched,
dec2 => reg_b1_dec,
k2 => reg_b1_k,
dec3 => reg_b2_dec,
k3 => reg_b2_k,
dec4 => reg_b3_dec,
k4 => reg_b3_k,
dec5 => reg_b4_dec,
k5 => reg_b4_k,
dec6 => reg_b5_dec,
k6 => reg_b5_k,
l_in => w1,
r_in => w2,
l_out => out_r1l,
r_out => out_r1r
);
 
SIX2: SIXROUND128
GENERIC MAP(
k1e_offset => KL_OFFSET,
k1e_shift => 45,
k2e_offset => KL_OFFSET,
k2e_shift => 45,
k3e_offset => KA_OFFSET,
k3e_shift => 45,
k4e_offset => KL_OFFSET,
k4e_shift => 60,
k5e_offset => KA_OFFSET,
k5e_shift => 60,
k6e_offset => KA_OFFSET,
k6e_shift => 60,
k1d_offset => KA_OFFSET,
k1d_shift => 60,
k2d_offset => KA_OFFSET,
k2d_shift => 60,
k3d_offset => KL_OFFSET,
k3d_shift => 60,
k4d_offset => KA_OFFSET,
k4d_shift => 45,
k5d_offset => KL_OFFSET,
k5d_shift => 45,
k6d_offset => KL_OFFSET,
k6d_shift => 45
)
PORT MAP(
reset => reset,
clk => clk,
dec1 => reg_b7_dec,
k1 => reg_b7_k,
dec2 => reg_b8_dec,
k2 => reg_b8_k,
dec3 => reg_b9_dec,
k3 => reg_b9_k,
dec4 => reg_b10_dec,
k4 => reg_b10_k,
dec5 => reg_b11_dec,
k5 => reg_b11_k,
dec6 => reg_b12_dec,
k6 => reg_b12_k,
l_in => out_fl1l,
r_in => out_fl1r,
l_out => out_r2l,
r_out => out_r2r
);
 
SIX3: SIXROUND128
GENERIC MAP(
k1e_offset => KL_OFFSET,
k1e_shift => 94,
k2e_offset => KL_OFFSET,
k2e_shift => 94,
k3e_offset => KA_OFFSET,
k3e_shift => 94,
k4e_offset => KA_OFFSET,
k4e_shift => 94,
k5e_offset => KL_OFFSET,
k5e_shift => 111,
k6e_offset => KL_OFFSET,
k6e_shift => 111,
k1d_offset => KA_OFFSET,
k1d_shift => 15,
k2d_offset => KA_OFFSET,
k2d_shift => 15,
k3d_offset => KL_OFFSET,
k3d_shift => 15,
k4d_offset => KL_OFFSET,
k4d_shift => 15,
k5d_offset => KA_OFFSET,
k5d_shift => 0,
k6d_offset => KA_OFFSET,
k6d_shift => 0
)
PORT MAP(
reset => reset,
clk => clk,
dec1 => reg_b14_dec,
k1 => reg_b14_k,
dec2 => reg_b15_dec,
k2 => reg_b15_k,
dec3 => reg_b16_dec,
k3 => reg_b16_k,
dec4 => reg_b17_dec,
k4 => reg_b17_k,
dec5 => reg_b18_dec,
k5 => reg_b18_k,
dec6 => reg_b19_dec,
k6 => reg_b19_k,
l_in => out_fl2l,
r_in => out_fl2r,
l_out => out_r3l,
r_out => out_r3r
);
 
FL1: FL128
GENERIC MAP (
fl_ke_offset => KA_OFFSET,
fl_ke_shift => 30,
fli_ke_offset => KA_OFFSET,
fli_ke_shift => 30,
fl_kd_offset => KL_OFFSET,
fl_kd_shift => 77,
fli_kd_offset => KL_OFFSET,
fli_kd_shift => 77
)
PORT MAP (
reset => reset,
clk => clk,
fl_in => out_r1l,
fli_in => out_r1r,
k => reg_b7_k,
dec => reg_b7_dec,
fl_out => out_fl1l,
fli_out => out_fl1r
);
 
FL2: FL128
GENERIC MAP (
fl_ke_offset => KL_OFFSET,
fl_ke_shift => 77,
fli_ke_offset => KL_OFFSET,
fli_ke_shift => 77,
fl_kd_offset => KA_OFFSET,
fl_kd_shift => 30,
fli_kd_offset => KA_OFFSET,
fli_kd_shift => 30
)
PORT MAP (
reset => reset,
clk => clk,
fl_in => out_r2l,
fli_in => out_r2r,
k => reg_b14_k,
dec => reg_b14_dec,
fl_out => out_fl2l,
fli_out => out_fl2r
);
 
process(reset, clk)
begin
if(reset = '1') then
reg_m <= (others=>'0');
reg_k <= (others=>'0');
reg_dec <= '0';
reg_rdy <= '0';
reg_a1_rdy <= '0';
reg_a2_rdy <= '0';
reg_a3_rdy <= '0';
reg_a4_rdy <= '0';
reg_b1_rdy <= '0';
reg_b2_rdy <= '0';
reg_b3_rdy <= '0';
reg_b4_rdy <= '0';
reg_b5_rdy <= '0';
reg_b6_rdy <= '0';
reg_b7_rdy <= '0';
reg_b8_rdy <= '0';
reg_b9_rdy <= '0';
reg_b10_rdy <= '0';
reg_b11_rdy <= '0';
reg_b12_rdy <= '0';
reg_b13_rdy <= '0';
reg_b14_rdy <= '0';
reg_b15_rdy <= '0';
reg_b16_rdy <= '0';
reg_b17_rdy <= '0';
reg_b18_rdy <= '0';
reg_b19_rdy <= '0';
reg_b20_rdy <= '0';
output_rdy <= '0';
elsif(rising_edge(clk)) then
reg_m <= input;
reg_k <= key;
reg_dec <= enc_dec;
reg_rdy <= input_en;
 
reg_a1_m <= reg_m;
reg_a1_dec <= reg_dec;
reg_a1_rdy <= reg_rdy;
reg_a2_m <= reg_a1_m;
reg_a2_dec <= reg_a1_dec;
reg_a2_rdy <= reg_a1_rdy;
reg_a3_m <= reg_a2_m;
reg_a3_dec <= reg_a2_dec;
reg_a3_rdy <= reg_a2_rdy;
reg_a4_m <= reg_a3_m;
reg_a4_dec <= reg_a3_dec;
reg_a4_rdy <= reg_a3_rdy;
 
reg_b1_dec <= reg_a4_dec;
reg_b1_k <= out_ksched;
reg_b1_rdy <= reg_a4_rdy;
reg_b2_dec <= reg_b1_dec;
reg_b2_k <= reg_b1_k;
reg_b2_rdy <= reg_b1_rdy;
reg_b3_dec <= reg_b2_dec;
reg_b3_k <= reg_b2_k;
reg_b3_rdy <= reg_b2_rdy;
reg_b4_dec <= reg_b3_dec;
reg_b4_k <= reg_b3_k;
reg_b4_rdy <= reg_b3_rdy;
reg_b5_dec <= reg_b4_dec;
reg_b5_k <= reg_b4_k;
reg_b5_rdy <= reg_b4_rdy;
reg_b6_dec <= reg_b5_dec;
reg_b6_k <= reg_b5_k;
reg_b6_rdy <= reg_b5_rdy;
reg_b7_dec <= reg_b6_dec;
reg_b7_k <= reg_b6_k;
reg_b7_rdy <= reg_b6_rdy;
reg_b8_dec <= reg_b7_dec;
reg_b8_k <= reg_b7_k;
reg_b8_rdy <= reg_b7_rdy;
reg_b9_dec <= reg_b8_dec;
reg_b9_k <= reg_b8_k;
reg_b9_rdy <= reg_b8_rdy;
reg_b10_dec <= reg_b9_dec;
reg_b10_k <= reg_b9_k;
reg_b10_rdy <= reg_b9_rdy;
reg_b11_dec <= reg_b10_dec;
reg_b11_k <= reg_b10_k;
reg_b11_rdy <= reg_b10_rdy;
reg_b12_dec <= reg_b11_dec;
reg_b12_k <= reg_b11_k;
reg_b12_rdy <= reg_b11_rdy;
reg_b13_dec <= reg_b12_dec;
reg_b13_k <= reg_b12_k;
reg_b13_rdy <= reg_b12_rdy;
reg_b14_dec <= reg_b13_dec;
reg_b14_k <= reg_b13_k;
reg_b14_rdy <= reg_b13_rdy;
reg_b15_dec <= reg_b14_dec;
reg_b15_k <= reg_b14_k;
reg_b15_rdy <= reg_b14_rdy;
reg_b16_dec <= reg_b15_dec;
reg_b16_k <= reg_b15_k;
reg_b16_rdy <= reg_b15_rdy;
reg_b17_dec <= reg_b16_dec;
reg_b17_k <= reg_b16_k;
reg_b17_rdy <= reg_b16_rdy;
reg_b18_dec <= reg_b17_dec;
reg_b18_k <= reg_b17_k;
reg_b18_rdy <= reg_b17_rdy;
reg_b19_dec <= reg_b18_dec;
reg_b19_k <= reg_b18_k;
reg_b19_rdy <= reg_b18_rdy;
reg_b20_dec <= reg_b19_dec;
reg_b20_k <= reg_b19_k;
reg_b20_rdy <= reg_b19_rdy;
 
-- outputs
output <= w3 & w4;
output_rdy <= reg_b20_rdy;
 
 
end if;
end process;
 
-- pre-whitening
kw1_enc <= out_ksched(KL_OFFSET to KL_OFFSET+63);
kw2_enc <= out_ksched(KL_OFFSET+64 to KL_OFFSET+127);
 
ka_s111_dec <= out_ksched(KA_OFFSET+111 to KA_OFFSET+127) &
out_ksched(KA_OFFSET to KA_OFFSET+110);
kw1_dec <= ka_s111_dec(0 to 63);
kw2_dec <= ka_s111_dec(64 to 127);
 
kw1 <= kw1_dec when reg_a4_dec='1' else kw1_enc;
kw2 <= kw2_dec when reg_a4_dec='1' else kw2_enc;
 
w1 <= reg_a4_m(0 to 63) xor kw1;
w2 <= reg_a4_m(64 to 127) xor kw2;
 
-- post-whitening
ka_s111_enc <= reg_b20_k(KA_OFFSET+111 to KA_OFFSET+127) &
reg_b20_k(KA_OFFSET to KA_OFFSET+110);
kw3_enc <= ka_s111_enc(0 to 63);
kw4_enc <= ka_s111_enc(64 to 127);
 
kw3_dec <= reg_b20_k(KL_OFFSET to KL_OFFSET+63);
kw4_dec <= reg_b20_k(KL_OFFSET+64 to KL_OFFSET+127);
 
kw3 <= kw3_dec when reg_b20_dec='1' else kw3_enc;
kw4 <= kw4_dec when reg_b20_dec='1' else kw4_enc;
 
w3 <= out_r3r xor kw3;
w4 <= out_r3l xor kw4;
 
end RTL;
/camellia-vhdl/trunk/pipelining/camellia256.vhd
0,0 → 1,1071
 
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 09/15/2007
-- Last Update: 06/23/2008
-- Project Name: camellia-vhdl
-- Description: Camellia top level module, for 128/192/256-bit keys
--
-- Copyright (C) 2007 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
 
 
entity CAMELLIA256 is
port(
reset : in STD_LOGIC;
clk : in STD_LOGIC;
input : in STD_LOGIC_VECTOR (0 to 127); -- input data
input_en : in STD_LOGIC; -- input enable
key : in STD_LOGIC_VECTOR (0 to 255); -- key
key_len : in STD_LOGIC_VECTOR (0 to 1); -- key lenght
enc_dec : in STD_LOGIC; -- dec=0 enc, dec=1 dec
output : out STD_LOGIC_VECTOR (0 to 127); -- en/decrypted data
output_rdy : out STD_LOGIC -- output ready
);
end CAMELLIA256;
 
architecture RTL of CAMELLIA256 is
 
component KEYSCHED256 is
port(
reset : in STD_LOGIC;
clk : in STD_LOGIC;
kl_in : in STD_LOGIC_VECTOR (0 to 127);
kr_in : in STD_LOGIC_VECTOR (0 to 127);
kl_out : out STD_LOGIC_VECTOR (0 to 127);
kr_out : out STD_LOGIC_VECTOR (0 to 127);
ka_out : out STD_LOGIC_VECTOR (0 to 127);
kb_out : out STD_LOGIC_VECTOR (0 to 127)
);
end component;
 
component SIXROUND256 is
generic (
k1e128_offset : INTEGER; -- encryption 128bit
k1e128_shift : INTEGER;
k2e128_offset : INTEGER;
k2e128_shift : INTEGER;
k3e128_offset : INTEGER;
k3e128_shift : INTEGER;
k4e128_offset : INTEGER;
k4e128_shift : INTEGER;
k5e128_offset : INTEGER;
k5e128_shift : INTEGER;
k6e128_offset : INTEGER;
k6e128_shift : INTEGER;
k1d128_offset : INTEGER; -- decryption 128bit
k1d128_shift : INTEGER;
k2d128_offset : INTEGER;
k2d128_shift : INTEGER;
k3d128_offset : INTEGER;
k3d128_shift : INTEGER;
k4d128_offset : INTEGER;
k4d128_shift : INTEGER;
k5d128_offset : INTEGER;
k5d128_shift : INTEGER;
k6d128_offset : INTEGER;
k6d128_shift : INTEGER;
k1e256_offset : INTEGER; -- encryption 192/256bit
k1e256_shift : INTEGER;
k2e256_offset : INTEGER;
k2e256_shift : INTEGER;
k3e256_offset : INTEGER;
k3e256_shift : INTEGER;
k4e256_offset : INTEGER;
k4e256_shift : INTEGER;
k5e256_offset : INTEGER;
k5e256_shift : INTEGER;
k6e256_offset : INTEGER;
k6e256_shift : INTEGER;
k1d256_offset : INTEGER; -- decryption 192/256bit
k1d256_shift : INTEGER;
k2d256_offset : INTEGER;
k2d256_shift : INTEGER;
k3d256_offset : INTEGER;
k3d256_shift : INTEGER;
k4d256_offset : INTEGER;
k4d256_shift : INTEGER;
k5d256_offset : INTEGER;
k5d256_shift : INTEGER;
k6d256_offset : INTEGER;
k6d256_shift : INTEGER
);
port(
reset : in STD_LOGIC;
clk : in STD_LOGIC;
dec1 : in STD_LOGIC;
k_len1 : in STD_LOGIC_VECTOR (0 to 1);
k1 : in STD_LOGIC_VECTOR (0 to 511);
dec2 : in STD_LOGIC;
k_len2 : in STD_LOGIC_VECTOR (0 to 1);
k2 : in STD_LOGIC_VECTOR (0 to 511);
dec3 : in STD_LOGIC;
k_len3 : in STD_LOGIC_VECTOR (0 to 1);
k3 : in STD_LOGIC_VECTOR (0 to 511);
dec4 : in STD_LOGIC;
k_len4 : in STD_LOGIC_VECTOR (0 to 1);
k4 : in STD_LOGIC_VECTOR (0 to 511);
dec5 : in STD_LOGIC;
k_len5 : in STD_LOGIC_VECTOR (0 to 1);
k5 : in STD_LOGIC_VECTOR (0 to 511);
dec6 : in STD_LOGIC;
k_len6 : in STD_LOGIC_VECTOR (0 to 1);
k6 : in STD_LOGIC_VECTOR (0 to 511);
l_in : in STD_LOGIC_VECTOR (0 to 63);
r_in : in STD_LOGIC_VECTOR (0 to 63);
l_out : out STD_LOGIC_VECTOR (0 to 63);
r_out : out STD_LOGIC_VECTOR (0 to 63)
);
end component;
 
component FL256 is
generic (
fl_ke128_offset : INTEGER; -- 128bit encryption
fl_ke128_shift : INTEGER;
fli_ke128_offset : INTEGER;
fli_ke128_shift : INTEGER;
fl_kd128_offset : INTEGER; -- 128bit decryption
fl_kd128_shift : INTEGER;
fli_kd128_offset : INTEGER;
fli_kd128_shift : INTEGER;
fl_ke256_offset : INTEGER; -- 192/256bit encryption
fl_ke256_shift : INTEGER;
fli_ke256_offset : INTEGER;
fli_ke256_shift : INTEGER;
fl_kd256_offset : INTEGER; -- 192/256bit decryption
fl_kd256_shift : INTEGER;
fli_kd256_offset : INTEGER;
fli_kd256_shift : INTEGER
);
port(
reset : in STD_LOGIC;
clk : in STD_LOGIC;
fl_in : in STD_LOGIC_VECTOR (0 to 63);
fli_in : in STD_LOGIC_VECTOR (0 to 63);
k : in STD_LOGIC_VECTOR (0 to 511);
k_len : in STD_LOGIC_VECTOR (0 to 1);
dec : in STD_LOGIC;
fl_out : out STD_LOGIC_VECTOR (0 to 63);
fli_out : out STD_LOGIC_VECTOR (0 to 63)
);
end component;
 
 
-- input registers
signal reg_m : STD_LOGIC_VECTOR (0 to 127);
signal reg_kl : STD_LOGIC_VECTOR (0 to 127);
signal reg_kr_int : STD_LOGIC_VECTOR (0 to 127);
signal reg_k_len : STD_LOGIC_VECTOR (0 to 1);
signal reg_dec : STD_LOGIC;
signal reg_rdy : STD_LOGIC;
 
-- used by pre-whitening
signal kw1_enc : STD_LOGIC_VECTOR (0 to 63);
signal kw2_enc : STD_LOGIC_VECTOR (0 to 63);
signal ka_s111_dec128 : STD_LOGIC_VECTOR (0 to 127);
signal kw1_dec128 : STD_LOGIC_VECTOR (0 to 63);
signal kw2_dec128 : STD_LOGIC_VECTOR (0 to 63);
signal ka_s111_dec256 : STD_LOGIC_VECTOR (0 to 127);
signal kw1_dec256 : STD_LOGIC_VECTOR (0 to 63);
signal kw2_dec256 : STD_LOGIC_VECTOR (0 to 63);
signal kw1 : STD_LOGIC_VECTOR (0 to 63);
signal kw2 : STD_LOGIC_VECTOR (0 to 63);
signal w1 : STD_LOGIC_VECTOR (0 to 63);
signal w2 : STD_LOGIC_VECTOR (0 to 63);
 
-- used by post-whitening
signal ka_s111_enc128 : STD_LOGIC_VECTOR (0 to 127);
signal kw3_enc128 : STD_LOGIC_VECTOR (0 to 63);
signal kw4_enc128 : STD_LOGIC_VECTOR (0 to 63);
signal ka_s111_enc256 : STD_LOGIC_VECTOR (0 to 127);
signal kw3_enc256 : STD_LOGIC_VECTOR (0 to 63);
signal kw4_enc256 : STD_LOGIC_VECTOR (0 to 63);
signal kw3_dec : STD_LOGIC_VECTOR (0 to 63);
signal kw4_dec : STD_LOGIC_VECTOR (0 to 63);
signal kw3 : STD_LOGIC_VECTOR (0 to 63);
signal kw4 : STD_LOGIC_VECTOR (0 to 63);
signal w3 : STD_LOGIC_VECTOR (0 to 63);
signal w4 : STD_LOGIC_VECTOR (0 to 63);
 
-- registers used during key schedule
signal reg_a1_m : STD_LOGIC_VECTOR (0 to 127);
signal reg_a1_dec : STD_LOGIC;
signal reg_a1_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_a1_rdy : STD_LOGIC;
signal reg_a2_m : STD_LOGIC_VECTOR (0 to 127);
signal reg_a2_dec : STD_LOGIC;
signal reg_a2_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_a2_rdy : STD_LOGIC;
signal reg_a3_m : STD_LOGIC_VECTOR (0 to 127);
signal reg_a3_dec : STD_LOGIC;
signal reg_a3_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_a3_rdy : STD_LOGIC;
signal reg_a4_m : STD_LOGIC_VECTOR (0 to 127);
signal reg_a4_dec : STD_LOGIC;
signal reg_a4_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_a4_rdy : STD_LOGIC;
signal reg_a5_m : STD_LOGIC_VECTOR (0 to 127);
signal reg_a5_dec : STD_LOGIC;
signal reg_a5_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_a5_rdy : STD_LOGIC;
signal reg_a6_m : STD_LOGIC_VECTOR (0 to 127);
signal reg_a6_dec : STD_LOGIC;
signal reg_a6_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_a6_rdy : STD_LOGIC;
 
-- registers used during 6-rounds and fls
signal reg_b1_dec : STD_LOGIC;
signal reg_b1_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b1_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b1_rdy : STD_LOGIC;
signal reg_b2_dec : STD_LOGIC;
signal reg_b2_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b2_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b2_rdy : STD_LOGIC;
signal reg_b3_dec : STD_LOGIC;
signal reg_b3_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b3_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b3_rdy : STD_LOGIC;
signal reg_b4_dec : STD_LOGIC;
signal reg_b4_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b4_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b4_rdy : STD_LOGIC;
signal reg_b5_dec : STD_LOGIC;
signal reg_b5_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b5_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b5_rdy : STD_LOGIC;
signal reg_b6_dec : STD_LOGIC;
signal reg_b6_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b6_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b6_rdy : STD_LOGIC;
signal reg_b7_dec : STD_LOGIC;
signal reg_b7_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b7_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b7_rdy : STD_LOGIC;
signal reg_b8_dec : STD_LOGIC;
signal reg_b8_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b8_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b8_rdy : STD_LOGIC;
signal reg_b9_dec : STD_LOGIC;
signal reg_b9_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b9_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b9_rdy : STD_LOGIC;
signal reg_b10_dec : STD_LOGIC;
signal reg_b10_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b10_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b10_rdy : STD_LOGIC;
signal reg_b11_dec : STD_LOGIC;
signal reg_b11_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b11_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b11_rdy : STD_LOGIC;
signal reg_b12_dec : STD_LOGIC;
signal reg_b12_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b12_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b12_rdy : STD_LOGIC;
signal reg_b13_dec : STD_LOGIC;
signal reg_b13_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b13_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b13_rdy : STD_LOGIC;
signal reg_b14_dec : STD_LOGIC;
signal reg_b14_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b14_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b14_rdy : STD_LOGIC;
signal reg_b15_dec : STD_LOGIC;
signal reg_b15_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b15_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b15_rdy : STD_LOGIC;
signal reg_b16_dec : STD_LOGIC;
signal reg_b16_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b16_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b16_rdy : STD_LOGIC;
signal reg_b17_dec : STD_LOGIC;
signal reg_b17_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b17_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b17_rdy : STD_LOGIC;
signal reg_b18_dec : STD_LOGIC;
signal reg_b18_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b18_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b18_rdy : STD_LOGIC;
signal reg_b19_dec : STD_LOGIC;
signal reg_b19_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b19_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b19_rdy : STD_LOGIC;
signal reg_b20_dec : STD_LOGIC;
signal reg_b20_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b20_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b20_rdy : STD_LOGIC;
signal reg_b21_dec : STD_LOGIC;
signal reg_b21_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b21_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b21_rdy : STD_LOGIC;
signal reg_b22_dec : STD_LOGIC;
signal reg_b22_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b22_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b22_rdy : STD_LOGIC;
signal reg_b23_dec : STD_LOGIC;
signal reg_b23_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b23_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b23_rdy : STD_LOGIC;
signal reg_b24_dec : STD_LOGIC;
signal reg_b24_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b24_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b24_rdy : STD_LOGIC;
signal reg_b25_dec : STD_LOGIC;
signal reg_b25_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b25_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b25_rdy : STD_LOGIC;
signal reg_b26_dec : STD_LOGIC;
signal reg_b26_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b26_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b26_rdy : STD_LOGIC;
signal reg_b27_dec : STD_LOGIC;
signal reg_b27_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b27_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b27_rdy : STD_LOGIC;
 
-- registers used for 128bit key encryptions
signal reg_l128_1 : STD_LOGIC_VECTOR (0 to 63);
signal reg_r128_1 : STD_LOGIC_VECTOR (0 to 63);
signal reg_l128_2 : STD_LOGIC_VECTOR (0 to 63);
signal reg_r128_2 : STD_LOGIC_VECTOR (0 to 63);
signal reg_l128_3 : STD_LOGIC_VECTOR (0 to 63);
signal reg_r128_3 : STD_LOGIC_VECTOR (0 to 63);
signal reg_l128_4 : STD_LOGIC_VECTOR (0 to 63);
signal reg_r128_4 : STD_LOGIC_VECTOR (0 to 63);
signal reg_l128_5 : STD_LOGIC_VECTOR (0 to 63);
signal reg_r128_5 : STD_LOGIC_VECTOR (0 to 63);
signal reg_l128_6 : STD_LOGIC_VECTOR (0 to 63);
signal reg_r128_6 : STD_LOGIC_VECTOR (0 to 63);
signal reg_l128_7 : STD_LOGIC_VECTOR (0 to 63);
signal reg_r128_7 : STD_LOGIC_VECTOR (0 to 63);
 
-- components outputs
signal out_ksched : STD_LOGIC_VECTOR (0 to 511); -- key schedule
signal out_r1l : STD_LOGIC_VECTOR (0 to 63); -- first six-round
signal out_r1r : STD_LOGIC_VECTOR (0 to 63);
signal out_r2l : STD_LOGIC_VECTOR (0 to 63); -- second six-round
signal out_r2r : STD_LOGIC_VECTOR (0 to 63);
signal out_r3l : STD_LOGIC_VECTOR (0 to 63); -- third six-round
signal out_r3r : STD_LOGIC_VECTOR (0 to 63);
signal out_r4l : STD_LOGIC_VECTOR (0 to 63); -- fourth six-round
signal out_r4r : STD_LOGIC_VECTOR (0 to 63);
signal out_fl1l : STD_LOGIC_VECTOR (0 to 63); -- first fl
signal out_fl1r : STD_LOGIC_VECTOR (0 to 63);
signal out_fl2l : STD_LOGIC_VECTOR (0 to 63); -- second fl
signal out_fl2r : STD_LOGIC_VECTOR (0 to 63);
signal out_fl3l : STD_LOGIC_VECTOR (0 to 63); -- third fl
signal out_fl3r : STD_LOGIC_VECTOR (0 to 63);
 
-- misc signals
signal kr_int : STD_LOGIC_VECTOR (0 to 127);
 
-- constants
constant KL_OFFSET : INTEGER := 0;
constant KR_OFFSET : INTEGER := 128;
constant KA_OFFSET : INTEGER := 256;
constant KB_OFFSET : INTEGER := 384;
 
begin
 
KEY_SCHED: KEYSCHED256
PORT MAP (
reset => reset,
clk => clk,
kl_in => reg_kl,
kr_in => reg_kr_int,
kl_out => out_ksched(KL_OFFSET to KL_OFFSET+127),
kr_out => out_ksched(KR_OFFSET to KR_OFFSET+127),
ka_out => out_ksched(KA_OFFSET to KA_OFFSET+127),
kb_out => out_ksched(KB_OFFSET to KB_OFFSET+127)
);
 
SIX1: SIXROUND256
GENERIC MAP(
k1e128_offset => KA_OFFSET,
k1e128_shift => 0,
k2e128_offset => KA_OFFSET,
k2e128_shift => 0,
k3e128_offset => KL_OFFSET,
k3e128_shift => 15,
k4e128_offset => KL_OFFSET,
k4e128_shift => 15,
k5e128_offset => KA_OFFSET,
k5e128_shift => 15,
k6e128_offset => KA_OFFSET,
k6e128_shift => 15,
k1d128_offset => KL_OFFSET,
k1d128_shift => 111,
k2d128_offset => KL_OFFSET,
k2d128_shift => 111,
k3d128_offset => KA_OFFSET,
k3d128_shift => 94,
k4d128_offset => KA_OFFSET,
k4d128_shift => 94,
k5d128_offset => KL_OFFSET,
k5d128_shift => 94,
k6d128_offset => KL_OFFSET,
k6d128_shift => 94,
k1e256_offset => KB_OFFSET,
k1e256_shift => 0,
k2e256_offset => KB_OFFSET,
k2e256_shift => 0,
k3e256_offset => KR_OFFSET,
k3e256_shift => 15,
k4e256_offset => KR_OFFSET,
k4e256_shift => 15,
k5e256_offset => KA_OFFSET,
k5e256_shift => 15,
k6e256_offset => KA_OFFSET,
k6e256_shift => 15,
k1d256_offset => KL_OFFSET,
k1d256_shift => 111,
k2d256_offset => KL_OFFSET,
k2d256_shift => 111,
k3d256_offset => KA_OFFSET,
k3d256_shift => 94,
k4d256_offset => KA_OFFSET,
k4d256_shift => 94,
k5d256_offset => KR_OFFSET,
k5d256_shift => 94,
k6d256_offset => KR_OFFSET,
k6d256_shift => 94
)
PORT MAP(
reset => reset,
clk => clk,
dec1 => reg_a6_dec,
k_len1 => reg_a6_klen,
k1 => out_ksched,
dec2 => reg_b1_dec,
k_len2 => reg_b1_klen,
k2 => reg_b1_k,
dec3 => reg_b2_dec,
k_len3 => reg_b2_klen,
k3 => reg_b2_k,
dec4 => reg_b3_dec,
k_len4 => reg_b3_klen,
k4 => reg_b3_k,
dec5 => reg_b4_dec,
k_len5 => reg_b4_klen,
k5 => reg_b4_k,
dec6 => reg_b5_dec,
k_len6 => reg_b5_klen,
k6 => reg_b5_k,
l_in => w1,
r_in => w2,
l_out => out_r1l,
r_out => out_r1r
);
 
SIX2: SIXROUND256
GENERIC MAP(
k1e128_offset => KL_OFFSET,
k1e128_shift => 45,
k2e128_offset => KL_OFFSET,
k2e128_shift => 45,
k3e128_offset => KA_OFFSET,
k3e128_shift => 45,
k4e128_offset => KL_OFFSET,
k4e128_shift => 60,
k5e128_offset => KA_OFFSET,
k5e128_shift => 60,
k6e128_offset => KA_OFFSET,
k6e128_shift => 60,
k1d128_offset => KA_OFFSET,
k1d128_shift => 60,
k2d128_offset => KA_OFFSET,
k2d128_shift => 60,
k3d128_offset => KL_OFFSET,
k3d128_shift => 60,
k4d128_offset => KA_OFFSET,
k4d128_shift => 45,
k5d128_offset => KL_OFFSET,
k5d128_shift => 45,
k6d128_offset => KL_OFFSET,
k6d128_shift => 45,
k1e256_offset => KB_OFFSET,
k1e256_shift => 30,
k2e256_offset => KB_OFFSET,
k2e256_shift => 30,
k3e256_offset => KL_OFFSET,
k3e256_shift => 45,
k4e256_offset => KL_OFFSET,
k4e256_shift => 45,
k5e256_offset => KA_OFFSET,
k5e256_shift => 45,
k6e256_offset => KA_OFFSET,
k6e256_shift => 45,
k1d256_offset => KL_OFFSET,
k1d256_shift => 77,
k2d256_offset => KL_OFFSET,
k2d256_shift => 77,
k3d256_offset => KB_OFFSET,
k3d256_shift => 60,
k4d256_offset => KB_OFFSET,
k4d256_shift => 60,
k5d256_offset => KR_OFFSET,
k5d256_shift => 60,
k6d256_offset => KR_OFFSET,
k6d256_shift => 60
)
PORT MAP(
reset => reset,
clk => clk,
dec1 => reg_b7_dec,
k_len1 => reg_b7_klen,
k1 => reg_b7_k,
dec2 => reg_b8_dec,
k_len2 => reg_b8_klen,
k2 => reg_b8_k,
dec3 => reg_b9_dec,
k_len3 => reg_b9_klen,
k3 => reg_b9_k,
dec4 => reg_b10_dec,
k_len4 => reg_b10_klen,
k4 => reg_b10_k,
dec5 => reg_b11_dec,
k_len5 => reg_b11_klen,
k5 => reg_b11_k,
dec6 => reg_b12_dec,
k_len6 => reg_b12_klen,
k6 => reg_b12_k,
l_in => out_fl1l,
r_in => out_fl1r,
l_out => out_r2l,
r_out => out_r2r
);
 
SIX3: SIXROUND256
GENERIC MAP(
k1e128_offset => KL_OFFSET,
k1e128_shift => 94,
k2e128_offset => KL_OFFSET,
k2e128_shift => 94,
k3e128_offset => KA_OFFSET,
k3e128_shift => 94,
k4e128_offset => KA_OFFSET,
k4e128_shift => 94,
k5e128_offset => KL_OFFSET,
k5e128_shift => 111,
k6e128_offset => KL_OFFSET,
k6e128_shift => 111,
k1d128_offset => KA_OFFSET,
k1d128_shift => 15,
k2d128_offset => KA_OFFSET,
k2d128_shift => 15,
k3d128_offset => KL_OFFSET,
k3d128_shift => 15,
k4d128_offset => KL_OFFSET,
k4d128_shift => 15,
k5d128_offset => KA_OFFSET,
k5d128_shift => 0,
k6d128_offset => KA_OFFSET,
k6d128_shift => 0,
k1e256_offset => KR_OFFSET,
k1e256_shift => 60,
k2e256_offset => KR_OFFSET,
k2e256_shift => 60,
k3e256_offset => KB_OFFSET,
k3e256_shift => 60,
k4e256_offset => KB_OFFSET,
k4e256_shift => 60,
k5e256_offset => KL_OFFSET,
k5e256_shift => 77,
k6e256_offset => KL_OFFSET,
k6e256_shift => 77,
k1d256_offset => KA_OFFSET,
k1d256_shift => 45,
k2d256_offset => KA_OFFSET,
k2d256_shift => 45,
k3d256_offset => KL_OFFSET,
k3d256_shift => 45,
k4d256_offset => KL_OFFSET,
k4d256_shift => 45,
k5d256_offset => KB_OFFSET,
k5d256_shift => 30,
k6d256_offset => KB_OFFSET,
k6d256_shift => 30
)
PORT MAP(
reset => reset,
clk => clk,
dec1 => reg_b14_dec,
k_len1 => reg_b14_klen,
k1 => reg_b14_k,
dec2 => reg_b15_dec,
k_len2 => reg_b15_klen,
k2 => reg_b15_k,
dec3 => reg_b16_dec,
k_len3 => reg_b16_klen,
k3 => reg_b16_k,
dec4 => reg_b17_dec,
k_len4 => reg_b17_klen,
k4 => reg_b17_k,
dec5 => reg_b18_dec,
k_len5 => reg_b18_klen,
k5 => reg_b18_k,
dec6 => reg_b19_dec,
k_len6 => reg_b19_klen,
k6 => reg_b19_k,
l_in => out_fl2l,
r_in => out_fl2r,
l_out => out_r3l,
r_out => out_r3r
);
 
SIX4: SIXROUND256
GENERIC MAP(
k1e128_offset => 0,
k1e128_shift => 0,
k2e128_offset => 0,
k2e128_shift => 0,
k3e128_offset => 0,
k3e128_shift => 0,
k4e128_offset => 0,
k4e128_shift => 0,
k5e128_offset => 0,
k5e128_shift => 0,
k6e128_offset => 0,
k6e128_shift => 0,
k1d128_offset => 0,
k1d128_shift => 0,
k2d128_offset => 0,
k2d128_shift => 0,
k3d128_offset => 0,
k3d128_shift => 0,
k4d128_offset => 0,
k4d128_shift => 0,
k5d128_offset => 0,
k5d128_shift => 0,
k6d128_offset => 0,
k6d128_shift => 0,
k1e256_offset => KR_OFFSET,
k1e256_shift => 94,
k2e256_offset => KR_OFFSET,
k2e256_shift => 94,
k3e256_offset => KA_OFFSET,
k3e256_shift => 94,
k4e256_offset => KA_OFFSET,
k4e256_shift => 94,
k5e256_offset => KL_OFFSET,
k5e256_shift => 111,
k6e256_offset => KL_OFFSET,
k6e256_shift => 111,
k1d256_offset => KA_OFFSET,
k1d256_shift => 15,
k2d256_offset => KA_OFFSET,
k2d256_shift => 15,
k3d256_offset => KR_OFFSET,
k3d256_shift => 15,
k4d256_offset => KR_OFFSET,
k4d256_shift => 15,
k5d256_offset => KB_OFFSET,
k5d256_shift => 0,
k6d256_offset => KB_OFFSET,
k6d256_shift => 0
)
PORT MAP(
reset => reset,
clk => clk,
dec1 => reg_b21_dec,
k_len1 => reg_b21_klen,
k1 => reg_b21_k,
dec2 => reg_b22_dec,
k_len2 => reg_b22_klen,
k2 => reg_b22_k,
dec3 => reg_b23_dec,
k_len3 => reg_b23_klen,
k3 => reg_b23_k,
dec4 => reg_b24_dec,
k_len4 => reg_b24_klen,
k4 => reg_b24_k,
dec5 => reg_b25_dec,
k_len5 => reg_b25_klen,
k5 => reg_b25_k,
dec6 => reg_b26_dec,
k_len6 => reg_b26_klen,
k6 => reg_b26_k,
l_in => out_fl3l,
r_in => out_fl3r,
l_out => out_r4l,
r_out => out_r4r
);
 
FL1: FL256
GENERIC MAP (
fl_ke128_offset => KA_OFFSET,
fl_ke128_shift => 30,
fli_ke128_offset => KA_OFFSET,
fli_ke128_shift => 30,
fl_kd128_offset => KL_OFFSET,
fl_kd128_shift => 77,
fli_kd128_offset => KL_OFFSET,
fli_kd128_shift => 77,
fl_ke256_offset => KR_OFFSET,
fl_ke256_shift => 30,
fli_ke256_offset => KR_OFFSET,
fli_ke256_shift => 30,
fl_kd256_offset => KA_OFFSET,
fl_kd256_shift => 77,
fli_kd256_offset => KA_OFFSET,
fli_kd256_shift => 77
)
PORT MAP (
reset => reset,
clk => clk,
fl_in => out_r1l,
fli_in => out_r1r,
k => reg_b7_k,
k_len => reg_b7_klen,
dec => reg_b7_dec,
fl_out => out_fl1l,
fli_out => out_fl1r
);
 
FL2: FL256
GENERIC MAP (
fl_ke128_offset => KL_OFFSET,
fl_ke128_shift => 77,
fli_ke128_offset => KL_OFFSET,
fli_ke128_shift => 77,
fl_kd128_offset => KA_OFFSET,
fl_kd128_shift => 30,
fli_kd128_offset => KA_OFFSET,
fli_kd128_shift => 30,
fl_ke256_offset => KL_OFFSET,
fl_ke256_shift => 60,
fli_ke256_offset => KL_OFFSET,
fli_ke256_shift => 60,
fl_kd256_offset => KL_OFFSET,
fl_kd256_shift => 60,
fli_kd256_offset => KL_OFFSET,
fli_kd256_shift => 60
)
PORT MAP (
reset => reset,
clk => clk,
fl_in => out_r2l,
fli_in => out_r2r,
k => reg_b14_k,
k_len => reg_b14_klen,
dec => reg_b14_dec,
fl_out => out_fl2l,
fli_out => out_fl2r
);
 
FL3: FL256
GENERIC MAP (
fl_ke128_offset => 0,
fl_ke128_shift => 0,
fli_ke128_offset => 0,
fli_ke128_shift => 0,
fl_kd128_offset => 0,
fl_kd128_shift => 0,
fli_kd128_offset => 0,
fli_kd128_shift => 0,
fl_ke256_offset => KA_OFFSET,
fl_ke256_shift => 77,
fli_ke256_offset => KA_OFFSET,
fli_ke256_shift => 77,
fl_kd256_offset => KR_OFFSET,
fl_kd256_shift => 30,
fli_kd256_offset => KR_OFFSET,
fli_kd256_shift => 30
)
PORT MAP (
reset => reset,
clk => clk,
fl_in => out_r3l,
fli_in => out_r3r,
k => reg_b21_k,
k_len => reg_b21_klen,
dec => reg_b21_dec,
fl_out => out_fl3l,
fli_out => out_fl3r
);
 
 
process(reset, clk)
begin
if(reset = '1') then
reg_m <= (others=>'0');
reg_kl <= (others=>'0');
reg_kr_int <= (others=>'0');
reg_k_len <= (others=>'0');
 
reg_dec <= '0';
reg_rdy <= '0';
reg_a1_rdy <= '0';
reg_a2_rdy <= '0';
reg_a3_rdy <= '0';
reg_a4_rdy <= '0';
reg_a5_rdy <= '0';
reg_a6_rdy <= '0';
reg_b1_rdy <= '0';
reg_b2_rdy <= '0';
reg_b3_rdy <= '0';
reg_b4_rdy <= '0';
reg_b5_rdy <= '0';
reg_b6_rdy <= '0';
reg_b7_rdy <= '0';
reg_b8_rdy <= '0';
reg_b9_rdy <= '0';
reg_b10_rdy <= '0';
reg_b11_rdy <= '0';
reg_b12_rdy <= '0';
reg_b13_rdy <= '0';
reg_b14_rdy <= '0';
reg_b15_rdy <= '0';
reg_b16_rdy <= '0';
reg_b17_rdy <= '0';
reg_b18_rdy <= '0';
reg_b19_rdy <= '0';
reg_b20_rdy <= '0';
reg_b21_rdy <= '0';
reg_b22_rdy <= '0';
reg_b23_rdy <= '0';
reg_b24_rdy <= '0';
reg_b25_rdy <= '0';
reg_b26_rdy <= '0';
reg_b27_rdy <= '0';
output_rdy <= '0';
elsif(rising_edge(clk)) then
reg_m <= input;
reg_kl <= key(0 to 127);
reg_kr_int <= kr_int;
reg_dec <= enc_dec;
reg_k_len <= key_len;
reg_rdy <= input_en;
 
reg_a1_m <= reg_m;
reg_a1_dec <= reg_dec;
reg_a1_klen <= reg_k_len;
reg_a1_rdy <= reg_rdy;
reg_a2_m <= reg_a1_m;
reg_a2_dec <= reg_a1_dec;
reg_a2_klen <= reg_a1_klen;
reg_a2_rdy <= reg_a1_rdy;
reg_a3_m <= reg_a2_m;
reg_a3_dec <= reg_a2_dec;
reg_a3_klen <= reg_a2_klen;
reg_a3_rdy <= reg_a2_rdy;
reg_a4_m <= reg_a3_m;
reg_a4_dec <= reg_a3_dec;
reg_a4_klen <= reg_a3_klen;
reg_a4_rdy <= reg_a3_rdy;
reg_a5_m <= reg_a4_m;
reg_a5_dec <= reg_a4_dec;
reg_a5_klen <= reg_a4_klen;
reg_a5_rdy <= reg_a4_rdy;
reg_a6_m <= reg_a5_m;
reg_a6_dec <= reg_a5_dec;
reg_a6_klen <= reg_a5_klen;
reg_a6_rdy <= reg_a5_rdy;
 
reg_b1_dec <= reg_a6_dec;
reg_b1_k <= out_ksched;
reg_b1_klen <= reg_a6_klen;
reg_b1_rdy <= reg_a6_rdy;
reg_b2_dec <= reg_b1_dec;
reg_b2_k <= reg_b1_k;
reg_b2_klen <= reg_b1_klen;
reg_b2_rdy <= reg_b1_rdy;
reg_b3_dec <= reg_b2_dec;
reg_b3_k <= reg_b2_k;
reg_b3_klen <= reg_b2_klen;
reg_b3_rdy <= reg_b2_rdy;
reg_b4_dec <= reg_b3_dec;
reg_b4_k <= reg_b3_k;
reg_b4_klen <= reg_b3_klen;
reg_b4_rdy <= reg_b3_rdy;
reg_b5_dec <= reg_b4_dec;
reg_b5_k <= reg_b4_k;
reg_b5_klen <= reg_b4_klen;
reg_b5_rdy <= reg_b4_rdy;
reg_b6_dec <= reg_b5_dec;
reg_b6_k <= reg_b5_k;
reg_b6_klen <= reg_b5_klen;
reg_b6_rdy <= reg_b5_rdy;
reg_b7_dec <= reg_b6_dec;
reg_b7_k <= reg_b6_k;
reg_b7_klen <= reg_b6_klen;
reg_b7_rdy <= reg_b6_rdy;
reg_b8_dec <= reg_b7_dec;
reg_b8_k <= reg_b7_k;
reg_b8_klen <= reg_b7_klen;
reg_b8_rdy <= reg_b7_rdy;
reg_b9_dec <= reg_b8_dec;
reg_b9_k <= reg_b8_k;
reg_b9_klen <= reg_b8_klen;
reg_b9_rdy <= reg_b8_rdy;
reg_b10_dec <= reg_b9_dec;
reg_b10_k <= reg_b9_k;
reg_b10_klen <= reg_b9_klen;
reg_b10_rdy <= reg_b9_rdy;
reg_b11_dec <= reg_b10_dec;
reg_b11_k <= reg_b10_k;
reg_b11_klen <= reg_b10_klen;
reg_b11_rdy <= reg_b10_rdy;
reg_b12_dec <= reg_b11_dec;
reg_b12_k <= reg_b11_k;
reg_b12_klen <= reg_b11_klen;
reg_b12_rdy <= reg_b11_rdy;
reg_b13_dec <= reg_b12_dec;
reg_b13_k <= reg_b12_k;
reg_b13_klen <= reg_b12_klen;
reg_b13_rdy <= reg_b12_rdy;
reg_b14_dec <= reg_b13_dec;
reg_b14_k <= reg_b13_k;
reg_b14_klen <= reg_b13_klen;
reg_b14_rdy <= reg_b13_rdy;
reg_b15_dec <= reg_b14_dec;
reg_b15_k <= reg_b14_k;
reg_b15_klen <= reg_b14_klen;
reg_b15_rdy <= reg_b14_rdy;
reg_b16_dec <= reg_b15_dec;
reg_b16_k <= reg_b15_k;
reg_b16_klen <= reg_b15_klen;
reg_b16_rdy <= reg_b15_rdy;
reg_b17_dec <= reg_b16_dec;
reg_b17_k <= reg_b16_k;
reg_b17_klen <= reg_b16_klen;
reg_b17_rdy <= reg_b16_rdy;
reg_b18_dec <= reg_b17_dec;
reg_b18_k <= reg_b17_k;
reg_b18_klen <= reg_b17_klen;
reg_b18_rdy <= reg_b17_rdy;
reg_b19_dec <= reg_b18_dec;
reg_b19_k <= reg_b18_k;
reg_b19_klen <= reg_b18_klen;
reg_b19_rdy <= reg_b18_rdy;
reg_b20_dec <= reg_b19_dec;
reg_b20_k <= reg_b19_k;
reg_b20_klen <= reg_b19_klen;
reg_b20_rdy <= reg_b19_rdy;
reg_b21_dec <= reg_b20_dec;
reg_b21_k <= reg_b20_k;
reg_b21_klen <= reg_b20_klen;
reg_b21_rdy <= reg_b20_rdy;
reg_b22_dec <= reg_b21_dec;
reg_b22_k <= reg_b21_k;
reg_b22_klen <= reg_b21_klen;
reg_b22_rdy <= reg_b21_rdy;
reg_b23_dec <= reg_b22_dec;
reg_b23_k <= reg_b22_k;
reg_b23_klen <= reg_b22_klen;
reg_b23_rdy <= reg_b22_rdy;
reg_b24_dec <= reg_b23_dec;
reg_b24_k <= reg_b23_k;
reg_b24_klen <= reg_b23_klen;
reg_b24_rdy <= reg_b23_rdy;
reg_b25_dec <= reg_b24_dec;
reg_b25_k <= reg_b24_k;
reg_b25_klen <= reg_b24_klen;
reg_b25_rdy <= reg_b24_rdy;
reg_b26_dec <= reg_b25_dec;
reg_b26_k <= reg_b25_k;
reg_b26_klen <= reg_b25_klen;
reg_b26_rdy <= reg_b25_rdy;
reg_b27_dec <= reg_b26_dec;
reg_b27_k <= reg_b26_k;
reg_b27_klen <= reg_b26_klen;
reg_b27_rdy <= reg_b26_rdy;
 
reg_l128_1 <= out_r3l;
reg_r128_1 <= out_r3r;
reg_l128_2 <= reg_l128_1;
reg_r128_2 <= reg_r128_1;
reg_l128_3 <= reg_l128_2;
reg_r128_3 <= reg_r128_2;
reg_l128_4 <= reg_l128_3;
reg_r128_4 <= reg_r128_3;
reg_l128_5 <= reg_l128_4;
reg_r128_5 <= reg_r128_4;
reg_l128_6 <= reg_l128_5;
reg_r128_6 <= reg_r128_5;
reg_l128_7 <= reg_l128_6;
reg_r128_7 <= reg_r128_6;
 
-- output
output <= w3 & w4;
output_rdy <= reg_b27_rdy;
 
end if;
end process;
 
--kr depends on key lenght
kr_int <= (others=>'0') when key_len(0)='0' else
key(128 to 191) & not key(128 to 191) when key_len="10" else
key(128 to 255);
 
-- pre-whitening
kw1_enc <= out_ksched(KL_OFFSET to KL_OFFSET+63);
kw2_enc <= out_ksched(KL_OFFSET+64 to KL_OFFSET+127);
 
ka_s111_dec128 <= out_ksched(KA_OFFSET+111 to KA_OFFSET+127) &
out_ksched(KA_OFFSET to KA_OFFSET+110);
kw1_dec128 <= ka_s111_dec128(0 to 63);
kw2_dec128 <= ka_s111_dec128(64 to 127);
 
ka_s111_dec256 <= out_ksched(KB_OFFSET+111 to KB_OFFSET+127) &
out_ksched(KB_OFFSET to KB_OFFSET+110);
kw1_dec256 <= ka_s111_dec256(0 to 63);
kw2_dec256 <= ka_s111_dec256(64 to 127);
 
kw1 <= kw1_dec128 when reg_a6_dec='1' and reg_a6_klen(0)='0' else
kw1_dec256 when reg_a6_dec='1' and reg_a6_klen(0)='1' else
kw1_enc;
kw2 <= kw2_dec128 when reg_a6_dec='1' and reg_a6_klen(0)='0' else
kw2_dec256 when reg_a6_dec='1' and reg_a6_klen(0)='1' else
kw2_enc;
 
w1 <= reg_a6_m(0 to 63) xor kw1;
w2 <= reg_a6_m(64 to 127) xor kw2;
 
-- post-whitening
ka_s111_enc128 <= reg_b27_k(KA_OFFSET+111 to KA_OFFSET+127) &
reg_b27_k(KA_OFFSET to KA_OFFSET+110);
kw3_enc128 <= ka_s111_enc128(0 to 63);
kw4_enc128 <= ka_s111_enc128(64 to 127);
 
ka_s111_enc256 <= reg_b27_k(KB_OFFSET+111 to KB_OFFSET+127) &
reg_b27_k(KB_OFFSET to KB_OFFSET+110);
kw3_enc256 <= ka_s111_enc256(0 to 63);
kw4_enc256 <= ka_s111_enc256(64 to 127);
 
kw3_dec <= reg_b27_k(KL_OFFSET to KL_OFFSET+63);
kw4_dec <= reg_b27_k(KL_OFFSET+64 to KL_OFFSET+127);
 
kw3 <= kw3_enc128 when reg_b27_dec='0' and reg_b27_klen(0)='0' else
kw3_enc256 when reg_b27_dec='0' and reg_b27_klen(0)='1' else
kw3_dec;
kw4 <= kw4_enc128 when reg_b27_dec='0' and reg_b27_klen(0)='0' else
kw4_enc256 when reg_b27_dec='0' and reg_b27_klen(0)='1' else
kw4_dec;
 
 
w3 <= reg_r128_7 xor kw3 when reg_b27_klen(0)='0' else
out_r4r xor kw3;
w4 <= reg_l128_7 xor kw4 when reg_b27_klen(0)='0' else
out_r4l xor kw4;
 
end RTL;
/camellia-vhdl/trunk/pipelining/camellia256_tb.do
0,0 → 1,31
vcom -quiet sbox1.vhd
vcom -quiet sbox2.vhd
vcom -quiet sbox3.vhd
vcom -quiet sbox4.vhd
vcom -quiet f.vhd
vcom -quiet fl256.vhd
vcom -quiet 6round256.vhd
vcom -quiet keysched256.vhd
vcom -quiet camellia256.vhd
vcom -quiet camellia256_tb.vhd
vsim camellia256_tb
view wave
add wave -divider "camellia256"
add wave -HEX -ports /uut/*
add wave -divider "key"
add wave -HEX -ports /uut/key_sched/*
add wave -divider "six1"
add wave -HEX -ports /uut/six1/*
add wave -divider "fl1"
add wave -HEX -ports /uut/fl1/*
add wave -divider "six2"
add wave -HEX -ports /uut/six2/*
add wave -divider "fl2"
add wave -HEX -ports /uut/fl2/*
add wave -divider "six3"
add wave -HEX -ports /uut/six3/*
add wave -divider "fl3"
add wave -HEX -ports /uut/fl3/*
add wave -divider "six4"
add wave -HEX -ports /uut/six4/*
run 250 ns
/camellia-vhdl/trunk/pipelining/camellia256_tb.vhd
0,0 → 1,140
 
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 09/14/2007
-- Last Update: 06/23/2008
-- Project Name: camellia-vhdl
-- Description: VHDL Test Bench for module CAMELLIA256
--
-- Copyright (C) 2007 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
 
entity camellia256_tb is
end camellia256_tb;
 
ARCHITECTURE behavior of camellia256_tb is
 
-- Component Declaration for the Unit Under Test (UUT)
component CAMELLIA256 is
port(
reset : in STD_LOGIC;
clk : in STD_LOGIC;
input : in STD_LOGIC_VECTOR (0 to 127);
input_en : in STD_LOGIC;
key : in STD_LOGIC_VECTOR (0 to 255);
key_len : in STD_LOGIC_VECTOR (0 to 1);
enc_dec : in STD_LOGIC;
output : out STD_LOGIC_VECTOR (0 to 127);
output_rdy : out STD_LOGIC
);
end component;
 
--Inputs
signal reset : STD_LOGIC;
signal clk : STD_LOGIC;
signal input : STD_LOGIC_VECTOR(0 to 127) := (others=>'0');
signal input_en : STD_LOGIC := '0';
signal key : STD_LOGIC_VECTOR(0 to 255) := (others=>'0');
signal key_len : STD_LOGIC_VECTOR(0 to 1) := "00";
signal enc_dec : STD_LOGIC;
 
--Output
signal output : STD_LOGIC_VECTOR(0 to 127);
signal output_rdy : STD_LOGIC;
 
-- Time constants
constant ClockPeriod : TIME := 5 ns;
 
 
 
begin
 
-- Instantiate the Unit Under Test (UUT)
uut: CAMELLIA256
port map(
reset => reset,
clk => clk,
input => input,
input_en => input_en,
key => key,
key_len => key_len,
enc_dec => enc_dec,
output => output,
output_rdy => output_rdy
);
 
ck : process
begin
clk <= '0';
wait for ClockPeriod / 2;
clk <= '1';
wait for ClockPeriod / 2;
end process;
 
process
begin
reset <= '1';
wait for ClockPeriod*2; --falling clock edge
reset <= '0';
wait until clk = '1';
input <= X"0123456789ABCDEFFEDCBA9876543210";
key <= X"0123456789ABCDEFFEDCBA9876543210" &
X"00112233445566778899AABBCCDDEEFF";
key_len <= "00";
enc_dec <= '0';
input_en <= '1';
wait until clk = '1';
input <= X"67673138549669730857065648EABE43";
key <= X"0123456789ABCDEFFEDCBA9876543210" &
X"00112233445566778899AABBCCDDEEFF";
key_len <= "00";
enc_dec <= '1';
wait until clk = '1';
input <= X"0123456789ABCDEFFEDCBA9876543210";
key <= X"0123456789ABCDEFFEDCBA9876543210" &
X"00112233445566778899AABBCCDDEEFF";
key_len <= "10";
enc_dec <= '0';
wait until clk = '1';
input <= X"B4993401B3E996F84EE5CEE7D79B09B9";
key <= X"0123456789ABCDEFFEDCBA9876543210" &
X"00112233445566778899AABBCCDDEEFF";
key_len <= "10";
enc_dec <= '1';
wait until clk = '1';
input <= X"0123456789ABCDEFFEDCBA9876543210";
key <= X"0123456789ABCDEFFEDCBA9876543210" &
X"00112233445566778899AABBCCDDEEFF";
key_len <= "11";
enc_dec <= '0';
wait until clk = '1';
input <= X"9ACC237DFF16D76C20EF7C919E3A7509";
key <= X"0123456789ABCDEFFEDCBA9876543210" &
X"00112233445566778899AABBCCDDEEFF";
key_len <= "11";
enc_dec <= '1';
wait until clk = '1';
input_en <= '0';
wait;
end process;
 
 
end;
/camellia-vhdl/trunk/pipelining/6round128.vhd
0,0 → 1,241
 
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 09/14/2007
-- Last Update: 04/09/2008
-- Project Name: camellia-vhdl
-- Description: Six rounds of F, only for 128-bit key en/decryption
--
-- Copyright (C) 2007 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
 
 
entity SIXROUND128 is
generic (
k1e_offset : INTEGER; -- encryption
k1e_shift : INTEGER;
k2e_offset : INTEGER;
k2e_shift : INTEGER;
k3e_offset : INTEGER;
k3e_shift : INTEGER;
k4e_offset : INTEGER;
k4e_shift : INTEGER;
k5e_offset : INTEGER;
k5e_shift : INTEGER;
k6e_offset : INTEGER;
k6e_shift : INTEGER;
k1d_offset : INTEGER; -- decryption
k1d_shift : INTEGER;
k2d_offset : INTEGER;
k2d_shift : INTEGER;
k3d_offset : INTEGER;
k3d_shift : INTEGER;
k4d_offset : INTEGER;
k4d_shift : INTEGER;
k5d_offset : INTEGER;
k5d_shift : INTEGER;
k6d_offset : INTEGER;
k6d_shift : INTEGER
);
port(
reset : in STD_LOGIC;
clk : in STD_LOGIC;
dec1 : in STD_LOGIC;
k1 : in STD_LOGIC_VECTOR (0 to 255);
dec2 : in STD_LOGIC;
k2 : in STD_LOGIC_VECTOR (0 to 255);
dec3 : in STD_LOGIC;
k3 : in STD_LOGIC_VECTOR (0 to 255);
dec4 : in STD_LOGIC;
k4 : in STD_LOGIC_VECTOR (0 to 255);
dec5 : in STD_LOGIC;
k5 : in STD_LOGIC_VECTOR (0 to 255);
dec6 : in STD_LOGIC;
k6 : in STD_LOGIC_VECTOR (0 to 255);
l_in : in STD_LOGIC_VECTOR (0 to 63);
r_in : in STD_LOGIC_VECTOR (0 to 63);
l_out : out STD_LOGIC_VECTOR (0 to 63);
r_out : out STD_LOGIC_VECTOR (0 to 63)
);
end SIXROUND128;
 
architecture RTL of SIXROUND128 is
 
component F is
port (
reset : in STD_LOGIC;
clk : in STD_LOGIC;
x : in STD_LOGIC_VECTOR (0 to 63);
k : in STD_LOGIC_VECTOR (0 to 63);
z : out STD_LOGIC_VECTOR (0 to 63)
);
end component;
 
-- subkeys
signal t_enc1 : STD_LOGIC_VECTOR (0 to 127);
signal t_enc2 : STD_LOGIC_VECTOR (0 to 127);
signal t_enc3 : STD_LOGIC_VECTOR (0 to 127);
signal t_enc4 : STD_LOGIC_VECTOR (0 to 127);
signal t_enc5 : STD_LOGIC_VECTOR (0 to 127);
signal t_enc6 : STD_LOGIC_VECTOR (0 to 127);
signal t_dec1 : STD_LOGIC_VECTOR (0 to 127);
signal t_dec2 : STD_LOGIC_VECTOR (0 to 127);
signal t_dec3 : STD_LOGIC_VECTOR (0 to 127);
signal t_dec4 : STD_LOGIC_VECTOR (0 to 127);
signal t_dec5 : STD_LOGIC_VECTOR (0 to 127);
signal t_dec6 : STD_LOGIC_VECTOR (0 to 127);
signal int_k1 : STD_LOGIC_VECTOR (0 to 63);
signal int_k2 : STD_LOGIC_VECTOR (0 to 63);
signal int_k3 : STD_LOGIC_VECTOR (0 to 63);
signal int_k4 : STD_LOGIC_VECTOR (0 to 63);
signal int_k5 : STD_LOGIC_VECTOR (0 to 63);
signal int_k6 : STD_LOGIC_VECTOR (0 to 63);
 
-- f inputs
signal f1_in : STD_LOGIC_VECTOR (0 to 63);
signal f2_in : STD_LOGIC_VECTOR (0 to 63);
signal f3_in : STD_LOGIC_VECTOR (0 to 63);
signal f4_in : STD_LOGIC_VECTOR (0 to 63);
signal f5_in : STD_LOGIC_VECTOR (0 to 63);
signal f6_in : STD_LOGIC_VECTOR (0 to 63);
 
-- f outputs
signal f1_out : STD_LOGIC_VECTOR (0 to 63);
signal f2_out : STD_LOGIC_VECTOR (0 to 63);
signal f3_out : STD_LOGIC_VECTOR (0 to 63);
signal f4_out : STD_LOGIC_VECTOR (0 to 63);
signal f5_out : STD_LOGIC_VECTOR (0 to 63);
signal f6_out : STD_LOGIC_VECTOR (0 to 63);
 
-- intermediate registers
signal reg1_l : STD_LOGIC_VECTOR (0 to 63);
signal reg1_r : STD_LOGIC_VECTOR (0 to 63);
signal reg2_l : STD_LOGIC_VECTOR (0 to 63);
signal reg2_r : STD_LOGIC_VECTOR (0 to 63);
signal reg3_l : STD_LOGIC_VECTOR (0 to 63);
signal reg3_r : STD_LOGIC_VECTOR (0 to 63);
signal reg4_l : STD_LOGIC_VECTOR (0 to 63);
signal reg4_r : STD_LOGIC_VECTOR (0 to 63);
signal reg5_l : STD_LOGIC_VECTOR (0 to 63);
signal reg5_r : STD_LOGIC_VECTOR (0 to 63);
signal reg6_l : STD_LOGIC_VECTOR (0 to 63);
signal reg6_r : STD_LOGIC_VECTOR (0 to 63);
 
begin
 
-- shift of kl, ka
t_enc1 <= k1(k1e_offset+k1e_shift to k1e_offset+127) &
k1(k1e_offset to k1e_offset+k1e_shift-1);
t_enc2 <= k2(k2e_offset+k2e_shift to k2e_offset+127) &
k2(k2e_offset to k2e_offset+k2e_shift-1);
t_enc3 <= k3(k3e_offset+k3e_shift to k3e_offset+127) &
k3(k3e_offset to k3e_offset+k3e_shift-1);
t_enc4 <= k4(k4e_offset+k4e_shift to k4e_offset+127) &
k4(k4e_offset to k4e_offset+k4e_shift-1);
t_enc5 <= k5(k5e_offset+k5e_shift to k5e_offset+127) &
k5(k5e_offset to k5e_offset+k5e_shift-1);
t_enc6 <= k6(k6e_offset+k6e_shift to k6e_offset+127) &
k6(k6e_offset to k6e_offset+k6e_shift-1);
 
t_dec1 <= k1(k1d_offset+k1d_shift to k1d_offset+127) &
k1(k1d_offset to k1d_offset+k1d_shift-1);
t_dec2 <= k2(k2d_offset+k2d_shift to k2d_offset+127) &
k2(k2d_offset to k2d_offset+k2d_shift-1);
t_dec3 <= k3(k3d_offset+k3d_shift to k3d_offset+127) &
k3(k3d_offset to k3d_offset+k3d_shift-1);
t_dec4 <= k4(k4d_offset+k4d_shift to k4d_offset+127) &
k4(k4d_offset to k4d_offset+k4d_shift-1);
t_dec5 <= k5(k5d_offset+k5d_shift to k5d_offset+127) &
k5(k5d_offset to k5d_offset+k5d_shift-1);
t_dec6 <= k6(k6d_offset+k6d_shift to k6d_offset+127) &
k6(k6d_offset to k6d_offset+k6d_shift-1);
 
-- subkeys generation
-- int_k1, int_k3, int_k5 get always the left/right slice when en/decrypting
-- int_k2, int_k4, int_k6 get always the right/left slice when en/decrypting
int_k1 <= t_enc1(0 to 63) when dec1='0' else t_dec1(64 to 127);
int_k2 <= t_enc2(64 to 127) when dec2='0' else t_dec2(0 to 63);
int_k3 <= t_enc3(0 to 63) when dec3='0' else t_dec3(64 to 127);
int_k4 <= t_enc4(64 to 127) when dec4='0' else t_dec4(0 to 63);
int_k5 <= t_enc5(0 to 63) when dec5='0' else t_dec5(64 to 127);
int_k6 <= t_enc6(64 to 127) when dec6='0' else t_dec6(0 to 63);
 
-- f inputs
f1_in <= l_in;
f2_in <= f1_out xor reg1_r;
f3_in <= f2_out xor reg2_r;
f4_in <= f3_out xor reg3_r;
f5_in <= f4_out xor reg4_r;
f6_in <= f5_out xor reg5_r;
 
F1 : F
port map(reset, clk, f1_in, int_k1, f1_out);
F2 : F
port map(reset, clk, f2_in, int_k2, f2_out);
F3 : F
port map(reset, clk, f3_in, int_k3, f3_out);
F4 : F
port map(reset, clk, f4_in, int_k4, f4_out);
F5 : F
port map(reset, clk, f5_in, int_k5, f5_out);
F6 : F
port map(reset, clk, f6_in, int_k6, f6_out);
 
 
REG : process(reset, clk)
begin
 
if (reset = '1') then
reg1_l <= (others=>'0');
reg1_r <= (others=>'0');
reg2_l <= (others=>'0');
reg2_r <= (others=>'0');
reg3_l <= (others=>'0');
reg3_r <= (others=>'0');
reg4_l <= (others=>'0');
reg4_r <= (others=>'0');
reg5_l <= (others=>'0');
reg5_r <= (others=>'0');
reg6_l <= (others=>'0');
reg6_r <= (others=>'0');
else
if (rising_edge(clk)) then -- rising clock edge
reg1_l <= f1_in;
reg1_r <= r_in;
reg2_l <= f2_in;
reg2_r <= reg1_l;
reg3_l <= f3_in;
reg3_r <= reg2_l;
reg4_l <= f4_in;
reg4_r <= reg3_l;
reg5_l <= f5_in;
reg5_r <= reg4_l;
reg6_l <= f6_in;
reg6_r <= reg5_l;
end if;
end if;
end process;
 
-- there isn't an output register
l_out <= f6_out xor reg6_r;
r_out <= reg6_l;
 
end RTL;
/camellia-vhdl/trunk/pipelining/camellia128_tb.do
0,0 → 1,27
vcom -quiet sbox1.vhd
vcom -quiet sbox2.vhd
vcom -quiet sbox3.vhd
vcom -quiet sbox4.vhd
vcom -quiet f.vhd
vcom -quiet fl128.vhd
vcom -quiet 6round128.vhd
vcom -quiet keysched128.vhd
vcom -quiet camellia128.vhd
vcom -quiet camellia128_tb.vhd
vsim camellia128_tb
view wave
add wave -divider "camellia128"
add wave -HEX -ports /uut/*
add wave -divider "key"
add wave -HEX -ports /uut/key_sched/*
add wave -divider "six1"
add wave -HEX -ports /uut/six1/*
add wave -divider "fl1"
add wave -HEX -ports /uut/fl1/*
add wave -divider "six2"
add wave -HEX -ports /uut/six2/*
add wave -divider "fl2"
add wave -HEX -ports /uut/fl2/*
add wave -divider "six3"
add wave -HEX -ports /uut/six3/*
run 150 ns
/camellia-vhdl/trunk/pipelining/6round256.vhd
0,0 → 1,327
 
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 09/14/2007
-- Last Update: 04/09/2008
-- Project Name: camellia-vhdl
-- Description: Six rounds of F, for 128/192/256-bit key en/decryption
--
-- Copyright (C) 2007 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
 
 
entity SIXROUND256 is
generic (
k1e128_offset : INTEGER; -- encryption 128bit
k1e128_shift : INTEGER;
k2e128_offset : INTEGER;
k2e128_shift : INTEGER;
k3e128_offset : INTEGER;
k3e128_shift : INTEGER;
k4e128_offset : INTEGER;
k4e128_shift : INTEGER;
k5e128_offset : INTEGER;
k5e128_shift : INTEGER;
k6e128_offset : INTEGER;
k6e128_shift : INTEGER;
k1d128_offset : INTEGER; -- decryption 128bit
k1d128_shift : INTEGER;
k2d128_offset : INTEGER;
k2d128_shift : INTEGER;
k3d128_offset : INTEGER;
k3d128_shift : INTEGER;
k4d128_offset : INTEGER;
k4d128_shift : INTEGER;
k5d128_offset : INTEGER;
k5d128_shift : INTEGER;
k6d128_offset : INTEGER;
k6d128_shift : INTEGER;
k1e256_offset : INTEGER; -- encryption 192/256bit
k1e256_shift : INTEGER;
k2e256_offset : INTEGER;
k2e256_shift : INTEGER;
k3e256_offset : INTEGER;
k3e256_shift : INTEGER;
k4e256_offset : INTEGER;
k4e256_shift : INTEGER;
k5e256_offset : INTEGER;
k5e256_shift : INTEGER;
k6e256_offset : INTEGER;
k6e256_shift : INTEGER;
k1d256_offset : INTEGER; -- decryption 192/256bit
k1d256_shift : INTEGER;
k2d256_offset : INTEGER;
k2d256_shift : INTEGER;
k3d256_offset : INTEGER;
k3d256_shift : INTEGER;
k4d256_offset : INTEGER;
k4d256_shift : INTEGER;
k5d256_offset : INTEGER;
k5d256_shift : INTEGER;
k6d256_offset : INTEGER;
k6d256_shift : INTEGER
);
port(
reset : in STD_LOGIC;
clk : in STD_LOGIC;
dec1 : in STD_LOGIC;
k_len1 : in STD_LOGIC_VECTOR (0 to 1);
k1 : in STD_LOGIC_VECTOR (0 to 511);
dec2 : in STD_LOGIC;
k_len2 : in STD_LOGIC_VECTOR (0 to 1);
k2 : in STD_LOGIC_VECTOR (0 to 511);
dec3 : in STD_LOGIC;
k_len3 : in STD_LOGIC_VECTOR (0 to 1);
k3 : in STD_LOGIC_VECTOR (0 to 511);
dec4 : in STD_LOGIC;
k_len4 : in STD_LOGIC_VECTOR (0 to 1);
k4 : in STD_LOGIC_VECTOR (0 to 511);
dec5 : in STD_LOGIC;
k_len5 : in STD_LOGIC_VECTOR (0 to 1);
k5 : in STD_LOGIC_VECTOR (0 to 511);
dec6 : in STD_LOGIC;
k_len6 : in STD_LOGIC_VECTOR (0 to 1);
k6 : in STD_LOGIC_VECTOR (0 to 511);
l_in : in STD_LOGIC_VECTOR (0 to 63);
r_in : in STD_LOGIC_VECTOR (0 to 63);
l_out : out STD_LOGIC_VECTOR (0 to 63);
r_out : out STD_LOGIC_VECTOR (0 to 63)
);
end SIXROUND256;
 
architecture RTL of SIXROUND256 is
 
component F is
port (
reset : in STD_LOGIC;
clk : in STD_LOGIC;
x : in STD_LOGIC_VECTOR (0 to 63);
k : in STD_LOGIC_VECTOR (0 to 63);
z : out STD_LOGIC_VECTOR (0 to 63)
);
end component;
 
-- subkeys
signal t1_enc128 : STD_LOGIC_VECTOR (0 to 127);
signal t2_enc128 : STD_LOGIC_VECTOR (0 to 127);
signal t3_enc128 : STD_LOGIC_VECTOR (0 to 127);
signal t4_enc128 : STD_LOGIC_VECTOR (0 to 127);
signal t5_enc128 : STD_LOGIC_VECTOR (0 to 127);
signal t6_enc128 : STD_LOGIC_VECTOR (0 to 127);
signal t1_dec128 : STD_LOGIC_VECTOR (0 to 127);
signal t2_dec128 : STD_LOGIC_VECTOR (0 to 127);
signal t3_dec128 : STD_LOGIC_VECTOR (0 to 127);
signal t4_dec128 : STD_LOGIC_VECTOR (0 to 127);
signal t5_dec128 : STD_LOGIC_VECTOR (0 to 127);
signal t6_dec128 : STD_LOGIC_VECTOR (0 to 127);
signal t1_enc256 : STD_LOGIC_VECTOR (0 to 127);
signal t2_enc256 : STD_LOGIC_VECTOR (0 to 127);
signal t3_enc256 : STD_LOGIC_VECTOR (0 to 127);
signal t4_enc256 : STD_LOGIC_VECTOR (0 to 127);
signal t5_enc256 : STD_LOGIC_VECTOR (0 to 127);
signal t6_enc256 : STD_LOGIC_VECTOR (0 to 127);
signal t1_dec256 : STD_LOGIC_VECTOR (0 to 127);
signal t2_dec256 : STD_LOGIC_VECTOR (0 to 127);
signal t3_dec256 : STD_LOGIC_VECTOR (0 to 127);
signal t4_dec256 : STD_LOGIC_VECTOR (0 to 127);
signal t5_dec256 : STD_LOGIC_VECTOR (0 to 127);
signal t6_dec256 : STD_LOGIC_VECTOR (0 to 127);
signal int_k1 : STD_LOGIC_VECTOR (0 to 63);
signal int_k2 : STD_LOGIC_VECTOR (0 to 63);
signal int_k3 : STD_LOGIC_VECTOR (0 to 63);
signal int_k4 : STD_LOGIC_VECTOR (0 to 63);
signal int_k5 : STD_LOGIC_VECTOR (0 to 63);
signal int_k6 : STD_LOGIC_VECTOR (0 to 63);
 
-- f inputs
signal f1_in : STD_LOGIC_VECTOR (0 to 63);
signal f2_in : STD_LOGIC_VECTOR (0 to 63);
signal f3_in : STD_LOGIC_VECTOR (0 to 63);
signal f4_in : STD_LOGIC_VECTOR (0 to 63);
signal f5_in : STD_LOGIC_VECTOR (0 to 63);
signal f6_in : STD_LOGIC_VECTOR (0 to 63);
 
-- f outputs
signal f1_out : STD_LOGIC_VECTOR (0 to 63);
signal f2_out : STD_LOGIC_VECTOR (0 to 63);
signal f3_out : STD_LOGIC_VECTOR (0 to 63);
signal f4_out : STD_LOGIC_VECTOR (0 to 63);
signal f5_out : STD_LOGIC_VECTOR (0 to 63);
signal f6_out : STD_LOGIC_VECTOR (0 to 63);
 
-- intermediate registers
signal reg1_l : STD_LOGIC_VECTOR (0 to 63);
signal reg1_r : STD_LOGIC_VECTOR (0 to 63);
signal reg2_l : STD_LOGIC_VECTOR (0 to 63);
signal reg2_r : STD_LOGIC_VECTOR (0 to 63);
signal reg3_l : STD_LOGIC_VECTOR (0 to 63);
signal reg3_r : STD_LOGIC_VECTOR (0 to 63);
signal reg4_l : STD_LOGIC_VECTOR (0 to 63);
signal reg4_r : STD_LOGIC_VECTOR (0 to 63);
signal reg5_l : STD_LOGIC_VECTOR (0 to 63);
signal reg5_r : STD_LOGIC_VECTOR (0 to 63);
signal reg6_l : STD_LOGIC_VECTOR (0 to 63);
signal reg6_r : STD_LOGIC_VECTOR (0 to 63);
 
begin
 
-- shift of kl, kr, ka, kb
t1_enc128 <= k1(k1e128_offset+k1e128_shift to k1e128_offset+127) &
k1(k1e128_offset to k1e128_offset+k1e128_shift-1);
t2_enc128 <= k2(k2e128_offset+k2e128_shift to k2e128_offset+127) &
k2(k2e128_offset to k2e128_offset+k2e128_shift-1);
t3_enc128 <= k3(k3e128_offset+k3e128_shift to k3e128_offset+127) &
k3(k3e128_offset to k3e128_offset+k3e128_shift-1);
t4_enc128 <= k4(k4e128_offset+k4e128_shift to k4e128_offset+127) &
k4(k4e128_offset to k4e128_offset+k4e128_shift-1);
t5_enc128 <= k5(k5e128_offset+k5e128_shift to k5e128_offset+127) &
k5(k5e128_offset to k5e128_offset+k5e128_shift-1);
t6_enc128 <= k6(k6e128_offset+k6e128_shift to k6e128_offset+127) &
k6(k6e128_offset to k6e128_offset+k6e128_shift-1);
 
t1_dec128 <= k1(k1d128_offset+k1d128_shift to k1d128_offset+127) &
k1(k1d128_offset to k1d128_offset+k1d128_shift-1);
t2_dec128 <= k2(k2d128_offset+k2d128_shift to k2d128_offset+127) &
k2(k2d128_offset to k2d128_offset+k2d128_shift-1);
t3_dec128 <= k3(k3d128_offset+k3d128_shift to k3d128_offset+127) &
k3(k3d128_offset to k3d128_offset+k3d128_shift-1);
t4_dec128 <= k4(k4d128_offset+k4d128_shift to k4d128_offset+127) &
k4(k4d128_offset to k4d128_offset+k4d128_shift-1);
t5_dec128 <= k5(k5d128_offset+k5d128_shift to k5d128_offset+127) &
k5(k5d128_offset to k5d128_offset+k5d128_shift-1);
t6_dec128 <= k6(k6d128_offset+k6d128_shift to k6d128_offset+127) &
k6(k6d128_offset to k6d128_offset+k6d128_shift-1);
 
t1_enc256 <= k1(k1e256_offset+k1e256_shift to k1e256_offset+127) &
k1(k1e256_offset to k1e256_offset+k1e256_shift-1);
t2_enc256 <= k2(k2e256_offset+k2e256_shift to k2e256_offset+127) &
k2(k2e256_offset to k2e256_offset+k2e256_shift-1);
t3_enc256 <= k3(k3e256_offset+k3e256_shift to k3e256_offset+127) &
k3(k3e256_offset to k3e256_offset+k3e256_shift-1);
t4_enc256 <= k4(k4e256_offset+k4e256_shift to k4e256_offset+127) &
k4(k4e256_offset to k4e256_offset+k4e256_shift-1);
t5_enc256 <= k5(k5e256_offset+k5e256_shift to k5e256_offset+127) &
k5(k5e256_offset to k5e256_offset+k5e256_shift-1);
t6_enc256 <= k6(k6e256_offset+k6e256_shift to k6e256_offset+127) &
k6(k6e256_offset to k6e256_offset+k6e256_shift-1);
 
t1_dec256 <= k1(k1d256_offset+k1d256_shift to k1d256_offset+127) &
k1(k1d256_offset to k1d256_offset+k1d256_shift-1);
t2_dec256 <= k2(k2d256_offset+k2d256_shift to k2d256_offset+127) &
k2(k2d256_offset to k2d256_offset+k2d256_shift-1);
t3_dec256 <= k3(k3d256_offset+k3d256_shift to k3d256_offset+127) &
k3(k3d256_offset to k3d256_offset+k3d256_shift-1);
t4_dec256 <= k4(k4d256_offset+k4d256_shift to k4d256_offset+127) &
k4(k4d256_offset to k4d256_offset+k4d256_shift-1);
t5_dec256 <= k5(k5d256_offset+k5d256_shift to k5d256_offset+127) &
k5(k5d256_offset to k5d256_offset+k5d256_shift-1);
t6_dec256 <= k6(k6d256_offset+k6d256_shift to k6d256_offset+127) &
k6(k6d256_offset to k6d256_offset+k6d256_shift-1);
 
-- subkeys generation
-- int_k1, int_k3, int_k5 get always the left/right slice when en/decrypting
-- int_k2, int_k4, int_k6 get always the right/left slice when en/decrypting
int_k1 <= t1_enc128(0 to 63) when dec1='0' and k_len1(0)='0' else
t1_dec128(64 to 127) when dec1='1' and k_len1(0)='0' else
t1_enc256(0 to 63) when dec1='0' and k_len1(0)='1' else
t1_dec256(64 to 127);
int_k2 <= t2_enc128(64 to 127) when dec2='0' and k_len2(0)='0' else
t2_dec128(0 to 63) when dec2='1' and k_len2(0)='0' else
t2_enc256(64 to 127) when dec2='0' and k_len2(0)='1' else
t2_dec256(0 to 63);
int_k3 <= t3_enc128(0 to 63) when dec3='0' and k_len3(0)='0' else
t3_dec128(64 to 127) when dec3='1' and k_len3(0)='0' else
t3_enc256(0 to 63) when dec3='0' and k_len3(0)='1' else
t3_dec256(64 to 127);
int_k4 <= t4_enc128(64 to 127) when dec4='0' and k_len4(0)='0' else
t4_dec128(0 to 63) when dec4='1' and k_len4(0)='0' else
t4_enc256(64 to 127) when dec4='0' and k_len4(0)='1' else
t4_dec256(0 to 63);
int_k5 <= t5_enc128(0 to 63) when dec5='0' and k_len5(0)='0' else
t5_dec128(64 to 127) when dec5='1' and k_len5(0)='0' else
t5_enc256(0 to 63) when dec5='0' and k_len5(0)='1' else
t5_dec256(64 to 127);
int_k6 <= t6_enc128(64 to 127) when dec6='0' and k_len6(0)='0' else
t6_dec128(0 to 63) when dec6='1' and k_len6(0)='0' else
t6_enc256(64 to 127) when dec6='0' and k_len6(0)='1' else
t6_dec256(0 to 63);
 
-- f inputs
f1_in <= l_in;
f2_in <= f1_out xor reg1_r;
f3_in <= f2_out xor reg2_r;
f4_in <= f3_out xor reg3_r;
f5_in <= f4_out xor reg4_r;
f6_in <= f5_out xor reg5_r;
 
F1 : F
port map(reset, clk, f1_in, int_k1, f1_out);
F2 : F
port map(reset, clk, f2_in, int_k2, f2_out);
F3 : F
port map(reset, clk, f3_in, int_k3, f3_out);
F4 : F
port map(reset, clk, f4_in, int_k4, f4_out);
F5 : F
port map(reset, clk, f5_in, int_k5, f5_out);
F6 : F
port map(reset, clk, f6_in, int_k6, f6_out);
 
 
REG : process(reset, clk)
begin
 
if (reset = '1') then
reg1_l <= (others=>'0');
reg1_r <= (others=>'0');
reg2_l <= (others=>'0');
reg2_r <= (others=>'0');
reg3_l <= (others=>'0');
reg3_r <= (others=>'0');
reg4_l <= (others=>'0');
reg4_r <= (others=>'0');
reg5_l <= (others=>'0');
reg5_r <= (others=>'0');
reg6_l <= (others=>'0');
reg6_r <= (others=>'0');
else
if (rising_edge(clk)) then -- rising clock edge
reg1_l <= f1_in;
reg1_r <= r_in;
reg2_l <= f2_in;
reg2_r <= reg1_l;
reg3_l <= f3_in;
reg3_r <= reg2_l;
reg4_l <= f4_in;
reg4_r <= reg3_l;
reg5_l <= f5_in;
reg5_r <= reg4_l;
reg6_l <= f6_in;
reg6_r <= reg5_l;
end if;
end if;
end process;
 
-- there isn't an output register
l_out <= f6_out xor reg6_r;
r_out <= reg6_l;
 
end RTL;
/camellia-vhdl/trunk/pipelining/f.vhd
0,0 → 1,142
 
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 09/14/2007
-- Last Update: 04/09/2008
-- Project Name: camellia-vhdl
-- Description: F function
--
-- Copyright (C) 2007 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
 
entity F is
port (
reset : in STD_LOGIC;
clk : in STD_LOGIC;
x : in STD_LOGIC_VECTOR (0 to 63);
k : in STD_LOGIC_VECTOR (0 to 63);
z : out STD_LOGIC_VECTOR (0 to 63)
);
end F;
 
architecture RTL of F is
 
-- S-BOX
component SBOX1 is
port (
clk : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(0 to 7);
addrb : IN STD_LOGIC_VECTOR(0 to 7);
douta : OUT STD_LOGIC_VECTOR(0 to 7);
doutb : OUT STD_LOGIC_VECTOR(0 to 7)
);
end component;
component SBOX2 is
port (
clk : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(0 to 7);
addrb : IN STD_LOGIC_VECTOR(0 to 7);
douta : OUT STD_LOGIC_VECTOR(0 to 7);
doutb : OUT STD_LOGIC_VECTOR(0 to 7)
 
);
end component;
component SBOX3 is
port (
clk : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(0 to 7);
addrb : IN STD_LOGIC_VECTOR(0 to 7);
douta : OUT STD_LOGIC_VECTOR(0 to 7);
doutb : OUT STD_LOGIC_VECTOR(0 to 7)
 
);
end component;
component SBOX4 is
port (
clk : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(0 to 7);
addrb : IN STD_LOGIC_VECTOR(0 to 7);
douta : OUT STD_LOGIC_VECTOR(0 to 7);
doutb : OUT STD_LOGIC_VECTOR(0 to 7)
 
);
end component;
 
 
signal y : STD_LOGIC_VECTOR (0 to 63);
signal y1, y2, y3, y4, y5, y6, y7, y8 : STD_LOGIC_VECTOR (0 to 7);
 
signal so1, so2, so3, so4, so5, so6, so7, so8 : STD_LOGIC_VECTOR (0 to 7);
 
signal pa1, pa2, pa3, pa4, pa5, pa6, pa7, pa8 : STD_LOGIC_VECTOR (0 to 7);
 
signal pb1, pb2, pb3, pb4, pb5, pb6, pb7, pb8 : STD_LOGIC_VECTOR (0 to 7);
 
 
begin
 
y <= x xor k;
 
y8 <= y(56 to 63);
y7 <= y(48 to 55);
y6 <= y(40 to 47);
y5 <= y(32 to 39);
y4 <= y(24 to 31);
y3 <= y(16 to 23);
y2 <= y(8 to 15);
y1 <= y(0 to 7);
 
 
-- S-FUNCTION
 
S1 : SBOX1
port map(clk, y8, y1, so8, so1);
S2 : SBOX2
port map(clk, y5, y2, so5, so2);
S3 : SBOX3
port map(clk, y6, y3, so6, so3);
S4 : SBOX4
port map(clk, y7, y4, so7, so4);
 
-- P-FUNCTION
pa8 <= so8 xor pa2;
pa7 <= so7 xor pa1;
pa6 <= so6 xor pa4;
pa5 <= so5 xor pa3;
pa4 <= so4 xor so5;
pa3 <= so3 xor so8;
pa2 <= so2 xor so7;
pa1 <= so1 xor so6;
 
pb8 <= pa8 xor pb3;
pb7 <= pa7 xor pb2;
pb6 <= pa6 xor pb1;
pb5 <= pa5 xor pb4;
pb4 <= pa4 xor pa7;
pb3 <= pa3 xor pa6;
pb2 <= pa2 xor pa5;
pb1 <= pa1 xor pa8;
 
 
z <= pb5 & pb6 & pb7 & pb8 & pb1 & pb2 & pb3 & pb4;
 
 
end RTL;
/camellia-vhdl/trunk/pipelining/camellia128_tb.vhd
0,0 → 1,111
 
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 09/14/2007
-- Last Update: 04/09/2008
-- Project Name: camellia-vhdl
-- Description: VHDL Test Bench for module CAMELLIA128
--
-- Copyright (C) 2007 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
 
entity camellia128_tb is
end camellia128_tb;
 
ARCHITECTURE behavior of camellia128_tb is
 
-- Component Declaration for the Unit Under Test (UUT)
component CAMELLIA128 is
port(
reset : in STD_LOGIC;
clk : in STD_LOGIC;
input : in STD_LOGIC_VECTOR (0 to 127);
input_en : in STD_LOGIC;
key : in STD_LOGIC_VECTOR (0 to 127);
enc_dec : in STD_LOGIC;
output : out STD_LOGIC_VECTOR (0 to 127);
output_rdy : out STD_LOGIC
);
end component;
 
--Inputs
signal reset : STD_LOGIC;
signal clk : STD_LOGIC;
signal input : STD_LOGIC_VECTOR(0 to 127) := (others=>'0');
signal input_en : STD_LOGIC := '0';
signal key : STD_LOGIC_VECTOR(0 to 127) := (others=>'0');
signal enc_dec : STD_LOGIC;
 
--Output
signal output : STD_LOGIC_VECTOR(0 to 127);
signal output_rdy : STD_LOGIC;
 
-- Time constants
constant ClockPeriod : TIME := 5 ns;
 
 
begin
 
-- Instantiate the Unit Under Test (UUT)
uut: CAMELLIA128
port map(
reset => reset,
clk => clk,
input => input,
input_en => input_en,
key => key,
enc_dec => enc_dec,
output => output,
output_rdy => output_rdy
);
 
ck : process
begin
clk <= '0';
wait for ClockPeriod / 2;
clk <= '1';
wait for ClockPeriod / 2;
end process;
 
process
begin
reset <= '1';
wait for ClockPeriod*2; --falling clock edge
reset <= '0';
wait until clk = '1';
input <= X"0123456789ABCDEFFEDCBA9876543210";
key <= X"0123456789ABCDEFFEDCBA9876543210";
enc_dec <= '0';
input_en <= '1';
wait until clk = '1';
input <= X"17E02528D6655CEA7BE6B8548FC2DA65";
key <= X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE";
enc_dec <= '1';
wait until clk = '1';
input <= X"67673138549669730857065648EABE43";
key <= X"0123456789ABCDEFFEDCBA9876543210";
enc_dec <= '1';
wait until clk = '1';
input_en <= '0';
wait;
end process;
 
end;
/camellia-vhdl/trunk/pipelining/keysched128.vhd
0,0 → 1,145
 
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 09/14/2007
-- Last Update: 04/09/2008
-- Project Name: camellia-vhdl
-- Description: Key schedule only for 128-bit keys
--
-- Copyright (C) 2007 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
 
 
entity KEYSCHED128 is
port (
reset : in STD_LOGIC;
clk : in STD_LOGIC;
kl_in : in STD_LOGIC_VECTOR (0 to 127);
kl_out : out STD_LOGIC_VECTOR (0 to 127);
ka_out : out STD_LOGIC_VECTOR (0 to 127)
);
end KEYSCHED128;
 
architecture RTL of KEYSCHED128 is
 
component F is
port (
reset : in STD_LOGIC;
clk : in STD_LOGIC;
x : in STD_LOGIC_VECTOR (0 to 63);
k : in STD_LOGIC_VECTOR (0 to 63);
z : out STD_LOGIC_VECTOR (0 to 63)
);
end component;
 
-- f inputs
signal f1_in : STD_LOGIC_VECTOR (0 to 63);
signal f2_in : STD_LOGIC_VECTOR (0 to 63);
signal f3_in : STD_LOGIC_VECTOR (0 to 63);
signal f4_in : STD_LOGIC_VECTOR (0 to 63);
 
-- f outputs
signal f1_out : STD_LOGIC_VECTOR (0 to 63);
signal f2_out : STD_LOGIC_VECTOR (0 to 63);
signal f3_out : STD_LOGIC_VECTOR (0 to 63);
signal f4_out : STD_LOGIC_VECTOR (0 to 63);
 
-- intermediate registers
signal reg1_l : STD_LOGIC_VECTOR (0 to 63);
signal reg1_r : STD_LOGIC_VECTOR (0 to 63);
signal reg1_kl : STD_LOGIC_VECTOR (0 to 127);
signal reg2_l : STD_LOGIC_VECTOR (0 to 63);
signal reg2_r : STD_LOGIC_VECTOR (0 to 63);
signal reg2_kl : STD_LOGIC_VECTOR (0 to 127);
signal reg3_l : STD_LOGIC_VECTOR (0 to 63);
signal reg3_r : STD_LOGIC_VECTOR (0 to 63);
signal reg3_kl : STD_LOGIC_VECTOR (0 to 127);
signal reg4_l : STD_LOGIC_VECTOR (0 to 63);
signal reg4_r : STD_LOGIC_VECTOR (0 to 63);
signal reg4_kl : STD_LOGIC_VECTOR (0 to 127);
 
-- constant keys
constant k1 : STD_LOGIC_VECTOR (0 to 63) := X"A09E667F3BCC908B";
constant k2 : STD_LOGIC_VECTOR (0 to 63) := X"B67AE8584CAA73B2";
constant k3 : STD_LOGIC_VECTOR (0 to 63) := X"C6EF372FE94F82BE";
constant k4 : STD_LOGIC_VECTOR (0 to 63) := X"54FF53A5F1D36F1C";
 
-- intermediate signal
signal inter : STD_LOGIC_VECTOR (0 to 127);
 
begin
 
F1 : F
port map(reset, clk, f1_in, k1, f1_out);
F2 : F
port map(reset, clk, f2_in, k2, f2_out);
F3 : F
port map(reset, clk, f3_in, k3, f3_out);
F4 : F
port map(reset, clk, f4_in, k4, f4_out);
 
REG : process(reset, clk)
begin
 
if (reset = '1') then
reg1_l <= (others=>'0');
reg1_r <= (others=>'0');
reg1_kl <= (others=>'0');
reg2_l <= (others=>'0');
reg2_r <= (others=>'0');
reg2_kl <= (others=>'0');
reg3_l <= (others=>'0');
reg3_r <= (others=>'0');
reg3_kl <= (others=>'0');
reg4_l <= (others=>'0');
reg4_r <= (others=>'0');
reg4_kl <= (others=>'0');
else
if (rising_edge(clk)) then -- rising clock edge
reg1_l <= f1_in;
reg1_r <= kl_in(64 to 127);
reg1_kl <= kl_in;
reg2_l <= f2_in;
reg2_r <= reg1_l;
reg2_kl <= reg1_kl;
reg3_l <= f3_in;
reg3_r <= inter(64 to 127);
reg3_kl <= reg2_kl;
reg4_l <= f4_in;
reg4_r <= reg3_l;
reg4_kl <= reg3_kl;
end if;
end if;
end process;
 
inter <= ((f2_out xor reg2_r) & reg2_l) xor reg2_kl;
 
-- f inputs
f1_in <= kl_in(0 to 63);
f2_in <= f1_out xor reg1_r;
f3_in <= inter(0 to 63);
f4_in <= f3_out xor reg3_r;
 
-- output
kl_out <= reg4_kl;
ka_out <= (f4_out xor reg4_r) & reg4_l;
 
end RTL;
/camellia-vhdl/trunk/pipelining/fl128.vhd
0,0 → 1,138
 
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 09/14/2007
-- Last Update: 04/09/2008
-- Project Name: camellia-vhdl
-- Description: FL and FL^-1 functions, only for 128-bit key en/decryption
--
-- Copyright (C) 2007 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
 
 
entity FL128 is
generic (
fl_ke_offset : INTEGER; -- encryption
fl_ke_shift : INTEGER;
fli_ke_offset : INTEGER;
fli_ke_shift : INTEGER;
fl_kd_offset : INTEGER; -- decryption
fl_kd_shift : INTEGER;
fli_kd_offset : INTEGER;
fli_kd_shift : INTEGER
);
port(
reset : in STD_LOGIC;
clk : in STD_LOGIC;
fl_in : in STD_LOGIC_VECTOR (0 to 63);
fli_in : in STD_LOGIC_VECTOR (0 to 63);
k : in STD_LOGIC_VECTOR (0 to 255);
dec : in STD_LOGIC;
fl_out : out STD_LOGIC_VECTOR (0 to 63);
fli_out : out STD_LOGIC_VECTOR (0 to 63)
);
end FL128;
 
architecture RTL of FL128 is
 
signal fl_in_l : STD_LOGIC_VECTOR (0 to 31);
signal fl_in_r : STD_LOGIC_VECTOR (0 to 31);
signal fli_in_l : STD_LOGIC_VECTOR (0 to 31);
signal fli_in_r : STD_LOGIC_VECTOR (0 to 31);
 
signal tmp_fl_ke : STD_LOGIC_VECTOR (0 to 127); -- encryption
signal tmp_fli_ke : STD_LOGIC_VECTOR (0 to 127);
signal tmp_fl_kd : STD_LOGIC_VECTOR (0 to 127); -- decryption
signal tmp_fli_kd : STD_LOGIC_VECTOR (0 to 127);
 
signal fl_k_l : STD_LOGIC_VECTOR (0 to 31);
signal fl_k_r : STD_LOGIC_VECTOR (0 to 31);
signal fli_k_l : STD_LOGIC_VECTOR (0 to 31);
signal fli_k_r : STD_LOGIC_VECTOR (0 to 31);
 
signal fl_a1 : STD_LOGIC_VECTOR (0 to 31);
signal fl_a2 : STD_LOGIC_VECTOR (0 to 31);
signal fl_b1 : STD_LOGIC_VECTOR (0 to 31);
signal fl_b2 : STD_LOGIC_VECTOR (0 to 31);
signal fli_a1 : STD_LOGIC_VECTOR (0 to 31);
signal fli_a2 : STD_LOGIC_VECTOR (0 to 31);
signal fli_b1 : STD_LOGIC_VECTOR (0 to 31);
signal fli_b2 : STD_LOGIC_VECTOR (0 to 31);
 
-- registers
signal reg_fl_in : STD_LOGIC_VECTOR (0 to 63);
signal reg_fli_in : STD_LOGIC_VECTOR (0 to 63);
 
begin
 
REG : process(reset, clk)
begin
 
if (reset = '1') then
reg_fl_in <= (others=>'0');
reg_fli_in <= (others=>'0');
else
if (rising_edge(clk)) then -- rising clock edge
reg_fl_in <= fl_in;
reg_fli_in <= fli_in;
end if;
end if;
end process;
 
--FL function
fl_in_l <= reg_fl_in(0 to 31);
fl_in_r <= reg_fl_in(32 to 63);
 
tmp_fl_ke <= k(fl_ke_offset+fl_ke_shift to fl_ke_offset+127) &
k(fl_ke_offset to fl_ke_offset+fl_ke_shift-1);
tmp_fl_kd <= k(fl_kd_offset+fl_kd_shift to fl_kd_offset+127) &
k(fl_kd_offset to fl_kd_offset+fl_kd_shift-1);
fl_k_l <= tmp_fl_ke(0 to 31) when dec='0' else tmp_fl_kd(64 to 95);
fl_k_r <= tmp_fl_ke(32 to 63) when dec='0' else tmp_fl_kd(96 to 127);
 
fl_a1 <= fl_in_l and fl_k_l;
fl_a2 <= (fl_a1(1 to 31) & fl_a1(0)) xor fl_in_r;
 
fl_b1 <= fl_a2 or fl_k_r;
fl_b2 <= fl_in_l xor fl_b1;
 
fl_out <= fl_b2 & fl_a2;
 
--FL^-1 function
fli_in_l <= reg_fli_in(0 to 31);
fli_in_r <= reg_fli_in(32 to 63);
 
tmp_fli_ke <= k(fli_ke_offset+fli_ke_shift to fli_ke_offset+127) &
k(fli_ke_offset to fli_ke_offset+fli_ke_shift-1);
tmp_fli_kd <= k(fli_kd_offset+fli_kd_shift to fli_kd_offset+127) &
k(fli_kd_offset to fli_kd_offset+fli_kd_shift-1);
fli_k_l <= tmp_fli_ke(64 to 95) when dec='0' else tmp_fli_kd(0 to 31);
fli_k_r <= tmp_fli_ke(96 to 127) when dec='0' else tmp_fli_kd(32 to 63);
 
fli_a1 <= fli_in_r or fli_k_r;
fli_a2 <= fli_in_l xor fli_a1;
 
fli_b1 <= fli_a2 and fli_k_l;
fli_b2 <= (fli_b1(1 to 31) & fli_b1(0)) xor fli_in_r;
 
fli_out <= fli_a2 & fli_b2;
 
end RTL;
/camellia-vhdl/trunk/pipelining/keysched256.vhd
0,0 → 1,208
 
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 09/15/2007
-- Last Update: 04/09/2008
-- Project Name: camellia-vhdl
-- Description: Key schedule for 128/192/256-bit keys
--
-- Copyright (C) 2007 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
 
 
entity KEYSCHED256 is
port(
reset : in STD_LOGIC;
clk : in STD_LOGIC;
kl_in : in STD_LOGIC_VECTOR (0 to 127);
kr_in : in STD_LOGIC_VECTOR (0 to 127);
kl_out : out STD_LOGIC_VECTOR (0 to 127);
kr_out : out STD_LOGIC_VECTOR (0 to 127);
ka_out : out STD_LOGIC_VECTOR (0 to 127);
kb_out : out STD_LOGIC_VECTOR (0 to 127)
);
end KEYSCHED256;
 
architecture RTL of KEYSCHED256 is
 
component F is
port (
reset : in STD_LOGIC;
clk : in STD_LOGIC;
x : in STD_LOGIC_VECTOR (0 to 63);
k : in STD_LOGIC_VECTOR (0 to 63);
z : out STD_LOGIC_VECTOR (0 to 63)
);
end component;
 
-- f inputs
signal f1_in : STD_LOGIC_VECTOR (0 to 63);
signal f2_in : STD_LOGIC_VECTOR (0 to 63);
signal f3_in : STD_LOGIC_VECTOR (0 to 63);
signal f4_in : STD_LOGIC_VECTOR (0 to 63);
signal f5_in : STD_LOGIC_VECTOR (0 to 63);
signal f6_in : STD_LOGIC_VECTOR (0 to 63);
 
-- f outputs
signal f1_out : STD_LOGIC_VECTOR (0 to 63);
signal f2_out : STD_LOGIC_VECTOR (0 to 63);
signal f3_out : STD_LOGIC_VECTOR (0 to 63);
signal f4_out : STD_LOGIC_VECTOR (0 to 63);
signal f5_out : STD_LOGIC_VECTOR (0 to 63);
signal f6_out : STD_LOGIC_VECTOR (0 to 63);
 
-- intermediate registers
signal reg1_l : STD_LOGIC_VECTOR (0 to 63);
signal reg1_r : STD_LOGIC_VECTOR (0 to 63);
signal reg1_kl : STD_LOGIC_VECTOR (0 to 127);
signal reg1_kr : STD_LOGIC_VECTOR (0 to 127);
signal reg2_l : STD_LOGIC_VECTOR (0 to 63);
signal reg2_r : STD_LOGIC_VECTOR (0 to 63);
signal reg2_kl : STD_LOGIC_VECTOR (0 to 127);
signal reg2_kr : STD_LOGIC_VECTOR (0 to 127);
signal reg3_l : STD_LOGIC_VECTOR (0 to 63);
signal reg3_r : STD_LOGIC_VECTOR (0 to 63);
signal reg3_kl : STD_LOGIC_VECTOR (0 to 127);
signal reg3_kr : STD_LOGIC_VECTOR (0 to 127);
signal reg4_l : STD_LOGIC_VECTOR (0 to 63);
signal reg4_r : STD_LOGIC_VECTOR (0 to 63);
signal reg4_kl : STD_LOGIC_VECTOR (0 to 127);
signal reg4_kr : STD_LOGIC_VECTOR (0 to 127);
signal reg5_l : STD_LOGIC_VECTOR (0 to 63);
signal reg5_r : STD_LOGIC_VECTOR (0 to 63);
signal reg5_kl : STD_LOGIC_VECTOR (0 to 127);
signal reg5_kr : STD_LOGIC_VECTOR (0 to 127);
signal reg5_ka : STD_LOGIC_VECTOR (0 to 127);
signal reg6_l : STD_LOGIC_VECTOR (0 to 63);
signal reg6_r : STD_LOGIC_VECTOR (0 to 63);
signal reg6_kl : STD_LOGIC_VECTOR (0 to 127);
signal reg6_kr : STD_LOGIC_VECTOR (0 to 127);
signal reg6_ka : STD_LOGIC_VECTOR (0 to 127);
 
-- constant keys
constant k1 : STD_LOGIC_VECTOR (0 to 63) := X"A09E667F3BCC908B";
constant k2 : STD_LOGIC_VECTOR (0 to 63) := X"B67AE8584CAA73B2";
constant k3 : STD_LOGIC_VECTOR (0 to 63) := X"C6EF372FE94F82BE";
constant k4 : STD_LOGIC_VECTOR (0 to 63) := X"54FF53A5F1D36F1C";
constant k5 : STD_LOGIC_VECTOR (0 to 63) := X"10E527FADE682D1D";
constant k6 : STD_LOGIC_VECTOR (0 to 63) := X"B05688C2B3E6C1FD";
 
-- intermediate signals
signal inter1 : STD_LOGIC_VECTOR (0 to 127);
signal inter2 : STD_LOGIC_VECTOR (0 to 127);
signal ka_tmp : STD_LOGIC_VECTOR (0 to 127);
 
begin
 
F1 : F
port map(reset, clk, f1_in, k1, f1_out);
F2 : F
port map(reset, clk, f2_in, k2, f2_out);
F3 : F
port map(reset, clk, f3_in, k3, f3_out);
F4 : F
port map(reset, clk, f4_in, k4, f4_out);
F5 : F
port map(reset, clk, f5_in, k5, f5_out);
F6 : F
port map(reset, clk, f6_in, k6, f6_out);
 
REG : process(reset, clk)
begin
 
if (reset = '1') then
reg1_l <= (others=>'0');
reg1_r <= (others=>'0');
reg1_kl <= (others=>'0');
reg1_kr <= (others=>'0');
reg2_l <= (others=>'0');
reg2_r <= (others=>'0');
reg2_kl <= (others=>'0');
reg2_kr <= (others=>'0');
reg3_l <= (others=>'0');
reg3_r <= (others=>'0');
reg3_kl <= (others=>'0');
reg3_kr <= (others=>'0');
reg4_l <= (others=>'0');
reg4_r <= (others=>'0');
reg4_kl <= (others=>'0');
reg4_kr <= (others=>'0');
reg5_l <= (others=>'0');
reg5_r <= (others=>'0');
reg5_kl <= (others=>'0');
reg5_kr <= (others=>'0');
reg5_ka <= (others=>'0');
reg6_l <= (others=>'0');
reg6_r <= (others=>'0');
reg6_kl <= (others=>'0');
reg6_kr <= (others=>'0');
reg6_ka <= (others=>'0');
else
if (rising_edge(clk)) then -- rising clock edge
reg1_l <= f1_in;
reg1_r <= kl_in(64 to 127) xor kr_in(64 to 127);
reg1_kl <= kl_in;
reg1_kr <= kr_in;
reg2_l <= f2_in;
reg2_r <= reg1_l;
reg2_kl <= reg1_kl;
reg2_kr <= reg1_kr;
reg3_l <= f3_in;
reg3_r <= inter1(64 to 127);
reg3_kl <= reg2_kl;
reg3_kr <= reg2_kr;
reg4_l <= f4_in;
reg4_r <= reg3_l;
reg4_kl <= reg3_kl;
reg4_kr <= reg3_kr;
reg5_l <= f5_in;
reg5_r <= inter2(64 to 127);
reg5_kl <= reg4_kl;
reg5_kr <= reg4_kr;
reg5_ka <= ka_tmp;
reg6_l <= f6_in;
reg6_r <= reg5_l;
reg6_kl <= reg5_kl;
reg6_kr <= reg5_kr;
reg6_ka <= reg5_ka;
end if;
end if;
end process;
 
inter1 <= ((f2_out xor reg2_r) & reg2_l) xor reg2_kl;
ka_tmp <= (f4_out xor reg4_r) & reg4_l;
inter2 <= ka_tmp xor reg4_kr;
 
-- f inputs
f1_in <= kl_in(0 to 63) xor kr_in(0 to 63);
f2_in <= f1_out xor reg1_r;
f3_in <= inter1(0 to 63);
f4_in <= f3_out xor reg3_r;
f5_in <= inter2(0 to 63);
f6_in <= f5_out xor reg5_r;
 
-- output
kl_out <= reg6_kl;
kr_out <= reg6_kr;
ka_out <= reg6_ka;
kb_out <= (f6_out xor reg6_r) & reg6_l;
 
end RTL;
/camellia-vhdl/trunk/pipelining/sbox1.vhd
0,0 → 1,322
 
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 09/14/2007
-- Last Update: 04/09/2008
-- Project Name: camellia-vhdl
-- Description: Dual-port SBOX1
--
-- Copyright (C) 2007 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
 
 
entity SBOX1 is
port (
clk : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(0 to 7);
addrb : IN STD_LOGIC_VECTOR(0 to 7);
douta : OUT STD_LOGIC_VECTOR(0 to 7);
doutb : OUT STD_LOGIC_VECTOR(0 to 7)
);
end SBOX1;
 
architecture RTL of SBOX1 is
 
subtype ROM_WORD is STD_LOGIC_VECTOR (0 to 7);
type ROM_TABLE is array (0 to 255) of ROM_WORD;
 
constant ROM: ROM_TABLE := ROM_TABLE'(
ROM_WORD'(X"70"),
ROM_WORD'(X"82"),
ROM_WORD'(X"2C"),
ROM_WORD'(X"EC"),
ROM_WORD'(X"B3"),
ROM_WORD'(X"27"),
ROM_WORD'(X"C0"),
ROM_WORD'(X"E5"),
ROM_WORD'(X"E4"),
ROM_WORD'(X"85"),
ROM_WORD'(X"57"),
ROM_WORD'(X"35"),
ROM_WORD'(X"EA"),
ROM_WORD'(X"0C"),
ROM_WORD'(X"AE"),
ROM_WORD'(X"41"),
ROM_WORD'(X"23"),
ROM_WORD'(X"EF"),
ROM_WORD'(X"6B"),
ROM_WORD'(X"93"),
ROM_WORD'(X"45"),
ROM_WORD'(X"19"),
ROM_WORD'(X"A5"),
ROM_WORD'(X"21"),
ROM_WORD'(X"ED"),
ROM_WORD'(X"0E"),
ROM_WORD'(X"4F"),
ROM_WORD'(X"4E"),
ROM_WORD'(X"1D"),
ROM_WORD'(X"65"),
ROM_WORD'(X"92"),
ROM_WORD'(X"BD"),
ROM_WORD'(X"86"),
ROM_WORD'(X"B8"),
ROM_WORD'(X"AF"),
ROM_WORD'(X"8F"),
ROM_WORD'(X"7C"),
ROM_WORD'(X"EB"),
ROM_WORD'(X"1F"),
ROM_WORD'(X"CE"),
ROM_WORD'(X"3E"),
ROM_WORD'(X"30"),
ROM_WORD'(X"DC"),
ROM_WORD'(X"5F"),
ROM_WORD'(X"5E"),
ROM_WORD'(X"C5"),
ROM_WORD'(X"0B"),
ROM_WORD'(X"1A"),
ROM_WORD'(X"A6"),
ROM_WORD'(X"E1"),
ROM_WORD'(X"39"),
ROM_WORD'(X"CA"),
ROM_WORD'(X"D5"),
ROM_WORD'(X"47"),
ROM_WORD'(X"5D"),
ROM_WORD'(X"3D"),
ROM_WORD'(X"D9"),
ROM_WORD'(X"01"),
ROM_WORD'(X"5A"),
ROM_WORD'(X"D6"),
ROM_WORD'(X"51"),
ROM_WORD'(X"56"),
ROM_WORD'(X"6C"),
ROM_WORD'(X"4D"),
ROM_WORD'(X"8B"),
ROM_WORD'(X"0D"),
ROM_WORD'(X"9A"),
ROM_WORD'(X"66"),
ROM_WORD'(X"FB"),
ROM_WORD'(X"CC"),
ROM_WORD'(X"B0"),
ROM_WORD'(X"2D"),
ROM_WORD'(X"74"),
ROM_WORD'(X"12"),
ROM_WORD'(X"2B"),
ROM_WORD'(X"20"),
ROM_WORD'(X"F0"),
ROM_WORD'(X"B1"),
ROM_WORD'(X"84"),
ROM_WORD'(X"99"),
ROM_WORD'(X"DF"),
ROM_WORD'(X"4C"),
ROM_WORD'(X"CB"),
ROM_WORD'(X"C2"),
ROM_WORD'(X"34"),
ROM_WORD'(X"7E"),
ROM_WORD'(X"76"),
ROM_WORD'(X"05"),
ROM_WORD'(X"6D"),
ROM_WORD'(X"B7"),
ROM_WORD'(X"A9"),
ROM_WORD'(X"31"),
ROM_WORD'(X"D1"),
ROM_WORD'(X"17"),
ROM_WORD'(X"04"),
ROM_WORD'(X"D7"),
ROM_WORD'(X"14"),
ROM_WORD'(X"58"),
ROM_WORD'(X"3A"),
ROM_WORD'(X"61"),
ROM_WORD'(X"DE"),
ROM_WORD'(X"1B"),
ROM_WORD'(X"11"),
ROM_WORD'(X"1C"),
ROM_WORD'(X"32"),
ROM_WORD'(X"0F"),
ROM_WORD'(X"9C"),
ROM_WORD'(X"16"),
ROM_WORD'(X"53"),
ROM_WORD'(X"18"),
ROM_WORD'(X"F2"),
ROM_WORD'(X"22"),
ROM_WORD'(X"FE"),
ROM_WORD'(X"44"),
ROM_WORD'(X"CF"),
ROM_WORD'(X"B2"),
ROM_WORD'(X"C3"),
ROM_WORD'(X"B5"),
ROM_WORD'(X"7A"),
ROM_WORD'(X"91"),
ROM_WORD'(X"24"),
ROM_WORD'(X"08"),
ROM_WORD'(X"E8"),
ROM_WORD'(X"A8"),
ROM_WORD'(X"60"),
ROM_WORD'(X"FC"),
ROM_WORD'(X"69"),
ROM_WORD'(X"50"),
ROM_WORD'(X"AA"),
ROM_WORD'(X"D0"),
ROM_WORD'(X"A0"),
ROM_WORD'(X"7D"),
ROM_WORD'(X"A1"),
ROM_WORD'(X"89"),
ROM_WORD'(X"62"),
ROM_WORD'(X"97"),
ROM_WORD'(X"54"),
ROM_WORD'(X"5B"),
ROM_WORD'(X"1E"),
ROM_WORD'(X"95"),
ROM_WORD'(X"E0"),
ROM_WORD'(X"FF"),
ROM_WORD'(X"64"),
ROM_WORD'(X"D2"),
ROM_WORD'(X"10"),
ROM_WORD'(X"C4"),
ROM_WORD'(X"00"),
ROM_WORD'(X"48"),
ROM_WORD'(X"A3"),
ROM_WORD'(X"F7"),
ROM_WORD'(X"75"),
ROM_WORD'(X"DB"),
ROM_WORD'(X"8A"),
ROM_WORD'(X"03"),
ROM_WORD'(X"E6"),
ROM_WORD'(X"DA"),
ROM_WORD'(X"09"),
ROM_WORD'(X"3F"),
ROM_WORD'(X"DD"),
ROM_WORD'(X"94"),
ROM_WORD'(X"87"),
ROM_WORD'(X"5C"),
ROM_WORD'(X"83"),
ROM_WORD'(X"02"),
ROM_WORD'(X"CD"),
ROM_WORD'(X"4A"),
ROM_WORD'(X"90"),
ROM_WORD'(X"33"),
ROM_WORD'(X"73"),
ROM_WORD'(X"67"),
ROM_WORD'(X"F6"),
ROM_WORD'(X"F3"),
ROM_WORD'(X"9D"),
ROM_WORD'(X"7F"),
ROM_WORD'(X"BF"),
ROM_WORD'(X"E2"),
ROM_WORD'(X"52"),
ROM_WORD'(X"9B"),
ROM_WORD'(X"D8"),
ROM_WORD'(X"26"),
ROM_WORD'(X"C8"),
ROM_WORD'(X"37"),
ROM_WORD'(X"C6"),
ROM_WORD'(X"3B"),
ROM_WORD'(X"81"),
ROM_WORD'(X"96"),
ROM_WORD'(X"6F"),
ROM_WORD'(X"4B"),
ROM_WORD'(X"13"),
ROM_WORD'(X"BE"),
ROM_WORD'(X"63"),
ROM_WORD'(X"2E"),
ROM_WORD'(X"E9"),
ROM_WORD'(X"79"),
ROM_WORD'(X"A7"),
ROM_WORD'(X"8C"),
ROM_WORD'(X"9F"),
ROM_WORD'(X"6E"),
ROM_WORD'(X"BC"),
ROM_WORD'(X"8E"),
ROM_WORD'(X"29"),
ROM_WORD'(X"F5"),
ROM_WORD'(X"F9"),
ROM_WORD'(X"B6"),
ROM_WORD'(X"2F"),
ROM_WORD'(X"FD"),
ROM_WORD'(X"B4"),
ROM_WORD'(X"59"),
ROM_WORD'(X"78"),
ROM_WORD'(X"98"),
ROM_WORD'(X"06"),
ROM_WORD'(X"6A"),
ROM_WORD'(X"E7"),
ROM_WORD'(X"46"),
ROM_WORD'(X"71"),
ROM_WORD'(X"BA"),
ROM_WORD'(X"D4"),
ROM_WORD'(X"25"),
ROM_WORD'(X"AB"),
ROM_WORD'(X"42"),
ROM_WORD'(X"88"),
ROM_WORD'(X"A2"),
ROM_WORD'(X"8D"),
ROM_WORD'(X"FA"),
ROM_WORD'(X"72"),
ROM_WORD'(X"07"),
ROM_WORD'(X"B9"),
ROM_WORD'(X"55"),
ROM_WORD'(X"F8"),
ROM_WORD'(X"EE"),
ROM_WORD'(X"AC"),
ROM_WORD'(X"0A"),
ROM_WORD'(X"36"),
ROM_WORD'(X"49"),
ROM_WORD'(X"2A"),
ROM_WORD'(X"68"),
ROM_WORD'(X"3C"),
ROM_WORD'(X"38"),
ROM_WORD'(X"F1"),
ROM_WORD'(X"A4"),
ROM_WORD'(X"40"),
ROM_WORD'(X"28"),
ROM_WORD'(X"D3"),
ROM_WORD'(X"7B"),
ROM_WORD'(X"BB"),
ROM_WORD'(X"C9"),
ROM_WORD'(X"43"),
ROM_WORD'(X"C1"),
ROM_WORD'(X"15"),
ROM_WORD'(X"E3"),
ROM_WORD'(X"AD"),
ROM_WORD'(X"F4"),
ROM_WORD'(X"77"),
ROM_WORD'(X"C7"),
ROM_WORD'(X"80"),
ROM_WORD'(X"9E")
);
begin
 
PORT_A : process(clk)
begin
if(rising_edge(clk)) then
douta <= ROM(conv_integer(addra));
end if;
end process;
 
PORT_B : process(clk)
begin
if(rising_edge(clk)) then
doutb <= ROM(conv_integer(addrb));
end if;
end process;
 
end RTL;
/camellia-vhdl/trunk/pipelining/sbox2.vhd
0,0 → 1,72
 
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 09/14/2007
-- Last Update: 04/09/2008
-- Project Name: camellia-vhdl
-- Description: Dual-port SBOX2
--
-- Copyright (C) 2007 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
 
 
entity SBOX2 is
port (
clk : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(0 to 7);
addrb : IN STD_LOGIC_VECTOR(0 to 7);
douta : OUT STD_LOGIC_VECTOR(0 to 7);
doutb : OUT STD_LOGIC_VECTOR(0 to 7)
);
end SBOX2;
 
architecture RTL of SBOX2 is
 
component SBOX1 is
port (
clk : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(0 to 7);
addrb : IN STD_LOGIC_VECTOR(0 to 7);
douta : OUT STD_LOGIC_VECTOR(0 to 7);
doutb : OUT STD_LOGIC_VECTOR(0 to 7)
);
end component;
 
-- SBOX1 signals
signal s1_addra : STD_LOGIC_VECTOR(0 to 7);
signal s1_addrb : STD_LOGIC_VECTOR(0 to 7);
signal s1_clk : STD_LOGIC;
signal s1_douta : STD_LOGIC_VECTOR(0 to 7);
signal s1_doutb : STD_LOGIC_VECTOR(0 to 7);
 
begin
 
S1 : SBOX1
port map(s1_clk, s1_addra, s1_addrb, s1_douta, s1_doutb);
 
s1_clk <= clk;
s1_addra <= addra;
s1_addrb <= addrb;
 
douta <= s1_douta(1 to 7) & s1_douta(0);
doutb <= s1_doutb(1 to 7) & s1_doutb(0);
 
end RTL;
/camellia-vhdl/trunk/pipelining/fl256.vhd
0,0 → 1,170
 
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 09/14/2007
-- Last Update: 04/09/2008
-- Project Name: camellia-vhdl
-- Description: FL and FL^-1 functions, for 128/192/256-bit key en/decryption
--
-- Copyright (C) 2007 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
 
 
entity FL256 is
generic (
fl_ke128_offset : INTEGER; -- 128bit encryption
fl_ke128_shift : INTEGER;
fli_ke128_offset : INTEGER;
fli_ke128_shift : INTEGER;
fl_kd128_offset : INTEGER; -- 128bit decryption
fl_kd128_shift : INTEGER;
fli_kd128_offset : INTEGER;
fli_kd128_shift : INTEGER;
fl_ke256_offset : INTEGER; -- 192/256bit encryption
fl_ke256_shift : INTEGER;
fli_ke256_offset : INTEGER;
fli_ke256_shift : INTEGER;
fl_kd256_offset : INTEGER; -- 192/256bit decryption
fl_kd256_shift : INTEGER;
fli_kd256_offset : INTEGER;
fli_kd256_shift : INTEGER
);
port(
reset : in STD_LOGIC;
clk : in STD_LOGIC;
fl_in : in STD_LOGIC_VECTOR (0 to 63);
fli_in : in STD_LOGIC_VECTOR (0 to 63);
k : in STD_LOGIC_VECTOR (0 to 511);
k_len : in STD_LOGIC_VECTOR (0 to 1);
dec : in STD_LOGIC;
fl_out : out STD_LOGIC_VECTOR (0 to 63);
fli_out : out STD_LOGIC_VECTOR (0 to 63)
);
end FL256;
 
architecture RTL of FL256 is
 
signal fl_in_l : STD_LOGIC_VECTOR (0 to 31);
signal fl_in_r : STD_LOGIC_VECTOR (0 to 31);
signal fli_in_l : STD_LOGIC_VECTOR (0 to 31);
signal fli_in_r : STD_LOGIC_VECTOR (0 to 31);
 
signal fl_ke128 : STD_LOGIC_VECTOR (0 to 127); -- 128bit encryption
signal fli_ke128 : STD_LOGIC_VECTOR (0 to 127);
signal fl_kd128 : STD_LOGIC_VECTOR (0 to 127); -- 128bit decryption
signal fli_kd128 : STD_LOGIC_VECTOR (0 to 127);
signal fl_ke256 : STD_LOGIC_VECTOR (0 to 127); -- 192/256bit encryption
signal fli_ke256 : STD_LOGIC_VECTOR (0 to 127);
signal fl_kd256 : STD_LOGIC_VECTOR (0 to 127); -- 192/256bit decryption
signal fli_kd256 : STD_LOGIC_VECTOR (0 to 127);
signal fl_k_l : STD_LOGIC_VECTOR (0 to 31);
signal fl_k_r : STD_LOGIC_VECTOR (0 to 31);
signal fli_k_l : STD_LOGIC_VECTOR (0 to 31);
signal fli_k_r : STD_LOGIC_VECTOR (0 to 31);
 
signal fl_a1 : STD_LOGIC_VECTOR (0 to 31);
signal fl_a2 : STD_LOGIC_VECTOR (0 to 31);
signal fl_b1 : STD_LOGIC_VECTOR (0 to 31);
signal fl_b2 : STD_LOGIC_VECTOR (0 to 31);
signal fli_a1 : STD_LOGIC_VECTOR (0 to 31);
signal fli_a2 : STD_LOGIC_VECTOR (0 to 31);
signal fli_b1 : STD_LOGIC_VECTOR (0 to 31);
signal fli_b2 : STD_LOGIC_VECTOR (0 to 31);
 
-- registers
signal reg_fl_in : STD_LOGIC_VECTOR (0 to 63);
signal reg_fli_in : STD_LOGIC_VECTOR (0 to 63);
 
begin
 
REG : process(reset, clk)
begin
 
if (reset = '1') then
reg_fl_in <= (others=>'0');
reg_fli_in <= (others=>'0');
else
if (rising_edge(clk)) then -- rising clock edge
reg_fl_in <= fl_in;
reg_fli_in <= fli_in;
end if;
end if;
end process;
 
--FL function
fl_in_l <= reg_fl_in(0 to 31);
fl_in_r <= reg_fl_in(32 to 63);
 
fl_ke128 <= k(fl_ke128_offset+fl_ke128_shift to fl_ke128_offset+127) &
k(fl_ke128_offset to fl_ke128_offset+fl_ke128_shift-1);
fl_kd128 <= k(fl_kd128_offset+fl_kd128_shift to fl_kd128_offset+127) &
k(fl_kd128_offset to fl_kd128_offset+fl_kd128_shift-1);
fl_ke256 <= k(fl_ke256_offset+fl_ke256_shift to fl_ke256_offset+127) &
k(fl_ke256_offset to fl_ke256_offset+fl_ke256_shift-1);
fl_kd256 <= k(fl_kd256_offset+fl_kd256_shift to fl_kd256_offset+127) &
k(fl_kd256_offset to fl_kd256_offset+fl_kd256_shift-1);
fl_k_l <= fl_ke128(0 to 31) when dec='0' and k_len(0)='0' else
fl_kd128(64 to 95) when dec='1' and k_len(0)='0' else
fl_ke256(0 to 31) when dec='0' and k_len(0)='1' else
fl_kd256(64 to 95);
fl_k_r <= fl_ke128(32 to 63) when dec='0' and k_len(0)='0' else
fl_kd128(96 to 127) when dec='1' and k_len(0)='0' else
fl_ke256(32 to 63) when dec='0' and k_len(0)='1' else
fl_kd256(96 to 127);
 
fl_a1 <= fl_in_l and fl_k_l;
fl_a2 <= (fl_a1(1 to 31) & fl_a1(0)) xor fl_in_r;
 
fl_b1 <= fl_a2 or fl_k_r;
fl_b2 <= fl_in_l xor fl_b1;
 
fl_out <= fl_b2 & fl_a2;
 
--FL^-1 function
fli_in_l <= reg_fli_in(0 to 31);
fli_in_r <= reg_fli_in(32 to 63);
 
fli_ke128 <= k(fli_ke128_offset+fli_ke128_shift to fli_ke128_offset+127) &
k(fli_ke128_offset to fli_ke128_offset+fli_ke128_shift-1);
fli_kd128 <= k(fli_kd128_offset+fli_kd128_shift to fli_kd128_offset+127) &
k(fli_kd128_offset to fli_kd128_offset+fli_kd128_shift-1);
fli_ke256 <= k(fli_ke256_offset+fli_ke256_shift to fli_ke256_offset+127) &
k(fli_ke256_offset to fli_ke256_offset+fli_ke256_shift-1);
fli_kd256 <= k(fli_kd256_offset+fli_kd256_shift to fli_kd256_offset+127) &
k(fli_kd256_offset to fli_kd256_offset+fli_kd256_shift-1);
fli_k_l <= fli_ke128(64 to 95) when dec='0' and k_len(0)='0' else
fli_kd128(0 to 31) when dec='1' and k_len(0)='0' else
fli_ke256(64 to 95) when dec='0' and k_len(0)='1' else
fli_kd256(0 to 31);
fli_k_r <= fli_ke128(96 to 127) when dec='0' and k_len(0)='0' else
fli_kd128(32 to 63) when dec='1' and k_len(0)='0' else
fli_ke256(96 to 127) when dec='0' and k_len(0)='1' else
fli_kd256(32 to 63);
 
fli_a1 <= fli_in_r or fli_k_r;
fli_a2 <= fli_in_l xor fli_a1;
 
fli_b1 <= fli_a2 and fli_k_l;
fli_b2 <= (fli_b1(1 to 31) & fli_b1(0)) xor fli_in_r;
 
fli_out <= fli_a2 & fli_b2;
 
end RTL;
/camellia-vhdl/trunk/pipelining/sbox3.vhd
0,0 → 1,72
 
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 09/14/2007
-- Last Update: 04/09/2008
-- Project Name: camellia-vhdl
-- Description: Dual-port SBOX3
--
-- Copyright (C) 2007 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
 
 
entity SBOX3 is
port (
clk : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(0 to 7);
addrb : IN STD_LOGIC_VECTOR(0 to 7);
douta : OUT STD_LOGIC_VECTOR(0 to 7);
doutb : OUT STD_LOGIC_VECTOR(0 to 7)
);
end SBOX3;
 
architecture RTL of SBOX3 is
 
component SBOX1 is
port (
clk : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(0 to 7);
addrb : IN STD_LOGIC_VECTOR(0 to 7);
douta : OUT STD_LOGIC_VECTOR(0 to 7);
doutb : OUT STD_LOGIC_VECTOR(0 to 7)
);
end component;
 
-- SBOX1 signals
signal s1_addra : STD_LOGIC_VECTOR(0 to 7);
signal s1_addrb : STD_LOGIC_VECTOR(0 to 7);
signal s1_clk : STD_LOGIC;
signal s1_douta : STD_LOGIC_VECTOR(0 to 7);
signal s1_doutb : STD_LOGIC_VECTOR(0 to 7);
 
begin
 
S1 : SBOX1
port map(s1_clk, s1_addra, s1_addrb, s1_douta, s1_doutb);
 
s1_clk <= clk;
s1_addra <= addra;
s1_addrb <= addrb;
 
douta <= s1_douta(7) & s1_douta(0 to 6);
doutb <= s1_doutb(7) & s1_doutb(0 to 6);
 
end RTL;
/camellia-vhdl/trunk/pipelining/f_tb.vhd
0,0 → 1,87
 
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 09/14/2007
-- Last Update: 09/25/2007
-- Project Name: camellia-vhdl
-- Description: VHDL Test Bench for module F
--
-- Copyright (C) 2007 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
 
entity f_tb is
end f_tb;
 
ARCHITECTURE behavior of f_tb is
 
-- Component Declaration for the Unit Under Test (UUT)
component F
port (
reset : in STD_LOGIC;
clk : in STD_LOGIC;
x : in STD_LOGIC_VECTOR (0 to 63);
k : in STD_LOGIC_VECTOR (0 to 63);
z : out STD_LOGIC_VECTOR (0 to 63)
);
end component;
 
--Inputs
signal reset : STD_LOGIC;
signal clk : STD_LOGIC;
signal x : STD_LOGIC_VECTOR(0 to 63) := (others=>'0');
signal k : STD_LOGIC_VECTOR(0 to 63) := (others=>'0');
 
--Outputs
signal z : STD_LOGIC_VECTOR(0 to 63);
 
begin
 
-- Instantiate the Unit Under Test (UUT)
uut: F port map(
reset => reset,
clk => clk,
x => x,
k => k,
z => z
);
 
tb : process
begin
reset <= '1';
wait for 10 ns;
reset <= '0';
x <= X"abcdef1234567890";
k <= X"0987654321abcdef";
wait for 30 ns;
x <= X"0000000000000000";
k <= X"0000000000000000";
wait;
end process;
 
ck : process
begin
clk <= '0';
wait for 15 ns;
clk <= '1';
wait for 15 ns;
end process;
 
end;
/camellia-vhdl/trunk/looping/control.vhd
0,0 → 1,821
 
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 01/31/2008
-- Last Update: 03/28/2008
-- Project Name: camellia-vhdl
-- Description: Control unit and key handling
--
-- Copyright (C) 2008 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
 
entity control is
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (0 to 127);
enc_dec : in STD_LOGIC;
data_rdy : in STD_LOGIC;
data_acq : out STD_LOGIC;
key_in : in STD_LOGIC_VECTOR (0 to 255);
k_len : in STD_LOGIC_VECTOR (0 to 1);
key_rdy : in STD_LOGIC;
key_acq : out STD_LOGIC;
data_to : out STD_LOGIC_VECTOR (0 to 127); -- data to datapath
output_rdy : out STD_LOGIC;
k1 : out STD_LOGIC_VECTOR (0 to 63);
k2 : out STD_LOGIC_VECTOR (0 to 63);
newdata : out STD_LOGIC;
sel : out STD_LOGIC;
pre_xor : out STD_LOGIC_VECTOR (0 to 127);
post_xor : out STD_LOGIC_VECTOR (0 to 127);
data_from : in STD_LOGIC_VECTOR (0 to 127) -- data from datapath
);
end control;
 
architecture RTL of control is
 
type STATUS is (KEYa, KEYb, KEYc, KEYd, KEYe, KEYf,
SIX1a, SIX1b, SIX1c, SIX1d, SIX1e, SIX1f,
FL1,
SIX2a, SIX2b, SIX2c, SIX2d, SIX2e, SIX2f,
FL2,
SIX3a, SIX3b, SIX3c, SIX3d, SIX3e, SIX3f,
FL3,
SIX4a, SIX4b, SIX4c, SIX4d, SIX4e, SIX4f,
WT
);
signal PS, NS : STATUS;
type K1_TYPE is (SIG1, SIG2, SIG3, SIG4, SIG5, SIG6,
KL_L, KL_R, KR_L, KR_R, KA_L, KA_R, KB_L, KB_R);
signal k1_sel : K1_TYPE;
type K2_TYPE is (KL_L, KL_R, KR_L, KR_R, KA_L, KA_R, KB_L, KB_R);
signal k2_sel : K2_TYPE;
type POSTXOR_TYPE is (KL, KA, KB, ZERO);
signal postxor_sel : POSTXOR_TYPE;
type PREXOR_TYPE is (KL, KR, KA, KB, ZERO);
signal prexor_sel : PREXOR_TYPE;
 
-- keys
signal reg_kl : STD_LOGIC_VECTOR (0 to 127);
signal reg_kr : STD_LOGIC_VECTOR (0 to 127);
signal reg_ka : STD_LOGIC_VECTOR (0 to 127);
signal reg_kb : STD_LOGIC_VECTOR (0 to 127);
--keys shifted each step
signal reg_kl_s : STD_LOGIC_VECTOR (0 to 127);
signal reg_kr_s : STD_LOGIC_VECTOR (0 to 127);
signal reg_ka_s : STD_LOGIC_VECTOR (0 to 127);
signal reg_kb_s : STD_LOGIC_VECTOR (0 to 127);
signal reg_k_len : STD_LOGIC_VECTOR (0 to 1);
signal reg_enc_dec : STD_LOGIC;
 
-- input constant
constant KLEN_128 : STD_LOGIC_VECTOR (0 to 1) := "00";
constant KLEN_192 : STD_LOGIC_VECTOR (0 to 1) := "01";
constant KLEN_256 : STD_LOGIC_VECTOR (0 to 1) := "10";
constant ENC : STD_LOGIC := '0';
constant DEC : STD_LOGIC := '1';
constant SEL_F : STD_LOGIC := '0';
constant SEL_FL : STD_LOGIC := '1';
 
-- constant keys
constant sigma1 : STD_LOGIC_VECTOR (0 to 63) := X"A09E667F3BCC908B";
constant sigma2 : STD_LOGIC_VECTOR (0 to 63) := X"B67AE8584CAA73B2";
constant sigma3 : STD_LOGIC_VECTOR (0 to 63) := X"C6EF372FE94F82BE";
constant sigma4 : STD_LOGIC_VECTOR (0 to 63) := X"54FF53A5F1D36F1C";
constant sigma5 : STD_LOGIC_VECTOR (0 to 63) := X"10E527FADE682D1D";
constant sigma6 : STD_LOGIC_VECTOR (0 to 63) := X"B05688C2B3E6C1FD";
 
begin
 
with k1_sel select
k1 <= sigma1 when SIG1,
sigma2 when SIG2,
sigma3 when SIG3,
sigma4 when SIG4,
sigma5 when SIG5,
sigma6 when SIG6,
reg_kl_s(0 to 63) when KL_L,
reg_kl_s(64 to 127) when KL_R,
reg_kr_s(0 to 63) when KR_L,
reg_kr_s(64 to 127) when KR_R,
reg_ka_s(0 to 63) when KA_L,
reg_ka_s(64 to 127) when KA_R,
reg_kb_s(0 to 63) when KB_L,
reg_kb_s(64 to 127) when others;
with k2_sel select
k2 <= reg_kl_s(0 to 63) when KL_L,
reg_kl_s(64 to 127) when KL_R,
reg_kr_s(0 to 63) when KR_L,
reg_kr_s(64 to 127) when KR_R,
reg_ka_s(0 to 63) when KA_L,
reg_ka_s(64 to 127) when KA_R,
reg_kb_s(0 to 63) when KB_L,
reg_kb_s(64 to 127) when others;
with postxor_sel select
post_xor <= reg_kl_s(64 to 127) & reg_kl_s(0 to 63) when KL,
reg_ka_s(64 to 127) & reg_ka_s(0 to 63) when KA,
reg_kb_s(64 to 127) & reg_kb_s(0 to 63) when KB,
(others=>'0') when others;
with prexor_sel select
pre_xor <= reg_kl_s when KL,
reg_kr_s when KR,
reg_ka_s when KA,
reg_kb_s when KB,
(others=>'0') when others;
 
REGISTERS_UPDATE : process(reset, clk)
variable coming_from_key : STD_LOGIC;
begin
if (reset = '1') then
reg_kl <= (others=>'0');
reg_kr <= (others=>'0');
reg_ka <= (others=>'0');
reg_kb <= (others=>'0');
reg_kl_s <= (others=>'0');
reg_kr_s <= (others=>'0');
reg_ka_s <= (others=>'0');
reg_kb_s <= (others=>'0');
reg_enc_dec <= '0';
reg_k_len <= (others=>'0');
output_rdy <= '0';
coming_from_key := '0';
else
if (clk'event and clk = '1') then
case PS is
when KEYa =>
coming_from_key := '1';
reg_kl <= key_in(0 to 127);
reg_kl_s <= key_in(0 to 127);
reg_k_len <= k_len;
case k_len is
when KLEN_192 =>
reg_kr <= key_in(128 to 191) & not (key_in(128 to 191));
reg_kr_s <= key_in(128 to 191) & not (key_in(128 to 191));
when KLEN_256 =>
reg_kr <= key_in(128 to 255);
reg_kr_s <= key_in(128 to 255);
when others =>
reg_kr <= (others=>'0');
reg_kr_s <= (others=>'0');
end case;
k1_sel <= SIG1;
when KEYb =>
k1_sel <= SIG2;
when KEYc =>
k1_sel <= SIG3;
when KEYd =>
k1_sel <= SIG4;
when KEYe =>
reg_ka <= data_from;
reg_ka_s <= data_from;
k1_sel <= SIG5;
when KEYf =>
k1_sel <= SIG6;
when SIX1a =>
if (enc_dec = ENC) then
if (coming_from_key = '1') then
if (reg_k_len = KLEN_128) then
reg_ka <= data_from;
reg_ka_s <= data_from;
else
reg_kb <= data_from;
reg_kb_s <= data_from;
end if;
else
reg_ka_s <= reg_ka;
reg_kb_s <= reg_kb;
reg_kl_s <= reg_kl;
reg_kr_s <= reg_kr;
end if;
if (reg_k_len = KLEN_128) then
k1_sel <= KA_L;
else
k1_sel <= KB_L;
end if;
else -- DEC
if (coming_from_key = '1') then
if (reg_k_len = KLEN_128) then
reg_ka <= data_from;
reg_ka_s <= data_from(111 to 127) & data_from(0 to 110); -- >>> 17
else
reg_kb <= data_from;
reg_kb_s <= data_from(111 to 127) & data_from(0 to 110); -- >>> 17
reg_ka_s <= reg_ka_s(111 to 127) & reg_ka_s(0 to 110); -- >>> 17
reg_kr_s <= reg_kr_s(111 to 127) & reg_kr_s(0 to 110); -- >>> 17
end if;
reg_kl_s <= reg_kl_s(111 to 127) & reg_kl_s(0 to 110); -- >>> 17
else
reg_ka_s <= reg_ka(111 to 127) & reg_ka(0 to 110); -- >>> 17
reg_kb_s <= reg_kb(111 to 127) & reg_kb(0 to 110); -- >>> 17
reg_kl_s <= key_in(111 to 127) & key_in(0 to 110); --kl >>> 17
reg_kr_s <= reg_kr(111 to 127) & reg_kr(0 to 110); -- >>> 17
end if;
k1_sel <= KL_R;
end if;
reg_enc_dec <= enc_dec;
when SIX1b =>
coming_from_key := '0';
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
k1_sel <= KA_R;
else
k1_sel <= KB_R;
end if;
else -- DEC
k1_sel <= KL_L; -- for each value of reg_k_len
end if;
when SIX1c =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
k1_sel <= KL_L;
reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
else
k1_sel <= KR_L;
reg_kr_s <= reg_kr_s(15 to 127) & reg_kr_s(0 to 14); -- <<< 15
end if;
else -- DEC
reg_ka_s <= reg_ka_s(111 to 127) & reg_ka_s(0 to 110); -- >>> 17
k1_sel <= KA_R; -- for each value of reg_k_len
end if;
when SIX1d =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
k1_sel <= KL_R;
else
k1_sel <= KR_R;
end if;
else -- DEC
k1_sel <= KA_L; -- for each value of reg_k_len
end if;
when SIX1e =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
else
reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
end if;
k1_sel <= KA_L;
else -- DEC
if (reg_k_len = KLEN_128) then
reg_kl_s <= reg_kl_s(111 to 127) & reg_kl_s(0 to 110); -- >>> 17
k1_sel <= KL_R;
else
reg_kr_s <= reg_kr_s(111 to 127) & reg_kr_s(0 to 110); -- >>> 17
k1_sel <= KR_R;
end if;
end if;
when SIX1f =>
if (reg_enc_dec = ENC) then
k1_sel <= KA_R;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KL_L;
else
k1_sel <= KR_L;
end if;
end if;
when FL1 =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
k1_sel <= KA_L;
k2_sel <= KA_R;
reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
else
k1_sel <= KR_L;
k2_sel <= KR_R;
reg_kb_s <= reg_kb_s(15 to 127) & reg_kb_s(0 to 14); -- <<< 15
reg_kr_s <= reg_kr_s(15 to 127) & reg_kr_s(0 to 14); -- <<< 15
end if;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KL_R;
k2_sel <= KL_L;
else
k1_sel <= KA_R;
k2_sel <= KA_L;
end if;
reg_ka_s <= reg_ka_s(111 to 127) & reg_ka_s(0 to 110); -- >>> 17
reg_kl_s <= reg_kl_s(111 to 127) & reg_kl_s(0 to 110); -- >>> 17
end if;
when SIX2a =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
k1_sel <= KL_L;
reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
else
k1_sel <= KB_L;
reg_kb_s <= reg_kb_s(15 to 127) & reg_kb_s(0 to 14); -- <<< 15
reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
end if;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KA_R;
reg_ka_s <= reg_ka_s(111 to 127) & reg_ka_s(0 to 110); -- >>> 17
else
k1_sel <= KL_R;
reg_kb_s <= reg_kb_s(111 to 127) & reg_kb_s(0 to 110); -- >>> 17
reg_kl_s <= reg_kl_s(111 to 127) & reg_kl_s(0 to 110); -- >>> 17
end if;
end if;
when SIX2b =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
k1_sel <= KL_R;
else
k1_sel <= KB_R;
reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
end if;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KA_L;
else
k1_sel <= KL_L;
reg_kb_s <= reg_kb_s(111 to 127) & reg_kb_s(0 to 110); -- >>> 17
end if;
end if;
when SIX2c =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
k1_sel <= KA_L;
reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
else
k1_sel <= KL_L;
reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
end if;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KL_R;
reg_kl_s <= reg_kl_s(111 to 127) & reg_kl_s(0 to 110); -- >>> 17
else
k1_sel <= KB_R;
reg_kb_s <= reg_kb_s(111 to 127) & reg_kb_s(0 to 110); -- >>> 17
end if;
end if;
when SIX2d =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
else
reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
end if;
k1_sel <= KL_R;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KA_L;
reg_ka_s <= reg_ka_s(113 to 127) & reg_ka_s(0 to 112); -- >>> 15
else
k1_sel <= KB_L;
reg_kr_s <= reg_kr_s(111 to 127) & reg_kr_s(0 to 110); -- >>> 17
end if;
end if;
when SIX2e =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
else
reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
end if;
k1_sel <= KA_L;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KL_R;
reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15
else
k1_sel <= KR_R;
reg_kr_s <= reg_kr_s(111 to 127) & reg_kr_s(0 to 110); -- >>> 17
end if;
end if;
when SIX2f =>
if (reg_enc_dec = ENC) then
k1_sel <= KA_R;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KL_L;
else
k1_sel <= KR_L;
end if;
end if;
when FL2 =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
reg_kl_s <= reg_kl_s(17 to 127) & reg_kl_s(0 to 16); -- <<< 17
else
reg_kr_s <= reg_kr_s(15 to 127) & reg_kr_s(0 to 14); -- <<< 15
reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
end if;
k1_sel <= KL_L;
k2_sel <= KL_R;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KA_R;
k2_sel <= KA_L;
reg_ka_s <= reg_ka_s(113 to 127) & reg_ka_s(0 to 112); -- >>> 15
else
k1_sel <= KL_R;
k2_sel <= KL_L;
reg_ka_s <= reg_ka_s(111 to 127) & reg_ka_s(0 to 110); -- >>> 17
reg_kl_s <= reg_kl_s(111 to 127) & reg_kl_s(0 to 110); -- >>> 17
end if;
end if;
when SIX3a =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
k1_sel <= KL_L;
reg_kl_s <= reg_kl_s(17 to 127) & reg_kl_s(0 to 16); -- <<< 17
else
k1_sel <= KR_L;
reg_kr_s <= reg_kr_s(15 to 127) & reg_kr_s(0 to 14); -- <<< 15
end if;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KA_R;
else
k1_sel <= KA_R;
end if;
reg_ka_s <= reg_ka_s(113 to 127) & reg_ka_s(0 to 112); -- >>> 15
end if;
when SIX3b =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
k1_sel <= KL_R;
reg_ka_s <= reg_ka_s(17 to 127) & reg_ka_s(0 to 16); -- <<< 17
else
k1_sel <= KR_R;
reg_kb_s <= reg_kb_s(15 to 127) & reg_kb_s(0 to 14); -- <<< 15
end if;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KA_L;
reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15
else
k1_sel <= KA_L;
end if;
end if;
when SIX3c =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
k1_sel <= KA_L;
reg_ka_s <= reg_ka_s(17 to 127) & reg_ka_s(0 to 16); -- <<< 17
else
k1_sel <= KB_L;
reg_kb_s <= reg_kb_s(15 to 127) & reg_kb_s(0 to 14); -- <<< 15
end if;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KL_R;
else
k1_sel <= KL_R;
end if;
reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15
end if;
when SIX3d =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
k1_sel <= KA_R;
else
k1_sel <= KB_R;
end if;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KL_L;
else
k1_sel <= KL_L;
reg_kb_s <= reg_kb_s(113 to 127) & reg_kb_s(0 to 112); -- >>> 15
end if;
end if;
when SIX3e =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
reg_kl_s <= reg_kl_s(17 to 127) & reg_kl_s(0 to 16); -- <<< 17
else
reg_kl_s <= reg_kl_s(17 to 127) & reg_kl_s(0 to 16); -- <<< 17
end if;
k1_sel <= KL_L;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KA_R;
reg_ka_s <= reg_ka_s(113 to 127) & reg_ka_s(0 to 112); -- >>> 15
else
k1_sel <= KB_R;
reg_kb_s <= reg_kb_s(113 to 127) & reg_kb_s(0 to 112); -- >>> 15
end if;
end if;
when SIX3f =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
reg_ka_s <= reg_ka_s(17 to 127) & reg_ka_s(0 to 16); -- <<< 17
else
reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
end if;
k1_sel <= KL_R;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KA_L;
reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15
else
k1_sel <= KB_L;
reg_kr_s <= reg_kr_s(113 to 127) & reg_kr_s(0 to 112); -- >>> 15
end if;
end if;
when FL3 =>
if (reg_enc_dec = ENC) then
k1_sel <= KA_L;
k2_sel <= KA_R;
reg_kr_s <= reg_kr_s(17 to 127) & reg_kr_s(0 to 16); -- <<< 17
reg_ka_s <= reg_ka_s(17 to 127) & reg_ka_s(0 to 16); -- <<< 17
else -- DEC
k1_sel <= KR_R;
k2_sel <= KR_L;
reg_ka_s <= reg_ka_s(113 to 127) & reg_ka_s(0 to 112); -- >>> 15
reg_kr_s <= reg_kr_s(113 to 127) & reg_kr_s(0 to 112); -- >>> 15
end if;
when SIX4a =>
if (reg_enc_dec = ENC) then
k1_sel <= KR_L;
reg_kr_s <= reg_kr_s(17 to 127) & reg_kr_s(0 to 16); -- <<< 17
else -- DEC
k1_sel <= KA_R;
reg_ka_s <= reg_ka_s(113 to 127) & reg_ka_s(0 to 112); -- >>> 15
end if;
when SIX4b =>
if (reg_enc_dec = ENC) then
k1_sel <= KR_R;
else -- DEC
k1_sel <= KA_L;
end if;
when SIX4c =>
if (reg_enc_dec = ENC) then
k1_sel <= KA_L;
reg_ka_s <= reg_ka_s(17 to 127) & reg_ka_s(0 to 16); -- <<< 17
else -- DEC
k1_sel <= KR_R;
reg_kr_s <= reg_kr_s(113 to 127) & reg_kr_s(0 to 112); -- >>> 15
end if;
when SIX4d =>
if (reg_enc_dec = ENC) then
k1_sel <= KA_R;
reg_kl_s <= reg_kl_s(17 to 127) & reg_kl_s(0 to 16); -- <<< 17
reg_kb_s <= reg_kb_s(17 to 127) & reg_kb_s(0 to 16); -- <<< 17
else -- DEC
k1_sel <= KR_L;
reg_kb_s <= reg_kb_s(113 to 127) & reg_kb_s(0 to 112); -- >>> 15
reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15
end if;
when SIX4e =>
if (reg_enc_dec = ENC) then
k1_sel <= KL_L;
reg_kl_s <= reg_kl_s(17 to 127) & reg_kl_s(0 to 16); -- <<< 17
reg_kb_s <= reg_kb_s(17 to 127) & reg_kb_s(0 to 16); -- <<< 17
else -- DEC
k1_sel <= KB_R;
reg_kb_s <= reg_kb_s(113 to 127) & reg_kb_s(0 to 112); -- >>> 15
reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15
end if;
when SIX4f =>
if (reg_enc_dec = ENC) then
k1_sel <= KL_R;
reg_kb_s <= reg_kb_s(17 to 127) & reg_kb_s(0 to 16); -- <<< 17
else -- DEC
k1_sel <= KB_L;
reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15
end if;
when WT =>
-- do nothing
end case;
 
if (PS = KEYa) then
data_to <= key_in(0 to 127); --kl
else
data_to <= data_in;
end if;
 
case PS is
when KEYc =>
prexor_sel <= KL;
when KEYa | KEYe =>
prexor_sel <= KR;
when SIX1a =>
if (enc_dec = ENC) then
prexor_sel <= KL;
else
if (reg_k_len = KLEN_128) then
prexor_sel <= KA;
else
prexor_sel <= KB;
end if;
end if;
when others =>
prexor_sel <= ZERO;
end case;
 
case PS is
when SIX3f =>
if (reg_k_len = KLEN_128) then
if (reg_enc_dec = ENC) then
postxor_sel <= KA;
else
postxor_sel <= KL;
end if;
else
postxor_sel <= ZERO;
end if;
when SIX4f =>
if (reg_enc_dec = ENC) then
postxor_sel <= KB;
else
postxor_sel <= KL;
end if;
when others =>
postxor_sel <= ZERO;
end case;
 
if (PS = SIX1a or PS = KEYa) then
newdata <= '1';
else
newdata <= '0';
end if;
if ((PS = SIX3f and reg_k_len = KLEN_128) or PS = SIX4f) then
output_rdy <= '1';
else
output_rdy <= '0';
end if;
 
if (PS = FL1 or PS = FL2 or PS = FL3) then
sel <= SEL_FL;
else
sel <= SEL_F;
end if;
if (PS = KEYb) then
key_acq <= '1';
else
key_acq <= '0';
end if;
if (PS = SIX1b) then
data_acq <= '1';
else
data_acq <= '0';
end if;
end if;
end if;
end process;
 
STATE_UPDATE: process (reset, clk)
begin
 
if (reset = '1') then
PS <= KEYa;
else
if (clk'event and clk = '1') then
PS <= NS;
end if;
end if;
end process;
NEXT_STATE: process (PS, data_rdy, key_rdy)
begin
case PS is
when KEYa =>
if(key_rdy = '1') then
NS <= KEYb;
else
NS <= KEYa;
end if;
when KEYb =>
NS <= KEYc;
when KEYc =>
NS <= KEYd;
when KEYd =>
if (reg_k_len = KLEN_128) then
NS <= SIX1a;
else
NS <= KEYe;
end if;
when KEYe =>
NS <= KEYf;
when KEYf =>
NS <= SIX1a;
when SIX1a =>
if(data_rdy = '1') then
NS <= SIX1b;
else
NS <= SIX1a;
end if;
when SIX1b =>
NS <= SIX1c;
when SIX1c =>
NS <= SIX1d;
when SIX1d =>
NS <= SIX1e;
when SIX1e =>
NS <= SIX1f;
when SIX1f =>
NS <= FL1;
when FL1 =>
NS <= SIX2a;
when SIX2a =>
NS <= SIX2b;
when SIX2b =>
NS <= SIX2c;
when SIX2c =>
NS <= SIX2d;
when SIX2d =>
NS <= SIX2e;
when SIX2e =>
NS <= SIX2f;
when SIX2f =>
NS <= FL2;
when FL2 =>
NS <= SIX3a;
when SIX3a =>
NS <= SIX3b;
when SIX3b =>
NS <= SIX3c;
when SIX3c =>
NS <= SIX3d;
when SIX3d =>
NS <= SIX3e;
when SIX3e =>
NS <= SIX3f;
when SIX3f =>
if (reg_k_len = KLEN_128) then
if (key_rdy = '1') then
NS <= KEYa;
else
if (data_rdy = '1') then
NS <= SIX1a;
else
NS <= WT;
end if;
end if;
else
NS <= FL3;
end if;
when FL3 =>
NS <= SIX4a;
when SIX4a =>
NS <= SIX4b;
when SIX4b =>
NS <= SIX4c;
when SIX4c =>
NS <= SIX4d;
when SIX4d =>
NS <= SIX4e;
when SIX4e =>
NS <= SIX4f;
when SIX4f =>
if (key_rdy = '1') then
NS <= KEYa;
else
if (data_rdy = '1') then
NS <= SIX1a;
else
NS <= WT;
end if;
end if;
when WT =>
if (key_rdy = '1') then
NS <= KEYa;
else
if (data_rdy = '1') then
NS <= SIX1a;
else
NS <= WT;
end if;
end if;
end case;
end process;
 
end RTL;
/camellia-vhdl/trunk/looping/camellia_if.vhd
0,0 → 1,224
 
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 03/25/2008
-- Last Update: 04/02/2008
-- Project Name: camellia-vhdl
-- Description: Interface to the Camellia core
--
-- Copyright (C) 2008 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
 
entity CAMELLIA_IF is
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (0 to 15);
enc_dec : in STD_LOGIC;
en_data : in STD_LOGIC;
next_data : out STD_LOGIC;
key_in : in STD_LOGIC_VECTOR (0 to 15);
k_len : in STD_LOGIC_VECTOR (0 to 1);
en_key : in STD_LOGIC;
next_key : out STD_LOGIC;
data_out : out STD_LOGIC_VECTOR (0 to 15);
out_rdy : out STD_LOGIC
);
end CAMELLIA_IF;
 
architecture RTL of CAMELLIA_IF is
 
component CAMELLIA is
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (0 to 127);
enc_dec : in STD_LOGIC;
data_rdy : in STD_LOGIC;
data_acq : out STD_LOGIC;
key : in STD_LOGIC_VECTOR (0 to 255);
k_len : in STD_LOGIC_VECTOR (0 to 1);
key_rdy : in STD_LOGIC;
key_acq : out STD_LOGIC;
data_out : out STD_LOGIC_VECTOR (0 to 127);
output_rdy : out STD_LOGIC
);
end component;
 
signal s_clk : STD_LOGIC;
signal s_reset : STD_LOGIC;
signal s_data_in : STD_LOGIC_VECTOR (0 to 127);
signal s_enc_dec : STD_LOGIC;
signal s_data_rdy : STD_LOGIC;
signal s_data_acq : STD_LOGIC;
signal s_key : STD_LOGIC_VECTOR (0 to 255);
signal s_k_len : STD_LOGIC_VECTOR (0 to 1);
signal s_key_rdy : STD_LOGIC;
signal s_key_acq : STD_LOGIC;
signal s_data_out : STD_LOGIC_VECTOR (0 to 127);
signal s_output_rdy : STD_LOGIC;
signal key_count : STD_LOGIC_VECTOR (3 downto 0);
signal din_count : STD_LOGIC_VECTOR (2 downto 0);
signal dout_count : STD_LOGIC_VECTOR (2 downto 0);
signal reg_key : STD_LOGIC_VECTOR (0 to 255);
signal reg_din : STD_LOGIC_VECTOR (0 to 127);
signal reg_dout : STD_LOGIC_VECTOR (0 to 127);
signal reg_next_data : STD_LOGIC;
signal reg_next_key : STD_LOGIC;
signal int_out_rdy : STD_LOGIC;
-- input constant
constant KLEN_128 : STD_LOGIC_VECTOR (0 to 1) := "00";
constant KLEN_192 : STD_LOGIC_VECTOR (0 to 1) := "01";
constant KLEN_256 : STD_LOGIC_VECTOR (0 to 1) := "10";
 
begin
 
-- S-FUNCTION
core : CAMELLIA
port map(s_clk, s_reset, s_data_in, s_enc_dec, s_data_rdy,
s_data_acq, s_key, s_k_len, s_key_rdy, s_key_acq,
s_data_out, s_output_rdy);
 
KEY_PROC: process (reset, clk)
begin
if (reset = '1') then
reg_next_key <= '1';
key_count <= "0000";
reg_key <= (others=>'0');
s_key_rdy <= '0';
elsif (clk'event and clk = '1') then
if (en_key = '1') then
reg_next_key <= '0';
key_count <= key_count + "0001";
case k_len is
when KLEN_128 =>
reg_key <= reg_key(16 to 127) & key_in & X"00000000000000000000000000000000";
when KLEN_192 =>
reg_key <= reg_key(16 to 191) & key_in & X"0000000000000000";
when others =>
reg_key <= reg_key(16 to 255) & key_in;
end case;
else
key_count <= "0000";
if (s_key_acq = '1') then
reg_next_key <= '1';
else
reg_next_key <= reg_next_key;
end if;
end if;
if ((key_count = "0111" and k_len = KLEN_128) or
(key_count = "1100" and k_len = KLEN_192) or
key_count = "1111") then
s_key_rdy <= '1';
elsif (s_key_acq = '1') then
s_key_rdy <= '0';
else
s_key_rdy <= s_key_rdy;
end if;
end if;
end process;
DATA_IN_PROC: process (reset, clk)
begin
if (reset = '1') then
reg_next_data <= '1';
din_count <= "000";
reg_din <= (others=>'0');
s_data_rdy <= '0';
elsif (clk'event and clk = '1') then
if (en_data = '1') then
reg_next_data <= '0';
din_count <= din_count + "001";
reg_din <= reg_din(16 to 127) & data_in;
else
din_count <= "000";
if (s_data_acq = '1') then
reg_next_data <= '1';
else
reg_next_data <= reg_next_data;
end if;
end if;
if (din_count = "111") then
s_data_rdy <= '1';
elsif (s_data_acq = '1') then
s_data_rdy <= '0';
else
s_data_rdy <= s_data_rdy;
end if;
end if;
end process;
 
DATA_OUT_PROC: process (reset, clk)
begin
if (reset = '1') then
dout_count <= "000";
int_out_rdy <= '0';
reg_dout <= (others=>'0');
elsif (clk'event and clk = '1') then
if (int_out_rdy = '1') then
if (dout_count /= "111") then
dout_count <= dout_count + "001";
reg_dout <= reg_dout(16 to 127) & X"0000"; -- <<< 16
else
int_out_rdy <= '0';
end if;
else
if (s_output_rdy = '1') then
dout_count <= "000";
reg_dout <= s_data_out;
int_out_rdy<= '1';
end if;
end if;
end if;
end process;
 
s_clk <= clk;
s_reset <= reset;
s_data_in <= reg_din;
s_enc_dec <= enc_dec;
s_key <= reg_key;
s_k_len <= k_len;
data_out <= reg_dout(0 to 15);
out_rdy <= int_out_rdy;
next_key <= reg_next_key;
next_data <= reg_next_data;
end RTL;
 
/camellia-vhdl/trunk/looping/camellia.vhd
0,0 → 1,168
 
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 02/01/2008
-- Last Update: 03/28/2008
-- Project Name: camellia-vhdl
-- Description: Looping version of Camellia
--
-- Copyright (C) 2008 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
 
entity camellia is
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (0 to 127);
enc_dec : in STD_LOGIC;
data_rdy : in STD_LOGIC;
data_acq : out STD_LOGIC;
key : in STD_LOGIC_VECTOR (0 to 255);
k_len : in STD_LOGIC_VECTOR (0 to 1);
key_rdy : in STD_LOGIC;
key_acq : out STD_LOGIC;
data_out : out STD_LOGIC_VECTOR (0 to 127);
output_rdy : out STD_LOGIC
-- post-synthesis debug
);
end camellia;
 
architecture RTL of camellia is
signal s_clk : STD_LOGIC;
signal s_reset : STD_LOGIC;
signal s_data_in : STD_LOGIC_VECTOR (0 to 127);
signal s_enc_dec : STD_LOGIC;
signal s_data_rdy : STD_LOGIC;
signal s_data_acq : STD_LOGIC;
signal s_key_in : STD_LOGIC_VECTOR (0 to 255);
signal s_k_len : STD_LOGIC_VECTOR (0 to 1);
signal s_key_rdy : STD_LOGIC;
signal s_key_acq : STD_LOGIC;
signal s_data_to : STD_LOGIC_VECTOR (0 to 127);
signal s_output_rdy : STD_LOGIC;
signal s_k1 : STD_LOGIC_VECTOR (0 to 63);
signal s_k2 : STD_LOGIC_VECTOR (0 to 63);
signal s_newdata : STD_LOGIC;
signal s_sel : STD_LOGIC;
signal s_pre_xor : STD_LOGIC_VECTOR (0 to 127);
signal s_post_xor : STD_LOGIC_VECTOR (0 to 127);
signal s_data_from : STD_LOGIC_VECTOR (0 to 127);
 
component datapath is
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (0 to 127);
k1 : in STD_LOGIC_VECTOR (0 to 63);
k2 : in STD_LOGIC_VECTOR (0 to 63);
newdata : in STD_LOGIC;
sel : in STD_LOGIC;
pre_xor : in STD_LOGIC_VECTOR (0 to 127);
post_xor : in STD_LOGIC_VECTOR (0 to 127);
data_out : out STD_LOGIC_VECTOR (0 to 127)
);
end component;
 
component control is
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (0 to 127);
enc_dec : in STD_LOGIC;
data_rdy : in STD_LOGIC;
data_acq : out STD_LOGIC;
key_in : in STD_LOGIC_VECTOR (0 to 255);
k_len : in STD_LOGIC_VECTOR (0 to 1);
key_rdy : in STD_LOGIC;
key_acq : out STD_LOGIC;
data_to : out STD_LOGIC_VECTOR (0 to 127);
output_rdy : out STD_LOGIC;
k1 : out STD_LOGIC_VECTOR (0 to 63);
k2 : out STD_LOGIC_VECTOR (0 to 63);
newdata : out STD_LOGIC;
sel : out STD_LOGIC;
pre_xor : out STD_LOGIC_VECTOR (0 to 127);
post_xor : out STD_LOGIC_VECTOR (0 to 127);
data_from : in STD_LOGIC_VECTOR (0 to 127)
);
end component;
 
begin
 
DP : datapath
port map(
clk => s_clk,
reset => s_reset,
data_in => s_data_to,
k1 => s_k1,
k2 => s_k2,
newdata => s_newdata,
sel => s_sel,
pre_xor => s_pre_xor,
post_xor => s_post_xor,
data_out => s_data_from
);
 
CTRL : control
port map(
clk => s_clk,
reset => s_reset,
data_in => s_data_in,
enc_dec => s_enc_dec,
data_rdy => s_data_rdy,
data_acq => s_data_acq,
key_in => s_key_in,
k_len => s_k_len,
key_rdy => s_key_rdy,
key_acq => s_key_acq,
data_to => s_data_to,
output_rdy => s_output_rdy,
k1 => s_k1,
k2 => s_k2,
newdata => s_newdata,
sel => s_sel,
pre_xor => s_pre_xor,
post_xor => s_post_xor,
data_from => s_data_from
);
 
s_clk <= clk;
s_reset <= reset;
s_data_in <= data_in;
s_enc_dec <= enc_dec;
s_data_rdy <= data_rdy;
s_key_in <= key;
s_k_len <= k_len;
s_key_rdy <= key_rdy;
data_acq <= s_data_acq;
key_acq <= s_key_acq;
data_out <= s_data_from(64 to 127) & s_data_from(0 to 63);
output_rdy <= s_output_rdy;
 
end RTL;
/camellia-vhdl/trunk/looping/camellia_tb.vhd
0,0 → 1,127
 
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 02/19/2008
-- Last Update: 04/02/2008
-- Project Name: camellia-vhdl
-- Description: VHDL Test Bench for module camellia
--
-- Copyright (C) 2008 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
 
entity camellia_tb is
 
end camellia_tb;
 
architecture RTL of camellia_tb is
 
component camellia is
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (0 to 127);
enc_dec : in STD_LOGIC;
data_rdy : in STD_LOGIC;
data_acq : out STD_LOGIC;
key : in STD_LOGIC_VECTOR (0 to 255);
k_len : in STD_LOGIC_VECTOR (0 to 1);
key_rdy : in STD_LOGIC;
key_acq : out STD_LOGIC;
data_out : out STD_LOGIC_VECTOR (0 to 127);
output_rdy : out STD_LOGIC
);
end component;
 
signal clk : STD_LOGIC;
signal reset : STD_LOGIC;
signal data_in : STD_LOGIC_VECTOR (0 to 127);
signal enc_dec : STD_LOGIC;
signal data_rdy : STD_LOGIC;
signal data_acq : STD_LOGIC;
signal key : STD_LOGIC_VECTOR (0 to 255);
signal k_len : STD_LOGIC_VECTOR (0 to 1);
signal key_rdy : STD_LOGIC;
signal key_acq : STD_LOGIC;
signal data_out : STD_LOGIC_VECTOR (0 to 127);
signal output_rdy : STD_LOGIC;
 
-- constants
constant KLEN_128 : STD_LOGIC_VECTOR (0 to 1) := "00";
constant KLEN_192 : STD_LOGIC_VECTOR (0 to 1) := "01";
constant KLEN_256 : STD_LOGIC_VECTOR (0 to 1) := "10";
constant ENC : STD_LOGIC := '0';
constant DEC : STD_LOGIC := '1';
constant CLK_PERIOD : TIME := 100 ns;
 
begin
 
uut : camellia
port map(clk, reset, data_in, enc_dec, data_rdy, data_acq,
key, k_len, key_rdy, key_acq, data_out, output_rdy);
 
tb : process
begin
reset <= '1';
wait for 80 ns;
reset <= '0';
wait until clk = '1';
data_in <= X"0123456789abcdeffedcba9876543210";
enc_dec <= ENC;
data_rdy <= '1';
key <= X"0123456789abcdeffedcba987654321000112233445566778899aabbccddeeff";
k_len <= KLEN_128;
key_rdy <= '1';
wait until key_acq = '1';
key_rdy <= '0';
wait until data_acq = '1';
data_in <= X"67673138549669730857065648eabe43";
enc_dec <= DEC;
wait until data_acq = '1';
data_in <= X"0123456789abcdeffedcba9876543210";
enc_dec <= ENC;
data_rdy <= '1';
key <= X"0123456789abcdeffedcba987654321000112233445566778899aabbccddeeff";
k_len <= KLEN_192;
key_rdy <= '1';
wait until key_acq = '1';
key_rdy <= '0';
wait until data_acq = '1';
data_rdy <= '0';
wait;
end process;
 
clk_gen : process
begin
clk <= '0';
wait for CLK_PERIOD / 2;
clk <= '1';
wait for CLK_PERIOD / 2;
end process;
 
end RTL;
/camellia-vhdl/trunk/looping/camellia_tb.do
0,0 → 1,32
vcom -quiet sbox1.vhd
vcom -quiet sbox2.vhd
vcom -quiet sbox3.vhd
vcom -quiet sbox4.vhd
vcom -quiet f.vhd
vcom -quiet fl.vhd
vcom -quiet datapath.vhd
vcom -quiet control.vhd
vcom -quiet camellia.vhd
vcom -quiet camellia_tb.vhd
vsim camellia_tb
view wave
add wave -divider "camellia"
add wave -HEX -ports /uut/*
add wave -divider "control"
add wave -HEX -ports /uut/CTRL/*
add wave /uut/CTRL/PS
add wave -divider "keys"
add wave -HEX /uut/CTRL/reg_kl
add wave -HEX /uut/CTRL/reg_kr
add wave -HEX /uut/CTRL/reg_ka
add wave -HEX /uut/CTRL/reg_kb
add wave -HEX /uut/CTRL/reg_kl_s
add wave -HEX /uut/CTRL/reg_kr_s
add wave -HEX /uut/CTRL/reg_ka_s
add wave -HEX /uut/CTRL/reg_kb_s
add wave -divider "other regs"
add wave -HEX /uut/CTRL/reg_enc_dec
add wave -HEX /uut/CTRL/reg_k_len
add wave -divider "datapath"
add wave -HEX -ports /uut/DP/*
run 6 us
/camellia-vhdl/trunk/looping/sbox4.vhd
0,0 → 1,59
 
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 01/22/2008
-- Last Update: 02/19/2008
-- Project Name: camellia-vhdl
-- Description: Asynchronous SBOX4
--
-- Copyright (C) 2008 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
 
 
entity SBOX4 is
port (
data_in : IN STD_LOGIC_VECTOR(0 to 7);
data_out : OUT STD_LOGIC_VECTOR(0 to 7)
);
end SBOX4;
 
architecture RTL of SBOX4 is
 
component SBOX1 is
port (
data_in : IN STD_LOGIC_VECTOR(0 to 7);
data_out : OUT STD_LOGIC_VECTOR(0 to 7)
);
end component;
 
-- SBOX1 signals
signal s1_data_in : STD_LOGIC_VECTOR(0 to 7);
signal s1_data_out : STD_LOGIC_VECTOR(0 to 7);
 
begin
 
S1 : SBOX1
port map(s1_data_in, s1_data_out);
 
s1_data_in <= data_in(1 to 7) & data_in(0);
data_out <= s1_data_out;
 
end RTL;
/camellia-vhdl/trunk/looping/fl.vhd
0,0 → 1,73
 
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 01/22/2008
-- Last Update: 02/21/2008
-- Project Name: camellia-vhdl
-- Description: Asynchronous FL and FL^-1 functions
--
-- Copyright (C) 2008 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
 
 
entity FL is
port(
fl_in : in STD_LOGIC_VECTOR (0 to 63);
fli_in : in STD_LOGIC_VECTOR (0 to 63);
fl_k : in STD_LOGIC_VECTOR (0 to 63);
fli_k : in STD_LOGIC_VECTOR (0 to 63);
fl_out : out STD_LOGIC_VECTOR (0 to 63);
fli_out : out STD_LOGIC_VECTOR (0 to 63)
);
end FL;
 
architecture RTL of FL is
 
signal fl_a1 : STD_LOGIC_VECTOR (0 to 31);
signal fl_a2 : STD_LOGIC_VECTOR (0 to 31);
signal fl_b1 : STD_LOGIC_VECTOR (0 to 31);
signal fl_b2 : STD_LOGIC_VECTOR (0 to 31);
signal fli_a1 : STD_LOGIC_VECTOR (0 to 31);
signal fli_a2 : STD_LOGIC_VECTOR (0 to 31);
signal fli_b1 : STD_LOGIC_VECTOR (0 to 31);
signal fli_b2 : STD_LOGIC_VECTOR (0 to 31);
 
begin
 
--FL function
fl_a1 <= fl_in(0 to 31) and fl_k(0 to 31);
fl_a2 <= (fl_a1(1 to 31) & fl_a1(0)) xor fl_in(32 to 63);
 
fl_b1 <= fl_a2 or fl_k(32 to 63);
fl_b2 <= fl_in(0 to 31) xor fl_b1;
 
fl_out <= fl_b2 & fl_a2;
 
--FL^-1 function
fli_a1 <= fli_in(32 to 63) or fli_k(32 to 63);
fli_a2 <= fli_in(0 to 31) xor fli_a1;
 
fli_b1 <= fli_a2 and fli_k(0 to 31);
fli_b2 <= (fli_b1(1 to 31) & fli_b1(0)) xor fli_in(32 to 63);
 
fli_out <= fli_a2 & fli_b2;
 
end RTL;
/camellia-vhdl/trunk/looping/f.vhd
0,0 → 1,131
 
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 01/22/2008
-- Last Update: 01/22/2008
-- Project Name: camellia-vhdl
-- Description: Asynchronous F function
--
-- Copyright (C) 2008 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
 
entity F is
port (
x : in STD_LOGIC_VECTOR (0 to 63);
k : in STD_LOGIC_VECTOR (0 to 63);
z : out STD_LOGIC_VECTOR (0 to 63)
);
end F;
 
architecture RTL of F is
 
-- S-BOX
component SBOX1 is
port (
data_in : IN STD_LOGIC_VECTOR(0 to 7);
data_out : OUT STD_LOGIC_VECTOR(0 to 7)
);
end component;
component SBOX2 is
port (
data_in : IN STD_LOGIC_VECTOR(0 to 7);
data_out : OUT STD_LOGIC_VECTOR(0 to 7)
);
end component;
component SBOX3 is
port (
data_in : IN STD_LOGIC_VECTOR(0 to 7);
data_out : OUT STD_LOGIC_VECTOR(0 to 7)
);
end component;
component SBOX4 is
port (
data_in : IN STD_LOGIC_VECTOR(0 to 7);
data_out : OUT STD_LOGIC_VECTOR(0 to 7)
);
end component;
 
 
signal y : STD_LOGIC_VECTOR (0 to 63);
signal y1, y2, y3, y4, y5, y6, y7, y8 : STD_LOGIC_VECTOR (0 to 7);
 
signal so1, so2, so3, so4, so5, so6, so7, so8 : STD_LOGIC_VECTOR (0 to 7);
 
signal pa1, pa2, pa3, pa4, pa5, pa6, pa7, pa8 : STD_LOGIC_VECTOR (0 to 7);
 
signal pb1, pb2, pb3, pb4, pb5, pb6, pb7, pb8 : STD_LOGIC_VECTOR (0 to 7);
 
begin
 
y <= x xor k;
 
y8 <= y(56 to 63);
y7 <= y(48 to 55);
y6 <= y(40 to 47);
y5 <= y(32 to 39);
y4 <= y(24 to 31);
y3 <= y(16 to 23);
y2 <= y(8 to 15);
y1 <= y(0 to 7);
 
 
-- S-FUNCTION
S1a : SBOX1
port map(y8, so8);
S1b : SBOX1
port map(y1, so1);
S2a : SBOX2
port map(y5, so5);
S2b : SBOX2
port map(y2, so2);
S3a : SBOX3
port map(y6, so6);
S3b : SBOX3
port map(y3, so3);
S4a : SBOX4
port map(y7, so7);
S4b : SBOX4
port map(y4, so4);
 
-- P-FUNCTION
pa8 <= so8 xor pa2;
pa7 <= so7 xor pa1;
pa6 <= so6 xor pa4;
pa5 <= so5 xor pa3;
pa4 <= so4 xor so5;
pa3 <= so3 xor so8;
pa2 <= so2 xor so7;
pa1 <= so1 xor so6;
 
pb8 <= pa8 xor pb3;
pb7 <= pa7 xor pb2;
pb6 <= pa6 xor pb1;
pb5 <= pa5 xor pb4;
pb4 <= pa4 xor pa7;
pb3 <= pa3 xor pa6;
pb2 <= pa2 xor pa5;
pb1 <= pa1 xor pa8;
 
 
z <= pb5 & pb6 & pb7 & pb8 & pb1 & pb2 & pb3 & pb4;
 
 
end RTL;
/camellia-vhdl/trunk/looping/datapath.vhd
0,0 → 1,148
 
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 01/22/2008
-- Last Update: 03/04/2008
-- Project Name: camellia-vhdl
-- Description: Datapath
--
-- Copyright (C) 2008 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
 
entity datapath is
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (0 to 127);
k1 : in STD_LOGIC_VECTOR (0 to 63);
k2 : in STD_LOGIC_VECTOR (0 to 63);
newdata : in STD_LOGIC;
sel : in STD_LOGIC; -- 0 if F, 1 if FL
pre_xor : in STD_LOGIC_VECTOR (0 to 127);
post_xor : in STD_LOGIC_VECTOR (0 to 127);
data_out : out STD_LOGIC_VECTOR (0 to 127)
);
end datapath;
 
architecture RTL of datapath is
 
component F is
port (
x : in STD_LOGIC_VECTOR (0 to 63);
k : in STD_LOGIC_VECTOR (0 to 63);
z : out STD_LOGIC_VECTOR (0 to 63)
);
end component;
 
component FL is
port(
fl_in : in STD_LOGIC_VECTOR (0 to 63);
fli_in : in STD_LOGIC_VECTOR (0 to 63);
fl_k : in STD_LOGIC_VECTOR (0 to 63);
fli_k : in STD_LOGIC_VECTOR (0 to 63);
fl_out : out STD_LOGIC_VECTOR (0 to 63);
fli_out : out STD_LOGIC_VECTOR (0 to 63)
);
end component;
 
signal f_in : STD_LOGIC_VECTOR (0 to 63);
signal f_k : STD_LOGIC_VECTOR (0 to 63);
signal f_out : STD_LOGIC_VECTOR (0 to 63);
signal fl_in : STD_LOGIC_VECTOR (0 to 63);
signal fl_k : STD_LOGIC_VECTOR (0 to 63);
signal fl_out : STD_LOGIC_VECTOR (0 to 63);
signal fli_in : STD_LOGIC_VECTOR (0 to 63);
signal fli_k : STD_LOGIC_VECTOR (0 to 63);
signal fli_out : STD_LOGIC_VECTOR (0 to 63);
 
signal data_in_sx : STD_LOGIC_VECTOR (0 to 63);
signal data_in_dx : STD_LOGIC_VECTOR (0 to 63);
signal pre_xor_sx : STD_LOGIC_VECTOR (0 to 63);
signal pre_xor_dx : STD_LOGIC_VECTOR (0 to 63);
 
signal mux1 : STD_LOGIC_VECTOR (0 to 63);
signal mux1_pxor : STD_LOGIC_VECTOR (0 to 63);
signal mux2 : STD_LOGIC_VECTOR (0 to 63);
signal mux2_pxor : STD_LOGIC_VECTOR (0 to 63);
signal f_out_xor : STD_LOGIC_VECTOR (0 to 63);
 
signal reg_fl_out : STD_LOGIC_VECTOR (0 to 63);
signal reg_fli_out : STD_LOGIC_VECTOR (0 to 63);
signal reg_f_out_xor : STD_LOGIC_VECTOR (0 to 63);
signal reg_mux2_pxor : STD_LOGIC_VECTOR (0 to 63);
signal reg_sel : STD_LOGIC;
 
constant SEL_F : STD_LOGIC := '0';
constant SEL_FL : STD_LOGIC := '1';
 
begin
 
F1 : F
port map(f_in, f_k, f_out);
 
FL1 : FL
port map(fl_in, fli_in, fl_k, fli_k, fl_out, fli_out);
 
 
data_in_sx <= data_in(0 to 63);
data_in_dx <= data_in(64 to 127);
pre_xor_sx <= pre_xor(0 to 63);
pre_xor_dx <= pre_xor(64 to 127);
f_in <= mux2_pxor;
f_k <= k1;
fl_in <= reg_f_out_xor;
fl_k <= k1;
fli_in <= reg_mux2_pxor;
fli_k <= k2;
f_out_xor <= f_out xor mux1_pxor;
 
mux1 <= reg_fli_out when newdata='0' and reg_sel=SEL_FL else
reg_mux2_pxor when newdata='0' and reg_sel=SEL_F else
data_in_dx;
mux2 <= reg_fl_out when newdata='0' and reg_sel=SEL_FL else
reg_f_out_xor when newdata='0' and reg_sel=SEL_F else
data_in_sx;
 
mux1_pxor <= mux1 xor pre_xor_dx;
mux2_pxor <= mux2 xor pre_xor_sx;
 
data_out <= (f_out_xor & mux2_pxor) xor post_xor;
 
REGISTERS: process(clk, reset)
begin
 
if (reset = '1') then
reg_fl_out <= (others=>'0');
reg_fli_out <= (others=>'0');
reg_f_out_xor <= (others=>'0');
reg_mux2_pxor <= (others=>'0');
reg_sel <= SEL_F;
elsif (clk'event and clk='1') then
reg_fl_out <= fl_out;
reg_fli_out <= fli_out;
reg_f_out_xor <= f_out_xor;
reg_mux2_pxor <= mux2_pxor;
reg_sel <= sel;
end if;
 
end process;
 
end RTL;
/camellia-vhdl/trunk/looping/f_tb.vhd
0,0 → 1,71
 
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 01/22/2008
-- Last Update: 02/25/2008
-- Project Name: camellia-vhdl
-- Description: VHDL Test Bench for module F
--
-- Copyright (C) 2008 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
 
entity f_tb is
end f_tb;
 
ARCHITECTURE behavior of f_tb is
 
-- Component Declaration for the Unit Under Test (UUT)
component F
port (
x : in STD_LOGIC_VECTOR (0 to 63);
k : in STD_LOGIC_VECTOR (0 to 63);
z : out STD_LOGIC_VECTOR (0 to 63)
);
end component;
 
--Inputs
signal x : STD_LOGIC_VECTOR(0 to 63) := (others=>'0');
signal k : STD_LOGIC_VECTOR(0 to 63) := (others=>'0');
 
--Outputs
signal z : STD_LOGIC_VECTOR(0 to 63);
 
begin
 
-- Instantiate the Unit Under Test (UUT)
uut: F port map(
x => x,
k => k,
z => z
);
 
tb : process
begin
x <= X"0123456789abcdef";
k <= X"a09e667f3bcc908b";
wait for 10 ns;
x <= X"0000000000000000";
k <= X"0000000000000000";
wait;
end process;
 
 
end;
/camellia-vhdl/trunk/looping/f_tb.do
0,0 → 1,10
vcom -quiet sbox1.vhd
vcom -quiet sbox2.vhd
vcom -quiet sbox3.vhd
vcom -quiet sbox4.vhd
vcom -quiet f.vhd
vcom -quiet f_tb.vhd
vsim f_tb
view wave
add wave -HEX /uut/*
run 50 ns
/camellia-vhdl/trunk/looping/sbox1.vhd
0,0 → 1,300
 
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 01/22/2008
-- Last Update: 01/22/2008
-- Project Name: camellia-vhdl
-- Description: Asynchronous SBOX1
--
-- Copyright (C) 2008 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
 
entity SBOX1 is
port (
data_in : IN STD_LOGIC_VECTOR(0 to 7);
data_out : OUT STD_LOGIC_VECTOR(0 to 7)
);
end SBOX1;
 
architecture RTL of SBOX1 is
begin
 
with data_in select
data_out <= X"70" when X"00",
X"82" when X"01",
X"2C" when X"02",
X"EC" when X"03",
X"B3" when X"04",
X"27" when X"05",
X"C0" when X"06",
X"E5" when X"07",
X"E4" when X"08",
X"85" when X"09",
X"57" when X"0A",
X"35" when X"0B",
X"EA" when X"0C",
X"0C" when X"0D",
X"AE" when X"0E",
X"41" when X"0F",
X"23" when X"10",
X"EF" when X"11",
X"6B" when X"12",
X"93" when X"13",
X"45" when X"14",
X"19" when X"15",
X"A5" when X"16",
X"21" when X"17",
X"ED" when X"18",
X"0E" when X"19",
X"4F" when X"1A",
X"4E" when X"1B",
X"1D" when X"1C",
X"65" when X"1D",
X"92" when X"1E",
X"BD" when X"1F",
X"86" when X"20",
X"B8" when X"21",
X"AF" when X"22",
X"8F" when X"23",
X"7C" when X"24",
X"EB" when X"25",
X"1F" when X"26",
X"CE" when X"27",
X"3E" when X"28",
X"30" when X"29",
X"DC" when X"2A",
X"5F" when X"2B",
X"5E" when X"2C",
X"C5" when X"2D",
X"0B" when X"2E",
X"1A" when X"2F",
X"A6" when X"30",
X"E1" when X"31",
X"39" when X"32",
X"CA" when X"33",
X"D5" when X"34",
X"47" when X"35",
X"5D" when X"36",
X"3D" when X"37",
X"D9" when X"38",
X"01" when X"39",
X"5A" when X"3A",
X"D6" when X"3B",
X"51" when X"3C",
X"56" when X"3D",
X"6C" when X"3E",
X"4D" when X"3F",
X"8B" when X"40",
X"0D" when X"41",
X"9A" when X"42",
X"66" when X"43",
X"FB" when X"44",
X"CC" when X"45",
X"B0" when X"46",
X"2D" when X"47",
X"74" when X"48",
X"12" when X"49",
X"2B" when X"4A",
X"20" when X"4B",
X"F0" when X"4C",
X"B1" when X"4D",
X"84" when X"4E",
X"99" when X"4F",
X"DF" when X"50",
X"4C" when X"51",
X"CB" when X"52",
X"C2" when X"53",
X"34" when X"54",
X"7E" when X"55",
X"76" when X"56",
X"05" when X"57",
X"6D" when X"58",
X"B7" when X"59",
X"A9" when X"5A",
X"31" when X"5B",
X"D1" when X"5C",
X"17" when X"5D",
X"04" when X"5E",
X"D7" when X"5F",
X"14" when X"60",
X"58" when X"61",
X"3A" when X"62",
X"61" when X"63",
X"DE" when X"64",
X"1B" when X"65",
X"11" when X"66",
X"1C" when X"67",
X"32" when X"68",
X"0F" when X"69",
X"9C" when X"6A",
X"16" when X"6B",
X"53" when X"6C",
X"18" when X"6D",
X"F2" when X"6E",
X"22" when X"6F",
X"FE" when X"70",
X"44" when X"71",
X"CF" when X"72",
X"B2" when X"73",
X"C3" when X"74",
X"B5" when X"75",
X"7A" when X"76",
X"91" when X"77",
X"24" when X"78",
X"08" when X"79",
X"E8" when X"7A",
X"A8" when X"7B",
X"60" when X"7C",
X"FC" when X"7D",
X"69" when X"7E",
X"50" when X"7F",
X"AA" when X"80",
X"D0" when X"81",
X"A0" when X"82",
X"7D" when X"83",
X"A1" when X"84",
X"89" when X"85",
X"62" when X"86",
X"97" when X"87",
X"54" when X"88",
X"5B" when X"89",
X"1E" when X"8A",
X"95" when X"8B",
X"E0" when X"8C",
X"FF" when X"8D",
X"64" when X"8E",
X"D2" when X"8F",
X"10" when X"90",
X"C4" when X"91",
X"00" when X"92",
X"48" when X"93",
X"A3" when X"94",
X"F7" when X"95",
X"75" when X"96",
X"DB" when X"97",
X"8A" when X"98",
X"03" when X"99",
X"E6" when X"9A",
X"DA" when X"9B",
X"09" when X"9C",
X"3F" when X"9D",
X"DD" when X"9E",
X"94" when X"9F",
X"87" when X"A0",
X"5C" when X"A1",
X"83" when X"A2",
X"02" when X"A3",
X"CD" when X"A4",
X"4A" when X"A5",
X"90" when X"A6",
X"33" when X"A7",
X"73" when X"A8",
X"67" when X"A9",
X"F6" when X"AA",
X"F3" when X"AB",
X"9D" when X"AC",
X"7F" when X"AD",
X"BF" when X"AE",
X"E2" when X"AF",
X"52" when X"B0",
X"9B" when X"B1",
X"D8" when X"B2",
X"26" when X"B3",
X"C8" when X"B4",
X"37" when X"B5",
X"C6" when X"B6",
X"3B" when X"B7",
X"81" when X"B8",
X"96" when X"B9",
X"6F" when X"BA",
X"4B" when X"BB",
X"13" when X"BC",
X"BE" when X"BD",
X"63" when X"BE",
X"2E" when X"BF",
X"E9" when X"C0",
X"79" when X"C1",
X"A7" when X"C2",
X"8C" when X"C3",
X"9F" when X"C4",
X"6E" when X"C5",
X"BC" when X"C6",
X"8E" when X"C7",
X"29" when X"C8",
X"F5" when X"C9",
X"F9" when X"CA",
X"B6" when X"CB",
X"2F" when X"CC",
X"FD" when X"CD",
X"B4" when X"CE",
X"59" when X"CF",
X"78" when X"D0",
X"98" when X"D1",
X"06" when X"D2",
X"6A" when X"D3",
X"E7" when X"D4",
X"46" when X"D5",
X"71" when X"D6",
X"BA" when X"D7",
X"D4" when X"D8",
X"25" when X"D9",
X"AB" when X"DA",
X"42" when X"DB",
X"88" when X"DC",
X"A2" when X"DD",
X"8D" when X"DE",
X"FA" when X"DF",
X"72" when X"E0",
X"07" when X"E1",
X"B9" when X"E2",
X"55" when X"E3",
X"F8" when X"E4",
X"EE" when X"E5",
X"AC" when X"E6",
X"0A" when X"E7",
X"36" when X"E8",
X"49" when X"E9",
X"2A" when X"EA",
X"68" when X"EB",
X"3C" when X"EC",
X"38" when X"ED",
X"F1" when X"EE",
X"A4" when X"EF",
X"40" when X"F0",
X"28" when X"F1",
X"D3" when X"F2",
X"7B" when X"F3",
X"BB" when X"F4",
X"C9" when X"F5",
X"43" when X"F6",
X"C1" when X"F7",
X"15" when X"F8",
X"E3" when X"F9",
X"AD" when X"FA",
X"F4" when X"FB",
X"77" when X"FC",
X"C7" when X"FD",
X"80" when X"FE",
X"9E" when X"FF",
"--------" when others;
 
end RTL;
/camellia-vhdl/trunk/looping/sbox2.vhd
0,0 → 1,59
 
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 01/22/2008
-- Last Update: 01/22/2008
-- Project Name: camellia-vhdl
-- Description: Asynchronous SBOX2
--
-- Copyright (C) 2008 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
 
 
entity SBOX2 is
port (
data_in : IN STD_LOGIC_VECTOR(0 to 7);
data_out : OUT STD_LOGIC_VECTOR(0 to 7)
);
end SBOX2;
 
architecture RTL of SBOX2 is
 
component SBOX1 is
port (
data_in : IN STD_LOGIC_VECTOR(0 to 7);
data_out : OUT STD_LOGIC_VECTOR(0 to 7)
);
end component;
 
-- SBOX1 signals
signal s1_data_in : STD_LOGIC_VECTOR(0 to 7);
signal s1_data_out : STD_LOGIC_VECTOR(0 to 7);
 
begin
 
S1 : SBOX1
port map(s1_data_in, s1_data_out);
 
s1_data_in <= data_in;
data_out <= s1_data_out(1 to 7) & s1_data_out(0);
 
end RTL;
/camellia-vhdl/trunk/looping/sbox3.vhd
0,0 → 1,59
 
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 01/22/2008
-- Last Update: 01/22/2008
-- Project Name: camellia-vhdl
-- Description: Asynchronous SBOX3
--
-- Copyright (C) 2008 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
 
 
entity SBOX3 is
port (
data_in : IN STD_LOGIC_VECTOR(0 to 7);
data_out : OUT STD_LOGIC_VECTOR(0 to 7)
);
end SBOX3;
 
architecture RTL of SBOX3 is
 
component SBOX1 is
port (
data_in : IN STD_LOGIC_VECTOR(0 to 7);
data_out : OUT STD_LOGIC_VECTOR(0 to 7)
);
end component;
 
-- SBOX1 signals
signal s1_data_in : STD_LOGIC_VECTOR(0 to 7);
signal s1_data_out : STD_LOGIC_VECTOR(0 to 7);
 
begin
 
S1 : SBOX1
port map(s1_data_in, s1_data_out);
 
s1_data_in <= data_in;
data_out <= s1_data_out(7) & s1_data_out(0 to 6);
 
end RTL;
/camellia-vhdl/trunk/LICENSE
0,0 → 1,674
GNU GENERAL PUBLIC LICENSE
Version 3, 29 June 2007
 
Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/>
Everyone is permitted to copy and distribute verbatim copies
of this license document, but changing it is not allowed.
 
Preamble
 
The GNU General Public License is a free, copyleft license for
software and other kinds of works.
 
The licenses for most software and other practical works are designed
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the GNU General Public License is intended to guarantee your freedom to
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software for all its users. We, the Free Software Foundation, use the
GNU General Public License for most of our software; it applies also to
any other work released this way by its authors. You can apply it to
your programs, too.
 
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Additional permissions that are applicable to the entire Program shall
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Each time you convey a covered work, the recipient automatically
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organization, or substantially all assets of one, or subdividing an
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You may not impose any further restrictions on the exercise of the
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A "contributor" is a copyright holder who authorizes use under this
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work thus licensed is called the contributor's "contributor version".
 
A contributor's "essential patent claims" are all patent claims
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available, or (2) arrange to deprive yourself of the benefit of the
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consistent with the requirements of this License, to extend the patent
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receiving the covered work authorizing them to use, propagate, modify
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you grant is automatically extended to all recipients of the covered
work and works based on it.
 
A patent license is "discriminatory" if it does not include within
the scope of its coverage, prohibits the exercise of, or is
conditioned on the non-exercise of one or more of the rights that are
specifically granted under this License. You may not convey a covered
work if you are a party to an arrangement with a third party that is
in the business of distributing software, under which you make payment
to the third party based on the extent of your activity of conveying
the work, and under which the third party grants, to any of the
parties who would receive the covered work from you, a discriminatory
patent license (a) in connection with copies of the covered work
conveyed by you (or copies made from those copies), or (b) primarily
for and in connection with specific products or compilations that
contain the covered work, unless you entered into that arrangement,
or that patent license was granted, prior to 28 March 2007.
 
Nothing in this License shall be construed as excluding or limiting
any implied license or other defenses to infringement that may
otherwise be available to you under applicable patent law.
 
12. No Surrender of Others' Freedom.
 
If conditions are imposed on you (whether by court order, agreement or
otherwise) that contradict the conditions of this License, they do not
excuse you from the conditions of this License. If you cannot convey a
covered work so as to satisfy simultaneously your obligations under this
License and any other pertinent obligations, then as a consequence you may
not convey it at all. For example, if you agree to terms that obligate you
to collect a royalty for further conveying from those to whom you convey
the Program, the only way you could satisfy both those terms and this
License would be to refrain entirely from conveying the Program.
 
13. Use with the GNU Affero General Public License.
 
Notwithstanding any other provision of this License, you have
permission to link or combine any covered work with a work licensed
under version 3 of the GNU Affero General Public License into a single
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License will continue to apply to the part which is the covered work,
but the special requirements of the GNU Affero General Public License,
section 13, concerning interaction through a network will apply to the
combination as such.
 
14. Revised Versions of this License.
 
The Free Software Foundation may publish revised and/or new versions of
the GNU General Public License from time to time. Such new versions will
be similar in spirit to the present version, but may differ in detail to
address new problems or concerns.
 
Each version is given a distinguishing version number. If the
Program specifies that a certain numbered version of the GNU General
Public License "or any later version" applies to it, you have the
option of following the terms and conditions either of that numbered
version or of any later version published by the Free Software
Foundation. If the Program does not specify a version number of the
GNU General Public License, you may choose any version ever published
by the Free Software Foundation.
 
If the Program specifies that a proxy can decide which future
versions of the GNU General Public License can be used, that proxy's
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to choose that version for the Program.
 
Later license versions may give you additional or different
permissions. However, no additional obligations are imposed on any
author or copyright holder as a result of your choosing to follow a
later version.
 
15. Disclaimer of Warranty.
 
THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY
APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT
HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY
OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO,
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF
ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
 
16. Limitation of Liability.
 
IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS
THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY
GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE
USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF
DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD
PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS),
EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF
SUCH DAMAGES.
 
17. Interpretation of Sections 15 and 16.
 
If the disclaimer of warranty and limitation of liability provided
above cannot be given local legal effect according to their terms,
reviewing courts shall apply local law that most closely approximates
an absolute waiver of all civil liability in connection with the
Program, unless a warranty or assumption of liability accompanies a
copy of the Program in return for a fee.
 
END OF TERMS AND CONDITIONS
 
How to Apply These Terms to Your New Programs
 
If you develop a new program, and you want it to be of the greatest
possible use to the public, the best way to achieve this is to make it
free software which everyone can redistribute and change under these terms.
 
To do so, attach the following notices to the program. It is safest
to attach them to the start of each source file to most effectively
state the exclusion of warranty; and each file should have at least
the "copyright" line and a pointer to where the full notice is found.
 
<one line to give the program's name and a brief idea of what it does.>
Copyright (C) <year> <name of author>
 
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
 
Also add information on how to contact you by electronic and paper mail.
 
If the program does terminal interaction, make it output a short
notice like this when it starts in an interactive mode:
 
<program> Copyright (C) <year> <name of author>
This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
 
The hypothetical commands `show w' and `show c' should show the appropriate
parts of the General Public License. Of course, your program's commands
might be different; for a GUI interface, you would use an "about box".
 
You should also get your employer (if you work as a programmer) or school,
if any, to sign a "copyright disclaimer" for the program, if necessary.
For more information on this, and how to apply and follow the GNU GPL, see
<http://www.gnu.org/licenses/>.
 
The GNU General Public License does not permit incorporating your program
into proprietary programs. If your program is a subroutine library, you
may consider it more useful to permit linking proprietary applications with
the library. If this is what you want to do, use the GNU Lesser General
Public License instead of this License. But first, please read
<http://www.gnu.org/philosophy/why-not-lgpl.html>.
/camellia-vhdl/trunk
camellia-vhdl/trunk Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: camellia-vhdl/web_uploads =================================================================== --- camellia-vhdl/web_uploads (nonexistent) +++ camellia-vhdl/web_uploads (revision 9)
camellia-vhdl/web_uploads Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: camellia-vhdl/branches =================================================================== --- camellia-vhdl/branches (nonexistent) +++ camellia-vhdl/branches (revision 9)
camellia-vhdl/branches Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: camellia-vhdl/tags =================================================================== --- camellia-vhdl/tags (nonexistent) +++ camellia-vhdl/tags (revision 9)
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