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Rev 8 → Rev 9

/trunk/src/testbench/DECODERTESTBENCH.prj
0,0 → 1,13
vhdl work ../common/FIFO.vhd
vhdl work ../common/INPUT_CONTROL.vhd
vhdl work ../encoder/STORAGE_REGISTER.vhd
vhdl work ../common/ARITHMETIC_UNIT.vhd
vhdl work ../common/CONVERGENCE_CHECK.vhd
vhdl work ../common/UPDATER.vhd
vhdl work ../common/HALVING_MANAGER.vhd
vhdl work ../common/Divider.vhd
vhdl work ../common/CONTEXT_MANAGER.vhd
vhdl work ../decoder/SYMBOL_DETECTOR.vhd
vhdl work ../decoder/ARITHMETICDECODER.vhd
vhdl work ../expgolomb/EXP_GOLOMB_DECODER.vhd
vhdl work ArithmeticCoderTestbench.vhd
trunk/src/testbench/DECODERTESTBENCH.prj Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src/testbench/DECODERTESTBENCH.VHD =================================================================== --- trunk/src/testbench/DECODERTESTBENCH.VHD (nonexistent) +++ trunk/src/testbench/DECODERTESTBENCH.VHD (revision 9) @@ -0,0 +1,361 @@ +-- ***** BEGIN LICENSE BLOCK ***** +-- +-- $Id: DECODERTESTBENCH.VHD,v 1.1 2006-09-06 18:41:06 petebleackley Exp $ $Name: not supported by cvs2svn $ +-- * +-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1 +-- * +-- * The contents of this file are subject to the Mozilla Public License +-- * Version 1.1 (the "License"); you may not use this file except in compliance +-- * with the License. You may obtain a copy of the License at +-- * http://www.mozilla.org/MPL/ +-- * +-- * Software distributed under the License is distributed on an "AS IS" basis, +-- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for +-- * the specific language governing rights and limitations under the License. +-- * +-- * The Original Code is BBC Research and Development code. +-- * +-- * The Initial Developer of the Original Code is the British Broadcasting +-- * Corporation. +-- * Portions created by the Initial Developer are Copyright (C) 2004. +-- * All Rights Reserved. +-- * +-- * Contributor(s): Peter Bleackley (Original author) +-- * +-- * Alternatively, the contents of this file may be used under the terms of +-- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser +-- * Public License Version 2.1 (the "LGPL"), in which case the provisions of +-- * the GPL or the LGPL are applicable instead of those above. If you wish to +-- * allow use of your version of this file only under the terms of the either +-- * the GPL or LGPL and not to allow others to use your version of this file +-- * under the MPL, indicate your decision by deleting the provisions above +-- * and replace them with the notice and other provisions required by the GPL +-- * or LGPL. If you do not delete the provisions above, a recipient may use +-- * your version of this file under the terms of any one of the MPL, the GPL +-- * or the LGPL. +-- * ***** END LICENSE BLOCK ***** */ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; +use IEEE.std_logic_textio.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; +use STD.textio.all; + + +entity DECODERTESTBENCH is +end DECODERTESTBENCH; + +architecture BEHAVIOUR of DECODERTESTBENCH is + + component ARITHMETICDECODER + port (ENABLE : in std_logic; + DATA_IN : in std_logic; + NEWCONTEXT : in std_logic; + CONTEXT_SELECT : in std_logic_vector (5 downto 0); + HALVECOUNTS : in std_logic; + RESET : in std_logic; + CLOCK : in std_logic; + SENDING : out std_logic; + DATA_OUT : out std_logic); + end component ARITHMETICDECODER; + component EXP_GOLOMB_DECODER + port ( ENABLE : in std_logic; + DATA_IN : in std_logic; + RESET : in std_logic; + CLOCK : in std_logic; + READY : out std_logic; + DATA_OUT : out std_logic_vector (31 downto 0)); + end component EXP_GOLOMB_DECODER; + signal BYTES_INPUT : std_logic_vector (31 downto 0); + type STATUS is (OFFSET,FIND_START,GET_SIZE,FEED_DATA,PAUSE,FINISHED); + signal DECODER_STATE : STATUS := OFFSET; + signal ENABLE_DECODER : std_logic; + signal DECODER_DATA_IN : std_logic; + signal NEWCONTEXT : std_logic; + signal CONTEXT_SELECT : std_logic_vector (5 downto 0); + signal HALVECOUNTS : std_logic; + signal FLUSH : std_logic; + signal RESET : std_logic; + signal CLOCK : std_logic := '0'; + signal SENDING : std_logic; + signal DATA_OUT : std_logic; + signal GETCONTEXT : std_logic; + signal EG_ENABLE : std_logic; + signal EG_DATA_IN : std_logic; + signal EG_READY : std_logic; + signal INIT : std_logic := '1'; +-- signal LAST_BYTE : integer; +-- signal AFTER_FLUSH : std_logic; +-- signal BITPOS2 : integer; +-- signal COMPDATA : integer; + signal BYTES_TO_DECODE : std_logic_vector (31 downto 0); + type CHARFILE is file of character; + file HEADERFILE : CHARFILE open read_mode is "test1.hdr"; + file DIRACFILE : CHARFILE open read_mode is "test1.dr1"; + file CONTEXTFILE : CHARFILE open read_mode is "test1.ctx"; + file TARGETFILE : CHARFILE open read_mode is "test1.dr0"; + type INTARRAY is array (5 downto 0) of integer; + constant PERIOD : time := 10 ns; +begin + +UUT : ARITHMETICDECODER + port map(ENABLE => ENABLE_DECODER, + DATA_IN => DECODER_DATA_IN, + NEWCONTEXT => NEWCONTEXT, + CONTEXT_SELECT => CONTEXT_SELECT, + HALVECOUNTS => HALVECOUNTS, + RESET => RESET, + CLOCK => CLOCK, + SENDING => SENDING, + DATA_OUT => DATA_OUT); + +EGD : EXP_GOLOMB_DECODER + port map(ENABLE => EG_ENABLE, + DATA_IN => EG_DATA_IN, + RESET => RESET, + CLOCK => CLOCK, + READY => EG_READY, + DATA_OUT => BYTES_TO_DECODE); + + + CLOCK <= not CLOCK after PERIOD/2; + +--DELAY_FLUSH_SIGNAL : process (CLOCK) +--begin +-- if CLOCK'event and CLOCK = '1' then +-- AFTER_FLUSH <= FLUSH; +-- end if; +--end process DELAY_FLUSH_SIGNAL; + +TESTBENCH : process (CLOCK) +variable SCAN : INTARRAY; +variable READPLACE : integer := 5; +variable BITPOSITION : integer; +variable DIRACDATA : integer; +variable DIRACREAD : character; +variable TARGETREAD : character; +variable PAUSECOUNT : integer; +begin + if CLOCK'event and CLOCK='1' then + if DECODER_STATE = OFFSET then + if READPLACE = 0 then + DECODER_STATE <= FIND_START; + BITPOSITION := 0; + -- elsif AFTER_FLUSH = '1' and READPLACE = 4 then + -- SCAN(5) := LAST_BYTE; + else + if READPLACE < 5 and INIT = '1' then + INIT <= '0'; + end if; + read(TARGETFILE,TARGETREAD); + SCAN(READPLACE) := character'pos(TARGETREAD); + READPLACE := READPLACE - 1; + + end if; + elsif DECODER_STATE = FIND_START then + if SCAN (5 downto 1) = ( 16#42#, 16#42#, 16#43#, 16#44#, 16#AC# ) then + --BITPOS2 <= BITPOSITION; + --COMPDATA <= SCAN(0); + DECODER_STATE <= GET_SIZE; + if BITPOSITION = 0 then + BITPOSITION := 128; + end if; + elsif SCAN(5 downto 1) = (16#42#, 16#42#, 16#43#, 16#44#, 16#D0# ) then + DECODER_STATE <= FINISHED; + elsif BITPOSITION = 0 then + read(TARGETFILE,TARGETREAD); + read(HEADERFILE,DIRACREAD); + SCAN(0) := character'pos(TARGETREAD); + DIRACDATA := character'pos(DIRACREAD); + BITPOSITION := 128; + else + for I in 5 downto 1 loop + if SCAN(I) > 127 then + SCAN(I) := SCAN(I) - 128; + end if; + SCAN(I) := SCAN(I)*2; + if SCAN(I-1) > 127 then + SCAN(I) := SCAN(I) + 1; + end if; + end loop; + if SCAN(0) > 127 then + SCAN(0) := SCAN(0) - 128; + end if; + SCAN(0) := SCAN(0)*2; + BITPOSITION := BITPOSITION/2; + end if; + elsif DECODER_STATE = GET_SIZE then + if EG_READY = '1' then + DECODER_STATE <= FEED_DATA; + BITPOSITION := 128; + EG_ENABLE <= '0'; + BYTES_INPUT <= (others => '0'); + elsif EG_ENABLE = '1' then + EG_ENABLE <= '0'; + else + if BITPOSITION = 128 then + READ(HEADERFILE,DIRACREAD); + DIRACDATA := character'pos(DIRACREAD); + end if; + if (DIRACDATA rem (BITPOSITION*2))/BITPOSITION = 1 then + EG_DATA_IN <= '1'; + else + EG_DATA_IN <= '0'; + end if; + EG_ENABLE <= '1'; + if BITPOSITION = 1 then + BITPOSITION := 128; + else + BITPOSITION := BITPOSITION/2; + end if; + end if; + elsif DECODER_STATE = FEED_DATA then + if FLUSH = '1' then + DECODER_STATE <= OFFSET; + ENABLE_DECODER <= '0'; + -- if BITPOSITION = 128 then + -- READPLACE := 4; + -- else + READPLACE := 5; + -- end if; + elsif BITPOSITION = 0 then + DECODER_STATE <= PAUSE; + BYTES_INPUT <= BYTES_INPUT + 1; + ENABLE_DECODER <= '0'; + PAUSECOUNT := 0; + else + if BITPOSITION = 128 then + if BYTES_INPUT < BYTES_TO_DECODE then + read(DIRACFILE,DIRACREAD); + DIRACDATA := character'pos(DIRACREAD); + else + DIRACDATA := 0; + end if; + end if; + if (DIRACDATA rem (BITPOSITION*2))/BITPOSITION = 1 then + DECODER_DATA_IN <= '1'; + else + DECODER_DATA_IN <= '0'; + end if; + ENABLE_DECODER <= '1'; + BITPOSITION := BITPOSITION/2; + end if; + elsif DECODER_STATE = PAUSE then + if FLUSH = '1' then + DECODER_STATE <= OFFSET; + READPLACE := 5; + elsif PAUSECOUNT > 7 then + DECODER_STATE <= FEED_DATA; + BITPOSITION := 128; + elsif SENDING = '1' then + PAUSECOUNT := 0; + else + PAUSECOUNT := PAUSECOUNT+1; + end if; + else --DECODER_STATE = FINISHED; + report "Finished" severity failure; + end if; + end if; +end process TESTBENCH; + +RESET <= INIT or FLUSH; + +GETCONTEXT <= (RESET or SENDING) and not NEWCONTEXT; + +CONTEXT : process (CLOCK) +variable CONTEXTREAD : character; +variable CONTEXTDATA : integer; +variable READPOSITION : integer; +variable NUMBER_READ : integer :=0; +begin + if CLOCK'event and CLOCK = '1' then + if GETCONTEXT = '1' then + read(CONTEXTFILE,CONTEXTREAD); + NUMBER_READ := NUMBER_READ + 1; + CONTEXTDATA := character'pos(CONTEXTREAD); + if (CONTEXTDATA rem 2) = 1 then + FLUSH <= '1'; + else + FLUSH <= '0'; + if(CONTEXTDATA rem 4)/2 = 1 then + HALVECOUNTS <= '1'; + else + HALVECOUNTS <= '0'; + end if; + READPOSITION := 128; + for I in 5 downto 0 loop + if (CONTEXTDATA rem (READPOSITION*2))/READPOSITION = 1 then + CONTEXT_SELECT(I) <= '1'; + else + CONTEXT_SELECT(I) <= '0'; + end if; + READPOSITION := READPOSITION/2; + end loop; + NEWCONTEXT <= '1'; + end if; + else + NEWCONTEXT <= '0'; + FLUSH <= '0'; + HALVECOUNTS <= '0'; + end if; + end if; +end process CONTEXT; + + +CHECK_RESULTS : process (CLOCK) +variable DATA : integer; +variable COMPARISON : integer; +variable COMP2 : integer; +--variable BITPOSITION : integer; +variable INDEX : integer; +variable COMPREAD : character; +begin + if CLOCK'event and CLOCK = '1' then + if RESET = '1' then + -- DATA := 0; + -- BITPOSITION := BITPOS2; + -- read(TARGETFILE,COMPREAD); + -- COMPARISON := character'pos(COMPREAD); + -- COMP2 := 0; + INDEX := 128; + elsif SENDING = '1' then + if INDEX = 128 then + DATA := 0; + read(TARGETFILE,COMPREAD); + COMPARISON := character'pos(COMPREAD); + COMP2 := 0; + end if; + if DATA_OUT = '1' then + DATA:=DATA+INDEX; + end if; + if (COMPARISON rem (INDEX*2))/INDEX = 1 then + COMP2 := COMP2 + INDEX; + end if; + assert COMP2 = DATA report "Decoder has Diverged" severity failure; + if INDEX = 1 then + -- read(TARGETFILE,COMPREAD); + -- COMPARISON := character'pos(COMPREAD); + -- LAST_BYTE <= COMPARISON; + -- COMP2 := 0; + -- DATA := 0; + -- BITPOSITION := 128; + INDEX := 128; + else + -- BITPOSITION := BITPOSITION/2; + INDEX := INDEX/2; + end if; + end if; + end if; +end process CHECK_RESULTS; + +end architecture BEHAVIOUR; + + + + + + + + + \ No newline at end of file
trunk/src/testbench/DECODERTESTBENCH.VHD Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src/testbench/ArithmeticCoderTestbench.vhd =================================================================== --- trunk/src/testbench/ArithmeticCoderTestbench.vhd (revision 8) +++ trunk/src/testbench/ArithmeticCoderTestbench.vhd (revision 9) @@ -1,37 +1,38 @@ -- ***** BEGIN LICENSE BLOCK ***** -- --- --- Version: MPL 1.1/GPL 2.0/LGPL 2.1 --- --- The contents of this file are subject to the Mozilla Public License --- Version 1.1 (the "License"); you may not use this file except in compliance --- with the License. You may obtain a copy of the License at --- http://www.mozilla.org/MPL/ --- --- Software distributed under the License is distributed on an "AS IS" basis, --- WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for --- the specific language governing rights and limitations under the License. --- --- The Original Code is BBC Research and Development code. --- --- The Initial Developer of the Original Code is the British Broadcasting --- Corporation. --- Portions created by the Initial Developer are Copyright (C) 2006. --- All Rights Reserved. --- --- Contributor(s): Peter Bleackley (Original author) --- --- Alternatively, the contents of this file may be used under the terms of --- the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser --- Public License Version 2.1 (the "LGPL"), in which case the provisions of --- the GPL or the LGPL are applicable instead of those above. If you wish to --- allow use of your version of this file only under the terms of the either --- the GPL or LGPL and not to allow others to use your version of this file --- under the MPL, indicate your decision by deleting the provisions above --- and replace them with the notice and other provisions required by the GPL --- or LGPL. If you do not delete the provisions above, a recipient may use --- your version of this file under the terms of any one of the MPL, the GPL --- or the LGPL. +-- $Id: ArithmeticCoderTestbench.vhd,v 1.5 2006-09-06 18:41:06 petebleackley Exp $ $Name: not supported by cvs2svn $ +-- * +-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1 +-- * +-- * The contents of this file are subject to the Mozilla Public License +-- * Version 1.1 (the "License"); you may not use this file except in compliance +-- * with the License. You may obtain a copy of the License at +-- * http://www.mozilla.org/MPL/ +-- * +-- * Software distributed under the License is distributed on an "AS IS" basis, +-- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for +-- * the specific language governing rights and limitations under the License. +-- * +-- * The Original Code is BBC Research and Development code. +-- * +-- * The Initial Developer of the Original Code is the British Broadcasting +-- * Corporation. +-- * Portions created by the Initial Developer are Copyright (C) 2004. +-- * All Rights Reserved. +-- * +-- * Contributor(s): Peter Bleackley (Original author) +-- * +-- * Alternatively, the contents of this file may be used under the terms of +-- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser +-- * Public License Version 2.1 (the "LGPL"), in which case the provisions of +-- * the GPL or the LGPL are applicable instead of those above. If you wish to +-- * allow use of your version of this file only under the terms of the either +-- * the GPL or LGPL and not to allow others to use your version of this file +-- * under the MPL, indicate your decision by deleting the provisions above +-- * and replace them with the notice and other provisions required by the GPL +-- * or LGPL. If you do not delete the provisions above, a recipient may use +-- * your version of this file under the terms of any one of the MPL, the GPL +-- * or the LGPL. -- * ***** END LICENSE BLOCK ***** */ LIBRARY ieee; @@ -311,7 +312,9 @@ if EXP_GOLOMB_READY = '0' then STATE <= WRITE_DATA; INDEX := 0; - write(coded_stream,character'val(WRITEVAL)); + if EGPOSITION /= 128 then + write(coded_stream,character'val(WRITEVAL)); + end if; PLACE := 7; else if EXP_GOLOMB_DATA = '1' then
/trunk/src/testbench/test1.hdr Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/src/testbench/test1.hdr
trunk/src/testbench/test1.hdr Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/src/decoder/ARITHMETICDECODER.vhd =================================================================== --- trunk/src/decoder/ARITHMETICDECODER.vhd (revision 8) +++ trunk/src/decoder/ARITHMETICDECODER.vhd (revision 9) @@ -1,41 +1,3 @@ --- ***** BEGIN LICENSE BLOCK ***** --- --- $Id: ARITHMETICDECODER.vhd,v 1.2 2005-05-27 16:00:29 petebleackley Exp $ $Name: not supported by cvs2svn $ --- * --- * Version: MPL 1.1/GPL 2.0/LGPL 2.1 --- * --- * The contents of this file are subject to the Mozilla Public License --- * Version 1.1 (the "License"); you may not use this file except in compliance --- * with the License. You may obtain a copy of the License at --- * http://www.mozilla.org/MPL/ --- * --- * Software distributed under the License is distributed on an "AS IS" basis, --- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for --- * the specific language governing rights and limitations under the License. --- * --- * The Original Code is BBC Research and Development code. --- * --- * The Initial Developer of the Original Code is the British Broadcasting --- * Corporation. --- * Portions created by the Initial Developer are Copyright (C) 2004. --- * All Rights Reserved. --- * --- * Contributor(s): Peter Bleackley (Original author) --- * --- * Alternatively, the contents of this file may be used under the terms of --- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser --- * Public License Version 2.1 (the "LGPL"), in which case the provisions of --- * the GPL or the LGPL are applicable instead of those above. If you wish to --- * allow use of your version of this file only under the terms of the either --- * the GPL or LGPL and not to allow others to use your version of this file --- * under the MPL, indicate your decision by deleting the provisions above --- * and replace them with the notice and other provisions required by the GPL --- * or LGPL. If you do not delete the provisions above, a recipient may use --- * your version of this file under the terms of any one of the MPL, the GPL --- * or the LGPL. --- * ***** END LICENSE BLOCK ***** */ - - library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; @@ -51,6 +13,7 @@ DATA_IN : in std_logic; NEWCONTEXT : in std_logic; CONTEXT_SELECT : in std_logic_vector (5 downto 0); + HALVECOUNTS : in std_logic; RESET : in std_logic; CLOCK : in std_logic; SENDING : out std_logic; @@ -108,10 +71,15 @@ DATA_OUT : out std_logic); end component SYMBOL_DETECTOR; component CONTEXT_MANAGER - port ( CONTEXT_NUMBER : in std_logic_vector(5 downto 0); + port ( CONTEXT_NUMBER : in std_logic_vector(5 downto 0); + SET : in std_logic; + UPDATE : in std_logic; + DATA_IN : in std_logic; + HALVECOUNTS : in std_logic; RESET : in std_logic; CLOCK : in std_logic; - PROB : out std_logic_vector(9 downto 0)); + PROB : out std_logic_vector(9 downto 0); + READY : out std_logic); end component CONTEXT_MANAGER; signal HIGH_SET : std_logic; signal LOW_SET : std_logic; @@ -129,6 +97,7 @@ signal BUFFERED_DATA : std_logic; signal SYMBOL : std_logic; signal HOLD : std_logic; + signal PROB_AVAILABLE : std_logic; signal DIFFERENCE_IN : std_logic_vector (15 downto 0); signal ARITHMETIC_UNIT_RESULT_OUT0 : std_logic_vector (15 downto 0); signal ARITHMETIC_UNIT_RESULT_OUT1 : std_logic_vector (15 downto 0); @@ -142,6 +111,7 @@ signal DATA_IN2 : std_logic_vector(0 downto 0); signal BUFFERED_DATA2 : std_logic_vector(0 downto 0); + begin -- input buffering INBUFFER: INPUT_CONTROL @@ -162,9 +132,14 @@ PROBABILITY : CONTEXT_MANAGER port map(CONTEXT_NUMBER => CONTEXT_SELECT, + SET => NEWCONTEXT, + UPDATE =>DATA_LOAD, + DATA_IN => SYMBOL, + HALVECOUNTS => HALVECOUNTS, RESET => RESET, CLOCK => CLOCK, - PROB => PROB); + PROB => PROB, + READY => PROB_AVAILABLE); -- Specify the registers HIGH: STORAGE_REGISTER @@ -254,20 +229,11 @@ DIFFERENCE_SHIFT_ALL <= SHIFT_ALL or SHIFT_MOST; --- Control logic for convergence check - --- CHECK <= DIFFERENCE_SHIFT_ALL or DATA_LOAD or RESET; - --- CONVERGENCE_TEST_DELAY: D_TYPE --- port map( D => CHECK, --- CLOCK => CLOCK, --- Q => CONVERGENCE_TEST); - CONVERGENCE_TEST <= not DATA_LOAD; -- Control logic for arithmetic unit - ARITHMETIC_UNIT_ENABLE <= not(GET_DATA or DATA_LOAD or NEWCONTEXT); + ARITHMETIC_UNIT_ENABLE <= PROB_AVAILABLE and not(GET_DATA or DATA_LOAD or NEWCONTEXT); -- Control Logic for input control SHIFT_ALL <= TRIGGER_INPUT and DATA_AVAILABLE; @@ -283,6 +249,4 @@ end if; end process NEWDIFF; - - end RTL;
/trunk/src/decoder/STORAGE_REGISTER.vhd
1,41 → 1,3
-- ***** BEGIN LICENSE BLOCK *****
--
-- $Id: STORAGE_REGISTER.vhd,v 1.2 2005-05-27 16:00:29 petebleackley Exp $ $Name: not supported by cvs2svn $
-- *
-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
-- *
-- * The contents of this file are subject to the Mozilla Public License
-- * Version 1.1 (the "License"); you may not use this file except in compliance
-- * with the License. You may obtain a copy of the License at
-- * http://www.mozilla.org/MPL/
-- *
-- * Software distributed under the License is distributed on an "AS IS" basis,
-- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
-- * the specific language governing rights and limitations under the License.
-- *
-- * The Original Code is BBC Research and Development code.
-- *
-- * The Initial Developer of the Original Code is the British Broadcasting
-- * Corporation.
-- * Portions created by the Initial Developer are Copyright (C) 2004.
-- * All Rights Reserved.
-- *
-- * Contributor(s): Peter Bleackley (Original author)
-- *
-- * Alternatively, the contents of this file may be used under the terms of
-- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
-- * Public License Version 2.1 (the "LGPL"), in which case the provisions of
-- * the GPL or the LGPL are applicable instead of those above. If you wish to
-- * allow use of your version of this file only under the terms of the either
-- * the GPL or LGPL and not to allow others to use your version of this file
-- * under the MPL, indicate your decision by deleting the provisions above
-- * and replace them with the notice and other provisions required by the GPL
-- * or LGPL. If you do not delete the provisions above, a recipient may use
-- * your version of this file under the terms of any one of the MPL, the GPL
-- * or the LGPL.
-- * ***** END LICENSE BLOCK ***** */
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
46,7 → 8,7
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity STORAGE_REGISTER is
entity STORAGE_REGISTER is
Port ( LOAD : in std_logic_vector(15 downto 0);
SHIFT_IN : in std_logic;
SET_VALUE : in std_logic;
59,55 → 21,28
 
architecture RTL of STORAGE_REGISTER is
 
signal SHIFT_LSBS: std_logic;
signal SET_RESET: std_logic;
signal ENABLE_MSB: std_logic;
signal ENABLE_LSBS: std_logic;
signal D: std_logic_vector(15 downto 0);
signal Q: std_logic_vector(15 downto 0);
begin
 
-- control logic
SET_RESET <= SET_VALUE or RESET;
ENABLE_MSB <= SET_RESET or SHIFT_ALL;
SHIFT_LSBS <= SHIFT_ALL or SHIFT_MOST;
ENABLE_LSBS <= SET_RESET or SHIFT_LSBS;
 
-- outputs
OUTPUT <= Q;
 
 
-- initialisation
 
INIT: process(RESET,LOAD)
begin
if RESET = '1' then
D <= "0000000000000000";
else
D <= LOAD;
end if;
end process INIT;
 
-- storage
 
STORE: process (CLOCK)
begin
if CLOCK'event and CLOCK = '1' then
if ENABLE_LSBS = '1' then
if SHIFT_LSBS = '1' then
Q(14 downto 0) <= Q(13 downto 0) & SHIFT_IN;
else
Q(14 downto 0) <= D(14 downto 0);
end if;
if RESET = '1' then
Q <= (others => '0');
elsif SET_VALUE = '1' then
Q <= LOAD;
elsif SHIFT_ALL = '1' then
Q <= Q(14 downto 0) & SHIFT_IN;
elsif SHIFT_MOST = '1' then
Q <= Q(15) & Q(13 downto 0) & SHIFT_IN;
end if;
if ENABLE_MSB = '1' then
if SHIFT_ALL = '1' then
Q(15) <= Q(14);
else
Q(15) <= D(15);
end if;
end if;
end if;
end process STORE;
 
/trunk/docs/synthesis_reports/encoder/arithmeticcoder.syr
0,0 → 1,956
Release 7.1.04i - xst H.42
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.34 s | Elapsed : 0.00 / 0.00 s
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.34 s | Elapsed : 0.00 / 0.00 s
--> Reading design: arithmeticcoder.prj
 
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) HDL Analysis
4) HDL Synthesis
5) Advanced HDL Synthesis
5.1) HDL Synthesis Report
6) Low Level Synthesis
7) Final Report
7.1) Device utilization summary
7.2) TIMING REPORT
 
 
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "arithmeticcoder.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
 
---- Target Parameters
Output File Name : "arithmeticcoder"
Output Format : NGC
Target Device : xc2v2000-6-bg575
 
---- Source Options
Top Module Name : arithmeticcoder
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
ROM Style : Auto
Mux Extraction : YES
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
Resource Sharing : YES
Multiplier Style : auto
Automatic Register Balancing : No
 
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 16
Register Duplication : YES
Equivalent register Removal : YES
Slice Packing : YES
Pack IO Registers into IOBs : auto
 
---- General Options
Optimization Goal : Speed
Optimization Effort : 2
Keep Hierarchy : NO
Global Optimization : AllClockNets
RTL Output : Yes
Write Timing Constraints : NO
Hierarchy Separator : _
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
Slice Utilization Ratio Delta : 5
 
---- Other Options
lso : arithmeticcoder.lso
Read Cores : YES
cross_clock_analysis : NO
verilog2001 : YES
safe_implementation : No
Optimize Instantiated Primitives : NO
tristate2logic : Yes
use_clock_enable : Yes
use_sync_set : Yes
use_sync_reset : Yes
enable_auto_floorplanning : No
 
=========================================================================
 
 
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/Divider.vhd" in Library work.
Architecture rtl of Entity divider is up to date.
Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/UPDATER.vhd" in Library work.
Entity <updater> compiled.
Entity <updater> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" in Library work.
Architecture rtl of Entity halving_manager is up to date.
Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/FIFO.vhd" in Library work.
Architecture rtl of Entity fifo is up to date.
Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/INPUT_CONTROL.vhd" in Library work.
Architecture rtl of Entity input_control is up to date.
Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/REGISTER.vhd" in Library work.
Architecture rtl of Entity limit_register is up to date.
Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/ARITHMETIC_UNIT.vhd" in Library work.
Architecture rtl of Entity arithmetic_unit is up to date.
Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/CONVERGENCE_CHECK.vhd" in Library work.
Architecture rtl of Entity convergence_check is up to date.
Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/FOLLOW_COUNTER.vhd" in Library work.
Architecture rtl of Entity follow_counter is up to date.
Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/OUTPUT_UNIT.vhd" in Library work.
Architecture rtl of Entity output_unit is up to date.
Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/CONTEXT_MANAGER.vhd" in Library work.
Architecture rtl of Entity context_manager is up to date.
Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/ARITHMETICCODER.vhd" in Library work.
Architecture rtl of Entity arithmeticcoder is up to date.
 
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity <arithmeticcoder> (Architecture <rtl>).
Entity <arithmeticcoder> analyzed. Unit <arithmeticcoder> generated.
 
Analyzing generic Entity <INPUT_CONTROL> (Architecture <rtl>).
WIDTH = 1
Entity <INPUT_CONTROL> analyzed. Unit <INPUT_CONTROL> generated.
 
Analyzing generic Entity <FIFO> (Architecture <rtl>).
RANK = 8
WIDTH = 1
Entity <FIFO> analyzed. Unit <FIFO> generated.
 
Analyzing generic Entity <INPUT_CONTROL.0> (Architecture <rtl>).
WIDTH = 8
Entity <INPUT_CONTROL.0> analyzed. Unit <INPUT_CONTROL.0> generated.
 
Analyzing generic Entity <FIFO.2> (Architecture <rtl>).
RANK = 8
WIDTH = 8
Entity <FIFO.2> analyzed. Unit <FIFO.2> generated.
 
Analyzing generic Entity <LIMIT_REGISTER> (Architecture <rtl>).
CONST = <u>1
Entity <LIMIT_REGISTER> analyzed. Unit <LIMIT_REGISTER> generated.
 
Analyzing generic Entity <LIMIT_REGISTER.1> (Architecture <rtl>).
CONST = <u>0
Entity <LIMIT_REGISTER.1> analyzed. Unit <LIMIT_REGISTER.1> generated.
 
Analyzing Entity <ARITHMETIC_UNIT> (Architecture <rtl>).
Entity <ARITHMETIC_UNIT> analyzed. Unit <ARITHMETIC_UNIT> generated.
 
Analyzing Entity <CONVERGENCE_CHECK> (Architecture <rtl>).
Entity <CONVERGENCE_CHECK> analyzed. Unit <CONVERGENCE_CHECK> generated.
 
Analyzing Entity <FOLLOW_COUNTER> (Architecture <rtl>).
Entity <FOLLOW_COUNTER> analyzed. Unit <FOLLOW_COUNTER> generated.
 
Analyzing Entity <OUTPUT_UNIT> (Architecture <rtl>).
Entity <OUTPUT_UNIT> analyzed. Unit <OUTPUT_UNIT> generated.
 
Analyzing Entity <CONTEXT_MANAGER> (Architecture <rtl>).
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/CONTEXT_MANAGER.vhd" line 133: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/CONTEXT_MANAGER.vhd" line 137: Index value(s) does not match array range, simulation mismatch.
Entity <CONTEXT_MANAGER> analyzed. Unit <CONTEXT_MANAGER> generated.
 
Analyzing Entity <DIVIDER> (Architecture <rtl>).
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/Divider.vhd" line 1079: Index value(s) does not match array range, simulation mismatch.
Entity <DIVIDER> analyzed. Unit <DIVIDER> generated.
 
Analyzing Entity <UPDATER> (Architecture <rtl>).
Entity <UPDATER> analyzed. Unit <UPDATER> generated.
 
Analyzing Entity <HALVING_MANAGER> (Architecture <rtl>).
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" line 71: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" line 71: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" line 73: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" line 108: Index value(s) does not match array range, simulation mismatch.
Entity <HALVING_MANAGER> analyzed. Unit <HALVING_MANAGER> generated.
 
 
=========================================================================
* HDL Synthesis *
=========================================================================
 
Synthesizing Unit <HALVING_MANAGER>.
Related source file is "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd".
Found 3-bit 46-to-1 multiplexer for signal <$n0002> created at line 108.
Found 3-bit 4-to-1 multiplexer for signal <$n0050>.
Found 3-bit 4-to-1 multiplexer for signal <$n0051>.
Found 3-bit 4-to-1 multiplexer for signal <$n0052>.
Found 3-bit 4-to-1 multiplexer for signal <$n0053>.
Found 3-bit 4-to-1 multiplexer for signal <$n0054>.
Found 3-bit 4-to-1 multiplexer for signal <$n0055>.
Found 3-bit 4-to-1 multiplexer for signal <$n0056>.
Found 3-bit 4-to-1 multiplexer for signal <$n0057>.
Found 3-bit 4-to-1 multiplexer for signal <$n0058>.
Found 3-bit 4-to-1 multiplexer for signal <$n0059>.
Found 3-bit 4-to-1 multiplexer for signal <$n0060>.
Found 3-bit 4-to-1 multiplexer for signal <$n0061>.
Found 3-bit 4-to-1 multiplexer for signal <$n0062>.
Found 3-bit 4-to-1 multiplexer for signal <$n0063>.
Found 3-bit 4-to-1 multiplexer for signal <$n0064>.
Found 3-bit 4-to-1 multiplexer for signal <$n0065>.
Found 3-bit 4-to-1 multiplexer for signal <$n0066>.
Found 3-bit 4-to-1 multiplexer for signal <$n0067>.
Found 3-bit 4-to-1 multiplexer for signal <$n0068>.
Found 3-bit 4-to-1 multiplexer for signal <$n0069>.
Found 3-bit 4-to-1 multiplexer for signal <$n0070>.
Found 3-bit 4-to-1 multiplexer for signal <$n0071>.
Found 3-bit 4-to-1 multiplexer for signal <$n0072>.
Found 3-bit 4-to-1 multiplexer for signal <$n0073>.
Found 3-bit 4-to-1 multiplexer for signal <$n0074>.
Found 3-bit 4-to-1 multiplexer for signal <$n0075>.
Found 3-bit 4-to-1 multiplexer for signal <$n0076>.
Found 3-bit 4-to-1 multiplexer for signal <$n0077>.
Found 3-bit 4-to-1 multiplexer for signal <$n0078>.
Found 3-bit 4-to-1 multiplexer for signal <$n0079>.
Found 3-bit 4-to-1 multiplexer for signal <$n0080>.
Found 3-bit 4-to-1 multiplexer for signal <$n0081>.
Found 3-bit 4-to-1 multiplexer for signal <$n0082>.
Found 3-bit 4-to-1 multiplexer for signal <$n0084>.
Found 3-bit 4-to-1 multiplexer for signal <$n0085>.
Found 3-bit 4-to-1 multiplexer for signal <$n0087>.
Found 3-bit 4-to-1 multiplexer for signal <$n0088>.
Found 3-bit 4-to-1 multiplexer for signal <$n0089>.
Found 3-bit 4-to-1 multiplexer for signal <$n0090>.
Found 3-bit 4-to-1 multiplexer for signal <$n0091>.
Found 3-bit 4-to-1 multiplexer for signal <$n0092>.
Found 3-bit 4-to-1 multiplexer for signal <$n0093>.
Found 3-bit 4-to-1 multiplexer for signal <$n0094>.
Found 3-bit 4-to-1 multiplexer for signal <$n0095>.
Found 3-bit 4-to-1 multiplexer for signal <$n0096>.
Found 3-bit 4-to-1 multiplexer for signal <$n0097>.
Found 3-bit addsub for signal <$n0098>.
Found 3-bit addsub for signal <$n0100>.
Found 3-bit addsub for signal <$n0101>.
Found 3-bit addsub for signal <$n0102>.
Found 3-bit addsub for signal <$n0103>.
Found 3-bit addsub for signal <$n0104>.
Found 3-bit addsub for signal <$n0105>.
Found 3-bit addsub for signal <$n0106>.
Found 3-bit addsub for signal <$n0107>.
Found 3-bit addsub for signal <$n0108>.
Found 3-bit addsub for signal <$n0109>.
Found 3-bit addsub for signal <$n0110>.
Found 3-bit addsub for signal <$n0111>.
Found 3-bit addsub for signal <$n0112>.
Found 3-bit addsub for signal <$n0113>.
Found 3-bit addsub for signal <$n0114>.
Found 3-bit addsub for signal <$n0115>.
Found 3-bit addsub for signal <$n0116>.
Found 3-bit addsub for signal <$n0117>.
Found 3-bit addsub for signal <$n0118>.
Found 3-bit addsub for signal <$n0119>.
Found 3-bit addsub for signal <$n0120>.
Found 3-bit addsub for signal <$n0121>.
Found 3-bit addsub for signal <$n0122>.
Found 3-bit addsub for signal <$n0123>.
Found 3-bit addsub for signal <$n0124>.
Found 3-bit addsub for signal <$n0125>.
Found 3-bit addsub for signal <$n0126>.
Found 3-bit addsub for signal <$n0127>.
Found 3-bit addsub for signal <$n0128>.
Found 3-bit addsub for signal <$n0129>.
Found 3-bit addsub for signal <$n0130>.
Found 3-bit addsub for signal <$n0131>.
Found 3-bit addsub for signal <$n0132>.
Found 3-bit addsub for signal <$n0133>.
Found 3-bit addsub for signal <$n0134>.
Found 3-bit addsub for signal <$n0135>.
Found 3-bit addsub for signal <$n0136>.
Found 3-bit addsub for signal <$n0137>.
Found 3-bit addsub for signal <$n0138>.
Found 3-bit addsub for signal <$n0139>.
Found 3-bit addsub for signal <$n0140>.
Found 3-bit addsub for signal <$n0141>.
Found 3-bit addsub for signal <$n0142>.
Found 3-bit addsub for signal <$n0143>.
Found 3-bit addsub for signal <$n0144>.
Found 10-bit comparator greater for signal <$n0147> created at line 99.
Found 3-bit comparator greater for signal <$n0241> created at line 108.
Found 1-bit register for signal <AFTER_TRIGGER>.
Found 10-bit register for signal <DENOMINATOR>.
Found 10-bit adder for signal <DENOMINATOR2>.
Found 10-bit register for signal <NUMERATOR>.
Found 10-bit adder for signal <NUMERATOR2>.
Found 138-bit register for signal <SHIFTS>.
Summary:
inferred 139 D-type flip-flop(s).
inferred 48 Adder/Subtractor(s).
inferred 2 Comparator(s).
inferred 141 Multiplexer(s).
Unit <HALVING_MANAGER> synthesized.
 
 
Synthesizing Unit <UPDATER>.
Related source file is "C:/Xilinx/bin/ArithmeticCoder/UPDATER.vhd".
WARNING:Xst:1780 - Signal <HALVING_ALLOWED> is never used or assigned.
Found 1-bit register for signal <UPDATE>.
Found 10-bit 4-to-1 multiplexer for signal <DENOMINATOR_OUT>.
Found 10-bit 4-to-1 multiplexer for signal <NUMERATOR_OUT>.
Found 10-bit adder for signal <$n0009> created at line 51.
Found 10-bit adder for signal <$n0011> created at line 73.
Found 10-bit adder for signal <$n0012> created at line 84.
Found 10-bit adder for signal <$n0013> created at line 62.
Found 10-bit register for signal <DENOMINATOR2>.
Found 10-bit register for signal <NUMERATOR1>.
Found 10-bit register for signal <NUMERATOR2>.
Found 10-bit register for signal <NUMERATOR3>.
Found 10-bit register for signal <NUMERATOR4>.
Found 1-bit xor2 for signal <UPDATE_SWITCH>.
Summary:
inferred 1 D-type flip-flop(s).
inferred 4 Adder/Subtractor(s).
inferred 20 Multiplexer(s).
Unit <UPDATER> synthesized.
 
 
Synthesizing Unit <DIVIDER>.
Related source file is "C:/Xilinx/bin/ArithmeticCoder/Divider.vhd".
WARNING:Xst:646 - Signal <TOTAL<41:32>> is assigned but never used.
WARNING:Xst:646 - Signal <TOTAL<21:0>> is assigned but never used.
Found 1022x32-bit ROM for signal <$n0002> created at line 1079.
Found 16x10-bit multiplier for signal <$n0003> created at line 1086.
Found 16x10-bit multiplier for signal <$n0004> created at line 1093.
Found 10-bit subtractor for signal <INDEX>.
Found 10-bit register for signal <NUMERATOR2>.
Found 26-bit register for signal <PRODUCT1>.
Found 26-bit register for signal <PRODUCT2>.
Found 32-bit register for signal <RECIPROCAL>.
Found 42-bit adder for signal <TOTAL>.
Summary:
inferred 1 ROM(s).
inferred 84 D-type flip-flop(s).
inferred 2 Adder/Subtractor(s).
inferred 2 Multiplier(s).
Unit <DIVIDER> synthesized.
 
 
Synthesizing Unit <FIFO_0>.
Related source file is "C:/Xilinx/bin/ArithmeticCoder/FIFO.vhd".
Found 256x8-bit dual-port distributed RAM for signal <GET_OUTPUT>.
-----------------------------------------------------------------------
| aspect ratio | 256-word x 8-bit | |
| clock | connected to signal <CLOCK> | rise |
| write enable | connected to signal <WRITE_ENABLE> | high |
| address | connected to signal <WRITE_ADDRESS> | |
| dual address | connected to signal <READ_ADDRESS> | |
| data in | connected to signal <DATA_IN> | |
| data out | not connected | |
| dual data out | connected to signal <DATA_OUT> | |
| ram_style | Auto | |
-----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronously. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
Found 8-bit comparator equal for signal <$n0003> created at line 69.
Found 8-bit up counter for signal <READ_ADDRESS>.
Found 8-bit up counter for signal <WRITE_ADDRESS>.
Summary:
inferred 1 RAM(s).
inferred 2 Counter(s).
inferred 1 Comparator(s).
Unit <FIFO_0> synthesized.
 
 
Synthesizing Unit <FIFO>.
Related source file is "C:/Xilinx/bin/ArithmeticCoder/FIFO.vhd".
Found 256x1-bit dual-port distributed RAM for signal <GET_OUTPUT>.
-----------------------------------------------------------------------
| aspect ratio | 256-word x 1-bit | |
| clock | connected to signal <CLOCK> | rise |
| write enable | connected to signal <WRITE_ENABLE> | high |
| address | connected to signal <WRITE_ADDRESS> | |
| dual address | connected to signal <READ_ADDRESS> | |
| data in | connected to signal <DATA_IN> | |
| data out | not connected | |
| dual data out | connected to signal <DATA_OUT> | |
| ram_style | Auto | |
-----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronously. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
Found 8-bit comparator equal for signal <$n0003> created at line 69.
Found 8-bit up counter for signal <READ_ADDRESS>.
Found 8-bit up counter for signal <WRITE_ADDRESS>.
Summary:
inferred 1 RAM(s).
inferred 2 Counter(s).
inferred 1 Comparator(s).
Unit <FIFO> synthesized.
 
 
Synthesizing Unit <CONTEXT_MANAGER>.
Related source file is "C:/Xilinx/bin/ArithmeticCoder/CONTEXT_MANAGER.vhd".
Found 46x20-bit dual-port block RAM for signal <PROBABILITY>.
-----------------------------------------------------------------------
| mode | write-first | |
| aspect ratio | 46-word x 20-bit | |
| clock | connected to signal <CLOCK> | rise |
| dual clock | connected to signal <CLOCK> | rise |
| dual enable | connected to signal <SET> | high |
| write enable | connected to signal <LOAD_DATA> | high |
| address | connected to signal <OLD_CONTEXT> | |
| dual address | connected to signal <CONTEXT_NUMBER> | |
| data in | connected to signal <NEWPROB> | |
| data out | not connected | |
| dual data out | connected to signal <RATIO> | |
| ram_style | Auto | |
-----------------------------------------------------------------------
Found 1-bit 64-to-1 multiplexer for signal <$n0003> created at line 141.
Found 1-bit register for signal <CONTEXT_VALID>.
Found 2-bit register for signal <DATA_READY>.
Found 6-bit register for signal <OLD_CONTEXT>.
Found 6-bit register for signal <READ_ADDRESS>.
Found 64-bit register for signal <RESET_FLAGS>.
Summary:
inferred 1 RAM(s).
inferred 79 D-type flip-flop(s).
inferred 1 Multiplexer(s).
Unit <CONTEXT_MANAGER> synthesized.
 
 
Synthesizing Unit <OUTPUT_UNIT>.
Related source file is "C:/Xilinx/bin/ArithmeticCoder/OUTPUT_UNIT.vhd".
Found 1-bit register for signal <DELAYED>.
Found 1-bit xor2 for signal <OUTVALUE>.
Summary:
inferred 1 D-type flip-flop(s).
Unit <OUTPUT_UNIT> synthesized.
 
 
Synthesizing Unit <FOLLOW_COUNTER>.
Related source file is "C:/Xilinx/bin/ArithmeticCoder/FOLLOW_COUNTER.vhd".
Found 8-bit comparator lessequal for signal <$n0003> created at line 30.
Found 8-bit comparator greater for signal <$n0004> created at line 39.
Found 8-bit updown counter for signal <NUMBER>.
Summary:
inferred 1 Counter(s).
inferred 2 Comparator(s).
Unit <FOLLOW_COUNTER> synthesized.
 
 
Synthesizing Unit <CONVERGENCE_CHECK>.
Related source file is "C:/Xilinx/bin/ArithmeticCoder/CONVERGENCE_CHECK.vhd".
Unit <CONVERGENCE_CHECK> synthesized.
 
 
Synthesizing Unit <ARITHMETIC_UNIT>.
Related source file is "C:/Xilinx/bin/ArithmeticCoder/ARITHMETIC_UNIT.vhd".
WARNING:Xst:646 - Signal <PRODUCT<9:0>> is assigned but never used.
WARNING:Xst:646 - Signal <DIFFERENCE3<16>> is assigned but never used.
WARNING:Xst:646 - Signal <DIFFERENCE4<16>> is assigned but never used.
WARNING:Xst:646 - Signal <RESULT0<16>> is assigned but never used.
Found 17x10-bit multiplier for signal <$n0000> created at line 48.
Found 1-bit register for signal <DELAY1>.
Found 17-bit register for signal <DIFFERENCE1>.
Found 17-bit adder for signal <DIFFERENCE2>.
Found 17-bit subtractor for signal <DIFFERENCE3>.
Found 17-bit subtractor for signal <DIFFERENCE4>.
Found 17-bit register for signal <LOW2>.
Found 27-bit register for signal <PRODUCT>.
Found 17-bit adder for signal <RESULT>.
Found 17-bit subtractor for signal <RESULT0>.
Summary:
inferred 62 D-type flip-flop(s).
inferred 5 Adder/Subtractor(s).
inferred 1 Multiplier(s).
Unit <ARITHMETIC_UNIT> synthesized.
 
 
Synthesizing Unit <LIMIT_REGISTER_0>.
Related source file is "C:/Xilinx/bin/ArithmeticCoder/REGISTER.vhd".
Found 16-bit register for signal <Q>.
Summary:
inferred 16 D-type flip-flop(s).
Unit <LIMIT_REGISTER_0> synthesized.
 
 
Synthesizing Unit <LIMIT_REGISTER>.
Related source file is "C:/Xilinx/bin/ArithmeticCoder/REGISTER.vhd".
Found 16-bit register for signal <Q>.
Summary:
inferred 16 D-type flip-flop(s).
Unit <LIMIT_REGISTER> synthesized.
 
 
Synthesizing Unit <INPUT_CONTROL_0>.
Related source file is "C:/Xilinx/bin/ArithmeticCoder/INPUT_CONTROL.vhd".
Found 8-bit register for signal <HELD>.
Found 8-bit 4-to-1 multiplexer for signal <OUTPUT>.
Summary:
inferred 8 D-type flip-flop(s).
inferred 8 Multiplexer(s).
Unit <INPUT_CONTROL_0> synthesized.
 
 
Synthesizing Unit <INPUT_CONTROL>.
Related source file is "C:/Xilinx/bin/ArithmeticCoder/INPUT_CONTROL.vhd".
Found 1-bit register for signal <HELD<0>>.
Found 1-bit 4-to-1 multiplexer for signal <OUTPUT<0>>.
Summary:
inferred 1 D-type flip-flop(s).
inferred 1 Multiplexer(s).
Unit <INPUT_CONTROL> synthesized.
 
 
Synthesizing Unit <arithmeticcoder>.
Related source file is "C:/Xilinx/bin/ArithmeticCoder/ARITHMETICCODER.vhd".
WARNING:Xst:646 - Signal <HIGH_OUT<13:0>> is assigned but never used.
Found 1-bit register for signal <ALLOWHALVING>.
Found 1-bit register for signal <DELAYED_CHECK>.
Found 1-bit register for signal <FLUSH_ENCODER>.
Found 1-bit register for signal <HOLDCONTEXT>.
Found 1-bit register for signal <LOCK>.
Summary:
inferred 5 D-type flip-flop(s).
Unit <arithmeticcoder> synthesized.
 
INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
 
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
 
Advanced RAM inference ...
INFO:Xst:1647 - Data output of ROM <Mrom__n0002> in block <DIVIDER> is tied to register <RECIPROCAL> in block <DIVIDER>.
INFO:Xst:1650 - The register is removed and the ROM is implemented as read-only block RAM.
Advanced multiplier inference ...
Found registered multiplier on signal <_n0000>:
- 1 register level(s) found in a register connected to the multiplier macro ouput.
Pushing register(s) into the multiplier macro.
Found registered multiplier on signal <_n0003>:
- 1 register level(s) found in a register connected to the multiplier macro ouput.
Pushing register(s) into the multiplier macro.
Found registered multiplier on signal <_n0004>:
- 1 register level(s) found in a register connected to the multiplier macro ouput.
Pushing register(s) into the multiplier macro.
Advanced Registered AddSub inference ...
Dynamic shift register inference ...
 
=========================================================================
HDL Synthesis Report
 
Macro Statistics
# Block RAMs : 2
1022x32-bit single-port block RAM : 1
46x20-bit dual-port block RAM : 1
# LUT RAMs : 2
256x1-bit dual-port distributed RAM: 1
256x8-bit dual-port distributed RAM: 1
# Multipliers : 3
16x10-bit registered multiplier : 2
17x10-bit registered multiplier : 1
# Adders/Subtractors : 59
10-bit adder : 6
10-bit subtractor : 1
17-bit adder : 2
17-bit subtractor : 3
3-bit addsub : 46
42-bit adder : 1
# Counters : 5
8-bit up counter : 4
8-bit updown counter : 1
# Registers : 184
1-bit register : 125
10-bit register : 8
17-bit register : 2
3-bit register : 46
6-bit register : 2
8-bit register : 1
# Comparators : 6
10-bit comparator greater : 1
3-bit comparator greater : 1
8-bit comparator equal : 2
8-bit comparator greater : 1
8-bit comparator lessequal : 1
# Multiplexers : 52
1-bit 4-to-1 multiplexer : 1
1-bit 64-to-1 multiplexer : 1
10-bit 4-to-1 multiplexer : 2
3-bit 4-to-1 multiplexer : 46
3-bit 46-to-1 multiplexer : 1
8-bit 4-to-1 multiplexer : 1
# Xors : 2
1-bit xor2 : 2
 
=========================================================================
 
=========================================================================
* Low Level Synthesis *
=========================================================================
WARNING:Xst:1710 - FF/Latch <LOW2_16> (without init value) has a constant value of 0 in block <ARITHMETIC_UNIT>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <DIFFERENCE1_16> (without init value) has a constant value of 0 in block <ARITHMETIC_UNIT>.
WARNING:Xst:1988 - Unit <FOLLOW_COUNTER>: instances <Mcompar__n0004>, <Mcompar__n0003> of unit <LPM_COMPARE_5> and unit <LPM_COMPARE_4> are dual, second instance is removed
 
Optimizing unit <arithmeticcoder> ...
 
Optimizing unit <CONTEXT_MANAGER> ...
 
Optimizing unit <CONVERGENCE_CHECK> ...
 
Optimizing unit <INPUT_CONTROL_0> ...
 
Optimizing unit <INPUT_CONTROL> ...
 
Optimizing unit <HALVING_MANAGER> ...
 
Optimizing unit <UPDATER> ...
 
Optimizing unit <DIVIDER> ...
 
Optimizing unit <FIFO_0> ...
 
Optimizing unit <FIFO> ...
 
Optimizing unit <FOLLOW_COUNTER> ...
 
Optimizing unit <OUTPUT_UNIT> ...
 
Optimizing unit <ARITHMETIC_UNIT> ...
 
Optimizing unit <LIMIT_REGISTER_0> ...
 
Optimizing unit <LIMIT_REGISTER> ...
Loading device for application Rf_Device from file '2v2000.nph' in environment C:/Xilinx.
 
Mapping all equations...
WARNING:Xst:637 - Naming conflict between signal DATA_OUT<7> of unit CONTEXT_BUFFER and signal CONTEXT_BUFFER_DATA_OUT<7> of unit arithmeticcoder : renaming CONTEXT_BUFFER_DATA_OUT<7> to CONTEXT_BUFFER_DATA_OUT<7>1.
WARNING:Xst:637 - Naming conflict between signal DATA_OUT<6> of unit CONTEXT_BUFFER and signal CONTEXT_BUFFER_DATA_OUT<6> of unit arithmeticcoder : renaming CONTEXT_BUFFER_DATA_OUT<6> to CONTEXT_BUFFER_DATA_OUT<6>1.
WARNING:Xst:637 - Naming conflict between signal DATA_OUT<5> of unit CONTEXT_BUFFER and signal CONTEXT_BUFFER_DATA_OUT<5> of unit arithmeticcoder : renaming CONTEXT_BUFFER_DATA_OUT<5> to CONTEXT_BUFFER_DATA_OUT<5>1.
WARNING:Xst:637 - Naming conflict between signal DATA_OUT<4> of unit CONTEXT_BUFFER and signal CONTEXT_BUFFER_DATA_OUT<4> of unit arithmeticcoder : renaming CONTEXT_BUFFER_DATA_OUT<4> to CONTEXT_BUFFER_DATA_OUT<4>1.
WARNING:Xst:637 - Naming conflict between signal DATA_OUT<3> of unit CONTEXT_BUFFER and signal CONTEXT_BUFFER_DATA_OUT<3> of unit arithmeticcoder : renaming CONTEXT_BUFFER_DATA_OUT<3> to CONTEXT_BUFFER_DATA_OUT<3>1.
WARNING:Xst:637 - Naming conflict between signal DATA_OUT<2> of unit CONTEXT_BUFFER and signal CONTEXT_BUFFER_DATA_OUT<2> of unit arithmeticcoder : renaming CONTEXT_BUFFER_DATA_OUT<2> to CONTEXT_BUFFER_DATA_OUT<2>1.
WARNING:Xst:637 - Naming conflict between signal DATA_OUT<1> of unit CONTEXT_BUFFER and signal CONTEXT_BUFFER_DATA_OUT<1> of unit arithmeticcoder : renaming CONTEXT_BUFFER_DATA_OUT<1> to CONTEXT_BUFFER_DATA_OUT<1>1.
WARNING:Xst:637 - Naming conflict between signal DATA_OUT<0> of unit CONTEXT_BUFFER and signal CONTEXT_BUFFER_DATA_OUT<0> of unit arithmeticcoder : renaming CONTEXT_BUFFER_DATA_OUT<0> to CONTEXT_BUFFER_DATA_OUT<0>1.
WARNING:Xst:637 - Naming conflict between signal SHIFT_ALL of unit DIFFERENCE and signal DIFFERENCE_SHIFT_ALL of unit arithmeticcoder : renaming DIFFERENCE_SHIFT_ALL to DIFFERENCE_SHIFT_ALL1.
Building and optimizing final netlist ...
Register <PROBABILITY_PROBUPDATE_UPDATE> equivalent to <PROBABILITY_DATA_READY_0> has been removed
Register <PROBABILITY_DIVISION_NUMERATOR2_7> equivalent to <PROBABILITY_PROBUPDATE_NUMERATOR1_7> has been removed
Register <PROBABILITY_DIVISION_NUMERATOR2_9> equivalent to <PROBABILITY_PROBUPDATE_NUMERATOR1_9> has been removed
Register <PROBABILITY_DIVISION_NUMERATOR2_8> equivalent to <PROBABILITY_PROBUPDATE_NUMERATOR1_8> has been removed
Register <PROBABILITY_DIVISION_NUMERATOR2_0> equivalent to <PROBABILITY_PROBUPDATE_NUMERATOR1_0> has been removed
Register <PROBABILITY_DIVISION_NUMERATOR2_1> equivalent to <PROBABILITY_PROBUPDATE_NUMERATOR1_1> has been removed
Register <PROBABILITY_DIVISION_NUMERATOR2_2> equivalent to <PROBABILITY_PROBUPDATE_NUMERATOR1_2> has been removed
Register <PROBABILITY_DIVISION_NUMERATOR2_3> equivalent to <PROBABILITY_PROBUPDATE_NUMERATOR1_3> has been removed
Register <PROBABILITY_DIVISION_NUMERATOR2_4> equivalent to <PROBABILITY_PROBUPDATE_NUMERATOR1_4> has been removed
Register <PROBABILITY_DIVISION_NUMERATOR2_5> equivalent to <PROBABILITY_PROBUPDATE_NUMERATOR1_5> has been removed
Register <PROBABILITY_DIVISION_NUMERATOR2_6> equivalent to <PROBABILITY_PROBUPDATE_NUMERATOR1_6> has been removed
Found area constraint ratio of 100 (+ 5) on block arithmeticcoder, actual ratio is 6.
FlipFlop ARITH_DELAY1 has been replicated 1 time(s)
FlipFlop CONTEXT_BUFFER_STORAGE_READ_ADDRESS_0 has been replicated 14 time(s)
FlipFlop CONTEXT_BUFFER_STORAGE_READ_ADDRESS_1 has been replicated 14 time(s)
FlipFlop CONTEXT_BUFFER_STORAGE_READ_ADDRESS_2 has been replicated 14 time(s)
FlipFlop CONTEXT_BUFFER_STORAGE_READ_ADDRESS_3 has been replicated 14 time(s)
FlipFlop CONTEXT_BUFFER_STORAGE_READ_ADDRESS_4 has been replicated 7 time(s)
FlipFlop CONTEXT_BUFFER_STORAGE_READ_ADDRESS_5 has been replicated 2 time(s)
FlipFlop CONTEXT_BUFFER_STORAGE_WRITE_ADDRESS_0 has been replicated 1 time(s)
FlipFlop CONTEXT_BUFFER_STORAGE_WRITE_ADDRESS_1 has been replicated 1 time(s)
FlipFlop CONTEXT_BUFFER_STORAGE_WRITE_ADDRESS_2 has been replicated 1 time(s)
FlipFlop CONTEXT_BUFFER_STORAGE_WRITE_ADDRESS_3 has been replicated 1 time(s)
FlipFlop CONTEXT_BUFFER_STORAGE_WRITE_ADDRESS_4 has been replicated 1 time(s)
FlipFlop CONTEXT_BUFFER_STORAGE_WRITE_ADDRESS_5 has been replicated 1 time(s)
FlipFlop INBUFFER_STORAGE_WRITE_ADDRESS_0 has been replicated 1 time(s)
FlipFlop INBUFFER_STORAGE_WRITE_ADDRESS_1 has been replicated 1 time(s)
FlipFlop INBUFFER_STORAGE_WRITE_ADDRESS_2 has been replicated 1 time(s)
FlipFlop INBUFFER_STORAGE_WRITE_ADDRESS_3 has been replicated 1 time(s)
 
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : arithmeticcoder.ngr
Top Level Output File Name : arithmeticcoder
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
 
Design Statistics
# IOs : 16
 
Macro Statistics :
# RAM : 4
# 1022x32-bit single-port block RAM: 1
# 256x1-bit dual-port distributed RAM: 1
# 256x8-bit dual-port distributed RAM: 1
# 46x20-bit dual-port block RAM: 1
# Registers : 261
# 1-bit register : 205
# 17-bit register : 2
# 3-bit register : 46
# 6-bit register : 2
# 8-bit register : 6
# Multiplexers : 52
# 1-bit 4-to-1 multiplexer : 1
# 1-bit 64-to-1 multiplexer : 1
# 10-bit 4-to-1 multiplexer : 2
# 3-bit 4-to-1 multiplexer : 46
# 3-bit 46-to-1 multiplexer : 1
# 8-bit 4-to-1 multiplexer : 1
# Adders/Subtractors : 18
# 10-bit adder : 6
# 10-bit subtractor : 1
# 17-bit adder : 2
# 17-bit subtractor : 3
# 42-bit adder : 1
# 8-bit adder : 5
# Multipliers : 3
# 16x10-bit registered multiplier: 2
# 17x10-bit registered multiplier: 1
# Comparators : 6
# 10-bit comparator greater : 1
# 3-bit comparator greater : 1
# 8-bit comparator equal : 2
# 8-bit comparator greater : 1
# 8-bit comparator lessequal : 1
# Xors : 92
# 1-bit xor3 : 92
 
Cell Usage :
# BELS : 1489
# GND : 1
# INV : 36
# LUT1 : 64
# LUT1_L : 9
# LUT2 : 60
# LUT2_D : 2
# LUT2_L : 2
# LUT3 : 108
# LUT3_D : 10
# LUT3_L : 246
# LUT4 : 272
# LUT4_D : 33
# LUT4_L : 158
# MUXCY : 196
# MUXF5 : 69
# MUXF6 : 23
# MUXF7 : 10
# MUXF8 : 5
# VCC : 1
# XORCY : 184
# FlipFlops/Latches : 500
# FD : 7
# FDE : 86
# FDR : 50
# FDRE : 281
# FDRSE : 2
# FDS : 7
# FDSE : 67
# RAMS : 39
# RAM64X1D : 36
# RAMB16_S18 : 2
# RAMB16_S36_S36 : 1
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 15
# IBUF : 12
# OBUF : 3
# MULTs : 3
# MULT18X18S : 3
=========================================================================
 
Device utilization summary:
---------------------------
 
Selected Device : 2v2000bg575-6
 
Number of Slices: 750 out of 10752 6%
Number of Slice Flip Flops: 500 out of 21504 2%
Number of 4 input LUTs: 1108 out of 21504 5%
Number of bonded IOBs: 16 out of 408 3%
Number of BRAMs: 3 out of 56 5%
Number of MULT18X18s: 3 out of 56 5%
Number of GCLKs: 1 out of 16 6%
 
 
=========================================================================
TIMING REPORT
 
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
 
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
CLOCK | BUFGP | 540 |
-----------------------------------+------------------------+-------+
 
Timing Summary:
---------------
Speed Grade: -6
 
Minimum period: 16.221ns (Maximum Frequency: 61.648MHz)
Minimum input arrival time before clock: 15.527ns
Maximum output required time after clock: 8.122ns
Maximum combinational path delay: 7.764ns
 
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
 
=========================================================================
Timing constraint: Default period analysis for Clock 'CLOCK'
Clock period: 16.221ns (frequency: 61.648MHz)
Total number of paths / destination ports: 30998811 / 1448
-------------------------------------------------------------------------
Delay: 16.221ns (Levels of Logic = 30)
Source: INBUFFER_STORAGE_READ_ADDRESS_1 (FF)
Destination: PROBABILITY_PROBUPDATE_NUMERATOR4_9 (FF)
Source Clock: CLOCK rising
Destination Clock: CLOCK rising
 
Data Path: INBUFFER_STORAGE_READ_ADDRESS_1 to PROBABILITY_PROBUPDATE_NUMERATOR4_9
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDRE:C->Q 18 0.449 0.788 INBUFFER_STORAGE_READ_ADDRESS_1 (INBUFFER_STORAGE_READ_ADDRESS_1)
LUT4_L:I3->LO 1 0.347 0.000 INBUFFER_STORAGE_Eq_stagelut (INBUFFER_STORAGE_N4)
MUXCY:S->O 1 0.235 0.000 INBUFFER_STORAGE_Eq_stagecy (INBUFFER_STORAGE_Eq_stage_cyo)
MUXCY:CI->O 1 0.042 0.000 INBUFFER_STORAGE_Eq_stagecy_rn_0 (INBUFFER_STORAGE_Eq_stage_cyo1)
MUXCY:CI->O 1 0.042 0.000 INBUFFER_STORAGE_Eq_stagecy_rn_1 (INBUFFER_STORAGE_Eq_stage_cyo2)
MUXCY:CI->O 10 0.601 0.819 INBUFFER_STORAGE_Eq_stagecy_rn_2 (INBUFFER_FIFO_EMPTY)
LUT2:I1->O 1 0.347 0.547 BUFFER_INPUT1_SW1 (N827)
LUT4_D:I1->O 12 0.347 0.715 INBUFFER_SENDING1 (DATA_AVAILABLE)
LUT4:I2->O 8 0.347 0.653 CONTEXT_BUFFER_Ker01 (CONTEXT_BUFFER_N01)
LUT4_D:I3->O 6 0.347 0.613 CONTEXT_BUFFER_DATA_OUT<6>_SW0_SW0 (N829)
LUT3:I2->O 9 0.347 0.665 CONTEXT_BUFFER_DATA_OUT<6>_2 (CONTEXT_BUFFER_DATA_OUT<6>_1)
LUT3_L:I2->LO 1 0.347 0.000 PROBABILITY_REFRESH_CONTEXT<4>3 (PROBABILITY_REFRESH_MUX_BLOCK_N4)
MUXF5:I0->O 1 0.345 0.000 PROBABILITY_REFRESH_CONTEXT<1>_rn_0 (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<1>_MUXF51)
MUXF6:I0->O 1 0.354 0.000 PROBABILITY_REFRESH_CONTEXT<0> (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<0>_MUXF6)
MUXF7:I1->O 1 0.354 0.000 PROBABILITY_REFRESH_CONTEXT<2> (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<2>_MUXF7)
MUXF8:I1->O 1 0.354 0.548 PROBABILITY_REFRESH_CONTEXT<3> (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<3>_MUXF8)
LUT4_D:I1->LO 1 0.347 0.132 PROBABILITY_REFRESH__n0241106 (N969)
LUT4:I3->O 11 0.347 0.699 PROBABILITY_REFRESH__n0241109_1 (PROBABILITY_REFRESH__n0241109)
LUT4_D:I2->LO 2 0.347 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<0>lut (N979)
MUXCY:S->O 1 0.235 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<0>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<0>_cyo)
MUXCY:CI->O 1 0.042 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<1>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<1>_cyo)
MUXCY:CI->O 1 0.042 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<2>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<2>_cyo)
MUXCY:CI->O 1 0.042 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<3>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<3>_cyo)
MUXCY:CI->O 1 0.042 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<4>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<4>_cyo)
MUXCY:CI->O 1 0.042 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<5>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<5>_cyo)
MUXCY:CI->O 1 0.042 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<6>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<6>_cyo)
MUXCY:CI->O 1 0.042 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<7>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<7>_cyo)
XORCY:CI->O 2 0.824 0.744 PROBABILITY_PROBUPDATE_UPDATER__n0013<8>_xor (PROBABILITY_PROBUPDATE__n0013<8>)
LUT1_L:I0->LO 1 0.347 0.000 PROBABILITY_PROBUPDATE__n0013<8>_rt (PROBABILITY_PROBUPDATE__n0013<8>_rt)
MUXCY:S->O 0 0.235 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0011<8>cy (PROBABILITY_PROBUPDATE_UPDATER__n0011<8>_cyo)
XORCY:CI->O 1 0.824 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0011<9>_xor (PROBABILITY_PROBUPDATE__n0011<9>)
FDR:D 0.293 PROBABILITY_PROBUPDATE_NUMERATOR4_9
----------------------------------------
Total 16.221ns (9.298ns logic, 6.923ns route)
(57.3% logic, 42.7% route)
 
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLOCK'
Total number of paths / destination ports: 1938326 / 1222
-------------------------------------------------------------------------
Offset: 15.527ns (Levels of Logic = 26)
Source: RESET (PAD)
Destination: PROBABILITY_PROBUPDATE_NUMERATOR4_9 (FF)
Destination Clock: CLOCK rising
 
Data Path: RESET to PROBABILITY_PROBUPDATE_NUMERATOR4_9
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 475 0.653 1.877 RESET_IBUF (RESET_IBUF)
LUT4:I0->O 8 0.347 0.648 OUTPUT_SENDING1 (SENDING_OBUF)
LUT4_D:I2->O 12 0.347 0.715 INBUFFER_SENDING1 (DATA_AVAILABLE)
LUT4:I2->O 8 0.347 0.653 CONTEXT_BUFFER_Ker01 (CONTEXT_BUFFER_N01)
LUT4_D:I3->O 6 0.347 0.613 CONTEXT_BUFFER_DATA_OUT<6>_SW0_SW0 (N829)
LUT3:I2->O 9 0.347 0.665 CONTEXT_BUFFER_DATA_OUT<6>_2 (CONTEXT_BUFFER_DATA_OUT<6>_1)
LUT3_L:I2->LO 1 0.347 0.000 PROBABILITY_REFRESH_CONTEXT<4>3 (PROBABILITY_REFRESH_MUX_BLOCK_N4)
MUXF5:I0->O 1 0.345 0.000 PROBABILITY_REFRESH_CONTEXT<1>_rn_0 (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<1>_MUXF51)
MUXF6:I0->O 1 0.354 0.000 PROBABILITY_REFRESH_CONTEXT<0> (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<0>_MUXF6)
MUXF7:I1->O 1 0.354 0.000 PROBABILITY_REFRESH_CONTEXT<2> (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<2>_MUXF7)
MUXF8:I1->O 1 0.354 0.548 PROBABILITY_REFRESH_CONTEXT<3> (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<3>_MUXF8)
LUT4_D:I1->LO 1 0.347 0.132 PROBABILITY_REFRESH__n0241106 (N969)
LUT4:I3->O 11 0.347 0.699 PROBABILITY_REFRESH__n0241109_1 (PROBABILITY_REFRESH__n0241109)
LUT4_D:I2->LO 2 0.347 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<0>lut (N979)
MUXCY:S->O 1 0.235 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<0>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<0>_cyo)
MUXCY:CI->O 1 0.042 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<1>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<1>_cyo)
MUXCY:CI->O 1 0.042 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<2>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<2>_cyo)
MUXCY:CI->O 1 0.042 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<3>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<3>_cyo)
MUXCY:CI->O 1 0.042 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<4>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<4>_cyo)
MUXCY:CI->O 1 0.042 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<5>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<5>_cyo)
MUXCY:CI->O 1 0.042 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<6>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<6>_cyo)
MUXCY:CI->O 1 0.042 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<7>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<7>_cyo)
XORCY:CI->O 2 0.824 0.744 PROBABILITY_PROBUPDATE_UPDATER__n0013<8>_xor (PROBABILITY_PROBUPDATE__n0013<8>)
LUT1_L:I0->LO 1 0.347 0.000 PROBABILITY_PROBUPDATE__n0013<8>_rt (PROBABILITY_PROBUPDATE__n0013<8>_rt)
MUXCY:S->O 0 0.235 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0011<8>cy (PROBABILITY_PROBUPDATE_UPDATER__n0011<8>_cyo)
XORCY:CI->O 1 0.824 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0011<9>_xor (PROBABILITY_PROBUPDATE__n0011<9>)
FDR:D 0.293 PROBABILITY_PROBUPDATE_NUMERATOR4_9
----------------------------------------
Total 15.527ns (8.235ns logic, 7.292ns route)
(53.0% logic, 47.0% route)
 
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLOCK'
Total number of paths / destination ports: 44 / 3
-------------------------------------------------------------------------
Offset: 8.122ns (Levels of Logic = 5)
Source: OUTPUT_DELAYED (FF)
Destination: DATA_OUT (PAD)
Source Clock: CLOCK rising
 
Data Path: OUTPUT_DELAYED to DATA_OUT
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 20 0.449 0.934 OUTPUT_DELAYED (OUTPUT_DELAYED)
LUT2_L:I1->LO 1 0.347 0.127 CONVERGENCE_TEST1 (CONVERGENCE_TEST)
LUT4:I2->O 2 0.347 0.684 TRIGGER_OUTPUT1 (TRIGGER_OUTPUT)
LUT2:I1->O 1 0.347 0.414 OUTPUT_DATA_OUT1 (OUTPUT_N0)
LUT4:I3->O 1 0.347 0.383 OUTPUT_DATA_OUT2 (DATA_OUT_OBUF)
OBUF:I->O 3.743 DATA_OUT_OBUF (DATA_OUT)
----------------------------------------
Total 8.122ns (5.580ns logic, 2.542ns route)
(68.7% logic, 31.3% route)
 
=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Delay: 7.764ns (Levels of Logic = 4)
Source: RESET (PAD)
Destination: DATA_OUT (PAD)
 
Data Path: RESET to DATA_OUT
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 475 0.653 1.877 RESET_IBUF (RESET_IBUF)
LUT2:I0->O 1 0.347 0.414 OUTPUT_DATA_OUT1 (OUTPUT_N0)
LUT4:I3->O 1 0.347 0.383 OUTPUT_DATA_OUT2 (DATA_OUT_OBUF)
OBUF:I->O 3.743 DATA_OUT_OBUF (DATA_OUT)
----------------------------------------
Total 7.764ns (5.090ns logic, 2.674ns route)
(65.6% logic, 34.4% route)
 
=========================================================================
CPU : 34.83 / 35.22 s | Elapsed : 35.00 / 35.00 s
-->
 
Total memory usage is 130364 kilobytes
 
Number of errors : 0 ( 0 filtered)
Number of warnings : 27 ( 0 filtered)
Number of infos : 5 ( 0 filtered)
 
trunk/docs/synthesis_reports/encoder/arithmeticcoder.syr Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/docs/synthesis_reports/encoder/output_unit.syr =================================================================== --- trunk/docs/synthesis_reports/encoder/output_unit.syr (nonexistent) +++ trunk/docs/synthesis_reports/encoder/output_unit.syr (revision 9) @@ -0,0 +1,315 @@ +Release 7.1.04i - xst H.42 +Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. +--> Parameter TMPDIR set to __projnav +CPU : 0.00 / 0.33 s | Elapsed : 0.00 / 1.00 s + +--> Parameter xsthdpdir set to ./xst +CPU : 0.00 / 0.33 s | Elapsed : 0.00 / 1.00 s + +--> Reading design: output_unit.prj + +TABLE OF CONTENTS + 1) Synthesis Options Summary + 2) HDL Compilation + 3) HDL Analysis + 4) HDL Synthesis + 5) Advanced HDL Synthesis + 5.1) HDL Synthesis Report + 6) Low Level Synthesis + 7) Final Report + 7.1) Device utilization summary + 7.2) TIMING REPORT + + +========================================================================= +* Synthesis Options Summary * +========================================================================= +---- Source Parameters +Input File Name : "output_unit.prj" +Input Format : mixed +Ignore Synthesis Constraint File : NO + +---- Target Parameters +Output File Name : "output_unit" +Output Format : NGC +Target Device : xc2v2000-6-bg575 + +---- Source Options +Top Module Name : output_unit +Automatic FSM Extraction : YES +FSM Encoding Algorithm : Auto +FSM Style : lut +RAM Extraction : Yes +RAM Style : Auto +ROM Extraction : Yes +ROM Style : Auto +Mux Extraction : YES +Mux Style : Auto +Decoder Extraction : YES +Priority Encoder Extraction : YES +Shift Register Extraction : YES +Logical Shifter Extraction : YES +XOR Collapsing : YES +Resource Sharing : YES +Multiplier Style : auto +Automatic Register Balancing : No + +---- Target Options +Add IO Buffers : YES +Global Maximum Fanout : 500 +Add Generic Clock Buffer(BUFG) : 16 +Register Duplication : YES +Equivalent register Removal : YES +Slice Packing : YES +Pack IO Registers into IOBs : auto + +---- General Options +Optimization Goal : Speed +Optimization Effort : 2 +Keep Hierarchy : NO +Global Optimization : AllClockNets +RTL Output : Yes +Write Timing Constraints : NO +Hierarchy Separator : _ +Bus Delimiter : <> +Case Specifier : maintain +Slice Utilization Ratio : 100 +Slice Utilization Ratio Delta : 5 + +---- Other Options +lso : output_unit.lso +Read Cores : YES +cross_clock_analysis : NO +verilog2001 : YES +safe_implementation : No +Optimize Instantiated Primitives : NO +tristate2logic : Yes +use_clock_enable : Yes +use_sync_set : Yes +use_sync_reset : Yes +enable_auto_floorplanning : No + +========================================================================= + + +========================================================================= +* HDL Compilation * +========================================================================= +Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/OUTPUT_UNIT.vhd" in Library work. +Architecture rtl of Entity output_unit is up to date. + +========================================================================= +* HDL Analysis * +========================================================================= +Analyzing Entity (Architecture ). +Entity analyzed. Unit generated. + + +========================================================================= +* HDL Synthesis * +========================================================================= + +Synthesizing Unit . + Related source file is "C:/Xilinx/bin/ArithmeticCoder/OUTPUT_UNIT.vhd". + Found 1-bit register for signal . + Found 1-bit xor2 for signal . + Summary: + inferred 1 D-type flip-flop(s). +Unit synthesized. + + +========================================================================= +* Advanced HDL Synthesis * +========================================================================= + +Advanced RAM inference ... +Advanced multiplier inference ... +Advanced Registered AddSub inference ... +Dynamic shift register inference ... + +========================================================================= +HDL Synthesis Report + +Macro Statistics +# Registers : 1 + 1-bit register : 1 +# Xors : 1 + 1-bit xor2 : 1 + +========================================================================= + +========================================================================= +* Low Level Synthesis * +========================================================================= + +Optimizing unit ... +Loading device for application Rf_Device from file '2v2000.nph' in environment C:/Xilinx. + +Mapping all equations... +Building and optimizing final netlist ... +Found area constraint ratio of 100 (+ 5) on block output_unit, actual ratio is 0. + +========================================================================= +* Final Report * +========================================================================= +Final Results +RTL Top Level Output File Name : output_unit.ngr +Top Level Output File Name : output_unit +Output Format : NGC +Optimization Goal : Speed +Keep Hierarchy : NO + +Design Statistics +# IOs : 9 + +Macro Statistics : +# Registers : 1 +# 1-bit register : 1 + +Cell Usage : +# BELS : 4 +# LUT2 : 2 +# LUT4 : 1 +# LUT4_D : 1 +# FlipFlops/Latches : 1 +# FD : 1 +# Clock Buffers : 1 +# BUFGP : 1 +# IO Buffers : 8 +# IBUF : 4 +# OBUF : 4 +========================================================================= + +Device utilization summary: +--------------------------- + +Selected Device : 2v2000bg575-6 + + Number of Slices: 2 out of 10752 0% + Number of Slice Flip Flops: 1 out of 21504 0% + Number of 4 input LUTs: 4 out of 21504 0% + Number of bonded IOBs: 9 out of 408 2% + Number of GCLKs: 1 out of 16 6% + + +========================================================================= +TIMING REPORT + +NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. + FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT + GENERATED AFTER PLACE-and-ROUTE. + +Clock Information: +------------------ +-----------------------------------+------------------------+-------+ +Clock Signal | Clock buffer(FF name) | Load | +-----------------------------------+------------------------+-------+ +CLOCK | BUFGP | 1 | +-----------------------------------+------------------------+-------+ + +Timing Summary: +--------------- +Speed Grade: -6 + + Minimum period: 1.673ns (Maximum Frequency: 597.550MHz) + Minimum input arrival time before clock: 2.053ns + Maximum output required time after clock: 5.699ns + Maximum combinational path delay: 6.630ns + +Timing Detail: +-------------- +All values displayed in nanoseconds (ns) + +========================================================================= +Timing constraint: Default period analysis for Clock 'CLOCK' + Clock period: 1.673ns (frequency: 597.550MHz) + Total number of paths / destination ports: 1 / 1 +------------------------------------------------------------------------- +Delay: 1.673ns (Levels of Logic = 1) + Source: DELAYED (FF) + Destination: DELAYED (FF) + Source Clock: CLOCK rising + Destination Clock: CLOCK rising + + Data Path: DELAYED to DELAYED + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FD:C->Q 4 0.449 0.584 DELAYED (DELAYED) + LUT4_D:I3->LO 1 0.347 0.000 SENDING1 (N3) + FD:D 0.293 DELAYED + ---------------------------------------- + Total 1.673ns (1.089ns logic, 0.584ns route) + (65.1% logic, 34.9% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'CLOCK' + Total number of paths / destination ports: 3 / 1 +------------------------------------------------------------------------- +Offset: 2.053ns (Levels of Logic = 2) + Source: FOLLOW (PAD) + Destination: DELAYED (FF) + Destination Clock: CLOCK rising + + Data Path: FOLLOW to DELAYED + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 3 0.653 0.761 FOLLOW_IBUF (FOLLOW_IBUF) + LUT4_D:I0->LO 1 0.347 0.000 SENDING1 (N3) + FD:D 0.293 DELAYED + ---------------------------------------- + Total 2.053ns (1.293ns logic, 0.761ns route) + (63.0% logic, 37.0% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'CLOCK' + Total number of paths / destination ports: 4 / 4 +------------------------------------------------------------------------- +Offset: 5.699ns (Levels of Logic = 2) + Source: DELAYED (FF) + Destination: SHIFT (PAD) + Source Clock: CLOCK rising + + Data Path: DELAYED to SHIFT + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FD:C->Q 4 0.449 0.778 DELAYED (DELAYED) + LUT2:I0->O 1 0.347 0.383 SHIFT1 (SHIFT_OBUF) + OBUF:I->O 3.743 SHIFT_OBUF (SHIFT) + ---------------------------------------- + Total 5.699ns (4.539ns logic, 1.160ns route) + (79.6% logic, 20.4% route) + +========================================================================= +Timing constraint: Default path analysis + Total number of paths / destination ports: 8 / 3 +------------------------------------------------------------------------- +Delay: 6.630ns (Levels of Logic = 4) + Source: RESET (PAD) + Destination: DATA_OUT (PAD) + + Data Path: RESET to DATA_OUT + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 2 0.653 0.743 RESET_IBUF (RESET_IBUF) + LUT2:I0->O 1 0.347 0.414 DATA_OUT1 (N0) + LUT4:I3->O 1 0.347 0.383 DATA_OUT2 (DATA_OUT_OBUF) + OBUF:I->O 3.743 DATA_OUT_OBUF (DATA_OUT) + ---------------------------------------- + Total 6.630ns (5.090ns logic, 1.540ns route) + (76.8% logic, 23.2% route) + +========================================================================= +CPU : 4.45 / 4.81 s | Elapsed : 4.00 / 5.00 s + +--> + +Total memory usage is 120124 kilobytes + +Number of errors : 0 ( 0 filtered) +Number of warnings : 0 ( 0 filtered) +Number of infos : 0 ( 0 filtered) +
trunk/docs/synthesis_reports/encoder/output_unit.syr Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/docs/synthesis_reports/encoder/follow_counter.syr =================================================================== --- trunk/docs/synthesis_reports/encoder/follow_counter.syr (nonexistent) +++ trunk/docs/synthesis_reports/encoder/follow_counter.syr (revision 9) @@ -0,0 +1,339 @@ +Release 7.1.04i - xst H.42 +Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. +--> Parameter TMPDIR set to __projnav +CPU : 0.00 / 0.33 s | Elapsed : 0.00 / 0.00 s + +--> Parameter xsthdpdir set to ./xst +CPU : 0.00 / 0.33 s | Elapsed : 0.00 / 0.00 s + +--> Reading design: follow_counter.prj + +TABLE OF CONTENTS + 1) Synthesis Options Summary + 2) HDL Compilation + 3) HDL Analysis + 4) HDL Synthesis + 5) Advanced HDL Synthesis + 5.1) HDL Synthesis Report + 6) Low Level Synthesis + 7) Final Report + 7.1) Device utilization summary + 7.2) TIMING REPORT + + +========================================================================= +* Synthesis Options Summary * +========================================================================= +---- Source Parameters +Input File Name : "follow_counter.prj" +Input Format : mixed +Ignore Synthesis Constraint File : NO + +---- Target Parameters +Output File Name : "follow_counter" +Output Format : NGC +Target Device : xc2v2000-6-bg575 + +---- Source Options +Top Module Name : follow_counter +Automatic FSM Extraction : YES +FSM Encoding Algorithm : Auto +FSM Style : lut +RAM Extraction : Yes +RAM Style : Auto +ROM Extraction : Yes +ROM Style : Auto +Mux Extraction : YES +Mux Style : Auto +Decoder Extraction : YES +Priority Encoder Extraction : YES +Shift Register Extraction : YES +Logical Shifter Extraction : YES +XOR Collapsing : YES +Resource Sharing : YES +Multiplier Style : auto +Automatic Register Balancing : No + +---- Target Options +Add IO Buffers : YES +Global Maximum Fanout : 500 +Add Generic Clock Buffer(BUFG) : 16 +Register Duplication : YES +Equivalent register Removal : YES +Slice Packing : YES +Pack IO Registers into IOBs : auto + +---- General Options +Optimization Goal : Speed +Optimization Effort : 2 +Keep Hierarchy : NO +Global Optimization : AllClockNets +RTL Output : Yes +Write Timing Constraints : NO +Hierarchy Separator : _ +Bus Delimiter : <> +Case Specifier : maintain +Slice Utilization Ratio : 100 +Slice Utilization Ratio Delta : 5 + +---- Other Options +lso : follow_counter.lso +Read Cores : YES +cross_clock_analysis : NO +verilog2001 : YES +safe_implementation : No +Optimize Instantiated Primitives : NO +tristate2logic : Yes +use_clock_enable : Yes +use_sync_set : Yes +use_sync_reset : Yes +enable_auto_floorplanning : No + +========================================================================= + + +========================================================================= +* HDL Compilation * +========================================================================= +Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/FOLLOW_COUNTER.vhd" in Library work. +Architecture rtl of Entity follow_counter is up to date. + +========================================================================= +* HDL Analysis * +========================================================================= +Analyzing Entity (Architecture ). +Entity analyzed. Unit generated. + + +========================================================================= +* HDL Synthesis * +========================================================================= + +Synthesizing Unit . + Related source file is "C:/Xilinx/bin/ArithmeticCoder/FOLLOW_COUNTER.vhd". + Found 8-bit comparator lessequal for signal <$n0003> created at line 30. + Found 8-bit comparator greater for signal <$n0004> created at line 39. + Found 8-bit updown counter for signal . + Summary: + inferred 1 Counter(s). + inferred 2 Comparator(s). +Unit synthesized. + + +========================================================================= +* Advanced HDL Synthesis * +========================================================================= + +Advanced RAM inference ... +Advanced multiplier inference ... +Advanced Registered AddSub inference ... +Dynamic shift register inference ... + +========================================================================= +HDL Synthesis Report + +Macro Statistics +# Counters : 1 + 8-bit updown counter : 1 +# Comparators : 2 + 8-bit comparator greater : 1 + 8-bit comparator lessequal : 1 + +========================================================================= + +========================================================================= +* Low Level Synthesis * +========================================================================= +WARNING:Xst:1988 - Unit : instances , of unit and unit are dual, second instance is removed + +Optimizing unit ... +Loading device for application Rf_Device from file '2v2000.nph' in environment C:/Xilinx. + +Mapping all equations... +Building and optimizing final netlist ... +Found area constraint ratio of 100 (+ 5) on block follow_counter, actual ratio is 0. + +========================================================================= +* Final Report * +========================================================================= +Final Results +RTL Top Level Output File Name : follow_counter.ngr +Top Level Output File Name : follow_counter +Output Format : NGC +Optimization Goal : Speed +Keep Hierarchy : NO + +Design Statistics +# IOs : 5 + +Macro Statistics : +# Registers : 1 +# 8-bit register : 1 +# Adders/Subtractors : 1 +# 8-bit addsub : 1 +# Comparators : 2 +# 8-bit comparator greater : 1 +# 8-bit comparator lessequal : 1 + +Cell Usage : +# BELS : 29 +# LUT2 : 3 +# LUT3 : 1 +# LUT3_L : 8 +# LUT4 : 1 +# LUT4_D : 1 +# MUXCY : 7 +# XORCY : 8 +# FlipFlops/Latches : 8 +# FDRE : 8 +# Clock Buffers : 1 +# BUFGP : 1 +# IO Buffers : 4 +# IBUF : 3 +# OBUF : 1 +========================================================================= + +Device utilization summary: +--------------------------- + +Selected Device : 2v2000bg575-6 + + Number of Slices: 7 out of 10752 0% + Number of Slice Flip Flops: 8 out of 21504 0% + Number of 4 input LUTs: 14 out of 21504 0% + Number of bonded IOBs: 5 out of 408 1% + Number of GCLKs: 1 out of 16 6% + + +========================================================================= +TIMING REPORT + +NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. + FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT + GENERATED AFTER PLACE-and-ROUTE. + +Clock Information: +------------------ +-----------------------------------+------------------------+-------+ +Clock Signal | Clock buffer(FF name) | Load | +-----------------------------------+------------------------+-------+ +CLOCK | BUFGP | 8 | +-----------------------------------+------------------------+-------+ + +Timing Summary: +--------------- +Speed Grade: -6 + + Minimum period: 3.586ns (Maximum Frequency: 278.901MHz) + Minimum input arrival time before clock: 3.673ns + Maximum output required time after clock: 7.321ns + Maximum combinational path delay: 6.022ns + +Timing Detail: +-------------- +All values displayed in nanoseconds (ns) + +========================================================================= +Timing constraint: Default period analysis for Clock 'CLOCK' + Clock period: 3.586ns (frequency: 278.901MHz) + Total number of paths / destination ports: 128 / 16 +------------------------------------------------------------------------- +Delay: 3.586ns (Levels of Logic = 3) + Source: NUMBER_2 (FF) + Destination: NUMBER_6 (FF) + Source Clock: CLOCK rising + Destination Clock: CLOCK rising + + Data Path: NUMBER_2 to NUMBER_6 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDRE:C->Q 2 0.449 0.743 NUMBER_2 (NUMBER_2) + LUT4:I0->O 1 0.347 0.414 _n000419 (CHOICE19) + LUT4_D:I3->LO 1 0.347 0.127 _n0004112 (N15) + LUT3:I2->O 8 0.347 0.621 _n00091 (_n0009) + FDRE:CE 0.190 NUMBER_0 + ---------------------------------------- + Total 3.586ns (1.680ns logic, 1.905ns route) + (46.9% logic, 53.1% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'CLOCK' + Total number of paths / destination ports: 112 / 24 +------------------------------------------------------------------------- +Offset: 3.673ns (Levels of Logic = 10) + Source: INCREMENT (PAD) + Destination: NUMBER_7 (FF) + Destination Clock: CLOCK rising + + Data Path: INCREMENT to NUMBER_7 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 10 0.653 0.879 INCREMENT_IBUF (INCREMENT_IBUF) + LUT2:I0->O 1 0.347 0.383 NUMBER__n00021 (NUMBER__n0002) + MUXCY:CI->O 1 0.042 0.000 follow_counter_NUMBER__n0000<0>cy (follow_counter_NUMBER__n0000<0>_cyo) + MUXCY:CI->O 1 0.042 0.000 follow_counter_NUMBER__n0000<1>cy (follow_counter_NUMBER__n0000<1>_cyo) + MUXCY:CI->O 1 0.042 0.000 follow_counter_NUMBER__n0000<2>cy (follow_counter_NUMBER__n0000<2>_cyo) + MUXCY:CI->O 1 0.042 0.000 follow_counter_NUMBER__n0000<3>cy (follow_counter_NUMBER__n0000<3>_cyo) + MUXCY:CI->O 1 0.042 0.000 follow_counter_NUMBER__n0000<4>cy (follow_counter_NUMBER__n0000<4>_cyo) + MUXCY:CI->O 1 0.042 0.000 follow_counter_NUMBER__n0000<5>cy (follow_counter_NUMBER__n0000<5>_cyo) + MUXCY:CI->O 0 0.042 0.000 follow_counter_NUMBER__n0000<6>cy (follow_counter_NUMBER__n0000<6>_cyo) + XORCY:CI->O 1 0.824 0.000 follow_counter_NUMBER__n0000<7>_xor (NUMBER__n0000<7>) + FDRE:D 0.293 NUMBER_7 + ---------------------------------------- + Total 3.673ns (2.411ns logic, 1.262ns route) + (65.6% logic, 34.4% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'CLOCK' + Total number of paths / destination ports: 8 / 1 +------------------------------------------------------------------------- +Offset: 7.321ns (Levels of Logic = 4) + Source: NUMBER_2 (FF) + Destination: OUTPUT (PAD) + Source Clock: CLOCK rising + + Data Path: NUMBER_2 to OUTPUT + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDRE:C->Q 2 0.449 0.743 NUMBER_2 (NUMBER_2) + LUT4:I0->O 1 0.347 0.415 _n000419 (CHOICE19) + LUT4_D:I3->O 1 0.347 0.548 _n0004112 (_n0004) + LUT2:I1->O 1 0.347 0.383 _n00021 (OUTPUT_OBUF) + OBUF:I->O 3.743 OUTPUT_OBUF (OUTPUT) + ---------------------------------------- + Total 7.321ns (5.233ns logic, 2.088ns route) + (71.5% logic, 28.5% route) + +========================================================================= +Timing constraint: Default path analysis + Total number of paths / destination ports: 1 / 1 +------------------------------------------------------------------------- +Delay: 6.022ns (Levels of Logic = 3) + Source: TEST (PAD) + Destination: OUTPUT (PAD) + + Data Path: TEST to OUTPUT + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 11 0.653 0.897 TEST_IBUF (TEST_IBUF) + LUT2:I0->O 1 0.347 0.383 _n00021 (OUTPUT_OBUF) + OBUF:I->O 3.743 OUTPUT_OBUF (OUTPUT) + ---------------------------------------- + Total 6.022ns (4.743ns logic, 1.279ns route) + (78.8% logic, 21.2% route) + +========================================================================= +CPU : 4.63 / 4.98 s | Elapsed : 5.00 / 5.00 s + +--> + +Total memory usage is 121148 kilobytes + +Number of errors : 0 ( 0 filtered) +Number of warnings : 1 ( 0 filtered) +Number of infos : 0 ( 0 filtered) +
trunk/docs/synthesis_reports/encoder/follow_counter.syr Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/docs/synthesis_reports/decoder/storage_register.syr =================================================================== --- trunk/docs/synthesis_reports/decoder/storage_register.syr (nonexistent) +++ trunk/docs/synthesis_reports/decoder/storage_register.syr (revision 9) @@ -0,0 +1,298 @@ +Release 7.1.04i - xst H.42 +Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. +--> Parameter TMPDIR set to __projnav +CPU : 0.00 / 0.33 s | Elapsed : 0.00 / 0.00 s + +--> Parameter xsthdpdir set to ./xst +CPU : 0.00 / 0.33 s | Elapsed : 0.00 / 0.00 s + +--> Reading design: storage_register.prj + +TABLE OF CONTENTS + 1) Synthesis Options Summary + 2) HDL Compilation + 3) HDL Analysis + 4) HDL Synthesis + 5) Advanced HDL Synthesis + 5.1) HDL Synthesis Report + 6) Low Level Synthesis + 7) Final Report + 7.1) Device utilization summary + 7.2) TIMING REPORT + + +========================================================================= +* Synthesis Options Summary * +========================================================================= +---- Source Parameters +Input File Name : "storage_register.prj" +Input Format : mixed +Ignore Synthesis Constraint File : NO + +---- Target Parameters +Output File Name : "storage_register" +Output Format : NGC +Target Device : xc2v250-6-cs144 + +---- Source Options +Top Module Name : storage_register +Automatic FSM Extraction : YES +FSM Encoding Algorithm : Auto +FSM Style : lut +RAM Extraction : Yes +RAM Style : Auto +ROM Extraction : Yes +ROM Style : Auto +Mux Extraction : YES +Mux Style : Auto +Decoder Extraction : YES +Priority Encoder Extraction : YES +Shift Register Extraction : YES +Logical Shifter Extraction : YES +XOR Collapsing : YES +Resource Sharing : YES +Multiplier Style : auto +Automatic Register Balancing : No + +---- Target Options +Add IO Buffers : YES +Global Maximum Fanout : 500 +Add Generic Clock Buffer(BUFG) : 16 +Register Duplication : YES +Equivalent register Removal : YES +Slice Packing : YES +Pack IO Registers into IOBs : auto + +---- General Options +Optimization Goal : Speed +Optimization Effort : 1 +Keep Hierarchy : NO +Global Optimization : AllClockNets +RTL Output : Yes +Write Timing Constraints : NO +Hierarchy Separator : _ +Bus Delimiter : <> +Case Specifier : maintain +Slice Utilization Ratio : 100 +Slice Utilization Ratio Delta : 5 + +---- Other Options +lso : storage_register.lso +Read Cores : YES +cross_clock_analysis : NO +verilog2001 : YES +safe_implementation : No +Optimize Instantiated Primitives : NO +tristate2logic : Yes +use_clock_enable : Yes +use_sync_set : Yes +use_sync_reset : Yes +enable_auto_floorplanning : No + +========================================================================= + + +========================================================================= +* HDL Compilation * +========================================================================= +Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/STORAGE_REGISTER.vhd" in Library work. +Architecture rtl of Entity storage_register is up to date. + +========================================================================= +* HDL Analysis * +========================================================================= +Analyzing Entity (Architecture ). +Entity analyzed. Unit generated. + + +========================================================================= +* HDL Synthesis * +========================================================================= + +Synthesizing Unit . + Related source file is "C:/Xilinx/bin/ArithmeticDecoder/STORAGE_REGISTER.vhd". + Found 16-bit 4-to-1 multiplexer for signal <$n0001>. + Found 16-bit register for signal . + Summary: + inferred 16 D-type flip-flop(s). + inferred 16 Multiplexer(s). +Unit synthesized. + + +========================================================================= +* Advanced HDL Synthesis * +========================================================================= + +Advanced RAM inference ... +Advanced multiplier inference ... +Advanced Registered AddSub inference ... +Dynamic shift register inference ... + +========================================================================= +HDL Synthesis Report + +Macro Statistics +# Registers : 1 + 16-bit register : 1 +# Multiplexers : 1 + 16-bit 4-to-1 multiplexer : 1 + +========================================================================= + +========================================================================= +* Low Level Synthesis * +========================================================================= + +Optimizing unit ... +Loading device for application Rf_Device from file '2v250.nph' in environment C:/Xilinx. + +Mapping all equations... +Building and optimizing final netlist ... +Found area constraint ratio of 100 (+ 5) on block storage_register, actual ratio is 0. +FlipFlop Q_0 has been replicated 1 time(s) to handle iob=true attribute. + +========================================================================= +* Final Report * +========================================================================= +Final Results +RTL Top Level Output File Name : storage_register.ngr +Top Level Output File Name : storage_register +Output Format : NGC +Optimization Goal : Speed +Keep Hierarchy : NO + +Design Statistics +# IOs : 38 + +Macro Statistics : +# Registers : 1 +# 16-bit register : 1 +# Multiplexers : 1 +# 16-bit 4-to-1 multiplexer : 1 + +Cell Usage : +# BELS : 18 +# LUT3 : 2 +# LUT3_L : 16 +# FlipFlops/Latches : 17 +# FDRE : 17 +# Clock Buffers : 1 +# BUFGP : 1 +# IO Buffers : 37 +# IBUF : 21 +# OBUF : 16 +========================================================================= + +Device utilization summary: +--------------------------- + +Selected Device : 2v250cs144-6 + + Number of Slices: 10 out of 1536 0% + Number of Slice Flip Flops: 17 out of 3072 0% + Number of 4 input LUTs: 18 out of 3072 0% + Number of bonded IOBs: 38 out of 92 41% + Number of GCLKs: 1 out of 16 6% + + +========================================================================= +TIMING REPORT + +NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. + FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT + GENERATED AFTER PLACE-and-ROUTE. + +Clock Information: +------------------ +-----------------------------------+------------------------+-------+ +Clock Signal | Clock buffer(FF name) | Load | +-----------------------------------+------------------------+-------+ +CLOCK | BUFGP | 17 | +-----------------------------------+------------------------+-------+ + +Timing Summary: +--------------- +Speed Grade: -6 + + Minimum period: 2.247ns (Maximum Frequency: 445.137MHz) + Minimum input arrival time before clock: 2.911ns + Maximum output required time after clock: 4.711ns + Maximum combinational path delay: No path found + +Timing Detail: +-------------- +All values displayed in nanoseconds (ns) + +========================================================================= +Timing constraint: Default period analysis for Clock 'CLOCK' + Clock period: 2.247ns (frequency: 445.137MHz) + Total number of paths / destination ports: 16 / 15 +------------------------------------------------------------------------- +Delay: 2.247ns (Levels of Logic = 2) + Source: Q_15 (FF) + Destination: Q_15 (FF) + Source Clock: CLOCK rising + Destination Clock: CLOCK rising + + Data Path: Q_15 to Q_15 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDRE:C->Q 2 0.449 0.684 Q_15 (Q_15) + LUT3_L:I1->LO 1 0.347 0.127 _n0001<15>1 (N13) + LUT3_L:I2->LO 1 0.347 0.000 _n0001<15>2 (_n0001<15>) + FDRE:D 0.293 Q_15 + ---------------------------------------- + Total 2.247ns (1.436ns logic, 0.811ns route) + (63.9% logic, 36.1% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'CLOCK' + Total number of paths / destination ports: 105 / 51 +------------------------------------------------------------------------- +Offset: 2.911ns (Levels of Logic = 2) + Source: SET_VALUE (PAD) + Destination: Q_14 (FF) + Destination Clock: CLOCK rising + + Data Path: SET_VALUE to Q_14 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 17 0.653 0.973 SET_VALUE_IBUF (SET_VALUE_IBUF) + LUT3:I0->O 17 0.347 0.748 _n00051 (_n0005) + FDRE:CE 0.190 Q_0 + ---------------------------------------- + Total 2.911ns (1.190ns logic, 1.721ns route) + (40.9% logic, 59.1% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'CLOCK' + Total number of paths / destination ports: 16 / 16 +------------------------------------------------------------------------- +Offset: 4.711ns (Levels of Logic = 1) + Source: Q_15 (FF) + Destination: OUTPUT<15> (PAD) + Source Clock: CLOCK rising + + Data Path: Q_15 to OUTPUT<15> + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDRE:C->Q 2 0.449 0.518 Q_15 (Q_15) + OBUF:I->O 3.743 OUTPUT_15_OBUF (OUTPUT<15>) + ---------------------------------------- + Total 4.711ns (4.192ns logic, 0.518ns route) + (89.0% logic, 11.0% route) + +========================================================================= +CPU : 4.30 / 4.66 s | Elapsed : 4.00 / 4.00 s + +--> + +Total memory usage is 100604 kilobytes + +Number of errors : 0 ( 0 filtered) +Number of warnings : 0 ( 0 filtered) +Number of infos : 0 ( 0 filtered) +
trunk/docs/synthesis_reports/decoder/storage_register.syr Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/docs/synthesis_reports/decoder/symbol_detector.syr =================================================================== --- trunk/docs/synthesis_reports/decoder/symbol_detector.syr (nonexistent) +++ trunk/docs/synthesis_reports/decoder/symbol_detector.syr (revision 9) @@ -0,0 +1,256 @@ +Release 7.1.04i - xst H.42 +Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. +--> Parameter TMPDIR set to __projnav +CPU : 0.00 / 0.34 s | Elapsed : 0.00 / 0.00 s + +--> Parameter xsthdpdir set to ./xst +CPU : 0.00 / 0.34 s | Elapsed : 0.00 / 0.00 s + +--> Reading design: symbol_detector.prj + +TABLE OF CONTENTS + 1) Synthesis Options Summary + 2) HDL Compilation + 3) HDL Analysis + 4) HDL Synthesis + 5) Advanced HDL Synthesis + 5.1) HDL Synthesis Report + 6) Low Level Synthesis + 7) Final Report + 7.1) Device utilization summary + 7.2) TIMING REPORT + + +========================================================================= +* Synthesis Options Summary * +========================================================================= +---- Source Parameters +Input File Name : "symbol_detector.prj" +Input Format : mixed +Ignore Synthesis Constraint File : NO + +---- Target Parameters +Output File Name : "symbol_detector" +Output Format : NGC +Target Device : xc2v250-6-cs144 + +---- Source Options +Top Module Name : symbol_detector +Automatic FSM Extraction : YES +FSM Encoding Algorithm : Auto +FSM Style : lut +RAM Extraction : Yes +RAM Style : Auto +ROM Extraction : Yes +ROM Style : Auto +Mux Extraction : YES +Mux Style : Auto +Decoder Extraction : YES +Priority Encoder Extraction : YES +Shift Register Extraction : YES +Logical Shifter Extraction : YES +XOR Collapsing : YES +Resource Sharing : YES +Multiplier Style : auto +Automatic Register Balancing : No + +---- Target Options +Add IO Buffers : YES +Global Maximum Fanout : 500 +Add Generic Clock Buffer(BUFG) : 16 +Register Duplication : YES +Equivalent register Removal : YES +Slice Packing : YES +Pack IO Registers into IOBs : auto + +---- General Options +Optimization Goal : Speed +Optimization Effort : 1 +Keep Hierarchy : NO +Global Optimization : AllClockNets +RTL Output : Yes +Write Timing Constraints : NO +Hierarchy Separator : _ +Bus Delimiter : <> +Case Specifier : maintain +Slice Utilization Ratio : 100 +Slice Utilization Ratio Delta : 5 + +---- Other Options +lso : symbol_detector.lso +Read Cores : YES +cross_clock_analysis : NO +verilog2001 : YES +safe_implementation : No +Optimize Instantiated Primitives : NO +tristate2logic : Yes +use_clock_enable : Yes +use_sync_set : Yes +use_sync_reset : Yes +enable_auto_floorplanning : No + +========================================================================= + + +========================================================================= +* HDL Compilation * +========================================================================= +Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/SYMBOL_DETECTOR.vhd" in Library work. +Architecture rtl of Entity symbol_detector is up to date. + +========================================================================= +* HDL Analysis * +========================================================================= +Analyzing Entity (Architecture ). +Entity analyzed. Unit generated. + + +========================================================================= +* HDL Synthesis * +========================================================================= + +Synthesizing Unit . + Related source file is "C:/Xilinx/bin/ArithmeticDecoder/SYMBOL_DETECTOR.vhd". + Found 16-bit comparator greatequal for signal <$n0001> created at line 23. + Summary: + inferred 1 Comparator(s). +Unit synthesized. + + +========================================================================= +* Advanced HDL Synthesis * +========================================================================= + +Advanced RAM inference ... +Advanced multiplier inference ... +Advanced Registered AddSub inference ... +Dynamic shift register inference ... + +========================================================================= +HDL Synthesis Report + +Macro Statistics +# Comparators : 1 + 16-bit comparator greatequal : 1 + +========================================================================= + +========================================================================= +* Low Level Synthesis * +========================================================================= + +Optimizing unit ... +Loading device for application Rf_Device from file '2v250.nph' in environment C:/Xilinx. + +Mapping all equations... +Building and optimizing final netlist ... +Found area constraint ratio of 100 (+ 5) on block symbol_detector, actual ratio is 0. + +========================================================================= +* Final Report * +========================================================================= +Final Results +RTL Top Level Output File Name : symbol_detector.ngr +Top Level Output File Name : symbol_detector +Output Format : NGC +Optimization Goal : Speed +Keep Hierarchy : NO + +Design Statistics +# IOs : 34 + +Macro Statistics : +# Comparators : 1 +# 16-bit comparator greatequal: 1 + +Cell Usage : +# BELS : 34 +# LUT2 : 17 +# MUXCY : 16 +# VCC : 1 +# IO Buffers : 34 +# IBUF : 33 +# OBUF : 1 +========================================================================= + +Device utilization summary: +--------------------------- + +Selected Device : 2v250cs144-6 + + Number of Slices: 9 out of 1536 0% + Number of 4 input LUTs: 17 out of 3072 0% + Number of bonded IOBs: 34 out of 92 36% + + +========================================================================= +TIMING REPORT + +NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. + FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT + GENERATED AFTER PLACE-and-ROUTE. + +Clock Information: +------------------ +No clock signals found in this design + +Timing Summary: +--------------- +Speed Grade: -6 + + Minimum period: No path found + Minimum input arrival time before clock: No path found + Maximum output required time after clock: No path found + Maximum combinational path delay: 8.052ns + +Timing Detail: +-------------- +All values displayed in nanoseconds (ns) + +========================================================================= +Timing constraint: Default path analysis + Total number of paths / destination ports: 49 / 1 +------------------------------------------------------------------------- +Delay: 8.052ns (Levels of Logic = 20) + Source: DATA_IN<0> (PAD) + Destination: DATA_OUT (PAD) + + Data Path: DATA_IN<0> to DATA_OUT + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 1 0.653 0.608 DATA_IN_0_IBUF (DATA_IN_0_IBUF) + LUT2:I0->O 1 0.347 0.000 XNor_stagelut (N2) + MUXCY:S->O 1 0.235 0.000 XNor_stagecy (XNor_stage_cyo) + MUXCY:CI->O 1 0.042 0.000 XNor_stagecy_rn_0 (XNor_stage_cyo1) + MUXCY:CI->O 1 0.042 0.000 XNor_stagecy_rn_1 (XNor_stage_cyo2) + MUXCY:CI->O 1 0.042 0.000 XNor_stagecy_rn_2 (XNor_stage_cyo3) + MUXCY:CI->O 1 0.042 0.000 XNor_stagecy_rn_3 (XNor_stage_cyo4) + MUXCY:CI->O 1 0.042 0.000 XNor_stagecy_rn_4 (XNor_stage_cyo5) + MUXCY:CI->O 1 0.042 0.000 XNor_stagecy_rn_5 (XNor_stage_cyo6) + MUXCY:CI->O 1 0.042 0.000 XNor_stagecy_rn_6 (XNor_stage_cyo7) + MUXCY:CI->O 1 0.042 0.000 XNor_stagecy_rn_7 (XNor_stage_cyo8) + MUXCY:CI->O 1 0.042 0.000 XNor_stagecy_rn_8 (XNor_stage_cyo9) + MUXCY:CI->O 1 0.042 0.000 XNor_stagecy_rn_9 (XNor_stage_cyo10) + MUXCY:CI->O 1 0.042 0.000 XNor_stagecy_rn_10 (XNor_stage_cyo11) + MUXCY:CI->O 1 0.042 0.000 XNor_stagecy_rn_11 (XNor_stage_cyo12) + MUXCY:CI->O 1 0.042 0.000 XNor_stagecy_rn_12 (XNor_stage_cyo13) + MUXCY:CI->O 1 0.042 0.000 XNor_stagecy_rn_13 (XNor_stage_cyo14) + MUXCY:CI->O 1 0.601 0.548 XNor_stagecy_rn_14 (_n0001) + LUT2:I1->O 1 0.347 0.383 _n00001 (DATA_OUT_OBUF) + OBUF:I->O 3.743 DATA_OUT_OBUF (DATA_OUT) + ---------------------------------------- + Total 8.052ns (6.514ns logic, 1.538ns route) + (80.9% logic, 19.1% route) + +========================================================================= +CPU : 4.19 / 4.56 s | Elapsed : 4.00 / 4.00 s + +--> + +Total memory usage is 100604 kilobytes + +Number of errors : 0 ( 0 filtered) +Number of warnings : 0 ( 0 filtered) +Number of infos : 0 ( 0 filtered) +
trunk/docs/synthesis_reports/decoder/symbol_detector.syr Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/docs/synthesis_reports/decoder/arithmeticdecoder.syr =================================================================== --- trunk/docs/synthesis_reports/decoder/arithmeticdecoder.syr (nonexistent) +++ trunk/docs/synthesis_reports/decoder/arithmeticdecoder.syr (revision 9) @@ -0,0 +1,788 @@ +Release 7.1.04i - xst H.42 +Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. +--> Parameter TMPDIR set to __projnav +CPU : 0.00 / 2.34 s | Elapsed : 0.00 / 2.00 s + +--> Parameter xsthdpdir set to ./xst +CPU : 0.00 / 2.34 s | Elapsed : 0.00 / 2.00 s + +--> Reading design: arithmeticdecoder.prj + +TABLE OF CONTENTS + 1) Synthesis Options Summary + 2) HDL Compilation + 3) HDL Analysis + 4) HDL Synthesis + 5) Advanced HDL Synthesis + 5.1) HDL Synthesis Report + 6) Low Level Synthesis + 7) Final Report + 7.1) Device utilization summary + 7.2) TIMING REPORT + + +========================================================================= +* Synthesis Options Summary * +========================================================================= +---- Source Parameters +Input File Name : "arithmeticdecoder.prj" +Input Format : mixed +Ignore Synthesis Constraint File : NO + +---- Target Parameters +Output File Name : "arithmeticdecoder" +Output Format : NGC +Target Device : xc2v250-6-cs144 + +---- Source Options +Top Module Name : arithmeticdecoder +Automatic FSM Extraction : YES +FSM Encoding Algorithm : Auto +FSM Style : lut +RAM Extraction : Yes +RAM Style : Auto +ROM Extraction : Yes +ROM Style : Auto +Mux Extraction : YES +Mux Style : Auto +Decoder Extraction : YES +Priority Encoder Extraction : YES +Shift Register Extraction : YES +Logical Shifter Extraction : YES +XOR Collapsing : YES +Resource Sharing : YES +Multiplier Style : auto +Automatic Register Balancing : No + +---- Target Options +Add IO Buffers : YES +Global Maximum Fanout : 500 +Add Generic Clock Buffer(BUFG) : 16 +Register Duplication : YES +Equivalent register Removal : YES +Slice Packing : YES +Pack IO Registers into IOBs : auto + +---- General Options +Optimization Goal : Speed +Optimization Effort : 1 +Keep Hierarchy : NO +Global Optimization : AllClockNets +RTL Output : Yes +Write Timing Constraints : NO +Hierarchy Separator : _ +Bus Delimiter : <> +Case Specifier : maintain +Slice Utilization Ratio : 100 +Slice Utilization Ratio Delta : 5 + +---- Other Options +lso : arithmeticdecoder.lso +Read Cores : YES +cross_clock_analysis : NO +verilog2001 : YES +safe_implementation : No +Optimize Instantiated Primitives : NO +tristate2logic : Yes +use_clock_enable : Yes +use_sync_set : Yes +use_sync_reset : Yes +enable_auto_floorplanning : No + +========================================================================= + + +========================================================================= +* HDL Compilation * +========================================================================= +Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/Divider.vhd" in Library work. +Architecture rtl of Entity divider is up to date. +Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/UPDATER.vhd" in Library work. +Architecture rtl of Entity updater is up to date. +Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd" in Library work. +Architecture rtl of Entity halving_manager is up to date. +Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/FIFO.vhd" in Library work. +Architecture rtl of Entity fifo is up to date. +Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/INPUT_CONTROL.vhd" in Library work. +Architecture rtl of Entity input_control is up to date. +Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/CONTEXT_MANAGER.vhd" in Library work. +Architecture rtl of Entity context_manager is up to date. +Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/STORAGE_REGISTER.vhd" in Library work. +Entity compiled. +Entity (Architecture ) compiled. +Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/ARITHMETIC_UNIT.vhd" in Library work. +Architecture rtl of Entity arithmetic_unit is up to date. +Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/CONVERGENCE_CHECK.vhd" in Library work. +Architecture rtl of Entity convergence_check is up to date. +Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/SYMBOL_DETECTOR.vhd" in Library work. +Architecture rtl of Entity symbol_detector is up to date. +Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/ARITHMETICDECODER.vhd" in Library work. +Entity compiled. +Entity (Architecture ) compiled. + +========================================================================= +* HDL Analysis * +========================================================================= +Analyzing Entity (Architecture ). +Entity analyzed. Unit generated. + +Analyzing generic Entity (Architecture ). + WIDTH = 1 +Entity analyzed. Unit generated. + +Analyzing generic Entity (Architecture ). + RANK = 8 + WIDTH = 1 +Entity analyzed. Unit generated. + +Analyzing Entity (Architecture ). +WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/CONTEXT_MANAGER.vhd" line 133: Index value(s) does not match array range, simulation mismatch. +WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/CONTEXT_MANAGER.vhd" line 137: Index value(s) does not match array range, simulation mismatch. +Entity analyzed. Unit generated. + +Analyzing Entity (Architecture ). +WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/Divider.vhd" line 1079: Index value(s) does not match array range, simulation mismatch. +Entity analyzed. Unit generated. + +Analyzing Entity (Architecture ). +Entity analyzed. Unit generated. + +Analyzing Entity (Architecture ). +WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd" line 71: Index value(s) does not match array range, simulation mismatch. +WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd" line 71: Index value(s) does not match array range, simulation mismatch. +WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd" line 73: Index value(s) does not match array range, simulation mismatch. +WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd" line 108: Index value(s) does not match array range, simulation mismatch. +Entity analyzed. Unit generated. + +Analyzing Entity (Architecture ). +Entity analyzed. Unit generated. + +Analyzing Entity (Architecture ). +Entity analyzed. Unit generated. + +Analyzing Entity (Architecture ). +Entity analyzed. Unit generated. + +Analyzing Entity (Architecture ). +Entity analyzed. Unit generated. + + +========================================================================= +* HDL Synthesis * +========================================================================= + +Synthesizing Unit . + Related source file is "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd". + Found 3-bit 46-to-1 multiplexer for signal <$n0002> created at line 108. + Found 3-bit 4-to-1 multiplexer for signal <$n0050>. + Found 3-bit 4-to-1 multiplexer for signal <$n0051>. + Found 3-bit 4-to-1 multiplexer for signal <$n0052>. + Found 3-bit 4-to-1 multiplexer for signal <$n0053>. + Found 3-bit 4-to-1 multiplexer for signal <$n0054>. + Found 3-bit 4-to-1 multiplexer for signal <$n0055>. + Found 3-bit 4-to-1 multiplexer for signal <$n0056>. + Found 3-bit 4-to-1 multiplexer for signal <$n0057>. + Found 3-bit 4-to-1 multiplexer for signal <$n0058>. + Found 3-bit 4-to-1 multiplexer for signal <$n0059>. + Found 3-bit 4-to-1 multiplexer for signal <$n0060>. + Found 3-bit 4-to-1 multiplexer for signal <$n0061>. + Found 3-bit 4-to-1 multiplexer for signal <$n0062>. + Found 3-bit 4-to-1 multiplexer for signal <$n0063>. + Found 3-bit 4-to-1 multiplexer for signal <$n0064>. + Found 3-bit 4-to-1 multiplexer for signal <$n0065>. + Found 3-bit 4-to-1 multiplexer for signal <$n0066>. + Found 3-bit 4-to-1 multiplexer for signal <$n0067>. + Found 3-bit 4-to-1 multiplexer for signal <$n0068>. + Found 3-bit 4-to-1 multiplexer for signal <$n0069>. + Found 3-bit 4-to-1 multiplexer for signal <$n0070>. + Found 3-bit 4-to-1 multiplexer for signal <$n0071>. + Found 3-bit 4-to-1 multiplexer for signal <$n0072>. + Found 3-bit 4-to-1 multiplexer for signal <$n0073>. + Found 3-bit 4-to-1 multiplexer for signal <$n0074>. + Found 3-bit 4-to-1 multiplexer for signal <$n0075>. + Found 3-bit 4-to-1 multiplexer for signal <$n0076>. + Found 3-bit 4-to-1 multiplexer for signal <$n0077>. + Found 3-bit 4-to-1 multiplexer for signal <$n0078>. + Found 3-bit 4-to-1 multiplexer for signal <$n0079>. + Found 3-bit 4-to-1 multiplexer for signal <$n0080>. + Found 3-bit 4-to-1 multiplexer for signal <$n0081>. + Found 3-bit 4-to-1 multiplexer for signal <$n0082>. + Found 3-bit 4-to-1 multiplexer for signal <$n0084>. + Found 3-bit 4-to-1 multiplexer for signal <$n0085>. + Found 3-bit 4-to-1 multiplexer for signal <$n0087>. + Found 3-bit 4-to-1 multiplexer for signal <$n0088>. + Found 3-bit 4-to-1 multiplexer for signal <$n0089>. + Found 3-bit 4-to-1 multiplexer for signal <$n0090>. + Found 3-bit 4-to-1 multiplexer for signal <$n0091>. + Found 3-bit 4-to-1 multiplexer for signal <$n0092>. + Found 3-bit 4-to-1 multiplexer for signal <$n0093>. + Found 3-bit 4-to-1 multiplexer for signal <$n0094>. + Found 3-bit 4-to-1 multiplexer for signal <$n0095>. + Found 3-bit 4-to-1 multiplexer for signal <$n0096>. + Found 3-bit 4-to-1 multiplexer for signal <$n0097>. + Found 3-bit addsub for signal <$n0098>. + Found 3-bit addsub for signal <$n0100>. + Found 3-bit addsub for signal <$n0101>. + Found 3-bit addsub for signal <$n0102>. + Found 3-bit addsub for signal <$n0103>. + Found 3-bit addsub for signal <$n0104>. + Found 3-bit addsub for signal <$n0105>. + Found 3-bit addsub for signal <$n0106>. + Found 3-bit addsub for signal <$n0107>. + Found 3-bit addsub for signal <$n0108>. + Found 3-bit addsub for signal <$n0109>. + Found 3-bit addsub for signal <$n0110>. + Found 3-bit addsub for signal <$n0111>. + Found 3-bit addsub for signal <$n0112>. + Found 3-bit addsub for signal <$n0113>. + Found 3-bit addsub for signal <$n0114>. + Found 3-bit addsub for signal <$n0115>. + Found 3-bit addsub for signal <$n0116>. + Found 3-bit addsub for signal <$n0117>. + Found 3-bit addsub for signal <$n0118>. + Found 3-bit addsub for signal <$n0119>. + Found 3-bit addsub for signal <$n0120>. + Found 3-bit addsub for signal <$n0121>. + Found 3-bit addsub for signal <$n0122>. + Found 3-bit addsub for signal <$n0123>. + Found 3-bit addsub for signal <$n0124>. + Found 3-bit addsub for signal <$n0125>. + Found 3-bit addsub for signal <$n0126>. + Found 3-bit addsub for signal <$n0127>. + Found 3-bit addsub for signal <$n0128>. + Found 3-bit addsub for signal <$n0129>. + Found 3-bit addsub for signal <$n0130>. + Found 3-bit addsub for signal <$n0131>. + Found 3-bit addsub for signal <$n0132>. + Found 3-bit addsub for signal <$n0133>. + Found 3-bit addsub for signal <$n0134>. + Found 3-bit addsub for signal <$n0135>. + Found 3-bit addsub for signal <$n0136>. + Found 3-bit addsub for signal <$n0137>. + Found 3-bit addsub for signal <$n0138>. + Found 3-bit addsub for signal <$n0139>. + Found 3-bit addsub for signal <$n0140>. + Found 3-bit addsub for signal <$n0141>. + Found 3-bit addsub for signal <$n0142>. + Found 3-bit addsub for signal <$n0143>. + Found 3-bit addsub for signal <$n0144>. + Found 10-bit comparator greater for signal <$n0147> created at line 99. + Found 3-bit comparator greater for signal <$n0241> created at line 108. + Found 1-bit register for signal . + Found 10-bit register for signal . + Found 10-bit adder for signal . + Found 10-bit register for signal . + Found 10-bit adder for signal . + Found 138-bit register for signal . + Summary: + inferred 139 D-type flip-flop(s). + inferred 48 Adder/Subtractor(s). + inferred 2 Comparator(s). + inferred 141 Multiplexer(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/UPDATER.vhd". +WARNING:Xst:1780 - Signal is never used or assigned. + Found 1-bit register for signal . + Found 10-bit 4-to-1 multiplexer for signal . + Found 10-bit 4-to-1 multiplexer for signal . + Found 10-bit adder for signal <$n0009> created at line 51. + Found 10-bit adder for signal <$n0011> created at line 73. + Found 10-bit adder for signal <$n0012> created at line 84. + Found 10-bit adder for signal <$n0013> created at line 62. + Found 10-bit register for signal . + Found 10-bit register for signal . + Found 10-bit register for signal . + Found 10-bit register for signal . + Found 10-bit register for signal . + Found 1-bit xor2 for signal . + Summary: + inferred 1 D-type flip-flop(s). + inferred 4 Adder/Subtractor(s). + inferred 20 Multiplexer(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/Divider.vhd". +WARNING:Xst:646 - Signal > is assigned but never used. +WARNING:Xst:646 - Signal > is assigned but never used. + Found 1022x32-bit ROM for signal <$n0002> created at line 1079. + Found 16x10-bit multiplier for signal <$n0003> created at line 1086. + Found 16x10-bit multiplier for signal <$n0004> created at line 1093. + Found 10-bit subtractor for signal . + Found 10-bit register for signal . + Found 26-bit register for signal . + Found 26-bit register for signal . + Found 32-bit register for signal . + Found 42-bit adder for signal . + Summary: + inferred 1 ROM(s). + inferred 84 D-type flip-flop(s). + inferred 2 Adder/Subtractor(s). + inferred 2 Multiplier(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/FIFO.vhd". + Found 256x1-bit dual-port distributed RAM for signal . + ----------------------------------------------------------------------- + | aspect ratio | 256-word x 1-bit | | + | clock | connected to signal | rise | + | write enable | connected to signal | high | + | address | connected to signal | | + | dual address | connected to signal | | + | data in | connected to signal | | + | data out | not connected | | + | dual data out | connected to signal | | + | ram_style | Auto | | + ----------------------------------------------------------------------- +INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronously. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + Found 8-bit comparator equal for signal <$n0003> created at line 69. + Found 8-bit up counter for signal . + Found 8-bit up counter for signal . + Summary: + inferred 1 RAM(s). + inferred 2 Counter(s). + inferred 1 Comparator(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "C:/Xilinx/bin/ArithmeticDecoder/SYMBOL_DETECTOR.vhd". + Found 16-bit comparator greatequal for signal <$n0001> created at line 23. + Summary: + inferred 1 Comparator(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "C:/Xilinx/bin/ArithmeticDecoder/CONVERGENCE_CHECK.vhd". +Unit synthesized. + + +Synthesizing Unit . + Related source file is "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/ARITHMETIC_UNIT.vhd". +WARNING:Xst:646 - Signal > is assigned but never used. +WARNING:Xst:646 - Signal > is assigned but never used. +WARNING:Xst:646 - Signal > is assigned but never used. +WARNING:Xst:646 - Signal > is assigned but never used. + Found 17x10-bit multiplier for signal <$n0000> created at line 48. + Found 1-bit register for signal . + Found 17-bit register for signal . + Found 17-bit adder for signal . + Found 17-bit subtractor for signal . + Found 17-bit subtractor for signal . + Found 17-bit register for signal . + Found 27-bit register for signal . + Found 17-bit adder for signal . + Found 17-bit subtractor for signal . + Summary: + inferred 62 D-type flip-flop(s). + inferred 5 Adder/Subtractor(s). + inferred 1 Multiplier(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "C:/Xilinx/bin/ArithmeticDecoder/STORAGE_REGISTER.vhd". + Found 16-bit 4-to-1 multiplexer for signal <$n0001>. + Found 16-bit register for signal . + Summary: + inferred 16 D-type flip-flop(s). + inferred 16 Multiplexer(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/CONTEXT_MANAGER.vhd". + Found 46x20-bit dual-port block RAM for signal . + ----------------------------------------------------------------------- + | mode | write-first | | + | aspect ratio | 46-word x 20-bit | | + | clock | connected to signal | rise | + | dual clock | connected to signal | rise | + | dual enable | connected to signal | high | + | write enable | connected to signal | high | + | address | connected to signal | | + | dual address | connected to signal | | + | data in | connected to signal | | + | data out | not connected | | + | dual data out | connected to signal | | + | ram_style | Auto | | + ----------------------------------------------------------------------- + Found 1-bit 64-to-1 multiplexer for signal <$n0003> created at line 141. + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 6-bit register for signal . + Found 6-bit register for signal . + Found 64-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 79 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/INPUT_CONTROL.vhd". + Found 1-bit register for signal >. + Found 1-bit 4-to-1 multiplexer for signal >. + Summary: + inferred 1 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "C:/Xilinx/bin/ArithmeticDecoder/ARITHMETICDECODER.vhd". +WARNING:Xst:646 - Signal > is assigned but never used. +Unit synthesized. + +INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing. + +========================================================================= +* Advanced HDL Synthesis * +========================================================================= + +Advanced RAM inference ... +INFO:Xst:1647 - Data output of ROM in block is tied to register in block . +INFO:Xst:1650 - The register is removed and the ROM is implemented as read-only block RAM. +Advanced multiplier inference ... + Found registered multiplier on signal <_n0000>: + - 1 register level(s) found in a register connected to the multiplier macro ouput. + Pushing register(s) into the multiplier macro. + Found registered multiplier on signal <_n0003>: + - 1 register level(s) found in a register connected to the multiplier macro ouput. + Pushing register(s) into the multiplier macro. + Found registered multiplier on signal <_n0004>: + - 1 register level(s) found in a register connected to the multiplier macro ouput. + Pushing register(s) into the multiplier macro. +Advanced Registered AddSub inference ... +Dynamic shift register inference ... + +========================================================================= +HDL Synthesis Report + +Macro Statistics +# Block RAMs : 2 + 1022x32-bit single-port block RAM : 1 + 46x20-bit dual-port block RAM : 1 +# LUT RAMs : 1 + 256x1-bit dual-port distributed RAM: 1 +# Multipliers : 3 + 16x10-bit registered multiplier : 2 + 17x10-bit registered multiplier : 1 +# Adders/Subtractors : 59 + 10-bit adder : 6 + 10-bit subtractor : 1 + 17-bit adder : 2 + 17-bit subtractor : 3 + 3-bit addsub : 46 + 42-bit adder : 1 +# Counters : 2 + 8-bit up counter : 2 +# Registers : 133 + 1-bit register : 71 + 10-bit register : 8 + 16-bit register : 4 + 17-bit register : 2 + 3-bit register : 46 + 6-bit register : 2 +# Comparators : 4 + 10-bit comparator greater : 1 + 16-bit comparator greatequal : 1 + 3-bit comparator greater : 1 + 8-bit comparator equal : 1 +# Multiplexers : 55 + 1-bit 4-to-1 multiplexer : 1 + 1-bit 64-to-1 multiplexer : 1 + 10-bit 4-to-1 multiplexer : 2 + 16-bit 4-to-1 multiplexer : 4 + 3-bit 4-to-1 multiplexer : 46 + 3-bit 46-to-1 multiplexer : 1 +# Xors : 1 + 1-bit xor2 : 1 + +========================================================================= + +========================================================================= +* Low Level Synthesis * +========================================================================= +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . +WARNING:Xst:637 - Naming conflict between signal SHIFT_ALL of unit DIFFERENCE and signal DIFFERENCE_SHIFT_ALL of unit arithmeticdecoder : renaming DIFFERENCE_SHIFT_ALL to DIFFERENCE_SHIFT_ALL1. + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... +Loading device for application Rf_Device from file '2v250.nph' in environment C:/Xilinx. + +Mapping all equations... +Building and optimizing final netlist ... +Register equivalent to has been removed +Register equivalent to has been removed +Register equivalent to has been removed +Register equivalent to has been removed +Register equivalent to has been removed +Register equivalent to has been removed +Register equivalent to has been removed +Register equivalent to has been removed +Register equivalent to has been removed +Register equivalent to has been removed +Register equivalent to has been removed +Found area constraint ratio of 100 (+ 5) on block arithmeticdecoder, actual ratio is 33. +FlipFlop PROBABILITY_READ_ADDRESS_0 has been replicated 3 time(s) + +========================================================================= +* Final Report * +========================================================================= +Final Results +RTL Top Level Output File Name : arithmeticdecoder.ngr +Top Level Output File Name : arithmeticdecoder +Output Format : NGC +Optimization Goal : Speed +Keep Hierarchy : NO + +Design Statistics +# IOs : 14 + +Macro Statistics : +# RAM : 3 +# 1022x32-bit single-port block RAM: 1 +# 256x1-bit dual-port distributed RAM: 1 +# 46x20-bit dual-port block RAM: 1 +# Registers : 207 +# 1-bit register : 151 +# 16-bit register : 4 +# 17-bit register : 2 +# 3-bit register : 46 +# 6-bit register : 2 +# 8-bit register : 2 +# Multiplexers : 55 +# 1-bit 4-to-1 multiplexer : 1 +# 1-bit 64-to-1 multiplexer : 1 +# 10-bit 4-to-1 multiplexer : 2 +# 16-bit 4-to-1 multiplexer : 4 +# 3-bit 4-to-1 multiplexer : 46 +# 3-bit 46-to-1 multiplexer : 1 +# Adders/Subtractors : 15 +# 10-bit adder : 6 +# 10-bit subtractor : 1 +# 17-bit adder : 2 +# 17-bit subtractor : 3 +# 42-bit adder : 1 +# 8-bit adder : 2 +# Multipliers : 3 +# 16x10-bit registered multiplier: 2 +# 17x10-bit registered multiplier: 1 +# Comparators : 4 +# 10-bit comparator greater : 1 +# 16-bit comparator greatequal: 1 +# 3-bit comparator greater : 1 +# 8-bit comparator equal : 1 +# Xors : 92 +# 1-bit xor3 : 92 + +Cell Usage : +# BELS : 1384 +# GND : 1 +# INV : 34 +# LUT1 : 31 +# LUT1_L : 28 +# LUT2 : 40 +# LUT2_D : 1 +# LUT2_L : 41 +# LUT3 : 109 +# LUT3_D : 4 +# LUT3_L : 154 +# LUT4 : 332 +# LUT4_D : 26 +# LUT4_L : 72 +# MUXCY : 187 +# MUXF5 : 123 +# MUXF6 : 23 +# MUXF7 : 10 +# MUXF8 : 5 +# VCC : 1 +# XORCY : 162 +# FlipFlops/Latches : 405 +# FD : 6 +# FDE : 41 +# FDR : 49 +# FDRE : 237 +# FDRSE : 1 +# FDS : 5 +# FDSE : 66 +# RAMS : 7 +# RAM64X1D : 4 +# RAMB16_S18 : 2 +# RAMB16_S36_S36 : 1 +# Clock Buffers : 1 +# BUFGP : 1 +# IO Buffers : 13 +# IBUF : 11 +# OBUF : 2 +# MULTs : 3 +# MULT18X18S : 3 +========================================================================= + +Device utilization summary: +--------------------------- + +Selected Device : 2v250cs144-6 + + Number of Slices: 490 out of 1536 31% + Number of Slice Flip Flops: 405 out of 3072 13% + Number of 4 input LUTs: 854 out of 3072 27% + Number of bonded IOBs: 14 out of 92 15% + Number of BRAMs: 3 out of 24 12% + Number of MULT18X18s: 3 out of 24 12% + Number of GCLKs: 1 out of 16 6% + + +========================================================================= +TIMING REPORT + +NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. + FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT + GENERATED AFTER PLACE-and-ROUTE. + +Clock Information: +------------------ +-----------------------------------+------------------------+-------+ +Clock Signal | Clock buffer(FF name) | Load | +-----------------------------------+------------------------+-------+ +CLOCK | BUFGP | 413 | +-----------------------------------+------------------------+-------+ + +Timing Summary: +--------------- +Speed Grade: -6 + + Minimum period: 9.680ns (Maximum Frequency: 103.303MHz) + Minimum input arrival time before clock: 10.225ns + Maximum output required time after clock: 11.576ns + Maximum combinational path delay: No path found + +Timing Detail: +-------------- +All values displayed in nanoseconds (ns) + +========================================================================= +Timing constraint: Default period analysis for Clock 'CLOCK' + Clock period: 9.680ns (frequency: 103.303MHz) + Total number of paths / destination ports: 273761 / 786 +------------------------------------------------------------------------- +Delay: 9.680ns (Levels of Logic = 12) + Source: PROBABILITY_REFRESH_SHIFTS_0_1 (FF) + Destination: PROBABILITY_Mram_PROBABILITY_inst_ramb_0 (RAM) + Source Clock: CLOCK rising + Destination Clock: CLOCK rising + + Data Path: PROBABILITY_REFRESH_SHIFTS_0_1 to PROBABILITY_Mram_PROBABILITY_inst_ramb_0 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDRE:C->Q 5 0.449 0.734 PROBABILITY_REFRESH_SHIFTS_0_1 (PROBABILITY_REFRESH_SHIFTS_0_1) + LUT3_L:I1->LO 1 0.347 0.000 PROBABILITY_REFRESH_CONTEXT<4>31 (PROBABILITY_REFRESH_MUX_BLOCK_N38) + MUXF5:I0->O 1 0.345 0.000 PROBABILITY_REFRESH_CONTEXT<1>_rn_14 (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<1>_MUXF515) + MUXF6:I0->O 1 0.354 0.000 PROBABILITY_REFRESH_CONTEXT<0>_rn_9 (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<0>_MUXF67) + MUXF7:I0->O 1 0.354 0.000 PROBABILITY_REFRESH_CONTEXT<2>_rn_3 (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<2>_MUXF73) + MUXF8:I0->O 1 0.354 0.608 PROBABILITY_REFRESH_CONTEXT<3>_rn_0 (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<3>_MUXF81) + LUT3_L:I0->LO 1 0.347 0.000 PROBABILITY_REFRESH__n0241109_F (N961) + MUXF5:I0->O 15 0.345 0.763 PROBABILITY_REFRESH__n0241109 (PROBABILITY_REFRESH__n0241) + LUT4_D:I3->O 7 0.347 0.630 PROBABILITY_REFRESH__n0145_1 (PROBABILITY_REFRESH__n01451) + LUT3:I2->O 1 0.347 0.548 PROBABILITY_REFRESH_DENOMINATOR_OUT<3>1 (PROBABILITY_FRACTION2<3>) + LUT4:I1->O 1 0.347 0.409 PROBABILITY_PROBUPDATE__n00144 (CHOICE132) + LUT4:I2->O 20 0.347 0.769 PROBABILITY_PROBUPDATE__n001417 (PROBABILITY_PROBUPDATE_HALVE_VALUES) + MUXF5:S->O 1 0.553 0.382 PROBABILITY_PROBUPDATE_DENOMINATOR_OUT<0>_DENOMINATOR_OUT<0>_rn_4111 (PROBABILITY_NEWPROB<15>) + RAMB16_S36_S36:DIA15 0.000 PROBABILITY_Mram_PROBABILITY_inst_ramb_0 + ---------------------------------------- + Total 9.680ns (4.836ns logic, 4.844ns route) + (50.0% logic, 50.0% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'CLOCK' + Total number of paths / destination ports: 124379 / 894 +------------------------------------------------------------------------- +Offset: 10.225ns (Levels of Logic = 13) + Source: CONTEXT_SELECT<4> (PAD) + Destination: PROBABILITY_Mram_PROBABILITY_inst_ramb_0 (RAM) + Destination Clock: CLOCK rising + + Data Path: CONTEXT_SELECT<4> to PROBABILITY_Mram_PROBABILITY_inst_ramb_0 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 56 0.653 1.075 CONTEXT_SELECT_4_IBUF (CONTEXT_SELECT_4_IBUF) + LUT3_L:I0->LO 1 0.347 0.000 PROBABILITY_REFRESH_CONTEXT<4>19 (PROBABILITY_REFRESH_MUX_BLOCK_N26) + MUXF5:I0->O 1 0.345 0.000 PROBABILITY_REFRESH_CONTEXT<1>_rn_8 (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<1>_MUXF59) + MUXF6:I0->O 1 0.354 0.000 PROBABILITY_REFRESH_CONTEXT<0>_rn_6 (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<0>_MUXF64) + MUXF7:I1->O 1 0.354 0.000 PROBABILITY_REFRESH_CONTEXT<2>_rn_2 (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<2>_MUXF72) + MUXF8:I1->O 1 0.354 0.608 PROBABILITY_REFRESH_CONTEXT<3>_rn_0 (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<3>_MUXF81) + LUT3_L:I0->LO 1 0.347 0.000 PROBABILITY_REFRESH__n0241109_F (N961) + MUXF5:I0->O 15 0.345 0.763 PROBABILITY_REFRESH__n0241109 (PROBABILITY_REFRESH__n0241) + LUT4_D:I3->O 7 0.347 0.630 PROBABILITY_REFRESH__n0145_1 (PROBABILITY_REFRESH__n01451) + LUT3:I2->O 1 0.347 0.548 PROBABILITY_REFRESH_DENOMINATOR_OUT<3>1 (PROBABILITY_FRACTION2<3>) + LUT4:I1->O 1 0.347 0.409 PROBABILITY_PROBUPDATE__n00144 (CHOICE132) + LUT4:I2->O 20 0.347 0.769 PROBABILITY_PROBUPDATE__n001417 (PROBABILITY_PROBUPDATE_HALVE_VALUES) + MUXF5:S->O 1 0.553 0.382 PROBABILITY_PROBUPDATE_DENOMINATOR_OUT<0>_DENOMINATOR_OUT<0>_rn_4111 (PROBABILITY_NEWPROB<15>) + RAMB16_S36_S36:DIA15 0.000 PROBABILITY_Mram_PROBABILITY_inst_ramb_0 + ---------------------------------------- + Total 10.225ns (5.040ns logic, 5.185ns route) + (49.3% logic, 50.7% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'CLOCK' + Total number of paths / destination ports: 426 / 2 +------------------------------------------------------------------------- +Offset: 11.576ns (Levels of Logic = 7) + Source: ARITH_Mmult__n00001_inst_mult_2 (MULT) + Destination: DATA_OUT (PAD) + Source Clock: CLOCK rising + + Data Path: ARITH_Mmult__n00001_inst_mult_2 to DATA_OUT + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + MULT18X18S:C->P24 3 1.976 0.701 ARITH_Mmult__n00001_inst_mult_2 (ARITH_PRODUCT<24>) + LUT2_L:I1->LO 1 0.347 0.000 ARITH_ARITHMETIC_UNIT_RESULT_OUT1<14>lut (ARITH_N55) + MUXCY:S->O 0 0.235 0.000 ARITH_ARITHMETIC_UNIT_RESULT_OUT1<14>cy (ARITH_ARITHMETIC_UNIT_RESULT_OUT1<14>_cyo) + XORCY:CI->O 3 0.824 0.701 ARITH_ARITHMETIC_UNIT_RESULT_OUT1<15>_xor (ARITHMETIC_UNIT_RESULT_OUT1<15>) + LUT2_L:I1->LO 1 0.347 0.000 XNor_stagelut15 (N17) + MUXCY:S->O 71 0.794 1.044 XNor_stagecy_rn_14 (OUTPUT__n0001) + LUT2_D:I1->O 2 0.347 0.518 DATA_OUT1 (DATA_OUT_OBUF) + OBUF:I->O 3.743 DATA_OUT_OBUF (DATA_OUT) + ---------------------------------------- + Total 11.576ns (8.613ns logic, 2.963ns route) + (74.4% logic, 25.6% route) + +========================================================================= +CPU : 27.55 / 29.98 s | Elapsed : 28.00 / 30.00 s + +--> + +Total memory usage is 109820 kilobytes + +Number of errors : 0 ( 0 filtered) +Number of warnings : 18 ( 0 filtered) +Number of infos : 4 ( 0 filtered) +
trunk/docs/synthesis_reports/decoder/arithmeticdecoder.syr Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/docs/synthesis_reports/common/fifo.syr =================================================================== --- trunk/docs/synthesis_reports/common/fifo.syr (nonexistent) +++ trunk/docs/synthesis_reports/common/fifo.syr (revision 9) @@ -0,0 +1,113 @@ +Release 7.1.04i - xst H.42 +Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. +--> Parameter TMPDIR set to __projnav +CPU : 0.00 / 0.33 s | Elapsed : 0.00 / 0.00 s + +--> Parameter xsthdpdir set to ./xst +CPU : 0.00 / 0.33 s | Elapsed : 0.00 / 0.00 s + +--> Reading design: fifo.prj + +TABLE OF CONTENTS + 1) Synthesis Options Summary + 2) HDL Compilation + 3) HDL Analysis + 4) HDL Synthesis + 5) Advanced HDL Synthesis + 5.1) HDL Synthesis Report + 6) Low Level Synthesis + 7) Final Report + 7.1) Device utilization summary + 7.2) TIMING REPORT + + +========================================================================= +* Synthesis Options Summary * +========================================================================= +---- Source Parameters +Input File Name : "fifo.prj" +Input Format : mixed +Ignore Synthesis Constraint File : NO + +---- Target Parameters +Output File Name : "fifo" +Output Format : NGC +Target Device : xc2v250-6-cs144 + +---- Source Options +Top Module Name : fifo +Automatic FSM Extraction : YES +FSM Encoding Algorithm : Auto +FSM Style : lut +RAM Extraction : Yes +RAM Style : Auto +ROM Extraction : Yes +ROM Style : Auto +Mux Extraction : YES +Mux Style : Auto +Decoder Extraction : YES +Priority Encoder Extraction : YES +Shift Register Extraction : YES +Logical Shifter Extraction : YES +XOR Collapsing : YES +Resource Sharing : YES +Multiplier Style : auto +Automatic Register Balancing : No + +---- Target Options +Add IO Buffers : YES +Global Maximum Fanout : 500 +Add Generic Clock Buffer(BUFG) : 16 +Register Duplication : YES +Equivalent register Removal : YES +Slice Packing : YES +Pack IO Registers into IOBs : auto + +---- General Options +Optimization Goal : Speed +Optimization Effort : 1 +Keep Hierarchy : NO +Global Optimization : AllClockNets +RTL Output : Yes +Write Timing Constraints : NO +Hierarchy Separator : _ +Bus Delimiter : <> +Case Specifier : maintain +Slice Utilization Ratio : 100 +Slice Utilization Ratio Delta : 5 + +---- Other Options +lso : fifo.lso +Read Cores : YES +cross_clock_analysis : NO +verilog2001 : YES +safe_implementation : No +Optimize Instantiated Primitives : NO +tristate2logic : Yes +use_clock_enable : Yes +use_sync_set : Yes +use_sync_reset : Yes +enable_auto_floorplanning : No + +========================================================================= + + +========================================================================= +* HDL Compilation * +========================================================================= +Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/FIFO.vhd" in Library work. +Architecture rtl of Entity fifo is up to date. + +========================================================================= +* HDL Analysis * +========================================================================= +Analyzing Entity (Architecture ). +ERROR:Xst:834 - "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/FIFO.vhd" line 13: Generic has not been given a value. +--> + +Total memory usage is 77708 kilobytes + +Number of errors : 1 ( 0 filtered) +Number of warnings : 0 ( 0 filtered) +Number of infos : 0 ( 0 filtered) +
trunk/docs/synthesis_reports/common/fifo.syr Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/docs/synthesis_reports/common/updater.syr =================================================================== --- trunk/docs/synthesis_reports/common/updater.syr (nonexistent) +++ trunk/docs/synthesis_reports/common/updater.syr (revision 9) @@ -0,0 +1,338 @@ +Release 7.1.04i - xst H.42 +Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. +--> Parameter TMPDIR set to __projnav +CPU : 0.00 / 0.33 s | Elapsed : 0.00 / 1.00 s + +--> Parameter xsthdpdir set to ./xst +CPU : 0.00 / 0.33 s | Elapsed : 0.00 / 1.00 s + +--> Reading design: updater.prj + +TABLE OF CONTENTS + 1) Synthesis Options Summary + 2) HDL Compilation + 3) HDL Analysis + 4) HDL Synthesis + 5) Advanced HDL Synthesis + 5.1) HDL Synthesis Report + 6) Low Level Synthesis + 7) Final Report + 7.1) Device utilization summary + 7.2) TIMING REPORT + + +========================================================================= +* Synthesis Options Summary * +========================================================================= +---- Source Parameters +Input File Name : "updater.prj" +Input Format : mixed +Ignore Synthesis Constraint File : NO + +---- Target Parameters +Output File Name : "updater" +Output Format : NGC +Target Device : xc2v250-6-cs144 + +---- Source Options +Top Module Name : updater +Automatic FSM Extraction : YES +FSM Encoding Algorithm : Auto +FSM Style : lut +RAM Extraction : Yes +RAM Style : Auto +ROM Extraction : Yes +ROM Style : Auto +Mux Extraction : YES +Mux Style : Auto +Decoder Extraction : YES +Priority Encoder Extraction : YES +Shift Register Extraction : YES +Logical Shifter Extraction : YES +XOR Collapsing : YES +Resource Sharing : YES +Multiplier Style : auto +Automatic Register Balancing : No + +---- Target Options +Add IO Buffers : YES +Global Maximum Fanout : 500 +Add Generic Clock Buffer(BUFG) : 16 +Register Duplication : YES +Equivalent register Removal : YES +Slice Packing : YES +Pack IO Registers into IOBs : auto + +---- General Options +Optimization Goal : Speed +Optimization Effort : 1 +Keep Hierarchy : NO +Global Optimization : AllClockNets +RTL Output : Yes +Write Timing Constraints : NO +Hierarchy Separator : _ +Bus Delimiter : <> +Case Specifier : maintain +Slice Utilization Ratio : 100 +Slice Utilization Ratio Delta : 5 + +---- Other Options +lso : updater.lso +Read Cores : YES +cross_clock_analysis : NO +verilog2001 : YES +safe_implementation : No +Optimize Instantiated Primitives : NO +tristate2logic : Yes +use_clock_enable : Yes +use_sync_set : Yes +use_sync_reset : Yes +enable_auto_floorplanning : No + +========================================================================= + + +========================================================================= +* HDL Compilation * +========================================================================= +Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/UPDATER.vhd" in Library work. +Architecture rtl of Entity updater is up to date. + +========================================================================= +* HDL Analysis * +========================================================================= +Analyzing Entity (Architecture ). +Entity analyzed. Unit generated. + + +========================================================================= +* HDL Synthesis * +========================================================================= + +Synthesizing Unit . + Related source file is "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/UPDATER.vhd". +WARNING:Xst:1780 - Signal is never used or assigned. + Found 10-bit 4-to-1 multiplexer for signal . + Found 10-bit 4-to-1 multiplexer for signal . + Found 1-bit register for signal . + Found 10-bit adder for signal <$n0009> created at line 51. + Found 10-bit adder for signal <$n0011> created at line 73. + Found 10-bit adder for signal <$n0012> created at line 84. + Found 10-bit adder for signal <$n0013> created at line 62. + Found 10-bit register for signal . + Found 10-bit register for signal . + Found 10-bit register for signal . + Found 10-bit register for signal . + Found 10-bit register for signal . + Found 1-bit xor2 for signal . + Summary: + inferred 1 D-type flip-flop(s). + inferred 4 Adder/Subtractor(s). + inferred 20 Multiplexer(s). +Unit synthesized. + + +========================================================================= +* Advanced HDL Synthesis * +========================================================================= + +Advanced RAM inference ... +Advanced multiplier inference ... +Advanced Registered AddSub inference ... +Dynamic shift register inference ... + +========================================================================= +HDL Synthesis Report + +Macro Statistics +# Adders/Subtractors : 4 + 10-bit adder : 4 +# Registers : 6 + 1-bit register : 1 + 10-bit register : 5 +# Multiplexers : 2 + 10-bit 4-to-1 multiplexer : 2 +# Xors : 1 + 1-bit xor2 : 1 + +========================================================================= + +========================================================================= +* Low Level Synthesis * +========================================================================= + +Optimizing unit ... +Loading device for application Rf_Device from file '2v250.nph' in environment C:/Xilinx. + +Mapping all equations... +Building and optimizing final netlist ... +Found area constraint ratio of 100 (+ 5) on block updater, actual ratio is 2. + +========================================================================= +* Final Report * +========================================================================= +Final Results +RTL Top Level Output File Name : updater.ngr +Top Level Output File Name : updater +Output Format : NGC +Optimization Goal : Speed +Keep Hierarchy : NO + +Design Statistics +# IOs : 45 + +Macro Statistics : +# Registers : 51 +# 1-bit register : 51 +# Multiplexers : 2 +# 10-bit 4-to-1 multiplexer : 2 +# Adders/Subtractors : 4 +# 10-bit adder : 4 + +Cell Usage : +# BELS : 155 +# GND : 1 +# INV : 3 +# LUT1 : 35 +# LUT2 : 9 +# LUT3 : 20 +# LUT4 : 5 +# MUXCY : 36 +# MUXF5 : 10 +# VCC : 1 +# XORCY : 35 +# FlipFlops/Latches : 51 +# FDR : 46 +# FDS : 5 +# Clock Buffers : 1 +# BUFGP : 1 +# IO Buffers : 44 +# IBUF : 23 +# OBUF : 21 +========================================================================= + +Device utilization summary: +--------------------------- + +Selected Device : 2v250cs144-6 + + Number of Slices: 40 out of 1536 2% + Number of Slice Flip Flops: 51 out of 3072 1% + Number of 4 input LUTs: 69 out of 3072 2% + Number of bonded IOBs: 45 out of 92 48% + Number of GCLKs: 1 out of 16 6% + + +========================================================================= +TIMING REPORT + +NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. + FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT + GENERATED AFTER PLACE-and-ROUTE. + +Clock Information: +------------------ +-----------------------------------+------------------------+-------+ +Clock Signal | Clock buffer(FF name) | Load | +-----------------------------------+------------------------+-------+ +CLOCK | BUFGP | 51 | +-----------------------------------+------------------------+-------+ + +Timing Summary: +--------------- +Speed Grade: -6 + + Minimum period: No path found + Minimum input arrival time before clock: 5.514ns + Maximum output required time after clock: 5.814ns + Maximum combinational path delay: 8.733ns + +Timing Detail: +-------------- +All values displayed in nanoseconds (ns) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'CLOCK' + Total number of paths / destination ports: 464 / 102 +------------------------------------------------------------------------- +Offset: 5.514ns (Levels of Logic = 13) + Source: NUMERATOR<2> (PAD) + Destination: NUMERATOR4_9 (FF) + Destination Clock: CLOCK rising + + Data Path: NUMERATOR<2> to NUMERATOR4_9 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 3 0.653 0.760 NUMERATOR_2_IBUF (NUMERATOR_2_IBUF) + LUT1:I0->O 1 0.347 0.000 NUMERATOR_2_IBUF_rt1 (NUMERATOR_2_IBUF_rt1) + MUXCY:S->O 1 0.235 0.000 updater__n0013<1>cy (updater__n0013<1>_cyo) + MUXCY:CI->O 1 0.042 0.000 updater__n0013<2>cy (updater__n0013<2>_cyo) + MUXCY:CI->O 1 0.042 0.000 updater__n0013<3>cy (updater__n0013<3>_cyo) + MUXCY:CI->O 1 0.042 0.000 updater__n0013<4>cy (updater__n0013<4>_cyo) + MUXCY:CI->O 1 0.042 0.000 updater__n0013<5>cy (updater__n0013<5>_cyo) + MUXCY:CI->O 1 0.042 0.000 updater__n0013<6>cy (updater__n0013<6>_cyo) + MUXCY:CI->O 1 0.042 0.000 updater__n0013<7>cy (updater__n0013<7>_cyo) + XORCY:CI->O 2 0.824 0.744 updater__n0013<8>_xor (_n0013<8>) + LUT1:I0->O 1 0.347 0.000 _n0013<8>_rt (_n0013<8>_rt) + MUXCY:S->O 0 0.235 0.000 updater__n0011<8>cy (updater__n0011<8>_cyo) + XORCY:CI->O 1 0.824 0.000 updater__n0011<9>_xor (_n0011<9>) + FDR:D 0.293 NUMERATOR4_9 + ---------------------------------------- + Total 5.514ns (4.010ns logic, 1.504ns route) + (72.7% logic, 27.3% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'CLOCK' + Total number of paths / destination ports: 51 / 21 +------------------------------------------------------------------------- +Offset: 5.814ns (Levels of Logic = 3) + Source: NUMERATOR2_9 (FF) + Destination: NUMERATOR_OUT<9> (PAD) + Source Clock: CLOCK rising + + Data Path: NUMERATOR2_9 to NUMERATOR_OUT<9> + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDR:C->Q 1 0.449 0.548 NUMERATOR2_9 (NUMERATOR2_9) + LUT3:I1->O 1 0.347 0.000 DATA_IN19 (MUX_BLOCK_N19) + MUXF5:I0->O 1 0.345 0.383 DENOMINATOR_OUT<0>_DENOMINATOR_OUT<0>_rn_8 (NUMERATOR_OUT_9_OBUF) + OBUF:I->O 3.743 NUMERATOR_OUT_9_OBUF (NUMERATOR_OUT<9>) + ---------------------------------------- + Total 5.814ns (4.884ns logic, 0.930ns route) + (84.0% logic, 16.0% route) + +========================================================================= +Timing constraint: Default path analysis + Total number of paths / destination ports: 224 / 20 +------------------------------------------------------------------------- +Delay: 8.733ns (Levels of Logic = 6) + Source: DENOMINATOR<0> (PAD) + Destination: DENOMINATOR_OUT<9> (PAD) + + Data Path: DENOMINATOR<0> to DENOMINATOR_OUT<9> + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 2 0.653 0.743 DENOMINATOR_0_IBUF (DENOMINATOR_0_IBUF) + LUT4:I0->O 1 0.347 0.415 _n001410 (CHOICE6) + LUT4:I3->O 1 0.347 0.415 _n001416_SW0 (N27) + LUT4:I3->O 20 0.347 0.994 _n001416 (HALVE_VALUES) + LUT2:I0->O 1 0.347 0.383 DENOMINATOR_OUT<9>1 (DENOMINATOR_OUT_9_OBUF) + OBUF:I->O 3.743 DENOMINATOR_OUT_9_OBUF (DENOMINATOR_OUT<9>) + ---------------------------------------- + Total 8.733ns (5.784ns logic, 2.949ns route) + (66.2% logic, 33.8% route) + +========================================================================= +CPU : 4.88 / 5.23 s | Elapsed : 5.00 / 6.00 s + +--> + +Total memory usage is 100604 kilobytes + +Number of errors : 0 ( 0 filtered) +Number of warnings : 1 ( 0 filtered) +Number of infos : 0 ( 0 filtered) +
trunk/docs/synthesis_reports/common/updater.syr Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/docs/synthesis_reports/common/divider.syr =================================================================== --- trunk/docs/synthesis_reports/common/divider.syr (nonexistent) +++ trunk/docs/synthesis_reports/common/divider.syr (revision 9) @@ -0,0 +1,343 @@ +Release 7.1.04i - xst H.42 +Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. +--> Parameter TMPDIR set to __projnav +CPU : 0.00 / 0.34 s | Elapsed : 0.00 / 0.00 s + +--> Parameter xsthdpdir set to ./xst +CPU : 0.00 / 0.34 s | Elapsed : 0.00 / 0.00 s + +--> Reading design: divider.prj + +TABLE OF CONTENTS + 1) Synthesis Options Summary + 2) HDL Compilation + 3) HDL Analysis + 4) HDL Synthesis + 5) Advanced HDL Synthesis + 5.1) HDL Synthesis Report + 6) Low Level Synthesis + 7) Final Report + 7.1) Device utilization summary + 7.2) TIMING REPORT + + +========================================================================= +* Synthesis Options Summary * +========================================================================= +---- Source Parameters +Input File Name : "divider.prj" +Input Format : mixed +Ignore Synthesis Constraint File : NO + +---- Target Parameters +Output File Name : "divider" +Output Format : NGC +Target Device : xc2v250-6-cs144 + +---- Source Options +Top Module Name : divider +Automatic FSM Extraction : YES +FSM Encoding Algorithm : Auto +FSM Style : lut +RAM Extraction : Yes +RAM Style : Auto +ROM Extraction : Yes +ROM Style : Auto +Mux Extraction : YES +Mux Style : Auto +Decoder Extraction : YES +Priority Encoder Extraction : YES +Shift Register Extraction : YES +Logical Shifter Extraction : YES +XOR Collapsing : YES +Resource Sharing : YES +Multiplier Style : auto +Automatic Register Balancing : No + +---- Target Options +Add IO Buffers : YES +Global Maximum Fanout : 500 +Add Generic Clock Buffer(BUFG) : 16 +Register Duplication : YES +Equivalent register Removal : YES +Slice Packing : YES +Pack IO Registers into IOBs : auto + +---- General Options +Optimization Goal : Speed +Optimization Effort : 1 +Keep Hierarchy : NO +Global Optimization : AllClockNets +RTL Output : Yes +Write Timing Constraints : NO +Hierarchy Separator : _ +Bus Delimiter : <> +Case Specifier : maintain +Slice Utilization Ratio : 100 +Slice Utilization Ratio Delta : 5 + +---- Other Options +lso : divider.lso +Read Cores : YES +cross_clock_analysis : NO +verilog2001 : YES +safe_implementation : No +Optimize Instantiated Primitives : NO +tristate2logic : Yes +use_clock_enable : Yes +use_sync_set : Yes +use_sync_reset : Yes +enable_auto_floorplanning : No + +========================================================================= + + +========================================================================= +* HDL Compilation * +========================================================================= +Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/Divider.vhd" in Library work. +Architecture rtl of Entity divider is up to date. + +========================================================================= +* HDL Analysis * +========================================================================= +Analyzing Entity (Architecture ). +WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/Divider.vhd" line 1079: Index value(s) does not match array range, simulation mismatch. +Entity analyzed. Unit generated. + + +========================================================================= +* HDL Synthesis * +========================================================================= + +Synthesizing Unit . + Related source file is "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/Divider.vhd". +WARNING:Xst:646 - Signal > is assigned but never used. +WARNING:Xst:646 - Signal > is assigned but never used. + Found 1022x32-bit ROM for signal <$n0002> created at line 1079. + Found 16x10-bit multiplier for signal <$n0003> created at line 1086. + Found 16x10-bit multiplier for signal <$n0004> created at line 1093. + Found 10-bit subtractor for signal . + Found 10-bit register for signal . + Found 26-bit register for signal . + Found 26-bit register for signal . + Found 32-bit register for signal . + Found 42-bit adder for signal . + Summary: + inferred 1 ROM(s). + inferred 84 D-type flip-flop(s). + inferred 2 Adder/Subtractor(s). + inferred 2 Multiplier(s). +Unit synthesized. + + +========================================================================= +* Advanced HDL Synthesis * +========================================================================= + +Advanced RAM inference ... +INFO:Xst:1647 - Data output of ROM in block is tied to register in block . +INFO:Xst:1650 - The register is removed and the ROM is implemented as read-only block RAM. +Advanced multiplier inference ... + Found registered multiplier on signal <_n0003>: + - 1 register level(s) found in a register connected to the multiplier macro ouput. + Pushing register(s) into the multiplier macro. + Found registered multiplier on signal <_n0004>: + - 1 register level(s) found in a register connected to the multiplier macro ouput. + Pushing register(s) into the multiplier macro. +Advanced Registered AddSub inference ... +Dynamic shift register inference ... + +========================================================================= +HDL Synthesis Report + +Macro Statistics +# Block RAMs : 1 + 1022x32-bit single-port block RAM : 1 +# Multipliers : 2 + 16x10-bit registered multiplier : 2 +# Adders/Subtractors : 2 + 10-bit subtractor : 1 + 42-bit adder : 1 +# Registers : 1 + 10-bit register : 1 + +========================================================================= + +========================================================================= +* Low Level Synthesis * +========================================================================= + +Optimizing unit ... +Loading device for application Rf_Device from file '2v250.nph' in environment C:/Xilinx. + +Mapping all equations... +Building and optimizing final netlist ... +Found area constraint ratio of 100 (+ 5) on block divider, actual ratio is 1. + +========================================================================= +* Final Report * +========================================================================= +Final Results +RTL Top Level Output File Name : divider.ngr +Top Level Output File Name : divider +Output Format : NGC +Optimization Goal : Speed +Keep Hierarchy : NO + +Design Statistics +# IOs : 32 + +Macro Statistics : +# RAM : 1 +# 1022x32-bit single-port block RAM: 1 +# Registers : 10 +# 1-bit register : 10 +# Adders/Subtractors : 2 +# 10-bit subtractor : 1 +# 42-bit adder : 1 +# Multipliers : 2 +# 16x10-bit registered multiplier: 2 + +Cell Usage : +# BELS : 69 +# GND : 1 +# LUT1 : 5 +# LUT2 : 20 +# MUXCY : 23 +# VCC : 1 +# XORCY : 19 +# FlipFlops/Latches : 10 +# FDR : 9 +# FDS : 1 +# RAMS : 2 +# RAMB16_S18 : 2 +# Clock Buffers : 1 +# BUFGP : 1 +# IO Buffers : 31 +# IBUF : 21 +# OBUF : 10 +# MULTs : 2 +# MULT18X18S : 2 +========================================================================= + +Device utilization summary: +--------------------------- + +Selected Device : 2v250cs144-6 + + Number of Slices: 19 out of 1536 1% + Number of Slice Flip Flops: 10 out of 3072 0% + Number of 4 input LUTs: 25 out of 3072 0% + Number of bonded IOBs: 32 out of 92 34% + Number of BRAMs: 2 out of 24 8% + Number of MULT18X18s: 2 out of 24 8% + Number of GCLKs: 1 out of 16 6% + + +========================================================================= +TIMING REPORT + +NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. + FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT + GENERATED AFTER PLACE-and-ROUTE. + +Clock Information: +------------------ +-----------------------------------+------------------------+-------+ +Clock Signal | Clock buffer(FF name) | Load | +-----------------------------------+------------------------+-------+ +CLOCK | BUFGP | 12 | +-----------------------------------+------------------------+-------+ + +Timing Summary: +--------------- +Speed Grade: -6 + + Minimum period: 3.967ns (Maximum Frequency: 252.048MHz) + Minimum input arrival time before clock: 1.644ns + Maximum output required time after clock: 8.362ns + Maximum combinational path delay: No path found + +Timing Detail: +-------------- +All values displayed in nanoseconds (ns) + +========================================================================= +Timing constraint: Default period analysis for Clock 'CLOCK' + Clock period: 3.967ns (frequency: 252.048MHz) + Total number of paths / destination ports: 20 / 20 +------------------------------------------------------------------------- +Delay: 3.967ns (Levels of Logic = 0) + Source: NUMERATOR2_9 (FF) + Destination: Mmult__n00041_inst_mult_0 (MULT) + Source Clock: CLOCK rising + Destination Clock: CLOCK rising + + Data Path: NUMERATOR2_9 to Mmult__n00041_inst_mult_0 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDR:C->Q 2 0.449 0.519 NUMERATOR2_9 (NUMERATOR2_9) + MULT18X18S:B9 3.000 Mmult__n00041_inst_mult_0 + ---------------------------------------- + Total 3.967ns (3.449ns logic, 0.519ns route) + (86.9% logic, 13.1% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'CLOCK' + Total number of paths / destination ports: 20 / 20 +------------------------------------------------------------------------- +Offset: 1.644ns (Levels of Logic = 1) + Source: RESET (PAD) + Destination: NUMERATOR2_7 (FF) + Destination Clock: CLOCK rising + + Data Path: RESET to NUMERATOR2_7 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 20 0.653 0.769 RESET_IBUF (RESET_IBUF) + FDR:R 0.222 NUMERATOR2_2 + ---------------------------------------- + Total 1.644ns (0.875ns logic, 0.769ns route) + (53.2% logic, 46.8% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'CLOCK' + Total number of paths / destination ports: 299 / 10 +------------------------------------------------------------------------- +Offset: 8.362ns (Levels of Logic = 9) + Source: Mmult__n00041_inst_mult_0 (MULT) + Destination: QUOTIENT<9> (PAD) + Source Clock: CLOCK rising + + Data Path: Mmult__n00041_inst_mult_0 to QUOTIENT<9> + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + MULT18X18S:C->P25 1 2.073 0.548 Mmult__n00041_inst_mult_0 (PRODUCT2<25>) + LUT2:I1->O 1 0.347 0.000 divider_QUOTIENT<3>lut (N23) + MUXCY:S->O 1 0.235 0.000 divider_QUOTIENT<3>cy (divider_QUOTIENT<3>_cyo) + MUXCY:CI->O 1 0.042 0.000 divider_QUOTIENT<4>cy (divider_QUOTIENT<4>_cyo) + MUXCY:CI->O 1 0.042 0.000 divider_QUOTIENT<5>cy (divider_QUOTIENT<5>_cyo) + MUXCY:CI->O 1 0.042 0.000 divider_QUOTIENT<6>cy (divider_QUOTIENT<6>_cyo) + MUXCY:CI->O 1 0.042 0.000 divider_QUOTIENT<7>cy (divider_QUOTIENT<7>_cyo) + MUXCY:CI->O 0 0.042 0.000 divider_QUOTIENT<8>cy (divider_QUOTIENT<8>_cyo) + XORCY:CI->O 1 0.824 0.383 divider_QUOTIENT<9>_xor (QUOTIENT_9_OBUF) + OBUF:I->O 3.743 QUOTIENT_9_OBUF (QUOTIENT<9>) + ---------------------------------------- + Total 8.362ns (7.432ns logic, 0.930ns route) + (88.9% logic, 11.1% route) + +========================================================================= +CPU : 5.28 / 5.66 s | Elapsed : 5.00 / 5.00 s + +--> + +Total memory usage is 101628 kilobytes + +Number of errors : 0 ( 0 filtered) +Number of warnings : 3 ( 0 filtered) +Number of infos : 2 ( 0 filtered) +
trunk/docs/synthesis_reports/common/divider.syr Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/docs/synthesis_reports/common/arithmetic_unit.syr =================================================================== --- trunk/docs/synthesis_reports/common/arithmetic_unit.syr (nonexistent) +++ trunk/docs/synthesis_reports/common/arithmetic_unit.syr (revision 9) @@ -0,0 +1,332 @@ +Release 7.1.04i - xst H.42 +Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. +--> Parameter TMPDIR set to __projnav +CPU : 0.00 / 0.34 s | Elapsed : 0.00 / 1.00 s + +--> Parameter xsthdpdir set to ./xst +CPU : 0.00 / 0.34 s | Elapsed : 0.00 / 1.00 s + +--> Reading design: arithmetic_unit.prj + +TABLE OF CONTENTS + 1) Synthesis Options Summary + 2) HDL Compilation + 3) HDL Analysis + 4) HDL Synthesis + 5) Advanced HDL Synthesis + 5.1) HDL Synthesis Report + 6) Low Level Synthesis + 7) Final Report + 7.1) Device utilization summary + 7.2) TIMING REPORT + + +========================================================================= +* Synthesis Options Summary * +========================================================================= +---- Source Parameters +Input File Name : "arithmetic_unit.prj" +Input Format : mixed +Ignore Synthesis Constraint File : NO + +---- Target Parameters +Output File Name : "arithmetic_unit" +Output Format : NGC +Target Device : xc2v250-6-cs144 + +---- Source Options +Top Module Name : arithmetic_unit +Automatic FSM Extraction : YES +FSM Encoding Algorithm : Auto +FSM Style : lut +RAM Extraction : Yes +RAM Style : Auto +ROM Extraction : Yes +ROM Style : Auto +Mux Extraction : YES +Mux Style : Auto +Decoder Extraction : YES +Priority Encoder Extraction : YES +Shift Register Extraction : YES +Logical Shifter Extraction : YES +XOR Collapsing : YES +Resource Sharing : YES +Multiplier Style : auto +Automatic Register Balancing : No + +---- Target Options +Add IO Buffers : YES +Global Maximum Fanout : 500 +Add Generic Clock Buffer(BUFG) : 16 +Register Duplication : YES +Equivalent register Removal : YES +Slice Packing : YES +Pack IO Registers into IOBs : auto + +---- General Options +Optimization Goal : Speed +Optimization Effort : 1 +Keep Hierarchy : NO +Global Optimization : AllClockNets +RTL Output : Yes +Write Timing Constraints : NO +Hierarchy Separator : _ +Bus Delimiter : <> +Case Specifier : maintain +Slice Utilization Ratio : 100 +Slice Utilization Ratio Delta : 5 + +---- Other Options +lso : arithmetic_unit.lso +Read Cores : YES +cross_clock_analysis : NO +verilog2001 : YES +safe_implementation : No +Optimize Instantiated Primitives : NO +tristate2logic : Yes +use_clock_enable : Yes +use_sync_set : Yes +use_sync_reset : Yes +enable_auto_floorplanning : No + +========================================================================= + + +========================================================================= +* HDL Compilation * +========================================================================= +Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/ARITHMETIC_UNIT.vhd" in Library work. +Architecture rtl of Entity arithmetic_unit is up to date. + +========================================================================= +* HDL Analysis * +========================================================================= +Analyzing Entity (Architecture ). +Entity analyzed. Unit generated. + + +========================================================================= +* HDL Synthesis * +========================================================================= + +Synthesizing Unit . + Related source file is "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/ARITHMETIC_UNIT.vhd". +WARNING:Xst:646 - Signal > is assigned but never used. +WARNING:Xst:646 - Signal > is assigned but never used. +WARNING:Xst:646 - Signal > is assigned but never used. +WARNING:Xst:646 - Signal > is assigned but never used. + Found 17x10-bit multiplier for signal <$n0000> created at line 48. + Found 1-bit register for signal . + Found 17-bit register for signal . + Found 17-bit adder for signal . + Found 17-bit subtractor for signal . + Found 17-bit subtractor for signal . + Found 17-bit register for signal . + Found 27-bit register for signal . + Found 17-bit adder for signal . + Found 17-bit subtractor for signal . + Summary: + inferred 62 D-type flip-flop(s). + inferred 5 Adder/Subtractor(s). + inferred 1 Multiplier(s). +Unit synthesized. + + +========================================================================= +* Advanced HDL Synthesis * +========================================================================= + +Advanced RAM inference ... +Advanced multiplier inference ... + Found registered multiplier on signal <_n0000>: + - 1 register level(s) found in a register connected to the multiplier macro ouput. + Pushing register(s) into the multiplier macro. +Advanced Registered AddSub inference ... +Dynamic shift register inference ... + +========================================================================= +HDL Synthesis Report + +Macro Statistics +# Multipliers : 1 + 17x10-bit registered multiplier : 1 +# Adders/Subtractors : 5 + 17-bit adder : 2 + 17-bit subtractor : 3 +# Registers : 3 + 1-bit register : 1 + 17-bit register : 2 + +========================================================================= + +========================================================================= +* Low Level Synthesis * +========================================================================= +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . + +Optimizing unit ... +Loading device for application Rf_Device from file '2v250.nph' in environment C:/Xilinx. + +Mapping all equations... +Building and optimizing final netlist ... +Found area constraint ratio of 100 (+ 5) on block arithmetic_unit, actual ratio is 3. + +========================================================================= +* Final Report * +========================================================================= +Final Results +RTL Top Level Output File Name : arithmetic_unit.ngr +Top Level Output File Name : arithmetic_unit +Output Format : NGC +Optimization Goal : Speed +Keep Hierarchy : NO + +Design Statistics +# IOs : 110 + +Macro Statistics : +# Registers : 3 +# 1-bit register : 1 +# 17-bit register : 2 +# Adders/Subtractors : 5 +# 17-bit adder : 2 +# 17-bit subtractor : 3 +# Multipliers : 1 +# 17x10-bit registered multiplier: 1 + +Cell Usage : +# BELS : 236 +# GND : 1 +# INV : 31 +# LUT1 : 16 +# LUT2 : 33 +# MUXCY : 76 +# VCC : 1 +# XORCY : 78 +# FlipFlops/Latches : 33 +# FDE : 32 +# FDR : 1 +# Clock Buffers : 1 +# BUFGP : 1 +# IO Buffers : 109 +# IBUF : 44 +# OBUF : 65 +# MULTs : 1 +# MULT18X18S : 1 +========================================================================= + +Device utilization summary: +--------------------------- + +Selected Device : 2v250cs144-6 + + Number of Slices: 59 out of 1536 3% + Number of Slice Flip Flops: 33 out of 3072 1% + Number of 4 input LUTs: 49 out of 3072 1% + Number of bonded IOBs: 110 out of 92 119% (*) + Number of MULT18X18s: 1 out of 24 4% + Number of GCLKs: 1 out of 16 6% + +WARNING:Xst:1336 - (*) More than 100% of Device resources are used + + +========================================================================= +TIMING REPORT + +NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. + FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT + GENERATED AFTER PLACE-and-ROUTE. + +Clock Information: +------------------ +-----------------------------------+------------------------+-------+ +Clock Signal | Clock buffer(FF name) | Load | +-----------------------------------+------------------------+-------+ +CLOCK | BUFGP | 34 | +-----------------------------------+------------------------+-------+ + +Timing Summary: +--------------- +Speed Grade: -6 + + Minimum period: No path found + Minimum input arrival time before clock: 6.731ns + Maximum output required time after clock: 10.035ns + Maximum combinational path delay: No path found + +Timing Detail: +-------------- +All values displayed in nanoseconds (ns) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'CLOCK' + Total number of paths / destination ports: 228 / 93 +------------------------------------------------------------------------- +Offset: 6.731ns (Levels of Logic = 17) + Source: DIFFERENCE<1> (PAD) + Destination: Mmult__n00001_inst_mult_0 (MULT) + Destination Clock: CLOCK rising + + Data Path: DIFFERENCE<1> to Mmult__n00001_inst_mult_0 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 2 0.653 0.744 DIFFERENCE_1_IBUF (DIFFERENCE_1_IBUF) + LUT1:I0->O 1 0.347 0.000 DIFFERENCE_1_IBUF_rt (DIFFERENCE_1_IBUF_rt) + MUXCY:S->O 1 0.235 0.000 arithmetic_unit_DIFFERENCE2<1>cy (arithmetic_unit_DIFFERENCE2<1>_cyo) + MUXCY:CI->O 1 0.042 0.000 arithmetic_unit_DIFFERENCE2<2>cy (arithmetic_unit_DIFFERENCE2<2>_cyo) + MUXCY:CI->O 1 0.042 0.000 arithmetic_unit_DIFFERENCE2<3>cy (arithmetic_unit_DIFFERENCE2<3>_cyo) + MUXCY:CI->O 1 0.042 0.000 arithmetic_unit_DIFFERENCE2<4>cy (arithmetic_unit_DIFFERENCE2<4>_cyo) + MUXCY:CI->O 1 0.042 0.000 arithmetic_unit_DIFFERENCE2<5>cy (arithmetic_unit_DIFFERENCE2<5>_cyo) + MUXCY:CI->O 1 0.042 0.000 arithmetic_unit_DIFFERENCE2<6>cy (arithmetic_unit_DIFFERENCE2<6>_cyo) + MUXCY:CI->O 1 0.042 0.000 arithmetic_unit_DIFFERENCE2<7>cy (arithmetic_unit_DIFFERENCE2<7>_cyo) + MUXCY:CI->O 1 0.042 0.000 arithmetic_unit_DIFFERENCE2<8>cy (arithmetic_unit_DIFFERENCE2<8>_cyo) + MUXCY:CI->O 1 0.042 0.000 arithmetic_unit_DIFFERENCE2<9>cy (arithmetic_unit_DIFFERENCE2<9>_cyo) + MUXCY:CI->O 1 0.042 0.000 arithmetic_unit_DIFFERENCE2<10>cy (arithmetic_unit_DIFFERENCE2<10>_cyo) + MUXCY:CI->O 1 0.042 0.000 arithmetic_unit_DIFFERENCE2<11>cy (arithmetic_unit_DIFFERENCE2<11>_cyo) + MUXCY:CI->O 1 0.042 0.000 arithmetic_unit_DIFFERENCE2<12>cy (arithmetic_unit_DIFFERENCE2<12>_cyo) + MUXCY:CI->O 1 0.042 0.000 arithmetic_unit_DIFFERENCE2<13>cy (arithmetic_unit_DIFFERENCE2<13>_cyo) + MUXCY:CI->O 1 0.042 0.000 arithmetic_unit_DIFFERENCE2<14>cy (arithmetic_unit_DIFFERENCE2<14>_cyo) + XORCY:CI->O 1 0.824 0.382 arithmetic_unit_DIFFERENCE2<15>_xor (DIFFERENCE2<15>) + MULT18X18S:A15 3.000 Mmult__n00001_inst_mult_0 + ---------------------------------------- + Total 6.731ns (5.605ns logic, 1.126ns route) + (83.3% logic, 16.7% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'CLOCK' + Total number of paths / destination ports: 3233 / 65 +------------------------------------------------------------------------- +Offset: 10.035ns (Levels of Logic = 7) + Source: Mmult__n00001_inst_mult_0 (MULT) + Destination: RESULT_OUT0<15> (PAD) + Source Clock: CLOCK rising + + Data Path: Mmult__n00001_inst_mult_0 to RESULT_OUT0<15> + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + MULT18X18S:C->P23 3 1.879 0.700 Mmult__n00001_inst_mult_0 (PRODUCT<23>) + LUT2:I1->O 1 0.347 0.000 arithmetic_unit_RESULT_OUT1<13>lut (N54) + MUXCY:S->O 1 0.235 0.000 arithmetic_unit_RESULT_OUT1<13>cy (arithmetic_unit_RESULT_OUT1<13>_cyo) + XORCY:CI->O 2 0.824 0.518 arithmetic_unit_RESULT_OUT1<14>_xor (RESULT_OUT1_14_OBUF) + INV:I->O 1 0.347 0.000 arithmetic_unit_RESULT_OUT0<14>lut_INV_0 (N70) + MUXCY:S->O 0 0.235 0.000 arithmetic_unit_RESULT_OUT0<14>cy (arithmetic_unit_RESULT_OUT0<14>_cyo) + XORCY:CI->O 1 0.824 0.383 arithmetic_unit_RESULT_OUT0<15>_xor (RESULT_OUT0_15_OBUF) + OBUF:I->O 3.743 RESULT_OUT0_15_OBUF (RESULT_OUT0<15>) + ---------------------------------------- + Total 10.035ns (8.434ns logic, 1.601ns route) + (84.0% logic, 16.0% route) + +========================================================================= +CPU : 4.94 / 5.31 s | Elapsed : 5.00 / 6.00 s + +--> + +Total memory usage is 100604 kilobytes + +Number of errors : 0 ( 0 filtered) +Number of warnings : 7 ( 0 filtered) +Number of infos : 0 ( 0 filtered) +
trunk/docs/synthesis_reports/common/arithmetic_unit.syr Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/docs/synthesis_reports/common/convergence_check.syr =================================================================== --- trunk/docs/synthesis_reports/common/convergence_check.syr (nonexistent) +++ trunk/docs/synthesis_reports/common/convergence_check.syr (revision 9) @@ -0,0 +1,230 @@ +Release 7.1.04i - xst H.42 +Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. +--> Parameter TMPDIR set to __projnav +CPU : 0.00 / 0.33 s | Elapsed : 0.00 / 0.00 s + +--> Parameter xsthdpdir set to ./xst +CPU : 0.00 / 0.33 s | Elapsed : 0.00 / 0.00 s + +--> Reading design: convergence_check.prj + +TABLE OF CONTENTS + 1) Synthesis Options Summary + 2) HDL Compilation + 3) HDL Analysis + 4) HDL Synthesis + 5) Advanced HDL Synthesis + 5.1) HDL Synthesis Report + 6) Low Level Synthesis + 7) Final Report + 7.1) Device utilization summary + 7.2) TIMING REPORT + + +========================================================================= +* Synthesis Options Summary * +========================================================================= +---- Source Parameters +Input File Name : "convergence_check.prj" +Input Format : mixed +Ignore Synthesis Constraint File : NO + +---- Target Parameters +Output File Name : "convergence_check" +Output Format : NGC +Target Device : xc2v250-6-cs144 + +---- Source Options +Top Module Name : convergence_check +Automatic FSM Extraction : YES +FSM Encoding Algorithm : Auto +FSM Style : lut +RAM Extraction : Yes +RAM Style : Auto +ROM Extraction : Yes +ROM Style : Auto +Mux Extraction : YES +Mux Style : Auto +Decoder Extraction : YES +Priority Encoder Extraction : YES +Shift Register Extraction : YES +Logical Shifter Extraction : YES +XOR Collapsing : YES +Resource Sharing : YES +Multiplier Style : auto +Automatic Register Balancing : No + +---- Target Options +Add IO Buffers : YES +Global Maximum Fanout : 500 +Add Generic Clock Buffer(BUFG) : 16 +Register Duplication : YES +Equivalent register Removal : YES +Slice Packing : YES +Pack IO Registers into IOBs : auto + +---- General Options +Optimization Goal : Speed +Optimization Effort : 1 +Keep Hierarchy : NO +Global Optimization : AllClockNets +RTL Output : Yes +Write Timing Constraints : NO +Hierarchy Separator : _ +Bus Delimiter : <> +Case Specifier : maintain +Slice Utilization Ratio : 100 +Slice Utilization Ratio Delta : 5 + +---- Other Options +lso : convergence_check.lso +Read Cores : YES +cross_clock_analysis : NO +verilog2001 : YES +safe_implementation : No +Optimize Instantiated Primitives : NO +tristate2logic : Yes +use_clock_enable : Yes +use_sync_set : Yes +use_sync_reset : Yes +enable_auto_floorplanning : No + +========================================================================= + + +========================================================================= +* HDL Compilation * +========================================================================= +Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/CONVERGENCE_CHECK.vhd" in Library work. +Architecture rtl of Entity convergence_check is up to date. + +========================================================================= +* HDL Analysis * +========================================================================= +Analyzing Entity (Architecture ). +Entity analyzed. Unit generated. + + +========================================================================= +* HDL Synthesis * +========================================================================= + +Synthesizing Unit . + Related source file is "C:/Xilinx/bin/ArithmeticDecoder/CONVERGENCE_CHECK.vhd". +Unit synthesized. + + +========================================================================= +* Advanced HDL Synthesis * +========================================================================= + +Advanced RAM inference ... +Advanced multiplier inference ... +Advanced Registered AddSub inference ... +Dynamic shift register inference ... + +========================================================================= +HDL Synthesis Report + +Found no macro +========================================================================= + +========================================================================= +* Low Level Synthesis * +========================================================================= + +Optimizing unit ... +Loading device for application Rf_Device from file '2v250.nph' in environment C:/Xilinx. + +Mapping all equations... +Building and optimizing final netlist ... +Found area constraint ratio of 100 (+ 5) on block convergence_check, actual ratio is 0. + +========================================================================= +* Final Report * +========================================================================= +Final Results +RTL Top Level Output File Name : convergence_check.ngr +Top Level Output File Name : convergence_check +Output Format : NGC +Optimization Goal : Speed +Keep Hierarchy : NO + +Design Statistics +# IOs : 7 + +Cell Usage : +# BELS : 3 +# LUT2 : 1 +# LUT3 : 1 +# LUT4 : 1 +# IO Buffers : 7 +# IBUF : 5 +# OBUF : 2 +========================================================================= + +Device utilization summary: +--------------------------- + +Selected Device : 2v250cs144-6 + + Number of Slices: 2 out of 1536 0% + Number of 4 input LUTs: 3 out of 3072 0% + Number of bonded IOBs: 7 out of 92 7% + + +========================================================================= +TIMING REPORT + +NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. + FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT + GENERATED AFTER PLACE-and-ROUTE. + +Clock Information: +------------------ +No clock signals found in this design + +Timing Summary: +--------------- +Speed Grade: -6 + + Minimum period: No path found + Minimum input arrival time before clock: No path found + Maximum output required time after clock: No path found + Maximum combinational path delay: 6.703ns + +Timing Detail: +-------------- +All values displayed in nanoseconds (ns) + +========================================================================= +Timing constraint: Default path analysis + Total number of paths / destination ports: 8 / 2 +------------------------------------------------------------------------- +Delay: 6.703ns (Levels of Logic = 4) + Source: LOW_MSB (PAD) + Destination: TRIGGER_FOLLOW (PAD) + + Data Path: LOW_MSB to TRIGGER_FOLLOW + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 2 0.653 0.684 LOW_MSB_IBUF (LOW_MSB_IBUF) + LUT4:I1->O 1 0.347 0.548 TRIGGER_FOLLOW1 (N1) + LUT2:I1->O 1 0.347 0.383 TRIGGER_FOLLOW2 (TRIGGER_FOLLOW_OBUF) + OBUF:I->O 3.743 TRIGGER_FOLLOW_OBUF (TRIGGER_FOLLOW) + ---------------------------------------- + Total 6.703ns (5.090ns logic, 1.614ns route) + (75.9% logic, 24.1% route) + +========================================================================= +CPU : 4.06 / 4.42 s | Elapsed : 4.00 / 4.00 s + +--> + +Total memory usage is 100604 kilobytes + +Number of errors : 0 ( 0 filtered) +Number of warnings : 0 ( 0 filtered) +Number of infos : 0 ( 0 filtered) +
trunk/docs/synthesis_reports/common/convergence_check.syr Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/docs/synthesis_reports/common/context_manager.syr =================================================================== --- trunk/docs/synthesis_reports/common/context_manager.syr (nonexistent) +++ trunk/docs/synthesis_reports/common/context_manager.syr (revision 9) @@ -0,0 +1,619 @@ +Release 7.1.04i - xst H.42 +Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. +--> Parameter TMPDIR set to __projnav +CPU : 0.00 / 0.33 s | Elapsed : 0.00 / 0.00 s + +--> Parameter xsthdpdir set to ./xst +CPU : 0.00 / 0.33 s | Elapsed : 0.00 / 0.00 s + +--> Reading design: context_manager.prj + +TABLE OF CONTENTS + 1) Synthesis Options Summary + 2) HDL Compilation + 3) HDL Analysis + 4) HDL Synthesis + 5) Advanced HDL Synthesis + 5.1) HDL Synthesis Report + 6) Low Level Synthesis + 7) Final Report + 7.1) Device utilization summary + 7.2) TIMING REPORT + + +========================================================================= +* Synthesis Options Summary * +========================================================================= +---- Source Parameters +Input File Name : "context_manager.prj" +Input Format : mixed +Ignore Synthesis Constraint File : NO + +---- Target Parameters +Output File Name : "context_manager" +Output Format : NGC +Target Device : xc2v250-6-cs144 + +---- Source Options +Top Module Name : context_manager +Automatic FSM Extraction : YES +FSM Encoding Algorithm : Auto +FSM Style : lut +RAM Extraction : Yes +RAM Style : Auto +ROM Extraction : Yes +ROM Style : Auto +Mux Extraction : YES +Mux Style : Auto +Decoder Extraction : YES +Priority Encoder Extraction : YES +Shift Register Extraction : YES +Logical Shifter Extraction : YES +XOR Collapsing : YES +Resource Sharing : YES +Multiplier Style : auto +Automatic Register Balancing : No + +---- Target Options +Add IO Buffers : YES +Global Maximum Fanout : 500 +Add Generic Clock Buffer(BUFG) : 16 +Register Duplication : YES +Equivalent register Removal : YES +Slice Packing : YES +Pack IO Registers into IOBs : auto + +---- General Options +Optimization Goal : Speed +Optimization Effort : 1 +Keep Hierarchy : NO +Global Optimization : AllClockNets +RTL Output : Yes +Write Timing Constraints : NO +Hierarchy Separator : _ +Bus Delimiter : <> +Case Specifier : maintain +Slice Utilization Ratio : 100 +Slice Utilization Ratio Delta : 5 + +---- Other Options +lso : context_manager.lso +Read Cores : YES +cross_clock_analysis : NO +verilog2001 : YES +safe_implementation : No +Optimize Instantiated Primitives : NO +tristate2logic : Yes +use_clock_enable : Yes +use_sync_set : Yes +use_sync_reset : Yes +enable_auto_floorplanning : No + +========================================================================= + + +========================================================================= +* HDL Compilation * +========================================================================= +Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/Divider.vhd" in Library work. +Architecture rtl of Entity divider is up to date. +Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/UPDATER.vhd" in Library work. +Architecture rtl of Entity updater is up to date. +Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd" in Library work. +Architecture rtl of Entity halving_manager is up to date. +Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/CONTEXT_MANAGER.vhd" in Library work. +Architecture rtl of Entity context_manager is up to date. + +========================================================================= +* HDL Analysis * +========================================================================= +Analyzing Entity (Architecture ). +WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/CONTEXT_MANAGER.vhd" line 133: Index value(s) does not match array range, simulation mismatch. +WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/CONTEXT_MANAGER.vhd" line 137: Index value(s) does not match array range, simulation mismatch. +Entity analyzed. Unit generated. + +Analyzing Entity (Architecture ). +WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/Divider.vhd" line 1079: Index value(s) does not match array range, simulation mismatch. +Entity analyzed. Unit generated. + +Analyzing Entity (Architecture ). +Entity analyzed. Unit generated. + +Analyzing Entity (Architecture ). +WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd" line 71: Index value(s) does not match array range, simulation mismatch. +WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd" line 71: Index value(s) does not match array range, simulation mismatch. +WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd" line 73: Index value(s) does not match array range, simulation mismatch. +WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd" line 108: Index value(s) does not match array range, simulation mismatch. +Entity analyzed. Unit generated. + + +========================================================================= +* HDL Synthesis * +========================================================================= + +Synthesizing Unit . + Related source file is "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd". + Found 3-bit 46-to-1 multiplexer for signal <$n0002> created at line 108. + Found 3-bit 4-to-1 multiplexer for signal <$n0050>. + Found 3-bit 4-to-1 multiplexer for signal <$n0051>. + Found 3-bit 4-to-1 multiplexer for signal <$n0052>. + Found 3-bit 4-to-1 multiplexer for signal <$n0053>. + Found 3-bit 4-to-1 multiplexer for signal <$n0054>. + Found 3-bit 4-to-1 multiplexer for signal <$n0055>. + Found 3-bit 4-to-1 multiplexer for signal <$n0056>. + Found 3-bit 4-to-1 multiplexer for signal <$n0057>. + Found 3-bit 4-to-1 multiplexer for signal <$n0058>. + Found 3-bit 4-to-1 multiplexer for signal <$n0059>. + Found 3-bit 4-to-1 multiplexer for signal <$n0060>. + Found 3-bit 4-to-1 multiplexer for signal <$n0061>. + Found 3-bit 4-to-1 multiplexer for signal <$n0062>. + Found 3-bit 4-to-1 multiplexer for signal <$n0063>. + Found 3-bit 4-to-1 multiplexer for signal <$n0064>. + Found 3-bit 4-to-1 multiplexer for signal <$n0065>. + Found 3-bit 4-to-1 multiplexer for signal <$n0066>. + Found 3-bit 4-to-1 multiplexer for signal <$n0067>. + Found 3-bit 4-to-1 multiplexer for signal <$n0068>. + Found 3-bit 4-to-1 multiplexer for signal <$n0069>. + Found 3-bit 4-to-1 multiplexer for signal <$n0070>. + Found 3-bit 4-to-1 multiplexer for signal <$n0071>. + Found 3-bit 4-to-1 multiplexer for signal <$n0072>. + Found 3-bit 4-to-1 multiplexer for signal <$n0073>. + Found 3-bit 4-to-1 multiplexer for signal <$n0074>. + Found 3-bit 4-to-1 multiplexer for signal <$n0075>. + Found 3-bit 4-to-1 multiplexer for signal <$n0076>. + Found 3-bit 4-to-1 multiplexer for signal <$n0077>. + Found 3-bit 4-to-1 multiplexer for signal <$n0078>. + Found 3-bit 4-to-1 multiplexer for signal <$n0079>. + Found 3-bit 4-to-1 multiplexer for signal <$n0080>. + Found 3-bit 4-to-1 multiplexer for signal <$n0081>. + Found 3-bit 4-to-1 multiplexer for signal <$n0082>. + Found 3-bit 4-to-1 multiplexer for signal <$n0084>. + Found 3-bit 4-to-1 multiplexer for signal <$n0085>. + Found 3-bit 4-to-1 multiplexer for signal <$n0087>. + Found 3-bit 4-to-1 multiplexer for signal <$n0088>. + Found 3-bit 4-to-1 multiplexer for signal <$n0089>. + Found 3-bit 4-to-1 multiplexer for signal <$n0090>. + Found 3-bit 4-to-1 multiplexer for signal <$n0091>. + Found 3-bit 4-to-1 multiplexer for signal <$n0092>. + Found 3-bit 4-to-1 multiplexer for signal <$n0093>. + Found 3-bit 4-to-1 multiplexer for signal <$n0094>. + Found 3-bit 4-to-1 multiplexer for signal <$n0095>. + Found 3-bit 4-to-1 multiplexer for signal <$n0096>. + Found 3-bit 4-to-1 multiplexer for signal <$n0097>. + Found 3-bit addsub for signal <$n0098>. + Found 3-bit addsub for signal <$n0100>. + Found 3-bit addsub for signal <$n0101>. + Found 3-bit addsub for signal <$n0102>. + Found 3-bit addsub for signal <$n0103>. + Found 3-bit addsub for signal <$n0104>. + Found 3-bit addsub for signal <$n0105>. + Found 3-bit addsub for signal <$n0106>. + Found 3-bit addsub for signal <$n0107>. + Found 3-bit addsub for signal <$n0108>. + Found 3-bit addsub for signal <$n0109>. + Found 3-bit addsub for signal <$n0110>. + Found 3-bit addsub for signal <$n0111>. + Found 3-bit addsub for signal <$n0112>. + Found 3-bit addsub for signal <$n0113>. + Found 3-bit addsub for signal <$n0114>. + Found 3-bit addsub for signal <$n0115>. + Found 3-bit addsub for signal <$n0116>. + Found 3-bit addsub for signal <$n0117>. + Found 3-bit addsub for signal <$n0118>. + Found 3-bit addsub for signal <$n0119>. + Found 3-bit addsub for signal <$n0120>. + Found 3-bit addsub for signal <$n0121>. + Found 3-bit addsub for signal <$n0122>. + Found 3-bit addsub for signal <$n0123>. + Found 3-bit addsub for signal <$n0124>. + Found 3-bit addsub for signal <$n0125>. + Found 3-bit addsub for signal <$n0126>. + Found 3-bit addsub for signal <$n0127>. + Found 3-bit addsub for signal <$n0128>. + Found 3-bit addsub for signal <$n0129>. + Found 3-bit addsub for signal <$n0130>. + Found 3-bit addsub for signal <$n0131>. + Found 3-bit addsub for signal <$n0132>. + Found 3-bit addsub for signal <$n0133>. + Found 3-bit addsub for signal <$n0134>. + Found 3-bit addsub for signal <$n0135>. + Found 3-bit addsub for signal <$n0136>. + Found 3-bit addsub for signal <$n0137>. + Found 3-bit addsub for signal <$n0138>. + Found 3-bit addsub for signal <$n0139>. + Found 3-bit addsub for signal <$n0140>. + Found 3-bit addsub for signal <$n0141>. + Found 3-bit addsub for signal <$n0142>. + Found 3-bit addsub for signal <$n0143>. + Found 3-bit addsub for signal <$n0144>. + Found 10-bit comparator greater for signal <$n0147> created at line 99. + Found 3-bit comparator greater for signal <$n0241> created at line 108. + Found 1-bit register for signal . + Found 10-bit register for signal . + Found 10-bit adder for signal . + Found 10-bit register for signal . + Found 10-bit adder for signal . + Found 138-bit register for signal . + Summary: + inferred 139 D-type flip-flop(s). + inferred 48 Adder/Subtractor(s). + inferred 2 Comparator(s). + inferred 141 Multiplexer(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/UPDATER.vhd". +WARNING:Xst:1780 - Signal is never used or assigned. + Found 1-bit register for signal . + Found 10-bit 4-to-1 multiplexer for signal . + Found 10-bit 4-to-1 multiplexer for signal . + Found 10-bit adder for signal <$n0009> created at line 51. + Found 10-bit adder for signal <$n0011> created at line 73. + Found 10-bit adder for signal <$n0012> created at line 84. + Found 10-bit adder for signal <$n0013> created at line 62. + Found 10-bit register for signal . + Found 10-bit register for signal . + Found 10-bit register for signal . + Found 10-bit register for signal . + Found 10-bit register for signal . + Found 1-bit xor2 for signal . + Summary: + inferred 1 D-type flip-flop(s). + inferred 4 Adder/Subtractor(s). + inferred 20 Multiplexer(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/Divider.vhd". +WARNING:Xst:646 - Signal > is assigned but never used. +WARNING:Xst:646 - Signal > is assigned but never used. + Found 1022x32-bit ROM for signal <$n0002> created at line 1079. + Found 16x10-bit multiplier for signal <$n0003> created at line 1086. + Found 16x10-bit multiplier for signal <$n0004> created at line 1093. + Found 10-bit subtractor for signal . + Found 10-bit register for signal . + Found 26-bit register for signal . + Found 26-bit register for signal . + Found 32-bit register for signal . + Found 42-bit adder for signal . + Summary: + inferred 1 ROM(s). + inferred 84 D-type flip-flop(s). + inferred 2 Adder/Subtractor(s). + inferred 2 Multiplier(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/CONTEXT_MANAGER.vhd". + Found 46x20-bit dual-port block RAM for signal . + ----------------------------------------------------------------------- + | mode | write-first | | + | aspect ratio | 46-word x 20-bit | | + | clock | connected to signal | rise | + | dual clock | connected to signal | rise | + | dual enable | connected to signal | high | + | write enable | connected to signal | high | + | address | connected to signal | | + | dual address | connected to signal | | + | data in | connected to signal | | + | data out | not connected | | + | dual data out | connected to signal | | + | ram_style | Auto | | + ----------------------------------------------------------------------- + Found 1-bit 64-to-1 multiplexer for signal <$n0003> created at line 141. + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 6-bit register for signal . + Found 6-bit register for signal . + Found 64-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 79 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing. + +========================================================================= +* Advanced HDL Synthesis * +========================================================================= + +Advanced RAM inference ... +INFO:Xst:1647 - Data output of ROM in block is tied to register in block . +INFO:Xst:1650 - The register is removed and the ROM is implemented as read-only block RAM. +Advanced multiplier inference ... + Found registered multiplier on signal <_n0003>: + - 1 register level(s) found in a register connected to the multiplier macro ouput. + Pushing register(s) into the multiplier macro. + Found registered multiplier on signal <_n0004>: + - 1 register level(s) found in a register connected to the multiplier macro ouput. + Pushing register(s) into the multiplier macro. +Advanced Registered AddSub inference ... +Dynamic shift register inference ... + +========================================================================= +HDL Synthesis Report + +Macro Statistics +# Block RAMs : 2 + 1022x32-bit single-port block RAM : 1 + 46x20-bit dual-port block RAM : 1 +# Multipliers : 2 + 16x10-bit registered multiplier : 2 +# Adders/Subtractors : 54 + 10-bit adder : 6 + 10-bit subtractor : 1 + 3-bit addsub : 46 + 42-bit adder : 1 +# Registers : 125 + 1-bit register : 69 + 10-bit register : 8 + 3-bit register : 46 + 6-bit register : 2 +# Comparators : 2 + 10-bit comparator greater : 1 + 3-bit comparator greater : 1 +# Multiplexers : 50 + 1-bit 64-to-1 multiplexer : 1 + 10-bit 4-to-1 multiplexer : 2 + 3-bit 4-to-1 multiplexer : 46 + 3-bit 46-to-1 multiplexer : 1 +# Xors : 1 + 1-bit xor2 : 1 + +========================================================================= + +========================================================================= +* Low Level Synthesis * +========================================================================= + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... +Loading device for application Rf_Device from file '2v250.nph' in environment C:/Xilinx. + +Mapping all equations... +Building and optimizing final netlist ... +Register equivalent to has been removed +Register equivalent to has been removed +Register equivalent to has been removed +Register equivalent to has been removed +Register equivalent to has been removed +Register equivalent to has been removed +Register equivalent to has been removed +Register equivalent to has been removed +Register equivalent to has been removed +Register equivalent to has been removed +Register equivalent to has been removed +Found area constraint ratio of 100 (+ 5) on block context_manager, actual ratio is 24. +FlipFlop READ_ADDRESS_0 has been replicated 3 time(s) + +========================================================================= +* Final Report * +========================================================================= +Final Results +RTL Top Level Output File Name : context_manager.ngr +Top Level Output File Name : context_manager +Output Format : NGC +Optimization Goal : Speed +Keep Hierarchy : NO + +Design Statistics +# IOs : 23 + +Macro Statistics : +# RAM : 2 +# 1022x32-bit single-port block RAM: 1 +# 46x20-bit dual-port block RAM: 1 +# Registers : 197 +# 1-bit register : 149 +# 3-bit register : 46 +# 6-bit register : 2 +# Multiplexers : 50 +# 1-bit 64-to-1 multiplexer : 1 +# 10-bit 4-to-1 multiplexer : 2 +# 3-bit 4-to-1 multiplexer : 46 +# 3-bit 46-to-1 multiplexer : 1 +# Adders/Subtractors : 8 +# 10-bit adder : 6 +# 10-bit subtractor : 1 +# 42-bit adder : 1 +# Multipliers : 2 +# 16x10-bit registered multiplier: 2 +# Comparators : 2 +# 10-bit comparator greater : 1 +# 3-bit comparator greater : 1 +# Xors : 92 +# 1-bit xor3 : 92 + +Cell Usage : +# BELS : 960 +# GND : 1 +# INV : 1 +# LUT1 : 20 +# LUT1_L : 9 +# LUT2 : 33 +# LUT3 : 89 +# LUT3_D : 4 +# LUT3_L : 151 +# LUT4 : 319 +# LUT4_D : 24 +# LUT4_L : 16 +# MUXCY : 77 +# MUXF5 : 107 +# MUXF6 : 23 +# MUXF7 : 10 +# MUXF8 : 5 +# VCC : 1 +# XORCY : 70 +# FlipFlops/Latches : 291 +# FD : 6 +# FDE : 9 +# FDR : 48 +# FDRE : 156 +# FDRSE : 1 +# FDS : 5 +# FDSE : 66 +# RAMS : 3 +# RAMB16_S18 : 2 +# RAMB16_S36_S36 : 1 +# Clock Buffers : 1 +# BUFGP : 1 +# IO Buffers : 22 +# IBUF : 11 +# OBUF : 11 +# MULTs : 2 +# MULT18X18S : 2 +========================================================================= + +Device utilization summary: +--------------------------- + +Selected Device : 2v250cs144-6 + + Number of Slices: 359 out of 1536 23% + Number of Slice Flip Flops: 291 out of 3072 9% + Number of 4 input LUTs: 665 out of 3072 21% + Number of bonded IOBs: 23 out of 92 25% + Number of BRAMs: 3 out of 24 12% + Number of MULT18X18s: 2 out of 24 8% + Number of GCLKs: 1 out of 16 6% + + +========================================================================= +TIMING REPORT + +NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. + FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT + GENERATED AFTER PLACE-and-ROUTE. + +Clock Information: +------------------ +-----------------------------------+------------------------+-------+ +Clock Signal | Clock buffer(FF name) | Load | +-----------------------------------+------------------------+-------+ +CLOCK | BUFGP | 294 | +-----------------------------------+------------------------+-------+ + +Timing Summary: +--------------- +Speed Grade: -6 + + Minimum period: 9.680ns (Maximum Frequency: 103.303MHz) + Minimum input arrival time before clock: 10.225ns + Maximum output required time after clock: 8.362ns + Maximum combinational path delay: No path found + +Timing Detail: +-------------- +All values displayed in nanoseconds (ns) + +========================================================================= +Timing constraint: Default period analysis for Clock 'CLOCK' + Clock period: 9.680ns (frequency: 103.303MHz) + Total number of paths / destination ports: 223210 / 475 +------------------------------------------------------------------------- +Delay: 9.680ns (Levels of Logic = 12) + Source: REFRESH_SHIFTS_0_1 (FF) + Destination: Mram_PROBABILITY_inst_ramb_0 (RAM) + Source Clock: CLOCK rising + Destination Clock: CLOCK rising + + Data Path: REFRESH_SHIFTS_0_1 to Mram_PROBABILITY_inst_ramb_0 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDRE:C->Q 5 0.449 0.734 REFRESH_SHIFTS_0_1 (REFRESH_SHIFTS_0_1) + LUT3_L:I1->LO 1 0.347 0.000 REFRESH_CONTEXT<4>31 (REFRESH_MUX_BLOCK_N38) + MUXF5:I0->O 1 0.345 0.000 REFRESH_CONTEXT<1>_rn_14 (REFRESH_MUX_BLOCK_CONTEXT<1>_MUXF515) + MUXF6:I0->O 1 0.354 0.000 REFRESH_CONTEXT<0>_rn_9 (REFRESH_MUX_BLOCK_CONTEXT<0>_MUXF67) + MUXF7:I0->O 1 0.354 0.000 REFRESH_CONTEXT<2>_rn_3 (REFRESH_MUX_BLOCK_CONTEXT<2>_MUXF73) + MUXF8:I0->O 1 0.354 0.608 REFRESH_CONTEXT<3>_rn_0 (REFRESH_MUX_BLOCK_CONTEXT<3>_MUXF81) + LUT3_L:I0->LO 1 0.347 0.000 REFRESH__n0241109_F (N797) + MUXF5:I0->O 15 0.345 0.763 REFRESH__n0241109 (REFRESH__n0241) + LUT4_D:I3->O 7 0.347 0.630 REFRESH__n0145_1 (REFRESH__n01451) + LUT3:I2->O 1 0.347 0.548 REFRESH_DENOMINATOR_OUT<3>1 (FRACTION2<3>) + LUT4:I1->O 1 0.347 0.409 PROBUPDATE__n00144 (CHOICE11) + LUT4:I2->O 20 0.347 0.769 PROBUPDATE__n001417 (PROBUPDATE_HALVE_VALUES) + MUXF5:S->O 1 0.553 0.382 PROBUPDATE_DENOMINATOR_OUT<0>_DENOMINATOR_OUT<0>_rn_6111 (NEWPROB<17>) + RAMB16_S36_S36:DIA17 0.000 Mram_PROBABILITY_inst_ramb_0 + ---------------------------------------- + Total 9.680ns (4.836ns logic, 4.844ns route) + (50.0% logic, 50.0% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'CLOCK' + Total number of paths / destination ports: 124256 / 757 +------------------------------------------------------------------------- +Offset: 10.225ns (Levels of Logic = 13) + Source: CONTEXT_NUMBER<4> (PAD) + Destination: Mram_PROBABILITY_inst_ramb_0 (RAM) + Destination Clock: CLOCK rising + + Data Path: CONTEXT_NUMBER<4> to Mram_PROBABILITY_inst_ramb_0 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 56 0.653 1.075 CONTEXT_NUMBER_4_IBUF (CONTEXT_NUMBER_4_IBUF) + LUT3_L:I0->LO 1 0.347 0.000 REFRESH_CONTEXT<4>19 (REFRESH_MUX_BLOCK_N26) + MUXF5:I0->O 1 0.345 0.000 REFRESH_CONTEXT<1>_rn_8 (REFRESH_MUX_BLOCK_CONTEXT<1>_MUXF59) + MUXF6:I0->O 1 0.354 0.000 REFRESH_CONTEXT<0>_rn_6 (REFRESH_MUX_BLOCK_CONTEXT<0>_MUXF64) + MUXF7:I1->O 1 0.354 0.000 REFRESH_CONTEXT<2>_rn_2 (REFRESH_MUX_BLOCK_CONTEXT<2>_MUXF72) + MUXF8:I1->O 1 0.354 0.608 REFRESH_CONTEXT<3>_rn_0 (REFRESH_MUX_BLOCK_CONTEXT<3>_MUXF81) + LUT3_L:I0->LO 1 0.347 0.000 REFRESH__n0241109_F (N797) + MUXF5:I0->O 15 0.345 0.763 REFRESH__n0241109 (REFRESH__n0241) + LUT4_D:I3->O 7 0.347 0.630 REFRESH__n0145_1 (REFRESH__n01451) + LUT3:I2->O 1 0.347 0.548 REFRESH_DENOMINATOR_OUT<3>1 (FRACTION2<3>) + LUT4:I1->O 1 0.347 0.409 PROBUPDATE__n00144 (CHOICE11) + LUT4:I2->O 20 0.347 0.769 PROBUPDATE__n001417 (PROBUPDATE_HALVE_VALUES) + MUXF5:S->O 1 0.553 0.382 PROBUPDATE_DENOMINATOR_OUT<0>_DENOMINATOR_OUT<0>_rn_6111 (NEWPROB<17>) + RAMB16_S36_S36:DIA17 0.000 Mram_PROBABILITY_inst_ramb_0 + ---------------------------------------- + Total 10.225ns (5.040ns logic, 5.185ns route) + (49.3% logic, 50.7% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'CLOCK' + Total number of paths / destination ports: 301 / 11 +------------------------------------------------------------------------- +Offset: 8.362ns (Levels of Logic = 9) + Source: DIVISION_Mmult__n00041_inst_mult_0 (MULT) + Destination: PROB<9> (PAD) + Source Clock: CLOCK rising + + Data Path: DIVISION_Mmult__n00041_inst_mult_0 to PROB<9> + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + MULT18X18S:C->P25 1 2.073 0.548 DIVISION_Mmult__n00041_inst_mult_0 (DIVISION_PRODUCT2<25>) + LUT2:I1->O 1 0.347 0.000 DIVISION_DIVIDER_QUOTIENT<3>lut (DIVISION_N23) + MUXCY:S->O 1 0.235 0.000 DIVISION_DIVIDER_QUOTIENT<3>cy (DIVISION_DIVIDER_QUOTIENT<3>_cyo) + MUXCY:CI->O 1 0.042 0.000 DIVISION_DIVIDER_QUOTIENT<4>cy (DIVISION_DIVIDER_QUOTIENT<4>_cyo) + MUXCY:CI->O 1 0.042 0.000 DIVISION_DIVIDER_QUOTIENT<5>cy (DIVISION_DIVIDER_QUOTIENT<5>_cyo) + MUXCY:CI->O 1 0.042 0.000 DIVISION_DIVIDER_QUOTIENT<6>cy (DIVISION_DIVIDER_QUOTIENT<6>_cyo) + MUXCY:CI->O 1 0.042 0.000 DIVISION_DIVIDER_QUOTIENT<7>cy (DIVISION_DIVIDER_QUOTIENT<7>_cyo) + MUXCY:CI->O 0 0.042 0.000 DIVISION_DIVIDER_QUOTIENT<8>cy (DIVISION_DIVIDER_QUOTIENT<8>_cyo) + XORCY:CI->O 1 0.824 0.383 DIVISION_DIVIDER_QUOTIENT<9>_xor (PROB_9_OBUF) + OBUF:I->O 3.743 PROB_9_OBUF (PROB<9>) + ---------------------------------------- + Total 8.362ns (7.432ns logic, 0.930ns route) + (88.9% logic, 11.1% route) + +========================================================================= +CPU : 18.47 / 18.83 s | Elapsed : 18.00 / 18.00 s + +--> + +Total memory usage is 106748 kilobytes + +Number of errors : 0 ( 0 filtered) +Number of warnings : 10 ( 0 filtered) +Number of infos : 3 ( 0 filtered) +
trunk/docs/synthesis_reports/common/context_manager.syr Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/docs/synthesis_reports/common/input_control.syr =================================================================== --- trunk/docs/synthesis_reports/common/input_control.syr (nonexistent) +++ trunk/docs/synthesis_reports/common/input_control.syr (revision 9) @@ -0,0 +1,391 @@ +Release 7.1.04i - xst H.42 +Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. +--> Parameter TMPDIR set to __projnav +CPU : 0.00 / 0.34 s | Elapsed : 0.00 / 1.00 s + +--> Parameter xsthdpdir set to ./xst +CPU : 0.00 / 0.34 s | Elapsed : 0.00 / 1.00 s + +--> Reading design: input_control.prj + +TABLE OF CONTENTS + 1) Synthesis Options Summary + 2) HDL Compilation + 3) HDL Analysis + 4) HDL Synthesis + 5) Advanced HDL Synthesis + 5.1) HDL Synthesis Report + 6) Low Level Synthesis + 7) Final Report + 7.1) Device utilization summary + 7.2) TIMING REPORT + + +========================================================================= +* Synthesis Options Summary * +========================================================================= +---- Source Parameters +Input File Name : "input_control.prj" +Input Format : mixed +Ignore Synthesis Constraint File : NO + +---- Target Parameters +Output File Name : "input_control" +Output Format : NGC +Target Device : xc2v250-6-cs144 + +---- Source Options +Top Module Name : input_control +Automatic FSM Extraction : YES +FSM Encoding Algorithm : Auto +FSM Style : lut +RAM Extraction : Yes +RAM Style : Auto +ROM Extraction : Yes +ROM Style : Auto +Mux Extraction : YES +Mux Style : Auto +Decoder Extraction : YES +Priority Encoder Extraction : YES +Shift Register Extraction : YES +Logical Shifter Extraction : YES +XOR Collapsing : YES +Resource Sharing : YES +Multiplier Style : auto +Automatic Register Balancing : No + +---- Target Options +Add IO Buffers : YES +Global Maximum Fanout : 500 +Add Generic Clock Buffer(BUFG) : 16 +Register Duplication : YES +Equivalent register Removal : YES +Slice Packing : YES +Pack IO Registers into IOBs : auto + +---- General Options +Optimization Goal : Speed +Optimization Effort : 1 +Keep Hierarchy : NO +Global Optimization : AllClockNets +RTL Output : Yes +Write Timing Constraints : NO +Hierarchy Separator : _ +Bus Delimiter : <> +Case Specifier : maintain +Slice Utilization Ratio : 100 +Slice Utilization Ratio Delta : 5 + +---- Other Options +lso : input_control.lso +Read Cores : YES +cross_clock_analysis : NO +verilog2001 : YES +safe_implementation : No +Optimize Instantiated Primitives : NO +tristate2logic : Yes +use_clock_enable : Yes +use_sync_set : Yes +use_sync_reset : Yes +enable_auto_floorplanning : No + +========================================================================= + + +========================================================================= +* HDL Compilation * +========================================================================= +Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/FIFO.vhd" in Library work. +Architecture rtl of Entity fifo is up to date. +Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/INPUT_CONTROL.vhd" in Library work. +Architecture rtl of Entity input_control is up to date. + +========================================================================= +* HDL Analysis * +========================================================================= +Analyzing Entity (Architecture ). +Entity analyzed. Unit generated. + +Analyzing generic Entity (Architecture ). + RANK = 8 + WIDTH = 1 +Entity analyzed. Unit generated. + + +========================================================================= +* HDL Synthesis * +========================================================================= + +Synthesizing Unit . + Related source file is "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/FIFO.vhd". + Found 256x1-bit dual-port distributed RAM for signal . + ----------------------------------------------------------------------- + | aspect ratio | 256-word x 1-bit | | + | clock | connected to signal | rise | + | write enable | connected to signal | high | + | address | connected to signal | | + | dual address | connected to signal | | + | data in | connected to signal | | + | data out | not connected | | + | dual data out | connected to signal | | + | ram_style | Auto | | + ----------------------------------------------------------------------- +INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronously. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + Found 8-bit comparator equal for signal <$n0003> created at line 69. + Found 8-bit up counter for signal . + Found 8-bit up counter for signal . + Summary: + inferred 1 RAM(s). + inferred 2 Counter(s). + inferred 1 Comparator(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/INPUT_CONTROL.vhd". + Found 1-bit register for signal >. + Found 1-bit 4-to-1 multiplexer for signal >. + Summary: + inferred 1 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + + +========================================================================= +* Advanced HDL Synthesis * +========================================================================= + +Advanced RAM inference ... +Advanced multiplier inference ... +Advanced Registered AddSub inference ... +Dynamic shift register inference ... + +========================================================================= +HDL Synthesis Report + +Macro Statistics +# LUT RAMs : 1 + 256x1-bit dual-port distributed RAM: 1 +# Counters : 2 + 8-bit up counter : 2 +# Registers : 1 + 1-bit register : 1 +# Comparators : 1 + 8-bit comparator equal : 1 +# Multiplexers : 1 + 1-bit 4-to-1 multiplexer : 1 + +========================================================================= + +========================================================================= +* Low Level Synthesis * +========================================================================= + +Optimizing unit ... + +Optimizing unit ... +Loading device for application Rf_Device from file '2v250.nph' in environment C:/Xilinx. + +Mapping all equations... +Building and optimizing final netlist ... +Found area constraint ratio of 100 (+ 5) on block input_control, actual ratio is 2. +FlipFlop STORAGE_WRITE_ADDRESS_0 has been replicated 1 time(s) +FlipFlop STORAGE_WRITE_ADDRESS_2 has been replicated 1 time(s) + +========================================================================= +* Final Report * +========================================================================= +Final Results +RTL Top Level Output File Name : input_control.ngr +Top Level Output File Name : input_control +Output Format : NGC +Optimization Goal : Speed +Keep Hierarchy : NO + +Design Statistics +# IOs : 8 + +Macro Statistics : +# RAM : 1 +# 256x1-bit dual-port distributed RAM: 1 +# Registers : 3 +# 1-bit register : 1 +# 8-bit register : 2 +# Multiplexers : 1 +# 1-bit 4-to-1 multiplexer : 1 +# Adders/Subtractors : 2 +# 8-bit adder : 2 +# Comparators : 1 +# 8-bit comparator equal : 1 + +Cell Usage : +# BELS : 70 +# GND : 1 +# INV : 2 +# LUT1 : 4 +# LUT1_L : 10 +# LUT2 : 2 +# LUT3 : 4 +# LUT3_D : 1 +# LUT3_L : 2 +# LUT4 : 5 +# LUT4_L : 5 +# MUXCY : 18 +# MUXF5 : 1 +# VCC : 1 +# XORCY : 14 +# FlipFlops/Latches : 19 +# FDRE : 19 +# RAMS : 4 +# RAM64X1D : 4 +# Clock Buffers : 1 +# BUFGP : 1 +# IO Buffers : 7 +# IBUF : 5 +# OBUF : 2 +========================================================================= + +Device utilization summary: +--------------------------- + +Selected Device : 2v250cs144-6 + + Number of Slices: 42 out of 1536 2% + Number of Slice Flip Flops: 19 out of 3072 0% + Number of 4 input LUTs: 49 out of 3072 1% + Number of bonded IOBs: 8 out of 92 8% + Number of GCLKs: 1 out of 16 6% + + +========================================================================= +TIMING REPORT + +NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. + FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT + GENERATED AFTER PLACE-and-ROUTE. + +Clock Information: +------------------ +-----------------------------------+------------------------+-------+ +Clock Signal | Clock buffer(FF name) | Load | +-----------------------------------+------------------------+-------+ +CLOCK | BUFGP | 23 | +-----------------------------------+------------------------+-------+ + +Timing Summary: +--------------- +Speed Grade: -6 + + Minimum period: 5.493ns (Maximum Frequency: 182.050MHz) + Minimum input arrival time before clock: 3.689ns + Maximum output required time after clock: 9.654ns + Maximum combinational path delay: 6.977ns + +Timing Detail: +-------------- +All values displayed in nanoseconds (ns) + +========================================================================= +Timing constraint: Default period analysis for Clock 'CLOCK' + Clock period: 5.493ns (frequency: 182.050MHz) + Total number of paths / destination ports: 611 / 94 +------------------------------------------------------------------------- +Delay: 5.493ns (Levels of Logic = 7) + Source: STORAGE_READ_ADDRESS_1 (FF) + Destination: STORAGE_Mram_GET_OUTPUT_inst_ramx1d_1 (RAM) + Source Clock: CLOCK rising + Destination Clock: CLOCK rising + + Data Path: STORAGE_READ_ADDRESS_1 to STORAGE_Mram_GET_OUTPUT_inst_ramx1d_1 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDRE:C->Q 18 0.449 0.922 STORAGE_READ_ADDRESS_1 (STORAGE_READ_ADDRESS_1) + LUT4_L:I1->LO 1 0.347 0.000 STORAGE_Eq_stagelut (STORAGE_N4) + MUXCY:S->O 1 0.235 0.000 STORAGE_Eq_stagecy (STORAGE_Eq_stage_cyo) + MUXCY:CI->O 1 0.042 0.000 STORAGE_Eq_stagecy_rn_0 (STORAGE_Eq_stage_cyo1) + MUXCY:CI->O 1 0.042 0.000 STORAGE_Eq_stagecy_rn_1 (STORAGE_Eq_stage_cyo2) + MUXCY:CI->O 7 0.601 0.631 STORAGE_Eq_stagecy_rn_2 (FIFO_EMPTY) + LUT3_D:I2->O 13 0.347 0.733 FIFO_WRITE_ENABLE1 (FIFO_WRITE_ENABLE) + LUT3:I2->O 1 0.347 0.382 STORAGE_Mram_GET_OUTPUT_inst_lut2_41 (STORAGE_Mram_GET_OUTPUT_inst_lut2_4) + RAM64X1D:WE 0.416 STORAGE_Mram_GET_OUTPUT_inst_ramx1d_0 + ---------------------------------------- + Total 5.493ns (2.826ns logic, 2.667ns route) + (51.4% logic, 48.6% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'CLOCK' + Total number of paths / destination ports: 73 / 47 +------------------------------------------------------------------------- +Offset: 3.689ns (Levels of Logic = 3) + Source: BUFFER_CONTROL (PAD) + Destination: STORAGE_Mram_GET_OUTPUT_inst_ramx1d_1 (RAM) + Destination Clock: CLOCK rising + + Data Path: BUFFER_CONTROL to STORAGE_Mram_GET_OUTPUT_inst_ramx1d_1 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 6 0.653 0.811 BUFFER_CONTROL_IBUF (BUFFER_CONTROL_IBUF) + LUT3_D:I0->O 13 0.347 0.733 FIFO_WRITE_ENABLE1 (FIFO_WRITE_ENABLE) + LUT3:I2->O 1 0.347 0.382 STORAGE_Mram_GET_OUTPUT_inst_lut2_41 (STORAGE_Mram_GET_OUTPUT_inst_lut2_4) + RAM64X1D:WE 0.416 STORAGE_Mram_GET_OUTPUT_inst_ramx1d_0 + ---------------------------------------- + Total 3.689ns (1.763ns logic, 1.926ns route) + (47.8% logic, 52.2% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'CLOCK' + Total number of paths / destination ports: 96 / 2 +------------------------------------------------------------------------- +Offset: 9.654ns (Levels of Logic = 6) + Source: STORAGE_READ_ADDRESS_0 (FF) + Destination: DATA_OUT<0> (PAD) + Source Clock: CLOCK rising + + Data Path: STORAGE_READ_ADDRESS_0 to DATA_OUT<0> + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDRE:C->Q 18 0.449 0.757 STORAGE_READ_ADDRESS_0 (STORAGE_READ_ADDRESS_0) + RAM64X1D:DPRA0->DPO 1 1.236 0.548 STORAGE_Mram_GET_OUTPUT_inst_ramx1d_1 (STORAGE_Mram_GET_OUTPUT__net9) + LUT3_L:I1->LO 1 0.347 0.000 STORAGE_Mram_GET_OUTPUT_inst_mux_f5_1111_G (N48) + MUXF5:I1->O 2 0.345 0.744 STORAGE_Mram_GET_OUTPUT_inst_mux_f5_1111 (FIFO_DATA_OUT) + LUT4:I0->O 1 0.347 0.410 DATA_OUT19 (CHOICE40) + LUT4:I2->O 1 0.347 0.383 DATA_OUT44 (DATA_OUT) + OBUF:I->O 3.743 DATA_OUT_0_OBUF (DATA_OUT<0>) + ---------------------------------------- + Total 9.654ns (6.814ns logic, 2.840ns route) + (70.6% logic, 29.4% route) + +========================================================================= +Timing constraint: Default path analysis + Total number of paths / destination ports: 11 / 2 +------------------------------------------------------------------------- +Delay: 6.977ns (Levels of Logic = 4) + Source: DEMAND (PAD) + Destination: DATA_OUT<0> (PAD) + + Data Path: DEMAND to DATA_OUT<0> + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 2 0.653 0.744 DEMAND_IBUF (DEMAND_IBUF) + LUT4:I0->O 3 0.347 0.760 SENDING1 (SENDING_OBUF) + LUT4:I0->O 1 0.347 0.383 DATA_OUT44 (DATA_OUT) + OBUF:I->O 3.743 DATA_OUT_0_OBUF (DATA_OUT<0>) + ---------------------------------------- + Total 6.977ns (5.090ns logic, 1.887ns route) + (73.0% logic, 27.0% route) + +========================================================================= +CPU : 5.14 / 5.51 s | Elapsed : 5.00 / 6.00 s + +--> + +Total memory usage is 100604 kilobytes + +Number of errors : 0 ( 0 filtered) +Number of warnings : 0 ( 0 filtered) +Number of infos : 1 ( 0 filtered) +
trunk/docs/synthesis_reports/common/input_control.syr Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/docs/synthesis_reports/common/halving_manager.syr =================================================================== --- trunk/docs/synthesis_reports/common/halving_manager.syr (nonexistent) +++ trunk/docs/synthesis_reports/common/halving_manager.syr (revision 9) @@ -0,0 +1,486 @@ +Release 7.1.04i - xst H.42 +Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. +--> Parameter TMPDIR set to __projnav +CPU : 0.00 / 0.31 s | Elapsed : 0.00 / 0.00 s + +--> Parameter xsthdpdir set to ./xst +CPU : 0.00 / 0.31 s | Elapsed : 0.00 / 0.00 s + +--> Reading design: halving_manager.prj + +TABLE OF CONTENTS + 1) Synthesis Options Summary + 2) HDL Compilation + 3) HDL Analysis + 4) HDL Synthesis + 5) Advanced HDL Synthesis + 5.1) HDL Synthesis Report + 6) Low Level Synthesis + 7) Final Report + 7.1) Device utilization summary + 7.2) TIMING REPORT + + +========================================================================= +* Synthesis Options Summary * +========================================================================= +---- Source Parameters +Input File Name : "halving_manager.prj" +Input Format : mixed +Ignore Synthesis Constraint File : NO + +---- Target Parameters +Output File Name : "halving_manager" +Output Format : NGC +Target Device : xc2v250-6-cs144 + +---- Source Options +Top Module Name : halving_manager +Automatic FSM Extraction : YES +FSM Encoding Algorithm : Auto +FSM Style : lut +RAM Extraction : Yes +RAM Style : Auto +ROM Extraction : Yes +ROM Style : Auto +Mux Extraction : YES +Mux Style : Auto +Decoder Extraction : YES +Priority Encoder Extraction : YES +Shift Register Extraction : YES +Logical Shifter Extraction : YES +XOR Collapsing : YES +Resource Sharing : YES +Multiplier Style : auto +Automatic Register Balancing : No + +---- Target Options +Add IO Buffers : YES +Global Maximum Fanout : 500 +Add Generic Clock Buffer(BUFG) : 16 +Register Duplication : YES +Equivalent register Removal : YES +Slice Packing : YES +Pack IO Registers into IOBs : auto + +---- General Options +Optimization Goal : Speed +Optimization Effort : 1 +Keep Hierarchy : NO +Global Optimization : AllClockNets +RTL Output : Yes +Write Timing Constraints : NO +Hierarchy Separator : _ +Bus Delimiter : <> +Case Specifier : maintain +Slice Utilization Ratio : 100 +Slice Utilization Ratio Delta : 5 + +---- Other Options +lso : halving_manager.lso +Read Cores : YES +cross_clock_analysis : NO +verilog2001 : YES +safe_implementation : No +Optimize Instantiated Primitives : NO +tristate2logic : Yes +use_clock_enable : Yes +use_sync_set : Yes +use_sync_reset : Yes +enable_auto_floorplanning : No + +========================================================================= + + +========================================================================= +* HDL Compilation * +========================================================================= +Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd" in Library work. +Architecture rtl of Entity halving_manager is up to date. + +========================================================================= +* HDL Analysis * +========================================================================= +Analyzing Entity (Architecture ). +WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd" line 71: Index value(s) does not match array range, simulation mismatch. +WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd" line 71: Index value(s) does not match array range, simulation mismatch. +WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd" line 73: Index value(s) does not match array range, simulation mismatch. +WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd" line 108: Index value(s) does not match array range, simulation mismatch. +Entity analyzed. Unit generated. + + +========================================================================= +* HDL Synthesis * +========================================================================= + +Synthesizing Unit . + Related source file is "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd". + Found 3-bit 46-to-1 multiplexer for signal <$n0002> created at line 108. + Found 3-bit 4-to-1 multiplexer for signal <$n0050>. + Found 3-bit 4-to-1 multiplexer for signal <$n0051>. + Found 3-bit 4-to-1 multiplexer for signal <$n0052>. + Found 3-bit 4-to-1 multiplexer for signal <$n0053>. + Found 3-bit 4-to-1 multiplexer for signal <$n0054>. + Found 3-bit 4-to-1 multiplexer for signal <$n0055>. + Found 3-bit 4-to-1 multiplexer for signal <$n0056>. + Found 3-bit 4-to-1 multiplexer for signal <$n0057>. + Found 3-bit 4-to-1 multiplexer for signal <$n0058>. + Found 3-bit 4-to-1 multiplexer for signal <$n0059>. + Found 3-bit 4-to-1 multiplexer for signal <$n0060>. + Found 3-bit 4-to-1 multiplexer for signal <$n0061>. + Found 3-bit 4-to-1 multiplexer for signal <$n0062>. + Found 3-bit 4-to-1 multiplexer for signal <$n0063>. + Found 3-bit 4-to-1 multiplexer for signal <$n0064>. + Found 3-bit 4-to-1 multiplexer for signal <$n0065>. + Found 3-bit 4-to-1 multiplexer for signal <$n0066>. + Found 3-bit 4-to-1 multiplexer for signal <$n0067>. + Found 3-bit 4-to-1 multiplexer for signal <$n0068>. + Found 3-bit 4-to-1 multiplexer for signal <$n0069>. + Found 3-bit 4-to-1 multiplexer for signal <$n0070>. + Found 3-bit 4-to-1 multiplexer for signal <$n0071>. + Found 3-bit 4-to-1 multiplexer for signal <$n0072>. + Found 3-bit 4-to-1 multiplexer for signal <$n0073>. + Found 3-bit 4-to-1 multiplexer for signal <$n0074>. + Found 3-bit 4-to-1 multiplexer for signal <$n0075>. + Found 3-bit 4-to-1 multiplexer for signal <$n0076>. + Found 3-bit 4-to-1 multiplexer for signal <$n0077>. + Found 3-bit 4-to-1 multiplexer for signal <$n0078>. + Found 3-bit 4-to-1 multiplexer for signal <$n0079>. + Found 3-bit 4-to-1 multiplexer for signal <$n0080>. + Found 3-bit 4-to-1 multiplexer for signal <$n0081>. + Found 3-bit 4-to-1 multiplexer for signal <$n0082>. + Found 3-bit 4-to-1 multiplexer for signal <$n0084>. + Found 3-bit 4-to-1 multiplexer for signal <$n0085>. + Found 3-bit 4-to-1 multiplexer for signal <$n0087>. + Found 3-bit 4-to-1 multiplexer for signal <$n0088>. + Found 3-bit 4-to-1 multiplexer for signal <$n0089>. + Found 3-bit 4-to-1 multiplexer for signal <$n0090>. + Found 3-bit 4-to-1 multiplexer for signal <$n0091>. + Found 3-bit 4-to-1 multiplexer for signal <$n0092>. + Found 3-bit 4-to-1 multiplexer for signal <$n0093>. + Found 3-bit 4-to-1 multiplexer for signal <$n0094>. + Found 3-bit 4-to-1 multiplexer for signal <$n0095>. + Found 3-bit 4-to-1 multiplexer for signal <$n0096>. + Found 3-bit 4-to-1 multiplexer for signal <$n0097>. + Found 3-bit addsub for signal <$n0098>. + Found 3-bit addsub for signal <$n0100>. + Found 3-bit addsub for signal <$n0101>. + Found 3-bit addsub for signal <$n0102>. + Found 3-bit addsub for signal <$n0103>. + Found 3-bit addsub for signal <$n0104>. + Found 3-bit addsub for signal <$n0105>. + Found 3-bit addsub for signal <$n0106>. + Found 3-bit addsub for signal <$n0107>. + Found 3-bit addsub for signal <$n0108>. + Found 3-bit addsub for signal <$n0109>. + Found 3-bit addsub for signal <$n0110>. + Found 3-bit addsub for signal <$n0111>. + Found 3-bit addsub for signal <$n0112>. + Found 3-bit addsub for signal <$n0113>. + Found 3-bit addsub for signal <$n0114>. + Found 3-bit addsub for signal <$n0115>. + Found 3-bit addsub for signal <$n0116>. + Found 3-bit addsub for signal <$n0117>. + Found 3-bit addsub for signal <$n0118>. + Found 3-bit addsub for signal <$n0119>. + Found 3-bit addsub for signal <$n0120>. + Found 3-bit addsub for signal <$n0121>. + Found 3-bit addsub for signal <$n0122>. + Found 3-bit addsub for signal <$n0123>. + Found 3-bit addsub for signal <$n0124>. + Found 3-bit addsub for signal <$n0125>. + Found 3-bit addsub for signal <$n0126>. + Found 3-bit addsub for signal <$n0127>. + Found 3-bit addsub for signal <$n0128>. + Found 3-bit addsub for signal <$n0129>. + Found 3-bit addsub for signal <$n0130>. + Found 3-bit addsub for signal <$n0131>. + Found 3-bit addsub for signal <$n0132>. + Found 3-bit addsub for signal <$n0133>. + Found 3-bit addsub for signal <$n0134>. + Found 3-bit addsub for signal <$n0135>. + Found 3-bit addsub for signal <$n0136>. + Found 3-bit addsub for signal <$n0137>. + Found 3-bit addsub for signal <$n0138>. + Found 3-bit addsub for signal <$n0139>. + Found 3-bit addsub for signal <$n0140>. + Found 3-bit addsub for signal <$n0141>. + Found 3-bit addsub for signal <$n0142>. + Found 3-bit addsub for signal <$n0143>. + Found 3-bit addsub for signal <$n0144>. + Found 10-bit comparator greater for signal <$n0147> created at line 99. + Found 3-bit comparator greater for signal <$n0241> created at line 108. + Found 1-bit register for signal . + Found 10-bit register for signal . + Found 10-bit adder for signal . + Found 10-bit register for signal . + Found 10-bit adder for signal . + Found 138-bit register for signal . + Summary: + inferred 139 D-type flip-flop(s). + inferred 48 Adder/Subtractor(s). + inferred 2 Comparator(s). + inferred 141 Multiplexer(s). +Unit synthesized. + +INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing. + +========================================================================= +* Advanced HDL Synthesis * +========================================================================= + +Advanced RAM inference ... +Advanced multiplier inference ... +Advanced Registered AddSub inference ... +Dynamic shift register inference ... + +========================================================================= +HDL Synthesis Report + +Macro Statistics +# Adders/Subtractors : 48 + 10-bit adder : 2 + 3-bit addsub : 46 +# Registers : 49 + 1-bit register : 1 + 10-bit register : 2 + 3-bit register : 46 +# Comparators : 2 + 10-bit comparator greater : 1 + 3-bit comparator greater : 1 +# Multiplexers : 47 + 3-bit 4-to-1 multiplexer : 46 + 3-bit 46-to-1 multiplexer : 1 + +========================================================================= + +========================================================================= +* Low Level Synthesis * +========================================================================= + +Optimizing unit ... +Loading device for application Rf_Device from file '2v250.nph' in environment C:/Xilinx. + +Mapping all equations... +Building and optimizing final netlist ... +Found area constraint ratio of 100 (+ 5) on block halving_manager, actual ratio is 16. + +========================================================================= +* Final Report * +========================================================================= +Final Results +RTL Top Level Output File Name : halving_manager.ngr +Top Level Output File Name : halving_manager +Output Format : NGC +Optimization Goal : Speed +Keep Hierarchy : NO + +Design Statistics +# IOs : 51 + +Macro Statistics : +# Registers : 67 +# 1-bit register : 21 +# 3-bit register : 46 +# Multiplexers : 47 +# 3-bit 4-to-1 multiplexer : 46 +# 3-bit 46-to-1 multiplexer : 1 +# Adders/Subtractors : 2 +# 10-bit adder : 2 +# Comparators : 2 +# 10-bit comparator greater : 1 +# 3-bit comparator greater : 1 +# Xors : 92 +# 1-bit xor3 : 92 + +Cell Usage : +# BELS : 570 +# GND : 1 +# INV : 1 +# LUT1 : 15 +# LUT2 : 9 +# LUT3 : 70 +# LUT3_L : 132 +# LUT4 : 118 +# LUT4_D : 18 +# LUT4_L : 112 +# MUXCY : 18 +# MUXF5 : 35 +# MUXF6 : 15 +# MUXF7 : 6 +# MUXF8 : 3 +# VCC : 1 +# XORCY : 16 +# FlipFlops/Latches : 159 +# FDR : 1 +# FDRE : 156 +# FDSE : 2 +# Clock Buffers : 1 +# BUFGP : 1 +# IO Buffers : 50 +# IBUF : 29 +# OBUF : 21 +========================================================================= + +Device utilization summary: +--------------------------- + +Selected Device : 2v250cs144-6 + + Number of Slices: 263 out of 1536 17% + Number of Slice Flip Flops: 159 out of 3072 5% + Number of 4 input LUTs: 474 out of 3072 15% + Number of bonded IOBs: 51 out of 92 55% + Number of GCLKs: 1 out of 16 6% + + +========================================================================= +TIMING REPORT + +NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. + FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT + GENERATED AFTER PLACE-and-ROUTE. + +Clock Information: +------------------ +-----------------------------------+------------------------+-------+ +Clock Signal | Clock buffer(FF name) | Load | +-----------------------------------+------------------------+-------+ +CLOCK | BUFGP | 159 | +-----------------------------------+------------------------+-------+ + +Timing Summary: +--------------- +Speed Grade: -6 + + Minimum period: 6.759ns (Maximum Frequency: 147.951MHz) + Minimum input arrival time before clock: 7.315ns + Maximum output required time after clock: 11.278ns + Maximum combinational path delay: 11.850ns + +Timing Detail: +-------------- +All values displayed in nanoseconds (ns) + +========================================================================= +Timing constraint: Default period analysis for Clock 'CLOCK' + Clock period: 6.759ns (frequency: 147.951MHz) + Total number of paths / destination ports: 44219 / 316 +------------------------------------------------------------------------- +Delay: 6.759ns (Levels of Logic = 8) + Source: SHIFTS_0_1 (FF) + Destination: SHIFTS_8_2 (FF) + Source Clock: CLOCK rising + Destination Clock: CLOCK rising + + Data Path: SHIFTS_0_1 to SHIFTS_8_2 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDRE:C->Q 4 0.449 0.718 SHIFTS_0_1 (SHIFTS_0_1) + LUT3_L:I1->LO 1 0.347 0.000 CONTEXT<4>31 (MUX_BLOCK_N38) + MUXF5:I0->O 1 0.345 0.000 CONTEXT<1>_rn_14 (MUX_BLOCK_CONTEXT<1>_MUXF515) + MUXF6:I0->O 1 0.354 0.000 CONTEXT<0>_rn_9 (MUX_BLOCK_CONTEXT<0>_MUXF67) + MUXF7:I0->O 2 0.354 0.743 CONTEXT<2>_rn_3 (MUX_BLOCK_CONTEXT<2>_MUXF73) + LUT4_L:I0->LO 1 0.347 0.000 _n0241106_1_F (N760) + MUXF5:I0->O 4 0.345 0.579 _n0241106_1 (_n0241106) + LUT4_D:I2->O 15 0.347 0.758 Ker601 (N60) + LUT4:I2->O 3 0.347 0.535 _n0484 (_n0484) + FDRE:CE 0.190 SHIFTS_20_0 + ---------------------------------------- + Total 6.759ns (3.425ns logic, 3.334ns route) + (50.7% logic, 49.3% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'CLOCK' + Total number of paths / destination ports: 39794 / 476 +------------------------------------------------------------------------- +Offset: 7.315ns (Levels of Logic = 9) + Source: CONTEXT<4> (PAD) + Destination: SHIFTS_8_2 (FF) + Destination Clock: CLOCK rising + + Data Path: CONTEXT<4> to SHIFTS_8_2 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 53 0.653 1.069 CONTEXT_4_IBUF (CONTEXT_4_IBUF) + LUT3_L:I0->LO 1 0.347 0.000 CONTEXT<4>19 (MUX_BLOCK_N26) + MUXF5:I0->O 1 0.345 0.000 CONTEXT<1>_rn_8 (MUX_BLOCK_CONTEXT<1>_MUXF59) + MUXF6:I0->O 1 0.354 0.000 CONTEXT<0>_rn_6 (MUX_BLOCK_CONTEXT<0>_MUXF64) + MUXF7:I1->O 2 0.354 0.743 CONTEXT<2>_rn_2 (MUX_BLOCK_CONTEXT<2>_MUXF72) + LUT4_L:I0->LO 1 0.347 0.000 _n0241106_1_G (N761) + MUXF5:I1->O 4 0.345 0.579 _n0241106_1 (_n0241106) + LUT4_D:I2->O 15 0.347 0.758 Ker601 (N60) + LUT4:I2->O 3 0.347 0.535 _n0484 (_n0484) + FDRE:CE 0.190 SHIFTS_20_0 + ---------------------------------------- + Total 7.315ns (3.629ns logic, 3.686ns route) + (49.6% logic, 50.4% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'CLOCK' + Total number of paths / destination ports: 3148 / 21 +------------------------------------------------------------------------- +Offset: 11.278ns (Levels of Logic = 10) + Source: SHIFTS_0_2 (FF) + Destination: DENOMINATOR_OUT<9> (PAD) + Source Clock: CLOCK rising + + Data Path: SHIFTS_0_2 to DENOMINATOR_OUT<9> + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDRE:C->Q 3 0.449 0.700 SHIFTS_0_2 (SHIFTS_0_2) + LUT3_L:I1->LO 1 0.347 0.000 CONTEXT<4>47 (MUX_BLOCK_N60) + MUXF5:I0->O 1 0.345 0.000 CONTEXT<1>_rn_22 (MUX_BLOCK_CONTEXT<1>_MUXF523) + MUXF6:I0->O 1 0.354 0.000 CONTEXT<0>_rn_16 (MUX_BLOCK_CONTEXT<0>_MUXF611) + MUXF7:I0->O 2 0.354 0.000 CONTEXT<2>_rn_6 (MUX_BLOCK_CONTEXT<2>_MUXF75) + MUXF8:I0->O 1 0.354 0.547 CONTEXT<3>_rn_1 (MUX_BLOCK_CONTEXT<3>_MUXF82) + LUT4:I1->O 16 0.347 0.905 _n0241106 (CHOICE33) + LUT4:I1->O 1 0.347 0.415 _n0145_SW1 (N718) + LUT4:I3->O 20 0.347 0.994 _n0145 (_n0145) + LUT3:I0->O 1 0.347 0.383 NUMERATOR_OUT<0>1 (NUMERATOR_OUT_0_OBUF) + OBUF:I->O 3.743 NUMERATOR_OUT_0_OBUF (NUMERATOR_OUT<0>) + ---------------------------------------- + Total 11.278ns (7.334ns logic, 3.944ns route) + (65.0% logic, 35.0% route) + +========================================================================= +Timing constraint: Default path analysis + Total number of paths / destination ports: 2813 / 21 +------------------------------------------------------------------------- +Delay: 11.850ns (Levels of Logic = 11) + Source: CONTEXT<4> (PAD) + Destination: DENOMINATOR_OUT<9> (PAD) + + Data Path: CONTEXT<4> to DENOMINATOR_OUT<9> + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 53 0.653 1.069 CONTEXT_4_IBUF (CONTEXT_4_IBUF) + LUT3_L:I0->LO 1 0.347 0.000 CONTEXT<4>35 (MUX_BLOCK_N48) + MUXF5:I0->O 1 0.345 0.000 CONTEXT<1>_rn_16 (MUX_BLOCK_CONTEXT<1>_MUXF517) + MUXF6:I0->O 1 0.354 0.000 CONTEXT<0>_rn_13 (MUX_BLOCK_CONTEXT<0>_MUXF68) + MUXF7:I1->O 2 0.354 0.000 CONTEXT<2>_rn_5 (MUX_BLOCK_CONTEXT<2>_MUXF74) + MUXF8:I1->O 1 0.354 0.547 CONTEXT<3>_rn_1 (MUX_BLOCK_CONTEXT<3>_MUXF82) + LUT4:I1->O 16 0.347 0.905 _n0241106 (CHOICE33) + LUT4:I1->O 1 0.347 0.415 _n0145_SW1 (N718) + LUT4:I3->O 20 0.347 0.994 _n0145 (_n0145) + LUT3:I0->O 1 0.347 0.383 NUMERATOR_OUT<0>1 (NUMERATOR_OUT_0_OBUF) + OBUF:I->O 3.743 NUMERATOR_OUT_0_OBUF (NUMERATOR_OUT<0>) + ---------------------------------------- + Total 11.850ns (7.538ns logic, 4.312ns route) + (63.6% logic, 36.4% route) + +========================================================================= +CPU : 13.28 / 13.63 s | Elapsed : 14.00 / 14.00 s + +--> + +Total memory usage is 103676 kilobytes + +Number of errors : 0 ( 0 filtered) +Number of warnings : 4 ( 0 filtered) +Number of infos : 1 ( 0 filtered) +
trunk/docs/synthesis_reports/common/halving_manager.syr Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/docs/synthesis_reports/expgolomb/exp_golomb_counter.syr =================================================================== --- trunk/docs/synthesis_reports/expgolomb/exp_golomb_counter.syr (nonexistent) +++ trunk/docs/synthesis_reports/expgolomb/exp_golomb_counter.syr (revision 9) @@ -0,0 +1,361 @@ +Release 7.1.04i - xst H.42 +Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. +--> Parameter TMPDIR set to __projnav +CPU : 0.00 / 2.44 s | Elapsed : 0.00 / 2.00 s + +--> Parameter xsthdpdir set to ./xst +CPU : 0.00 / 2.44 s | Elapsed : 0.00 / 2.00 s + +--> Reading design: exp_golomb_counter.prj + +TABLE OF CONTENTS + 1) Synthesis Options Summary + 2) HDL Compilation + 3) HDL Analysis + 4) HDL Synthesis + 5) Advanced HDL Synthesis + 5.1) HDL Synthesis Report + 6) Low Level Synthesis + 7) Final Report + 7.1) Device utilization summary + 7.2) TIMING REPORT + + +========================================================================= +* Synthesis Options Summary * +========================================================================= +---- Source Parameters +Input File Name : "exp_golomb_counter.prj" +Input Format : mixed +Ignore Synthesis Constraint File : NO + +---- Target Parameters +Output File Name : "exp_golomb_counter" +Output Format : NGC +Target Device : xc2v2000-6-bg575 + +---- Source Options +Top Module Name : exp_golomb_counter +Automatic FSM Extraction : YES +FSM Encoding Algorithm : Auto +FSM Style : lut +RAM Extraction : Yes +RAM Style : Auto +ROM Extraction : Yes +ROM Style : Auto +Mux Extraction : YES +Mux Style : Auto +Decoder Extraction : YES +Priority Encoder Extraction : YES +Shift Register Extraction : YES +Logical Shifter Extraction : YES +XOR Collapsing : YES +Resource Sharing : YES +Multiplier Style : auto +Automatic Register Balancing : No + +---- Target Options +Add IO Buffers : YES +Global Maximum Fanout : 500 +Add Generic Clock Buffer(BUFG) : 16 +Register Duplication : YES +Equivalent register Removal : YES +Slice Packing : YES +Pack IO Registers into IOBs : auto + +---- General Options +Optimization Goal : Speed +Optimization Effort : 1 +Keep Hierarchy : NO +Global Optimization : AllClockNets +RTL Output : Yes +Write Timing Constraints : NO +Hierarchy Separator : / +Bus Delimiter : <> +Case Specifier : maintain +Slice Utilization Ratio : 100 +Slice Utilization Ratio Delta : 5 + +---- Other Options +lso : exp_golomb_counter.lso +Read Cores : YES +cross_clock_analysis : NO +verilog2001 : YES +safe_implementation : No +Optimize Instantiated Primitives : NO +tristate2logic : Yes +use_clock_enable : Yes +use_sync_set : Yes +use_sync_reset : Yes +enable_auto_floorplanning : No + +========================================================================= + + +========================================================================= +* HDL Compilation * +========================================================================= +Compiling vhdl file "C:/Xilinx/bin/exp_golomb_counter/EXP_GOLOMB_COUNTER.vhd" in Library work. +Architecture rtl of Entity exp_golomb_counter is up to date. + +========================================================================= +* HDL Analysis * +========================================================================= +Analyzing Entity (Architecture ). +WARNING:Xst:790 - "C:/Xilinx/bin/exp_golomb_counter/EXP_GOLOMB_COUNTER.vhd" line 155: Index value(s) does not match array range, simulation mismatch. +Entity analyzed. Unit generated. + + +========================================================================= +* HDL Synthesis * +========================================================================= + +Synthesizing Unit . + Related source file is "C:/Xilinx/bin/exp_golomb_counter/EXP_GOLOMB_COUNTER.vhd". + Found 1-bit register for signal . + Found 1-bit 33-to-1 multiplexer for signal <$n0035> created at line 155. + Found 1-bit 4-to-1 multiplexer for signal <$n0036>. + Found 6-bit comparator equal for signal <$n0042> created at line 146. + Found 6-bit comparator not equal for signal <$n0043> created at line 146. + Found 33-bit adder for signal . + Found 6-bit register for signal . + Found 6-bit updown counter for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 1 Counter(s). + inferred 3 D-type flip-flop(s). + inferred 1 Adder/Subtractor(s). + inferred 2 Comparator(s). + inferred 2 Multiplexer(s). +Unit synthesized. + + +========================================================================= +* Advanced HDL Synthesis * +========================================================================= + +Advanced RAM inference ... +Advanced multiplier inference ... +Advanced Registered AddSub inference ... +Dynamic shift register inference ... + +========================================================================= +HDL Synthesis Report + +Macro Statistics +# Adders/Subtractors : 1 + 33-bit adder : 1 +# Counters : 1 + 6-bit updown counter : 1 +# Registers : 4 + 1-bit register : 3 + 6-bit register : 1 +# Comparators : 2 + 6-bit comparator equal : 1 + 6-bit comparator not equal : 1 +# Multiplexers : 2 + 1-bit 33-to-1 multiplexer : 1 + 1-bit 4-to-1 multiplexer : 1 + +========================================================================= + +========================================================================= +* Low Level Synthesis * +========================================================================= +WARNING:Xst:1988 - Unit : instances , of unit and unit are dual, second instance is removed + +Optimizing unit ... +Loading device for application Rf_Device from file '2v2000.nph' in environment C:/Xilinx. + +Mapping all equations... +Building and optimizing final netlist ... +Found area constraint ratio of 100 (+ 5) on block exp_golomb_counter, actual ratio is 0. +FlipFlop OUTPUT_ACTIVE has been replicated 1 time(s) to handle iob=true attribute. + +========================================================================= +* Final Report * +========================================================================= +Final Results +RTL Top Level Output File Name : exp_golomb_counter.ngr +Top Level Output File Name : exp_golomb_counter +Output Format : NGC +Optimization Goal : Speed +Keep Hierarchy : NO + +Design Statistics +# IOs : 37 + +Macro Statistics : +# Registers : 10 +# 1-bit register : 9 +# 6-bit register : 1 +# Multiplexers : 2 +# 1-bit 33-to-1 multiplexer : 1 +# 1-bit 4-to-1 multiplexer : 1 +# Adders/Subtractors : 2 +# 33-bit adder : 1 +# 6-bit addsub : 1 +# Comparators : 2 +# 6-bit comparator equal : 1 +# 6-bit comparator not equal : 1 + +Cell Usage : +# BELS : 196 +# GND : 1 +# INV : 1 +# LUT1 : 31 +# LUT2 : 4 +# LUT2_L : 5 +# LUT3 : 7 +# LUT3_L : 16 +# LUT4 : 31 +# LUT4_L : 6 +# MUXCY : 40 +# MUXF5 : 9 +# MUXF6 : 4 +# MUXF7 : 2 +# MUXF8 : 1 +# VCC : 1 +# XORCY : 37 +# FlipFlops/Latches : 16 +# FDRE : 8 +# FDRS : 5 +# FDRSE : 2 +# FDS : 1 +# Clock Buffers : 1 +# BUFGP : 1 +# IO Buffers : 36 +# IBUF : 34 +# OBUF : 2 +========================================================================= + +Device utilization summary: +--------------------------- + +Selected Device : 2v2000bg575-6 + + Number of Slices: 54 out of 10752 0% + Number of Slice Flip Flops: 16 out of 21504 0% + Number of 4 input LUTs: 100 out of 21504 0% + Number of bonded IOBs: 37 out of 408 9% + Number of GCLKs: 1 out of 16 6% + + +========================================================================= +TIMING REPORT + +NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. + FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT + GENERATED AFTER PLACE-and-ROUTE. + +Clock Information: +------------------ +-----------------------------------+------------------------+-------+ +Clock Signal | Clock buffer(FF name) | Load | +-----------------------------------+------------------------+-------+ +CLOCK | BUFGP | 16 | +-----------------------------------+------------------------+-------+ + +Timing Summary: +--------------- +Speed Grade: -6 + + Minimum period: 4.224ns (Maximum Frequency: 236.770MHz) + Minimum input arrival time before clock: 11.608ns + Maximum output required time after clock: 4.575ns + Maximum combinational path delay: No path found + +Timing Detail: +-------------- +All values displayed in nanoseconds (ns) + +========================================================================= +Timing constraint: Default period analysis for Clock 'CLOCK' + Clock period: 4.224ns (frequency: 236.770MHz) + Total number of paths / destination ports: 233 / 17 +------------------------------------------------------------------------- +Delay: 4.224ns (Levels of Logic = 6) + Source: OUT_ADDRESS_0 (FF) + Destination: DATA_OUT (FF) + Source Clock: CLOCK rising + Destination Clock: CLOCK rising + + Data Path: OUT_ADDRESS_0 to DATA_OUT + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDRE:C->Q 19 0.449 0.792 OUT_ADDRESS_0 (OUT_ADDRESS_0) + LUT3_L:I2->LO 1 0.347 0.000 OUT_ADDRESS<0>13 (MUX_BLOCK_N13) + MUXF5:I0->O 1 0.345 0.000 OUT_ADDRESS<1>_rn_5 (MUX_BLOCK_OUT_ADDRESS<1>_MUXF56) + MUXF6:I1->O 1 0.354 0.000 OUT_ADDRESS<2>_rn_2 (MUX_BLOCK_OUT_ADDRESS<2>_MUXF63) + MUXF7:I0->O 1 0.354 0.000 OUT_ADDRESS<3>_rn_0 (MUX_BLOCK_OUT_ADDRESS<3>_MUXF71) + MUXF8:I0->O 1 0.354 0.382 OUT_ADDRESS<4> (MUX_BLOCK_OUT_ADDRESS<4>_MUXF8) + MUXF5:S->O 1 0.553 0.000 _n0058<2>1111 (_n0036) + FDRE:D 0.293 DATA_OUT + ---------------------------------------- + Total 4.224ns (3.049ns logic, 1.174ns route) + (72.2% logic, 27.8% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'CLOCK' + Total number of paths / destination ports: 3250 / 29 +------------------------------------------------------------------------- +Offset: 11.608ns (Levels of Logic = 14) + Source: DATA_IN<1> (PAD) + Destination: LOG_0 (FF) + Destination Clock: CLOCK rising + + Data Path: DATA_IN<1> to LOG_0 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 1 0.653 0.608 DATA_IN_1_IBUF (DATA_IN_1_IBUF) + LUT1:I0->O 1 0.347 0.000 DATA_IN_1_IBUF_rt (DATA_IN_1_IBUF_rt) + MUXCY:S->O 1 0.235 0.000 exp_golomb_counter_DATA2<1>cy (exp_golomb_counter_DATA2<1>_cyo) + XORCY:CI->O 3 0.824 0.701 exp_golomb_counter_DATA2<2>_xor (DATA2<2>) + LUT4:I1->O 1 0.347 0.410 _n0037<0>24 (CHOICE501) + LUT4:I2->O 1 0.347 0.608 _n0037<0>42 (CHOICE504) + LUT4:I0->O 1 0.347 0.410 _n0037<0>75 (CHOICE507) + LUT4:I2->O 1 0.347 0.608 _n0037<0>120 (CHOICE510) + LUT4:I0->O 1 0.347 0.410 _n0037<0>170 (CHOICE513) + LUT4:I2->O 1 0.347 0.608 _n0037<0>219 (CHOICE516) + LUT4:I0->O 1 0.347 0.410 _n0037<0>269 (CHOICE519) + LUT4:I2->O 1 0.347 0.607 _n0037<0>318 (CHOICE522) + LUT4:I0->O 1 0.347 0.410 _n0037<0>368 (CHOICE525) + LUT3:I2->O 1 0.347 0.000 _n0037<0>4171 (N375) + FDRS:D 0.293 LOG_0 + ---------------------------------------- + Total 11.608ns (5.822ns logic, 5.786ns route) + (50.2% logic, 49.8% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'CLOCK' + Total number of paths / destination ports: 2 / 2 +------------------------------------------------------------------------- +Offset: 4.575ns (Levels of Logic = 1) + Source: DATA_OUT (FF) + Destination: DATA_OUT (PAD) + Source Clock: CLOCK rising + + Data Path: DATA_OUT to DATA_OUT + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDRE:C->Q 1 0.449 0.383 DATA_OUT (DATA_OUT_OBUF) + OBUF:I->O 3.743 DATA_OUT_OBUF (DATA_OUT) + ---------------------------------------- + Total 4.575ns (4.192ns logic, 0.383ns route) + (91.6% logic, 8.4% route) + +========================================================================= +CPU : 7.20 / 9.72 s | Elapsed : 7.00 / 9.00 s + +--> + +Total memory usage is 121148 kilobytes + +Number of errors : 0 ( 0 filtered) +Number of warnings : 2 ( 0 filtered) +Number of infos : 0 ( 0 filtered) +
trunk/docs/synthesis_reports/expgolomb/exp_golomb_counter.syr Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/docs/synthesis_reports/expgolomb/exp_golomb_decoder.syr =================================================================== --- trunk/docs/synthesis_reports/expgolomb/exp_golomb_decoder.syr (nonexistent) +++ trunk/docs/synthesis_reports/expgolomb/exp_golomb_decoder.syr (revision 9) @@ -0,0 +1,390 @@ +Release 7.1.04i - xst H.42 +Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. +--> Parameter TMPDIR set to __projnav +CPU : 0.00 / 0.34 s | Elapsed : 0.00 / 0.00 s + +--> Parameter xsthdpdir set to ./xst +CPU : 0.00 / 0.34 s | Elapsed : 0.00 / 0.00 s + +--> Reading design: exp_golomb_decoder.prj + +TABLE OF CONTENTS + 1) Synthesis Options Summary + 2) HDL Compilation + 3) HDL Analysis + 4) HDL Synthesis + 5) Advanced HDL Synthesis + 5.1) HDL Synthesis Report + 6) Low Level Synthesis + 7) Final Report + 7.1) Device utilization summary + 7.2) TIMING REPORT + + +========================================================================= +* Synthesis Options Summary * +========================================================================= +---- Source Parameters +Input File Name : "exp_golomb_decoder.prj" +Input Format : mixed +Ignore Synthesis Constraint File : NO + +---- Target Parameters +Output File Name : "exp_golomb_decoder" +Output Format : NGC +Target Device : xc2v2000-6-bg575 + +---- Source Options +Top Module Name : exp_golomb_decoder +Automatic FSM Extraction : YES +FSM Encoding Algorithm : Auto +FSM Style : lut +RAM Extraction : Yes +RAM Style : Auto +ROM Extraction : Yes +ROM Style : Auto +Mux Extraction : YES +Mux Style : Auto +Decoder Extraction : YES +Priority Encoder Extraction : YES +Shift Register Extraction : YES +Logical Shifter Extraction : YES +XOR Collapsing : YES +Resource Sharing : YES +Multiplier Style : auto +Automatic Register Balancing : No + +---- Target Options +Add IO Buffers : YES +Global Maximum Fanout : 500 +Add Generic Clock Buffer(BUFG) : 16 +Register Duplication : YES +Equivalent register Removal : YES +Slice Packing : YES +Pack IO Registers into IOBs : auto + +---- General Options +Optimization Goal : Speed +Optimization Effort : 1 +Keep Hierarchy : NO +Global Optimization : AllClockNets +RTL Output : Yes +Write Timing Constraints : NO +Hierarchy Separator : / +Bus Delimiter : <> +Case Specifier : maintain +Slice Utilization Ratio : 100 +Slice Utilization Ratio Delta : 5 + +---- Other Options +lso : exp_golomb_decoder.lso +Read Cores : YES +cross_clock_analysis : NO +verilog2001 : YES +safe_implementation : No +Optimize Instantiated Primitives : NO +tristate2logic : Yes +use_clock_enable : Yes +use_sync_set : Yes +use_sync_reset : Yes +enable_auto_floorplanning : No + +========================================================================= + + +========================================================================= +* HDL Compilation * +========================================================================= +Compiling vhdl file "C:/Xilinx/bin/exp-golomb-decoder/EXP_GOLOMB_DECODER.vhd" in Library work. +Entity compiled. +Entity (Architecture ) compiled. + +========================================================================= +* HDL Analysis * +========================================================================= +Analyzing Entity (Architecture ). +Entity analyzed. Unit generated. + + +========================================================================= +* HDL Synthesis * +========================================================================= + +Synthesizing Unit . + Related source file is "C:/Xilinx/bin/exp-golomb-decoder/EXP_GOLOMB_DECODER.vhd". + Found 5-bit comparator equal for signal <$n0005> created at line 83. + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 5-bit up counter for signal . + Found 5-bit up counter for signal . + Found 32-bit adder for signal . + Summary: + inferred 2 Counter(s). + inferred 97 D-type flip-flop(s). + inferred 1 Adder/Subtractor(s). + inferred 1 Comparator(s). +Unit synthesized. + + +========================================================================= +* Advanced HDL Synthesis * +========================================================================= + +Advanced RAM inference ... +Advanced multiplier inference ... +Advanced Registered AddSub inference ... +Dynamic shift register inference ... + +========================================================================= +HDL Synthesis Report + +Macro Statistics +# Adders/Subtractors : 1 + 32-bit adder : 1 +# Counters : 2 + 5-bit up counter : 2 +# Registers : 66 + 1-bit register : 65 + 32-bit register : 1 +# Comparators : 1 + 5-bit comparator equal : 1 + +========================================================================= + +========================================================================= +* Low Level Synthesis * +========================================================================= + +Optimizing unit ... +Loading device for application Rf_Device from file '2v2000.nph' in environment C:/Xilinx. + +Mapping all equations... +Building and optimizing final netlist ... +Found area constraint ratio of 100 (+ 5) on block exp_golomb_decoder, actual ratio is 0. + +========================================================================= +* Final Report * +========================================================================= +Final Results +RTL Top Level Output File Name : exp_golomb_decoder.ngr +Top Level Output File Name : exp_golomb_decoder +Output Format : NGC +Optimization Goal : Speed +Keep Hierarchy : NO + +Design Statistics +# IOs : 37 + +Macro Statistics : +# Registers : 68 +# 1-bit register : 65 +# 32-bit register : 1 +# 5-bit register : 2 +# Adders/Subtractors : 1 +# 32-bit adder : 1 +# Comparators : 1 +# 5-bit comparator equal : 1 + +Cell Usage : +# BELS : 159 +# GND : 1 +# INV : 2 +# LUT2 : 4 +# LUT2_L : 33 +# LUT3 : 40 +# LUT3_D : 1 +# LUT4 : 11 +# LUT4_D : 2 +# LUT4_L : 2 +# MUXCY : 31 +# VCC : 1 +# XORCY : 31 +# FlipFlops/Latches : 107 +# FDRE : 107 +# Clock Buffers : 1 +# BUFGP : 1 +# IO Buffers : 36 +# IBUF : 3 +# OBUF : 33 +========================================================================= + +Device utilization summary: +--------------------------- + +Selected Device : 2v2000bg575-6 + + Number of Slices: 64 out of 10752 0% + Number of Slice Flip Flops: 107 out of 21504 0% + Number of 4 input LUTs: 93 out of 21504 0% + Number of bonded IOBs: 37 out of 408 9% + Number of GCLKs: 1 out of 16 6% + + +========================================================================= +TIMING REPORT + +NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. + FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT + GENERATED AFTER PLACE-and-ROUTE. + +Clock Information: +------------------ +-----------------------------------+------------------------+-------+ +Clock Signal | Clock buffer(FF name) | Load | +-----------------------------------+------------------------+-------+ +CLOCK | BUFGP | 107 | +-----------------------------------+------------------------+-------+ + +Timing Summary: +--------------- +Speed Grade: -6 + + Minimum period: 4.169ns (Maximum Frequency: 239.894MHz) + Minimum input arrival time before clock: 2.955ns + Maximum output required time after clock: 8.894ns + Maximum combinational path delay: No path found + +Timing Detail: +-------------- +All values displayed in nanoseconds (ns) + +========================================================================= +Timing constraint: Default period analysis for Clock 'CLOCK' + Clock period: 4.169ns (frequency: 239.894MHz) + Total number of paths / destination ports: 2896 / 286 +------------------------------------------------------------------------- +Delay: 4.169ns (Levels of Logic = 33) + Source: DATA_1_0 (FF) + Destination: DATA_STORE_31 (FF) + Source Clock: CLOCK rising + Destination Clock: CLOCK rising + + Data Path: DATA_1_0 to DATA_STORE_31 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDRE:C->Q 3 0.449 0.760 DATA_1_0 (DATA_1_0) + LUT2_L:I0->LO 2 0.347 0.000 exp_golomb_decoder_SUM<0>lut (SUM<0>) + MUXCY:S->O 1 0.235 0.000 exp_golomb_decoder_SUM<0>cy (exp_golomb_decoder_SUM<0>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<1>cy (exp_golomb_decoder_SUM<1>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<2>cy (exp_golomb_decoder_SUM<2>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<3>cy (exp_golomb_decoder_SUM<3>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<4>cy (exp_golomb_decoder_SUM<4>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<5>cy (exp_golomb_decoder_SUM<5>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<6>cy (exp_golomb_decoder_SUM<6>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<7>cy (exp_golomb_decoder_SUM<7>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<8>cy (exp_golomb_decoder_SUM<8>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<9>cy (exp_golomb_decoder_SUM<9>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<10>cy (exp_golomb_decoder_SUM<10>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<11>cy (exp_golomb_decoder_SUM<11>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<12>cy (exp_golomb_decoder_SUM<12>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<13>cy (exp_golomb_decoder_SUM<13>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<14>cy (exp_golomb_decoder_SUM<14>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<15>cy (exp_golomb_decoder_SUM<15>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<16>cy (exp_golomb_decoder_SUM<16>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<17>cy (exp_golomb_decoder_SUM<17>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<18>cy (exp_golomb_decoder_SUM<18>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<19>cy (exp_golomb_decoder_SUM<19>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<20>cy (exp_golomb_decoder_SUM<20>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<21>cy (exp_golomb_decoder_SUM<21>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<22>cy (exp_golomb_decoder_SUM<22>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<23>cy (exp_golomb_decoder_SUM<23>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<24>cy (exp_golomb_decoder_SUM<24>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<25>cy (exp_golomb_decoder_SUM<25>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<26>cy (exp_golomb_decoder_SUM<26>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<27>cy (exp_golomb_decoder_SUM<27>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<28>cy (exp_golomb_decoder_SUM<28>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<29>cy (exp_golomb_decoder_SUM<29>_cyo) + MUXCY:CI->O 0 0.042 0.000 exp_golomb_decoder_SUM<30>cy (exp_golomb_decoder_SUM<30>_cyo) + XORCY:CI->O 2 0.824 0.000 exp_golomb_decoder_SUM<31>_xor (SUM<31>) + FDRE:D 0.293 DATA_STORE_31 + ---------------------------------------- + Total 4.169ns (3.408ns logic, 0.760ns route) + (81.8% logic, 18.2% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'CLOCK' + Total number of paths / destination ports: 221 / 183 +------------------------------------------------------------------------- +Offset: 2.955ns (Levels of Logic = 2) + Source: RESET (PAD) + Destination: DATA_2_9 (FF) + Destination Clock: CLOCK rising + + Data Path: RESET to DATA_2_9 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 40 0.653 1.044 RESET_IBUF (RESET_IBUF) + LUT4:I0->O 12 0.347 0.689 _n00021_7 (_n000216) + FDRE:R 0.222 DATA_2_9 + ---------------------------------------- + Total 2.955ns (1.222ns logic, 1.733ns route) + (41.4% logic, 58.6% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'CLOCK' + Total number of paths / destination ports: 1947 / 33 +------------------------------------------------------------------------- +Offset: 8.894ns (Levels of Logic = 35) + Source: DATA_1_0 (FF) + Destination: DATA_OUT<31> (PAD) + Source Clock: CLOCK rising + + Data Path: DATA_1_0 to DATA_OUT<31> + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDRE:C->Q 3 0.449 0.760 DATA_1_0 (DATA_1_0) + LUT2_L:I0->LO 2 0.347 0.000 exp_golomb_decoder_SUM<0>lut (SUM<0>) + MUXCY:S->O 1 0.235 0.000 exp_golomb_decoder_SUM<0>cy (exp_golomb_decoder_SUM<0>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<1>cy (exp_golomb_decoder_SUM<1>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<2>cy (exp_golomb_decoder_SUM<2>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<3>cy (exp_golomb_decoder_SUM<3>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<4>cy (exp_golomb_decoder_SUM<4>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<5>cy (exp_golomb_decoder_SUM<5>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<6>cy (exp_golomb_decoder_SUM<6>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<7>cy (exp_golomb_decoder_SUM<7>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<8>cy (exp_golomb_decoder_SUM<8>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<9>cy (exp_golomb_decoder_SUM<9>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<10>cy (exp_golomb_decoder_SUM<10>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<11>cy (exp_golomb_decoder_SUM<11>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<12>cy (exp_golomb_decoder_SUM<12>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<13>cy (exp_golomb_decoder_SUM<13>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<14>cy (exp_golomb_decoder_SUM<14>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<15>cy (exp_golomb_decoder_SUM<15>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<16>cy (exp_golomb_decoder_SUM<16>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<17>cy (exp_golomb_decoder_SUM<17>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<18>cy (exp_golomb_decoder_SUM<18>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<19>cy (exp_golomb_decoder_SUM<19>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<20>cy (exp_golomb_decoder_SUM<20>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<21>cy (exp_golomb_decoder_SUM<21>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<22>cy (exp_golomb_decoder_SUM<22>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<23>cy (exp_golomb_decoder_SUM<23>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<24>cy (exp_golomb_decoder_SUM<24>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<25>cy (exp_golomb_decoder_SUM<25>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<26>cy (exp_golomb_decoder_SUM<26>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<27>cy (exp_golomb_decoder_SUM<27>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<28>cy (exp_golomb_decoder_SUM<28>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<29>cy (exp_golomb_decoder_SUM<29>_cyo) + MUXCY:CI->O 0 0.042 0.000 exp_golomb_decoder_SUM<30>cy (exp_golomb_decoder_SUM<30>_cyo) + XORCY:CI->O 2 0.824 0.546 exp_golomb_decoder_SUM<31>_xor (SUM<31>) + LUT3:I2->O 1 0.347 0.383 DATA_OUT<31>1 (DATA_OUT_31_OBUF) + OBUF:I->O 3.743 DATA_OUT_31_OBUF (DATA_OUT<31>) + ---------------------------------------- + Total 8.894ns (7.205ns logic, 1.689ns route) + (81.0% logic, 19.0% route) + +========================================================================= +CPU : 6.84 / 7.22 s | Elapsed : 7.00 / 7.00 s + +--> + +Total memory usage is 121148 kilobytes + +Number of errors : 0 ( 0 filtered) +Number of warnings : 0 ( 0 filtered) +Number of infos : 0 ( 0 filtered) +
trunk/docs/synthesis_reports/expgolomb/exp_golomb_decoder.syr Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

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