URL
https://opencores.org/ocsvn/hf-risc/hf-risc/trunk
Subversion Repositories hf-risc
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 8 to Rev 9
- ↔ Reverse comparison
Rev 8 → Rev 9
/hf-risc/trunk/ucore/peripherals_busmux.vhd
2,7 → 2,7
-- Sergio Johann Filho, 2013 - 2016 |
-- |
-- *This is a quick and dirty organization of a 3-stage pipelined MIPS microprocessor. All registers / memory |
-- accesses are synchonized to the rising edge of clock. The same processor could be designed with only 2 |
-- accesses are synchronized to the rising edge of clock. The same processor could be designed with only 2 |
-- pipeline stages, but this would require memories to be either asynchronous (as presented on comp arq text |
-- books), double clocked or operating on the opposite edge. Pipeline stages are: |
-- |