URL
https://opencores.org/ocsvn/jtag/jtag/trunk
Subversion Repositories jtag
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- This comparison shows the changes necessary to convert path
/
- from Rev 8 to Rev 9
- ↔ Reverse comparison
Rev 8 → Rev 9
/trunk/tap/rtl/verilog/tap_top.v
43,6 → 43,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2004/01/08 10:29:44 mohor |
// Control signals for tdo_pad_o mux are changed to negedge. |
// |
// Revision 1.1 2003/12/23 14:52:14 mohor |
// Directory structure changed. New version of TAP. |
// |
171,8 → 174,9
reg bypass_select; |
reg tdo_pad_o; |
reg tdo_padoe_o; |
reg tms_q1, tms_q2, tms_q3, tms_q4; |
wire tms_reset; |
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|
assign tdo_o = tdi_pad_i; |
assign shift_dr_o = shift_dr; |
assign pause_dr_o = pause_dr; |
183,6 → 187,19
assign mbist_select_o = mbist_select; |
assign debug_select_o = debug_select; |
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always @ (posedge tck_pad_i) |
begin |
tms_q1 <= #1 tms_pad_i; |
tms_q2 <= #1 tms_q1; |
tms_q3 <= #1 tms_q2; |
tms_q4 <= #1 tms_q3; |
end |
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assign tms_reset = tms_q1 & tms_q2 & tms_q3 & tms_q4 & tms_pad_i; // 5 consecutive TMS=1 causes reset |
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/********************************************************************************** |
* * |
* TAP State Machine: Fully JTAG compliant * |
194,6 → 211,8
begin |
if(trst_pad_i) |
test_logic_reset<=#1 1'b1; |
else if (tms_reset) |
test_logic_reset<=#1 1'b1; |
else |
begin |
if(tms_pad_i & (test_logic_reset | select_ir_scan)) |
208,6 → 227,8
begin |
if(trst_pad_i) |
run_test_idle<=#1 1'b0; |
else if (tms_reset) |
run_test_idle<=#1 1'b0; |
else |
if(~tms_pad_i & (test_logic_reset | run_test_idle | update_dr | update_ir)) |
run_test_idle<=#1 1'b1; |
220,6 → 241,8
begin |
if(trst_pad_i) |
select_dr_scan<=#1 1'b0; |
else if (tms_reset) |
select_dr_scan<=#1 1'b0; |
else |
if(tms_pad_i & (run_test_idle | update_dr | update_ir)) |
select_dr_scan<=#1 1'b1; |
232,6 → 255,8
begin |
if(trst_pad_i) |
capture_dr<=#1 1'b0; |
else if (tms_reset) |
capture_dr<=#1 1'b0; |
else |
if(~tms_pad_i & select_dr_scan) |
capture_dr<=#1 1'b1; |
244,6 → 269,8
begin |
if(trst_pad_i) |
shift_dr<=#1 1'b0; |
else if (tms_reset) |
shift_dr<=#1 1'b0; |
else |
if(~tms_pad_i & (capture_dr | shift_dr | exit2_dr)) |
shift_dr<=#1 1'b1; |
256,6 → 283,8
begin |
if(trst_pad_i) |
exit1_dr<=#1 1'b0; |
else if (tms_reset) |
exit1_dr<=#1 1'b0; |
else |
if(tms_pad_i & (capture_dr | shift_dr)) |
exit1_dr<=#1 1'b1; |
268,6 → 297,8
begin |
if(trst_pad_i) |
pause_dr<=#1 1'b0; |
else if (tms_reset) |
pause_dr<=#1 1'b0; |
else |
if(~tms_pad_i & (exit1_dr | pause_dr)) |
pause_dr<=#1 1'b1; |
280,6 → 311,8
begin |
if(trst_pad_i) |
exit2_dr<=#1 1'b0; |
else if (tms_reset) |
exit2_dr<=#1 1'b0; |
else |
if(tms_pad_i & pause_dr) |
exit2_dr<=#1 1'b1; |
292,6 → 325,8
begin |
if(trst_pad_i) |
update_dr<=#1 1'b0; |
else if (tms_reset) |
update_dr<=#1 1'b0; |
else |
if(tms_pad_i & (exit1_dr | exit2_dr)) |
update_dr<=#1 1'b1; |
304,6 → 339,8
begin |
if(trst_pad_i) |
select_ir_scan<=#1 1'b0; |
else if (tms_reset) |
select_ir_scan<=#1 1'b0; |
else |
if(tms_pad_i & select_dr_scan) |
select_ir_scan<=#1 1'b1; |
316,6 → 353,8
begin |
if(trst_pad_i) |
capture_ir<=#1 1'b0; |
else if (tms_reset) |
capture_ir<=#1 1'b0; |
else |
if(~tms_pad_i & select_ir_scan) |
capture_ir<=#1 1'b1; |
328,6 → 367,8
begin |
if(trst_pad_i) |
shift_ir<=#1 1'b0; |
else if (tms_reset) |
shift_ir<=#1 1'b0; |
else |
if(~tms_pad_i & (capture_ir | shift_ir | exit2_ir)) |
shift_ir<=#1 1'b1; |
340,6 → 381,8
begin |
if(trst_pad_i) |
exit1_ir<=#1 1'b0; |
else if (tms_reset) |
exit1_ir<=#1 1'b0; |
else |
if(tms_pad_i & (capture_ir | shift_ir)) |
exit1_ir<=#1 1'b1; |
352,6 → 395,8
begin |
if(trst_pad_i) |
pause_ir<=#1 1'b0; |
else if (tms_reset) |
pause_ir<=#1 1'b0; |
else |
if(~tms_pad_i & (exit1_ir | pause_ir)) |
pause_ir<=#1 1'b1; |
364,6 → 409,8
begin |
if(trst_pad_i) |
exit2_ir<=#1 1'b0; |
else if (tms_reset) |
exit2_ir<=#1 1'b0; |
else |
if(tms_pad_i & pause_ir) |
exit2_ir<=#1 1'b1; |
376,6 → 423,8
begin |
if(trst_pad_i) |
update_ir<=#1 1'b0; |
else if (tms_reset) |
update_ir<=#1 1'b0; |
else |
if(tms_pad_i & (exit1_ir | exit2_ir)) |
update_ir<=#1 1'b1; |
404,11 → 453,9
begin |
if(trst_pad_i) |
jtag_ir[`IR_LENGTH-1:0] <= #1 `IR_LENGTH'b0; |
else |
if(capture_ir) |
else if(capture_ir) |
jtag_ir <= #1 4'b0101; // This value is fixed for easier fault detection |
else |
if(shift_ir) |
else if(shift_ir) |
jtag_ir[`IR_LENGTH-1:0] <= #1 {tdi_pad_i, jtag_ir[`IR_LENGTH-1:1]}; |
end |
|
519,8 → 566,9
begin |
if(trst_pad_i) |
latched_jtag_ir <=#1 `IDCODE; // IDCODE selected after reset |
else |
if(update_ir) |
else if (tms_reset) |
latched_jtag_ir <=#1 `IDCODE; // IDCODE selected after reset |
else if(update_ir) |
latched_jtag_ir <=#1 jtag_ir; |
end |
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