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Rev 8 → Rev 9

/uart6551/trunk/trunk/rtl/uart6551.sv
46,7 → 46,7
rxDRQ_o, txDRQ_o,
xclk_i, RxC_i
);
parameter pClkFreq = 40;
parameter pClkFreq = 100;
parameter pCounterBits = 24;
parameter pFifoSize = 1024;
parameter pClkDiv = 24'd1302; // 9.6k baud, 200.000MHz clock
450,7 → 450,7
 
always @(posedge clk_i)
if (rst_i)
c <= 1'd1;
c <= 24'd1;
else begin
c <= c + 2'd1;
if (c >= clkdiv2)
468,7 → 468,7
wire rxClkEdge;
edge_det ed2(.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(RxCs[1]), .pe(rxClkEdge), .ne() );
 
always @(xClkSrc or xclkEdge or ibaud16)
always_comb
if (xClkSrc) // 16x external clock (xclk)
baud16 <= xclkEdge;
else
/uart6551/trunk/trunk/rtl/uart6551BaudLUT.sv
35,7 → 35,7
// ============================================================================
//
module uart6551BaudLUT(a, o);
parameter pClkFreq = 40;
parameter pClkFreq = 100;
parameter pCounterBits = 24;
input [4:0] a;
output reg [pCounterBits-1:0] o;
124,7 → 124,34
5'd21: o <= 24'd5; // 921600 baud
default: o <= 24'd521; // 9600 baud
endcase
else if (pClkFreq==100)
case (a) // synopsys full_case parallel_case
5'd0: o <= 0;
5'd1: o <= 24'd125000; // 50 baud
5'd2: o <= 24'd83333; // 75 baud
5'd3: o <= 24'd56860; // 109.92 baud
5'd4: o <= 24'd46441; // 134.58 baud
5'd5: o <= 24'd41667; // 150 baud
5'd6: o <= 24'd20833; // 300 baud
5'd7: o <= 24'd10417; // 600 baud
5'd8: o <= 24'd5208; // 1200 baud
5'd9: o <= 24'd3472; // 1800 baud
5'd10: o <= 24'd2604; // 2400 baud
5'd11: o <= 24'd1736; // 3600 baud
5'd12: o <= 24'd1302; // 4800 baud
5'd13: o <= 24'd868; // 7200 baud
5'd14: o <= 24'd651; // 9600 baud
5'd15: o <= 24'd326; // 19200 baud
 
5'd16: o <= 24'd163; // 38400 baud
5'd17: o <= 24'd109; // 57600 baud
5'd18: o <= 24'd54; // 115200 baud
5'd19: o <= 24'd27; // 230400 baud
5'd20: o <= 24'd14; // 460800 baud
5'd21: o <= 24'd7; // 921600 baud
default: o <= 24'd651; // 9600 baud
endcase
 
endmodule
 
 
/uart6551/trunk/trunk/rtl/uart6551Tx.sv
37,7 → 37,7
`define IDLE 0
`define CNT 1
 
//`define UART_NO_TX_FIFO 1'b1
`define UART_NO_TX_FIFO 1'b1
 
module uart6551Tx(rst, clk, cyc, cs, wr, din, ack,
fifoEnable, fifoClear, txBreak,
69,7 → 69,11
reg [7:0] t1;
reg [11:0] t2;
reg [11:0] tx_data; // transmit data working reg (raw)
reg state; // state machine state
typedef enum logic {
IDLE = 1'b0,
XMIT
} state_t;
state_t state; // state machine state
reg [7:0] cnt; // baud clock counter
reg rd;
reg p1, p2; // parity bit
81,10 → 85,10
reg [7:0] fdo2;
reg empty;
 
always @(posedge clk)
always_ff @(posedge clk)
if (awr) fdo2 <= {3'd0,din};
 
always @(posedge clk)
always_ff @(posedge clk)
begin
if (awr) empty <= 0;
else if (rd) empty <= 1;
94,11 → 98,11
wire [7:0] fdo = fdo2;
`else
reg [7:0] fdo2;
always @(posedge clk)
always_ff @(posedge clk)
if (awr) fdo2 <= {3'd0,din};
// generate an empty signal for when the fifo is disabled
reg fempty2;
always @(posedge clk)
always_ff @(posedge clk)
if (rst)
fempty2 <= 1;
else begin
132,11 → 136,11
// this mask is needed for proper parity generation
integer n;
reg [7:0] mask;
always @*
always_comb
for (n = 0; n < 8; n = n + 1)
mask[n] = n < wordLength ? 1'b1 : 1'b0;
 
always @*
always_comb
if (txBreak)
t1 <= 0;
else
144,7 → 148,7
 
 
// compute parity bit
always @*
always_comb
begin
case (parityCtrl)
3'b001: p1 <= ~^t1;// odd parity
164,7 → 168,7
if (ce) p2 <= p1;
*/
// Insert start, parity bit and stop
always @*
always_comb
case(wordLength)
4'd5: t2 <= {5'b11111,p1,t1[4:0],1'b0};
4'd6: t2 <= {4'b1111,p1,t1[5:0],1'b0};
172,25 → 176,25
default: t2 <= {2'b11,p1,t1[7:0],1'b0};
endcase
 
always @(posedge clk)
always_ff @(posedge clk)
if (rst)
state <= `IDLE;
state <= IDLE;
else begin
if (clear)
state <= `IDLE;
state <= IDLE;
if (baud16x_ce) begin
case(state)
`IDLE:
if ((!empty && cts)||txBreak)
state <= `CNT;
`CNT:
if (cnt==frameSize)
state <= `IDLE;
IDLE:
if (((!empty && cts)||txBreak) && cnt==frameSize)
state <= XMIT;
XMIT:
if (cnt==frameSize-1)
state <= IDLE;
endcase
end
end
 
always @(posedge clk)
always_ff @(posedge clk)
if (rst)
cnt <= 8'h00;
else begin
197,16 → 201,14
if (clear)
cnt <= 8'h00;
if (baud16x_ce) begin
case(state)
`IDLE:
cnt <= 8'h00;
`CNT:
if (cnt==frameSize)
cnt <= 8'h0;
else
cnt <= cnt + 8'd1;
endcase
end
end
 
always @(posedge clk)
always_ff @(posedge clk)
if (rst)
rd <= 0;
else begin
213,25 → 215,25
rd <= 0;
if (clear)
rd <= 0;
if (baud16x_ce) begin
if (baud16x_ce)
case(state)
`IDLE:
if ((!empty && cts)||txBreak)
IDLE:
if (((!empty && cts)||txBreak) && cnt==frameSize)
rd <= 1;
default: ;
endcase
end
end
 
always @(posedge clk)
always_ff @(posedge clk)
if (rst)
tx_data <= 12'hFFF;
else begin
if (baud16x_ce) begin
case(state)
`IDLE:
if ((!empty && cts)||txBreak)
IDLE:
if (((!empty && cts)||txBreak) && cnt==frameSize)
tx_data <= t2;
`CNT:
XMIT:
// Shift the data out. LSB first.
if (cnt[3:0]==4'hF)
tx_data <= {1'b1,tx_data[11:1]};
239,7 → 241,7
end
end
 
always @(posedge clk)
always_ff @(posedge clk)
if (rst)
txd <= 1'b1;
else

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