URL
https://opencores.org/ocsvn/uart16550/uart16550/trunk
Subversion Repositories uart16550
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- This comparison shows the changes necessary to convert path
/
- from Rev 83 to Rev 84
- ↔ Reverse comparison
Rev 83 → Rev 84
/trunk/rtl/verilog/uart_regs.v
62,6 → 62,22
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.38 2002/07/22 23:02:23 gorban |
// Bug Fixes: |
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. |
// Problem reported by Kenny.Tung. |
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. |
// |
// Improvements: |
// * Made FIFO's as general inferrable memory where possible. |
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). |
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times. |
// |
// * Added optional baudrate output (baud_o). |
// This is identical to BAUDOUT* signal on 16550 chip. |
// It outputs 16xbit_clock_rate - the divided clock. |
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. |
// |
// Revision 1.37 2001/12/27 13:24:09 mohor |
// lsr[7] was not showing overrun errors. |
// |
198,7 → 214,7
`include "timescale.v" |
// synopsys translate_on |
|
//`include "uart_defines.v" |
`include "uart_defines.v" |
|
`define UART_DL1 7:0 |
`define UART_DL2 15:8 |
/trunk/rtl/verilog/uart_top.v
64,6 → 64,22
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.18 2002/07/22 23:02:23 gorban |
// Bug Fixes: |
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. |
// Problem reported by Kenny.Tung. |
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. |
// |
// Improvements: |
// * Made FIFO's as general inferrable memory where possible. |
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). |
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times. |
// |
// * Added optional baudrate output (baud_o). |
// This is identical to BAUDOUT* signal on 16550 chip. |
// It outputs 16xbit_clock_rate - the divided clock. |
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. |
// |
// Revision 1.17 2001/12/19 08:40:03 mohor |
// Warnings fixed (unused signals removed). |
// |
119,7 → 135,7
`include "timescale.v" |
// synopsys translate_on |
|
// `include "uart_defines.v" |
`include "uart_defines.v" |
|
module uart_top ( |
wb_clk_i, |
/trunk/rtl/verilog/raminfr.v
1,95 → 1,111
////////////////////////////////////////////////////////////////////// |
//// //// |
//// raminfr.v //// |
//// //// |
//// //// |
//// This file is part of the "UART 16550 compatible" project //// |
//// http://www.opencores.org/cores/uart16550/ //// |
//// //// |
//// Documentation related to this project: //// |
//// - http://www.opencores.org/cores/uart16550/ //// |
//// //// |
//// Projects compatibility: //// |
//// - WISHBONE //// |
//// RS232 Protocol //// |
//// 16550D uart (mostly supported) //// |
//// //// |
//// Overview (main Features): //// |
//// Inferrable Distributed RAM for FIFOs //// |
//// //// |
//// Known problems (limits): //// |
//// None . //// |
//// //// |
//// To Do: //// |
//// Nothing so far. //// |
//// //// |
//// Author(s): //// |
//// - gorban@opencores.org //// |
//// - Jacob Gorban //// |
//// //// |
//// Created: 2002/07/22 //// |
//// Last Updated: 2002/07/22 //// |
//// (See log for the revision history) //// |
//// //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000, 2001 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
|
//Following is the Verilog code for a dual-port RAM with asynchronous read. |
module raminfr |
(clk, we, a, dpra, di, dpo); |
|
parameter addr_width = 4; |
parameter data_width = 8; |
parameter depth = 16; |
|
input clk; |
input we; |
input [addr_width-1:0] a; |
input [addr_width-1:0] dpra; |
input [data_width-1:0] di; |
//output [data_width-1:0] spo; |
output [data_width-1:0] dpo; |
reg [data_width-1:0] ram [depth-1:0]; |
|
wire [data_width-1:0] dpo; |
wire [data_width-1:0] di; |
wire [addr_width-1:0] a; |
wire [addr_width-1:0] dpra; |
|
always @(posedge clk) begin |
if (we) |
ram[a] <= di; |
end |
// assign spo = ram[a]; |
assign dpo = ram[dpra]; |
endmodule |
|
////////////////////////////////////////////////////////////////////// |
//// //// |
//// raminfr.v //// |
//// //// |
//// //// |
//// This file is part of the "UART 16550 compatible" project //// |
//// http://www.opencores.org/cores/uart16550/ //// |
//// //// |
//// Documentation related to this project: //// |
//// - http://www.opencores.org/cores/uart16550/ //// |
//// //// |
//// Projects compatibility: //// |
//// - WISHBONE //// |
//// RS232 Protocol //// |
//// 16550D uart (mostly supported) //// |
//// //// |
//// Overview (main Features): //// |
//// Inferrable Distributed RAM for FIFOs //// |
//// //// |
//// Known problems (limits): //// |
//// None . //// |
//// //// |
//// To Do: //// |
//// Nothing so far. //// |
//// //// |
//// Author(s): //// |
//// - gorban@opencores.org //// |
//// - Jacob Gorban //// |
//// //// |
//// Created: 2002/07/22 //// |
//// Last Updated: 2002/07/22 //// |
//// (See log for the revision history) //// |
//// //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000, 2001 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2002/07/22 23:02:23 gorban |
// Bug Fixes: |
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. |
// Problem reported by Kenny.Tung. |
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. |
// |
// Improvements: |
// * Made FIFO's as general inferrable memory where possible. |
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). |
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times. |
// |
// * Added optional baudrate output (baud_o). |
// This is identical to BAUDOUT* signal on 16550 chip. |
// It outputs 16xbit_clock_rate - the divided clock. |
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. |
// |
|
//Following is the Verilog code for a dual-port RAM with asynchronous read. |
module raminfr |
(clk, we, a, dpra, di, dpo); |
|
parameter addr_width = 4; |
parameter data_width = 8; |
parameter depth = 16; |
|
input clk; |
input we; |
input [addr_width-1:0] a; |
input [addr_width-1:0] dpra; |
input [data_width-1:0] di; |
//output [data_width-1:0] spo; |
output [data_width-1:0] dpo; |
reg [data_width-1:0] ram [depth-1:0]; |
|
wire [data_width-1:0] dpo; |
wire [data_width-1:0] di; |
wire [addr_width-1:0] a; |
wire [addr_width-1:0] dpra; |
|
always @(posedge clk) begin |
if (we) |
ram[a] <= di; |
end |
// assign spo = ram[a]; |
assign dpo = ram[dpra]; |
endmodule |
|
/trunk/rtl/verilog/uart_debug_if.v
54,6 → 54,22
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.4 2002/07/22 23:02:23 gorban |
// Bug Fixes: |
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. |
// Problem reported by Kenny.Tung. |
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. |
// |
// Improvements: |
// * Made FIFO's as general inferrable memory where possible. |
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). |
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times. |
// |
// * Added optional baudrate output (baud_o). |
// This is identical to BAUDOUT* signal on 16550 chip. |
// It outputs 16xbit_clock_rate - the divided clock. |
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. |
// |
// Revision 1.3 2001/12/19 08:40:03 mohor |
// Warnings fixed (unused signals removed). |
// |
68,7 → 84,7
`include "timescale.v" |
// synopsys translate_on |
|
//`include "uart_defines.v" |
`include "uart_defines.v" |
|
module uart_debug_if (/*AUTOARG*/ |
// Outputs |
/trunk/rtl/verilog/uart_receiver.v
63,6 → 63,22
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.28 2002/07/22 23:02:23 gorban |
// Bug Fixes: |
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. |
// Problem reported by Kenny.Tung. |
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. |
// |
// Improvements: |
// * Made FIFO's as general inferrable memory where possible. |
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). |
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times. |
// |
// * Added optional baudrate output (baud_o). |
// This is identical to BAUDOUT* signal on 16550 chip. |
// It outputs 16xbit_clock_rate - the divided clock. |
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. |
// |
// Revision 1.27 2001/12/30 20:39:13 mohor |
// More than one character was stored in case of break. End of the break |
// was not detected correctly. |
174,7 → 190,7
`include "timescale.v" |
// synopsys translate_on |
|
//`include "uart_defines.v" |
`include "uart_defines.v" |
|
module uart_receiver (clk, wb_rst_i, lcr, rf_pop, srx_pad_i, enable, |
counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse); |
/trunk/rtl/verilog/uart_rfifo.v
60,6 → 60,22
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2002/07/22 23:02:23 gorban |
// Bug Fixes: |
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. |
// Problem reported by Kenny.Tung. |
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. |
// |
// Improvements: |
// * Made FIFO's as general inferrable memory where possible. |
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). |
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times. |
// |
// * Added optional baudrate output (baud_o). |
// This is identical to BAUDOUT* signal on 16550 chip. |
// It outputs 16xbit_clock_rate - the divided clock. |
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. |
// |
// Revision 1.16 2001/12/20 13:25:46 mohor |
// rx push changed to be only one cycle wide. |
// |
123,7 → 139,7
`include "timescale.v" |
// synopsys translate_on |
|
//`include "uart_defines.v" |
`include "uart_defines.v" |
|
module uart_rfifo (clk, |
wb_rst_i, data_in, data_out, |
/trunk/rtl/verilog/uart_tfifo.v
60,6 → 60,22
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2002/07/22 23:02:23 gorban |
// Bug Fixes: |
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. |
// Problem reported by Kenny.Tung. |
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. |
// |
// Improvements: |
// * Made FIFO's as general inferrable memory where possible. |
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). |
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times. |
// |
// * Added optional baudrate output (baud_o). |
// This is identical to BAUDOUT* signal on 16550 chip. |
// It outputs 16xbit_clock_rate - the divided clock. |
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. |
// |
// Revision 1.16 2001/12/20 13:25:46 mohor |
// rx push changed to be only one cycle wide. |
// |
123,7 → 139,7
`include "timescale.v" |
// synopsys translate_on |
|
//`include "uart_defines.v" |
`include "uart_defines.v" |
|
module uart_tfifo (clk, |
wb_rst_i, data_in, data_out, |
/trunk/rtl/verilog/uart_wb.v
64,6 → 64,22
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.15 2002/07/22 23:02:23 gorban |
// Bug Fixes: |
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. |
// Problem reported by Kenny.Tung. |
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. |
// |
// Improvements: |
// * Made FIFO's as general inferrable memory where possible. |
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). |
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times. |
// |
// * Added optional baudrate output (baud_o). |
// This is identical to BAUDOUT* signal on 16550 chip. |
// It outputs 16xbit_clock_rate - the divided clock. |
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. |
// |
// Revision 1.12 2001/12/19 08:03:34 mohor |
// Warnings cleared. |
// |
118,7 → 134,7
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
//`include "uart_defines.v" |
`include "uart_defines.v" |
|
module uart_wb (clk, wb_rst_i, |
wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_adr_i, |
/trunk/rtl/verilog/uart_transmitter.v
63,6 → 63,22
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.18 2002/07/22 23:02:23 gorban |
// Bug Fixes: |
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. |
// Problem reported by Kenny.Tung. |
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. |
// |
// Improvements: |
// * Made FIFO's as general inferrable memory where possible. |
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). |
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times. |
// |
// * Added optional baudrate output (baud_o). |
// This is identical to BAUDOUT* signal on 16550 chip. |
// It outputs 16xbit_clock_rate - the divided clock. |
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. |
// |
// Revision 1.16 2002/01/08 11:29:40 mohor |
// tf_pop was too wide. Now it is only 1 clk cycle width. |
// |
133,7 → 149,7
`include "timescale.v" |
// synopsys translate_on |
|
//`include "uart_defines.v" |
`include "uart_defines.v" |
|
module uart_transmitter (clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, stx_pad_o, tstate, tf_count, tx_reset, lsr_mask); |
|