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    from Rev 90 to Rev 91
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Rev 90 → Rev 91

/trunk/hdl/filelist.dc
1,149 → 1,149
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/behav/sparc_libs/u1_lib.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/behav/sparc_libs/m1_lib.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/behav/sparc_libs/u1_lib.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_divcntl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/test_stub_bist.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_dcl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_frf.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_dctldp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_mared.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ffu.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_prencoder16.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_rml.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_tlbdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_qdp1.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_irf_register.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_dec.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_milfsm.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_pcx_qmon.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_dc_parity_gen.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_madp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_div_yreg.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_eclccr.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_wen.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ffu_vis.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_rf16x32.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_lfsr5.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_mamul.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_dctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_stb_rwdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc_dec.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrfsm.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_tlb.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/cpx_spc_buf.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_mast.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_mul_top.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_inc3.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_rf32x152b.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_dcl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_byp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/cpx_spc_rpt.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_tlu_intdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_reg.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_dctldp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_qctl2.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_par16.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/test_stub_scan.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/mul64.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_qdp2.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_dcd.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_maexp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_maaeqb.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_mdqctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog_rs1.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_incr64.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/synchronizer_asr.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl_visctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_div.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluadder64.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_irf_register.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_mul_top.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_lru4.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_stb_rwdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_mul_dp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_madp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_stb_ctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_swpla.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_par32.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_cnt6.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluor32.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_irf.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_cmp35.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_hyperv.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_par32.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_dcache_lfsr.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_scm.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_alulogic.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_excpctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_rf16x160.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_imd.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_rrobin_picker2.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_maexp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_eccctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_clk_cl_sparc_cmp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_reg.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_tlu_dec64.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_alulogic.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_errdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_swl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_misctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_rrobin_picker.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_rrobin_picker2.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_frf.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ffu_dp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluor32.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_mdqctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_scm.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_alu_16eql.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_cwp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_incr46.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_stb_rwctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_ctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_par34.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_tdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_div_32eql.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/swrvr_dlib.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_lsurpt.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_pib.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_dctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_mald.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_maaddr.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_maaeqb.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_idct.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_dcdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_fdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_lsurpt1.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_alu_16eql.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_wseldp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_qctl2.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_stb_ctldp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_rf32x80.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_ctr5.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_tagdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_par16.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ffu_dp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluaddsub.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_lsurpt1.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_stb_ctldp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluadder64.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_eclcomp7.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_cnt6.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_tlu_intctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_stb_ctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_sscan.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_wseldp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_mactl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_rndrob.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_hyperv.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_milfsm.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_wen.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_tlu_penc64.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_divcntl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_rf32x152b.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_rf16x32.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_icd.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_byp_eccgen.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_ctr5.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluspr.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/synchronizer_asr.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_mul_cntl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_invctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/cmp_sram_redhdr.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/cluster_header.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_eccctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl_visctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrcmpl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_mul_dp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_mmu_ctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_qdp2.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_lfsr5.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_alu.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_fcl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ffu_part_add32.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_lsurpt.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_mast.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_asi_decode.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_fdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_ctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_mmu_dp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_tagdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_stb_rwctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_rndrob.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_qctl1.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_wb.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_lru4.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_mmu_dp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_fcl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_rf16x160.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_div.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_pib.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_mald.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/swrvr_clib.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_maaddr.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_errctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_dcache_lfsr.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_mmu_ctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_invctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_pcx_qmon.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_dec.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_rml.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_rrobin_picker.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc_dec.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_mbist.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_par34.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/cpx_spc_rpt.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_byp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/test_stub_scan.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_tlu_zcmp64.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_clk_cl_sparc_cmp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluzcmp64.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_mbist.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_excpctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_rndrob.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_swpla.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_mamul.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_swl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_rndrob.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_eclcomp7.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_tlu_intdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_misctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/swrvr_clib.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_tlbdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_dc_parity_gen.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_addern_32.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_tlu_penc64.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_imd.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluspr.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_alu.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ffu.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_tcl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_div_yreg.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_eclccr.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_tlu_intctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_tdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/test_stub_bist.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_qdp1.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_cwp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/swrvr_dlib.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluzcmp64.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_shft.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_asi_decode.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ffu_vis.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_sscan.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_cmp35.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/cmp_sram_redhdr.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_incr46.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/cpx_spc_buf.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/mul64.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_dcdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_byp_eccgen.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_inc3.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/cluster_header.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_dcd.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_wb.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_tlb.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrcmpl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_prencoder16.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_mactl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/s1_top/rst_ctrl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/s1_top/int_ctrl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/s1_top/spc2wbm.v
152,38 → 152,43
# The Tcl script under $S1_ROOT/tools/src/build_dc.cmd is attached at the end of the filelist for DC;
# if you modify this file *REMEMBER* to run 'update_filelist' or you'll run the old version!!!
 
# Technology-independent elaboration and linking
# Variables setting
 
set active_design s1_top
elaborate $active_design
current_design $active_design
link
uniquify
check_design
set sub_modules {sparc_ifu lsu sparc_exu sparc_ffu sparc_mul_top spu tlu s1_top}
set sub_clocks {rclk clk sys_clock_i}
set sub_resets {grst_l arst_l sys_reset_i}
 
# Constraints and mapping on target library
foreach active_design $sub_modules {
 
create_clock -period 4.0 -waveform [list 0 2.0] sys_clock_i
set_input_delay 2.0 -clock sys_clock_i -max [all_inputs]
set_output_delay 1.0 -clock sys_clock_i -max [all_outputs]
set_dont_touch_network [list sys_clock_i sys_reset_i]
set_drive 0 [list sys_clock_i sys_reset_i]
set_wire_load_mode enclosed
set_max_area 0
set_fix_multiple_port_nets -buffer_constants -all
compile
# Technology-independent elaboration and linking
elaborate $active_design
current_design $active_design
link
uniquify -dont_skip_empty_designs
 
# Export the mapped design
# Set constraints and mapping on target library
create_clock -period 5.0 -waveform [list 0 2.5] [get_ports $sub_clocks]
set_input_delay 1.8 -clock [get_clocks $sub_clocks] -max [all_inputs]
set_output_delay 1.2 -clock [get_clocks $sub_clocks] -max [all_outputs]
set_dont_touch_network [concat $sub_clocks $sub_resets]
set_drive 0 [concat $sub_clocks $sub_resets]
set_max_area 0
set_wire_load_mode enclosed
set_fix_multiple_port_nets -buffer_constants -all
compile
 
remove_unconnected_ports [find -hierarchy cell {"*"}]
write -format ddc -hierarchy -output $active_design.ddc
write -format verilog -hierarchy -output $active_design.sv
# Export the mapped design
remove_unconnected_ports [find -hierarchy cell {"*"}]
set_dont_touch current_design
write -format ddc -hierarchy -output $active_design.ddc
write -format verilog -hierarchy -output $active_design.sv
 
# Report area and timing
# Report area and timing
report_area -hierarchy > report_${active_design}_area.rpt
report_timing > report_${active_design}_timing.rpt
report_constraint -all_violators > report_${active_design}_constraint.rpt
 
report_area -hierarchy > report_area.rpt
report_timing > report_timing.rpt
report_constraint -all_violators > report_constraint.rpt
}
 
quit
 
/trunk/hdl/filelist.icarus
1,149 → 1,149
~/s1_core/hdl/behav/sparc_libs/u1_lib.v
~/s1_core/hdl/behav/sparc_libs/m1_lib.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_dcl.v
~/s1_core/hdl/rtl/sparc_core/bw_r_frf.v
~/s1_core/hdl/rtl/sparc_core/lsu_dctldp.v
~/s1_core/hdl/rtl/sparc_core/spu_mared.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrfsm.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_mdqctl.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog_rs1.v
~/s1_core/hdl/rtl/sparc_core/tlu_incr64.v
~/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl_visctl.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_div.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluadder64.v
~/s1_core/hdl/rtl/sparc_core/bw_r_irf_register.v
~/s1_core/hdl/rtl/sparc_core/sparc_mul_top.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_lru4.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc.v
~/s1_core/hdl/rtl/sparc_core/lsu_stb_rwdp.v
~/s1_core/hdl/rtl/sparc_core/sparc_mul_dp.v
~/s1_core/hdl/rtl/sparc_core/spu_madp.v
~/s1_core/hdl/rtl/sparc_core/lsu_stb_ctl.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_swpla.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_par32.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_cnt6.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluor32.v
~/s1_core/hdl/rtl/sparc_core/bw_r_irf.v
~/s1_core/hdl/rtl/sparc_core/lsu_dcache_lfsr.v
~/s1_core/hdl/rtl/sparc_core/bw_r_scm.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_alulogic.v
~/s1_core/hdl/rtl/sparc_core/lsu_excpctl.v
~/s1_core/hdl/rtl/sparc_core/bw_r_rf16x160.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_imd.v
~/s1_core/hdl/rtl/sparc_core/lsu_rrobin_picker2.v
~/s1_core/hdl/rtl/sparc_core/spu_maexp.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_eccctl.v
~/s1_core/hdl/rtl/sparc_core/bw_clk_cl_sparc_cmp.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_reg.v
~/s1_core/hdl/rtl/sparc_core/sparc_tlu_dec64.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_errdp.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_div_32eql.v
~/s1_core/hdl/rtl/sparc_core/spu_lsurpt.v
~/s1_core/hdl/rtl/sparc_core/tlu_pib.v
~/s1_core/hdl/rtl/sparc_core/lsu_dctl.v
~/s1_core/hdl/rtl/sparc_core/spu_mald.v
~/s1_core/hdl/rtl/sparc_core/spu_maaddr.v
~/s1_core/hdl/rtl/sparc_core/spu_maaeqb.v
~/s1_core/hdl/rtl/sparc_core/bw_r_idct.v
~/s1_core/hdl/rtl/sparc_core/spu_lsurpt1.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_alu_16eql.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_wseldp.v
~/s1_core/hdl/rtl/sparc_core/lsu_qctl2.v
~/s1_core/hdl/rtl/sparc_core/lsu_stb_ctldp.v
~/s1_core/hdl/rtl/sparc_core/test_stub_bist.v
~/s1_core/hdl/rtl/sparc_core/lsu_qctl2.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc.v
~/s1_core/hdl/rtl/sparc_core/lsu_stb_rwctl.v
~/s1_core/hdl/rtl/sparc_core/spu_mamul.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc_dec.v
~/s1_core/hdl/rtl/sparc_core/spu_mast.v
~/s1_core/hdl/rtl/sparc_core/tlu_addern_32.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrcmpl.v
~/s1_core/hdl/rtl/sparc_core/spu_ctl.v
~/s1_core/hdl/rtl/sparc_core/tlu_rrobin_picker.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_divcntl.v
~/s1_core/hdl/rtl/sparc_core/sparc_mul_cntl.v
~/s1_core/hdl/rtl/sparc_core/lsu_dc_parity_gen.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_inc3.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_lfsr5.v
~/s1_core/hdl/rtl/sparc_core/bw_r_frf.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_invctl.v
~/s1_core/hdl/rtl/sparc_core/lsu_dcdp.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_mbist.v
~/s1_core/hdl/rtl/sparc_core/bw_r_rf32x80.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_dcl.v
~/s1_core/hdl/rtl/sparc_core/tlu_pib.v
~/s1_core/hdl/rtl/sparc_core/swrvr_dlib.v
~/s1_core/hdl/rtl/sparc_core/bw_r_irf.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_par16.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog.v
~/s1_core/hdl/rtl/sparc_core/sparc_ffu_dp.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluaddsub.v
~/s1_core/hdl/rtl/sparc_core/tlu_hyperv.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_milfsm.v
~/s1_core/hdl/rtl/sparc_core/spu_wen.v
~/s1_core/hdl/rtl/sparc_core/sparc_tlu_penc64.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_divcntl.v
~/s1_core/hdl/rtl/sparc_core/bw_r_rf32x152b.v
~/s1_core/hdl/rtl/sparc_core/bw_r_rf16x32.v
~/s1_core/hdl/rtl/sparc_core/cpx_spc_rpt.v
~/s1_core/hdl/rtl/sparc_core/swrvr_clib.v
~/s1_core/hdl/rtl/sparc_core/lsu_dctldp.v
~/s1_core/hdl/rtl/sparc_core/bw_r_idct.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_par34.v
~/s1_core/hdl/rtl/sparc_core/lsu_stb_rwdp.v
~/s1_core/hdl/rtl/sparc_core/bw_r_icd.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_ctr5.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluspr.v
~/s1_core/hdl/rtl/sparc_core/spu.v
~/s1_core/hdl/rtl/sparc_core/synchronizer_asr.v
~/s1_core/hdl/rtl/sparc_core/spu_madp.v
~/s1_core/hdl/rtl/sparc_core/sparc_ffu_vis.v
~/s1_core/hdl/rtl/sparc_core/sparc_tlu_intdp.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_ctr5.v
~/s1_core/hdl/rtl/sparc_core/lsu_dcache_lfsr.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_eccctl.v
~/s1_core/hdl/rtl/sparc_core/tlu_tdp.v
~/s1_core/hdl/rtl/sparc_core/lsu_stb_ctl.v
~/s1_core/hdl/rtl/sparc_core/sparc_mul_dp.v
~/s1_core/hdl/rtl/sparc_core/sparc_mul_cntl.v
~/s1_core/hdl/rtl/sparc_core/lsu_qdp2.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_lfsr5.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_alu.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_fcl.v
~/s1_core/hdl/rtl/sparc_core/sparc_ffu_part_add32.v
~/s1_core/hdl/rtl/sparc_core/spu_mast.v
~/s1_core/hdl/rtl/sparc_core/lsu_asi_decode.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_byp_eccgen.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_cwp.v
~/s1_core/hdl/rtl/sparc_core/sparc_ffu.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog_rs1.v
~/s1_core/hdl/rtl/sparc_core/bw_r_irf_register.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_fdp.v
~/s1_core/hdl/rtl/sparc_core/spu_ctl.v
~/s1_core/hdl/rtl/sparc_core/tlu_mmu_dp.v
~/s1_core/hdl/rtl/sparc_core/lsu_tagdp.v
~/s1_core/hdl/rtl/sparc_core/lsu_stb_rwctl.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_rndrob.v
~/s1_core/hdl/rtl/sparc_core/lsu_qctl1.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_errctl.v
~/s1_core/hdl/rtl/sparc_core/tlu_mmu_ctl.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_sscan.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_invctl.v
~/s1_core/hdl/rtl/sparc_core/lsu_pcx_qmon.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_dec.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_rml.v
~/s1_core/hdl/rtl/sparc_core/tlu_rrobin_picker.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc_dec.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_mbist.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_par34.v
~/s1_core/hdl/rtl/sparc_core/cpx_spc_rpt.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_byp.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_errdp.v
~/s1_core/hdl/rtl/sparc_core/spu_maaeqb.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_errctl.v
~/s1_core/hdl/rtl/sparc_core/lsu_dctl.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_cmp35.v
~/s1_core/hdl/rtl/sparc_core/lsu_qdp1.v
~/s1_core/hdl/rtl/sparc_core/test_stub_scan.v
~/s1_core/hdl/rtl/sparc_core/sparc_tlu_zcmp64.v
~/s1_core/hdl/rtl/sparc_core/spu_mamul.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_swl.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_rndrob.v
~/s1_core/hdl/rtl/sparc_core/spu_mared.v
~/s1_core/hdl/rtl/sparc_core/sparc_tlu_intctl.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_fdp.v
~/s1_core/hdl/rtl/sparc_core/tlu_mmu_dp.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_rml.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_fcl.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_dec.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_lru4.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_alu.v
~/s1_core/hdl/rtl/sparc_core/bw_r_icd.v
~/s1_core/hdl/rtl/sparc_core/cluster_header.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_eclcomp7.v
~/s1_core/hdl/rtl/sparc_core/sparc_tlu_intdp.v
~/s1_core/hdl/rtl/sparc_core/tlu_misctl.v
~/s1_core/hdl/rtl/sparc_core/swrvr_clib.v
~/s1_core/hdl/rtl/sparc_core/lsu_tlbdp.v
~/s1_core/hdl/rtl/sparc_core/lsu_dc_parity_gen.v
~/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl.v
~/s1_core/hdl/rtl/sparc_core/tlu_addern_32.v
~/s1_core/hdl/rtl/sparc_core/sparc_ffu.v
~/s1_core/hdl/rtl/sparc_core/tlu_tcl.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_div_yreg.v
~/s1_core/hdl/rtl/sparc_core/tlu.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_eclccr.v
~/s1_core/hdl/rtl/sparc_core/tlu_incr64.v
~/s1_core/hdl/rtl/sparc_core/sparc_tlu_zcmp64.v
~/s1_core/hdl/rtl/sparc_core/lsu_qdp2.v
~/s1_core/hdl/rtl/sparc_core/bw_r_dcd.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_reg.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_milfsm.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_mdqctl.v
~/s1_core/hdl/rtl/sparc_core/test_stub_scan.v
~/s1_core/hdl/rtl/sparc_core/sparc_tlu_intctl.v
~/s1_core/hdl/rtl/sparc_core/tlu_tdp.v
~/s1_core/hdl/rtl/sparc_core/lsu.v
~/s1_core/hdl/rtl/sparc_core/test_stub_bist.v
~/s1_core/hdl/rtl/sparc_core/lsu_qdp1.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_cwp.v
~/s1_core/hdl/rtl/sparc_core/swrvr_dlib.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluzcmp64.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_shft.v
~/s1_core/hdl/rtl/sparc_core/tlu_tcl.v
~/s1_core/hdl/rtl/sparc_core/spu_mactl.v
~/s1_core/hdl/rtl/sparc_core/bw_r_rf32x152b.v
~/s1_core/hdl/rtl/sparc_core/spu_wen.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluor32.v
~/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl.v
~/s1_core/hdl/rtl/sparc_core/sparc_ffu_dp.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluspr.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_imd.v
~/s1_core/hdl/rtl/sparc_core/bw_clk_cl_sparc_cmp.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_swpla.v
~/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl_visctl.v
~/s1_core/hdl/rtl/sparc_core/lsu_tlbdp.v
~/s1_core/hdl/rtl/sparc_core/lsu_rrobin_picker2.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_div.v
~/s1_core/hdl/rtl/sparc_core/sparc_ffu_vis.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_sscan.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu.v
~/s1_core/hdl/rtl/sparc_core/tlu.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_cmp35.v
~/s1_core/hdl/rtl/sparc_core/cmp_sram_redhdr.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_incr46.v
~/s1_core/hdl/rtl/sparc_core/spu_mald.v
~/s1_core/hdl/rtl/sparc_core/bw_r_scm.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_wseldp.v
~/s1_core/hdl/rtl/sparc_core/cpx_spc_buf.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqctl.v
~/s1_core/hdl/rtl/sparc_core/spu.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_rndrob.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqdp.v
~/s1_core/hdl/rtl/sparc_core/tlu_misctl.v
~/s1_core/hdl/rtl/sparc_core/sparc_ffu_part_add32.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_cnt6.v
~/s1_core/hdl/rtl/sparc_core/lsu_tagdp.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrfsm.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluzcmp64.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_div_32eql.v
~/s1_core/hdl/rtl/sparc_core/tlu_hyperv.v
~/s1_core/hdl/rtl/sparc_core/spu_maaddr.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluadder64.v
~/s1_core/hdl/rtl/sparc_core/spu_lsurpt.v
~/s1_core/hdl/rtl/sparc_core/cmp_sram_redhdr.v
~/s1_core/hdl/rtl/sparc_core/lsu.v
~/s1_core/hdl/rtl/sparc_core/spu_maexp.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_swl.v
~/s1_core/hdl/rtl/sparc_core/sparc_mul_top.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_alu_16eql.v
~/s1_core/hdl/rtl/sparc_core/mul64.v
~/s1_core/hdl/rtl/sparc_core/lsu_dcdp.v
~/s1_core/hdl/rtl/sparc_core/sparc.v
~/s1_core/hdl/rtl/sparc_core/lsu_qctl1.v
~/s1_core/hdl/rtl/sparc_core/lsu_excpctl.v
~/s1_core/hdl/rtl/sparc_core/bw_r_rf16x160.v
~/s1_core/hdl/rtl/sparc_core/spu_lsurpt1.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_byp_eccgen.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_inc3.v
~/s1_core/hdl/rtl/sparc_core/cluster_header.v
~/s1_core/hdl/rtl/sparc_core/bw_r_dcd.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_wb.v
~/s1_core/hdl/rtl/sparc_core/bw_r_tlb.v
~/s1_core/hdl/rtl/sparc_core/sparc_tlu_penc64.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrcmpl.v
~/s1_core/hdl/rtl/sparc_core/tlu_prencoder16.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_eclcomp7.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluaddsub.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_wb.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_alulogic.v
~/s1_core/hdl/rtl/sparc_core/sparc_tlu_dec64.v
~/s1_core/hdl/rtl/sparc_core/mul64.v
~/s1_core/hdl/rtl/sparc_core/spu_mactl.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqdp.v
~/s1_core/hdl/rtl/s1_top/rst_ctrl.v
~/s1_core/hdl/rtl/s1_top/int_ctrl.v
~/s1_core/hdl/rtl/s1_top/spc2wbm.v
/trunk/hdl/filelist.vcs
1,149 → 1,149
-v ~/s1_core/hdl/behav/sparc_libs/u1_lib.v
-v ~/s1_core/hdl/behav/sparc_libs/m1_lib.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_dcl.v
-v ~/s1_core/hdl/rtl/sparc_core/bw_r_frf.v
-v ~/s1_core/hdl/rtl/sparc_core/lsu_dctldp.v
-v ~/s1_core/hdl/rtl/sparc_core/spu_mared.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrfsm.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_mdqctl.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog_rs1.v
-v ~/s1_core/hdl/rtl/sparc_core/tlu_incr64.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl_visctl.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_div.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluadder64.v
-v ~/s1_core/hdl/rtl/sparc_core/bw_r_irf_register.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_mul_top.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_lru4.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc.v
-v ~/s1_core/hdl/rtl/sparc_core/lsu_stb_rwdp.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_mul_dp.v
-v ~/s1_core/hdl/rtl/sparc_core/spu_madp.v
-v ~/s1_core/hdl/rtl/sparc_core/lsu_stb_ctl.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_swpla.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_par32.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_cnt6.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluor32.v
-v ~/s1_core/hdl/rtl/sparc_core/bw_r_irf.v
-v ~/s1_core/hdl/rtl/sparc_core/lsu_dcache_lfsr.v
-v ~/s1_core/hdl/rtl/sparc_core/bw_r_scm.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_alulogic.v
-v ~/s1_core/hdl/rtl/sparc_core/lsu_excpctl.v
-v ~/s1_core/hdl/rtl/sparc_core/bw_r_rf16x160.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_imd.v
-v ~/s1_core/hdl/rtl/sparc_core/lsu_rrobin_picker2.v
-v ~/s1_core/hdl/rtl/sparc_core/spu_maexp.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_eccctl.v
-v ~/s1_core/hdl/rtl/sparc_core/bw_clk_cl_sparc_cmp.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_reg.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_tlu_dec64.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_errdp.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_div_32eql.v
-v ~/s1_core/hdl/rtl/sparc_core/spu_lsurpt.v
-v ~/s1_core/hdl/rtl/sparc_core/tlu_pib.v
-v ~/s1_core/hdl/rtl/sparc_core/lsu_dctl.v
-v ~/s1_core/hdl/rtl/sparc_core/spu_mald.v
-v ~/s1_core/hdl/rtl/sparc_core/spu_maaddr.v
-v ~/s1_core/hdl/rtl/sparc_core/spu_maaeqb.v
-v ~/s1_core/hdl/rtl/sparc_core/bw_r_idct.v
-v ~/s1_core/hdl/rtl/sparc_core/spu_lsurpt1.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_alu_16eql.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_wseldp.v
-v ~/s1_core/hdl/rtl/sparc_core/lsu_qctl2.v
-v ~/s1_core/hdl/rtl/sparc_core/lsu_stb_ctldp.v
-v ~/s1_core/hdl/rtl/sparc_core/test_stub_bist.v
-v ~/s1_core/hdl/rtl/sparc_core/lsu_qctl2.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc.v
-v ~/s1_core/hdl/rtl/sparc_core/lsu_stb_rwctl.v
-v ~/s1_core/hdl/rtl/sparc_core/spu_mamul.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc_dec.v
-v ~/s1_core/hdl/rtl/sparc_core/spu_mast.v
-v ~/s1_core/hdl/rtl/sparc_core/tlu_addern_32.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrcmpl.v
-v ~/s1_core/hdl/rtl/sparc_core/spu_ctl.v
-v ~/s1_core/hdl/rtl/sparc_core/tlu_rrobin_picker.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_divcntl.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_mul_cntl.v
-v ~/s1_core/hdl/rtl/sparc_core/lsu_dc_parity_gen.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_inc3.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_lfsr5.v
-v ~/s1_core/hdl/rtl/sparc_core/bw_r_frf.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_invctl.v
-v ~/s1_core/hdl/rtl/sparc_core/lsu_dcdp.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_mbist.v
-v ~/s1_core/hdl/rtl/sparc_core/bw_r_rf32x80.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_dcl.v
-v ~/s1_core/hdl/rtl/sparc_core/tlu_pib.v
-v ~/s1_core/hdl/rtl/sparc_core/swrvr_dlib.v
-v ~/s1_core/hdl/rtl/sparc_core/bw_r_irf.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_par16.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ffu_dp.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluaddsub.v
-v ~/s1_core/hdl/rtl/sparc_core/tlu_hyperv.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_milfsm.v
-v ~/s1_core/hdl/rtl/sparc_core/spu_wen.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_tlu_penc64.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_divcntl.v
-v ~/s1_core/hdl/rtl/sparc_core/bw_r_rf32x152b.v
-v ~/s1_core/hdl/rtl/sparc_core/bw_r_rf16x32.v
-v ~/s1_core/hdl/rtl/sparc_core/cpx_spc_rpt.v
-v ~/s1_core/hdl/rtl/sparc_core/swrvr_clib.v
-v ~/s1_core/hdl/rtl/sparc_core/lsu_dctldp.v
-v ~/s1_core/hdl/rtl/sparc_core/bw_r_idct.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_par34.v
-v ~/s1_core/hdl/rtl/sparc_core/lsu_stb_rwdp.v
-v ~/s1_core/hdl/rtl/sparc_core/bw_r_icd.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_ctr5.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluspr.v
-v ~/s1_core/hdl/rtl/sparc_core/spu.v
-v ~/s1_core/hdl/rtl/sparc_core/synchronizer_asr.v
-v ~/s1_core/hdl/rtl/sparc_core/spu_madp.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ffu_vis.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_tlu_intdp.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_ctr5.v
-v ~/s1_core/hdl/rtl/sparc_core/lsu_dcache_lfsr.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_eccctl.v
-v ~/s1_core/hdl/rtl/sparc_core/tlu_tdp.v
-v ~/s1_core/hdl/rtl/sparc_core/lsu_stb_ctl.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_mul_dp.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_mul_cntl.v
-v ~/s1_core/hdl/rtl/sparc_core/lsu_qdp2.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_lfsr5.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_alu.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_fcl.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ffu_part_add32.v
-v ~/s1_core/hdl/rtl/sparc_core/spu_mast.v
-v ~/s1_core/hdl/rtl/sparc_core/lsu_asi_decode.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_byp_eccgen.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_cwp.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ffu.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog_rs1.v
-v ~/s1_core/hdl/rtl/sparc_core/bw_r_irf_register.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_fdp.v
-v ~/s1_core/hdl/rtl/sparc_core/spu_ctl.v
-v ~/s1_core/hdl/rtl/sparc_core/tlu_mmu_dp.v
-v ~/s1_core/hdl/rtl/sparc_core/lsu_tagdp.v
-v ~/s1_core/hdl/rtl/sparc_core/lsu_stb_rwctl.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_rndrob.v
-v ~/s1_core/hdl/rtl/sparc_core/lsu_qctl1.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_errctl.v
-v ~/s1_core/hdl/rtl/sparc_core/tlu_mmu_ctl.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_sscan.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_invctl.v
-v ~/s1_core/hdl/rtl/sparc_core/lsu_pcx_qmon.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_dec.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_rml.v
-v ~/s1_core/hdl/rtl/sparc_core/tlu_rrobin_picker.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc_dec.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_mbist.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_par34.v
-v ~/s1_core/hdl/rtl/sparc_core/cpx_spc_rpt.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_byp.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_errdp.v
-v ~/s1_core/hdl/rtl/sparc_core/spu_maaeqb.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_errctl.v
-v ~/s1_core/hdl/rtl/sparc_core/lsu_dctl.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_cmp35.v
-v ~/s1_core/hdl/rtl/sparc_core/lsu_qdp1.v
-v ~/s1_core/hdl/rtl/sparc_core/test_stub_scan.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_tlu_zcmp64.v
-v ~/s1_core/hdl/rtl/sparc_core/spu_mamul.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_swl.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_rndrob.v
-v ~/s1_core/hdl/rtl/sparc_core/spu_mared.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_tlu_intctl.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_fdp.v
-v ~/s1_core/hdl/rtl/sparc_core/tlu_mmu_dp.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_rml.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_fcl.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_dec.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_lru4.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_alu.v
-v ~/s1_core/hdl/rtl/sparc_core/bw_r_icd.v
-v ~/s1_core/hdl/rtl/sparc_core/cluster_header.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_eclcomp7.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_tlu_intdp.v
-v ~/s1_core/hdl/rtl/sparc_core/tlu_misctl.v
-v ~/s1_core/hdl/rtl/sparc_core/swrvr_clib.v
-v ~/s1_core/hdl/rtl/sparc_core/lsu_tlbdp.v
-v ~/s1_core/hdl/rtl/sparc_core/lsu_dc_parity_gen.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl.v
-v ~/s1_core/hdl/rtl/sparc_core/tlu_addern_32.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ffu.v
-v ~/s1_core/hdl/rtl/sparc_core/tlu_tcl.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_div_yreg.v
-v ~/s1_core/hdl/rtl/sparc_core/tlu.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_eclccr.v
-v ~/s1_core/hdl/rtl/sparc_core/tlu_incr64.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_tlu_zcmp64.v
-v ~/s1_core/hdl/rtl/sparc_core/lsu_qdp2.v
-v ~/s1_core/hdl/rtl/sparc_core/bw_r_dcd.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_reg.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_milfsm.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_mdqctl.v
-v ~/s1_core/hdl/rtl/sparc_core/test_stub_scan.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_tlu_intctl.v
-v ~/s1_core/hdl/rtl/sparc_core/tlu_tdp.v
-v ~/s1_core/hdl/rtl/sparc_core/lsu.v
-v ~/s1_core/hdl/rtl/sparc_core/test_stub_bist.v
-v ~/s1_core/hdl/rtl/sparc_core/lsu_qdp1.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_cwp.v
-v ~/s1_core/hdl/rtl/sparc_core/swrvr_dlib.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluzcmp64.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_shft.v
-v ~/s1_core/hdl/rtl/sparc_core/tlu_tcl.v
-v ~/s1_core/hdl/rtl/sparc_core/spu_mactl.v
-v ~/s1_core/hdl/rtl/sparc_core/bw_r_rf32x152b.v
-v ~/s1_core/hdl/rtl/sparc_core/spu_wen.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluor32.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ffu_dp.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluspr.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_imd.v
-v ~/s1_core/hdl/rtl/sparc_core/bw_clk_cl_sparc_cmp.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_swpla.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl_visctl.v
-v ~/s1_core/hdl/rtl/sparc_core/lsu_tlbdp.v
-v ~/s1_core/hdl/rtl/sparc_core/lsu_rrobin_picker2.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_div.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ffu_vis.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_sscan.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu.v
-v ~/s1_core/hdl/rtl/sparc_core/tlu.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_cmp35.v
-v ~/s1_core/hdl/rtl/sparc_core/cmp_sram_redhdr.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_incr46.v
-v ~/s1_core/hdl/rtl/sparc_core/spu_mald.v
-v ~/s1_core/hdl/rtl/sparc_core/bw_r_scm.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_wseldp.v
-v ~/s1_core/hdl/rtl/sparc_core/cpx_spc_buf.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqctl.v
-v ~/s1_core/hdl/rtl/sparc_core/spu.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_rndrob.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqdp.v
-v ~/s1_core/hdl/rtl/sparc_core/tlu_misctl.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ffu_part_add32.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_cnt6.v
-v ~/s1_core/hdl/rtl/sparc_core/lsu_tagdp.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrfsm.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluzcmp64.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_div_32eql.v
-v ~/s1_core/hdl/rtl/sparc_core/tlu_hyperv.v
-v ~/s1_core/hdl/rtl/sparc_core/spu_maaddr.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluadder64.v
-v ~/s1_core/hdl/rtl/sparc_core/spu_lsurpt.v
-v ~/s1_core/hdl/rtl/sparc_core/cmp_sram_redhdr.v
-v ~/s1_core/hdl/rtl/sparc_core/lsu.v
-v ~/s1_core/hdl/rtl/sparc_core/spu_maexp.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_swl.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_mul_top.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_alu_16eql.v
-v ~/s1_core/hdl/rtl/sparc_core/mul64.v
-v ~/s1_core/hdl/rtl/sparc_core/lsu_dcdp.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc.v
-v ~/s1_core/hdl/rtl/sparc_core/lsu_qctl1.v
-v ~/s1_core/hdl/rtl/sparc_core/lsu_excpctl.v
-v ~/s1_core/hdl/rtl/sparc_core/bw_r_rf16x160.v
-v ~/s1_core/hdl/rtl/sparc_core/spu_lsurpt1.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_byp_eccgen.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_inc3.v
-v ~/s1_core/hdl/rtl/sparc_core/cluster_header.v
-v ~/s1_core/hdl/rtl/sparc_core/bw_r_dcd.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_wb.v
-v ~/s1_core/hdl/rtl/sparc_core/bw_r_tlb.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_tlu_penc64.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrcmpl.v
-v ~/s1_core/hdl/rtl/sparc_core/tlu_prencoder16.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_eclcomp7.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluaddsub.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_wb.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_exu_alulogic.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_tlu_dec64.v
-v ~/s1_core/hdl/rtl/sparc_core/mul64.v
-v ~/s1_core/hdl/rtl/sparc_core/spu_mactl.v
-v ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqdp.v
~/s1_core/hdl/rtl/s1_top/rst_ctrl.v
~/s1_core/hdl/rtl/s1_top/int_ctrl.v
~/s1_core/hdl/rtl/s1_top/spc2wbm.v
/trunk/hdl/filelist.fpga
1,149 → 1,149
~/s1_core/hdl/behav/sparc_libs/u1_lib.v
~/s1_core/hdl/behav/sparc_libs/m1_lib.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_dcl.v
~/s1_core/hdl/rtl/sparc_core/bw_r_frf.v
~/s1_core/hdl/rtl/sparc_core/lsu_dctldp.v
~/s1_core/hdl/rtl/sparc_core/spu_mared.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrfsm.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_mdqctl.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog_rs1.v
~/s1_core/hdl/rtl/sparc_core/tlu_incr64.v
~/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl_visctl.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_div.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluadder64.v
~/s1_core/hdl/rtl/sparc_core/bw_r_irf_register.v
~/s1_core/hdl/rtl/sparc_core/sparc_mul_top.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_lru4.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc.v
~/s1_core/hdl/rtl/sparc_core/lsu_stb_rwdp.v
~/s1_core/hdl/rtl/sparc_core/sparc_mul_dp.v
~/s1_core/hdl/rtl/sparc_core/spu_madp.v
~/s1_core/hdl/rtl/sparc_core/lsu_stb_ctl.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_swpla.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_par32.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_cnt6.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluor32.v
~/s1_core/hdl/rtl/sparc_core/bw_r_irf.v
~/s1_core/hdl/rtl/sparc_core/lsu_dcache_lfsr.v
~/s1_core/hdl/rtl/sparc_core/bw_r_scm.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_alulogic.v
~/s1_core/hdl/rtl/sparc_core/lsu_excpctl.v
~/s1_core/hdl/rtl/sparc_core/bw_r_rf16x160.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_imd.v
~/s1_core/hdl/rtl/sparc_core/lsu_rrobin_picker2.v
~/s1_core/hdl/rtl/sparc_core/spu_maexp.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_eccctl.v
~/s1_core/hdl/rtl/sparc_core/bw_clk_cl_sparc_cmp.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_reg.v
~/s1_core/hdl/rtl/sparc_core/sparc_tlu_dec64.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_errdp.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_div_32eql.v
~/s1_core/hdl/rtl/sparc_core/spu_lsurpt.v
~/s1_core/hdl/rtl/sparc_core/tlu_pib.v
~/s1_core/hdl/rtl/sparc_core/lsu_dctl.v
~/s1_core/hdl/rtl/sparc_core/spu_mald.v
~/s1_core/hdl/rtl/sparc_core/spu_maaddr.v
~/s1_core/hdl/rtl/sparc_core/spu_maaeqb.v
~/s1_core/hdl/rtl/sparc_core/bw_r_idct.v
~/s1_core/hdl/rtl/sparc_core/spu_lsurpt1.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_alu_16eql.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_wseldp.v
~/s1_core/hdl/rtl/sparc_core/lsu_qctl2.v
~/s1_core/hdl/rtl/sparc_core/lsu_stb_ctldp.v
~/s1_core/hdl/rtl/sparc_core/test_stub_bist.v
~/s1_core/hdl/rtl/sparc_core/lsu_qctl2.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc.v
~/s1_core/hdl/rtl/sparc_core/lsu_stb_rwctl.v
~/s1_core/hdl/rtl/sparc_core/spu_mamul.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc_dec.v
~/s1_core/hdl/rtl/sparc_core/spu_mast.v
~/s1_core/hdl/rtl/sparc_core/tlu_addern_32.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrcmpl.v
~/s1_core/hdl/rtl/sparc_core/spu_ctl.v
~/s1_core/hdl/rtl/sparc_core/tlu_rrobin_picker.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_divcntl.v
~/s1_core/hdl/rtl/sparc_core/sparc_mul_cntl.v
~/s1_core/hdl/rtl/sparc_core/lsu_dc_parity_gen.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_inc3.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_lfsr5.v
~/s1_core/hdl/rtl/sparc_core/bw_r_frf.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_invctl.v
~/s1_core/hdl/rtl/sparc_core/lsu_dcdp.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_mbist.v
~/s1_core/hdl/rtl/sparc_core/bw_r_rf32x80.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_dcl.v
~/s1_core/hdl/rtl/sparc_core/tlu_pib.v
~/s1_core/hdl/rtl/sparc_core/swrvr_dlib.v
~/s1_core/hdl/rtl/sparc_core/bw_r_irf.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_par16.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog.v
~/s1_core/hdl/rtl/sparc_core/sparc_ffu_dp.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluaddsub.v
~/s1_core/hdl/rtl/sparc_core/tlu_hyperv.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_milfsm.v
~/s1_core/hdl/rtl/sparc_core/spu_wen.v
~/s1_core/hdl/rtl/sparc_core/sparc_tlu_penc64.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_divcntl.v
~/s1_core/hdl/rtl/sparc_core/bw_r_rf32x152b.v
~/s1_core/hdl/rtl/sparc_core/bw_r_rf16x32.v
~/s1_core/hdl/rtl/sparc_core/cpx_spc_rpt.v
~/s1_core/hdl/rtl/sparc_core/swrvr_clib.v
~/s1_core/hdl/rtl/sparc_core/lsu_dctldp.v
~/s1_core/hdl/rtl/sparc_core/bw_r_idct.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_par34.v
~/s1_core/hdl/rtl/sparc_core/lsu_stb_rwdp.v
~/s1_core/hdl/rtl/sparc_core/bw_r_icd.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_ctr5.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluspr.v
~/s1_core/hdl/rtl/sparc_core/spu.v
~/s1_core/hdl/rtl/sparc_core/synchronizer_asr.v
~/s1_core/hdl/rtl/sparc_core/spu_madp.v
~/s1_core/hdl/rtl/sparc_core/sparc_ffu_vis.v
~/s1_core/hdl/rtl/sparc_core/sparc_tlu_intdp.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_ctr5.v
~/s1_core/hdl/rtl/sparc_core/lsu_dcache_lfsr.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_eccctl.v
~/s1_core/hdl/rtl/sparc_core/tlu_tdp.v
~/s1_core/hdl/rtl/sparc_core/lsu_stb_ctl.v
~/s1_core/hdl/rtl/sparc_core/sparc_mul_dp.v
~/s1_core/hdl/rtl/sparc_core/sparc_mul_cntl.v
~/s1_core/hdl/rtl/sparc_core/lsu_qdp2.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_lfsr5.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_alu.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_fcl.v
~/s1_core/hdl/rtl/sparc_core/sparc_ffu_part_add32.v
~/s1_core/hdl/rtl/sparc_core/spu_mast.v
~/s1_core/hdl/rtl/sparc_core/lsu_asi_decode.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_byp_eccgen.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_cwp.v
~/s1_core/hdl/rtl/sparc_core/sparc_ffu.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog_rs1.v
~/s1_core/hdl/rtl/sparc_core/bw_r_irf_register.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_fdp.v
~/s1_core/hdl/rtl/sparc_core/spu_ctl.v
~/s1_core/hdl/rtl/sparc_core/tlu_mmu_dp.v
~/s1_core/hdl/rtl/sparc_core/lsu_tagdp.v
~/s1_core/hdl/rtl/sparc_core/lsu_stb_rwctl.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_rndrob.v
~/s1_core/hdl/rtl/sparc_core/lsu_qctl1.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_errctl.v
~/s1_core/hdl/rtl/sparc_core/tlu_mmu_ctl.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_sscan.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_invctl.v
~/s1_core/hdl/rtl/sparc_core/lsu_pcx_qmon.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_dec.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_rml.v
~/s1_core/hdl/rtl/sparc_core/tlu_rrobin_picker.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc_dec.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_mbist.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_par34.v
~/s1_core/hdl/rtl/sparc_core/cpx_spc_rpt.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_byp.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_errdp.v
~/s1_core/hdl/rtl/sparc_core/spu_maaeqb.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_errctl.v
~/s1_core/hdl/rtl/sparc_core/lsu_dctl.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_cmp35.v
~/s1_core/hdl/rtl/sparc_core/lsu_qdp1.v
~/s1_core/hdl/rtl/sparc_core/test_stub_scan.v
~/s1_core/hdl/rtl/sparc_core/sparc_tlu_zcmp64.v
~/s1_core/hdl/rtl/sparc_core/spu_mamul.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_swl.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_rndrob.v
~/s1_core/hdl/rtl/sparc_core/spu_mared.v
~/s1_core/hdl/rtl/sparc_core/sparc_tlu_intctl.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_fdp.v
~/s1_core/hdl/rtl/sparc_core/tlu_mmu_dp.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_rml.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_fcl.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_dec.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_lru4.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_alu.v
~/s1_core/hdl/rtl/sparc_core/bw_r_icd.v
~/s1_core/hdl/rtl/sparc_core/cluster_header.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_eclcomp7.v
~/s1_core/hdl/rtl/sparc_core/sparc_tlu_intdp.v
~/s1_core/hdl/rtl/sparc_core/tlu_misctl.v
~/s1_core/hdl/rtl/sparc_core/swrvr_clib.v
~/s1_core/hdl/rtl/sparc_core/lsu_tlbdp.v
~/s1_core/hdl/rtl/sparc_core/lsu_dc_parity_gen.v
~/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl.v
~/s1_core/hdl/rtl/sparc_core/tlu_addern_32.v
~/s1_core/hdl/rtl/sparc_core/sparc_ffu.v
~/s1_core/hdl/rtl/sparc_core/tlu_tcl.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_div_yreg.v
~/s1_core/hdl/rtl/sparc_core/tlu.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_eclccr.v
~/s1_core/hdl/rtl/sparc_core/tlu_incr64.v
~/s1_core/hdl/rtl/sparc_core/sparc_tlu_zcmp64.v
~/s1_core/hdl/rtl/sparc_core/lsu_qdp2.v
~/s1_core/hdl/rtl/sparc_core/bw_r_dcd.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_reg.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_milfsm.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_mdqctl.v
~/s1_core/hdl/rtl/sparc_core/test_stub_scan.v
~/s1_core/hdl/rtl/sparc_core/sparc_tlu_intctl.v
~/s1_core/hdl/rtl/sparc_core/tlu_tdp.v
~/s1_core/hdl/rtl/sparc_core/lsu.v
~/s1_core/hdl/rtl/sparc_core/test_stub_bist.v
~/s1_core/hdl/rtl/sparc_core/lsu_qdp1.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_cwp.v
~/s1_core/hdl/rtl/sparc_core/swrvr_dlib.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluzcmp64.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_shft.v
~/s1_core/hdl/rtl/sparc_core/tlu_tcl.v
~/s1_core/hdl/rtl/sparc_core/spu_mactl.v
~/s1_core/hdl/rtl/sparc_core/bw_r_rf32x152b.v
~/s1_core/hdl/rtl/sparc_core/spu_wen.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluor32.v
~/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl.v
~/s1_core/hdl/rtl/sparc_core/sparc_ffu_dp.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluspr.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_imd.v
~/s1_core/hdl/rtl/sparc_core/bw_clk_cl_sparc_cmp.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_swpla.v
~/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl_visctl.v
~/s1_core/hdl/rtl/sparc_core/lsu_tlbdp.v
~/s1_core/hdl/rtl/sparc_core/lsu_rrobin_picker2.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_div.v
~/s1_core/hdl/rtl/sparc_core/sparc_ffu_vis.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_sscan.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu.v
~/s1_core/hdl/rtl/sparc_core/tlu.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_cmp35.v
~/s1_core/hdl/rtl/sparc_core/cmp_sram_redhdr.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_incr46.v
~/s1_core/hdl/rtl/sparc_core/spu_mald.v
~/s1_core/hdl/rtl/sparc_core/bw_r_scm.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_wseldp.v
~/s1_core/hdl/rtl/sparc_core/cpx_spc_buf.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqctl.v
~/s1_core/hdl/rtl/sparc_core/spu.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_rndrob.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqdp.v
~/s1_core/hdl/rtl/sparc_core/tlu_misctl.v
~/s1_core/hdl/rtl/sparc_core/sparc_ffu_part_add32.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_cnt6.v
~/s1_core/hdl/rtl/sparc_core/lsu_tagdp.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrfsm.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluzcmp64.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_div_32eql.v
~/s1_core/hdl/rtl/sparc_core/tlu_hyperv.v
~/s1_core/hdl/rtl/sparc_core/spu_maaddr.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluadder64.v
~/s1_core/hdl/rtl/sparc_core/spu_lsurpt.v
~/s1_core/hdl/rtl/sparc_core/cmp_sram_redhdr.v
~/s1_core/hdl/rtl/sparc_core/lsu.v
~/s1_core/hdl/rtl/sparc_core/spu_maexp.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_swl.v
~/s1_core/hdl/rtl/sparc_core/sparc_mul_top.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_alu_16eql.v
~/s1_core/hdl/rtl/sparc_core/mul64.v
~/s1_core/hdl/rtl/sparc_core/lsu_dcdp.v
~/s1_core/hdl/rtl/sparc_core/sparc.v
~/s1_core/hdl/rtl/sparc_core/lsu_qctl1.v
~/s1_core/hdl/rtl/sparc_core/lsu_excpctl.v
~/s1_core/hdl/rtl/sparc_core/bw_r_rf16x160.v
~/s1_core/hdl/rtl/sparc_core/spu_lsurpt1.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_byp_eccgen.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_inc3.v
~/s1_core/hdl/rtl/sparc_core/cluster_header.v
~/s1_core/hdl/rtl/sparc_core/bw_r_dcd.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_wb.v
~/s1_core/hdl/rtl/sparc_core/bw_r_tlb.v
~/s1_core/hdl/rtl/sparc_core/sparc_tlu_penc64.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrcmpl.v
~/s1_core/hdl/rtl/sparc_core/tlu_prencoder16.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_eclcomp7.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluaddsub.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_wb.v
~/s1_core/hdl/rtl/sparc_core/sparc_exu_alulogic.v
~/s1_core/hdl/rtl/sparc_core/sparc_tlu_dec64.v
~/s1_core/hdl/rtl/sparc_core/mul64.v
~/s1_core/hdl/rtl/sparc_core/spu_mactl.v
~/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqdp.v
~/s1_core/hdl/rtl/s1_top/rst_ctrl.v
~/s1_core/hdl/rtl/s1_top/int_ctrl.v
~/s1_core/hdl/rtl/s1_top/spc2wbm.v
/trunk/hdl/filelist.xst
1,149 → 1,149
verilog work ~/s1_core/hdl/behav/sparc_libs/u1_lib.v
verilog work ~/s1_core/hdl/behav/sparc_libs/m1_lib.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_dcl.v
verilog work ~/s1_core/hdl/rtl/sparc_core/bw_r_frf.v
verilog work ~/s1_core/hdl/rtl/sparc_core/lsu_dctldp.v
verilog work ~/s1_core/hdl/rtl/sparc_core/spu_mared.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrfsm.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_mdqctl.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog_rs1.v
verilog work ~/s1_core/hdl/rtl/sparc_core/tlu_incr64.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl_visctl.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_div.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluadder64.v
verilog work ~/s1_core/hdl/rtl/sparc_core/bw_r_irf_register.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_mul_top.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_lru4.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc.v
verilog work ~/s1_core/hdl/rtl/sparc_core/lsu_stb_rwdp.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_mul_dp.v
verilog work ~/s1_core/hdl/rtl/sparc_core/spu_madp.v
verilog work ~/s1_core/hdl/rtl/sparc_core/lsu_stb_ctl.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_swpla.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_par32.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_cnt6.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluor32.v
verilog work ~/s1_core/hdl/rtl/sparc_core/bw_r_irf.v
verilog work ~/s1_core/hdl/rtl/sparc_core/lsu_dcache_lfsr.v
verilog work ~/s1_core/hdl/rtl/sparc_core/bw_r_scm.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_alulogic.v
verilog work ~/s1_core/hdl/rtl/sparc_core/lsu_excpctl.v
verilog work ~/s1_core/hdl/rtl/sparc_core/bw_r_rf16x160.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_imd.v
verilog work ~/s1_core/hdl/rtl/sparc_core/lsu_rrobin_picker2.v
verilog work ~/s1_core/hdl/rtl/sparc_core/spu_maexp.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_eccctl.v
verilog work ~/s1_core/hdl/rtl/sparc_core/bw_clk_cl_sparc_cmp.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_reg.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_tlu_dec64.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_errdp.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_div_32eql.v
verilog work ~/s1_core/hdl/rtl/sparc_core/spu_lsurpt.v
verilog work ~/s1_core/hdl/rtl/sparc_core/tlu_pib.v
verilog work ~/s1_core/hdl/rtl/sparc_core/lsu_dctl.v
verilog work ~/s1_core/hdl/rtl/sparc_core/spu_mald.v
verilog work ~/s1_core/hdl/rtl/sparc_core/spu_maaddr.v
verilog work ~/s1_core/hdl/rtl/sparc_core/spu_maaeqb.v
verilog work ~/s1_core/hdl/rtl/sparc_core/bw_r_idct.v
verilog work ~/s1_core/hdl/rtl/sparc_core/spu_lsurpt1.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_alu_16eql.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_wseldp.v
verilog work ~/s1_core/hdl/rtl/sparc_core/lsu_qctl2.v
verilog work ~/s1_core/hdl/rtl/sparc_core/lsu_stb_ctldp.v
verilog work ~/s1_core/hdl/rtl/sparc_core/test_stub_bist.v
verilog work ~/s1_core/hdl/rtl/sparc_core/lsu_qctl2.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc.v
verilog work ~/s1_core/hdl/rtl/sparc_core/lsu_stb_rwctl.v
verilog work ~/s1_core/hdl/rtl/sparc_core/spu_mamul.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc_dec.v
verilog work ~/s1_core/hdl/rtl/sparc_core/spu_mast.v
verilog work ~/s1_core/hdl/rtl/sparc_core/tlu_addern_32.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrcmpl.v
verilog work ~/s1_core/hdl/rtl/sparc_core/spu_ctl.v
verilog work ~/s1_core/hdl/rtl/sparc_core/tlu_rrobin_picker.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_divcntl.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_mul_cntl.v
verilog work ~/s1_core/hdl/rtl/sparc_core/lsu_dc_parity_gen.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_inc3.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_lfsr5.v
verilog work ~/s1_core/hdl/rtl/sparc_core/bw_r_frf.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_invctl.v
verilog work ~/s1_core/hdl/rtl/sparc_core/lsu_dcdp.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_mbist.v
verilog work ~/s1_core/hdl/rtl/sparc_core/bw_r_rf32x80.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_dcl.v
verilog work ~/s1_core/hdl/rtl/sparc_core/tlu_pib.v
verilog work ~/s1_core/hdl/rtl/sparc_core/swrvr_dlib.v
verilog work ~/s1_core/hdl/rtl/sparc_core/bw_r_irf.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_par16.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ffu_dp.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluaddsub.v
verilog work ~/s1_core/hdl/rtl/sparc_core/tlu_hyperv.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_milfsm.v
verilog work ~/s1_core/hdl/rtl/sparc_core/spu_wen.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_tlu_penc64.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_divcntl.v
verilog work ~/s1_core/hdl/rtl/sparc_core/bw_r_rf32x152b.v
verilog work ~/s1_core/hdl/rtl/sparc_core/bw_r_rf16x32.v
verilog work ~/s1_core/hdl/rtl/sparc_core/cpx_spc_rpt.v
verilog work ~/s1_core/hdl/rtl/sparc_core/swrvr_clib.v
verilog work ~/s1_core/hdl/rtl/sparc_core/lsu_dctldp.v
verilog work ~/s1_core/hdl/rtl/sparc_core/bw_r_idct.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_par34.v
verilog work ~/s1_core/hdl/rtl/sparc_core/lsu_stb_rwdp.v
verilog work ~/s1_core/hdl/rtl/sparc_core/bw_r_icd.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_ctr5.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluspr.v
verilog work ~/s1_core/hdl/rtl/sparc_core/spu.v
verilog work ~/s1_core/hdl/rtl/sparc_core/synchronizer_asr.v
verilog work ~/s1_core/hdl/rtl/sparc_core/spu_madp.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ffu_vis.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_tlu_intdp.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_ctr5.v
verilog work ~/s1_core/hdl/rtl/sparc_core/lsu_dcache_lfsr.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_eccctl.v
verilog work ~/s1_core/hdl/rtl/sparc_core/tlu_tdp.v
verilog work ~/s1_core/hdl/rtl/sparc_core/lsu_stb_ctl.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_mul_dp.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_mul_cntl.v
verilog work ~/s1_core/hdl/rtl/sparc_core/lsu_qdp2.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_lfsr5.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_alu.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_fcl.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ffu_part_add32.v
verilog work ~/s1_core/hdl/rtl/sparc_core/spu_mast.v
verilog work ~/s1_core/hdl/rtl/sparc_core/lsu_asi_decode.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_byp_eccgen.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_cwp.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ffu.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog_rs1.v
verilog work ~/s1_core/hdl/rtl/sparc_core/bw_r_irf_register.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_fdp.v
verilog work ~/s1_core/hdl/rtl/sparc_core/spu_ctl.v
verilog work ~/s1_core/hdl/rtl/sparc_core/tlu_mmu_dp.v
verilog work ~/s1_core/hdl/rtl/sparc_core/lsu_tagdp.v
verilog work ~/s1_core/hdl/rtl/sparc_core/lsu_stb_rwctl.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_rndrob.v
verilog work ~/s1_core/hdl/rtl/sparc_core/lsu_qctl1.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_errctl.v
verilog work ~/s1_core/hdl/rtl/sparc_core/tlu_mmu_ctl.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_sscan.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_invctl.v
verilog work ~/s1_core/hdl/rtl/sparc_core/lsu_pcx_qmon.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_dec.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_rml.v
verilog work ~/s1_core/hdl/rtl/sparc_core/tlu_rrobin_picker.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc_dec.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_mbist.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_par34.v
verilog work ~/s1_core/hdl/rtl/sparc_core/cpx_spc_rpt.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_byp.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_errdp.v
verilog work ~/s1_core/hdl/rtl/sparc_core/spu_maaeqb.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_errctl.v
verilog work ~/s1_core/hdl/rtl/sparc_core/lsu_dctl.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_cmp35.v
verilog work ~/s1_core/hdl/rtl/sparc_core/lsu_qdp1.v
verilog work ~/s1_core/hdl/rtl/sparc_core/test_stub_scan.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_tlu_zcmp64.v
verilog work ~/s1_core/hdl/rtl/sparc_core/spu_mamul.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_swl.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_rndrob.v
verilog work ~/s1_core/hdl/rtl/sparc_core/spu_mared.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_tlu_intctl.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_fdp.v
verilog work ~/s1_core/hdl/rtl/sparc_core/tlu_mmu_dp.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_rml.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_fcl.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_dec.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_lru4.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_alu.v
verilog work ~/s1_core/hdl/rtl/sparc_core/bw_r_icd.v
verilog work ~/s1_core/hdl/rtl/sparc_core/cluster_header.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_eclcomp7.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_tlu_intdp.v
verilog work ~/s1_core/hdl/rtl/sparc_core/tlu_misctl.v
verilog work ~/s1_core/hdl/rtl/sparc_core/swrvr_clib.v
verilog work ~/s1_core/hdl/rtl/sparc_core/lsu_tlbdp.v
verilog work ~/s1_core/hdl/rtl/sparc_core/lsu_dc_parity_gen.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl.v
verilog work ~/s1_core/hdl/rtl/sparc_core/tlu_addern_32.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ffu.v
verilog work ~/s1_core/hdl/rtl/sparc_core/tlu_tcl.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_div_yreg.v
verilog work ~/s1_core/hdl/rtl/sparc_core/tlu.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_eclccr.v
verilog work ~/s1_core/hdl/rtl/sparc_core/tlu_incr64.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_tlu_zcmp64.v
verilog work ~/s1_core/hdl/rtl/sparc_core/lsu_qdp2.v
verilog work ~/s1_core/hdl/rtl/sparc_core/bw_r_dcd.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_reg.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_milfsm.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_mdqctl.v
verilog work ~/s1_core/hdl/rtl/sparc_core/test_stub_scan.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_tlu_intctl.v
verilog work ~/s1_core/hdl/rtl/sparc_core/tlu_tdp.v
verilog work ~/s1_core/hdl/rtl/sparc_core/lsu.v
verilog work ~/s1_core/hdl/rtl/sparc_core/test_stub_bist.v
verilog work ~/s1_core/hdl/rtl/sparc_core/lsu_qdp1.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_cwp.v
verilog work ~/s1_core/hdl/rtl/sparc_core/swrvr_dlib.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluzcmp64.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_shft.v
verilog work ~/s1_core/hdl/rtl/sparc_core/tlu_tcl.v
verilog work ~/s1_core/hdl/rtl/sparc_core/spu_mactl.v
verilog work ~/s1_core/hdl/rtl/sparc_core/bw_r_rf32x152b.v
verilog work ~/s1_core/hdl/rtl/sparc_core/spu_wen.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluor32.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ffu_dp.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluspr.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_imd.v
verilog work ~/s1_core/hdl/rtl/sparc_core/bw_clk_cl_sparc_cmp.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_swpla.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl_visctl.v
verilog work ~/s1_core/hdl/rtl/sparc_core/lsu_tlbdp.v
verilog work ~/s1_core/hdl/rtl/sparc_core/lsu_rrobin_picker2.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_div.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ffu_vis.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_sscan.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu.v
verilog work ~/s1_core/hdl/rtl/sparc_core/tlu.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_cmp35.v
verilog work ~/s1_core/hdl/rtl/sparc_core/cmp_sram_redhdr.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_incr46.v
verilog work ~/s1_core/hdl/rtl/sparc_core/spu_mald.v
verilog work ~/s1_core/hdl/rtl/sparc_core/bw_r_scm.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_wseldp.v
verilog work ~/s1_core/hdl/rtl/sparc_core/cpx_spc_buf.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqctl.v
verilog work ~/s1_core/hdl/rtl/sparc_core/spu.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_rndrob.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqdp.v
verilog work ~/s1_core/hdl/rtl/sparc_core/tlu_misctl.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ffu_part_add32.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_cnt6.v
verilog work ~/s1_core/hdl/rtl/sparc_core/lsu_tagdp.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrfsm.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluzcmp64.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_div_32eql.v
verilog work ~/s1_core/hdl/rtl/sparc_core/tlu_hyperv.v
verilog work ~/s1_core/hdl/rtl/sparc_core/spu_maaddr.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluadder64.v
verilog work ~/s1_core/hdl/rtl/sparc_core/spu_lsurpt.v
verilog work ~/s1_core/hdl/rtl/sparc_core/cmp_sram_redhdr.v
verilog work ~/s1_core/hdl/rtl/sparc_core/lsu.v
verilog work ~/s1_core/hdl/rtl/sparc_core/spu_maexp.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_swl.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_mul_top.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_alu_16eql.v
verilog work ~/s1_core/hdl/rtl/sparc_core/mul64.v
verilog work ~/s1_core/hdl/rtl/sparc_core/lsu_dcdp.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc.v
verilog work ~/s1_core/hdl/rtl/sparc_core/lsu_qctl1.v
verilog work ~/s1_core/hdl/rtl/sparc_core/lsu_excpctl.v
verilog work ~/s1_core/hdl/rtl/sparc_core/bw_r_rf16x160.v
verilog work ~/s1_core/hdl/rtl/sparc_core/spu_lsurpt1.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_byp_eccgen.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_inc3.v
verilog work ~/s1_core/hdl/rtl/sparc_core/cluster_header.v
verilog work ~/s1_core/hdl/rtl/sparc_core/bw_r_dcd.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_wb.v
verilog work ~/s1_core/hdl/rtl/sparc_core/bw_r_tlb.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_tlu_penc64.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrcmpl.v
verilog work ~/s1_core/hdl/rtl/sparc_core/tlu_prencoder16.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_eclcomp7.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluaddsub.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_wb.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_exu_alulogic.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_tlu_dec64.v
verilog work ~/s1_core/hdl/rtl/sparc_core/mul64.v
verilog work ~/s1_core/hdl/rtl/sparc_core/spu_mactl.v
verilog work ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqdp.v
verilog work ~/s1_core/hdl/rtl/s1_top/rst_ctrl.v
verilog work ~/s1_core/hdl/rtl/s1_top/int_ctrl.v
verilog work ~/s1_core/hdl/rtl/s1_top/spc2wbm.v

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