URL
https://opencores.org/ocsvn/10_100m_ethernet-fifo_convertor/10_100m_ethernet-fifo_convertor/trunk
Subversion Repositories 10_100m_ethernet-fifo_convertor
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/10_100m_ethernet-fifo_convertor
- from Rev 4 to Rev 5
- ↔ Reverse comparison
Rev 4 → Rev 5
/trunk/rtl/verilog/CRC_Module.v
1,4 → 1,4
module CRC_Module(Clk, Reset, Data, Enable, Initialize, Crc, CrcError); |
module CRC_Module(Clk, Reset, Data, Enable, Initialize, Crc, CrcError); |
|
input Clk; |
input Reset; |
/trunk/rtl/verilog/tri_state.v
1,3 → 1,7
//author :gurenliang |
//Email: gurenliang@gmail.com |
//note: if there are some errors, you are welcome to contact me. It would be the best appreciation to me. |
|
module tri_state(d_in, d_out, out_en, ioport); |
input d_out, out_en; //init_clk should be 10KHz |
output d_in; |
/trunk/rtl/verilog/RxModule.v
1,17 → 1,34
//author :gurenliang |
//Email: gurenliang@gmail.com |
//note: if there are some errors, you are welcome to contact me. It would be the best appreciation to me. |
|
////Next task: make the feedback to PC showing need data. |
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//version 0.3, changed the changes made by version 0.2 back |
//version 0.2, set empty when ff_data_buf_index's less significant bits is 3'b111 or 3'b000 |
`include "common.v" |
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`define eth_buf_len 1416 //1416=8*(8+6+6+2+3+148+4) |
`define nibble_cnt_step 9'h001 |
`define MAC_ADD 48'h0100_0000_0000 //mac address: 0x00-00-00-00-00-01 |
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module RxModule(phy_rxd, phy_rxen, phy_rxclk, phy_rxer, |
ff_clk, ff_data, ff_en, frameid, empty, start); |
ff_clk, ff_data, ff_en, |
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`ifdef frameIDfromRx |
frameid, |
`endif |
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empty, start); |
input phy_rxen, phy_rxclk, phy_rxer; //MII interface |
input [3:0] phy_rxd; |
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input ff_clk; //270.8333KHz |
output ff_data, ff_en; |
output[23:0] frameid; |
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`ifdef frameIDfromRx |
output[23:0] frameid; |
`endif |
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output empty, start; //to tell TxModule that buf in RxModule needs data |
reg ff_data; |
reg ff_en; |
24,7 → 41,9
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reg[8:0] nibble_cnt=9'h00; |
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reg[23:0] frameidt[0:1]; |
`ifdef frameIDfromRx |
reg[23:0] frameidt[0:1]; |
`endif |
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reg start=1'b0; |
reg start_intra=1'b0; |
42,7 → 61,11
end |
else if ((nibble_cnt == 9'd354 ) & ((eth_buf[111:64] ^ `MAC_ADD)==48'h0)) begin |
//one frame has been transfered over, the destinate address is right and then been put into the buffer |
frameidt[toggle[3]] <= eth_buf[199:176]; |
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`ifdef frameIDfromRx |
frameidt[toggle[3]] <= eth_buf[199:176]; |
`endif |
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ff_data_buf[toggle ] <= eth_buf[347:200]; |
ff_data_buf[toggle+4'h1] <= eth_buf[495:348]; |
ff_data_buf[toggle+4'h2] <= eth_buf[643:496]; |
58,11 → 81,14
nibble_cnt <= 9'h000; |
end |
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assign empty = ((ff_data_buf_index[2:0]==3'b111)|(ff_data_buf_index[2:0]==3'b000)); |
assign empty = ((ff_data_buf_index[2:0]==3'b011)|(ff_data_buf_index[2:0]==3'b100)); |
//every four 148bit, generate an empty signal to the TxModule |
assign toggle = {~ff_data_buf_index[3],3'h0}; //indicate which half buffer is available |
assign frameid = frameidt[ff_data_buf_index[3]];// |
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`ifdef frameIDfromRx |
assign frameid = frameidt[ff_data_buf_index[3]];// |
`endif |
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always@(negedge ff_clk) //flow the data out of the buffer |
if(start_intra==1'b0) begin //wait the first frame to come |
ff_state <= transfer; |
/trunk/rtl/verilog/TxModule.v
1,4 → 1,17
//author :gurenliang |
//Email: gurenliang@gmail.com |
//note: if there are some errors, you are welcome to contact me. It would be the best appreciation to me. |
|
|
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//Next step, add ff_data control to show the IP is busy |
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//version 0.3, declared a new variable data_av, and use it to start sending frame. |
//version 0.3, delete the usage of pre_buf, and rename the pre to preaddlt |
//version 0.3, add the option of frameID mode, by include common.v and judge the macro-varible frameIDfromRx |
//This module is used to receive data from the demodulate module and send the data to the Ethernet PHY chip |
`include "common.v" |
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`define tx_data_buf_len 649 //3*8+156.25*4 |
`define tx_data_len 656 //make the length of tx_data_buf be conformed to IEEE802.3 |
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7,11 → 20,21
`define ff_cnt_step 11'h1 |
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module TxModule(reset, phy_txd, phy_txen, phy_txclk, phy_txer, |
ff_clk, ff_en, ff_data, frameid, empty, start, |
ff_clk, ff_en, ff_data, |
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`ifdef frameIDfromRx |
frameid, |
`endif |
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empty, start, |
test1, test2, test3, test4); |
input phy_txclk, reset; |
input ff_clk, ff_en, ff_data; //ff_clk should be 207.83333KHz |
input[23:0] frameid; //get the frameid information from RxModule |
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`ifdef frameIDfromRx |
input[23:0] frameid; //get the frameid information from RxModule |
`endif |
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input empty, start; //decide whether should give out the "need-data" ethernet package |
output [3:0] phy_txd; //MII |
output phy_txen, phy_txer; |
19,17 → 42,16
output test1, test2, test3, test4; |
reg test1;//, test2, test3, test4; |
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`ifdef frameIDcount |
reg[23:0] frameid=24'h00_00_00; |
`endif |
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reg[3:0] phy_txd; |
reg phy_txen; |
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reg[175:0] pre; |
reg[175:0] preaddlt; |
//reg[175:0] pre_buf=176'h0008_5952_264C_5247_FFFF_FFFF_FFFF_D555_5555_5555_5555; |
reg[159:0] pre_buf=159'h0100_0000_0000_FFFF_FFFF_FFFF_D555_5555_5555_5555; |
//already stored MAC preamble, destination address and source address from right to left respectively. |
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//reg[223:0] temp_buf=224'h0186_15ac_0000_0000_0000_be86_15ac_88fe_467d_2300_0100_0406_0008_0100; |
//reg[223:0] temp_buf=224'h0000_0000_0000_0000_0000_0000_0000_0000_467d_2300_0100_0a30_0008_0100; |
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reg[`tx_data_buf_len-1:0] tx_data_buf[0:1]; //two buffer helps to step over different frame seamlessly |
reg pre_toggle, toggle=1'b0; //helps to decide when to give PC a MAC frame |
reg[`tx_data_len-1:0] tx_data; //used as FIFO |
65,7 → 87,10
//tx_data_buf[toggle] <= {144'h0,temp_buf}; |
ff_cnt <= 0; |
toggle <= ~toggle; |
//tosend <= 1'b1; |
//every time a frame being sent, frameID increases one |
`ifdef frameIDcount |
frameid <= frameid + 24'h00_00_01; |
`endif |
end |
else begin |
tx_data_buf[toggle] <= {ff_data, tx_data_buf[toggle][`tx_data_buf_len-1:1]}; |
72,14 → 97,6
ff_cnt <= ff_cnt + `ff_cnt_step; |
end |
end |
//else if(ff_cnt != 0) begin |
// tx_data_buf[toggle] <= {(tx_data_buf[toggle][`MAXLEN-1:8]>>(`DATALEN-ff_cnt)),2'b00 ,ff_cnt[8:3]}; |
//tx_data_buf[toggle] <= {144'h0,temp_buf}; |
// ff_cnt <= 0; |
// toggle <= ~toggle; |
//tosend <= 1'b1; |
//end |
//else tosend <=1'b0; |
end |
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assign phy_txer = 1'b0; |
89,11 → 106,14
if (reset) |
state <= s_idle; |
else begin |
if(pre_toggle ^ toggle) data_av<=1'b1; |
case (state) |
s_idle: begin //wait to be trigged |
test1 <= ~test1; |
if(pre_toggle ^ toggle) //once be trigged, prepare the data to send |
if(data_av) begin //once be trigged, prepare the data to send |
state <= s_pre; |
data_av <= 1'b0; |
end |
else state <= s_idle; |
end |
|
147,13 → 167,15
case (state) |
s_idle: begin |
tx_data <= {7'h0,tx_data_buf[~toggle]}; |
if(empty) pre <= {16'h0008,pre_buf}; //decide whether should ask PC for new packages |
else pre <= {16'h0000, pre_buf}; |
//already stored MAC preamble, dest address and source address from right to left. |
//decide whether should ask PC for new frame |
if(empty) preaddlt <= {16'h0008, `MAC_ADD, `PC_MAC_ADD, `Preamble}; |
else preaddlt <= {16'h0000, `MAC_ADD, `PC_MAC_ADD, `Preamble}; |
end |
s_pre: |
{pre[171:0], phy_txd} <= pre; |
{preaddlt[171:0], phy_txd} <= preaddlt; |
s_add: |
{pre[171:0], phy_txd} <= pre; |
{preaddlt[171:0], phy_txd} <= preaddlt; |
s_data: |
{tx_data[`tx_data_len-5:0],phy_txd} <= tx_data; |
s_crc: begin |
/trunk/rtl/verilog/EthernetModule.v
1,4 → 1,13
//author :gurenliang |
//Email: gurenliang@gmail.com |
//note: if there are some errors, you are welcome to contact me. It would be the best appreciation to me. |
|
|
//version 0.3 correct some minor errors |
//version 0.3 add the option of frameID mode, by include common.v and judge the macro-varible frameIDfromRx |
//The top layer module provided full functions |
`include "common.v" |
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module EthernetModule(reset, clk_10K, |
ff_clk, ff_en_source, ff_en_sink, ff_data_source, ff_data_sink, //ff_clk should be a 270.33KHz clock |
phy_rxd, phy_rxen, phy_rxclk, phy_rxer, |
24,31 → 33,37
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//wire ff_en, ff_data, |
wire out_en; |
wire txclk_in, rxclk_in, rxen_in, txclk_in_t; |
wire[23:0] frameid; //share the frameid between TxModule and RxModule |
wire rxen_in, txclk_in; |
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`ifdef frameIDfromRx |
wire[23:0] frameid; //share the frameid between TxModule and RxModule |
`endif |
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wire empty, start; |
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InitModule initModule_inst(.init_clk(clk_10K), .reset(reset), .phy_reset(phy_reset), .out_en(out_en)); |
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tri_state tri_state_inst1(.d_in(txclk_in_t), .d_out(1'b0), .out_en(out_en), .ioport(phy_txclk)); |
tri_state tri_state_inst2(.d_in(), .d_out(1'b0), .out_en(out_en), .ioport(phy_col)); |
tri_state tri_state_inst3(.d_in(rxen_in), .d_out(1'b0), .out_en(out_en), .ioport(phy_rxen)); |
tri_state tri_state_inst4(.d_in(), .d_out(1'b0), .out_en(out_en), .ioport(phy_linksts)); |
tri_state tri_state_inst5(.d_in(), .d_out(1'b1), .out_en(out_en), .ioport(phy_crs)); |
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//make the two 25MHz clk as global clocks |
clkctrl clkctrl_txclk (.inclk (txclk_in_t), .outclk (txclk_in)); |
clkctrl clkctrl_rxclk (.inclk (phy_rxclk), .outclk (rxclk_in)); |
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tri_state tri_state_inst1(.d_in(txclk_in ), .d_out(1'b0), .out_en(out_en), .ioport(phy_txclk)); |
tri_state tri_state_inst2(.d_in( ), .d_out(1'b0), .out_en(out_en), .ioport(phy_col)); |
tri_state tri_state_inst3(.d_in(rxen_in ), .d_out(1'b0), .out_en(out_en), .ioport(phy_rxen)); |
tri_state tri_state_inst4(.d_in( ), .d_out(1'b0), .out_en(out_en), .ioport(phy_linksts)); |
tri_state tri_state_inst5(.d_in( ), .d_out(1'b1), .out_en(out_en), .ioport(phy_crs)); |
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TxModule TxModule_inst(.reset(out_en), |
.phy_txd(phy_txd), .phy_txen(phy_txen), .phy_txclk(txclk_in), .phy_txer(phy_txer), |
.ff_clk(ff_clk), .ff_en(ff_en_sink), .ff_data(ff_data_sink), |
.frameid(frameid), .empty(empty), .start(start), |
`ifdef frameIDfromRx |
.frameid(frameid), |
`endif |
.empty(empty), .start(start), |
.test1(test1), .test2(test2), .test3(test3), .test4(test4)); |
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RxModule RxModule_inst(.phy_rxd(phy_rxd), .phy_rxen(rxen_in), .phy_rxclk(rxclk_in), .phy_rxer(phy_rxer), |
RxModule RxModule_inst(.phy_rxd(phy_rxd), .phy_rxen(rxen_in), .phy_rxclk(phy_rxclk), .phy_rxer(phy_rxer), |
.ff_clk(ff_clk), .ff_data(ff_data_source), .ff_en(ff_en_source), |
.frameid(frameid), .empty(empty), .start(start)); |
`ifdef frameIDfromRx |
.frameid(frameid), |
`endif |
.empty(empty), .start(start)); |
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//assign test1 = ff_en; |
//assign test2 = ff_data; |
/trunk/rtl/verilog/InitModule.v
1,3 → 1,7
//author :gurenliang |
//Email: gurenliang@gmail.com |
//note: if there are some errors, you are welcome to contact me. It would be the best appreciation to me. |
|
//This module incharge of the generation of the reset signal for PHY chip |
//and hold low for at least 10ms. |
module InitModule(init_clk, reset, phy_reset, out_en); |
/trunk/doc/10_100M_Ethernet-FIFO_Convertor.doc
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trunk/doc/10_100M_Ethernet-FIFO_Convertor.doc
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