URL
https://opencores.org/ocsvn/1g_ethernet_dpi/1g_ethernet_dpi/trunk
Subversion Repositories 1g_ethernet_dpi
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Rev 3 → Rev 4
/trunk/hw/layout/bd/base_microblaze_design.bd
0,0 → 1,3395
<?xml version="1.0" encoding="UTF-8" standalone="no" ?> |
<bd:repository xmlns:bd="http://www.xilinx.com/bd" bd:synthFlowMode="None" bd:tool_version="2015.4" bd:top="base_microblaze_design" bd:version="1.00.a"> |
|
<spirit:component xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> |
<spirit:vendor>xilinx.com</spirit:vendor> |
<spirit:library>BlockDiagram</spirit:library> |
<spirit:name>base_microblaze_design</spirit:name> |
<spirit:version>1.00.a</spirit:version> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>isTop</spirit:name> |
<spirit:value spirit:format="bool" spirit:resolve="immediate">true</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
<spirit:busInterfaces> |
<spirit:busInterface> |
<spirit:name>led_8bits</spirit:name> |
<spirit:master/> |
<spirit:busType spirit:library="interface" spirit:name="gpio" spirit:vendor="xilinx.com" spirit:version="1.0"/> |
<spirit:abstractionType spirit:library="interface" spirit:name="gpio_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/> |
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<spirit:busInterface> |
<spirit:name>rs232_uart</spirit:name> |
<spirit:master/> |
<spirit:busType spirit:library="interface" spirit:name="uart" spirit:vendor="xilinx.com" spirit:version="1.0"/> |
<spirit:abstractionType spirit:library="interface" spirit:name="uart_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/> |
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<spirit:busInterface> |
<spirit:name>tmemac_1</spirit:name> |
<spirit:master/> |
<spirit:busType spirit:library="user" spirit:name="tmemac" spirit:vendor="user-v" spirit:version="1.0"/> |
<spirit:abstractionType spirit:library="user" spirit:name="tmemac_rtl" spirit:vendor="user-v" spirit:version="1.0"/> |
</spirit:busInterface> |
<spirit:busInterface> |
<spirit:name>CLK.CLK</spirit:name> |
<spirit:displayName>Clk</spirit:displayName> |
<spirit:description>Clock</spirit:description> |
<spirit:busType spirit:library="signal" spirit:name="clock" spirit:vendor="xilinx.com" spirit:version="1.0"/> |
<spirit:abstractionType spirit:library="signal" spirit:name="clock_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/> |
<spirit:slave/> |
<spirit:portMaps> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>CLK</spirit:name> |
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<spirit:physicalPort> |
<spirit:name>Clk</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
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<spirit:parameter> |
<spirit:name>FREQ_HZ</spirit:name> |
<spirit:value>100000000</spirit:value> |
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<spirit:parameter> |
<spirit:name>ASSOCIATED_RESET</spirit:name> |
<spirit:value>reset</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:busInterface> |
<spirit:busInterface> |
<spirit:name>RST.RESET</spirit:name> |
<spirit:displayName>Reset</spirit:displayName> |
<spirit:description>Reset</spirit:description> |
<spirit:busType spirit:library="signal" spirit:name="reset" spirit:vendor="xilinx.com" spirit:version="1.0"/> |
<spirit:abstractionType spirit:library="signal" spirit:name="reset_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/> |
<spirit:slave/> |
<spirit:portMaps> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>RST</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>reset</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
</spirit:portMaps> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>POLARITY</spirit:name> |
<spirit:value>ACTIVE_HIGH</spirit:value> |
</spirit:parameter> |
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<spirit:name>BlockDiagram</spirit:name> |
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<spirit:port> |
<spirit:name>Clk</spirit:name> |
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</spirit:port> |
<spirit:port> |
<spirit:name>reset</spirit:name> |
<spirit:wire> |
<spirit:direction>in</spirit:direction> |
</spirit:wire> |
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|
<spirit:design xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> |
<spirit:vendor>xilinx.com</spirit:vendor> |
<spirit:library>BlockDiagram</spirit:library> |
<spirit:name>base_microblaze_design_imp</spirit:name> |
<spirit:version>1.00.a</spirit:version> |
<spirit:componentInstances> |
<spirit:componentInstance> |
<spirit:instanceName>axi_gpio_0</spirit:instanceName> |
<spirit:componentRef spirit:library="ip" spirit:name="axi_gpio" spirit:vendor="xilinx.com" spirit:version="2.0"/> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="bd:xciName">base_microblaze_design_axi_gpio_0_0</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="USE_BOARD_FLOW">true</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="GPIO_BOARD_INTERFACE">led_8bits</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
<spirit:componentInstance> |
<spirit:instanceName>axi_uartlite_0</spirit:instanceName> |
<spirit:componentRef spirit:library="ip" spirit:name="axi_uartlite" spirit:vendor="xilinx.com" spirit:version="2.0"/> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="bd:xciName">base_microblaze_design_axi_uartlite_0_0</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="C_BAUDRATE">115200</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="USE_BOARD_FLOW">true</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="UARTLITE_BOARD_INTERFACE">rs232_uart</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
<spirit:componentInstance> |
<spirit:instanceName>tri_mode_emac_0</spirit:instanceName> |
<spirit:componentRef spirit:library="user" spirit:name="tri_mode_emac" spirit:vendor="user-org" spirit:version="1.0"/> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="bd:xciName">base_microblaze_design_tri_mode_emac_0_0</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
<spirit:componentInstance> |
<spirit:instanceName>microblaze_0</spirit:instanceName> |
<spirit:componentRef spirit:library="ip" spirit:name="microblaze" spirit:vendor="xilinx.com" spirit:version="9.5"/> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="bd:xciName">base_microblaze_design_microblaze_0_0</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="C_D_AXI">1</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="C_D_LMB">1</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="C_I_LMB">1</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="C_USE_PCMP_INSTR">1</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="C_USE_BARREL">1</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="C_USE_DIV">1</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="C_USE_HW_MUL">1</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="C_USE_FPU">1</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="C_DEBUG_ENABLED">1</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
<spirit:componentInstance> |
<spirit:instanceName>microblaze_0_local_memory</spirit:instanceName> |
<spirit:componentRef spirit:library="BlockDiagram/base_microblaze_design_imp" spirit:name="microblaze_0_local_memory" spirit:vendor="xilinx.com" spirit:version="1.00.a"/> |
</spirit:componentInstance> |
<spirit:componentInstance> |
<spirit:instanceName>mdm_1</spirit:instanceName> |
<spirit:componentRef spirit:library="ip" spirit:name="mdm" spirit:vendor="xilinx.com" spirit:version="3.2"/> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="bd:xciName">base_microblaze_design_mdm_1_0</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
<spirit:componentInstance> |
<spirit:instanceName>rst_Clk_100M</spirit:instanceName> |
<spirit:componentRef spirit:library="ip" spirit:name="proc_sys_reset" spirit:vendor="xilinx.com" spirit:version="5.0"/> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="bd:xciName">base_microblaze_design_rst_Clk_100M_0</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
<spirit:componentInstance> |
<spirit:instanceName>microblaze_0_axi_periph</spirit:instanceName> |
<spirit:componentRef spirit:library="BlockDiagram/base_microblaze_design_imp" spirit:name="microblaze_0_axi_periph" spirit:vendor="xilinx.com" spirit:version="1.00.a"/> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="bd:xciName">base_microblaze_design_microblaze_0_axi_periph_0</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="NUM_SI">3</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="NUM_MI">6</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="appcore">xilinx.com:ip:axi_interconnect:2.1</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
<spirit:componentInstance> |
<spirit:instanceName>axi_dma_0</spirit:instanceName> |
<spirit:componentRef spirit:library="ip" spirit:name="axi_dma" spirit:vendor="xilinx.com" spirit:version="7.1"/> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="bd:xciName">base_microblaze_design_axi_dma_0_0</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="c_include_sg">0</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="c_include_mm2s">1</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="c_m_axis_mm2s_tdata_width">8</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
<spirit:componentInstance> |
<spirit:instanceName>blk_mem_gen_0</spirit:instanceName> |
<spirit:componentRef spirit:library="ip" spirit:name="blk_mem_gen" spirit:vendor="xilinx.com" spirit:version="8.3"/> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="bd:xciName">base_microblaze_design_blk_mem_gen_0_0</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="Memory_Type">True_Dual_Port_RAM</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="Assume_Synchronous_Clk">true</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="Enable_B">Use_ENB_Pin</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="Use_RSTB_Pin">true</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="Port_B_Clock">100</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="Port_B_Write_Rate">50</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="Port_B_Enable_Rate">100</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
<spirit:componentInstance> |
<spirit:instanceName>axi_bram_ctrl_0</spirit:instanceName> |
<spirit:componentRef spirit:library="ip" spirit:name="axi_bram_ctrl" spirit:vendor="xilinx.com" spirit:version="4.0"/> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="bd:xciName">base_microblaze_design_axi_bram_ctrl_0_0</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
<spirit:componentInstance> |
<spirit:instanceName>axi_intc_0</spirit:instanceName> |
<spirit:componentRef spirit:library="ip" spirit:name="axi_intc" spirit:vendor="xilinx.com" spirit:version="4.1"/> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="bd:xciName">base_microblaze_design_axi_intc_0_0</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
<spirit:componentInstance> |
<spirit:instanceName>xlconcat_0</spirit:instanceName> |
<spirit:componentRef spirit:library="ip" spirit:name="xlconcat" spirit:vendor="xilinx.com" spirit:version="2.1"/> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="bd:xciName">base_microblaze_design_xlconcat_0_0</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
</spirit:componentInstances> |
<spirit:interconnections> |
<spirit:interconnection> |
<spirit:name>microblaze_0_dlmb_1</spirit:name> |
<spirit:activeInterface spirit:busRef="DLMB" spirit:componentRef="microblaze_0"/> |
<spirit:activeInterface spirit:busRef="DLMB" spirit:componentRef="microblaze_0_local_memory"/> |
</spirit:interconnection> |
<spirit:interconnection> |
<spirit:name>microblaze_0_ilmb_1</spirit:name> |
<spirit:activeInterface spirit:busRef="ILMB" spirit:componentRef="microblaze_0"/> |
<spirit:activeInterface spirit:busRef="ILMB" spirit:componentRef="microblaze_0_local_memory"/> |
</spirit:interconnection> |
<spirit:interconnection> |
<spirit:name>microblaze_0_debug</spirit:name> |
<spirit:activeInterface spirit:busRef="MBDEBUG_0" spirit:componentRef="mdm_1"/> |
<spirit:activeInterface spirit:busRef="DEBUG" spirit:componentRef="microblaze_0"/> |
</spirit:interconnection> |
<spirit:interconnection> |
<spirit:name>microblaze_0_M_AXI_DP</spirit:name> |
<spirit:activeInterface spirit:busRef="M_AXI_DP" spirit:componentRef="microblaze_0"/> |
<spirit:activeInterface spirit:busRef="S00_AXI" spirit:componentRef="microblaze_0_axi_periph"/> |
</spirit:interconnection> |
<spirit:interconnection> |
<spirit:name>microblaze_0_axi_periph_M00_AXI</spirit:name> |
<spirit:activeInterface spirit:busRef="M00_AXI" spirit:componentRef="microblaze_0_axi_periph"/> |
<spirit:activeInterface spirit:busRef="S_AXI" spirit:componentRef="axi_gpio_0"/> |
</spirit:interconnection> |
<spirit:interconnection> |
<spirit:name>microblaze_0_axi_periph_M01_AXI</spirit:name> |
<spirit:activeInterface spirit:busRef="M01_AXI" spirit:componentRef="microblaze_0_axi_periph"/> |
<spirit:activeInterface spirit:busRef="S_AXI" spirit:componentRef="axi_uartlite_0"/> |
</spirit:interconnection> |
<spirit:interconnection> |
<spirit:name>microblaze_0_axi_periph_M02_AXI</spirit:name> |
<spirit:activeInterface spirit:busRef="M02_AXI" spirit:componentRef="microblaze_0_axi_periph"/> |
<spirit:activeInterface spirit:busRef="s_axi" spirit:componentRef="tri_mode_emac_0"/> |
</spirit:interconnection> |
<spirit:interconnection> |
<spirit:name>microblaze_0_axi_periph_M03_AXI</spirit:name> |
<spirit:activeInterface spirit:busRef="M03_AXI" spirit:componentRef="microblaze_0_axi_periph"/> |
<spirit:activeInterface spirit:busRef="S_AXI_LITE" spirit:componentRef="axi_dma_0"/> |
</spirit:interconnection> |
<spirit:interconnection> |
<spirit:name>axi_dma_0_M_AXIS_MM2S</spirit:name> |
<spirit:activeInterface spirit:busRef="tx_axis_fifo" spirit:componentRef="tri_mode_emac_0"/> |
<spirit:activeInterface spirit:busRef="M_AXIS_MM2S" spirit:componentRef="axi_dma_0"/> |
</spirit:interconnection> |
<spirit:interconnection> |
<spirit:name>tri_mode_emac_0_rx_axis_fifo</spirit:name> |
<spirit:activeInterface spirit:busRef="rx_axis_fifo" spirit:componentRef="tri_mode_emac_0"/> |
<spirit:activeInterface spirit:busRef="S_AXIS_S2MM" spirit:componentRef="axi_dma_0"/> |
</spirit:interconnection> |
<spirit:interconnection> |
<spirit:name>axi_bram_ctrl_0_BRAM_PORTA</spirit:name> |
<spirit:activeInterface spirit:busRef="BRAM_PORTA" spirit:componentRef="blk_mem_gen_0"/> |
<spirit:activeInterface spirit:busRef="BRAM_PORTA" spirit:componentRef="axi_bram_ctrl_0"/> |
</spirit:interconnection> |
<spirit:interconnection> |
<spirit:name>axi_bram_ctrl_0_BRAM_PORTB</spirit:name> |
<spirit:activeInterface spirit:busRef="BRAM_PORTB" spirit:componentRef="blk_mem_gen_0"/> |
<spirit:activeInterface spirit:busRef="BRAM_PORTB" spirit:componentRef="axi_bram_ctrl_0"/> |
</spirit:interconnection> |
<spirit:interconnection> |
<spirit:name>microblaze_0_axi_periph_M04_AXI</spirit:name> |
<spirit:activeInterface spirit:busRef="M04_AXI" spirit:componentRef="microblaze_0_axi_periph"/> |
<spirit:activeInterface spirit:busRef="S_AXI" spirit:componentRef="axi_bram_ctrl_0"/> |
</spirit:interconnection> |
<spirit:interconnection> |
<spirit:name>axi_dma_0_M_AXI_MM2S</spirit:name> |
<spirit:activeInterface spirit:busRef="M_AXI_MM2S" spirit:componentRef="axi_dma_0"/> |
<spirit:activeInterface spirit:busRef="S01_AXI" spirit:componentRef="microblaze_0_axi_periph"/> |
</spirit:interconnection> |
<spirit:interconnection> |
<spirit:name>axi_dma_0_M_AXI_S2MM</spirit:name> |
<spirit:activeInterface spirit:busRef="M_AXI_S2MM" spirit:componentRef="axi_dma_0"/> |
<spirit:activeInterface spirit:busRef="S02_AXI" spirit:componentRef="microblaze_0_axi_periph"/> |
</spirit:interconnection> |
<spirit:interconnection> |
<spirit:name>microblaze_0_axi_periph_M05_AXI</spirit:name> |
<spirit:activeInterface spirit:busRef="M05_AXI" spirit:componentRef="microblaze_0_axi_periph"/> |
<spirit:activeInterface spirit:busRef="s_axi" spirit:componentRef="axi_intc_0"/> |
</spirit:interconnection> |
<spirit:interconnection> |
<spirit:name>axi_intc_0_interrupt</spirit:name> |
<spirit:activeInterface spirit:busRef="interrupt" spirit:componentRef="axi_intc_0"/> |
<spirit:activeInterface spirit:busRef="INTERRUPT" spirit:componentRef="microblaze_0"/> |
</spirit:interconnection> |
</spirit:interconnections> |
<spirit:adHocConnections> |
<spirit:adHocConnection> |
<spirit:name>microblaze_0_Clk</spirit:name> |
<spirit:externalPortReference spirit:portRef="Clk"/> |
<spirit:internalPortReference spirit:componentRef="axi_gpio_0" spirit:portRef="s_axi_aclk"/> |
<spirit:internalPortReference spirit:componentRef="axi_uartlite_0" spirit:portRef="s_axi_aclk"/> |
<spirit:internalPortReference spirit:componentRef="tri_mode_emac_0" spirit:portRef="s_axi_aclk"/> |
<spirit:internalPortReference spirit:componentRef="microblaze_0" spirit:portRef="Clk"/> |
<spirit:internalPortReference spirit:componentRef="rst_Clk_100M" spirit:portRef="slowest_sync_clk"/> |
<spirit:internalPortReference spirit:componentRef="axi_dma_0" spirit:portRef="m_axi_mm2s_aclk"/> |
<spirit:internalPortReference spirit:componentRef="axi_dma_0" spirit:portRef="m_axi_s2mm_aclk"/> |
<spirit:internalPortReference spirit:componentRef="axi_dma_0" spirit:portRef="s_axi_lite_aclk"/> |
<spirit:internalPortReference spirit:componentRef="tri_mode_emac_0" spirit:portRef="rx_fifo_clock"/> |
<spirit:internalPortReference spirit:componentRef="tri_mode_emac_0" spirit:portRef="tx_fifo_clock"/> |
<spirit:internalPortReference spirit:componentRef="axi_bram_ctrl_0" spirit:portRef="s_axi_aclk"/> |
<spirit:internalPortReference spirit:componentRef="axi_intc_0" spirit:portRef="s_axi_aclk"/> |
<spirit:internalPortReference spirit:componentRef="microblaze_0_local_memory" spirit:portRef="LMB_Clk"/> |
<spirit:internalPortReference spirit:componentRef="microblaze_0_axi_periph" spirit:portRef="S00_ACLK"/> |
<spirit:internalPortReference spirit:componentRef="microblaze_0_axi_periph" spirit:portRef="ACLK"/> |
<spirit:internalPortReference spirit:componentRef="microblaze_0_axi_periph" spirit:portRef="M00_ACLK"/> |
<spirit:internalPortReference spirit:componentRef="microblaze_0_axi_periph" spirit:portRef="M01_ACLK"/> |
<spirit:internalPortReference spirit:componentRef="microblaze_0_axi_periph" spirit:portRef="M02_ACLK"/> |
<spirit:internalPortReference spirit:componentRef="microblaze_0_axi_periph" spirit:portRef="M03_ACLK"/> |
<spirit:internalPortReference spirit:componentRef="microblaze_0_axi_periph" spirit:portRef="M04_ACLK"/> |
<spirit:internalPortReference spirit:componentRef="microblaze_0_axi_periph" spirit:portRef="S01_ACLK"/> |
<spirit:internalPortReference spirit:componentRef="microblaze_0_axi_periph" spirit:portRef="S02_ACLK"/> |
<spirit:internalPortReference spirit:componentRef="microblaze_0_axi_periph" spirit:portRef="M05_ACLK"/> |
</spirit:adHocConnection> |
<spirit:adHocConnection> |
<spirit:name>rst_Clk_100M_mb_reset</spirit:name> |
<spirit:internalPortReference spirit:componentRef="rst_Clk_100M" spirit:portRef="mb_reset"/> |
<spirit:internalPortReference spirit:componentRef="microblaze_0" spirit:portRef="Reset"/> |
</spirit:adHocConnection> |
<spirit:adHocConnection> |
<spirit:name>rst_Clk_100M_bus_struct_reset</spirit:name> |
<spirit:internalPortReference spirit:componentRef="rst_Clk_100M" spirit:portRef="bus_struct_reset"/> |
<spirit:internalPortReference spirit:componentRef="microblaze_0_local_memory" spirit:portRef="SYS_Rst"/> |
</spirit:adHocConnection> |
<spirit:adHocConnection> |
<spirit:name>mdm_1_debug_sys_rst</spirit:name> |
<spirit:internalPortReference spirit:componentRef="mdm_1" spirit:portRef="Debug_SYS_Rst"/> |
<spirit:internalPortReference spirit:componentRef="rst_Clk_100M" spirit:portRef="mb_debug_sys_rst"/> |
</spirit:adHocConnection> |
<spirit:adHocConnection> |
<spirit:name>reset_1</spirit:name> |
<spirit:externalPortReference spirit:portRef="reset"/> |
<spirit:internalPortReference spirit:componentRef="rst_Clk_100M" spirit:portRef="ext_reset_in"/> |
</spirit:adHocConnection> |
<spirit:adHocConnection> |
<spirit:name>rst_Clk_100M_peripheral_aresetn1</spirit:name> |
<spirit:internalPortReference spirit:componentRef="rst_Clk_100M" spirit:portRef="peripheral_aresetn"/> |
<spirit:internalPortReference spirit:componentRef="axi_gpio_0" spirit:portRef="s_axi_aresetn"/> |
<spirit:internalPortReference spirit:componentRef="axi_uartlite_0" spirit:portRef="s_axi_aresetn"/> |
<spirit:internalPortReference spirit:componentRef="tri_mode_emac_0" spirit:portRef="s_axi_resetn"/> |
<spirit:internalPortReference spirit:componentRef="axi_dma_0" spirit:portRef="axi_resetn"/> |
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<spirit:internalPortReference spirit:componentRef="tri_mode_emac_0" spirit:portRef="rx_fifo_resetn"/> |
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|
<spirit:component xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> |
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|
<spirit:design xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> |
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<spirit:envIdentifier>:vivado.xilinx.com:</spirit:envIdentifier> |
<spirit:hierarchyRef spirit:library="BlockDiagram/base_microblaze_design_imp/microblaze_0_axi_periph_imp" spirit:name="s00_couplers_imp" spirit:vendor="xilinx.com" spirit:version="1.00.a"/> |
</spirit:view> |
</spirit:views> |
<spirit:ports> |
<spirit:port> |
<spirit:name>M_ACLK</spirit:name> |
<spirit:wire> |
<spirit:direction>in</spirit:direction> |
</spirit:wire> |
</spirit:port> |
<spirit:port> |
<spirit:name>M_ARESETN</spirit:name> |
<spirit:wire> |
<spirit:direction>in</spirit:direction> |
<spirit:vector> |
<spirit:left>0</spirit:left> |
<spirit:right>0</spirit:right> |
</spirit:vector> |
</spirit:wire> |
</spirit:port> |
<spirit:port> |
<spirit:name>S_ACLK</spirit:name> |
<spirit:wire> |
<spirit:direction>in</spirit:direction> |
</spirit:wire> |
</spirit:port> |
<spirit:port> |
<spirit:name>S_ARESETN</spirit:name> |
<spirit:wire> |
<spirit:direction>in</spirit:direction> |
<spirit:vector> |
<spirit:left>0</spirit:left> |
<spirit:right>0</spirit:right> |
</spirit:vector> |
</spirit:wire> |
</spirit:port> |
</spirit:ports> |
</spirit:model> |
</spirit:component> |
|
<spirit:design xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> |
<spirit:vendor>xilinx.com</spirit:vendor> |
<spirit:library>BlockDiagram/base_microblaze_design_imp/microblaze_0_axi_periph_imp</spirit:library> |
<spirit:name>s00_couplers_imp</spirit:name> |
<spirit:version>1.00.a</spirit:version> |
<spirit:componentInstances> |
<spirit:componentInstance> |
<spirit:instanceName>auto_pc</spirit:instanceName> |
<spirit:componentRef spirit:library="ip" spirit:name="axi_protocol_converter" spirit:vendor="xilinx.com" spirit:version="2.1"/> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="bd:xciName">base_microblaze_design_auto_pc_5</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="SI_PROTOCOL">AXI4LITE</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="MI_PROTOCOL">AXI4</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
</spirit:componentInstances> |
<spirit:interconnections/> |
<spirit:adHocConnections> |
<spirit:adHocConnection> |
<spirit:name>S_ACLK_1</spirit:name> |
<spirit:externalPortReference spirit:portRef="S_ACLK"/> |
<spirit:internalPortReference spirit:componentRef="auto_pc" spirit:portRef="aclk"/> |
</spirit:adHocConnection> |
<spirit:adHocConnection> |
<spirit:name>S_ARESETN_1</spirit:name> |
<spirit:externalPortReference spirit:portRef="S_ARESETN"/> |
<spirit:internalPortReference spirit:componentRef="auto_pc" spirit:portRef="aresetn"/> |
</spirit:adHocConnection> |
</spirit:adHocConnections> |
<spirit:hierConnections> |
<spirit:hierConnection spirit:interfaceRef="M_AXI/auto_pc_to_s00_couplers"> |
<spirit:activeInterface spirit:busRef="M_AXI" spirit:componentRef="auto_pc"/> |
</spirit:hierConnection> |
<spirit:hierConnection spirit:interfaceRef="S_AXI/s00_couplers_to_auto_pc"> |
<spirit:activeInterface spirit:busRef="S_AXI" spirit:componentRef="auto_pc"/> |
</spirit:hierConnection> |
</spirit:hierConnections> |
</spirit:design> |
|
<spirit:component xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> |
<spirit:vendor>xilinx.com</spirit:vendor> |
<spirit:library>BlockDiagram/base_microblaze_design_imp</spirit:library> |
<spirit:name>microblaze_0_local_memory</spirit:name> |
<spirit:version>1.00.a</spirit:version> |
<spirit:busInterfaces> |
<spirit:busInterface> |
<spirit:name>DLMB</spirit:name> |
<spirit:mirroredMaster/> |
<spirit:busType spirit:library="interface" spirit:name="lmb" spirit:vendor="xilinx.com" spirit:version="1.0"/> |
<spirit:abstractionType spirit:library="interface" spirit:name="lmb_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/> |
</spirit:busInterface> |
<spirit:busInterface> |
<spirit:name>ILMB</spirit:name> |
<spirit:mirroredMaster/> |
<spirit:busType spirit:library="interface" spirit:name="lmb" spirit:vendor="xilinx.com" spirit:version="1.0"/> |
<spirit:abstractionType spirit:library="interface" spirit:name="lmb_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/> |
</spirit:busInterface> |
<spirit:busInterface> |
<spirit:name>CLK.LMB_CLK</spirit:name> |
<spirit:displayName>Clk</spirit:displayName> |
<spirit:description>Clock</spirit:description> |
<spirit:busType spirit:library="signal" spirit:name="clock" spirit:vendor="xilinx.com" spirit:version="1.0"/> |
<spirit:abstractionType spirit:library="signal" spirit:name="clock_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/> |
<spirit:slave/> |
<spirit:portMaps> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>CLK</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>LMB_Clk</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
</spirit:portMaps> |
</spirit:busInterface> |
<spirit:busInterface> |
<spirit:name>RST.SYS_RST</spirit:name> |
<spirit:displayName>Reset</spirit:displayName> |
<spirit:description>Reset</spirit:description> |
<spirit:busType spirit:library="signal" spirit:name="reset" spirit:vendor="xilinx.com" spirit:version="1.0"/> |
<spirit:abstractionType spirit:library="signal" spirit:name="reset_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/> |
<spirit:slave/> |
<spirit:portMaps> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>RST</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>SYS_Rst</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
</spirit:portMaps> |
</spirit:busInterface> |
</spirit:busInterfaces> |
<spirit:model> |
<spirit:views> |
<spirit:view> |
<spirit:name>BlockDiagram</spirit:name> |
<spirit:envIdentifier>:vivado.xilinx.com:</spirit:envIdentifier> |
<spirit:hierarchyRef spirit:library="BlockDiagram/base_microblaze_design_imp" spirit:name="microblaze_0_local_memory_imp" spirit:vendor="xilinx.com" spirit:version="1.00.a"/> |
</spirit:view> |
</spirit:views> |
<spirit:ports> |
<spirit:port> |
<spirit:name>LMB_Clk</spirit:name> |
<spirit:wire> |
<spirit:direction>in</spirit:direction> |
</spirit:wire> |
</spirit:port> |
<spirit:port> |
<spirit:name>SYS_Rst</spirit:name> |
<spirit:wire> |
<spirit:direction>in</spirit:direction> |
<spirit:vector> |
<spirit:left>0</spirit:left> |
<spirit:right>0</spirit:right> |
</spirit:vector> |
</spirit:wire> |
</spirit:port> |
</spirit:ports> |
</spirit:model> |
</spirit:component> |
|
<spirit:design xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> |
<spirit:vendor>xilinx.com</spirit:vendor> |
<spirit:library>BlockDiagram/base_microblaze_design_imp</spirit:library> |
<spirit:name>microblaze_0_local_memory_imp</spirit:name> |
<spirit:version>1.00.a</spirit:version> |
<spirit:componentInstances> |
<spirit:componentInstance> |
<spirit:instanceName>dlmb_v10</spirit:instanceName> |
<spirit:componentRef spirit:library="ip" spirit:name="lmb_v10" spirit:vendor="xilinx.com" spirit:version="3.0"/> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="bd:xciName">base_microblaze_design_dlmb_v10_0</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
<spirit:componentInstance> |
<spirit:instanceName>ilmb_v10</spirit:instanceName> |
<spirit:componentRef spirit:library="ip" spirit:name="lmb_v10" spirit:vendor="xilinx.com" spirit:version="3.0"/> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="bd:xciName">base_microblaze_design_ilmb_v10_0</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
<spirit:componentInstance> |
<spirit:instanceName>dlmb_bram_if_cntlr</spirit:instanceName> |
<spirit:componentRef spirit:library="ip" spirit:name="lmb_bram_if_cntlr" spirit:vendor="xilinx.com" spirit:version="4.0"/> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="bd:xciName">base_microblaze_design_dlmb_bram_if_cntlr_0</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="C_ECC">0</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
<spirit:componentInstance> |
<spirit:instanceName>ilmb_bram_if_cntlr</spirit:instanceName> |
<spirit:componentRef spirit:library="ip" spirit:name="lmb_bram_if_cntlr" spirit:vendor="xilinx.com" spirit:version="4.0"/> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="bd:xciName">base_microblaze_design_ilmb_bram_if_cntlr_0</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="C_ECC">0</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
<spirit:componentInstance> |
<spirit:instanceName>lmb_bram</spirit:instanceName> |
<spirit:componentRef spirit:library="ip" spirit:name="blk_mem_gen" spirit:vendor="xilinx.com" spirit:version="8.3"/> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="bd:xciName">base_microblaze_design_lmb_bram_0</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="Memory_Type">True_Dual_Port_RAM</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="use_bram_block">BRAM_Controller</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
</spirit:componentInstance> |
</spirit:componentInstances> |
<spirit:interconnections> |
<spirit:interconnection> |
<spirit:name>microblaze_0_dlmb_bus</spirit:name> |
<spirit:activeInterface spirit:busRef="LMB_Sl_0" spirit:componentRef="dlmb_v10"/> |
<spirit:activeInterface spirit:busRef="SLMB" spirit:componentRef="dlmb_bram_if_cntlr"/> |
</spirit:interconnection> |
<spirit:interconnection> |
<spirit:name>microblaze_0_ilmb_bus</spirit:name> |
<spirit:activeInterface spirit:busRef="LMB_Sl_0" spirit:componentRef="ilmb_v10"/> |
<spirit:activeInterface spirit:busRef="SLMB" spirit:componentRef="ilmb_bram_if_cntlr"/> |
</spirit:interconnection> |
<spirit:interconnection> |
<spirit:name>microblaze_0_dlmb_cntlr</spirit:name> |
<spirit:activeInterface spirit:busRef="BRAM_PORT" spirit:componentRef="dlmb_bram_if_cntlr"/> |
<spirit:activeInterface spirit:busRef="BRAM_PORTA" spirit:componentRef="lmb_bram"/> |
</spirit:interconnection> |
<spirit:interconnection> |
<spirit:name>microblaze_0_ilmb_cntlr</spirit:name> |
<spirit:activeInterface spirit:busRef="BRAM_PORT" spirit:componentRef="ilmb_bram_if_cntlr"/> |
<spirit:activeInterface spirit:busRef="BRAM_PORTB" spirit:componentRef="lmb_bram"/> |
</spirit:interconnection> |
</spirit:interconnections> |
<spirit:adHocConnections> |
<spirit:adHocConnection> |
<spirit:name>microblaze_0_Clk</spirit:name> |
<spirit:externalPortReference spirit:portRef="LMB_Clk"/> |
<spirit:internalPortReference spirit:componentRef="dlmb_v10" spirit:portRef="LMB_Clk"/> |
<spirit:internalPortReference spirit:componentRef="dlmb_bram_if_cntlr" spirit:portRef="LMB_Clk"/> |
<spirit:internalPortReference spirit:componentRef="ilmb_v10" spirit:portRef="LMB_Clk"/> |
<spirit:internalPortReference spirit:componentRef="ilmb_bram_if_cntlr" spirit:portRef="LMB_Clk"/> |
</spirit:adHocConnection> |
<spirit:adHocConnection> |
<spirit:name>SYS_Rst_1</spirit:name> |
<spirit:externalPortReference spirit:portRef="SYS_Rst"/> |
<spirit:internalPortReference spirit:componentRef="dlmb_v10" spirit:portRef="SYS_Rst"/> |
<spirit:internalPortReference spirit:componentRef="dlmb_bram_if_cntlr" spirit:portRef="LMB_Rst"/> |
<spirit:internalPortReference spirit:componentRef="ilmb_v10" spirit:portRef="SYS_Rst"/> |
<spirit:internalPortReference spirit:componentRef="ilmb_bram_if_cntlr" spirit:portRef="LMB_Rst"/> |
</spirit:adHocConnection> |
</spirit:adHocConnections> |
<spirit:hierConnections> |
<spirit:hierConnection spirit:interfaceRef="DLMB/microblaze_0_dlmb"> |
<spirit:activeInterface spirit:busRef="LMB_M" spirit:componentRef="dlmb_v10"/> |
</spirit:hierConnection> |
<spirit:hierConnection spirit:interfaceRef="ILMB/microblaze_0_ilmb"> |
<spirit:activeInterface spirit:busRef="LMB_M" spirit:componentRef="ilmb_v10"/> |
</spirit:hierConnection> |
</spirit:hierConnections> |
</spirit:design> |
|
<spirit:component xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> |
<spirit:vendor>xilinx.com</spirit:vendor> |
<spirit:library>Addressing/microblaze_0</spirit:library> |
<spirit:name>microblaze</spirit:name> |
<spirit:version>9.5</spirit:version> |
<spirit:addressSpaces> |
<spirit:addressSpace> |
<spirit:name>Data</spirit:name> |
<spirit:range>4G</spirit:range> |
<spirit:width>32</spirit:width> |
<spirit:segments> |
<spirit:segment> |
<spirit:name>SEG_dlmb_bram_if_cntlr_Mem</spirit:name> |
<spirit:displayName>/microblaze_0_local_memory/dlmb_bram_if_cntlr/SLMB/Mem</spirit:displayName> |
<spirit:addressOffset>0x00000000</spirit:addressOffset> |
<spirit:range>128K</spirit:range> |
</spirit:segment> |
<spirit:segment> |
<spirit:name>SEG_axi_gpio_0_Reg</spirit:name> |
<spirit:displayName>/axi_gpio_0/S_AXI/Reg</spirit:displayName> |
<spirit:addressOffset>0x40000000</spirit:addressOffset> |
<spirit:range>64K</spirit:range> |
</spirit:segment> |
<spirit:segment> |
<spirit:name>SEG_axi_uartlite_0_Reg</spirit:name> |
<spirit:displayName>/axi_uartlite_0/S_AXI/Reg</spirit:displayName> |
<spirit:addressOffset>0x40600000</spirit:addressOffset> |
<spirit:range>64K</spirit:range> |
</spirit:segment> |
<spirit:segment> |
<spirit:name>SEG_tri_mode_emac_0_reg0</spirit:name> |
<spirit:displayName>/tri_mode_emac_0/s_axi/reg0</spirit:displayName> |
<spirit:addressOffset>0x44A00000</spirit:addressOffset> |
<spirit:range>64K</spirit:range> |
</spirit:segment> |
<spirit:segment> |
<spirit:name>SEG_axi_dma_0_Reg</spirit:name> |
<spirit:displayName>/axi_dma_0/S_AXI_LITE/Reg</spirit:displayName> |
<spirit:addressOffset>0x41E00000</spirit:addressOffset> |
<spirit:range>64K</spirit:range> |
</spirit:segment> |
<spirit:segment> |
<spirit:name>SEG_axi_bram_ctrl_0_Mem0</spirit:name> |
<spirit:displayName>/axi_bram_ctrl_0/S_AXI/Mem0</spirit:displayName> |
<spirit:addressOffset>0xC0000000</spirit:addressOffset> |
<spirit:range>8K</spirit:range> |
</spirit:segment> |
<spirit:segment> |
<spirit:name>SEG_axi_intc_0_Reg</spirit:name> |
<spirit:displayName>/axi_intc_0/s_axi/Reg</spirit:displayName> |
<spirit:addressOffset>0x41200000</spirit:addressOffset> |
<spirit:range>64K</spirit:range> |
</spirit:segment> |
</spirit:segments> |
</spirit:addressSpace> |
<spirit:addressSpace> |
<spirit:name>Instruction</spirit:name> |
<spirit:range>4G</spirit:range> |
<spirit:width>32</spirit:width> |
<spirit:segments> |
<spirit:segment> |
<spirit:name>SEG_ilmb_bram_if_cntlr_Mem</spirit:name> |
<spirit:displayName>/microblaze_0_local_memory/ilmb_bram_if_cntlr/SLMB/Mem</spirit:displayName> |
<spirit:addressOffset>0x00000000</spirit:addressOffset> |
<spirit:range>128K</spirit:range> |
</spirit:segment> |
</spirit:segments> |
</spirit:addressSpace> |
</spirit:addressSpaces> |
</spirit:component> |
|
<spirit:component xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> |
<spirit:vendor>xilinx.com</spirit:vendor> |
<spirit:library>Addressing/mdm_1</spirit:library> |
<spirit:name>mdm</spirit:name> |
<spirit:version>3.2</spirit:version> |
<spirit:addressSpaces/> |
</spirit:component> |
|
<spirit:component xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> |
<spirit:vendor>xilinx.com</spirit:vendor> |
<spirit:library>Addressing/axi_dma_0</spirit:library> |
<spirit:name>axi_dma</spirit:name> |
<spirit:version>7.1</spirit:version> |
<spirit:addressSpaces> |
<spirit:addressSpace> |
<spirit:name>Data_MM2S</spirit:name> |
<spirit:range>4G</spirit:range> |
<spirit:width>32</spirit:width> |
<spirit:segments> |
<spirit:segment> |
<spirit:name>SEG_axi_bram_ctrl_0_Mem0</spirit:name> |
<spirit:displayName>/axi_bram_ctrl_0/S_AXI/Mem0</spirit:displayName> |
<spirit:addressOffset>0xC0000000</spirit:addressOffset> |
<spirit:range>8K</spirit:range> |
</spirit:segment> |
<spirit:segment bd:isExcluded="true"> |
<spirit:name>SEG_axi_dma_0_Reg</spirit:name> |
<spirit:displayName>/axi_dma_0/S_AXI_LITE/Reg</spirit:displayName> |
<spirit:addressOffset>0x41E00000</spirit:addressOffset> |
<spirit:range>64K</spirit:range> |
</spirit:segment> |
<spirit:segment bd:isExcluded="true"> |
<spirit:name>SEG_axi_gpio_0_Reg</spirit:name> |
<spirit:displayName>/axi_gpio_0/S_AXI/Reg</spirit:displayName> |
<spirit:addressOffset>0x40000000</spirit:addressOffset> |
<spirit:range>64K</spirit:range> |
</spirit:segment> |
<spirit:segment bd:isExcluded="true"> |
<spirit:name>SEG_axi_uartlite_0_Reg</spirit:name> |
<spirit:displayName>/axi_uartlite_0/S_AXI/Reg</spirit:displayName> |
<spirit:addressOffset>0x40600000</spirit:addressOffset> |
<spirit:range>64K</spirit:range> |
</spirit:segment> |
<spirit:segment bd:isExcluded="true"> |
<spirit:name>SEG_tri_mode_emac_0_reg0</spirit:name> |
<spirit:displayName>/tri_mode_emac_0/s_axi/reg0</spirit:displayName> |
<spirit:addressOffset>0x44A00000</spirit:addressOffset> |
<spirit:range>64K</spirit:range> |
</spirit:segment> |
<spirit:segment bd:isExcluded="true"> |
<spirit:name>SEG_axi_intc_0_Reg</spirit:name> |
<spirit:displayName>/axi_intc_0/s_axi/Reg</spirit:displayName> |
<spirit:addressOffset>0x41200000</spirit:addressOffset> |
<spirit:range>64K</spirit:range> |
</spirit:segment> |
</spirit:segments> |
</spirit:addressSpace> |
<spirit:addressSpace> |
<spirit:name>Data_S2MM</spirit:name> |
<spirit:range>4G</spirit:range> |
<spirit:width>32</spirit:width> |
<spirit:segments> |
<spirit:segment> |
<spirit:name>SEG_axi_bram_ctrl_0_Mem0</spirit:name> |
<spirit:displayName>/axi_bram_ctrl_0/S_AXI/Mem0</spirit:displayName> |
<spirit:addressOffset>0xC0000000</spirit:addressOffset> |
<spirit:range>8K</spirit:range> |
</spirit:segment> |
<spirit:segment bd:isExcluded="true"> |
<spirit:name>SEG_axi_dma_0_Reg</spirit:name> |
<spirit:displayName>/axi_dma_0/S_AXI_LITE/Reg</spirit:displayName> |
<spirit:addressOffset>0x41E00000</spirit:addressOffset> |
<spirit:range>64K</spirit:range> |
</spirit:segment> |
<spirit:segment bd:isExcluded="true"> |
<spirit:name>SEG_axi_gpio_0_Reg</spirit:name> |
<spirit:displayName>/axi_gpio_0/S_AXI/Reg</spirit:displayName> |
<spirit:addressOffset>0x40000000</spirit:addressOffset> |
<spirit:range>64K</spirit:range> |
</spirit:segment> |
<spirit:segment bd:isExcluded="true"> |
<spirit:name>SEG_axi_uartlite_0_Reg</spirit:name> |
<spirit:displayName>/axi_uartlite_0/S_AXI/Reg</spirit:displayName> |
<spirit:addressOffset>0x40600000</spirit:addressOffset> |
<spirit:range>64K</spirit:range> |
</spirit:segment> |
<spirit:segment bd:isExcluded="true"> |
<spirit:name>SEG_tri_mode_emac_0_reg0</spirit:name> |
<spirit:displayName>/tri_mode_emac_0/s_axi/reg0</spirit:displayName> |
<spirit:addressOffset>0x44A00000</spirit:addressOffset> |
<spirit:range>64K</spirit:range> |
</spirit:segment> |
<spirit:segment bd:isExcluded="true"> |
<spirit:name>SEG_axi_intc_0_Reg</spirit:name> |
<spirit:displayName>/axi_intc_0/s_axi/Reg</spirit:displayName> |
<spirit:addressOffset>0x41200000</spirit:addressOffset> |
<spirit:range>64K</spirit:range> |
</spirit:segment> |
</spirit:segments> |
</spirit:addressSpace> |
</spirit:addressSpaces> |
</spirit:component> |
|
</bd:repository> |
/trunk/hw/layout/tcl/vdbg.tcl
0,0 → 1,7
#set_property mark_debug true [get_nets [list {u0/microblaze_0/M_AXI_DP_ARADDR[4]} {u0/microblaze_0/M_AXI_DP_ARADDR[20]} {u0/microblaze_0/M_AXI_DP_AWADDR[2]} {u0/microblaze_0/M_AXI_DP_AWADDR[18]} {u0/microblaze_0/M_AXI_DP_AWPROT[2]} {u0/microblaze_0/M_AXI_DP_RDATA[13]} {u0/microblaze_0/M_AXI_DP_RDATA[29]} {u0/microblaze_0/M_AXI_DP_WDATA[10]} {u0/microblaze_0/M_AXI_DP_AWADDR[15]} {u0/microblaze_0/M_AXI_DP_ARADDR[1]} {u0/microblaze_0/M_AXI_DP_ARADDR[17]} {u0/microblaze_0/M_AXI_DP_ARPROT[2]} {u0/microblaze_0/M_AXI_DP_AWADDR[31]} {u0/microblaze_0/M_AXI_DP_RDATA[9]} {u0/microblaze_0/M_AXI_DP_RDATA[26]} {u0/microblaze_0/M_AXI_DP_WDATA[8]} {u0/microblaze_0/M_AXI_DP_WDATA[24]} {u0/microblaze_0/M_AXI_DP_AWADDR[24]} {u0/microblaze_0/M_AXI_DP_ARADDR[26]} {u0/microblaze_0/M_AXI_DP_ARADDR[9]} {u0/microblaze_0/M_AXI_DP_AWADDR[8]} {u0/microblaze_0/M_AXI_DP_RDATA[3]} {u0/microblaze_0/M_AXI_DP_RDATA[19]} {u0/microblaze_0/M_AXI_DP_WDATA[1]} {u0/microblaze_0/M_AXI_DP_WDATA[17]} {u0/microblaze_0/M_AXI_DP_WDATA[29]} {u0/microblaze_0/M_AXI_DP_AWADDR[21]} {u0/microblaze_0/M_AXI_DP_AWADDR[5]} {u0/microblaze_0/M_AXI_DP_ARADDR[7]} {u0/microblaze_0/M_AXI_DP_ARADDR[23]} {u0/microblaze_0/M_AXI_DP_RDATA[0]} {u0/microblaze_0/M_AXI_DP_RDATA[16]} {u0/microblaze_0/M_AXI_DP_RRESP[0]} {u0/microblaze_0/M_AXI_DP_WDATA[14]} {u0/microblaze_0/M_AXI_DP_WDATA[26]} {u0/microblaze_0/M_AXI_DP_AWADDR[14]} {u0/microblaze_0/M_AXI_DP_ARADDR[0]} {u0/microblaze_0/M_AXI_DP_WSTRB[3]} {u0/microblaze_0/M_AXI_DP_ARADDR[16]} {u0/microblaze_0/M_AXI_DP_ARPROT[1]} {u0/microblaze_0/M_AXI_DP_AWADDR[30]} {u0/microblaze_0/M_AXI_DP_RDATA[11]} {u0/microblaze_0/M_AXI_DP_RDATA[25]} {u0/microblaze_0/M_AXI_DP_WDATA[7]} {u0/microblaze_0/M_AXI_DP_WDATA[23]} {u0/microblaze_0/M_AXI_DP_AWADDR[27]} {u0/microblaze_0/M_AXI_DP_ARADDR[29]} {u0/microblaze_0/M_AXI_DP_ARADDR[13]} {u0/microblaze_0/M_AXI_DP_AWADDR[10]} {u0/microblaze_0/M_AXI_DP_RDATA[6]} {u0/microblaze_0/M_AXI_DP_RDATA[22]} {u0/microblaze_0/M_AXI_DP_WDATA[4]} {u0/microblaze_0/M_AXI_DP_WDATA[20]} {u0/microblaze_0/M_AXI_DP_WSTRB[0]} {u0/microblaze_0/M_AXI_DP_AWADDR[20]} {u0/microblaze_0/M_AXI_DP_ARADDR[6]} {u0/microblaze_0/M_AXI_DP_ARADDR[22]} {u0/microblaze_0/M_AXI_DP_AWADDR[4]} {u0/microblaze_0/M_AXI_DP_BRESP[1]} {u0/microblaze_0/M_AXI_DP_RDATA[15]} {u0/microblaze_0/M_AXI_DP_RDATA[31]} {u0/microblaze_0/M_AXI_DP_WDATA[13]} {u0/microblaze_0/M_AXI_DP_WDATA[25]} {u0/microblaze_0/M_AXI_DP_ARADDR[19]} {u0/microblaze_0/M_AXI_DP_ARADDR[3]} {u0/microblaze_0/M_AXI_DP_AWADDR[1]} {u0/microblaze_0/M_AXI_DP_AWADDR[17]} {u0/microblaze_0/M_AXI_DP_AWPROT[1]} {u0/microblaze_0/M_AXI_DP_RDATA[12]} {u0/microblaze_0/M_AXI_DP_RDATA[28]} {u0/microblaze_0/M_AXI_DP_WDATA[9]} {u0/microblaze_0/M_AXI_DP_AWADDR[26]} {u0/microblaze_0/M_AXI_DP_ARADDR[28]} {u0/microblaze_0/M_AXI_DP_ARADDR[12]} {u0/microblaze_0/M_AXI_DP_AWADDR[9]} {u0/microblaze_0/M_AXI_DP_RDATA[5]} {u0/microblaze_0/M_AXI_DP_RDATA[21]} {u0/microblaze_0/M_AXI_DP_WDATA[3]} {u0/microblaze_0/M_AXI_DP_WDATA[19]} {u0/microblaze_0/M_AXI_DP_WDATA[31]} {u0/microblaze_0/M_AXI_DP_AWADDR[23]} {u0/microblaze_0/M_AXI_DP_ARADDR[25]} {u0/microblaze_0/M_AXI_DP_ARADDR[11]} {u0/microblaze_0/M_AXI_DP_AWADDR[7]} {u0/microblaze_0/M_AXI_DP_RDATA[2]} {u0/microblaze_0/M_AXI_DP_RDATA[18]} {u0/microblaze_0/M_AXI_DP_WDATA[0]} {u0/microblaze_0/M_AXI_DP_WDATA[16]} {u0/microblaze_0/M_AXI_DP_WDATA[28]} {u0/microblaze_0/M_AXI_DP_ARADDR[18]} {u0/microblaze_0/M_AXI_DP_ARADDR[2]} {u0/microblaze_0/M_AXI_DP_AWADDR[0]} {u0/microblaze_0/M_AXI_DP_AWADDR[16]} {u0/microblaze_0/M_AXI_DP_AWPROT[0]} {u0/microblaze_0/M_AXI_DP_RDATA[10]} {u0/microblaze_0/M_AXI_DP_RDATA[27]} {u0/microblaze_0/M_AXI_DP_WDATA[11]} {u0/microblaze_0/M_AXI_DP_AWADDR[13]} {u0/microblaze_0/M_AXI_DP_ARADDR[15]} {u0/microblaze_0/M_AXI_DP_AWADDR[29]} {u0/microblaze_0/M_AXI_DP_RDATA[8]} {u0/microblaze_0/M_AXI_DP_RDATA[24]} {u0/microblaze_0/M_AXI_DP_WDATA[6]} {u0/microblaze_0/M_AXI_DP_WDATA[22]} {u0/microblaze_0/M_AXI_DP_ARADDR[31]} {u0/microblaze_0/M_AXI_DP_ARPROT[0]} {u0/microblaze_0/M_AXI_DP_WSTRB[2]} {u0/microblaze_0/M_AXI_DP_AWADDR[22]} {u0/microblaze_0/M_AXI_DP_ARADDR[24]} {u0/microblaze_0/M_AXI_DP_ARADDR[8]} {u0/microblaze_0/M_AXI_DP_AWADDR[6]} {u0/microblaze_0/M_AXI_DP_RDATA[1]} {u0/microblaze_0/M_AXI_DP_RDATA[17]} {u0/microblaze_0/M_AXI_DP_RRESP[1]} {u0/microblaze_0/M_AXI_DP_WDATA[15]} {u0/microblaze_0/M_AXI_DP_WDATA[27]} {u0/microblaze_0/M_AXI_DP_ARADDR[5]} {u0/microblaze_0/M_AXI_DP_ARADDR[21]} {u0/microblaze_0/M_AXI_DP_AWADDR[3]} {u0/microblaze_0/M_AXI_DP_AWADDR[19]} {u0/microblaze_0/M_AXI_DP_BRESP[0]} {u0/microblaze_0/M_AXI_DP_RDATA[14]} {u0/microblaze_0/M_AXI_DP_RDATA[30]} {u0/microblaze_0/M_AXI_DP_WDATA[12]} {u0/microblaze_0/M_AXI_DP_AWADDR[28]} {u0/microblaze_0/M_AXI_DP_ARADDR[30]} {u0/microblaze_0/M_AXI_DP_ARADDR[14]} {u0/microblaze_0/M_AXI_DP_AWADDR[12]} {u0/microblaze_0/M_AXI_DP_RDATA[7]} {u0/microblaze_0/M_AXI_DP_RDATA[23]} {u0/microblaze_0/M_AXI_DP_WDATA[5]} {u0/microblaze_0/M_AXI_DP_WDATA[21]} {u0/microblaze_0/M_AXI_DP_WSTRB[1]} {u0/microblaze_0/M_AXI_DP_AWADDR[25]} {u0/microblaze_0/M_AXI_DP_ARADDR[27]} {u0/microblaze_0/M_AXI_DP_ARADDR[10]} {u0/microblaze_0/M_AXI_DP_AWADDR[11]} {u0/microblaze_0/M_AXI_DP_RDATA[4]} {u0/microblaze_0/M_AXI_DP_RDATA[20]} {u0/microblaze_0/M_AXI_DP_WDATA[2]} {u0/microblaze_0/M_AXI_DP_WDATA[18]} {u0/microblaze_0/M_AXI_DP_WDATA[30]}]] |
#set_property mark_debug true [get_nets [list u0/microblaze_0/M_AXI_DP_ARVALID u0/microblaze_0/M_AXI_DP_AWVALID u0/microblaze_0/M_AXI_DP_BVALID u0/microblaze_0/M_AXI_DP_RVALID u0/microblaze_0/M_AXI_DP_WVALID u0/microblaze_0/M_AXI_DP_ARREADY u0/microblaze_0/M_AXI_DP_AWREADY u0/microblaze_0/M_AXI_DP_BREADY u0/microblaze_0/M_AXI_DP_RREADY u0/microblaze_0/M_AXI_DP_WREADY]] |
#set_property TRIGGER_COMPARE_VALUE eq1'h1 [get_hw_probes u0/microblaze_0/M_AXI_DP_ARVALID -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7k325t_0] -filter {CELL_NAME=~"u_ila_0"}]] |
#set_property CONTROL.TRIGGER_POSITION 16 [get_hw_ilas -of_objects [get_hw_devices xc7k325t_0] -filter {CELL_NAME=~"u_ila_0"}] |
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#write_hw_ila_data -force mwform.zip |
#display_hw_ila_data [read_hw_ila_data mwform.zip] |
/trunk/hw/layout/tcl/vrun.tcl
0,0 → 1,14
|
open_project ./project_n1.xpr |
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config_webtalk -user off |
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update_compile_order -fileset sources_1 |
update_compile_order -fileset sim_1 |
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launch_runs impl_1 -to_step write_bitstream |
wait_on_run impl_1 |
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#open_run impl_1 |
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close_project |
/trunk/hw/layout/tcl/vsetup.tcl
0,0 → 1,44
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create_project project_n1 ./ -part xc7k325tffg900-2 |
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set obj [get_projects project_n1] |
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set_property "board_part" "xilinx.com:kc705:part0:1.2" $obj |
set_property "default_lib" "xil_defaultlib" $obj |
set_property "sim.ip.auto_export_scripts" "1" $obj |
set_property "simulator_language" "Mixed" $obj |
set_property "target_language" "Verilog" $obj |
set_property "target_simulator" "ModelSim" $obj |
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add_files -norecurse ../xdc/project_n1_b.sdc |
add_files -norecurse ../xdc/project_n1_p.sdc |
add_files -norecurse ../xdc/project_n1_t.sdc |
add_files -norecurse ../xdc/project_n1_user_phytiming.xdc |
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add_files -norecurse ../../src/rtl/microb_top.v |
add_files -norecurse ../../src/rtl/tri_mode_emac_support/tri_mode_ethernet_mac_0_clk_wiz.v |
add_files -norecurse ../../src/rtl/tri_mode_emac_support/tri_mode_ethernet_mac_0_example_design_clocks.v |
add_files -norecurse ../../src/rtl/tri_mode_emac_support/tri_mode_ethernet_mac_0_example_design_resets.v |
add_files -norecurse ../../src/rtl/tri_mode_emac_support/common/tri_mode_ethernet_mac_0_reset_sync.v |
add_files -norecurse ../../src/rtl/tri_mode_emac_support/common/tri_mode_ethernet_mac_0_sync_block.v |
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set_property "ip_repo_paths" "../../src/rtl" $obj |
update_ip_catalog |
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import_files -norecurse ../bd/base_microblaze_design.bd |
export_ip_user_files -of_objects [get_files ./project_n1.srcs/sources_1/bd/bd/base_microblaze_design.bd] -force -quiet |
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set obj [get_filesets sources_1] |
set_property "top" "microb_top" $obj |
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update_compile_order -fileset sources_1 |
update_compile_order -fileset sim_1 |
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# derive BD-files |
generate_target all [get_files ./project_n1.srcs/sources_1/bd/bd/base_microblaze_design.bd] |
# derive xci-src |
export_ip_user_files -of_objects [get_files ./project_n1.srcs/sources_1/bd/bd/base_microblaze_design.bd] -no_script -force -quiet |
# derive sim-scripts |
export_simulation -of_objects [get_files ./project_n1.srcs/sources_1/bd/bd/base_microblaze_design.bd] -directory ./project_n1.ip_user_files/sim_scripts -force -quiet |
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close_project |
/trunk/hw/layout/xdc/project_n1_b.sdc
0,0 → 1,2
# bit |
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design] |
/trunk/hw/layout/xdc/project_n1_p.sdc
0,0 → 1,73
# clk |
set_property LOC AD12 [ get_ports sys_diff_clock_clk_p] |
set_property IOSTANDARD DIFF_SSTL15 [ get_ports sys_diff_clock_clk_p] |
# rst |
set_property LOC AB7 [ get_ports glbl_rst] |
set_property IOSTANDARD LVCMOS15 [ get_ports glbl_rst] |
# led |
set_property LOC AB8 [ get_ports led_8bits_tri_o[0]] |
set_property IOSTANDARD LVCMOS15 [ get_ports led_8bits_tri_o[0]] |
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set_property LOC AA8 [ get_ports led_8bits_tri_o[1]] |
set_property IOSTANDARD LVCMOS15 [ get_ports led_8bits_tri_o[1]] |
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set_property LOC AC9 [ get_ports led_8bits_tri_o[2]] |
set_property IOSTANDARD LVCMOS15 [ get_ports led_8bits_tri_o[2]] |
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set_property LOC AB9 [ get_ports led_8bits_tri_o[3]] |
set_property IOSTANDARD LVCMOS15 [ get_ports led_8bits_tri_o[3]] |
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set_property LOC AE26 [ get_ports led_8bits_tri_o[4]] |
set_property IOSTANDARD LVCMOS25 [ get_ports led_8bits_tri_o[4]] |
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set_property LOC G19 [ get_ports led_8bits_tri_o[5]] |
set_property IOSTANDARD LVCMOS25 [ get_ports led_8bits_tri_o[5]] |
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set_property LOC E18 [ get_ports led_8bits_tri_o[6]] |
set_property IOSTANDARD LVCMOS25 [ get_ports led_8bits_tri_o[6]] |
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set_property LOC F16 [ get_ports led_8bits_tri_o[7]] |
set_property IOSTANDARD LVCMOS25 [ get_ports led_8bits_tri_o[7]] |
# uart |
set_property LOC M19 [ get_ports rs232_uart_rxd] |
set_property IOSTANDARD LVCMOS25 [ get_ports rs232_uart_rxd] |
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set_property LOC K24 [ get_ports rs232_uart_txd] |
set_property IOSTANDARD LVCMOS25 [ get_ports rs232_uart_txd] |
# PHY-MDIO |
set_property PACKAGE_PIN R23 [get_ports mdc] |
set_property IOSTANDARD LVCMOS25 [get_ports mdc] |
set_property PACKAGE_PIN J21 [get_ports mdio] |
set_property IOSTANDARD LVCMOS25 [get_ports mdio] |
# PHY-RGMII |
set_property PACKAGE_PIN U28 [get_ports rgmii_rxd[3]] |
set_property PACKAGE_PIN T25 [get_ports rgmii_rxd[2]] |
set_property PACKAGE_PIN U25 [get_ports rgmii_rxd[1]] |
set_property PACKAGE_PIN U30 [get_ports rgmii_rxd[0]] |
set_property IOSTANDARD LVCMOS25 [get_ports rgmii_rxd[3]] |
set_property IOSTANDARD LVCMOS25 [get_ports rgmii_rxd[2]] |
set_property IOSTANDARD LVCMOS25 [get_ports rgmii_rxd[1]] |
set_property IOSTANDARD LVCMOS25 [get_ports rgmii_rxd[0]] |
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set_property PACKAGE_PIN L28 [get_ports rgmii_txd[3]] |
set_property PACKAGE_PIN M29 [get_ports rgmii_txd[2]] |
set_property PACKAGE_PIN N25 [get_ports rgmii_txd[1]] |
set_property PACKAGE_PIN N27 [get_ports rgmii_txd[0]] |
set_property IOSTANDARD LVCMOS25 [get_ports rgmii_txd[3]] |
set_property IOSTANDARD LVCMOS25 [get_ports rgmii_txd[2]] |
set_property IOSTANDARD LVCMOS25 [get_ports rgmii_txd[1]] |
set_property IOSTANDARD LVCMOS25 [get_ports rgmii_txd[0]] |
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set_property PACKAGE_PIN M27 [get_ports rgmii_tx_ctl] |
set_property PACKAGE_PIN K30 [get_ports rgmii_txc] |
set_property IOSTANDARD LVCMOS25 [get_ports rgmii_tx_ctl] |
set_property IOSTANDARD LVCMOS25 [get_ports rgmii_txc] |
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set_property PACKAGE_PIN R28 [get_ports rgmii_rx_ctl] |
set_property IOSTANDARD LVCMOS25 [get_ports rgmii_rx_ctl] |
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set_property PACKAGE_PIN U27 [get_ports rgmii_rxc] |
set_property IOSTANDARD LVCMOS25 [get_ports rgmii_rxc] |
# PHY-RST |
set_property PACKAGE_PIN L20 [get_ports phy_resetn] |
set_property IOSTANDARD LVCMOS25 [get_ports phy_resetn] |
/trunk/hw/layout/xdc/project_n1_t.sdc
0,0 → 1,32
# clk |
create_clock -name sys_clk_pin -period "5.0" [get_ports "sys_diff_clock_clk_p"] |
set_input_jitter sys_clk_pin 0.050 |
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# Associate the IDELAYCTRL in the support level to the I/Os in the core using IODELAYs |
#set_property IODELAY_GROUP tri_mode_ethernet_mac_iodelay_grp [get_cells {trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_idelayctrl_common_i}] |
set_property IODELAY_GROUP tri_mode_ethernet_mac_iodelay_grp [get_cells -hierarchical tri_mode_ethernet_mac_idelayctrl_common_i] |
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# Get auto-generated clock names |
set axi_clk_name [get_clocks -of [get_pins example_clocks/clock_generator/mmcm_adv_inst/CLKOUT1]] |
# => set MDC output delay |
set_output_delay -clock $axi_clk_name 1 [get_ports mdc] |
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# PHY-RST cut-off |
set_false_path -from [get_cells -hier -filter {name =~ *phy_resetn_int_reg}] -to [get_ports phy_resetn] |
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# Clock Crossing Constraints |
set_false_path -from [get_cells -hier -filter {name =~ *phy_resetn_int_reg}] -to [get_cells -hier -filter {name =~ *axi_lite_reset_gen/reset_sync*}] |
# +Ignore paths to resync flops |
set_false_path -to [get_pins -hier -filter {NAME =~ */reset_sync*/PRE}] |
set_false_path -to [get_pins -hier -filter {NAME =~ */*_sync*/D}] |
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# FIFO Clock Crossing Constraints: control signal is synched separately so this is a false path |
set_max_delay -from [get_cells -hier -filter {name =~ *rx_fifo_i/rd_addr_reg[*]}] -to [get_cells -hier -filter {name =~ *fifo*wr_rd_addr_reg[*]}] 3.2 -datapath_only |
set_max_delay -from [get_cells -hier -filter {name =~ *rx_fifo_i/wr_store_frame_tog_reg}] -to [get_cells -hier -filter {name =~ *fifo_i/resync_wr_store_frame_tog/data_sync_reg0}] 3.2 -datapath_only |
set_max_delay -from [get_cells -hier -filter {name =~ *rx_fifo_i/update_addr_tog_reg}] -to [get_cells -hier -filter {name =~ *rx_fifo_i/sync_rd_addr_tog/data_sync_reg0}] 3.2 -datapath_only |
set_max_delay -from [get_cells -hier -filter {name =~ *tx_fifo_i/rd_addr_txfer_reg[*]}] -to [get_cells -hier -filter {name =~ *fifo*wr_rd_addr_reg[*]}] 3.2 -datapath_only |
set_max_delay -from [get_cells -hier -filter {name =~ *tx_fifo_i/wr_frame_in_fifo_reg}] -to [get_cells -hier -filter {name =~ *tx_fifo_i/resync_wr_frame_in_fifo/data_sync_reg0}] 3.2 -datapath_only |
set_max_delay -from [get_cells -hier -filter {name =~ *tx_fifo_i/wr_frames_in_fifo_reg}] -to [get_cells -hier -filter {name =~ *tx_fifo_i/resync_wr_frames_in_fifo/data_sync_reg0}] 3.2 -datapath_only |
set_max_delay -from [get_cells -hier -filter {name =~ *tx_fifo_i/frame_in_fifo_valid_tog_reg}] -to [get_cells -hier -filter {name =~ *tx_fifo_i/resync_fif_valid_tog/data_sync_reg0}] 3.2 -datapath_only |
set_max_delay -from [get_cells -hier -filter {name =~ *tx_fifo_i/rd_txfer_tog_reg}] -to [get_cells -hier -filter {name =~ *tx_fifo_i/resync_rd_txfer_tog/data_sync_reg0}] 3.2 -datapath_only |
set_max_delay -from [get_cells -hier -filter {name =~ *tx_fifo_i/rd_tran_frame_tog_reg}] -to [get_cells -hier -filter {name =~ *tx_fifo_i/resync_rd_tran_frame_tog/data_sync_reg0}] 3.2 -datapath_only |
/trunk/hw/layout/xdc/project_n1_user_phytiming.xdc
0,0 → 1,22
# !!!tri_mode_ethernet_mac_0_user_phytiming.xdc |
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set rx_clk_var [get_clocks -of [get_ports rgmii_rxc]] |
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## If the interface timing constraints cannot be met then these can be relaxed by adjusting the values in this |
## xdc file which is set to be processed after all other xdc files |
## this also allows for the IODELAY tap delay setting to be adjusted without needing to modify the xdc's |
## provided with the core |
## All commands in this file can be used directly in the tcl command window if the synthesized or implemented design is open. |
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# The RGMII receive interface requirement allows a 1ns setup and 1ns hold - this is met but only just so constraints are relaxed |
#set_input_delay -clock [get_clocks tri_mode_ethernet_mac_0_rgmii_rx_clk] -max -1.5 [get_ports {rgmii_rxd[*] rgmii_rx_ctl}] |
#set_input_delay -clock [get_clocks tri_mode_ethernet_mac_0_rgmii_rx_clk] -min -2.8 [get_ports {rgmii_rxd[*] rgmii_rx_ctl}] |
#set_input_delay -clock [get_clocks tri_mode_ethernet_mac_0_rgmii_rx_clk] -clock_fall -max -1.5 -add_delay [get_ports {rgmii_rxd[*] rgmii_rx_ctl}] |
#set_input_delay -clock [get_clocks tri_mode_ethernet_mac_0_rgmii_rx_clk] -clock_fall -min -2.8 -add_delay [get_ports {rgmii_rxd[*] rgmii_rx_ctl}] |
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# the following properties can be adjusted if requried to adjuct the IO timing |
# the value shown is the default used by the IP |
# increasing this value will improve the hold timing but will also add jitter. |
#set_property IDELAY_VALUE 12 [get_cells {trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/*/rgmii_interface/delay_rgmii_rx* trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/*/rgmii_interface/rxdata_bus[*].delay_rgmii_rx*}] |
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/trunk/hw/layout/process.sh
0,0 → 1,40
#!/bin/bash |
|
# USAGE: ./process.sh |
# ARGs: |
# <none> |
# -o |
# -clr |
# -asm |
|
# qui-open |
if [ "$1" == "-o" ]; then |
cd process |
vivado ./project_n1.xpr |
exit 0 |
fi |
|
# clr |
rm -rf .Xil |
rm -rf process |
rm -rf *.jou |
rm -rf *.log |
if [ "$1" == "-clr" ]; then |
exit 0 |
fi |
|
# prep |
mkdir process |
cd process |
|
# prj-cre |
vivado -mode batch -source ../tcl/vsetup.tcl |
if [ "$1" == "-asm" ]; then |
exit 0 |
fi |
|
# prj-asm |
vivado -mode batch -source ../tcl/vrun.tcl |
|
# Final |
exit 0 |
/trunk/hw/msim/process.sh
0,0 → 1,107
#!/bin/bash |
# |
# USAGE: ./process.sh |
# ARGs: |
# <none> |
# -clr |
# -reasm |
# -fast |
|
|
ROOT_DIR=$PWD |
|
SOLIB_DEV_NAME="test_main" |
SOLIB_DEV_DIR="$PWD/../../sw/dev/${SOLIB_DEV_NAME}/src" |
SOLIB_DEV_FILE="$SOLIB_DEV_DIR/${SOLIB_DEV_NAME}.so" |
|
SOLIB_HOSTB_NAME="test_bfm" |
SOLIB_HOSTB_DIR="$PWD/../../sw/dev/${SOLIB_HOSTB_NAME}" |
SOLIB_HOSTB_FILE="$SOLIB_HOSTB_DIR/${SOLIB_HOSTB_NAME}.so" |
|
# |
# view |
if [ "$1" == "-view" ]; then |
vsim -view vsim.wlf -do wave.do |
exit 0 |
fi |
|
# |
# clr / 2FIX!!! |
find -type d -exec rm -rf {} + |
rm -rf *.h |
rm -rf *.tr |
#rm -rf work |
rm -rf *wlf* |
rm -rf *.hex |
rm -rf *.mem |
rm -rf *.ver |
rm -rf *.so |
rm -rf *.log |
rm -rf *.pcap |
rm -rf *.vstf |
rm -rf *.ini |
rm -rf compile.do |
rm -rf *transcript* |
if [ "$1" == "-clr" ]; then |
exit 0 |
fi |
|
# |
# q2-chk |
if [ ! -d ../layout/process/project_n1.ip_user_files/sim_scripts ]; then |
echo "V-ASM:" |
cd ../layout/ |
./process.sh -asm &> /dev/null |
cd $ROOT_DIR |
echo"" |
fi |
# ublaze-bsp |
if [ ! -d ../../sw/dev/test_main/process ]; then |
echo "BSP-ASM:" |
cd ../../sw/dev/test_main |
./process.sh -bsp &> /dev/null |
cd $ROOT_DIR |
echo"" |
fi |
# ublaze-app / so-lib |
if [ ! -f $SOLIB_DEV_FILE ] || [ "$1" == "-reasm" ]; then |
cd $SOLIB_DEV_DIR |
cmd="make" |
$cmd &> $ROOT_DIR/dpi-main.log || { |
echo "test_main MAKE failed" |
exit 1 |
} |
fi |
cd $ROOT_DIR |
rm -rf ./${SOLIB_DEV_NAME}.so |
cp -f $SOLIB_DEV_FILE ./ |
# host-bfm / so-lib |
if [ ! -f $SOLIB_HOSTB_FILE ] || [ "$1" == "-reasm" ]; then |
cd $SOLIB_HOSTB_DIR |
cmd="make" |
$cmd &> $ROOT_DIR/dpi-hostb.log || { |
echo "HOST_BFM MAKE failed" |
exit 1 |
} |
fi |
cd $ROOT_DIR |
rm -rf ./$SOLIB_HOSTB_NAME.so |
cp -f $SOLIB_HOSTB_FILE ./ |
|
# prep-var |
export LIB_DEV_NAME=$SOLIB_DEV_NAME |
export LIB_HOSTB_NAME=$SOLIB_HOSTB_NAME |
|
# start |
if [ "$1" == "-fast" ] || [ "$2" == "-fast" ] |
then |
export FAST_SIM=1 |
vsim -c -do start_sim.tcl |
else |
export FAST_SIM=0 |
vsim -do start_sim.tcl |
fi |
|
# |
#Final |
exit 0 |
/trunk/hw/msim/start_sim.tcl
0,0 → 1,122
# |
quit -sim |
|
# def names |
quietly set SCR_PATH "../layout/process/project_n1.ip_user_files/sim_scripts/bd/modelsim" |
quietly set CPU_FILES [list "microblaze_v9_5_vh_rfs.vhd" "base_microblaze_design_microblaze_0_0.vhd"] |
quietly set BD_SCR_FILE "compile.do" |
quietly set BD_SIM_FILE "simulate.do" |
|
# cfg-env |
quietly set FAST_SIM $::env(FAST_SIM) |
quietly set LIB_DEV_NAME $::env(LIB_DEV_NAME) |
quietly set LIB_HOSTB_NAME $::env(LIB_HOSTB_NAME) |
|
# ?? |
proc match_element {llist arg} { |
foreach idx $llist { |
if {$arg == $idx} { |
return 1 |
} |
} |
return 0 |
} |
|
|
# |
# cp+prep compile.do |
quietly set infile [open "$SCR_PATH/$BD_SCR_FILE" r] |
quietly set outfile [open $BD_SCR_FILE w] |
|
quietly set lines [split [read $infile] \n] |
quietly set skip_list [list] |
|
quietly set cpu_line_cnt 0 |
foreach line $lines { |
foreach idx $CPU_FILES { |
if {[ expr [regexp $idx $line] == 1]} { |
lappend skip_list [expr $cpu_line_cnt - 1] |
lappend skip_list [expr $cpu_line_cnt - 0] |
} |
} |
incr cpu_line_cnt |
} |
#puts "skip_list: $skip_list" |
quietly set cpu_line_cnt 0 |
foreach line $lines { |
if {[ expr [regexp "glbl.v" $line] == 1]} { |
incr cpu_line_cnt |
continue |
} |
if {[ expr [regexp "vmap" $line] == 1]} { |
incr cpu_line_cnt |
continue |
} |
if {[match_element $skip_list $cpu_line_cnt] == 1} { |
incr cpu_line_cnt |
continue |
} |
incr cpu_line_cnt |
|
set sitem0 "../../../ipstatic" |
set ritem0 "../layout/process/project_n1.ip_user_files/ipstatic" |
|
set sitem1 "../../../../project_n1.srcs" |
set ritem1 "../layout/process/project_n1.srcs" |
|
regsub -all "vlib work" $line " " line |
regsub -all " msim/" $line " " line |
regsub -all "vcom " $line "vcom -quiet " line |
regsub -all "vlog " $line "vlog -quiet " line |
|
regsub -all $sitem0 $line $ritem0 line |
regsub -all $sitem1 $line $ritem1 line |
|
puts $outfile $line |
} |
close $infile |
close $outfile |
|
# get LIB-list |
quietly set infile [open "$SCR_PATH/$BD_SIM_FILE" r] |
|
quietly set lines [split [read $infile] \n] |
foreach line $lines { |
if {[ expr [regexp "vsim" $line] != 1]} { |
continue |
} |
set sta_pos [string first "-L" $line] |
set stp_pos [string first " " $line [expr [string last "-L" $line] + 3]] |
set lib_list [string range $line $sta_pos $stp_pos] |
|
} |
close $infile |
# cut-out secureip-lib |
quietly regsub -all " -L secureip " $lib_list " " lib_list |
#puts "lib_list: $lib_list" |
|
# bd-files |
foreach idx [glob -type f -nocomplain "${SCR_PATH}/*.mem"] { |
file copy -force $idx ./ |
} |
source $BD_SCR_FILE |
vlog -quiet -work xil_defaultlib $SCR_PATH/glbl.v |
|
|
# user-src |
vlog -quiet -work xil_defaultlib -sv -f vlog_synth.f |
vlog -quiet -work xil_defaultlib +incdir+../src/tb/bfm_eth_log -sv -f vlog_sim.f |
|
# sim |
if { $FAST_SIM == 1 } { |
eval "vsim -sv_lib $LIB_DEV_NAME -sv_lib $LIB_HOSTB_NAME -quiet -t ps $lib_list xil_defaultlib.testcase xil_defaultlib.glbl" |
} else { |
eval "vsim -sv_lib $LIB_DEV_NAME -sv_lib $LIB_HOSTB_NAME -novopt -t ps $lib_list xil_defaultlib.testcase xil_defaultlib.glbl" |
|
log -r /* |
do wave.do |
} |
quietly set StdArithNoWarnings 1 |
quietly set NumericStdNoWarnings 1 |
|
run -all |
/trunk/hw/msim/vlog_sim.f
0,0 → 1,12
../src/tb/bfm_eth_log/pcap_pkg.sv |
../src/tb/bfm_eth_log/rgmii_rx_if.sv |
|
../src/tb/bfm_host/eth_host_bfm.sv |
|
../src/tb/bfm_ublaze/axi4_lite_master_bfm.sv |
../src/tb/bfm_ublaze/bfm_ublaze_pkg.sv |
../src/tb/bfm_ublaze/base_microblaze_design_microblaze_0_0.sv |
|
../src/tb/tb.sv |
|
../src/tc/testcase.sv |
/trunk/hw/msim/vlog_synth.f
0,0 → 1,15
../src/rtl/tri_mode_emac/src/common/tri_mode_ethernet_mac_0_reset_sync.v |
../src/rtl/tri_mode_emac/src/common/tri_mode_ethernet_mac_0_sync_block.v |
../src/rtl/tri_mode_emac/src/fifo/tri_mode_ethernet_mac_0_bram_tdp.v |
../src/rtl/tri_mode_emac/src/fifo/tri_mode_ethernet_mac_0_rx_client_fifo.v |
../src/rtl/tri_mode_emac/src/fifo/tri_mode_ethernet_mac_0_ten_100_1g_eth_fifo.v |
../src/rtl/tri_mode_emac/src/fifo/tri_mode_ethernet_mac_0_tx_client_fifo.v |
../src/rtl/tri_mode_emac/src/support/tri_mode_ethernet_mac_0_support.v |
../src/rtl/tri_mode_emac/src/support/tri_mode_ethernet_mac_0_support_clocking.v |
../src/rtl/tri_mode_emac/src/support/tri_mode_ethernet_mac_0_support_resets.v |
|
../src/rtl/tri_mode_emac_support/tri_mode_ethernet_mac_0_clk_wiz.v |
../src/rtl/tri_mode_emac_support/tri_mode_ethernet_mac_0_example_design_clocks.v |
../src/rtl/tri_mode_emac_support/tri_mode_ethernet_mac_0_example_design_resets.v |
|
../src/rtl/microb_top.v |
/trunk/hw/msim/wave.do
0,0 → 1,156
onerror {resume} |
quietly WaveActivateNextPane {} 0 |
add wave -noupdate -group dut.SYS_CON /testcase/tb/dut/glbl_rst |
add wave -noupdate -group dut.SYS_CON /testcase/tb/dut/sys_diff_clock_clk_n |
add wave -noupdate -group dut.SYS_CON /testcase/tb/dut/sys_diff_clock_clk_p |
add wave -noupdate -group dut.SYS_CON /testcase/tb/dut/u0/Clk |
add wave -noupdate -group dut.SYS_CON /testcase/tb/dut/u0/reset |
add wave -noupdate -group dut.RGMII /testcase/tb/dut/rgmii_txd |
add wave -noupdate -group dut.RGMII /testcase/tb/dut/rgmii_tx_ctl |
add wave -noupdate -group dut.RGMII /testcase/tb/dut/rgmii_txc |
add wave -noupdate -group dut.RGMII /testcase/tb/dut/rgmii_rxd |
add wave -noupdate -group dut.RGMII /testcase/tb/dut/rgmii_rx_ctl |
add wave -noupdate -group dut.RGMII /testcase/tb/dut/rgmii_rxc |
add wave -noupdate -group dut.MDIO /testcase/tb/dut/mdio |
add wave -noupdate -group dut.MDIO /testcase/tb/dut/mdc |
add wave -noupdate -divider {New Divider} |
add wave -noupdate -group u0.MB.AXIM.IF /testcase/tb/dut/u0/microblaze_0/M_AXI_DP_AWADDR |
add wave -noupdate -group u0.MB.AXIM.IF /testcase/tb/dut/u0/microblaze_0/M_AXI_DP_AWPROT |
add wave -noupdate -group u0.MB.AXIM.IF /testcase/tb/dut/u0/microblaze_0/M_AXI_DP_AWVALID |
add wave -noupdate -group u0.MB.AXIM.IF /testcase/tb/dut/u0/microblaze_0/M_AXI_DP_AWREADY |
add wave -noupdate -group u0.MB.AXIM.IF /testcase/tb/dut/u0/microblaze_0/M_AXI_DP_WDATA |
add wave -noupdate -group u0.MB.AXIM.IF /testcase/tb/dut/u0/microblaze_0/M_AXI_DP_WSTRB |
add wave -noupdate -group u0.MB.AXIM.IF /testcase/tb/dut/u0/microblaze_0/M_AXI_DP_WVALID |
add wave -noupdate -group u0.MB.AXIM.IF /testcase/tb/dut/u0/microblaze_0/M_AXI_DP_WREADY |
add wave -noupdate -group u0.MB.AXIM.IF /testcase/tb/dut/u0/microblaze_0/M_AXI_DP_BRESP |
add wave -noupdate -group u0.MB.AXIM.IF /testcase/tb/dut/u0/microblaze_0/M_AXI_DP_BVALID |
add wave -noupdate -group u0.MB.AXIM.IF /testcase/tb/dut/u0/microblaze_0/M_AXI_DP_BREADY |
add wave -noupdate -group u0.MB.AXIM.IF /testcase/tb/dut/u0/microblaze_0/M_AXI_DP_ARADDR |
add wave -noupdate -group u0.MB.AXIM.IF /testcase/tb/dut/u0/microblaze_0/M_AXI_DP_ARPROT |
add wave -noupdate -group u0.MB.AXIM.IF /testcase/tb/dut/u0/microblaze_0/M_AXI_DP_ARVALID |
add wave -noupdate -group u0.MB.AXIM.IF /testcase/tb/dut/u0/microblaze_0/M_AXI_DP_ARREADY |
add wave -noupdate -group u0.MB.AXIM.IF /testcase/tb/dut/u0/microblaze_0/M_AXI_DP_RDATA |
add wave -noupdate -group u0.MB.AXIM.IF /testcase/tb/dut/u0/microblaze_0/M_AXI_DP_RRESP |
add wave -noupdate -group u0.MB.AXIM.IF /testcase/tb/dut/u0/microblaze_0/M_AXI_DP_RVALID |
add wave -noupdate -group u0.MB.AXIM.IF /testcase/tb/dut/u0/microblaze_0/M_AXI_DP_RREADY |
add wave -noupdate -group u0.TMEMAC.AXIS.IF /testcase/tb/dut/u0/tri_mode_emac_0/s_axi_aclk |
add wave -noupdate -group u0.TMEMAC.AXIS.IF /testcase/tb/dut/u0/tri_mode_emac_0/s_axi_resetn |
add wave -noupdate -group u0.TMEMAC.AXIS.IF /testcase/tb/dut/u0/tri_mode_emac_0/s_axi_awaddr |
add wave -noupdate -group u0.TMEMAC.AXIS.IF /testcase/tb/dut/u0/tri_mode_emac_0/s_axi_awvalid |
add wave -noupdate -group u0.TMEMAC.AXIS.IF /testcase/tb/dut/u0/tri_mode_emac_0/s_axi_awready |
add wave -noupdate -group u0.TMEMAC.AXIS.IF /testcase/tb/dut/u0/tri_mode_emac_0/s_axi_wdata |
add wave -noupdate -group u0.TMEMAC.AXIS.IF /testcase/tb/dut/u0/tri_mode_emac_0/s_axi_wvalid |
add wave -noupdate -group u0.TMEMAC.AXIS.IF /testcase/tb/dut/u0/tri_mode_emac_0/s_axi_wready |
add wave -noupdate -group u0.TMEMAC.AXIS.IF /testcase/tb/dut/u0/tri_mode_emac_0/s_axi_bresp |
add wave -noupdate -group u0.TMEMAC.AXIS.IF /testcase/tb/dut/u0/tri_mode_emac_0/s_axi_bvalid |
add wave -noupdate -group u0.TMEMAC.AXIS.IF /testcase/tb/dut/u0/tri_mode_emac_0/s_axi_bready |
add wave -noupdate -group u0.TMEMAC.AXIS.IF /testcase/tb/dut/u0/tri_mode_emac_0/s_axi_araddr |
add wave -noupdate -group u0.TMEMAC.AXIS.IF /testcase/tb/dut/u0/tri_mode_emac_0/s_axi_arvalid |
add wave -noupdate -group u0.TMEMAC.AXIS.IF /testcase/tb/dut/u0/tri_mode_emac_0/s_axi_arready |
add wave -noupdate -group u0.TMEMAC.AXIS.IF /testcase/tb/dut/u0/tri_mode_emac_0/s_axi_rdata |
add wave -noupdate -group u0.TMEMAC.AXIS.IF /testcase/tb/dut/u0/tri_mode_emac_0/s_axi_rresp |
add wave -noupdate -group u0.TMEMAC.AXIS.IF /testcase/tb/dut/u0/tri_mode_emac_0/s_axi_rvalid |
add wave -noupdate -group u0.TMEMAC.AXIS.IF /testcase/tb/dut/u0/tri_mode_emac_0/s_axi_rready |
add wave -noupdate -expand -group u0.AXIDMA -group MM2S.AXIM.IF /testcase/tb/dut/u0/axi_dma_0/m_axi_mm2s_araddr |
add wave -noupdate -expand -group u0.AXIDMA -group MM2S.AXIM.IF /testcase/tb/dut/u0/axi_dma_0/m_axi_mm2s_arlen |
add wave -noupdate -expand -group u0.AXIDMA -group MM2S.AXIM.IF /testcase/tb/dut/u0/axi_dma_0/m_axi_mm2s_arsize |
add wave -noupdate -expand -group u0.AXIDMA -group MM2S.AXIM.IF /testcase/tb/dut/u0/axi_dma_0/m_axi_mm2s_arburst |
add wave -noupdate -expand -group u0.AXIDMA -group MM2S.AXIM.IF /testcase/tb/dut/u0/axi_dma_0/m_axi_mm2s_arprot |
add wave -noupdate -expand -group u0.AXIDMA -group MM2S.AXIM.IF /testcase/tb/dut/u0/axi_dma_0/m_axi_mm2s_arcache |
add wave -noupdate -expand -group u0.AXIDMA -group MM2S.AXIM.IF /testcase/tb/dut/u0/axi_dma_0/m_axi_mm2s_arvalid |
add wave -noupdate -expand -group u0.AXIDMA -group MM2S.AXIM.IF /testcase/tb/dut/u0/axi_dma_0/m_axi_mm2s_arready |
add wave -noupdate -expand -group u0.AXIDMA -group MM2S.AXIM.IF /testcase/tb/dut/u0/axi_dma_0/m_axi_mm2s_rdata |
add wave -noupdate -expand -group u0.AXIDMA -group MM2S.AXIM.IF /testcase/tb/dut/u0/axi_dma_0/m_axi_mm2s_rresp |
add wave -noupdate -expand -group u0.AXIDMA -group MM2S.AXIM.IF /testcase/tb/dut/u0/axi_dma_0/m_axi_mm2s_rlast |
add wave -noupdate -expand -group u0.AXIDMA -group MM2S.AXIM.IF /testcase/tb/dut/u0/axi_dma_0/m_axi_mm2s_rvalid |
add wave -noupdate -expand -group u0.AXIDMA -group MM2S.AXIM.IF /testcase/tb/dut/u0/axi_dma_0/m_axi_mm2s_rready |
add wave -noupdate -expand -group u0.AXIDMA -group MM2S.AXIS-S.IF /testcase/tb/dut/u0/axi_dma_0/m_axis_mm2s_tdata |
add wave -noupdate -expand -group u0.AXIDMA -group MM2S.AXIS-S.IF /testcase/tb/dut/u0/axi_dma_0/m_axis_mm2s_tkeep |
add wave -noupdate -expand -group u0.AXIDMA -group MM2S.AXIS-S.IF /testcase/tb/dut/u0/axi_dma_0/m_axis_mm2s_tvalid |
add wave -noupdate -expand -group u0.AXIDMA -group MM2S.AXIS-S.IF /testcase/tb/dut/u0/axi_dma_0/m_axis_mm2s_tready |
add wave -noupdate -expand -group u0.AXIDMA -group MM2S.AXIS-S.IF /testcase/tb/dut/u0/axi_dma_0/m_axis_mm2s_tlast |
add wave -noupdate -expand -group u0.AXIDMA -group S2MM.AXIM.IF /testcase/tb/dut/u0/axi_dma_0/m_axi_s2mm_awaddr |
add wave -noupdate -expand -group u0.AXIDMA -group S2MM.AXIM.IF /testcase/tb/dut/u0/axi_dma_0/m_axi_s2mm_awlen |
add wave -noupdate -expand -group u0.AXIDMA -group S2MM.AXIM.IF /testcase/tb/dut/u0/axi_dma_0/m_axi_s2mm_awsize |
add wave -noupdate -expand -group u0.AXIDMA -group S2MM.AXIM.IF /testcase/tb/dut/u0/axi_dma_0/m_axi_s2mm_awburst |
add wave -noupdate -expand -group u0.AXIDMA -group S2MM.AXIM.IF /testcase/tb/dut/u0/axi_dma_0/m_axi_s2mm_awprot |
add wave -noupdate -expand -group u0.AXIDMA -group S2MM.AXIM.IF /testcase/tb/dut/u0/axi_dma_0/m_axi_s2mm_awcache |
add wave -noupdate -expand -group u0.AXIDMA -group S2MM.AXIM.IF /testcase/tb/dut/u0/axi_dma_0/m_axi_s2mm_awvalid |
add wave -noupdate -expand -group u0.AXIDMA -group S2MM.AXIM.IF /testcase/tb/dut/u0/axi_dma_0/m_axi_s2mm_awready |
add wave -noupdate -expand -group u0.AXIDMA -group S2MM.AXIM.IF /testcase/tb/dut/u0/axi_dma_0/m_axi_s2mm_wdata |
add wave -noupdate -expand -group u0.AXIDMA -group S2MM.AXIM.IF /testcase/tb/dut/u0/axi_dma_0/m_axi_s2mm_wstrb |
add wave -noupdate -expand -group u0.AXIDMA -group S2MM.AXIM.IF /testcase/tb/dut/u0/axi_dma_0/m_axi_s2mm_wlast |
add wave -noupdate -expand -group u0.AXIDMA -group S2MM.AXIM.IF /testcase/tb/dut/u0/axi_dma_0/m_axi_s2mm_wvalid |
add wave -noupdate -expand -group u0.AXIDMA -group S2MM.AXIM.IF /testcase/tb/dut/u0/axi_dma_0/m_axi_s2mm_wready |
add wave -noupdate -expand -group u0.AXIDMA -group S2MM.AXIM.IF /testcase/tb/dut/u0/axi_dma_0/m_axi_s2mm_bresp |
add wave -noupdate -expand -group u0.AXIDMA -group S2MM.AXIM.IF /testcase/tb/dut/u0/axi_dma_0/m_axi_s2mm_bvalid |
add wave -noupdate -expand -group u0.AXIDMA -group S2MM.AXIM.IF /testcase/tb/dut/u0/axi_dma_0/m_axi_s2mm_bready |
add wave -noupdate -expand -group u0.AXIDMA -group S2MM.AXIS-S.IF /testcase/tb/dut/u0/axi_dma_0/s_axis_s2mm_tdata |
add wave -noupdate -expand -group u0.AXIDMA -group S2MM.AXIS-S.IF /testcase/tb/dut/u0/axi_dma_0/s_axis_s2mm_tkeep |
add wave -noupdate -expand -group u0.AXIDMA -group S2MM.AXIS-S.IF /testcase/tb/dut/u0/axi_dma_0/s_axis_s2mm_tvalid |
add wave -noupdate -expand -group u0.AXIDMA -group S2MM.AXIS-S.IF /testcase/tb/dut/u0/axi_dma_0/s_axis_s2mm_tready |
add wave -noupdate -expand -group u0.AXIDMA -group S2MM.AXIS-S.IF /testcase/tb/dut/u0/axi_dma_0/s_axis_s2mm_tlast |
add wave -noupdate -group u0.BRAM -group AXIS /testcase/tb/dut/u0/axi_bram_ctrl_0/s_axi_awid |
add wave -noupdate -group u0.BRAM -group AXIS /testcase/tb/dut/u0/axi_bram_ctrl_0/s_axi_awaddr |
add wave -noupdate -group u0.BRAM -group AXIS /testcase/tb/dut/u0/axi_bram_ctrl_0/s_axi_awlen |
add wave -noupdate -group u0.BRAM -group AXIS /testcase/tb/dut/u0/axi_bram_ctrl_0/s_axi_awsize |
add wave -noupdate -group u0.BRAM -group AXIS /testcase/tb/dut/u0/axi_bram_ctrl_0/s_axi_awburst |
add wave -noupdate -group u0.BRAM -group AXIS /testcase/tb/dut/u0/axi_bram_ctrl_0/s_axi_awlock |
add wave -noupdate -group u0.BRAM -group AXIS /testcase/tb/dut/u0/axi_bram_ctrl_0/s_axi_awcache |
add wave -noupdate -group u0.BRAM -group AXIS /testcase/tb/dut/u0/axi_bram_ctrl_0/s_axi_awprot |
add wave -noupdate -group u0.BRAM -group AXIS /testcase/tb/dut/u0/axi_bram_ctrl_0/s_axi_awvalid |
add wave -noupdate -group u0.BRAM -group AXIS /testcase/tb/dut/u0/axi_bram_ctrl_0/s_axi_awready |
add wave -noupdate -group u0.BRAM -group AXIS /testcase/tb/dut/u0/axi_bram_ctrl_0/s_axi_wdata |
add wave -noupdate -group u0.BRAM -group AXIS /testcase/tb/dut/u0/axi_bram_ctrl_0/s_axi_wstrb |
add wave -noupdate -group u0.BRAM -group AXIS /testcase/tb/dut/u0/axi_bram_ctrl_0/s_axi_wlast |
add wave -noupdate -group u0.BRAM -group AXIS /testcase/tb/dut/u0/axi_bram_ctrl_0/s_axi_wvalid |
add wave -noupdate -group u0.BRAM -group AXIS /testcase/tb/dut/u0/axi_bram_ctrl_0/s_axi_wready |
add wave -noupdate -group u0.BRAM -group AXIS /testcase/tb/dut/u0/axi_bram_ctrl_0/s_axi_bid |
add wave -noupdate -group u0.BRAM -group AXIS /testcase/tb/dut/u0/axi_bram_ctrl_0/s_axi_bresp |
add wave -noupdate -group u0.BRAM -group AXIS /testcase/tb/dut/u0/axi_bram_ctrl_0/s_axi_bvalid |
add wave -noupdate -group u0.BRAM -group AXIS /testcase/tb/dut/u0/axi_bram_ctrl_0/s_axi_bready |
add wave -noupdate -group u0.BRAM -group AXIS /testcase/tb/dut/u0/axi_bram_ctrl_0/s_axi_arid |
add wave -noupdate -group u0.BRAM -group AXIS /testcase/tb/dut/u0/axi_bram_ctrl_0/s_axi_araddr |
add wave -noupdate -group u0.BRAM -group AXIS /testcase/tb/dut/u0/axi_bram_ctrl_0/s_axi_arlen |
add wave -noupdate -group u0.BRAM -group AXIS /testcase/tb/dut/u0/axi_bram_ctrl_0/s_axi_arsize |
add wave -noupdate -group u0.BRAM -group AXIS /testcase/tb/dut/u0/axi_bram_ctrl_0/s_axi_arburst |
add wave -noupdate -group u0.BRAM -group AXIS /testcase/tb/dut/u0/axi_bram_ctrl_0/s_axi_arlock |
add wave -noupdate -group u0.BRAM -group AXIS /testcase/tb/dut/u0/axi_bram_ctrl_0/s_axi_arcache |
add wave -noupdate -group u0.BRAM -group AXIS /testcase/tb/dut/u0/axi_bram_ctrl_0/s_axi_arprot |
add wave -noupdate -group u0.BRAM -group AXIS /testcase/tb/dut/u0/axi_bram_ctrl_0/s_axi_arvalid |
add wave -noupdate -group u0.BRAM -group AXIS /testcase/tb/dut/u0/axi_bram_ctrl_0/s_axi_arready |
add wave -noupdate -group u0.BRAM -group AXIS /testcase/tb/dut/u0/axi_bram_ctrl_0/s_axi_rid |
add wave -noupdate -group u0.BRAM -group AXIS /testcase/tb/dut/u0/axi_bram_ctrl_0/s_axi_rdata |
add wave -noupdate -group u0.BRAM -group AXIS /testcase/tb/dut/u0/axi_bram_ctrl_0/s_axi_rresp |
add wave -noupdate -group u0.BRAM -group AXIS /testcase/tb/dut/u0/axi_bram_ctrl_0/s_axi_rlast |
add wave -noupdate -group u0.BRAM -group AXIS /testcase/tb/dut/u0/axi_bram_ctrl_0/s_axi_rvalid |
add wave -noupdate -group u0.BRAM -group AXIS /testcase/tb/dut/u0/axi_bram_ctrl_0/s_axi_rready |
add wave -noupdate -group u0.BRAM -group BRAM /testcase/tb/dut/u0/axi_bram_ctrl_0/bram_en_a |
add wave -noupdate -group u0.BRAM -group BRAM /testcase/tb/dut/u0/axi_bram_ctrl_0/bram_we_a |
add wave -noupdate -group u0.BRAM -group BRAM /testcase/tb/dut/u0/axi_bram_ctrl_0/bram_addr_a |
add wave -noupdate -group u0.BRAM -group BRAM /testcase/tb/dut/u0/axi_bram_ctrl_0/bram_wrdata_a |
add wave -noupdate -group u0.BRAM -group BRAM /testcase/tb/dut/u0/axi_bram_ctrl_0/bram_rddata_a |
add wave -noupdate -group u0.BRAM -group BRAM /testcase/tb/dut/u0/axi_bram_ctrl_0/bram_en_b |
add wave -noupdate -group u0.BRAM -group BRAM /testcase/tb/dut/u0/axi_bram_ctrl_0/bram_we_b |
add wave -noupdate -group u0.BRAM -group BRAM /testcase/tb/dut/u0/axi_bram_ctrl_0/bram_addr_b |
add wave -noupdate -group u0.BRAM -group BRAM /testcase/tb/dut/u0/axi_bram_ctrl_0/bram_wrdata_b |
add wave -noupdate -group u0.BRAM -group BRAM /testcase/tb/dut/u0/axi_bram_ctrl_0/bram_rddata_b |
add wave -noupdate -divider {New Divider} |
TreeUpdate [SetDefaultTree] |
WaveRestoreCursors {{Cursor 1} {830667500 ps} 0} |
quietly wave cursor active 1 |
configure wave -namecolwidth 421 |
configure wave -valuecolwidth 100 |
configure wave -justifyvalue left |
configure wave -signalnamewidth 0 |
configure wave -snapdistance 10 |
configure wave -datasetprefix 0 |
configure wave -rowmargin 4 |
configure wave -childrowmargin 2 |
configure wave -gridoffset 0 |
configure wave -gridperiod 1 |
configure wave -griddelta 40 |
configure wave -timeline 0 |
configure wave -timelineunits ns |
update |
WaveRestoreZoom {0 ps} {1154520675 ps} |
/trunk/hw/src/rtl/tri_mode_emac/src/common/tri_mode_ethernet_mac_0_reset_sync.v
0,0 → 1,143
//------------------------------------------------------------------------------ |
// Title : Synchronous Reset generation flip-flop pair |
// Project : Tri-Mode ethernet MAC |
//------------------------------------------------------------------------------ |
// File : tri_mode_ethernet_mac_0_reset_sync.v |
// Author : Xilinx, Inc. |
//------------------------------------------------------------------------------ |
// Description: All flip-flops have the same asynchronous reset signal. |
// Together the flops create a minimum of a 1 clock period |
// duration pulse which is used for synchronous reset. |
// |
// The flops are placed, using the ASYNC_REG atrtribute, into the |
// same slice. |
// |
// ----------------------------------------------------------------------------- |
// (c) Copyright 2006-2008 Xilinx, Inc. All rights reserved. |
// |
// This file contains confidential and proprietary information |
// of Xilinx, Inc. and is protected under U.S. and |
// international copyright and other intellectual property |
// laws. |
// |
// DISCLAIMER |
// This disclaimer is not a license and does not grant any |
// rights to the materials distributed herewith. Except as |
// otherwise provided in a valid license issued to you by |
// Xilinx, and to the maximum extent permitted by applicable |
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND |
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES |
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING |
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- |
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and |
// (2) Xilinx shall not be liable (whether in contract or tort, |
// including negligence, or under any other theory of |
// liability) for any loss or damage of any kind or nature |
// related to, arising under or in connection with these |
// materials, including for any direct, or any indirect, |
// special, incidental, or consequential loss or damage |
// (including loss of data, profits, goodwill, or any type of |
// loss or damage suffered as a result of any action brought |
// by a third party) even if such damage or loss was |
// reasonably foreseeable or Xilinx had been advised of the |
// possibility of the same. |
// |
// CRITICAL APPLICATIONS |
// Xilinx products are not designed or intended to be fail- |
// safe, or for use in any application requiring fail-safe |
// performance, such as life-support or safety devices or |
// systems, Class III medical devices, nuclear facilities, |
// applications related to the deployment of airbags, or any |
// other applications that could lead to death, personal |
// injury, or severe property or environmental damage |
// (individually and collectively, "Critical |
// Applications"). Customer assumes the sole risk and |
// liability of any use of Xilinx products in Critical |
// Applications, subject only to applicable laws and |
// regulations governing limitations on product liability. |
// |
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS |
// PART OF THIS FILE AT ALL TIMES. |
// ----------------------------------------------------------------------------- |
|
`timescale 1ps/1ps |
|
(* dont_touch = "yes" *) |
module tri_mode_ethernet_mac_0_reset_sync #( |
parameter INITIALISE = 1'b1, |
parameter DEPTH = 5 |
) |
( |
input reset_in, |
input clk, |
input enable, |
output reset_out |
); |
|
|
wire reset_sync_reg0; |
wire reset_sync_reg1; |
wire reset_sync_reg2; |
wire reset_sync_reg3; |
wire reset_sync_reg4; |
|
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *) |
FDPE #( |
.INIT (INITIALISE[0]) |
) reset_sync0 ( |
.C (clk), |
.CE (enable), |
.PRE(reset_in), |
.D (1'b0), |
.Q (reset_sync_reg0) |
); |
|
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *) |
FDPE #( |
.INIT (INITIALISE[0]) |
) reset_sync1 ( |
.C (clk), |
.CE (enable), |
.PRE(reset_in), |
.D (reset_sync_reg0), |
.Q (reset_sync_reg1) |
); |
|
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *) |
FDPE #( |
.INIT (INITIALISE[0]) |
) reset_sync2 ( |
.C (clk), |
.CE (enable), |
.PRE(reset_in), |
.D (reset_sync_reg1), |
.Q (reset_sync_reg2) |
); |
|
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *) |
FDPE #( |
.INIT (INITIALISE[0]) |
) reset_sync3 ( |
.C (clk), |
.CE (enable), |
.PRE(reset_in), |
.D (reset_sync_reg2), |
.Q (reset_sync_reg3) |
); |
|
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *) |
FDPE #( |
.INIT (INITIALISE[0]) |
) reset_sync4 ( |
.C (clk), |
.CE (enable), |
.PRE(reset_in), |
.D (reset_sync_reg3), |
.Q (reset_sync_reg4) |
); |
|
|
assign reset_out = reset_sync_reg4; |
|
|
endmodule |
/trunk/hw/src/rtl/tri_mode_emac/src/common/tri_mode_ethernet_mac_0_sync_block.v
0,0 → 1,141
//------------------------------------------------------------------------------ |
// Title : CDC Sync Block |
// Project : Tri-Mode Ethernet MAC |
//------------------------------------------------------------------------------ |
// File : tri_mode_ethernet_mac_0_sync_block.v |
// Author : Xilinx Inc. |
//------------------------------------------------------------------------------ |
// Description: Used on signals crossing from one clock domain to another, this |
// is a multiple flip-flop pipeline, with all flops placed together |
// into the same slice. Thus the routing delay between the two is |
// minimum to safe-guard against metastability issues. |
// ----------------------------------------------------------------------------- |
// (c) Copyright 2001-2013 Xilinx, Inc. All rights reserved. |
// |
// This file contains confidential and proprietary information |
// of Xilinx, Inc. and is protected under U.S. and |
// international copyright and other intellectual property |
// laws. |
// |
// DISCLAIMER |
// This disclaimer is not a license and does not grant any |
// rights to the materials distributed herewith. Except as |
// otherwise provided in a valid license issued to you by |
// Xilinx, and to the maximum extent permitted by applicable |
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND |
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES |
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING |
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- |
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and |
// (2) Xilinx shall not be liable (whether in contract or tort, |
// including negligence, or under any other theory of |
// liability) for any loss or damage of any kind or nature |
// related to, arising under or in connection with these |
// materials, including for any direct, or any indirect, |
// special, incidental, or consequential loss or damage |
// (including loss of data, profits, goodwill, or any type of |
// loss or damage suffered as a result of any action brought |
// by a third party) even if such damage or loss was |
// reasonably foreseeable or Xilinx had been advised of the |
// possibility of the same. |
// |
// CRITICAL APPLICATIONS |
// Xilinx products are not designed or intended to be fail- |
// safe, or for use in any application requiring fail-safe |
// performance, such as life-support or safety devices or |
// systems, Class III medical devices, nuclear facilities, |
// applications related to the deployment of airbags, or any |
// other applications that could lead to death, personal |
// injury, or severe property or environmental damage |
// (individually and collectively, "Critical |
// Applications"). Customer assumes the sole risk and |
// liability of any use of Xilinx products in Critical |
// Applications, subject only to applicable laws and |
// regulations governing limitations on product liability. |
// |
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS |
// PART OF THIS FILE AT ALL TIMES. |
// ----------------------------------------------------------------------------- |
|
`timescale 1ps / 1ps |
|
(* dont_touch = "yes" *) |
module tri_mode_ethernet_mac_0_sync_block #( |
parameter INITIALISE = 1'b0, |
parameter DEPTH = 5 |
) |
( |
input clk, // clock to be sync'ed to |
input data_in, // Data to be 'synced' |
output data_out // synced data |
); |
|
// Internal Signals |
wire data_sync0; |
wire data_sync1; |
wire data_sync2; |
wire data_sync3; |
wire data_sync4; |
|
|
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *) |
FDRE #( |
.INIT (INITIALISE[0]) |
) data_sync_reg0 ( |
.C (clk), |
.D (data_in), |
.Q (data_sync0), |
.CE (1'b1), |
.R (1'b0) |
); |
|
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *) |
FDRE #( |
.INIT (INITIALISE[0]) |
) data_sync_reg1 ( |
.C (clk), |
.D (data_sync0), |
.Q (data_sync1), |
.CE (1'b1), |
.R (1'b0) |
); |
|
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *) |
FDRE #( |
.INIT (INITIALISE[0]) |
) data_sync_reg2 ( |
.C (clk), |
.D (data_sync1), |
.Q (data_sync2), |
.CE (1'b1), |
.R (1'b0) |
); |
|
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *) |
FDRE #( |
.INIT (INITIALISE[0]) |
) data_sync_reg3 ( |
.C (clk), |
.D (data_sync2), |
.Q (data_sync3), |
.CE (1'b1), |
.R (1'b0) |
); |
|
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *) |
FDRE #( |
.INIT (INITIALISE[0]) |
) data_sync_reg4 ( |
.C (clk), |
.D (data_sync3), |
.Q (data_sync4), |
.CE (1'b1), |
.R (1'b0) |
); |
|
assign data_out = data_sync4; |
|
|
endmodule |
|
|
/trunk/hw/src/rtl/tri_mode_emac/src/fifo/tri_mode_ethernet_mac_0_bram_tdp.v
0,0 → 1,107
//------------------------------------------------------------------------------ |
// Title : RAM memory for RX and TX client FIFOs |
// Version : 1.0 |
// Project : Tri-Mode Ethernet MAC |
//------------------------------------------------------------------------------ |
// File : tri_mode_ethernet_mac_0_bram_tdp.v |
// Author : Xilinx Inc. |
// ----------------------------------------------------------------------------- |
// (c) Copyright 2013 Xilinx, Inc. All rights reserved. |
// |
// This file contains confidential and proprietary information |
// of Xilinx, Inc. and is protected under U.S. and |
// international copyright and other intellectual property |
// laws. |
// |
// DISCLAIMER |
// This disclaimer is not a license and does not grant any |
// rights to the materials distributed herewith. Except as |
// otherwise provided in a valid license issued to you by |
// Xilinx, and to the maximum extent permitted by applicable |
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND |
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES |
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING |
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- |
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and |
// (2) Xilinx shall not be liable (whether in contract or tort, |
// including negligence, or under any other theory of |
// liability) for any loss or damage of any kind or nature |
// related to, arising under or in connection with these |
// materials, including for any direct, or any indirect, |
// special, incidental, or consequential loss or damage |
// (including loss of data, profits, goodwill, or any type of |
// loss or damage suffered as a result of any action brought |
// by a third party) even if such damage or loss was |
// reasonably foreseeable or Xilinx had been advised of the |
// possibility of the same. |
// |
// CRITICAL APPLICATIONS |
// Xilinx products are not designed or intended to be fail- |
// safe, or for use in any application requiring fail-safe |
// performance, such as life-support or safety devices or |
// systems, Class III medical devices, nuclear facilities, |
// applications related to the deployment of airbags, or any |
// other applications that could lead to death, personal |
// injury, or severe property or environmental damage |
// (individually and collectively, "Critical |
// Applications"). Customer assumes the sole risk and |
// liability of any use of Xilinx products in Critical |
// Applications, subject only to applicable laws and |
// regulations governing limitations on product liability. |
// |
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS |
// PART OF THIS FILE AT ALL TIMES. |
// ----------------------------------------------------------------------------- |
// Description: This is a parameterized inferred block RAM |
// |
//------------------------------------------------------------------------------ |
|
`timescale 1ps / 1ps |
|
//------------------------------------------------------------------------------ |
// The module declaration for the block RAM |
//------------------------------------------------------------------------------ |
|
|
module tri_mode_ethernet_mac_0_bram_tdp #( |
parameter DATA_WIDTH = 8, |
parameter ADDR_WIDTH = 12 |
) ( |
// Port A |
input wire a_clk, |
input wire a_rst, |
input wire a_wr, |
input wire [ADDR_WIDTH-1:0] a_addr, |
input wire [DATA_WIDTH-1:0] a_din, |
|
// Port B |
input wire b_clk, |
input wire b_en, |
input wire b_rst, |
input wire [ADDR_WIDTH-1:0] b_addr, |
output reg [DATA_WIDTH-1:0] b_dout |
); |
|
// Shared memory |
localparam RAM_DEPTH = 2 ** ADDR_WIDTH; |
reg [DATA_WIDTH-1:0] mem [RAM_DEPTH-1:0]; |
|
// To write use port A |
always @(posedge a_clk) |
begin |
if(!a_rst && a_wr) begin |
mem[a_addr] <= a_din; |
end |
end |
|
// To read use Port B |
always @(posedge b_clk) |
begin |
if(b_rst) |
b_dout <= {DATA_WIDTH{1'b0}}; |
else if(b_en) |
b_dout <= mem[b_addr]; |
end |
|
endmodule |
|
/trunk/hw/src/rtl/tri_mode_emac/src/fifo/tri_mode_ethernet_mac_0_rx_client_fifo.v
0,0 → 1,868
//------------------------------------------------------------------------------ |
// Title : Receiver FIFO with AxiStream interfaces |
// Version : 1.3 |
// Project : Tri-Mode Ethernet MAC |
//------------------------------------------------------------------------------ |
// File : tri_mode_ethernet_mac_0_rx_client_fifo.v |
// Author : Xilinx Inc. |
// ----------------------------------------------------------------------------- |
// (c) Copyright 2004-2013 Xilinx, Inc. All rights reserved. |
// |
// This file contains confidential and proprietary information |
// of Xilinx, Inc. and is protected under U.S. and |
// international copyright and other intellectual property |
// laws. |
// |
// DISCLAIMER |
// This disclaimer is not a license and does not grant any |
// rights to the materials distributed herewith. Except as |
// otherwise provided in a valid license issued to you by |
// Xilinx, and to the maximum extent permitted by applicable |
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND |
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES |
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING |
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- |
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and |
// (2) Xilinx shall not be liable (whether in contract or tort, |
// including negligence, or under any other theory of |
// liability) for any loss or damage of any kind or nature |
// related to, arising under or in connection with these |
// materials, including for any direct, or any indirect, |
// special, incidental, or consequential loss or damage |
// (including loss of data, profits, goodwill, or any type of |
// loss or damage suffered as a result of any action brought |
// by a third party) even if such damage or loss was |
// reasonably foreseeable or Xilinx had been advised of the |
// possibility of the same. |
// |
// CRITICAL APPLICATIONS |
// Xilinx products are not designed or intended to be fail- |
// safe, or for use in any application requiring fail-safe |
// performance, such as life-support or safety devices or |
// systems, Class III medical devices, nuclear facilities, |
// applications related to the deployment of airbags, or any |
// other applications that could lead to death, personal |
// injury, or severe property or environmental damage |
// (individually and collectively, "Critical |
// Applications"). Customer assumes the sole risk and |
// liability of any use of Xilinx products in Critical |
// Applications, subject only to applicable laws and |
// regulations governing limitations on product liability. |
// |
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS |
// PART OF THIS FILE AT ALL TIMES. |
// ----------------------------------------------------------------------------- |
// Description: This is the receiver side FIFO for the design example |
// of the Tri-Mode Ethernet MAC core. AxiStream interfaces are used. |
// |
// The FIFO is built around an Inferred Dual Port RAM, |
// giving a total memory capacity of 4096 bytes. |
// |
// Frame data received from the MAC receiver is written into the |
// FIFO on the rx_mac_aclk. An end-of-frame marker is written to |
// the BRAM parity bit on the last byte of data stored for a frame. |
// This acts as frame deliniation. |
// |
// The rx_axis_mac_tvalid, rx_axis_mac_tlast, and rx_axis_mac_tuser signals |
// qualify the frame. A frame which ends with rx_axis_mac_tuser asserted |
// indicates a bad frame and will cause the FIFO write address |
// pointer to be reset to the base address of that frame. In this |
// way the bad frame will be overwritten with the next received |
// frame and is therefore dropped from the FIFO. |
// |
// Frames will also be dropped from the FIFO if an overflow occurs. |
// If there is not enough memory capacity in the FIFO to store the |
// whole of an incoming frame, the write address pointer will be |
// reset and the overflow signal asserted. |
// |
// When there is at least one complete frame in the FIFO, |
// the 8-bit AxiStream read interface's rx_axis_fifo_tvalid signal will |
// be enabled allowing data to be read from the FIFO. |
// |
// The FIFO has been designed to operate with different clocks |
// on the write and read sides. The read clock (user side) should |
// always operate at an equal or faster frequency than the write |
// clock (MAC side). |
// |
// The FIFO is designed to work with a minimum frame length of 8 |
// bytes. |
// |
// The FIFO memory size can be increased by expanding the rd_addr |
// and wr_addr signal widths, to address further BRAMs. |
// |
// Requirements : |
// * Minimum frame size of 8 bytes |
// * Spacing between good/bad frame signaling (encoded by |
// rx_axis_mac_tvalid, rx_axis_mac_tlast, rx_axis_mac_tuser), is at least 64 |
// clock cycles |
// * Write AxiStream clock is 125MHz downto 1.25MHz |
// * Read AxiStream clock equal to or faster than write clock, |
// and downto 20MHz |
// |
//------------------------------------------------------------------------------ |
|
`timescale 1ps / 1ps |
|
//------------------------------------------------------------------------------ |
// The module declaration for the Receiver FIFO |
//------------------------------------------------------------------------------ |
|
(* DowngradeIPIdentifiedWarnings = "yes" *) |
module tri_mode_ethernet_mac_0_rx_client_fifo |
( |
// User-side (read-side) AxiStream interface |
input rx_fifo_aclk, |
input rx_fifo_resetn, |
output reg [7:0] rx_axis_fifo_tdata = 8'd0, |
output reg rx_axis_fifo_tvalid, |
output rx_axis_fifo_tlast, |
input rx_axis_fifo_tready, |
|
// MAC-side (write-side) AxiStream interface |
input rx_mac_aclk, |
input rx_mac_resetn, |
input [7:0] rx_axis_mac_tdata, |
input rx_axis_mac_tvalid, |
input rx_axis_mac_tlast, |
input rx_axis_mac_tuser, |
|
// FIFO status and overflow indication, |
// synchronous to write-side (rx_mac_aclk) interface |
output [3:0] fifo_status, |
output fifo_overflow |
); |
|
|
//---------------------------------------------------------------------------- |
// Define internal signals |
//---------------------------------------------------------------------------- |
|
// Binary encoded read state machine states |
parameter WAIT_s = 3'b000; |
parameter QUEUE1_s = 3'b001; |
parameter QUEUE2_s = 3'b010; |
parameter QUEUE3_s = 3'b011; |
parameter QUEUE_SOF_s = 3'b100; |
parameter SOF_s = 3'b101; |
parameter DATA_s = 3'b110; |
parameter EOF_s = 3'b111; |
|
|
reg [2:0] rd_state; |
|
reg [2:0] rd_nxt_state; |
|
// Binary encoded write state machine states |
parameter IDLE_s = 3'b000; |
parameter FRAME_s = 3'b001; |
parameter GF_s = 3'b010; |
parameter BF_s = 3'b011; |
parameter OVFLOW_s = 3'b100; |
|
|
reg [2:0] wr_state; |
|
reg [2:0] wr_nxt_state; |
|
wire wr_en; |
reg [11:0] wr_addr; |
wire wr_addr_inc; |
wire wr_start_addr_load; |
wire wr_addr_reload; |
reg [11:0] wr_start_addr; |
wire [8:0] wr_eof_data_bram; |
reg [7:0] wr_data_bram; |
reg [7:0] wr_data_pipe[0:1]; |
reg wr_dv_pipe[0:2]; |
reg wr_gfbf_pipe[0:1]; |
reg wr_gf; |
reg wr_bf; |
reg wr_eof_bram_pipe[0:1]; |
reg wr_eof_bram; |
reg frame_in_fifo; |
|
reg [11:0] rd_addr; |
wire rd_addr_inc; |
reg rd_addr_reload; |
wire [8:0] rd_eof_data_bram; |
wire [7:0] rd_data_bram; |
reg [7:0] rd_data_pipe = 8'd0; |
reg [7:0] rd_data_delay = 8'd0; |
reg [1:0] rd_valid_pipe; |
wire [0:0] rd_eof_bram; |
reg rd_en; |
reg rd_pull_frame; |
reg rd_eof; |
|
(* INIT = "0" *) |
reg wr_store_frame_tog = 1'b0; |
wire rd_store_frame_sync; |
|
(* INIT = "0" *) |
reg rd_store_frame_delay = 1'b0; |
reg rd_store_frame; |
reg [8:0] rd_frames; |
reg wr_fifo_full; |
|
reg [1:0] old_rd_addr; |
reg update_addr_tog; |
wire update_addr_tog_sync; |
reg update_addr_tog_sync_reg; |
|
reg [11:6] wr_rd_addr; |
wire [12:0] wr_addr_diff_in; |
reg [11:0] wr_addr_diff; |
|
reg [3:0] wr_fifo_status; |
reg rx_axis_fifo_tlast_int; |
|
wire rx_fifo_reset; |
wire rx_mac_reset; |
|
// invert reset sense as architecture is optimised for active high resets |
assign rx_fifo_reset = !rx_fifo_resetn; |
assign rx_mac_reset = !rx_mac_resetn; |
|
|
//---------------------------------------------------------------------------- |
// Begin FIFO architecture |
//---------------------------------------------------------------------------- |
|
|
//---------------------------------------------------------------------------- |
// Read state machines and control |
//---------------------------------------------------------------------------- |
|
// Read state machine. |
// States are WAIT, QUEUE1, QUEUE2, QUEUE3, QUEUE_SOF, SOF, DATA, EOF. |
// Clock state to next state. |
always @(posedge rx_fifo_aclk) |
begin |
if (rx_fifo_reset == 1'b1) begin |
rd_state <= WAIT_s; |
end |
else begin |
rd_state <= rd_nxt_state; |
end |
end |
|
assign rx_axis_fifo_tlast = rx_axis_fifo_tlast_int; |
|
// Decode next state, combinatorial. |
always @(rd_state, frame_in_fifo, rd_eof, rx_axis_fifo_tready, rx_axis_fifo_tlast_int, |
rd_valid_pipe) |
begin |
case (rd_state) |
WAIT_s : begin |
// Wait until there is a full frame in the FIFO, then |
// start to load the pipeline. |
if (frame_in_fifo == 1'b1 && rx_axis_fifo_tlast_int == 1'b0) begin |
rd_nxt_state <= QUEUE1_s; |
end |
else begin |
rd_nxt_state <= WAIT_s; |
end |
end |
|
// Load the output pipeline, which takes three clock cycles. |
QUEUE1_s : begin |
rd_nxt_state <= QUEUE2_s; |
end |
|
QUEUE2_s : begin |
rd_nxt_state <= QUEUE3_s; |
end |
|
QUEUE3_s : begin |
rd_nxt_state <= QUEUE_SOF_s; |
end |
|
QUEUE_SOF_s : begin |
// The pipeline is full and the frame output starts now. |
rd_nxt_state <= DATA_s; |
end |
|
SOF_s : begin |
// A new frame begins immediately following end of last frame. |
if (rx_axis_fifo_tready == 1'b1) begin |
rd_nxt_state <= DATA_s; |
end |
else begin |
rd_nxt_state <= SOF_s; |
end |
end |
|
DATA_s : begin |
// Read data from the FIFO. When the EOF marker is detected from |
// the BRAM output, move to EOF state. |
if (rx_axis_fifo_tready == 1'b1 && rd_eof == 1'b1) begin |
rd_nxt_state <= EOF_s; |
end |
else begin |
rd_nxt_state <= DATA_s; |
end |
end |
|
EOF_s : begin |
// Hold in this state until tready is asserted and the EOF |
// marker (tlast) is accepted on interface. |
// If there is another frame in the FIFO, then it will already be |
// queued into the pipeline so move straight to SOF state. |
if (rx_axis_fifo_tready == 1'b1) begin |
if (rd_valid_pipe[1] == 1'b1) begin |
rd_nxt_state <= SOF_s; |
end |
else begin |
rd_nxt_state <= WAIT_s; |
end |
end |
else begin |
rd_nxt_state <= EOF_s; |
end |
end |
|
default : begin |
rd_nxt_state <= WAIT_s; |
end |
|
endcase |
end |
|
// Detect if frame_in_fifo was high 3 reads ago. |
// This is used to ensure we only treat data in the pipeline as valid if |
// frame_in_fifo goes high at or before the EOF marker of the current frame. |
// It may be that there is valid data (i.e a partial frame has been written) |
// but until the end of that frame we do not know if it is a good frame. |
always @(posedge rx_fifo_aclk) |
begin |
if (rx_axis_fifo_tready == 1'b1) begin |
rd_valid_pipe <= {rd_valid_pipe[0], frame_in_fifo}; |
end |
end |
|
// Decode tlast signal from EOF marker. |
always @(posedge rx_fifo_aclk) |
begin |
if (rx_fifo_reset == 1'b1) begin |
rx_axis_fifo_tlast_int <= 1'b0; |
end |
else if (rx_axis_fifo_tready == 1'b1) begin |
// Assert tlast signal when the EOF marker has been detected, and |
// continue to drive it until it has been accepted on the interface. |
case (rd_state) |
EOF_s : |
rx_axis_fifo_tlast_int <= 1'b1; |
default : |
rx_axis_fifo_tlast_int <= 1'b0; |
endcase |
end |
end |
|
// Decode the tvalid output based on state. |
always @(posedge rx_fifo_aclk) |
begin |
if (rx_fifo_reset == 1'b1) begin |
rx_axis_fifo_tvalid <= 1'b0; |
end |
else begin |
case (rd_state) |
QUEUE_SOF_s : |
rx_axis_fifo_tvalid <= 1'b1; |
SOF_s : |
rx_axis_fifo_tvalid <= 1'b1; |
DATA_s : |
rx_axis_fifo_tvalid <= 1'b1; |
EOF_s : |
rx_axis_fifo_tvalid <= 1'b1; |
default : |
if (rx_axis_fifo_tready == 1'b1) begin |
rx_axis_fifo_tvalid <= 1'b0; |
end |
endcase |
end |
end |
|
// Decode internal control signals. |
// rd_en is used to enable the BRAM read and load the output pipeline. |
always @(rd_state, rx_axis_fifo_tready) |
begin |
case (rd_state) |
WAIT_s : |
rd_en <= 1'b0; |
QUEUE1_s : |
rd_en <= 1'b1; |
QUEUE2_s : |
rd_en <= 1'b1; |
QUEUE3_s : |
rd_en <= 1'b1; |
QUEUE_SOF_s : |
rd_en <= 1'b1; |
default : |
rd_en <= rx_axis_fifo_tready; |
endcase |
end |
|
// When the BRAM is being read, enable the read address to be incremented. |
assign rd_addr_inc = rd_en; |
|
// When the current frame is done, and if there is no frame in the FIFO, then |
// the FIFO must wait until a new frame is written in. This requires the read |
// address to be moved back to where the new frame will be written. The |
// pipeline is then reloaded using the QUEUE states. |
always @(posedge rx_fifo_aclk) |
begin |
if (rx_fifo_reset == 1'b1) begin |
rd_addr_reload <= 1'b0; |
end |
else begin |
if (rd_state == EOF_s && rd_nxt_state == WAIT_s) |
rd_addr_reload <= 1'b1; |
else |
rd_addr_reload <= 1'b0; |
end |
end |
|
// Data is available if there is at leat one frame stored in the FIFO. |
always @(posedge rx_fifo_aclk) |
begin |
if (rx_fifo_reset == 1'b1) begin |
frame_in_fifo <= 1'b0; |
end |
else begin |
if (rd_frames != 9'b0) begin |
frame_in_fifo <= 1'b1; |
end |
else begin |
frame_in_fifo <= 1'b0; |
end |
end |
end |
|
// When a frame has been stored we need to synchronize that event to the |
// read clock domain for frame count store. |
tri_mode_ethernet_mac_0_sync_block resync_wr_store_frame_tog |
( |
.clk (rx_fifo_aclk), |
.data_in (wr_store_frame_tog), |
.data_out (rd_store_frame_sync) |
); |
|
always @(posedge rx_fifo_aclk) |
begin |
rd_store_frame_delay <= rd_store_frame_sync; |
end |
|
// Edge detect of the resynchronized frame count. This creates a pulse |
// when a new frame has been stored. |
always @(posedge rx_fifo_aclk) |
begin |
if (rx_fifo_reset == 1'b1) begin |
rd_store_frame <= 1'b0; |
end |
else begin |
// Edge detector |
if ((rd_store_frame_delay ^ rd_store_frame_sync) == 1'b1) begin |
rd_store_frame <= 1'b1; |
end |
else begin |
rd_store_frame <= 1'b0; |
end |
end |
end |
|
// This creates a pulse when a new frame has begun to be output. |
always @(posedge rx_fifo_aclk) |
begin |
if (rx_fifo_reset == 1'b1) begin |
rd_pull_frame <= 1'b0; |
end |
else begin |
if (rd_state == SOF_s && rd_nxt_state != SOF_s) begin |
rd_pull_frame <= 1'b1; |
end |
else if (rd_state == QUEUE_SOF_s && rd_nxt_state != QUEUE_SOF_s) begin |
rd_pull_frame <= 1'b1; |
end |
else begin |
rd_pull_frame <= 1'b0; |
end |
end |
end |
|
// Up/down counter to monitor the number of frames stored within |
// the FIFO. Note: |
// * increments at the end of a frame write cycle |
// * decrements at the beginning of a frame read cycle |
always @(posedge rx_fifo_aclk) |
begin |
if (rx_fifo_reset == 1'b1) begin |
rd_frames <= 9'b0; |
end |
else begin |
// A frame is written to the FIFO in this cycle, and no frame is being |
// read out on the same cycle. |
if (rd_store_frame == 1'b1 && rd_pull_frame == 1'b0) begin |
rd_frames <= rd_frames + 9'b1; |
end |
// A frame is being read out on this cycle and no frame is being |
// written on the same cycle. |
else if (rd_store_frame == 1'b0 && rd_pull_frame == 1'b1) begin |
rd_frames <= rd_frames - 9'b1; |
end |
end |
end |
|
|
//---------------------------------------------------------------------------- |
// Write state machines and control |
//---------------------------------------------------------------------------- |
|
// Write state machine. |
// States are IDLE, FRAME, GF, BF, OVFLOW. |
// Clock state to next state. |
always @(posedge rx_mac_aclk) |
begin |
if (rx_mac_reset == 1'b1) begin |
wr_state <= IDLE_s; |
end |
else begin |
wr_state <= wr_nxt_state; |
end |
end |
|
// Decode next state, combinatorial. |
always @(wr_state, wr_dv_pipe[1], wr_gf, wr_bf, wr_fifo_full) |
begin |
case (wr_state) |
IDLE_s : begin |
// There is data in the incoming pipeline when dv_pipe[1] goes high. |
if (wr_dv_pipe[1] == 1'b1) begin |
wr_nxt_state <= FRAME_s; |
end |
else begin |
wr_nxt_state <= IDLE_s; |
end |
end |
|
FRAME_s : begin |
// If FIFO is full then go to overflow state. |
// If the good or bad flag is detected, then the end of the frame |
// has been reached and the gf or bf state is visited before idle. |
// Otherwise remain in frame state while data is written to FIFO. |
if (wr_fifo_full == 1'b1) begin |
wr_nxt_state <= OVFLOW_s; |
end |
else if (wr_gf == 1'b1) begin |
wr_nxt_state <= GF_s; |
end |
else if (wr_bf == 1'b1) begin |
wr_nxt_state <= BF_s; |
end |
else begin |
wr_nxt_state <= FRAME_s; |
end |
end |
|
GF_s : begin |
// Return to idle and wait for next frame. |
wr_nxt_state <= IDLE_s; |
end |
|
BF_s : begin |
// Return to idle and wait for next frame. |
wr_nxt_state <= IDLE_s; |
end |
|
OVFLOW_s : begin |
// Wait until the good or bad flag received. |
if (wr_gf == 1'b1 || wr_bf == 1'b1) begin |
wr_nxt_state <= IDLE_s; |
end |
else begin |
wr_nxt_state <= OVFLOW_s; |
end |
end |
|
default : begin |
wr_nxt_state <= IDLE_s; |
end |
|
endcase |
end |
|
// Decode control signals, combinatorial. |
// wr_en is used to enable the BRAM write and loading of the input pipeline. |
assign wr_en = (wr_state == FRAME_s) ? wr_dv_pipe[2] : 1'b0; |
|
// Increment the write address when we are receiving valid frame data. |
assign wr_addr_inc = (wr_state == FRAME_s) ? wr_dv_pipe[2] : 1'b0; |
|
// If the FIFO overflows or a frame is to be dropped, we need to move the |
// write address back to the start of the frame. This allows the data to be |
// overwritten. |
assign wr_addr_reload = (wr_state == BF_s || wr_state == OVFLOW_s) |
? 1'b1 : 1'b0; |
|
// The start address is saved when in the idle state. |
assign wr_start_addr_load = (wr_state == IDLE_s) ? 1'b1 : 1'b0; |
|
// We need to know when a frame is stored, in order to increment the count of |
// frames stored in the FIFO. |
always @(posedge rx_mac_aclk) |
begin |
if (wr_state == GF_s) begin |
wr_store_frame_tog <= !wr_store_frame_tog; |
end |
end |
|
|
//---------------------------------------------------------------------------- |
// Address counters |
//---------------------------------------------------------------------------- |
|
// Write address is incremented when data is being written into the FIFO. |
always @(posedge rx_mac_aclk) |
begin |
if (rx_mac_reset == 1'b1) begin |
wr_addr <= 12'b0; |
end |
else begin |
if (wr_addr_reload == 1'b1) begin |
wr_addr <= wr_start_addr; |
end |
else if (wr_addr_inc == 1'b1) begin |
wr_addr <= wr_addr + 12'b1; |
end |
end |
end |
|
// Store the start address. |
always @(posedge rx_mac_aclk) |
begin |
if (rx_mac_reset == 1'b1) begin |
wr_start_addr <= 12'b0; |
end |
else begin |
if (wr_start_addr_load == 1'b1) begin |
wr_start_addr <= wr_addr; |
end |
end |
end |
|
// Read address is incremented when data is being read from the FIFO. |
always @(posedge rx_fifo_aclk) |
begin |
if (rx_fifo_reset == 1'b1) begin |
rd_addr <= 12'd0; |
end |
else begin |
if (rd_addr_reload == 1'b1) begin |
rd_addr <= rd_addr - 12'd3; |
end |
else if (rd_addr_inc == 1'b1) begin |
rd_addr <= rd_addr + 12'd1; |
end |
end |
end |
|
|
//---------------------------------------------------------------------------- |
// Data pipelines |
//---------------------------------------------------------------------------- |
|
// Register data inputs to BRAM. |
// No resets to allow for SRL16 target. |
always @(posedge rx_mac_aclk) |
begin |
wr_data_pipe[0] <= rx_axis_mac_tdata; |
wr_data_pipe[1] <= wr_data_pipe[0]; |
wr_data_bram <= wr_data_pipe[1]; |
end |
|
// The valid input enables BRAM write and is a condition for other signals. |
always @(posedge rx_mac_aclk) |
begin |
wr_dv_pipe[0] <= rx_axis_mac_tvalid; |
wr_dv_pipe[1] <= wr_dv_pipe[0]; |
wr_dv_pipe[2] <= wr_dv_pipe[1]; |
end |
|
// End of frame flag set when tlast and tvalid are asserted together. |
always @(posedge rx_mac_aclk) |
begin |
wr_eof_bram_pipe[0] <= rx_axis_mac_tlast; |
wr_eof_bram_pipe[1] <= wr_eof_bram_pipe[0]; |
wr_eof_bram <= wr_eof_bram_pipe[1] & wr_dv_pipe[1]; |
end |
|
// Upon arrival of EOF flag, the frame is good good if tuser signal |
// is low, and bad if tuser signal is high. |
always @(posedge rx_mac_aclk) |
begin |
wr_gfbf_pipe[0] <= rx_axis_mac_tuser; |
wr_gfbf_pipe[1] <= wr_gfbf_pipe[0]; |
wr_gf <= !wr_gfbf_pipe[1] & wr_eof_bram_pipe[1] & wr_dv_pipe[1]; |
wr_bf <= wr_gfbf_pipe[1] & wr_eof_bram_pipe[1] & wr_dv_pipe[1]; |
end |
|
// Register data outputs from BRAM. |
// No resets to allow for SRL16 target. |
always @(posedge rx_fifo_aclk) |
begin |
if (rd_en == 1'b1) begin |
rd_data_delay <= rd_data_bram; |
rd_data_pipe <= rd_data_delay; |
rx_axis_fifo_tdata <= rd_data_pipe; |
end |
end |
|
always @(posedge rx_fifo_aclk) |
begin |
if (rd_en == 1'b1) begin |
rd_eof <= rd_eof_bram[0]; |
end |
end |
|
//---------------------------------------------------------------------------- |
// Overflow functionality |
//---------------------------------------------------------------------------- |
|
// to minimise the number of read address updates the bottom 6 bits of the |
// read address are not passed across and the write domain will only sample |
// them when bits 5 and 4 of the read address transition from 01 to 10. |
// Since this is for full detection this just means that if the read stops |
// the write will hit full up to 64 locations early |
|
// need to use two bits and look for an increment transition as reload can cause |
// a decrement on this boundary (decrement is only by 3 so above bit 2 should be safe) |
always @(posedge rx_fifo_aclk) |
begin |
if (rx_fifo_reset == 1'b1) begin |
old_rd_addr <= 2'b00; |
update_addr_tog <= 1'b0; |
end |
else begin |
old_rd_addr <= rd_addr[5:4]; |
if (rd_addr[5:4] == 2'b10 & old_rd_addr == 2'b01) begin |
update_addr_tog <= !update_addr_tog; |
end |
end |
end |
|
|
tri_mode_ethernet_mac_0_sync_block sync_rd_addr_tog |
( |
.clk (rx_mac_aclk), |
.data_in (update_addr_tog), |
.data_out (update_addr_tog_sync) |
); |
|
// Convert the synchronized read address pointer gray code back to binary. |
always @(posedge rx_mac_aclk) |
begin |
if (rx_mac_reset == 1'b1) begin |
update_addr_tog_sync_reg <= 1'b0; |
wr_rd_addr <= 6'd0; |
end |
else begin |
update_addr_tog_sync_reg <= update_addr_tog_sync; |
if (update_addr_tog_sync_reg ^ update_addr_tog_sync) begin |
wr_rd_addr <= rd_addr[11:6]; |
end |
end |
end |
|
assign wr_addr_diff_in = {1'b0, wr_rd_addr, 6'd0} - {1'b0,wr_addr}; |
|
// Obtain the difference between write and read pointers. |
always @(posedge rx_mac_aclk) |
begin |
if (rx_mac_reset == 1'b1) begin |
wr_addr_diff <= 12'b0; |
end |
else begin |
wr_addr_diff <= wr_addr_diff_in[11:0]; |
end |
end |
|
// Detect when the FIFO is full. |
// The FIFO is considered to be full if the write address pointer is |
// within 0 to 3 of the read address pointer. |
always @(posedge rx_mac_aclk) |
begin |
if (rx_mac_reset == 1'b1) begin |
wr_fifo_full <= 1'b0; |
end |
else begin |
if (wr_addr_diff[11:4] == 8'b0 && wr_addr_diff[3:2] != 2'b0) begin |
wr_fifo_full <= 1'b1; |
end |
else begin |
wr_fifo_full <= 1'b0; |
end |
end |
end |
|
// Decode the overflow indicator output. |
assign fifo_overflow = (wr_state == OVFLOW_s) ? 1'b1 : 1'b0; |
|
|
//---------------------------------------------------------------------------- |
// FIFO status signals |
//---------------------------------------------------------------------------- |
|
// The FIFO status is four bits which represents the occupancy of the FIFO |
// in sixteenths. To generate this signal we therefore only need to compare |
// the 4 most significant bits of the write address pointer with the 4 most |
// significant bits of the read address pointer. |
|
always @(posedge rx_mac_aclk) |
begin |
if (rx_mac_reset == 1'b1) begin |
wr_fifo_status <= 4'b0; |
end |
else begin |
if (wr_addr_diff == 12'b0) begin |
wr_fifo_status <= 4'b0; |
end |
else begin |
wr_fifo_status[3] <= !wr_addr_diff[11]; |
wr_fifo_status[2] <= !wr_addr_diff[10]; |
wr_fifo_status[1] <= !wr_addr_diff[9]; |
wr_fifo_status[0] <= !wr_addr_diff[8]; |
end |
end |
end |
|
assign fifo_status = wr_fifo_status; |
|
|
//---------------------------------------------------------------------------- |
// Instantiate FIFO block memory |
//---------------------------------------------------------------------------- |
|
assign wr_eof_data_bram[8] = wr_eof_bram; |
assign wr_eof_data_bram[7:0] = wr_data_bram; |
|
assign rd_eof_bram[0] = rd_eof_data_bram[8]; |
assign rd_data_bram = rd_eof_data_bram[7:0]; |
|
tri_mode_ethernet_mac_0_bram_tdp # |
( |
.DATA_WIDTH (9), |
.ADDR_WIDTH (12) |
) |
rx_ramgen_i ( |
.b_dout (rd_eof_data_bram), |
.a_addr (wr_addr[11:0]), |
.b_addr (rd_addr[11:0]), |
.a_clk (rx_mac_aclk), |
.b_clk (rx_fifo_aclk), |
.a_din (wr_eof_data_bram), |
.b_en (rd_en), |
.a_rst (rx_mac_reset), |
.b_rst (rx_fifo_reset), |
.a_wr (wr_en) |
); |
|
endmodule |
/trunk/hw/src/rtl/tri_mode_emac/src/fifo/tri_mode_ethernet_mac_0_ten_100_1g_eth_fifo.v
0,0 → 1,180
//------------------------------------------------------------------------------ |
// Title : 10/100/1G Ethernet FIFO |
// Version : 1.2 |
// Project : Tri-Mode Ethernet MAC |
//------------------------------------------------------------------------------ |
// File : tri_mode_ethernet_mac_0_ten_100_1g_eth_fifo.v |
// Author : Xilinx Inc. |
// ----------------------------------------------------------------------------- |
// (c) Copyright 2004-2008 Xilinx, Inc. All rights reserved. |
// |
// This file contains confidential and proprietary information |
// of Xilinx, Inc. and is protected under U.S. and |
// international copyright and other intellectual property |
// laws. |
// |
// DISCLAIMER |
// This disclaimer is not a license and does not grant any |
// rights to the materials distributed herewith. Except as |
// otherwise provided in a valid license issued to you by |
// Xilinx, and to the maximum extent permitted by applicable |
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND |
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES |
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING |
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- |
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and |
// (2) Xilinx shall not be liable (whether in contract or tort, |
// including negligence, or under any other theory of |
// liability) for any loss or damage of any kind or nature |
// related to, arising under or in connection with these |
// materials, including for any direct, or any indirect, |
// special, incidental, or consequential loss or damage |
// (including loss of data, profits, goodwill, or any type of |
// loss or damage suffered as a result of any action brought |
// by a third party) even if such damage or loss was |
// reasonably foreseeable or Xilinx had been advised of the |
// possibility of the same. |
// |
// CRITICAL APPLICATIONS |
// Xilinx products are not designed or intended to be fail- |
// safe, or for use in any application requiring fail-safe |
// performance, such as life-support or safety devices or |
// systems, Class III medical devices, nuclear facilities, |
// applications related to the deployment of airbags, or any |
// other applications that could lead to death, personal |
// injury, or severe property or environmental damage |
// (individually and collectively, "Critical |
// Applications"). Customer assumes the sole risk and |
// liability of any use of Xilinx products in Critical |
// Applications, subject only to applicable laws and |
// regulations governing limitations on product liability. |
// |
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS |
// PART OF THIS FILE AT ALL TIMES. |
// ----------------------------------------------------------------------------- |
// Description: This is the top level wrapper for the 10/100/1G Ethernet FIFO. |
// The top level wrapper consists of individual FIFOs on the |
// transmitter path and on the receiver path. |
// |
// Each path consists of an 8 bit local link to 8 bit client |
// interface FIFO. |
//------------------------------------------------------------------------------ |
|
|
`timescale 1ps / 1ps |
|
|
//------------------------------------------------------------------------------ |
// The module declaration for the FIFO |
//------------------------------------------------------------------------------ |
|
module tri_mode_ethernet_mac_0_ten_100_1g_eth_fifo # |
( |
parameter FULL_DUPLEX_ONLY = 1 |
) |
|
( |
|
input tx_fifo_aclk, // tx fifo clock |
input tx_fifo_resetn, // tx fifo clock synchronous reset |
// tx fifo AXI-Stream interface |
input [7:0] tx_axis_fifo_tdata, |
input tx_axis_fifo_tvalid, |
input tx_axis_fifo_tlast, |
output tx_axis_fifo_tready, |
|
input tx_mac_aclk, // tx_mac clock |
input tx_mac_resetn, // tx mac clock synchronous reset |
// tx mac AXI-Stream interface |
output [7:0] tx_axis_mac_tdata, |
output tx_axis_mac_tvalid, |
output tx_axis_mac_tlast, |
input tx_axis_mac_tready, |
output tx_axis_mac_tuser, |
// tx FIFO status outputs |
output tx_fifo_overflow, |
output [3:0] tx_fifo_status, |
// tx fifo duplex controls |
input tx_collision, |
input tx_retransmit, |
|
input rx_fifo_aclk, // rx fifo clock |
input rx_fifo_resetn, // rx fifo clock synchronous reset |
// rx fifo AXI-Stream interface |
output [7:0] rx_axis_fifo_tdata, |
output rx_axis_fifo_tvalid, |
output rx_axis_fifo_tlast, |
input rx_axis_fifo_tready, |
|
input rx_mac_aclk, // rx mac clock |
input rx_mac_resetn, // rx mac clock synchronous reset |
// rx mac AXI-Stream interface |
input [7:0] rx_axis_mac_tdata, |
input rx_axis_mac_tvalid, |
input rx_axis_mac_tlast, |
input rx_axis_mac_tuser, |
// rx fifo status outputs |
output [3:0] rx_fifo_status, |
output rx_fifo_overflow |
); |
|
|
|
//---------------------------------------------------------------------------- |
// Instantiate the Transmitter FIFO |
//---------------------------------------------------------------------------- |
tri_mode_ethernet_mac_0_tx_client_fifo # |
( |
.FULL_DUPLEX_ONLY (FULL_DUPLEX_ONLY) |
) |
tx_fifo_i |
( |
|
.tx_fifo_aclk (tx_fifo_aclk), |
.tx_fifo_resetn (tx_fifo_resetn), |
.tx_axis_fifo_tdata (tx_axis_fifo_tdata), |
.tx_axis_fifo_tvalid (tx_axis_fifo_tvalid), |
.tx_axis_fifo_tlast (tx_axis_fifo_tlast), |
.tx_axis_fifo_tready (tx_axis_fifo_tready), |
|
.tx_mac_aclk (tx_mac_aclk), |
.tx_mac_resetn (tx_mac_resetn), |
.tx_axis_mac_tdata (tx_axis_mac_tdata), |
.tx_axis_mac_tvalid (tx_axis_mac_tvalid), |
.tx_axis_mac_tlast (tx_axis_mac_tlast), |
.tx_axis_mac_tready (tx_axis_mac_tready), |
.tx_axis_mac_tuser (tx_axis_mac_tuser), |
|
.fifo_overflow (tx_fifo_overflow), |
.fifo_status (tx_fifo_status), |
|
.tx_collision (tx_collision), |
.tx_retransmit (tx_retransmit) |
); |
|
|
//---------------------------------------------------------------------------- |
// Instantiate the Receiver FIFO |
//---------------------------------------------------------------------------- |
tri_mode_ethernet_mac_0_rx_client_fifo rx_fifo_i |
( |
.rx_fifo_aclk (rx_fifo_aclk), |
.rx_fifo_resetn (rx_fifo_resetn), |
.rx_axis_fifo_tdata (rx_axis_fifo_tdata), |
.rx_axis_fifo_tvalid (rx_axis_fifo_tvalid), |
.rx_axis_fifo_tlast (rx_axis_fifo_tlast), |
.rx_axis_fifo_tready (rx_axis_fifo_tready), |
|
.rx_mac_aclk (rx_mac_aclk), |
.rx_mac_resetn (rx_mac_resetn), |
.rx_axis_mac_tdata (rx_axis_mac_tdata), |
.rx_axis_mac_tvalid (rx_axis_mac_tvalid), |
.rx_axis_mac_tlast (rx_axis_mac_tlast), |
.rx_axis_mac_tuser (rx_axis_mac_tuser), |
|
.fifo_status (rx_fifo_status), |
.fifo_overflow (rx_fifo_overflow) |
); |
|
|
endmodule |
/trunk/hw/src/rtl/tri_mode_emac/src/fifo/tri_mode_ethernet_mac_0_tx_client_fifo.v
0,0 → 1,1728
//------------------------------------------------------------------------------ |
// Title : Transmitter FIFO with AxiStream interfaces |
// Version : 1.3 |
// Project : Tri-Mode Ethernet MAC |
//------------------------------------------------------------------------------ |
// File : tri_mode_ethernet_mac_0_tx_client_fifo.v |
// Author : Xilinx Inc. |
// ----------------------------------------------------------------------------- |
// (c) Copyright 2004-2013 Xilinx, Inc. All rights reserved. |
// |
// This file contains confidential and proprietary information |
// of Xilinx, Inc. and is protected under U.S. and |
// international copyright and other intellectual property |
// laws. |
// |
// DISCLAIMER |
// This disclaimer is not a license and does not grant any |
// rights to the materials distributed herewith. Except as |
// otherwise provided in a valid license issued to you by |
// Xilinx, and to the maximum extent permitted by applicable |
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND |
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES |
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING |
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- |
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and |
// (2) Xilinx shall not be liable (whether in contract or tort, |
// including negligence, or under any other theory of |
// liability) for any loss or damage of any kind or nature |
// related to, arising under or in connection with these |
// materials, including for any direct, or any indirect, |
// special, incidental, or consequential loss or damage |
// (including loss of data, profits, goodwill, or any type of |
// loss or damage suffered as a result of any action brought |
// by a third party) even if such damage or loss was |
// reasonably foreseeable or Xilinx had been advised of the |
// possibility of the same. |
// |
// CRITICAL APPLICATIONS |
// Xilinx products are not designed or intended to be fail- |
// safe, or for use in any application requiring fail-safe |
// performance, such as life-support or safety devices or |
// systems, Class III medical devices, nuclear facilities, |
// applications related to the deployment of airbags, or any |
// other applications that could lead to death, personal |
// injury, or severe property or environmental damage |
// (individually and collectively, "Critical |
// Applications"). Customer assumes the sole risk and |
// liability of any use of Xilinx products in Critical |
// Applications, subject only to applicable laws and |
// regulations governing limitations on product liability. |
// |
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS |
// PART OF THIS FILE AT ALL TIMES. |
// ----------------------------------------------------------------------------- |
// Description: This is a transmitter side FIFO for the design example |
// of the Tri-Mode Ethernet MAC core. AxiStream interfaces are used. |
// |
// The FIFO is built around an Inferred Dual Port RAM, |
// giving a total memory capacity of 4096 bytes. |
// |
// Valid frame data received from the user interface is written |
// into the Block RAM on the tx_fifo_aclkk. The FIFO will store |
// frames up to 4kbytes in length. If larger frames are written |
// to the FIFO, the AxiStream interface will accept the rest of the |
// frame, but that frame will be dropped by the FIFO and the |
// overflow signal will be asserted. |
// |
// The FIFO is designed to work with a minimum frame length of 14 |
// bytes. |
// |
// When there is at least one complete frame in the FIFO, the MAC |
// transmitter AxiStream interface will be driven to request frame |
// transmission by placing the first byte of the frame onto |
// tx_axis_mac_tdata and by asserting tx_axis_mac_tvalid. The MAC will later |
// respond by asserting tx_axis_mac_tready. At this point the remaining |
// frame data is read out of the FIFO subject to tx_axis_mac_tready. |
// Data is read out of the FIFO on the tx_mac_aclk. |
// |
// If the generic FULL_DUPLEX_ONLY is set to false, the FIFO will |
// requeue and retransmit frames as requested by the MAC. Once a |
// frame has been transmitted by the FIFO it is stored until the |
// possible retransmit window for that frame has expired. |
// |
// The FIFO has been designed to operate with different clocks |
// on the write and read sides. The minimum write clock |
// frequency is the read clock frequency divided by 2. |
// |
// The FIFO memory size can be increased by expanding the rd_addr |
// and wr_addr signal widths, to address further BRAMs. |
// |
//------------------------------------------------------------------------------ |
|
`timescale 1ps / 1ps |
|
//------------------------------------------------------------------------------ |
// The module declaration for the Transmitter FIFO |
//------------------------------------------------------------------------------ |
|
(* DowngradeIPIdentifiedWarnings = "yes" *) |
module tri_mode_ethernet_mac_0_tx_client_fifo # |
( |
parameter FULL_DUPLEX_ONLY = 0 |
) |
|
( |
// User-side (write-side) AxiStream interface |
input tx_fifo_aclk, |
input tx_fifo_resetn, |
input [7:0] tx_axis_fifo_tdata, |
input tx_axis_fifo_tvalid, |
input tx_axis_fifo_tlast, |
output tx_axis_fifo_tready, |
|
// MAC-side (read-side) AxiStream interface |
input tx_mac_aclk, |
input tx_mac_resetn, |
output [7:0] tx_axis_mac_tdata, |
output reg tx_axis_mac_tvalid, |
output reg tx_axis_mac_tlast, |
input tx_axis_mac_tready, |
output reg tx_axis_mac_tuser, |
|
// FIFO status and overflow indication, |
// synchronous to write-side (tx_user_aclk) interface |
output fifo_overflow, |
output [3:0] fifo_status, |
|
// FIFO collision and retransmission requests from MAC |
input tx_collision, |
input tx_retransmit |
); |
|
|
//---------------------------------------------------------------------------- |
// Define internal signals |
//---------------------------------------------------------------------------- |
|
// Binary encoded read state machine states. |
localparam IDLE_s = 4'b0000; |
localparam QUEUE1_s = 4'b0001; |
localparam QUEUE2_s = 4'b0010; |
localparam QUEUE3_s = 4'b0011; |
localparam START_DATA1_s = 4'b0100; |
localparam DATA_PRELOAD1_s = 4'b0101; |
localparam DATA_PRELOAD2_s = 4'b0110; |
localparam WAIT_HANDSHAKE_s = 4'b0111; |
localparam FRAME_s = 4'b1000; |
localparam HANDSHAKE_s = 4'b1001; |
localparam FINISH_s = 4'b1010; |
localparam DROP_ERR_s = 4'b1011; |
localparam DROP_s = 4'b1100; |
localparam RETRANSMIT_ERR_s = 4'b1101; |
localparam RETRANSMIT_s = 4'b1111; |
|
|
reg [3:0] rd_state; |
|
reg [3:0] rd_nxt_state; |
|
// Binary encoded write state machine states. |
localparam WAIT_s = 2'b00; |
localparam DATA_s = 2'b01; |
localparam EOF_s = 2'b10; |
localparam OVFLOW_s = 2'b11; |
|
|
reg [1:0] wr_state; |
|
reg [1:0] wr_nxt_state; |
|
wire [8:0] wr_eof_data_bram; |
reg [7:0] wr_data_bram; |
reg [7:0] wr_data_pipe[0:1]; |
reg wr_sof_pipe[0:1]; |
reg wr_eof_pipe[0:1]; |
reg wr_accept_pipe[0:1]; |
reg wr_accept_bram; |
wire wr_sof_int; |
reg [0:0] wr_eof_bram; |
reg wr_eof_reg; |
reg [11:0] wr_addr; |
wire wr_addr_inc; |
wire wr_start_addr_load; |
wire wr_addr_reload; |
reg [11:0] wr_start_addr; |
reg wr_fifo_full; |
wire wr_en; |
reg wr_ovflow_dst_rdy; |
wire tx_axis_fifo_tready_int_n; |
reg [3:0] data_count; |
|
wire frame_in_fifo; |
wire frames_in_fifo; |
reg frame_in_fifo_valid; |
(* INIT = "0" *) |
reg frame_in_fifo_valid_tog = 1'b0; |
wire frame_in_fifo_valid_sync; |
reg frame_in_fifo_valid_delay; |
reg rd_eof; |
reg rd_eof_reg; |
reg rd_eof_pipe; |
reg [11:0] rd_addr; |
wire rd_addr_inc; |
wire rd_addr_reload; |
wire [8:0] rd_eof_data_bram; |
wire [7:0] rd_data_bram; |
reg [7:0] rd_data_pipe = 8'd0; |
reg [7:0] rd_data_delay = 8'd0; |
wire [0:0] rd_eof_bram; |
wire rd_en; |
|
|
(* INIT = "0" *) |
reg rd_tran_frame_tog = 1'b0; |
wire wr_tran_frame_sync; |
|
(* INIT = "0" *) |
reg wr_tran_frame_delay = 1'b0; |
|
(* INIT = "0" *) |
reg rd_retran_frame_tog = 1'b0; |
wire wr_retran_frame_sync; |
|
(* INIT = "0" *) |
reg wr_retran_frame_delay = 1'b0; |
wire wr_store_frame; |
reg wr_transmit_frame; |
reg wr_transmit_frame_delay; |
reg wr_retransmit_frame; |
reg [8:0] wr_frames; |
reg wr_frame_in_fifo; |
reg wr_frames_in_fifo; |
|
reg [3:0] rd_16_count; |
wire rd_txfer_en; |
reg [11:0] rd_addr_txfer; |
|
(* INIT = "0" *) |
reg rd_txfer_tog = 1'b0; |
wire wr_txfer_tog_sync; |
|
(* INIT = "0" *) |
reg wr_txfer_tog_delay = 1'b0; |
wire wr_txfer_en; |
|
(* ASYNC_REG = "TRUE" *) |
reg [11:0] wr_rd_addr; |
|
reg [11:0] wr_addr_diff; |
|
reg [3:0] wr_fifo_status; |
|
reg rd_drop_frame; |
reg rd_retransmit; |
|
reg [11:0] rd_start_addr; |
wire rd_start_addr_load; |
wire rd_start_addr_reload; |
|
reg [11:0] rd_dec_addr; |
|
wire rd_transmit_frame; |
wire rd_retransmit_frame; |
reg rd_col_window_expire; |
reg rd_col_window_pipe[0:1]; |
|
(* ASYNC_REG = "TRUE" *) |
reg wr_col_window_pipe[0:1]; |
|
wire wr_eof_state; |
reg wr_eof_state_reg; |
wire wr_fifo_overflow; |
reg [9:0] rd_slot_timer; |
reg wr_col_window_expire; |
wire rd_idle_state; |
|
wire [7:0] tx_axis_mac_tdata_int_frame; |
wire [7:0] tx_axis_mac_tdata_int_handshake; |
reg [7:0] tx_axis_mac_tdata_int = 8'b0; |
wire tx_axis_mac_tvalid_int_finish; |
wire tx_axis_mac_tvalid_int_droperr; |
wire tx_axis_mac_tvalid_int_retransmiterr; |
wire tx_axis_mac_tlast_int_frame_handshake; |
wire tx_axis_mac_tlast_int_finish; |
wire tx_axis_mac_tlast_int_droperr; |
wire tx_axis_mac_tlast_int_retransmiterr; |
wire tx_axis_mac_tuser_int_droperr; |
wire tx_axis_mac_tuser_int_retransmit; |
|
wire tx_fifo_reset; |
wire tx_mac_reset; |
|
// invert reset sense as architecture is optimised for active high resets |
assign tx_fifo_reset = !tx_fifo_resetn; |
assign tx_mac_reset = !tx_mac_resetn; |
|
//---------------------------------------------------------------------------- |
// Begin FIFO architecture |
//---------------------------------------------------------------------------- |
|
//---------------------------------------------------------------------------- |
// Write state machine and control |
//---------------------------------------------------------------------------- |
|
// Write state machine. |
// States are WAIT, DATA, EOF, OVFLOW. |
// Clock state to next state. |
always @(posedge tx_fifo_aclk) |
begin |
if (tx_fifo_reset == 1'b1) begin |
wr_state <= WAIT_s; |
end |
else begin |
wr_state <= wr_nxt_state; |
end |
end |
|
// Decode next state, combinatorial. |
always @(wr_state, wr_sof_pipe[1], wr_eof_pipe[0], wr_eof_pipe[1], |
wr_eof_bram[0], wr_fifo_overflow, data_count) |
begin |
case (wr_state) |
WAIT_s : begin |
if (wr_sof_pipe[1] == 1'b1 && wr_eof_pipe[1] == 1'b0) begin |
wr_nxt_state <= DATA_s; |
end |
else begin |
wr_nxt_state <= WAIT_s; |
end |
end |
|
DATA_s : begin |
// Wait for the end of frame to be detected. |
if (wr_fifo_overflow == 1'b1 && wr_eof_pipe[0] == 1'b0 |
&& wr_eof_pipe[1] == 1'b0) begin |
wr_nxt_state <= OVFLOW_s; |
end |
else if (wr_eof_pipe[1] == 1'b1) begin |
if (data_count[3:2] != 2'b11) begin |
wr_nxt_state <= OVFLOW_s; |
end |
else begin |
wr_nxt_state <= EOF_s; |
end |
end |
else begin |
wr_nxt_state <= DATA_s; |
end |
end |
|
EOF_s : begin |
// If the start of frame is already in the pipe, a back-to-back frame |
// transmission has occured. Move straight back to frame state. |
if (wr_sof_pipe[1] == 1'b1 && wr_eof_pipe[1] == 1'b0) begin |
wr_nxt_state <= DATA_s; |
end |
else if (wr_eof_bram[0] == 1'b1) begin |
wr_nxt_state <= WAIT_s; |
end |
else begin |
wr_nxt_state <= EOF_s; |
end |
end |
|
OVFLOW_s : begin |
// Wait until the end of frame is reached before clearing the overflow. |
if (wr_eof_bram[0] == 1'b1) begin |
wr_nxt_state <= WAIT_s; |
end |
else begin |
wr_nxt_state <= OVFLOW_s; |
end |
end |
|
default : begin |
wr_nxt_state <= WAIT_s; |
end |
|
endcase |
end |
|
// small frame count - frames smaller than 10 bytes are problematic as the frame_in_fifo cannot |
// react quickly enough - empty detect could be used in the read domain but this doesn't fully cover all cases |
// the cleanest fix is to simply ignore frames smaller than 10 bytes |
// generate a counter which is cleaered on an sof and counts in data |
always @(posedge tx_fifo_aclk) |
begin |
if (tx_fifo_reset == 1'b1) begin |
data_count <= 0; |
end |
else begin |
if (wr_sof_pipe[1] == 1'b1) begin |
data_count <= 0; |
end |
else begin |
if (data_count[3:2] != 2'b11) begin |
data_count <= data_count + 1; |
end |
end |
end |
end |
|
// Decode output signals. |
// wr_en is used to enable the BRAM write and the address to increment. |
assign wr_en = (wr_state == OVFLOW_s) ? 1'b0 : wr_accept_bram; |
|
assign wr_addr_inc = wr_en; |
|
assign wr_addr_reload = (wr_state == OVFLOW_s) ? 1'b1 : 1'b0; |
assign wr_start_addr_load = (wr_state == EOF_s && wr_nxt_state == WAIT_s) |
? 1'b1 : |
(wr_state == EOF_s && wr_nxt_state == DATA_s) |
? 1'b1 : 1'b0; |
|
// Pause the AxiStream handshake when the FIFO is full. |
assign tx_axis_fifo_tready_int_n = (wr_state == OVFLOW_s) ? |
wr_ovflow_dst_rdy : wr_fifo_full; |
|
assign tx_axis_fifo_tready = !tx_axis_fifo_tready_int_n; |
|
// Generate user overflow indicator. |
assign fifo_overflow = (wr_state == OVFLOW_s) ? 1'b1 : 1'b0; |
|
// When in overflow and have captured ovflow EOF, set tx_axis_fifo_tready again. |
always @(posedge tx_fifo_aclk) |
begin |
if (tx_fifo_reset == 1'b1) begin |
wr_ovflow_dst_rdy <= 1'b0; |
end |
else begin |
if (wr_fifo_overflow == 1'b1 && wr_state == DATA_s) begin |
wr_ovflow_dst_rdy <= 1'b0; |
end |
else if (tx_axis_fifo_tvalid == 1'b1 && tx_axis_fifo_tlast == 1'b1) begin |
wr_ovflow_dst_rdy <= 1'b1; |
end |
end |
end |
|
// EOF signals for use in overflow logic. |
assign wr_eof_state = (wr_state == EOF_s) ? 1'b1 : 1'b0; |
|
always @(posedge tx_fifo_aclk) |
begin |
if (tx_fifo_reset == 1'b1) begin |
wr_eof_state_reg <= 1'b0; |
end |
else begin |
wr_eof_state_reg <= wr_eof_state; |
end |
end |
|
|
//---------------------------------------------------------------------------- |
// Read state machine and control |
//---------------------------------------------------------------------------- |
|
// Read state machine. |
// States are IDLE, QUEUE1, QUEUE2, QUEUE3, QUEUE_ACK, WAIT_ACK, FRAME, |
// HANDSHAKE, FINISH, DROP_ERR, DROP, RETRANSMIT_ERR, RETRANSMIT. |
// Clock state to next state. |
always @(posedge tx_mac_aclk) |
begin |
if (tx_mac_reset == 1'b1) begin |
rd_state <= IDLE_s; |
end |
else begin |
rd_state <= rd_nxt_state; |
end |
end |
|
//---------------------------------------------------------------------------- |
// Full duplex-only state machine. |
generate if (FULL_DUPLEX_ONLY == 1) begin : gen_fd_sm |
// Decode next state, combinatorial. |
always @(rd_state, frame_in_fifo, frames_in_fifo, frame_in_fifo_valid, rd_eof, rd_eof_reg, tx_axis_mac_tready) |
begin |
case (rd_state) |
IDLE_s : begin |
// If there is a frame in the FIFO, start to queue the new frame |
// to the output. |
if ((frame_in_fifo & frame_in_fifo_valid) | frames_in_fifo) begin |
rd_nxt_state <= QUEUE1_s; |
end |
else begin |
rd_nxt_state <= IDLE_s; |
end |
end |
|
// Load the output pipeline, which takes three clock cycles. |
QUEUE1_s : begin |
rd_nxt_state <= QUEUE2_s; |
end |
|
QUEUE2_s : begin |
rd_nxt_state <= QUEUE3_s; |
end |
|
QUEUE3_s : begin |
rd_nxt_state <= START_DATA1_s; |
end |
|
START_DATA1_s : begin |
// The pipeline is full and the frame output starts now. |
rd_nxt_state <= DATA_PRELOAD1_s; |
end |
|
DATA_PRELOAD1_s : begin |
// Await the tx_axis_mac_tready acknowledge before moving on. |
if (tx_axis_mac_tready == 1'b1) begin |
rd_nxt_state <= FRAME_s; |
end |
else begin |
rd_nxt_state <= DATA_PRELOAD1_s; |
end |
end |
|
FRAME_s : begin |
// Read the frame out of the FIFO. If the MAC deasserts |
// tx_axis_mac_tready, stall in the handshake state. If the EOF |
// flag is encountered, move to the finish state. |
if (tx_axis_mac_tready == 1'b0) |
begin |
rd_nxt_state <= HANDSHAKE_s; |
end |
else if (rd_eof == 1'b1) begin |
rd_nxt_state <= FINISH_s; |
end |
else begin |
rd_nxt_state <= FRAME_s; |
end |
end |
|
HANDSHAKE_s : begin |
// Await tx_axis_mac_tready before continuing frame transmission. |
// If the EOF flag is encountered, move to the finish state. |
if (tx_axis_mac_tready == 1'b1 && rd_eof_reg == 1'b1) begin |
rd_nxt_state <= FINISH_s; |
end |
else if (tx_axis_mac_tready == 1'b1 && rd_eof_reg == 1'b0) begin |
rd_nxt_state <= FRAME_s; |
end |
else begin |
rd_nxt_state <= HANDSHAKE_s; |
end |
end |
|
FINISH_s : begin |
// Frame has finished. Assure that the MAC has accepted the final |
// byte by transitioning to idle only when tx_axis_mac_tready is high. |
if (tx_axis_mac_tready == 1'b1) begin |
rd_nxt_state <= IDLE_s; |
end |
else begin |
rd_nxt_state <= FINISH_s; |
end |
end |
|
default : begin |
rd_nxt_state <= IDLE_s; |
end |
endcase |
end |
|
end |
endgenerate |
|
//---------------------------------------------------------------------------- |
// Full and half duplex state machine. |
generate if (FULL_DUPLEX_ONLY != 1) begin : gen_hd_sm |
// Decode the next state, combinatorial. |
always @(rd_state, frame_in_fifo, frames_in_fifo, frame_in_fifo_valid, rd_eof_reg, |
tx_axis_mac_tready, rd_drop_frame, rd_retransmit) |
begin |
case (rd_state) |
IDLE_s : begin |
// If a retransmit request is detected then prepare to retransmit. |
if (rd_retransmit == 1'b1) begin |
rd_nxt_state <= RETRANSMIT_ERR_s; |
end |
// If there is a frame in the FIFO, then queue the new frame to |
// the output. |
else if ((frame_in_fifo & frame_in_fifo_valid) | frames_in_fifo) begin |
rd_nxt_state <= QUEUE1_s; |
end |
else begin |
rd_nxt_state <= IDLE_s; |
end |
end |
|
// Load the output pipeline, which takes three clock cycles. |
QUEUE1_s : begin |
if (rd_retransmit == 1'b1) begin |
rd_nxt_state <= RETRANSMIT_ERR_s; |
end |
else begin |
rd_nxt_state <= QUEUE2_s; |
end |
end |
|
QUEUE2_s : begin |
if (rd_retransmit == 1'b1) begin |
rd_nxt_state <= RETRANSMIT_ERR_s; |
end |
else begin |
rd_nxt_state <= QUEUE3_s; |
end |
end |
|
QUEUE3_s : begin |
if (rd_retransmit == 1'b1) begin |
rd_nxt_state <= RETRANSMIT_ERR_s; |
end |
else begin |
rd_nxt_state <= START_DATA1_s; |
end |
end |
|
START_DATA1_s : begin |
// The pipeline is full and the frame output starts now. |
if (rd_retransmit == 1'b1) begin |
rd_nxt_state <= RETRANSMIT_ERR_s; |
end |
else begin |
rd_nxt_state <= DATA_PRELOAD1_s; |
end |
end |
|
DATA_PRELOAD1_s : begin |
// Await the tx_axis_mac_tready acknowledge before moving on. |
if (rd_retransmit == 1'b1) begin |
rd_nxt_state <= RETRANSMIT_ERR_s; |
end |
else if (tx_axis_mac_tready == 1'b1) begin |
rd_nxt_state <= DATA_PRELOAD2_s; |
end |
else begin |
rd_nxt_state <= DATA_PRELOAD1_s; |
end |
end |
|
DATA_PRELOAD2_s : begin |
// If a collision-only request, then must drop the rest of the |
// current frame. If collision and retransmit, then prepare |
// to retransmit the frame. |
if (rd_drop_frame == 1'b1) begin |
rd_nxt_state <= DROP_ERR_s; |
end |
else if (rd_retransmit == 1'b1) begin |
rd_nxt_state <= RETRANSMIT_ERR_s; |
end |
// Read the frame out of the FIFO. If the MAC deasserts |
// tx_axis_mac_tready, stall in the handshake state. If the EOF |
// flag is encountered, move to the finish state. |
else if (tx_axis_mac_tready == 1'b0) begin |
rd_nxt_state <= WAIT_HANDSHAKE_s; |
end |
else if (rd_eof_reg == 1'b1) begin |
rd_nxt_state <= FINISH_s; |
end |
else begin |
rd_nxt_state <= DATA_PRELOAD2_s; |
end |
end |
|
WAIT_HANDSHAKE_s : begin |
// Await tx_axis_mac_tready before continuing frame transmission. |
// If the EOF flag is encountered, move to the finish state. |
if (rd_retransmit == 1'b1) begin |
rd_nxt_state <= RETRANSMIT_ERR_s; |
end |
else if (tx_axis_mac_tready == 1'b1 && rd_eof_reg == 1'b1) begin |
rd_nxt_state <= FINISH_s; |
end |
else if (tx_axis_mac_tready == 1'b1 && rd_eof_reg == 1'b0) begin |
rd_nxt_state <= FRAME_s; |
end |
else begin |
rd_nxt_state <= WAIT_HANDSHAKE_s; |
end |
end |
|
FRAME_s : begin |
// If a collision-only request, then must drop the rest of the |
// current frame. If collision and retransmit, then prepare |
// to retransmit the frame. |
if (rd_drop_frame == 1'b1) begin |
rd_nxt_state <= DROP_ERR_s; |
end |
else if (rd_retransmit == 1'b1) begin |
rd_nxt_state <= RETRANSMIT_ERR_s; |
end |
// Read the frame out of the FIFO. If the MAC deasserts |
// tx_axis_mac_tready, stall in the handshake state. If the EOF |
// flag is encountered, move to the finish state. |
else if (tx_axis_mac_tready == 1'b0) begin |
rd_nxt_state <= HANDSHAKE_s; |
end |
else if (rd_eof_reg == 1'b1) begin |
rd_nxt_state <= FINISH_s; |
end |
else begin |
rd_nxt_state <= FRAME_s; |
end |
end |
|
HANDSHAKE_s : begin |
// Await tx_axis_mac_tready before continuing frame transmission. |
// If the EOF flag is encountered, move to the finish state. |
if (rd_retransmit == 1'b1) begin |
rd_nxt_state <= RETRANSMIT_ERR_s; |
end |
else if (tx_axis_mac_tready == 1'b1 && rd_eof_reg == 1'b1) begin |
rd_nxt_state <= FINISH_s; |
end |
else if (tx_axis_mac_tready == 1'b1 && rd_eof_reg == 1'b0) begin |
rd_nxt_state <= FRAME_s; |
end |
else begin |
rd_nxt_state <= HANDSHAKE_s; |
end |
end |
|
FINISH_s : begin |
// Frame has finished. Assure that the MAC has accepted the final |
// byte by transitioning to idle only when tx_axis_mac_tready is high. |
if (rd_retransmit == 1'b1) begin |
rd_nxt_state <= RETRANSMIT_ERR_s; |
end |
if (tx_axis_mac_tready == 1'b1) begin |
rd_nxt_state <= IDLE_s; |
end |
else begin |
rd_nxt_state <= FINISH_s; |
end |
end |
|
DROP_ERR_s : begin |
// FIFO is ready to drop the frame. Assure that the MAC has |
// accepted the final byte and err signal before dropping. |
if (tx_axis_mac_tready == 1'b1) begin |
rd_nxt_state <= DROP_s; |
end |
else begin |
rd_nxt_state <= DROP_ERR_s; |
end |
end |
|
DROP_s : begin |
// Wait until rest of frame has been cleared. |
if (rd_eof_reg == 1'b1) begin |
rd_nxt_state <= IDLE_s; |
end |
else begin |
rd_nxt_state <= DROP_s; |
end |
end |
|
RETRANSMIT_ERR_s : begin |
// FIFO is ready to retransmit the frame. Assure that the MAC has |
// accepted the final byte and err signal before retransmitting. |
if (tx_axis_mac_tready == 1'b1) begin |
rd_nxt_state <= RETRANSMIT_s; |
end |
else begin |
rd_nxt_state <= RETRANSMIT_ERR_s; |
end |
end |
|
RETRANSMIT_s : begin |
// Reload the data pipeline from the start of the frame. |
rd_nxt_state <= QUEUE1_s; |
end |
|
default : begin |
rd_nxt_state <= IDLE_s; |
end |
endcase |
end |
|
end |
endgenerate |
|
// Combinatorially select tdata candidates. |
assign tx_axis_mac_tdata_int_frame = (rd_nxt_state == HANDSHAKE_s || rd_nxt_state == WAIT_HANDSHAKE_s) ? |
tx_axis_mac_tdata_int : rd_data_pipe; |
assign tx_axis_mac_tdata_int_handshake = (rd_nxt_state == FINISH_s) ? |
rd_data_pipe : tx_axis_mac_tdata_int; |
assign tx_axis_mac_tdata = tx_axis_mac_tdata_int; |
|
// Decode output tdata based on current and next read state. |
always @(posedge tx_mac_aclk) |
begin |
if (rd_nxt_state == FRAME_s || rd_nxt_state == DATA_PRELOAD2_s) |
tx_axis_mac_tdata_int <= rd_data_pipe; |
else if (rd_nxt_state == RETRANSMIT_ERR_s || rd_nxt_state == DROP_ERR_s) |
tx_axis_mac_tdata_int <= tx_axis_mac_tdata_int; |
else begin |
case (rd_state) |
START_DATA1_s : |
tx_axis_mac_tdata_int <= rd_data_pipe; |
FRAME_s, DATA_PRELOAD2_s : |
tx_axis_mac_tdata_int <= tx_axis_mac_tdata_int_frame; |
HANDSHAKE_s, WAIT_HANDSHAKE_s: |
tx_axis_mac_tdata_int <= tx_axis_mac_tdata_int_handshake; |
default : |
tx_axis_mac_tdata_int <= tx_axis_mac_tdata_int; |
endcase |
end |
end |
|
// Combinatorially select tvalid candidates. |
assign tx_axis_mac_tvalid_int_finish = (rd_nxt_state == IDLE_s) ? |
1'b0 : 1'b1; |
assign tx_axis_mac_tvalid_int_droperr = (rd_nxt_state == DROP_s) ? |
1'b0 : 1'b1; |
assign tx_axis_mac_tvalid_int_retransmiterr = (rd_nxt_state == RETRANSMIT_s) ? |
1'b0 : 1'b1; |
|
// Decode output tvalid based on current and next read state. |
always @(posedge tx_mac_aclk) |
begin |
if (rd_nxt_state == FRAME_s || rd_nxt_state == DATA_PRELOAD2_s) |
tx_axis_mac_tvalid <= 1'b1; |
else if (rd_nxt_state == RETRANSMIT_ERR_s || rd_nxt_state == DROP_ERR_s) |
tx_axis_mac_tvalid <= 1'b1; |
else |
begin |
case (rd_state) |
START_DATA1_s : |
tx_axis_mac_tvalid <= 1'b1; |
DATA_PRELOAD1_s : |
tx_axis_mac_tvalid <= 1'b1; |
FRAME_s, DATA_PRELOAD2_s : |
tx_axis_mac_tvalid <= 1'b1; |
HANDSHAKE_s, WAIT_HANDSHAKE_s : |
tx_axis_mac_tvalid <= 1'b1; |
FINISH_s : |
tx_axis_mac_tvalid <= tx_axis_mac_tvalid_int_finish; |
DROP_ERR_s : |
tx_axis_mac_tvalid <= tx_axis_mac_tvalid_int_droperr; |
RETRANSMIT_ERR_s : |
tx_axis_mac_tvalid <= tx_axis_mac_tvalid_int_retransmiterr; |
default : |
tx_axis_mac_tvalid <= 1'b0; |
endcase |
end |
end |
|
// Combinatorially select tlast candidates. |
assign tx_axis_mac_tlast_int_frame_handshake = (rd_nxt_state == FINISH_s) ? |
rd_eof_reg : 1'b0; |
assign tx_axis_mac_tlast_int_finish = (rd_nxt_state == IDLE_s) ? |
1'b0 : rd_eof_reg; |
assign tx_axis_mac_tlast_int_droperr = (rd_nxt_state == DROP_s) ? |
1'b0 : 1'b1; |
assign tx_axis_mac_tlast_int_retransmiterr = (rd_nxt_state == RETRANSMIT_s) ? |
1'b0 : 1'b1; |
|
// Decode output tlast based on current and next read state. |
always @(posedge tx_mac_aclk) |
begin |
if (rd_nxt_state == FRAME_s || rd_nxt_state == DATA_PRELOAD2_s) |
tx_axis_mac_tlast <= rd_eof; |
else if (rd_nxt_state == RETRANSMIT_ERR_s || rd_nxt_state == DROP_ERR_s) |
tx_axis_mac_tlast <= 1'b1; |
else |
begin |
case (rd_state) |
DATA_PRELOAD1_s : |
tx_axis_mac_tlast <= rd_eof; |
FRAME_s, DATA_PRELOAD2_s : |
tx_axis_mac_tlast <= tx_axis_mac_tlast_int_frame_handshake; |
HANDSHAKE_s, WAIT_HANDSHAKE_s : |
tx_axis_mac_tlast <= tx_axis_mac_tlast_int_frame_handshake; |
FINISH_s : |
tx_axis_mac_tlast <= tx_axis_mac_tlast_int_finish; |
DROP_ERR_s : |
tx_axis_mac_tlast <= tx_axis_mac_tlast_int_droperr; |
RETRANSMIT_ERR_s : |
tx_axis_mac_tlast <= tx_axis_mac_tlast_int_retransmiterr; |
default : |
tx_axis_mac_tlast <= 1'b0; |
endcase |
end |
end |
|
// Combinatorially select tuser candidates. |
assign tx_axis_mac_tuser_int_droperr = (rd_nxt_state == DROP_s) ? |
1'b0 : 1'b1; |
assign tx_axis_mac_tuser_int_retransmit = (rd_nxt_state == RETRANSMIT_s) ? |
1'b0 : 1'b1; |
|
// Decode output tuser based on current and next read state. |
always @(posedge tx_mac_aclk) |
begin |
if (rd_nxt_state == RETRANSMIT_ERR_s || rd_nxt_state == DROP_ERR_s) |
tx_axis_mac_tuser <= 1'b1; |
else |
begin |
case (rd_state) |
DROP_ERR_s : |
tx_axis_mac_tuser <= tx_axis_mac_tuser_int_droperr; |
RETRANSMIT_ERR_s : |
tx_axis_mac_tuser <= tx_axis_mac_tuser_int_retransmit; |
default : |
tx_axis_mac_tuser <= 1'b0; |
endcase |
end |
end |
|
//---------------------------------------------------------------------------- |
// Decode full duplex-only control signals. |
generate if (FULL_DUPLEX_ONLY == 1) begin : gen_fd_decode |
|
// rd_en is used to enable the BRAM read and load the output pipeline. |
assign rd_en = (rd_state == IDLE_s) ? 1'b0 : |
(rd_nxt_state == FRAME_s) ? 1'b1 : |
(rd_state == FRAME_s && rd_nxt_state == HANDSHAKE_s) ? 1'b0 : |
(rd_nxt_state == HANDSHAKE_s) ? 1'b0 : |
(rd_state == FINISH_s) ? 1'b0 : |
(rd_state == DATA_PRELOAD1_s) ? 1'b0 : 1'b1; |
|
// When the BRAM is being read, enable the read address to be incremented. |
assign rd_addr_inc = rd_en; |
|
assign rd_addr_reload = (rd_state != FINISH_s && rd_nxt_state == FINISH_s) |
? 1'b1 : 1'b0; |
|
// Transmit frame pulse must never be more frequent than once per 64 clocks to |
// allow toggle to cross clock domain. |
assign rd_transmit_frame = (rd_state == FINISH_s && rd_nxt_state == IDLE_s) |
? 1'b1 : 1'b0; |
|
// Unused for full duplex only. |
assign rd_start_addr_reload = 1'b0; |
assign rd_start_addr_load = 1'b0; |
assign rd_retransmit_frame = 1'b0; |
|
end |
endgenerate |
|
//---------------------------------------------------------------------------- |
// Decode full and half duplex control signals. |
generate if (FULL_DUPLEX_ONLY != 1) begin : gen_hd_decode |
|
// rd_en is used to enable the BRAM read and load the output pipeline. |
assign rd_en = (rd_state == IDLE_s) ? 1'b0 : |
(rd_nxt_state == DROP_ERR_s) ? 1'b0 : |
(rd_nxt_state == DROP_s && rd_eof == 1'b1) ? 1'b0 : |
(rd_nxt_state == FRAME_s || rd_nxt_state == DATA_PRELOAD2_s) ? 1'b1 : |
(rd_state == DATA_PRELOAD2_s && rd_nxt_state == WAIT_HANDSHAKE_s) ? 1'b0 : |
(rd_state == FRAME_s && rd_nxt_state == HANDSHAKE_s) ? 1'b0 : |
(rd_nxt_state == HANDSHAKE_s || rd_nxt_state == WAIT_HANDSHAKE_s) ? 1'b0 : |
(rd_state == FINISH_s) ? 1'b0 : |
(rd_state == RETRANSMIT_ERR_s) ? 1'b0 : |
(rd_state == RETRANSMIT_s) ? 1'b0 : |
(rd_state == DATA_PRELOAD1_s) ? 1'b0 : 1'b1; |
|
// When the BRAM is being read, enable the read address to be incremented. |
assign rd_addr_inc = rd_en; |
|
assign rd_addr_reload = (rd_state != FINISH_s && rd_nxt_state == FINISH_s) |
? 1'b1 : |
(rd_state == DROP_s && rd_nxt_state == IDLE_s) |
? 1'b1 : 1'b0; |
|
// Assertion indicates that the starting address must be reloaded to enable |
// the current frame to be retransmitted. |
assign rd_start_addr_reload = (rd_state == RETRANSMIT_s) ? 1'b1 : 1'b0; |
|
assign rd_start_addr_load = (rd_state== WAIT_HANDSHAKE_s && rd_nxt_state == FRAME_s) |
? 1'b1 : |
(rd_col_window_expire == 1'b1) ? 1'b1 : 1'b0; |
|
// Transmit frame pulse must never be more frequent than once per 64 clocks to |
// allow toggle to cross clock domain. |
assign rd_transmit_frame = (rd_state == FINISH_s && rd_nxt_state == IDLE_s) |
? 1'b1 : 1'b0; |
|
// Retransmit frame pulse must never be more frequent than once per 16 clocks |
// to allow toggle to cross clock domain. |
assign rd_retransmit_frame = (rd_state == RETRANSMIT_s) ? 1'b1 : 1'b0; |
|
end |
endgenerate |
|
|
//---------------------------------------------------------------------------- |
// Frame count |
// We need to maintain a count of frames in the FIFO, so that we know when a |
// frame is available for transmission. The counter must be held on the write |
// clock domain as this is the faster clock if they differ. |
//---------------------------------------------------------------------------- |
|
// A frame has been written to the FIFO. |
assign wr_store_frame = (wr_state == EOF_s && wr_nxt_state != EOF_s) |
? 1'b1 : 1'b0; |
|
// Generate a toggle to indicate when a frame has been transmitted by the FIFO. |
always @(posedge tx_mac_aclk) |
begin |
if (rd_transmit_frame == 1'b1) begin |
rd_tran_frame_tog <= !rd_tran_frame_tog; |
end |
end |
|
// Synchronize the read transmit frame signal into the write clock domain. |
tri_mode_ethernet_mac_0_sync_block resync_rd_tran_frame_tog |
( |
.clk (tx_fifo_aclk), |
.data_in (rd_tran_frame_tog), |
.data_out (wr_tran_frame_sync) |
); |
|
// Edge-detect of the resynchronized transmit frame signal. |
|
always @(posedge tx_fifo_aclk) |
begin |
wr_tran_frame_delay <= wr_tran_frame_sync; |
end |
|
always @(posedge tx_fifo_aclk) |
begin |
if (tx_fifo_reset == 1'b1) begin |
wr_transmit_frame <= 1'b0; |
end |
else begin |
// Edge detector |
if ((wr_tran_frame_delay ^ wr_tran_frame_sync) == 1'b1) begin |
wr_transmit_frame <= 1'b1; |
end |
else begin |
wr_transmit_frame <= 1'b0; |
end |
end |
end |
|
always @(posedge tx_fifo_aclk) |
begin |
if (tx_fifo_reset == 1'b1) begin |
wr_transmit_frame_delay <= 1'b0; |
end |
else begin |
wr_transmit_frame_delay <= wr_transmit_frame; |
end |
end |
|
always @(posedge tx_fifo_aclk) |
begin |
if (wr_transmit_frame_delay) begin |
frame_in_fifo_valid_tog <= !frame_in_fifo_valid_tog; |
end |
end |
|
//---------------------------------------------------------------------------- |
// Full duplex-only frame count. |
generate if (FULL_DUPLEX_ONLY == 1) begin : gen_fd_count |
|
// Count the number of frames in the FIFO. The counter is incremented when a |
// frame is stored and decremented when a frame is transmitted. Need to keep |
// the counter on the write clock as this is the fastest clock if they differ. |
always @(posedge tx_fifo_aclk) |
begin |
if (tx_fifo_reset == 1'b1) begin |
wr_frames <= 9'b0; |
end |
else begin |
if ((wr_store_frame & !wr_transmit_frame) == 1'b1) begin |
wr_frames <= wr_frames + 9'b1; |
end |
else if ((!wr_store_frame & wr_transmit_frame) == 1'b1) begin |
wr_frames <= wr_frames - 9'b1; |
end |
end |
end |
|
end |
endgenerate |
|
//---------------------------------------------------------------------------- |
// Full and half duplex frame count. |
generate if (FULL_DUPLEX_ONLY != 1) begin : gen_hd_count |
|
// Generate a toggle to indicate when a frame has been retransmitted by |
// the FIFO. |
always @(posedge tx_mac_aclk) |
begin // process |
if (rd_retransmit_frame == 1'b1) begin |
rd_retran_frame_tog <= !rd_retran_frame_tog; |
end |
end |
|
// Synchronize the read retransmit frame signal into the write clock domain. |
tri_mode_ethernet_mac_0_sync_block resync_rd_tran_frame_tog |
( |
.clk (tx_fifo_aclk), |
.data_in (rd_retran_frame_tog), |
.data_out (wr_retran_frame_sync) |
); |
|
// Edge detect of the resynchronized retransmit frame signal. |
|
always @(posedge tx_fifo_aclk) |
begin |
wr_retran_frame_delay <= wr_retran_frame_sync; |
end |
|
always @(posedge tx_fifo_aclk) |
begin |
if (tx_fifo_reset == 1'b1) begin |
wr_retransmit_frame <= 1'b0; |
end |
else begin |
// Edge detector |
if ((wr_retran_frame_delay ^ wr_retran_frame_sync) == 1'b1) begin |
wr_retransmit_frame <= 1'b1; |
end |
else begin |
wr_retransmit_frame <= 1'b0; |
end |
end |
end |
|
// Count the number of frames in the FIFO. The counter is incremented when a |
// frame is stored or retransmitted and decremented when a frame is |
// transmitted. Need to keep the counter on the write clock as this is the |
// fastest clock if they differ. Logic assumes transmit and retransmit cannot |
// happen at same time. |
always @(posedge tx_fifo_aclk) |
begin |
if (tx_fifo_reset == 1'b1) begin |
wr_frames <= 9'd0; |
end |
else begin |
if ((wr_store_frame & wr_retransmit_frame) == 1'b1) begin |
wr_frames <= wr_frames + 9'd2; |
end |
else if (((wr_store_frame | wr_retransmit_frame) |
& !wr_transmit_frame) == 1'b1) begin |
wr_frames <= wr_frames + 9'd1; |
end |
else if (wr_transmit_frame == 1'b1 & !wr_store_frame) begin |
wr_frames <= wr_frames - 9'd1; |
end |
end |
end |
|
end |
endgenerate |
|
// Generate a frame in FIFO signal for use in control logic. |
always @(posedge tx_fifo_aclk) |
begin |
if (tx_fifo_reset == 1'b1) begin |
wr_frame_in_fifo <= 1'b0; |
end |
else begin |
if (wr_frames != 9'b0) begin |
wr_frame_in_fifo <= 1'b1; |
end |
else begin |
wr_frame_in_fifo <= 1'b0; |
end |
end |
end |
|
// Generate a multiple frames in FIFO signal for use in control logic. |
always @(posedge tx_fifo_aclk) |
begin |
if (tx_fifo_reset == 1'b1) begin |
wr_frames_in_fifo <= 1'b0; |
end |
else begin |
if (wr_frames >= 9'h2) begin |
wr_frames_in_fifo <= 1'b1; |
end |
else begin |
wr_frames_in_fifo <= 1'b0; |
end |
end |
end |
|
// Synchronize it back onto read domain for use in the read logic. |
tri_mode_ethernet_mac_0_sync_block resync_wr_frame_in_fifo |
( |
.clk (tx_mac_aclk), |
.data_in (wr_frame_in_fifo), |
.data_out (frame_in_fifo) |
); |
|
// Synchronize it back onto read domain for use in the read logic. |
tri_mode_ethernet_mac_0_sync_block resync_wr_frames_in_fifo |
( |
.clk (tx_mac_aclk), |
.data_in (wr_frames_in_fifo), |
.data_out (frames_in_fifo) |
); |
|
// in he case where only one frame is in the fifo we have to be careful about the faling edge of |
// the frame in fifo signal as for short frames this could occur after the state machine completes |
tri_mode_ethernet_mac_0_sync_block resync_fif_valid_tog |
( |
.clk (tx_mac_aclk), |
.data_in (frame_in_fifo_valid_tog), |
.data_out (frame_in_fifo_valid_sync) |
); |
|
// Edge detect of the re-resynchronized read transmit frame signal. |
always @(posedge tx_mac_aclk) |
begin |
frame_in_fifo_valid_delay <= frame_in_fifo_valid_sync; |
end |
|
always @(posedge tx_mac_aclk) |
begin |
if (tx_mac_reset == 1'b1) begin |
frame_in_fifo_valid = 1'b1; |
end |
else begin |
if (frame_in_fifo_valid_delay ^ frame_in_fifo_valid_sync) begin |
frame_in_fifo_valid <= 1'b1; |
end |
else if (rd_transmit_frame) begin |
frame_in_fifo_valid <= 1'b0; |
end |
end |
end |
|
|
//---------------------------------------------------------------------------- |
// Address counters |
//---------------------------------------------------------------------------- |
|
// Write address is incremented when write enable signal has been asserted. |
always @(posedge tx_fifo_aclk) |
begin |
if (tx_fifo_reset == 1'b1) begin |
wr_addr <= 12'b0; |
end |
else if (wr_addr_reload == 1'b1) begin |
wr_addr <= wr_start_addr; |
end |
else if (wr_addr_inc == 1'b1) begin |
wr_addr <= wr_addr + 12'b1; |
end |
end |
|
// Store the start address in case the address must be reset. |
always @(posedge tx_fifo_aclk) |
begin |
if (tx_fifo_reset == 1'b1) begin |
wr_start_addr <= 12'b0; |
end |
else if (wr_start_addr_load == 1'b1) begin |
wr_start_addr <= wr_addr + 12'b1; |
end |
end |
|
//---------------------------------------------------------------------------- |
// Half duplex-only read address counters. |
generate if (FULL_DUPLEX_ONLY == 1) begin : gen_fd_addr |
// Read address is incremented when read enable signal has been asserted. |
always @(posedge tx_mac_aclk) |
begin |
if (tx_mac_reset == 1'b1) begin |
rd_addr <= 12'b0; |
end |
else begin |
if (rd_addr_reload == 1'b1) begin |
rd_addr <= rd_dec_addr; |
end |
else if (rd_addr_inc == 1'b1) begin |
rd_addr <= rd_addr + 12'b1; |
end |
end |
end |
|
// Do not need to keep a start address, but the address is needed to |
// calculate FIFO occupancy. |
always @(posedge tx_mac_aclk) |
begin |
if (tx_mac_reset == 1'b1) begin |
rd_start_addr <= 12'b0; |
end |
else begin |
rd_start_addr <= rd_addr; |
end |
end |
|
end |
endgenerate |
|
//---------------------------------------------------------------------------- |
// Full and half duplex read address counters. |
generate if (FULL_DUPLEX_ONLY != 1) begin : gen_hd_addr |
// Read address is incremented when read enable signal has been asserted. |
always @(posedge tx_mac_aclk) |
begin |
if (tx_mac_reset == 1'b1) begin |
rd_addr <= 12'b0; |
end |
else begin |
if (rd_addr_reload == 1'b1) begin |
rd_addr <= rd_dec_addr; |
end |
else if (rd_start_addr_reload == 1'b1) begin |
rd_addr <= rd_start_addr; |
end |
else if (rd_addr_inc == 1'b1) begin |
rd_addr <= rd_addr + 12'b1; |
end |
end |
end |
|
always @(posedge tx_mac_aclk) |
begin |
if (tx_mac_reset == 1'b1) begin |
rd_start_addr <= 12'd0; |
end |
else begin |
if (rd_start_addr_load == 1'b1) begin |
rd_start_addr <= rd_addr - 12'd6; |
end |
end |
end |
|
// Collision window expires after MAC has been transmitting for required slot |
// time. This is 512 clock cycles at 1Gbps. Also if the end of frame has fully |
// been transmitted by the MAC then a collision cannot occur. This collision |
// expiration signal goes high at 768 cycles from the start of the frame. |
// This is inefficient for short frames, however it should be enough to |
// prevent the FIFO from locking up. |
always @(posedge tx_mac_aclk) |
begin |
if (tx_mac_reset == 1'b1) begin |
rd_col_window_expire <= 1'b0; |
end |
else begin |
if (rd_transmit_frame == 1'b1) begin |
rd_col_window_expire <= 1'b0; |
end |
else if (rd_slot_timer[9:7] == 3'b110) begin |
rd_col_window_expire <= 1'b1; |
end |
end |
end |
|
assign rd_idle_state = (rd_state == IDLE_s) ? 1'b1 : 1'b0; |
|
always @(posedge tx_mac_aclk) |
begin |
rd_col_window_pipe[0] <= rd_col_window_expire & rd_idle_state; |
if (rd_txfer_en == 1'b1) begin |
rd_col_window_pipe[1] <= rd_col_window_pipe[0]; |
end |
end |
|
always @(posedge tx_mac_aclk) |
begin |
// Will not count until after the first frame is sent. |
if (tx_mac_reset == 1'b1) begin |
rd_slot_timer <= 10'b1111111111; |
end |
else begin |
// Reset counter. |
if (rd_transmit_frame == 1'b1) begin |
rd_slot_timer <= 10'b0; |
end |
// Do not allow counter to roll over, and |
// only count when frame is being transmitted. |
else if (rd_slot_timer != 10'b1111111111) begin |
rd_slot_timer <= rd_slot_timer + 10'b1; |
end |
end |
end |
|
end |
endgenerate |
|
// Read address generation. |
always @(posedge tx_mac_aclk) |
begin |
if (tx_mac_reset == 1'b1) begin |
rd_dec_addr <= 12'b0; |
end |
else begin |
if (rd_addr_inc == 1'b1) begin |
rd_dec_addr <= rd_addr - 12'b1; |
end |
end |
end |
|
|
//---------------------------------------------------------------------------- |
// Data pipelines |
//---------------------------------------------------------------------------- |
|
|
// Register data inputs to BRAM. |
// No resets to allow for SRL16 target. |
always @(posedge tx_fifo_aclk) |
begin |
wr_data_pipe[0] <= tx_axis_fifo_tdata; |
if (wr_accept_pipe[0] == 1'b1) begin |
wr_data_pipe[1] <= wr_data_pipe[0]; |
end |
if (wr_accept_pipe[1] == 1'b1) begin |
wr_data_bram <= wr_data_pipe[1]; |
end |
end |
|
|
|
// Start of frame set when tvalid is asserted and previous frame has ended. |
assign wr_sof_int = tx_axis_fifo_tvalid & wr_eof_reg; |
|
// Set end of frame flag when tlast and tvalid are asserted together. |
// Reset to logic 1 to enable first frame's start of frame flag. |
always @(posedge tx_fifo_aclk) |
begin |
if (tx_fifo_reset == 1'b1) begin |
wr_eof_reg <= 1'b1; |
end |
else begin |
if (tx_axis_fifo_tvalid == 1'b1 & tx_axis_fifo_tready_int_n == 1'b0) begin |
wr_eof_reg <= tx_axis_fifo_tlast; |
end |
end |
end |
|
// Pipeline the start of frame flag when the pipe is enabled. |
always @(posedge tx_fifo_aclk) |
begin |
wr_sof_pipe[0] <= wr_sof_int & !tx_axis_fifo_tlast; |
if (wr_accept_pipe[0] == 1'b1) begin |
wr_sof_pipe[1] <= wr_sof_pipe[0]; |
end |
end |
|
// Pipeline the pipeline enable signal, which is derived from simultaneous |
// assertion of tvalid and tready. |
always @(posedge tx_fifo_aclk) |
begin |
if (tx_fifo_reset == 1'b1) begin |
wr_accept_pipe[0] <= 1'b0; |
wr_accept_pipe[1] <= 1'b0; |
wr_accept_bram <= 1'b0; |
end |
else begin |
wr_accept_pipe[0] <= tx_axis_fifo_tvalid & !tx_axis_fifo_tready_int_n & |
!(tx_axis_fifo_tlast & wr_sof_int); |
wr_accept_pipe[1] <= wr_accept_pipe[0]; |
wr_accept_bram <= wr_accept_pipe[1]; |
end |
end |
|
// Pipeline the end of frame flag when the pipe is enabled. |
always @(posedge tx_fifo_aclk) |
begin |
wr_eof_pipe[0] <= tx_axis_fifo_tvalid & tx_axis_fifo_tlast & !wr_sof_int; |
if (wr_accept_pipe[0] == 1'b1) begin |
wr_eof_pipe[1] <= wr_eof_pipe[0]; |
end |
if (wr_accept_pipe[1] == 1'b1) begin |
wr_eof_bram[0] <= wr_eof_pipe[1]; |
end |
end |
|
// Register data outputs from BRAM. |
// No resets to allow for SRL16 target. |
always @(posedge tx_mac_aclk) |
begin |
if (rd_en == 1'b1) begin |
rd_data_delay <= rd_data_bram; |
rd_data_pipe <= rd_data_delay; |
end |
end |
|
always @(posedge tx_mac_aclk) |
begin |
if (rd_en == 1'b1) begin |
rd_eof_pipe <= rd_eof_bram[0]; |
rd_eof <= rd_eof_pipe; |
rd_eof_reg <= rd_eof | rd_eof_pipe; |
end |
end |
|
//---------------------------------------------------------------------------- |
// Half duplex-only drop and retransmission controls. |
generate if (FULL_DUPLEX_ONLY != 1) begin : gen_hd_input |
// Register the collision without retransmit signal, which is a pulse that |
// causes the FIFO to drop the frame. |
always @(posedge tx_mac_aclk) |
begin |
rd_drop_frame <= tx_collision & !tx_retransmit; |
end |
|
// Register the collision with retransmit signal, which is a pulse that |
// causes the FIFO to retransmit the frame. |
always @(posedge tx_mac_aclk) |
begin |
rd_retransmit <= tx_collision & tx_retransmit; |
end |
end |
endgenerate |
|
|
//---------------------------------------------------------------------------- |
// FIFO full functionality |
//---------------------------------------------------------------------------- |
|
// Full functionality is the difference between read and write addresses. |
// We cannot use gray code this time as the read address and read start |
// addresses jump by more than 1. |
// We generate an enable pulse for the read side every 16 read clocks. This |
// provides for the worst-case situation where the write clock is 20MHz and |
// read clock is 125MHz. |
always @(posedge tx_mac_aclk) |
begin |
if (tx_mac_reset == 1'b1) begin |
rd_16_count <= 4'b0; |
end |
else begin |
rd_16_count <= rd_16_count + 4'b1; |
end |
end |
|
assign rd_txfer_en = (rd_16_count == 4'b1111) ? 1'b1 : 1'b0; |
|
// Register the start address on the enable pulse. |
always @(posedge tx_mac_aclk) |
begin |
if (tx_mac_reset == 1'b1) begin |
rd_addr_txfer <= 12'b0; |
end |
else begin |
if (rd_txfer_en == 1'b1) begin |
rd_addr_txfer <= rd_start_addr; |
end |
end |
end |
|
// Generate a toggle to indicate that the address has been loaded. |
always @(posedge tx_mac_aclk) |
begin |
if (rd_txfer_en == 1'b1) begin |
rd_txfer_tog <= !rd_txfer_tog; |
end |
end |
|
// Synchronize the toggle to the write side. |
tri_mode_ethernet_mac_0_sync_block resync_rd_txfer_tog |
( |
.clk (tx_fifo_aclk), |
.data_in (rd_txfer_tog), |
.data_out (wr_txfer_tog_sync) |
); |
|
// Delay the synchronized toggle by one cycle. |
always @(posedge tx_fifo_aclk) |
begin |
wr_txfer_tog_delay <= wr_txfer_tog_sync; |
end |
|
// Generate an enable pulse from the toggle. The address should have been |
// steady on the wr clock input for at least one clock. |
assign wr_txfer_en = wr_txfer_tog_delay ^ wr_txfer_tog_sync; |
|
// Capture the address on the write clock when the enable pulse is high. |
always @(posedge tx_fifo_aclk) |
begin |
if (tx_fifo_reset == 1'b1) begin |
wr_rd_addr <= 12'b0; |
end |
else if (wr_txfer_en == 1'b1) begin |
wr_rd_addr <= rd_addr_txfer; |
end |
end |
|
// Obtain the difference between write and read pointers. |
always @(posedge tx_fifo_aclk) |
begin |
if (tx_fifo_reset == 1'b1) begin |
wr_addr_diff <= 12'b0; |
end |
else begin |
wr_addr_diff <= wr_rd_addr - wr_addr; |
end |
end |
|
// Detect when the FIFO is full. |
// The FIFO is considered to be full if the write address pointer is |
// within 0 to 3 of the read address pointer. |
always @(posedge tx_fifo_aclk) |
begin |
if (tx_fifo_reset == 1'b1) begin |
wr_fifo_full <= 1'b0; |
end |
else begin |
if (wr_addr_diff[11:4] == 8'b0 && wr_addr_diff[3:2] != 2'b0) begin |
wr_fifo_full <= 1'b1; |
end |
else begin |
wr_fifo_full <= 1'b0; |
end |
end |
end |
|
// Memory overflow occurs when the FIFO is full and there are no frames |
// available in the FIFO for transmission. If the collision window has |
// expired and there are no frames in the FIFO and the FIFO is full, then the |
// FIFO is in an overflow state. We must accept the rest of the incoming |
// frame in overflow condition. |
|
generate if (FULL_DUPLEX_ONLY == 1) begin : gen_fd_ovflow |
// In full duplex mode, the FIFO memory can only overflow if the FIFO goes |
// full but there is no frame available to be retranmsitted. Therefore, |
// prevent signal from being asserted when store_frame signal is high, as |
// frame count is being updated. |
assign wr_fifo_overflow = (wr_fifo_full == 1'b1 && wr_frame_in_fifo == 1'b0 |
&& wr_eof_state == 1'b0 |
&& wr_eof_state_reg == 1'b0) |
? 1'b1 : 1'b0; |
|
// Tie off unused half-duplex signals |
always @(posedge tx_fifo_aclk) |
begin |
wr_col_window_pipe[0] <= 1'b0; |
wr_col_window_pipe[1] <= 1'b0; |
end |
|
end |
endgenerate |
|
generate if (FULL_DUPLEX_ONLY != 1) begin : gen_hd_ovflow |
// In half duplex mode, register write collision window to give address |
// counter sufficient time to update. This will prevent the signal from |
// being asserted when the store_frame signal is high, as the frame count |
// is being updated. |
assign wr_fifo_overflow = (wr_fifo_full == 1'b1 && wr_frame_in_fifo == 1'b0 |
&& wr_eof_state == 1'b0 |
&& wr_eof_state_reg == 1'b0 |
&& wr_col_window_expire == 1'b1) |
? 1'b1 : 1'b0; |
|
// Register rd_col_window signal. |
// This signal is long, and will remain high until overflow functionality |
// has finished, so save just to register once. |
always @(posedge tx_fifo_aclk) |
begin |
if (tx_fifo_reset == 1'b1) begin |
wr_col_window_pipe[0] <= 1'b0; |
wr_col_window_pipe[1] <= 1'b0; |
wr_col_window_expire <= 1'b0; |
end |
else begin |
if (wr_txfer_en == 1'b1) begin |
wr_col_window_pipe[0] <= rd_col_window_pipe[1]; |
end |
wr_col_window_pipe[1] <= wr_col_window_pipe[0]; |
wr_col_window_expire <= wr_col_window_pipe[1]; |
end |
end |
|
end |
endgenerate |
|
|
//---------------------------------------------------------------------------- |
// FIFO status signals |
//---------------------------------------------------------------------------- |
|
// The FIFO status is four bits which represents the occupancy of the FIFO |
// in sixteenths. To generate this signal we therefore only need to compare |
// the 4 most significant bits of the write address pointer with the 4 most |
// significant bits of the read address pointer. |
|
always @(posedge tx_fifo_aclk) |
begin |
if (tx_fifo_reset == 1'b1) begin |
wr_fifo_status <= 4'b0; |
end |
else begin |
if (wr_addr_diff == 12'b0) begin |
wr_fifo_status <= 4'b0; |
end |
else begin |
wr_fifo_status[3] <= !wr_addr_diff[11]; |
wr_fifo_status[2] <= !wr_addr_diff[10]; |
wr_fifo_status[1] <= !wr_addr_diff[9]; |
wr_fifo_status[0] <= !wr_addr_diff[8]; |
end |
end |
end |
|
assign fifo_status = wr_fifo_status; |
|
|
//---------------------------------------------------------------------------- |
// Instantiate FIFO block memory |
//---------------------------------------------------------------------------- |
|
assign wr_eof_data_bram[8] = wr_eof_bram[0]; |
assign wr_eof_data_bram[7:0] = wr_data_bram; |
|
assign rd_eof_bram[0] = rd_eof_data_bram[8]; |
assign rd_data_bram = rd_eof_data_bram[7:0]; |
|
tri_mode_ethernet_mac_0_bram_tdp # |
( |
.DATA_WIDTH (9), |
.ADDR_WIDTH (12) |
) |
tx_ramgen_i ( |
.b_dout (rd_eof_data_bram), |
.a_addr (wr_addr[11:0]), |
.b_addr (rd_addr[11:0]), |
.a_clk (tx_fifo_aclk), |
.b_clk (tx_mac_aclk), |
.a_din (wr_eof_data_bram), |
.b_en (rd_en), |
.a_rst (tx_fifo_reset), |
.b_rst (tx_mac_reset), |
.a_wr (wr_en) |
); |
|
endmodule |
/trunk/hw/src/rtl/tri_mode_emac/src/support/tri_mode_ethernet_mac_0_support.v
0,0 → 1,308
//------------------------------------------------------------------------------ |
// Title : Verilog Support Level Module |
// File : tri_mode_ethernet_mac_0_support.v |
// Author : Xilinx Inc. |
// ----------------------------------------------------------------------------- |
// (c) Copyright 2013 Xilinx, Inc. All rights reserved. |
// |
// This file contains confidential and proprietary information |
// of Xilinx, Inc. and is protected under U.S. and |
// international copyright and other intellectual property |
// laws. |
// |
// DISCLAIMER |
// This disclaimer is not a license and does not grant any |
// rights to the materials distributed herewith. Except as |
// otherwise provided in a valid license issued to you by |
// Xilinx, and to the maximum extent permitted by applicable |
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND |
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES |
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING |
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- |
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and |
// (2) Xilinx shall not be liable (whether in contract or tort, |
// including negligence, or under any other theory of |
// liability) for any loss or damage of any kind or nature |
// related to, arising under or in connection with these |
// materials, including for any direct, or any indirect, |
// special, incidental, or consequential loss or damage |
// (including loss of data, profits, goodwill, or any type of |
// loss or damage suffered as a result of any action brought |
// by a third party) even if such damage or loss was |
// reasonably foreseeable or Xilinx had been advised of the |
// possibility of the same. |
// |
// CRITICAL APPLICATIONS |
// Xilinx products are not designed or intended to be fail- |
// safe, or for use in any application requiring fail-safe |
// performance, such as life-support or safety devices or |
// systems, Class III medical devices, nuclear facilities, |
// applications related to the deployment of airbags, or any |
// other applications that could lead to death, personal |
// injury, or severe property or environmental damage |
// (individually and collectively, "Critical |
// Applications"). Customer assumes the sole risk and |
// liability of any use of Xilinx products in Critical |
// Applications, subject only to applicable laws and |
// regulations governing limitations on product liability. |
// |
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS |
// PART OF THIS FILE AT ALL TIMES. |
// ----------------------------------------------------------------------------- |
// Description: This module holds the support level for the Tri-Mode |
// Ethernet MAC IP. It contains potentially shareable FPGA |
// resources such as clocking, reset and IDELAYCTRL logic. |
// This can be used as-is in a single core design, or adapted |
// for use with multi-core implementations. |
//------------------------------------------------------------------------------ |
|
|
`timescale 1 ps/1 ps |
|
|
//------------------------------------------------------------------------------ |
// The entity declaration for the block support level |
//------------------------------------------------------------------------------ |
module tri_mode_ethernet_mac_0_support |
( |
input gtx_clk, |
output gtx_clk_out, |
output gtx_clk90_out, |
// Reference clock for IDELAYCTRL's |
input refclk, |
|
// asynchronous reset |
input glbl_rstn, |
input rx_axi_rstn, |
input tx_axi_rstn, |
|
// Receiver Interface |
//-------------------------- |
output rx_enable, |
|
output [27:0] rx_statistics_vector, |
output rx_statistics_valid, |
|
output rx_mac_aclk, |
output rx_reset, |
output [7:0] rx_axis_mac_tdata, |
output rx_axis_mac_tvalid, |
output rx_axis_mac_tlast, |
output rx_axis_mac_tuser, |
|
|
// Transmitter Interface |
//----------------------------- |
output tx_enable, |
|
input [7:0] tx_ifg_delay, |
output [31:0] tx_statistics_vector, |
output tx_statistics_valid, |
|
output tx_mac_aclk, |
output tx_reset, |
input [7:0] tx_axis_mac_tdata, |
input tx_axis_mac_tvalid, |
input tx_axis_mac_tlast, |
input tx_axis_mac_tuser, |
output tx_axis_mac_tready, |
|
// MAC Control Interface |
//---------------------- |
input pause_req, |
input [15:0] pause_val, |
|
output speedis100, |
output speedis10100, |
|
// RGMII Interface |
//---------------- |
output [3:0] rgmii_txd, |
output rgmii_tx_ctl, |
output rgmii_txc, |
input [3:0] rgmii_rxd, |
input rgmii_rx_ctl, |
input rgmii_rxc, |
output inband_link_status, |
output [1:0] inband_clock_speed, |
output inband_duplex_status, |
|
|
// MDIO Interface |
//--------------- |
inout mdio, |
output mdc, |
|
// AXI-Lite Interface |
//--------------- |
input s_axi_aclk, |
input s_axi_resetn, |
|
input [11:0] s_axi_awaddr, |
input s_axi_awvalid, |
output s_axi_awready, |
|
input [31:0] s_axi_wdata, |
input s_axi_wvalid, |
output s_axi_wready, |
|
output [1:0] s_axi_bresp, |
output s_axi_bvalid, |
input s_axi_bready, |
|
input [11:0] s_axi_araddr, |
input s_axi_arvalid, |
output s_axi_arready, |
|
output [31:0] s_axi_rdata, |
output [1:0] s_axi_rresp, |
output s_axi_rvalid, |
input s_axi_rready, |
|
output mac_irq |
|
); |
|
//---------------------------------------------------------------------------- |
// Shareable logic |
//---------------------------------------------------------------------------- |
wire mmcm_out_gtx_clk; |
wire mmcm_out_gtx_clk90; |
|
assign gtx_clk_out = mmcm_out_gtx_clk; |
assign gtx_clk90_out = mmcm_out_gtx_clk90; |
|
// Instantiate the sharable clocking logic |
tri_mode_ethernet_mac_0_support_clocking tri_mode_ethernet_mac_support_clocking_i |
( |
.clk_in1 (gtx_clk), |
.clk_out1 (mmcm_out_gtx_clk), |
.clk_out2 (mmcm_out_gtx_clk90), |
.reset (gtx_mmcm_rst), |
.locked (gtx_mmcm_locked) |
); |
|
// Instantiate the sharable reset logic |
tri_mode_ethernet_mac_0_support_resets tri_mode_ethernet_mac_support_resets_i ( |
.glbl_rstn (glbl_rstn), |
.refclk (refclk), |
|
.idelayctrl_ready (idelayctrl_ready), |
|
.idelayctrl_reset_out (idelayctrl_reset), |
.gtx_clk (gtx_clk), |
.gtx_dcm_locked (gtx_mmcm_locked), |
.gtx_mmcm_rst_out (gtx_mmcm_rst) |
); |
|
// An IDELAYCTRL primitive needs to be instantiated for the Fixed Tap Delay |
// mode of the IDELAY. |
IDELAYCTRL #( |
.SIM_DEVICE ("7SERIES") |
) |
tri_mode_ethernet_mac_idelayctrl_common_i ( |
.RDY (idelayctrl_ready), |
.REFCLK (refclk), |
.RST (idelayctrl_reset) |
); |
|
|
//--------------------------------------------------------------------------- |
// Instantiate the TEMAC core |
//--------------------------------------------------------------------------- |
tri_mode_ethernet_mac_0 tri_mode_ethernet_mac_i ( |
.gtx_clk (mmcm_out_gtx_clk), |
.gtx_clk90 (mmcm_out_gtx_clk90), |
// asynchronous reset |
.glbl_rstn (glbl_rstn), |
.rx_axi_rstn (rx_axi_rstn), |
.tx_axi_rstn (tx_axi_rstn), |
|
// Receiver Interface |
//-------------------------- |
.rx_enable (rx_enable), |
|
.rx_statistics_vector (rx_statistics_vector), |
.rx_statistics_valid (rx_statistics_valid), |
|
.rx_mac_aclk (rx_mac_aclk), |
.rx_reset (rx_reset), |
.rx_axis_mac_tdata (rx_axis_mac_tdata), |
.rx_axis_mac_tvalid (rx_axis_mac_tvalid), |
.rx_axis_mac_tlast (rx_axis_mac_tlast), |
.rx_axis_mac_tuser (rx_axis_mac_tuser), |
// Transmitter Interface |
//----------------------------- |
.tx_enable (tx_enable), |
|
.tx_ifg_delay (tx_ifg_delay), |
.tx_statistics_vector (tx_statistics_vector), |
.tx_statistics_valid (tx_statistics_valid), |
|
.tx_mac_aclk (tx_mac_aclk), |
.tx_reset (tx_reset), |
.tx_axis_mac_tdata (tx_axis_mac_tdata), |
.tx_axis_mac_tvalid (tx_axis_mac_tvalid), |
.tx_axis_mac_tlast (tx_axis_mac_tlast), |
.tx_axis_mac_tuser (tx_axis_mac_tuser), |
.tx_axis_mac_tready (tx_axis_mac_tready), |
|
// MAC Control Interface |
//---------------------- |
.pause_req (pause_req), |
.pause_val (pause_val), |
|
.speedis100 (speedis100), |
.speedis10100 (speedis10100), |
// RGMII Interface |
//---------------- |
.rgmii_txd (rgmii_txd), |
.rgmii_tx_ctl (rgmii_tx_ctl), |
.rgmii_txc (rgmii_txc), |
.rgmii_rxd (rgmii_rxd), |
.rgmii_rx_ctl (rgmii_rx_ctl), |
.rgmii_rxc (rgmii_rxc), |
.inband_link_status (inband_link_status), |
.inband_clock_speed (inband_clock_speed), |
.inband_duplex_status (inband_duplex_status), |
|
|
// MDIO Interface |
//--------------- |
.mdio (mdio), |
.mdc (mdc), |
|
// AXI-Lite Interface |
//--------------- |
.s_axi_aclk (s_axi_aclk), |
.s_axi_resetn (s_axi_resetn), |
|
.s_axi_awaddr (s_axi_awaddr), |
.s_axi_awvalid (s_axi_awvalid), |
.s_axi_awready (s_axi_awready), |
|
.s_axi_wdata (s_axi_wdata), |
.s_axi_wvalid (s_axi_wvalid), |
.s_axi_wready (s_axi_wready), |
|
.s_axi_bresp (s_axi_bresp), |
.s_axi_bvalid (s_axi_bvalid), |
.s_axi_bready (s_axi_bready), |
|
.s_axi_araddr (s_axi_araddr), |
.s_axi_arvalid (s_axi_arvalid), |
.s_axi_arready (s_axi_arready), |
|
.s_axi_rdata (s_axi_rdata), |
.s_axi_rresp (s_axi_rresp), |
.s_axi_rvalid (s_axi_rvalid), |
.s_axi_rready (s_axi_rready), |
|
.mac_irq (mac_irq) |
|
); |
|
|
endmodule |
|
|
/trunk/hw/src/rtl/tri_mode_emac/src/support/tri_mode_ethernet_mac_0_support_clocking.v
0,0 → 1,172
//---------------------------------------------------------------------------- |
// File : tri_mode_ethernet_mac_0_support_clocking.v |
// Author : Xilinx Inc. |
// ----------------------------------------------------------------------------- |
// (c) Copyright 2013 Xilinx, Inc. All rights reserved. |
// |
// This file contains confidential and proprietary information |
// of Xilinx, Inc. and is protected under U.S. and |
// international copyright and other intellectual property |
// laws. |
// |
// DISCLAIMER |
// This disclaimer is not a license and does not grant any |
// rights to the materials distributed herewith. Except as |
// otherwise provided in a valid license issued to you by |
// Xilinx, and to the maximum extent permitted by applicable |
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND |
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES |
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING |
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- |
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and |
// (2) Xilinx shall not be liable (whether in contract or tort, |
// including negligence, or under any other theory of |
// liability) for any loss or damage of any kind or nature |
// related to, arising under or in connection with these |
// materials, including for any direct, or any indirect, |
// special, incidental, or consequential loss or damage |
// (including loss of data, profits, goodwill, or any type of |
// loss or damage suffered as a result of any action brought |
// by a third party) even if such damage or loss was |
// reasonably foreseeable or Xilinx had been advised of the |
// possibility of the same. |
// |
// CRITICAL APPLICATIONS |
// Xilinx products are not designed or intended to be fail- |
// safe, or for use in any application requiring fail-safe |
// performance, such as life-support or safety devices or |
// systems, Class III medical devices, nuclear facilities, |
// applications related to the deployment of airbags, or any |
// other applications that could lead to death, personal |
// injury, or severe property or environmental damage |
// (individually and collectively, "Critical |
// Applications"). Customer assumes the sole risk and |
// liability of any use of Xilinx products in Critical |
// Applications, subject only to applicable laws and |
// regulations governing limitations on product liability. |
// |
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS |
// PART OF THIS FILE AT ALL TIMES. |
// ----------------------------------------------------------------------------- |
// |
//---------------------------------------------------------------------------- |
// Output Output Phase Duty Cycle Pk-to-Pk Phase |
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) |
//---------------------------------------------------------------------------- |
// clk_out1 125.000 0.000 50.0 91.364 85.928 |
// clk_out2 125.000 90.000 50.0 70.716 85.928 |
// |
//---------------------------------------------------------------------------- |
// Input Clock Input Freq (MHz) Input Jitter (UI) |
//---------------------------------------------------------------------------- |
// primary 125.000 0.010 |
|
`timescale 1ns / 1ps |
|
//***************************** Entity Declaration **************************** |
module tri_mode_ethernet_mac_0_support_clocking ( |
// Clock in ports |
input clk_in1, |
// Clock out ports |
output clk_out1, |
output clk_out2, |
// Status and control signals |
input reset, |
output locked |
); |
|
// Clocking primitive |
//------------------------------------ |
// Instantiation of the MMCM primitive |
// * Unused inputs are tied off |
// * Unused outputs are labeled unused |
wire [15:0] do_unused; |
wire drdy_unused; |
wire psdone_unused; |
wire clkfbout; |
wire clkfboutb_unused; |
wire clkout0b_unused; |
wire clkout1b_unused; |
wire clkout2b_unused; |
wire clkout3_unused; |
wire clkout3b_unused; |
wire clkout4_unused; |
wire clkout5_unused; |
wire clkout6_unused; |
wire clkfbstopped_unused; |
wire clkinstopped_unused; |
|
MMCME2_ADV |
|
#(.BANDWIDTH ("OPTIMIZED"), |
.COMPENSATION ("ZHOLD"), |
.DIVCLK_DIVIDE (1), |
.CLKFBOUT_MULT_F (5.000), |
.CLKFBOUT_PHASE (0.000), |
.CLKOUT0_DIVIDE_F (5.000), |
.CLKOUT0_PHASE (0.000), |
.CLKOUT0_DUTY_CYCLE (0.500), |
.CLKOUT1_DIVIDE (5), |
.CLKOUT1_PHASE (90.000), |
.CLKOUT1_DUTY_CYCLE (0.500), |
.CLKOUT2_DIVIDE (5), |
.CLKOUT2_PHASE (0.000), |
.CLKOUT2_DUTY_CYCLE (0.500), |
.CLKIN1_PERIOD (8.000), |
.REF_JITTER1 (0.010)) |
mmcm_adv_inst |
// Output clocks |
(.CLKFBOUT (clkfbout), |
.CLKFBOUTB (clkfboutb_unused), |
.CLKOUT0 (clkout0), |
.CLKOUT0B (clkout0b_unused), |
.CLKOUT1 (clkout1), |
.CLKOUT1B (clkout1b_unused), |
.CLKOUT2 (clkout2), |
.CLKOUT2B (clkout2b_unused), |
.CLKOUT3 (clkout3_unused), |
.CLKOUT3B (clkout3b_unused), |
.CLKOUT4 (clkout4_unused), |
.CLKOUT5 (clkout5_unused), |
.CLKOUT6 (clkout6_unused), |
// Input clock control |
.CLKFBIN (clkfbout), |
.CLKIN1 (clk_in1), |
.CLKIN2 (1'b0), |
// Tied to always select the primary input clock |
.CLKINSEL (1'b1), |
// Ports for dynamic reconfiguration |
.DADDR (7'h0), |
.DCLK (1'b0), |
.DEN (1'b0), |
.DI (16'h0), |
.DO (do_unused), |
.DRDY (drdy_unused), |
.DWE (1'b0), |
// Ports for dynamic phase shift |
.PSCLK (1'b0), |
.PSEN (1'b0), |
.PSINCDEC (1'b0), |
.PSDONE (psdone_unused), |
|
// Other control and status signals |
.LOCKED (locked), |
.CLKINSTOPPED (clkinstopped_unused), |
.CLKFBSTOPPED (clkfbstopped_unused), |
.PWRDWN (1'b0), |
.RST (reset)); |
|
// Output buffering |
//----------------------------------- |
|
BUFGCE clkout1_buf |
(.O (clk_out1), |
.CE (1'b1), |
.I (clkout0)); |
|
BUFGCE clkout2_buf |
(.O (clk_out2), |
.CE (1'b1), |
.I (clkout1)); |
|
endmodule |
/trunk/hw/src/rtl/tri_mode_emac/src/support/tri_mode_ethernet_mac_0_support_resets.v
0,0 → 1,169
//--------------------------------------------------------------------------- |
// File : tri_mode_ethernet_mac_0_support_resets.v |
// Author : Xilinx Inc. |
// ----------------------------------------------------------------------------- |
// (c) Copyright 2013 Xilinx, Inc. All rights reserved. |
// |
// This file contains confidential and proprietary information |
// of Xilinx, Inc. and is protected under U.S. and |
// international copyright and other intellectual property |
// laws. |
// |
// DISCLAIMER |
// This disclaimer is not a license and does not grant any |
// rights to the materials distributed herewith. Except as |
// otherwise provided in a valid license issued to you by |
// Xilinx, and to the maximum extent permitted by applicable |
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND |
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES |
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING |
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- |
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and |
// (2) Xilinx shall not be liable (whether in contract or tort, |
// including negligence, or under any other theory of |
// liability) for any loss or damage of any kind or nature |
// related to, arising under or in connection with these |
// materials, including for any direct, or any indirect, |
// special, incidental, or consequential loss or damage |
// (including loss of data, profits, goodwill, or any type of |
// loss or damage suffered as a result of any action brought |
// by a third party) even if such damage or loss was |
// reasonably foreseeable or Xilinx had been advised of the |
// possibility of the same. |
// |
// CRITICAL APPLICATIONS |
// Xilinx products are not designed or intended to be fail- |
// safe, or for use in any application requiring fail-safe |
// performance, such as life-support or safety devices or |
// systems, Class III medical devices, nuclear facilities, |
// applications related to the deployment of airbags, or any |
// other applications that could lead to death, personal |
// injury, or severe property or environmental damage |
// (individually and collectively, "Critical |
// Applications"). Customer assumes the sole risk and |
// liability of any use of Xilinx products in Critical |
// Applications, subject only to applicable laws and |
// regulations governing limitations on product liability. |
// |
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS |
// PART OF THIS FILE AT ALL TIMES. |
// ----------------------------------------------------------------------------- |
// Description: This module holds the shared resets for the IDELAYCTRL |
// and the MMCM |
//------------------------------------------------------------------------------ |
|
`timescale 1ns / 1ps |
|
module tri_mode_ethernet_mac_0_support_resets |
( |
input glbl_rstn, |
input refclk, |
input idelayctrl_ready, |
output idelayctrl_reset_out, |
input gtx_clk, |
input gtx_dcm_locked, |
output gtx_mmcm_rst_out // The reset pulse for the MMCM. |
); |
|
wire glbl_rst; |
|
wire idelayctrl_reset_in; // Used to trigger reset_sync generation in refclk domain. |
wire idelayctrl_reset_sync; // Used to create a reset pulse in the IDELAYCTRL refclk domain. |
reg [3:0] idelay_reset_cnt; // Counter to create a long IDELAYCTRL reset pulse. |
reg idelayctrl_reset; |
|
wire gtx_mmcm_rst_in; |
wire gtx_dcm_locked_int; |
wire gtx_dcm_locked_sync; |
reg gtx_dcm_locked_reg = 1; |
reg gtx_dcm_locked_edge = 1; |
|
|
assign glbl_rst = !glbl_rstn; |
|
//---------------------------------------------------------------------------- |
// Reset circuitry associated with the IDELAYCTRL |
//---------------------------------------------------------------------------- |
|
assign idelayctrl_reset_out = idelayctrl_reset; |
assign idelayctrl_reset_in = glbl_rst || !idelayctrl_ready; |
|
// Create a synchronous reset in the IDELAYCTRL refclk clock domain. |
tri_mode_ethernet_mac_0_reset_sync idelayctrl_reset_gen ( |
.clk (refclk), |
.enable (1'b1), |
.reset_in (idelayctrl_reset_in), |
.reset_out (idelayctrl_reset_sync) |
); |
|
// Reset circuitry for the IDELAYCTRL reset. |
|
// The IDELAYCTRL must experience a pulse which is at least 50 ns in |
// duration. This is ten clock cycles of the 200MHz refclk. Here we |
// drive the reset pulse for 12 clock cycles. |
always @(posedge refclk) |
begin |
if (idelayctrl_reset_sync) begin |
idelay_reset_cnt <= 4'b0000; |
idelayctrl_reset <= 1'b1; |
end |
else begin |
case (idelay_reset_cnt) |
4'b0000 : idelay_reset_cnt <= 4'b0001; |
4'b0001 : idelay_reset_cnt <= 4'b0010; |
4'b0010 : idelay_reset_cnt <= 4'b0011; |
4'b0011 : idelay_reset_cnt <= 4'b0100; |
4'b0100 : idelay_reset_cnt <= 4'b0101; |
4'b0101 : idelay_reset_cnt <= 4'b0110; |
4'b0110 : idelay_reset_cnt <= 4'b0111; |
4'b0111 : idelay_reset_cnt <= 4'b1000; |
4'b1000 : idelay_reset_cnt <= 4'b1001; |
4'b1001 : idelay_reset_cnt <= 4'b1010; |
4'b1010 : idelay_reset_cnt <= 4'b1011; |
4'b1011 : idelay_reset_cnt <= 4'b1100; |
default : idelay_reset_cnt <= 4'b1100; |
endcase |
if (idelay_reset_cnt == 4'b1100) begin |
idelayctrl_reset <= 1'b0; |
end |
else begin |
idelayctrl_reset <= 1'b1; |
end |
end |
end |
|
|
//---------------------------------------------------------------------------- |
// Reset circuitry associated with the MMCM |
//---------------------------------------------------------------------------- |
|
assign gtx_mmcm_rst_in = glbl_rst | gtx_dcm_locked_edge; |
|
// Synchronise the async dcm_locked into the gtx_clk clock domain |
tri_mode_ethernet_mac_0_sync_block lock_sync ( |
.clk (gtx_clk), |
.data_in (gtx_dcm_locked), |
.data_out (gtx_dcm_locked_sync) |
); |
|
// for the falling edge detect we want to force this at power on so init the flop to 1 |
always @(posedge gtx_clk) |
begin |
gtx_dcm_locked_reg <= gtx_dcm_locked_sync; |
gtx_dcm_locked_edge <= gtx_dcm_locked_reg & !gtx_dcm_locked_sync; |
end |
|
// the MMCM reset should be at least 5ns - that is one cycle of the input clock - |
// since the source of the input reset is unknown (a push switch in board design) |
// this needs to be debounced |
tri_mode_ethernet_mac_0_reset_sync gtx_mmcm_reset_gen ( |
.clk (gtx_clk), |
.enable (1'b1), |
.reset_in (gtx_mmcm_rst_in), |
.reset_out (gtx_mmcm_rst_out) |
); |
|
|
endmodule |
|
|
/trunk/hw/src/rtl/tri_mode_emac/src/tri_mode_ethernet_mac_0_fifo_block.v
0,0 → 1,389
//------------------------------------------------------------------------------ |
// File : tri_mode_ethernet_mac_0_fifo_block.v |
// Author : Xilinx Inc. |
// ----------------------------------------------------------------------------- |
// (c) Copyright 2004-2013 Xilinx, Inc. All rights reserved. |
// |
// This file contains confidential and proprietary information |
// of Xilinx, Inc. and is protected under U.S. and |
// international copyright and other intellectual property |
// laws. |
// |
// DISCLAIMER |
// This disclaimer is not a license and does not grant any |
// rights to the materials distributed herewith. Except as |
// otherwise provided in a valid license issued to you by |
// Xilinx, and to the maximum extent permitted by applicable |
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND |
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES |
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING |
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- |
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and |
// (2) Xilinx shall not be liable (whether in contract or tort, |
// including negligence, or under any other theory of |
// liability) for any loss or damage of any kind or nature |
// related to, arising under or in connection with these |
// materials, including for any direct, or any indirect, |
// special, incidental, or consequential loss or damage |
// (including loss of data, profits, goodwill, or any type of |
// loss or damage suffered as a result of any action brought |
// by a third party) even if such damage or loss was |
// reasonably foreseeable or Xilinx had been advised of the |
// possibility of the same. |
// |
// CRITICAL APPLICATIONS |
// Xilinx products are not designed or intended to be fail- |
// safe, or for use in any application requiring fail-safe |
// performance, such as life-support or safety devices or |
// systems, Class III medical devices, nuclear facilities, |
// applications related to the deployment of airbags, or any |
// other applications that could lead to death, personal |
// injury, or severe property or environmental damage |
// (individually and collectively, "Critical |
// Applications"). Customer assumes the sole risk and |
// liability of any use of Xilinx products in Critical |
// Applications, subject only to applicable laws and |
// regulations governing limitations on product liability. |
// |
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS |
// PART OF THIS FILE AT ALL TIMES. |
// ----------------------------------------------------------------------------- |
// Description: This is the FIFO Block level vhdl wrapper for the Tri-Mode |
// Ethernet MAC core. This wrapper enhances the standard MAC core |
// with an example FIFO. The interface to this FIFO is |
// designed to the AXI-S specification. |
// Please refer to core documentation for |
// additional FIFO and AXI-S information. |
// |
// _________________________________________________________ |
// | | |
// | FIFO BLOCK LEVEL WRAPPER | |
// | | |
// | _____________________ ______________________ | |
// | | _________________ | | | | |
// | | | | | | | | |
// -------->| | TX AXI FIFO | |---->| Tx Tx |---------> |
// | | | | | | AXI-S PHY | | |
// | | |_________________| | | I/F I/F | | |
// | | | | | | |
// AXI | | 10/100/1G | | TRI-MODE ETHERNET | | |
// Stream | | ETHERNET FIFO | | MAC | | PHY I/F |
// | | | | SUPPORT LEVEL | | |
// | | _________________ | | | | |
// | | | | | | | | |
// <--------| | RX AXI FIFO | |<----| Rx Rx |<--------- |
// | | | | | | AXI-S PHY | | |
// | | |_________________| | | I/F I/F | | |
// | |_____________________| |______________________| | |
// | | |
// |_________________________________________________________| |
|
`timescale 1 ps/1 ps |
|
|
//------------------------------------------------------------------------------ |
// The module declaration for the FIFO Block level wrapper. |
//------------------------------------------------------------------------------ |
|
(* DowngradeIPIdentifiedWarnings = "yes" *) |
module tri_mode_ethernet_mac_0_fifo_block ( |
input gtx_clk, |
// asynchronous reset |
input glbl_rstn, |
input rx_axi_rstn, |
input tx_axi_rstn, |
|
// Reference clock for IDELAYCTRL's |
input refclk, |
/* |
// Receiver Statistics Interface |
//--------------------------------------- |
output rx_mac_aclk, |
output rx_reset, |
output [27:0] rx_statistics_vector, |
output rx_statistics_valid, |
*/ |
// Receiver (AXI-S) Interface |
//---------------------------------------- |
input rx_fifo_clock, |
input rx_fifo_resetn, |
|
output [7:0] rx_axis_fifo_tdata, |
|
output rx_axis_fifo_tvalid, |
input rx_axis_fifo_tready, |
output rx_axis_fifo_tlast, |
/* |
// Transmitter Statistics Interface |
//------------------------------------------ |
output tx_mac_aclk, |
output tx_reset, |
input [7:0] tx_ifg_delay, |
output [31:0] tx_statistics_vector, |
output tx_statistics_valid, |
*/ |
|
// Transmitter (AXI-S) Interface |
//------------------------------------------- |
input tx_fifo_clock, |
input tx_fifo_resetn, |
|
input [7:0] tx_axis_fifo_tdata, |
|
input tx_axis_fifo_tvalid, |
output tx_axis_fifo_tready, |
input tx_axis_fifo_tlast, |
/* |
// MAC Control Interface |
//------------------------ |
input pause_req, |
input [15:0] pause_val, |
*/ |
// RGMII Interface |
//------------------ |
output [3:0] rgmii_txd, |
output rgmii_tx_ctl, |
output rgmii_txc, |
input [3:0] rgmii_rxd, |
input rgmii_rx_ctl, |
input rgmii_rxc, |
|
// RGMII Inband Status Registers |
//-------------------------------- |
output inband_link_status, |
output [1:0] inband_clock_speed, |
output inband_duplex_status, |
|
|
// MDIO Interface |
//--------------- |
inout mdio, |
output mdc, |
|
// AXI-Lite Interface |
//--------------- |
input s_axi_aclk, |
input s_axi_resetn, |
|
input [11:0] s_axi_awaddr, |
input s_axi_awvalid, |
output s_axi_awready, |
|
input [31:0] s_axi_wdata, |
input s_axi_wvalid, |
output s_axi_wready, |
|
output [1:0] s_axi_bresp, |
output s_axi_bvalid, |
input s_axi_bready, |
|
input [11:0] s_axi_araddr, |
input s_axi_arvalid, |
output s_axi_arready, |
|
output [31:0] s_axi_rdata, |
output [1:0] s_axi_rresp, |
output s_axi_rvalid, |
input s_axi_rready |
|
); |
|
|
//---------------------------------------------------------------------------- |
// Internal signals used in this fifo block level wrapper. |
//---------------------------------------------------------------------------- |
|
wire rx_mac_aclk_int; // MAC Rx clock |
wire tx_mac_aclk_int; // MAC Tx clock |
wire rx_reset_int; // MAC Rx reset |
wire tx_reset_int; // MAC Tx reset |
|
// MAC receiver client I/F |
wire [7:0] rx_axis_mac_tdata; |
wire rx_axis_mac_tvalid; |
wire rx_axis_mac_tlast; |
wire rx_axis_mac_tuser; |
|
// MAC transmitter client I/F |
wire [7:0] tx_axis_mac_tdata; |
wire tx_axis_mac_tvalid; |
wire tx_axis_mac_tready; |
wire tx_axis_mac_tlast; |
wire tx_axis_mac_tuser; |
|
//---------------------------------------------------------------------------- |
// Connect the output clock signals |
//---------------------------------------------------------------------------- |
|
assign rx_mac_aclk = rx_mac_aclk_int; |
assign tx_mac_aclk = tx_mac_aclk_int; |
assign rx_reset = rx_reset_int; |
assign tx_reset = tx_reset_int; |
|
//---------------------------------------------------------------------------- |
// Instantiate the Tri-Mode Ethernet MAC Support Level wrapper |
//---------------------------------------------------------------------------- |
tri_mode_ethernet_mac_0_support trimac_sup_block ( |
.gtx_clk (gtx_clk), |
|
.gtx_clk_out (), |
.gtx_clk90_out (), |
// asynchronous reset |
.glbl_rstn (glbl_rstn), |
.rx_axi_rstn (rx_axi_rstn), |
.tx_axi_rstn (tx_axi_rstn), |
|
// Receiver Interface |
.rx_enable (), |
|
.rx_statistics_vector (rx_statistics_vector), |
.rx_statistics_valid (rx_statistics_valid), |
|
.rx_mac_aclk (rx_mac_aclk_int), |
.rx_reset (rx_reset_int), |
.rx_axis_mac_tdata (rx_axis_mac_tdata), |
.rx_axis_mac_tvalid (rx_axis_mac_tvalid), |
.rx_axis_mac_tlast (rx_axis_mac_tlast), |
.rx_axis_mac_tuser (rx_axis_mac_tuser), |
|
// Transmitter Interface |
.tx_enable (), |
|
.tx_ifg_delay (tx_ifg_delay), |
.tx_statistics_vector (tx_statistics_vector), |
.tx_statistics_valid (tx_statistics_valid), |
|
.tx_mac_aclk (tx_mac_aclk_int), |
.tx_reset (tx_reset_int), |
.tx_axis_mac_tdata (tx_axis_mac_tdata ), |
.tx_axis_mac_tvalid (tx_axis_mac_tvalid), |
.tx_axis_mac_tlast (tx_axis_mac_tlast), |
.tx_axis_mac_tuser (tx_axis_mac_tuser ), |
.tx_axis_mac_tready (tx_axis_mac_tready), |
|
// Flow Control |
.pause_req (pause_req), |
.pause_val (pause_val), |
|
// Reference clock for IDELAYCTRL's |
.refclk (refclk), |
|
// Speed Control |
.speedis100 (), |
.speedis10100 (), |
|
// RGMII Interface |
.rgmii_txd (rgmii_txd), |
.rgmii_tx_ctl (rgmii_tx_ctl), |
.rgmii_txc (rgmii_txc), |
.rgmii_rxd (rgmii_rxd), |
.rgmii_rx_ctl (rgmii_rx_ctl), |
.rgmii_rxc (rgmii_rxc), |
.inband_link_status (inband_link_status), |
.inband_clock_speed (inband_clock_speed), |
.inband_duplex_status (inband_duplex_status), |
|
|
// MDIO Interface |
//--------------- |
.mdio (mdio), |
.mdc (mdc), |
|
// AXI lite interface |
.s_axi_aclk (s_axi_aclk), |
.s_axi_resetn (s_axi_resetn), |
.s_axi_awaddr (s_axi_awaddr), |
.s_axi_awvalid (s_axi_awvalid), |
.s_axi_awready (s_axi_awready), |
.s_axi_wdata (s_axi_wdata), |
.s_axi_wvalid (s_axi_wvalid), |
.s_axi_wready (s_axi_wready), |
.s_axi_bresp (s_axi_bresp), |
.s_axi_bvalid (s_axi_bvalid), |
.s_axi_bready (s_axi_bready), |
.s_axi_araddr (s_axi_araddr), |
.s_axi_arvalid (s_axi_arvalid), |
.s_axi_arready (s_axi_arready), |
.s_axi_rdata (s_axi_rdata), |
.s_axi_rresp (s_axi_rresp), |
.s_axi_rvalid (s_axi_rvalid), |
.s_axi_rready (s_axi_rready), |
.mac_irq () |
); |
|
|
//---------------------------------------------------------------------------- |
// Instantiate the user side FIFO |
//---------------------------------------------------------------------------- |
|
// locally reset sync the mac generated resets - the resets are already fully sync |
// so adding a reset sync shouldn't change that |
tri_mode_ethernet_mac_0_reset_sync rx_mac_reset_gen ( |
.clk (rx_mac_aclk_int), |
.enable (1'b1), |
.reset_in (rx_reset_int), |
.reset_out (rx_mac_reset) |
); |
|
tri_mode_ethernet_mac_0_reset_sync tx_mac_reset_gen ( |
.clk (tx_mac_aclk_int), |
.enable (1'b1), |
.reset_in (tx_reset_int), |
.reset_out (tx_mac_reset) |
); |
|
// create inverted mac resets as the FIFO expects AXI compliant resets |
assign tx_mac_resetn = !tx_mac_reset; |
assign rx_mac_resetn = !rx_mac_reset; |
|
|
|
tri_mode_ethernet_mac_0_ten_100_1g_eth_fifo # |
( |
.FULL_DUPLEX_ONLY (1) |
) |
|
user_side_FIFO |
( |
// Transmit FIFO MAC TX Interface |
.tx_fifo_aclk (tx_fifo_clock), |
.tx_fifo_resetn (tx_fifo_resetn), |
.tx_axis_fifo_tdata (tx_axis_fifo_tdata), |
.tx_axis_fifo_tvalid (tx_axis_fifo_tvalid), |
.tx_axis_fifo_tlast (tx_axis_fifo_tlast), |
.tx_axis_fifo_tready (tx_axis_fifo_tready), |
|
|
.tx_mac_aclk (tx_mac_aclk_int), |
.tx_mac_resetn (tx_mac_resetn), |
.tx_axis_mac_tdata (tx_axis_mac_tdata), |
.tx_axis_mac_tvalid (tx_axis_mac_tvalid), |
.tx_axis_mac_tlast (tx_axis_mac_tlast), |
.tx_axis_mac_tready (tx_axis_mac_tready), |
.tx_axis_mac_tuser (tx_axis_mac_tuser), |
|
.tx_fifo_overflow (), |
.tx_fifo_status (), |
.tx_collision (1'b0), |
.tx_retransmit (1'b0), |
|
.rx_fifo_aclk (rx_fifo_clock), |
.rx_fifo_resetn (rx_fifo_resetn), |
.rx_axis_fifo_tdata (rx_axis_fifo_tdata), |
.rx_axis_fifo_tvalid (rx_axis_fifo_tvalid), |
.rx_axis_fifo_tlast (rx_axis_fifo_tlast), |
.rx_axis_fifo_tready (rx_axis_fifo_tready), |
.rx_mac_aclk (rx_mac_aclk_int), |
.rx_mac_resetn (rx_mac_resetn), |
.rx_axis_mac_tdata (rx_axis_mac_tdata), |
.rx_axis_mac_tvalid (rx_axis_mac_tvalid), |
.rx_axis_mac_tlast (rx_axis_mac_tlast), |
.rx_axis_mac_tuser (rx_axis_mac_tuser), |
|
.rx_fifo_status (), |
.rx_fifo_overflow () |
); |
|
|
endmodule |
|
/trunk/hw/src/rtl/tri_mode_emac/sw/data/tri_mode_emac.mdd
0,0 → 1,12
|
OPTION psf_version = 2.1; |
|
BEGIN driver tri_mode_emac |
|
OPTION supported_peripherals = (tri_mode_emac); |
OPTION driver_state = ACTIVE; |
OPTION copyfiles = all; |
OPTION VERSION = 1.0; |
OPTION NAME = tri_mode_emac; |
|
END driver |
/trunk/hw/src/rtl/tri_mode_emac/sw/data/tri_mode_emac.tcl
0,0 → 1,5
|
proc generate {drv_handle} { |
::hsi::utils::define_include_file $drv_handle "xparameters.h" "TMEMAC" "NUM_INSTANCES" "C_BASEADDR" "C_HIGHADDR" "DEVICE_ID" "C_INTERRUPT_PRESENT" |
::hsi::utils::define_canonical_xpars $drv_handle "xparameters.h" "TMEMAC" "C_BASEADDR" "C_HIGHADDR" "DEVICE_ID" "C_INTERRUPT_PRESENT" |
} |
/trunk/hw/src/rtl/tri_mode_emac/sw/src/Makefile
0,0 → 1,28
COMPILER= |
ARCHIVER= |
CP=cp |
COMPILER_FLAGS= |
EXTRA_COMPILER_FLAGS= |
LIB=libxil.a |
|
RELEASEDIR=../../../lib |
INCLUDEDIR=../../../include |
INCLUDES=-I./. -I${INCLUDEDIR} |
|
INCLUDEFILES=tri_mode_emac.h |
|
LIBSOURCES=*.c |
OUTS = *.o |
|
|
libs: |
echo "Compiling tri_mode_emac" |
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES) |
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} $(OUTS) |
make clean |
|
include: |
${CP} ${INCLUDEFILES} ${INCLUDEDIR} |
|
clean: |
rm -rf ${OUTS} |
/trunk/hw/src/rtl/tri_mode_emac/sw/src/tri_mode_emac.c
0,0 → 1,240
// base: tri_mode_ethernet_mac_0_axi_lite_sm |
|
#include <stdio.h> |
|
#include "xil_io.h" |
//#include "xstatus.h" |
|
#include "tri_mode_emac.h" |
|
#define TMEMAC_MDIO_TOUT (0x1FFFFFFF) |
#define TMEMAC_AN_TOUT (0x1FFFFFFF) |
|
// KC705 Evaluation Board Features: |
// ..On power-up, or on reset, the PHY is configured to operate in GMII mode with PHY address |
// 0b00111 using the settings shown in Table 1-17. These settings can be overwritten via |
// software commands passed over the MDIO interface. |
// {Table 1-17: Board Connections for PHY Configuration Pins} |
// |
// 88E1111Datasheet_Rev_J.pdf: |
// 2.3.4 Mode Switching |
// reg: 0_4, 0_1.12, 0_27.12, |
// HWCFG_MODE[3:0] == 1011 |
|
|
|
// |
u32 u32_tmemac_base;// = XPAR_TMEMAC_0_BASEADDR; |
// |
int phy_addr; |
int phy_id1; |
int phy_id2; |
int phy_link_speed; |
int phy_duplex; |
/**/ |
int tri_mode_emac_phy_cfg(void); |
int tri_mode_emac_phy_det(void); |
int tmemac_phy_rd_reg(u8 reg_addr); |
int tmemac_phy_wr_reg(u8 reg_addr, u16 reg_data); |
/**/ |
|
int tri_mode_emac_init(tmemac_cfg_t *iv_tmemac_cfg) |
{ |
// dec vars |
int Value; |
|
// wr base |
u32_tmemac_base = iv_tmemac_cfg->base; |
|
// -> STARTUP |
Xil_Out32(u32_tmemac_base+CONFIG_MANAGEMENT_ADD, (1 << 6) | (24)); // MDIO Enable[6], Clock Divide[5:0] |
// -> UPDATE_SPEED |
Value = Xil_In32(u32_tmemac_base+SPEED_CONFIG_ADD); |
if (Value == 0) { |
Xil_Out32(+SPEED_CONFIG_ADD, (2 << 30)); // 2'b10 == 1Gbps, |
} |
//xil_printf("ms=%x\n", Xil_In32(u32_tmemac_base+SPEED_CONFIG_ADD)); |
// PHY cfg |
Value = tri_mode_emac_phy_cfg(); |
if (Value < 0) { |
return Value; |
} |
|
// Reseting MAC RX |
Xil_Out32(u32_tmemac_base+RECEIVER_ADD, (1 << 31) | (1 << 28)); // Reset, Receiver Enable |
// Reseting MAC TX |
Xil_Out32(u32_tmemac_base+TRANSMITTER_ADD, (1 << 31) | (1 << 28)); // Reset, Transmit Enable |
// Disabling Flow control |
Xil_Out32(u32_tmemac_base+CONFIG_FLOW_CTRL_ADD, 0); |
// Configuring unicast address |
Xil_Out32(u32_tmemac_base+CONFIG_UNI1_CTRL_ADD, iv_tmemac_cfg->mac_high); // high word |
Xil_Out32(u32_tmemac_base+CONFIG_UNI0_CTRL_ADD, iv_tmemac_cfg->mac_low); // low .. |
// Setting core to promiscuous mode |
Xil_Out32(u32_tmemac_base+CONFIG_ADDR_CTRL_ADD, (1 << 31)); |
|
// Final |
return 0; |
} |
|
int tri_mode_emac_phy_cfg(void) |
{ |
#ifndef MSIM |
// dec vars |
int Value; |
u32 x; |
|
// PHY det |
if (tri_mode_emac_phy_det()) { |
return -1; |
} |
// further phy-cfg: |
// TSE_PHY_MDIO_1000BASE_T_CTRL |
if (tmemac_phy_wr_reg(TSE_PHY_MDIO_1000BASE_T_CTRL, 1 << 9)) { // 1G Full-Duplex |
return -2; |
} |
// TSE_PHY_MDIO_ADV |
if (tmemac_phy_wr_reg(TSE_PHY_MDIO_ADV, (1 << 8) | (1 << 6))) { // 100M Full-Duplex, 10M Full-Duplex |
return -3; |
} |
// HWCFG_MODE[3:0] == RGMII |
Value = tmemac_phy_rd_reg(MRVL_PHY_MDIO_ESPEC_STS); |
Value &= ~(0x0F); |
Value |= MARVELL_PHY_RGMII; // [3:0] == 1011 |
if (tmemac_phy_wr_reg(MRVL_PHY_MDIO_ESPEC_STS, Value)) { |
return -4; |
} |
// add/remove the clock delay |
Value = tmemac_phy_rd_reg(MRVL_PHY_MDIO_ESPEC_CTRL); |
Value &= ~((1 << 7) | (1 << 1)); |
Value |= (1 << 7) | (0 << 1); // tri_mode_ethernet_mac_0_axi_lite_sm.v, MDIO_DELAY_RD_POLL |
if (tmemac_phy_wr_reg(MRVL_PHY_MDIO_ESPEC_CTRL, Value)) { |
return -5; |
} |
// set autoneg and reset |
Value = (1 << 15) | (1 << 12); // bit15: software reset, bit12 : AN enable (set after power up) |
if (tmemac_phy_wr_reg(TSE_PHY_MDIO_CONTROL, Value)) { |
return -6; |
} |
// w8 4 rst-low |
x = 0; |
do { |
Value = tmemac_phy_rd_reg(TSE_PHY_MDIO_CONTROL); |
if (++x == TMEMAC_AN_TOUT) { |
return -7; |
} |
} while((Value & (1 << 15)) == 1); // .. When the reset operation is done, this bit is cleared to 0 automatically. |
//xil_printf(" [phy_rst ] reg 0_0 = 0x%04x\n\r", Value); |
// Wait for Autonegotiation to complete |
x = 0; |
do { |
// useful ibala |
{ |
volatile int wait; |
for (wait=0; wait < 100000; wait++); |
for (wait=0; wait < 100000; wait++); |
} |
// |
Value = tmemac_phy_rd_reg(TSE_PHY_MDIO_STATUS); |
if (Value == -1) { |
return -8; |
} |
// |
if (++x == TMEMAC_AN_TOUT) { |
xil_printf("ERR: Auto-Negotiation FAILED, STATUS: 0x%04x\n\r", tmemac_phy_rd_reg(TSE_PHY_MDIO_STATUS)); |
return -9; |
} |
} while((Value & (1 << 5)) == 0); |
xil_printf(" [phy_rst ] OK, reg 0_1 = 0x%04x\n\r", Value); |
// get PHY-{Speed+Duplex} |
Value = tmemac_phy_rd_reg(MRVL_PHY_MDIO_SPEC_STS_C); |
if (Value == -1) { |
return -10; |
} |
//xil_printf("reg 0_17 = 0x%04x\n", Value); |
phy_duplex = Value && (1 << 13); |
phy_link_speed = (Value && (1 << 15))? 1000 : |
(Value && (1 << 14))? 100 : |
10 ; |
xil_printf(" [phy_cfg ] Speed is 0x%x Full Duplex is %x\n\r", phy_link_speed, phy_duplex); |
#else |
phy_link_speed = 1000; |
phy_duplex = 1; |
printf(" [phy_init] MSIM: found Marvell 88E1111 PHY\n"); |
printf(" [phy_cfg ] MSIM: Speed is %d Full Duplex is %d\n", phy_link_speed, phy_duplex); |
#endif // MSIM |
// Final |
return 0; |
} |
|
int tri_mode_emac_phy_det(void) // phy detection |
{ |
for (phy_addr = 0; phy_addr < 32; phy_addr++) { |
// TSE_PHY_MDIO_PHY_ID1 |
phy_id1 = tmemac_phy_rd_reg(TSE_PHY_MDIO_PHY_ID1); |
if (phy_id1 == -1) { return -1; } |
// TSE_PHY_MDIO_PHY_ID2 |
phy_id2 = tmemac_phy_rd_reg(TSE_PHY_MDIO_PHY_ID2); |
if (phy_id2 == -1) { return -1; } |
// check |
if (phy_id1 != phy_id2) { |
//xil_printf(" [phy_init] phyID = 0x%02x 0x%04x 0x%04x\n", phy_addr, phy_id1, phy_id2); |
// |
if (MARVELL_PHY_ID_OK(phy_id1) & MARVELL_PHY_MODEL_OK(phy_id2)) { |
xil_printf(" [phy_init] found Marvell 88E1111 PHY\n\r"); |
return 0; |
} |
// |
break; |
} |
} |
return -1; |
} |
|
int tmemac_phy_rd_reg(u8 reg_addr) // phy reg-read |
{ |
u32 Value, j; |
// poll MDIO sts |
do { |
Value = Xil_In32(u32_tmemac_base+MDIO_CONTROL); |
if (++j == TMEMAC_MDIO_TOUT) { |
return -1; |
} |
} while((Value & (1 << 7)) == 0);// MDIO Control Word (0x504), [7] == MDIO ready: When set .. previous transaction has completed.. |
// post RD-req |
Value = (phy_addr << 24) | // TX_PHYAD |
(reg_addr << 16) | // TX_REGAD |
(MDIO_OP_RD << 14) | // TX_OP |
(1 << 11); // Initiate |
Xil_Out32(u32_tmemac_base+MDIO_CONTROL, Value); |
// poll RD-resp |
do { |
Value = Xil_In32(u32_tmemac_base+MDIO_RX_DATA); |
if (++j == TMEMAC_MDIO_TOUT) { |
return -1; |
} |
} while((Value & (1 << 16)) == 0); |
// Final |
return (Value & 0x0000FFFF); // [15:0] |
} |
|
int tmemac_phy_wr_reg(u8 reg_addr, u16 reg_data) // phy reg-write |
{ |
u32 Value, j; |
// poll MDIO sts |
do { |
Value = Xil_In32(u32_tmemac_base+MDIO_CONTROL); |
if (++j == TMEMAC_MDIO_TOUT) { |
return -1; |
} |
} while((Value & (1 << 7)) == 0);// MDIO Control Word (0x504), [7] == MDIO ready: When set .. previous transaction has completed.. |
// put WR-data |
Xil_Out32(u32_tmemac_base+MDIO_TX_DATA, reg_data); |
// post WR-req |
Value = (phy_addr << 24) | // TX_PHYAD |
(reg_addr << 16) | // TX_REGAD |
(MDIO_OP_WR << 14) | // TX_OP |
(1 << 11); // Initiate |
Xil_Out32(u32_tmemac_base+MDIO_CONTROL, Value); |
// Final |
return 0; |
} |
/trunk/hw/src/rtl/tri_mode_emac/sw/src/tri_mode_emac.h
0,0 → 1,93
|
#ifndef __TRI_MODE_MAC_H__ |
#define __TRI_MODE_MAC_H__ |
|
#ifdef __cplusplus |
extern "C" { |
#endif |
|
#include "xil_types.h" |
|
// |
#define MARVELL_PHY_ID (0x0141) |
#define MARVELL_PHY_MODEL (0x0CC0) // 88E1111: [9:4] == 00100 |
#define MARVELL_PHY_MODEL_MSK (0x0FF0) |
|
#define MARVELL_PHY_ID_OK(x) (x == MARVELL_PHY_ID) |
#define MARVELL_PHY_MODEL_OK(x) ((x & MARVELL_PHY_MODEL_MSK) == MARVELL_PHY_MODEL) |
// |
#define MARVELL_PHY_RGMII (0x0B) // 88E1111Datasheet_Rev_J.pdf: HWCFG_MODE[3:0] == 1011 / reg 0_27 |
|
|
// Management configuration register address (0x500) |
#define CONFIG_MANAGEMENT_ADD 0x0500 |
// Flow control configuration register address (0x40C) |
#define CONFIG_FLOW_CTRL_ADD 0x040C |
|
// Receiver configuration register address (0x404) |
#define RECEIVER_ADD 0x0404 |
|
// Transmitter configuration register address (0x408) |
#define TRANSMITTER_ADD 0x0408 |
|
// Speed configuration register address (0x410) |
#define SPEED_CONFIG_ADD 0x0410 |
|
// Unicast Word 0 configuration register address (0x700) |
#define CONFIG_UNI0_CTRL_ADD 0x0700 |
|
// Unicast Word 1 configuration register address (0x704) |
#define CONFIG_UNI1_CTRL_ADD 0x0704 |
|
// Address Filter configuration register address (0x708) |
#define CONFIG_ADDR_CTRL_ADD 0x0708 |
|
|
// MDIO registers |
#define MDIO_CONTROL 0x0504 |
#define MDIO_TX_DATA 0x0508 |
#define MDIO_RX_DATA 0x050C |
// MDIO IF op |
#define MDIO_OP_RD 2 |
#define MDIO_OP_WR 1 |
// |
|
//#define IORD_XLNX_TEMAC_MDIO(base, reg) |
//#define IOWR_XLNX_TEMAC_MDIO(base, reg) |
|
/* IEEE PHY register definition */ |
enum { |
TSE_PHY_MDIO_CONTROL = 0, |
TSE_PHY_MDIO_STATUS = 1, |
TSE_PHY_MDIO_PHY_ID1 = 2, |
TSE_PHY_MDIO_PHY_ID2 = 3, |
TSE_PHY_MDIO_ADV = 4, |
TSE_PHY_MDIO_REMADV = 5, |
|
TSE_PHY_MDIO_AN_EXT = 6, |
TSE_PHY_MDIO_1000BASE_T_CTRL = 9, |
TSE_PHY_MDIO_1000BASE_T_STATUS = 10, |
TSE_PHY_MDIO_EXT_STATUS = 15 |
}; |
#define MRVL_PHY_MDIO_SPEC_STS_C (17) // 88E1111Datasheet_Rev_J.pdf: Page 0, Register 17 |
#define MRVL_PHY_MDIO_ESPEC_CTRL (20) // 88E1111Datasheet_Rev_J.pdf: Page Any, Registe 20 |
#define MRVL_PHY_MDIO_ESPEC_STS (27) // 88E1111Datasheet_Rev_J.pdf: Page Any, Registe 27 |
|
typedef struct { |
// base-addr |
u32 base; |
// mac |
u32 mac_high; |
u32 mac_low; |
// ip-addr |
u32 ip_addr; |
} tmemac_cfg_t; |
|
|
int tri_mode_emac_init(tmemac_cfg_t *iv_tmemac_cfg); |
|
#ifdef __cplusplus |
} |
#endif |
|
#endif // __TRI_MODE_MAC_H__ |
/trunk/hw/src/rtl/tri_mode_emac/xci/tri_mode_ethernet_mac_0.xci
0,0 → 1,97
<?xml version="1.0" encoding="UTF-8"?> |
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> |
<spirit:vendor>xilinx.com</spirit:vendor> |
<spirit:library>xci</spirit:library> |
<spirit:name>unknown</spirit:name> |
<spirit:version>1.0</spirit:version> |
<spirit:componentInstances> |
<spirit:componentInstance> |
<spirit:instanceName>tri_mode_ethernet_mac_0</spirit:instanceName> |
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="tri_mode_ethernet_mac" spirit:version="9.0"/> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_1588">0</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_add_filter">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_addr_width">12</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_at_entries">0</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_avb">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_axilite_freq">150.00</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_cntr_rst">true</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_component_name">tri_mode_ethernet_mac_0</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_data_rate">1_Gbps</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_family">kintex7</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_half_duplex">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_has_host">true</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_has_mdio">true</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_has_stats">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_mac_speed">TRI_SPEED</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_mdio_external">true</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_num_stats">34</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_pfc">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_physical_interface">RGMII</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_rx_inband_ts_enable">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_rx_vec_width">79</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_stats_width">64</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_tx_inband_cf_enable">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_tx_tuser_width">1</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_tx_vec_width">79</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">tri_mode_ethernet_mac_0</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Rate">1_Gbps</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ETHERNET_BOARD_INTERFACE">rgmii</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_1588">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_1588_1step">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_AVB">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_MDIO">true</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Priority_Flow_Control">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Frame_Filter">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Half_Duplex">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MAC_Speed">Tri_speed</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MDIO_BOARD_INTERFACE">mdio_io</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Make_MDIO_External">true</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Management_Frequency">150.00</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Management_Interface">true</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Number_of_Table_Entries">0</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Physical_Interface">RGMII</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RX_Inband_TS_Enable">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Statistics_Counters">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Statistics_Reset">true</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Statistics_Width">64bit</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SupportLevel">0</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TX_Inband_CF_Enable">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Timer_Format">Time_of_day</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD">xilinx.com:kc705:part0:1.2</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/> |
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">3</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/> |
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.4</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue> |
</spirit:configurableElementValues> |
<spirit:vendorExtensions> |
<xilinx:componentInstanceExtensions> |
<xilinx:configElementInfos> |
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ETHERNET_BOARD_INTERFACE" xilinx:valueSource="user"/> |
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Frame_Filter" xilinx:valueSource="user"/> |
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MAC_Speed" xilinx:valueSource="user"/> |
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MDIO_BOARD_INTERFACE" xilinx:valueSource="user"/> |
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Number_of_Table_Entries" xilinx:valueSource="user"/> |
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Physical_Interface" xilinx:valueSource="user"/> |
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Statistics_Counters" xilinx:valueSource="user"/> |
</xilinx:configElementInfos> |
</xilinx:componentInstanceExtensions> |
</spirit:vendorExtensions> |
</spirit:componentInstance> |
</spirit:componentInstances> |
</spirit:design> |
/trunk/hw/src/rtl/tri_mode_emac/xgui/tri_mode_emac_v1_0.tcl
0,0 → 1,10
# Definitional proc to organize widgets for parameters. |
proc init_gui { IPINST } { |
ipgui::add_param $IPINST -name "Component_Name" |
#Adding Page |
ipgui::add_page $IPINST -name "Page 0" |
|
|
} |
|
|
/trunk/hw/src/rtl/tri_mode_emac/component.xml
0,0 → 1,1422
<?xml version="1.0" encoding="UTF-8"?> |
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> |
<spirit:vendor>user-org</spirit:vendor> |
<spirit:library>user</spirit:library> |
<spirit:name>tri_mode_emac</spirit:name> |
<spirit:version>1.0</spirit:version> |
<spirit:busInterfaces> |
<spirit:busInterface> |
<spirit:name>s_axi</spirit:name> |
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/> |
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/> |
<spirit:slave> |
<spirit:memoryMapRef spirit:memoryMapRef="s_axi"/> |
</spirit:slave> |
<spirit:portMaps> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>AWADDR</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>s_axi_awaddr</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>AWVALID</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>s_axi_awvalid</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>AWREADY</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>s_axi_awready</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>WDATA</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>s_axi_wdata</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>WVALID</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>s_axi_wvalid</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>WREADY</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>s_axi_wready</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>BRESP</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>s_axi_bresp</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>BVALID</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>s_axi_bvalid</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>BREADY</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>s_axi_bready</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>ARADDR</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>s_axi_araddr</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>ARVALID</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>s_axi_arvalid</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>ARREADY</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>s_axi_arready</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>RDATA</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>s_axi_rdata</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>RRESP</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>s_axi_rresp</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>RVALID</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>s_axi_rvalid</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>RREADY</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>s_axi_rready</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
</spirit:portMaps> |
</spirit:busInterface> |
<spirit:busInterface> |
<spirit:name>rx_axis_fifo</spirit:name> |
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/> |
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/> |
<spirit:master/> |
<spirit:portMaps> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>TDATA</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>rx_axis_fifo_tdata</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>TLAST</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>rx_axis_fifo_tlast</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>TVALID</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>rx_axis_fifo_tvalid</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>TREADY</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>rx_axis_fifo_tready</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
</spirit:portMaps> |
</spirit:busInterface> |
<spirit:busInterface> |
<spirit:name>tx_axis_fifo</spirit:name> |
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/> |
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/> |
<spirit:slave/> |
<spirit:portMaps> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>TDATA</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>tx_axis_fifo_tdata</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>TLAST</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>tx_axis_fifo_tlast</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>TVALID</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>tx_axis_fifo_tvalid</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>TREADY</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>tx_axis_fifo_tready</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
</spirit:portMaps> |
</spirit:busInterface> |
<spirit:busInterface> |
<spirit:name>s_axi_resetn</spirit:name> |
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/> |
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/> |
<spirit:slave/> |
<spirit:portMaps> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>RST</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>s_axi_resetn</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
</spirit:portMaps> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>POLARITY</spirit:name> |
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_RESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:busInterface> |
<spirit:busInterface> |
<spirit:name>s_axi_aclk</spirit:name> |
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/> |
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/> |
<spirit:slave/> |
<spirit:portMaps> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>CLK</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>s_axi_aclk</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
</spirit:portMaps> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>ASSOCIATED_BUSIF</spirit:name> |
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.ASSOCIATED_BUSIF">s_axi</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>ASSOCIATED_RESET</spirit:name> |
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.ASSOCIATED_RESET">s_axi_resetn</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:busInterface> |
<spirit:busInterface> |
<spirit:name>rx_axi_rstn</spirit:name> |
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/> |
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/> |
<spirit:slave/> |
<spirit:portMaps> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>RST</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>rx_axi_rstn</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
</spirit:portMaps> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>POLARITY</spirit:name> |
<spirit:value spirit:id="BUSIFPARAM_VALUE.RX_AXI_RSTN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:busInterface> |
<spirit:busInterface> |
<spirit:name>rx_fifo_resetn</spirit:name> |
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/> |
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/> |
<spirit:slave/> |
<spirit:portMaps> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>RST</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>rx_fifo_resetn</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
</spirit:portMaps> |
<spirit:parameters> |
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<spirit:wire> |
<spirit:onMaster> |
<spirit:presence>required</spirit:presence> |
<spirit:width>1</spirit:width> |
<spirit:direction>in</spirit:direction> |
</spirit:onMaster> |
<spirit:onSlave> |
<spirit:presence>required</spirit:presence> |
<spirit:width>1</spirit:width> |
<spirit:direction>out</spirit:direction> |
</spirit:onSlave> |
</spirit:wire> |
</spirit:port> |
<spirit:port> |
<spirit:logicalName>refclk</spirit:logicalName> |
<spirit:description/> |
<spirit:wire> |
<spirit:onMaster> |
<spirit:presence>required</spirit:presence> |
<spirit:width>1</spirit:width> |
<spirit:direction>in</spirit:direction> |
</spirit:onMaster> |
<spirit:onSlave> |
<spirit:presence>required</spirit:presence> |
<spirit:width>1</spirit:width> |
<spirit:direction>out</spirit:direction> |
</spirit:onSlave> |
</spirit:wire> |
</spirit:port> |
<spirit:port> |
<spirit:logicalName>rgmii_txd</spirit:logicalName> |
<spirit:description/> |
<spirit:wire> |
<spirit:onMaster> |
<spirit:presence>required</spirit:presence> |
<spirit:width>4</spirit:width> |
<spirit:direction>out</spirit:direction> |
</spirit:onMaster> |
<spirit:onSlave> |
<spirit:presence>required</spirit:presence> |
<spirit:width>4</spirit:width> |
<spirit:direction>in</spirit:direction> |
</spirit:onSlave> |
</spirit:wire> |
</spirit:port> |
<spirit:port> |
<spirit:logicalName>rgmii_tx_ctl</spirit:logicalName> |
<spirit:description/> |
<spirit:wire> |
<spirit:onMaster> |
<spirit:presence>required</spirit:presence> |
<spirit:width>1</spirit:width> |
<spirit:direction>out</spirit:direction> |
</spirit:onMaster> |
<spirit:onSlave> |
<spirit:presence>required</spirit:presence> |
<spirit:width>1</spirit:width> |
<spirit:direction>in</spirit:direction> |
</spirit:onSlave> |
</spirit:wire> |
</spirit:port> |
<spirit:port> |
<spirit:logicalName>rgmii_txc</spirit:logicalName> |
<spirit:description/> |
<spirit:wire> |
<spirit:onMaster> |
<spirit:presence>required</spirit:presence> |
<spirit:width>1</spirit:width> |
<spirit:direction>out</spirit:direction> |
</spirit:onMaster> |
<spirit:onSlave> |
<spirit:presence>required</spirit:presence> |
<spirit:width>1</spirit:width> |
<spirit:direction>in</spirit:direction> |
</spirit:onSlave> |
</spirit:wire> |
</spirit:port> |
<spirit:port> |
<spirit:logicalName>rgmii_rxd</spirit:logicalName> |
<spirit:description/> |
<spirit:wire> |
<spirit:onMaster> |
<spirit:presence>required</spirit:presence> |
<spirit:width>4</spirit:width> |
<spirit:direction>in</spirit:direction> |
</spirit:onMaster> |
<spirit:onSlave> |
<spirit:presence>required</spirit:presence> |
<spirit:width>4</spirit:width> |
<spirit:direction>out</spirit:direction> |
</spirit:onSlave> |
</spirit:wire> |
</spirit:port> |
<spirit:port> |
<spirit:logicalName>rgmii_rx_ctl</spirit:logicalName> |
<spirit:description/> |
<spirit:wire> |
<spirit:onMaster> |
<spirit:presence>required</spirit:presence> |
<spirit:width>1</spirit:width> |
<spirit:direction>in</spirit:direction> |
</spirit:onMaster> |
<spirit:onSlave> |
<spirit:presence>required</spirit:presence> |
<spirit:width>1</spirit:width> |
<spirit:direction>out</spirit:direction> |
</spirit:onSlave> |
</spirit:wire> |
</spirit:port> |
<spirit:port> |
<spirit:logicalName>rgmii_rxc</spirit:logicalName> |
<spirit:description/> |
<spirit:wire> |
<spirit:onMaster> |
<spirit:presence>required</spirit:presence> |
<spirit:width>1</spirit:width> |
<spirit:direction>in</spirit:direction> |
</spirit:onMaster> |
<spirit:onSlave> |
<spirit:presence>required</spirit:presence> |
<spirit:width>1</spirit:width> |
<spirit:direction>out</spirit:direction> |
</spirit:onSlave> |
</spirit:wire> |
</spirit:port> |
<spirit:port> |
<spirit:logicalName>inband_link_status</spirit:logicalName> |
<spirit:description/> |
<spirit:wire> |
<spirit:onMaster> |
<spirit:presence>required</spirit:presence> |
<spirit:width>1</spirit:width> |
<spirit:direction>out</spirit:direction> |
</spirit:onMaster> |
<spirit:onSlave> |
<spirit:presence>required</spirit:presence> |
<spirit:width>1</spirit:width> |
<spirit:direction>in</spirit:direction> |
</spirit:onSlave> |
</spirit:wire> |
</spirit:port> |
<spirit:port> |
<spirit:logicalName>inband_clock_speed</spirit:logicalName> |
<spirit:description/> |
<spirit:wire> |
<spirit:onMaster> |
<spirit:presence>required</spirit:presence> |
<spirit:width>2</spirit:width> |
<spirit:direction>out</spirit:direction> |
</spirit:onMaster> |
<spirit:onSlave> |
<spirit:presence>required</spirit:presence> |
<spirit:width>2</spirit:width> |
<spirit:direction>in</spirit:direction> |
</spirit:onSlave> |
</spirit:wire> |
</spirit:port> |
<spirit:port> |
<spirit:logicalName>inband_duplex_status</spirit:logicalName> |
<spirit:description/> |
<spirit:wire> |
<spirit:onMaster> |
<spirit:presence>required</spirit:presence> |
<spirit:width>1</spirit:width> |
<spirit:direction>out</spirit:direction> |
</spirit:onMaster> |
<spirit:onSlave> |
<spirit:presence>required</spirit:presence> |
<spirit:width>1</spirit:width> |
<spirit:direction>in</spirit:direction> |
</spirit:onSlave> |
</spirit:wire> |
</spirit:port> |
<spirit:port> |
<spirit:logicalName>mdio</spirit:logicalName> |
<spirit:description/> |
<spirit:wire> |
<spirit:onMaster> |
<spirit:presence>required</spirit:presence> |
<spirit:width>1</spirit:width> |
<spirit:direction>inout</spirit:direction> |
</spirit:onMaster> |
<spirit:onSlave> |
<spirit:presence>required</spirit:presence> |
<spirit:width>1</spirit:width> |
<spirit:direction>inout</spirit:direction> |
</spirit:onSlave> |
</spirit:wire> |
</spirit:port> |
<spirit:port> |
<spirit:logicalName>mdc</spirit:logicalName> |
<spirit:description/> |
<spirit:wire> |
<spirit:onMaster> |
<spirit:presence>required</spirit:presence> |
<spirit:width>1</spirit:width> |
<spirit:direction>out</spirit:direction> |
</spirit:onMaster> |
<spirit:onSlave> |
<spirit:presence>required</spirit:presence> |
<spirit:width>1</spirit:width> |
<spirit:direction>in</spirit:direction> |
</spirit:onSlave> |
</spirit:wire> |
</spirit:port> |
</spirit:ports> |
</spirit:abstractionDefinition> |
/trunk/hw/src/rtl/tri_mode_emac_support/common/tri_mode_ethernet_mac_0_reset_sync.v
0,0 → 1,143
//------------------------------------------------------------------------------ |
// Title : Synchronous Reset generation flip-flop pair |
// Project : Tri-Mode ethernet MAC |
//------------------------------------------------------------------------------ |
// File : tri_mode_ethernet_mac_0_reset_sync.v |
// Author : Xilinx, Inc. |
//------------------------------------------------------------------------------ |
// Description: All flip-flops have the same asynchronous reset signal. |
// Together the flops create a minimum of a 1 clock period |
// duration pulse which is used for synchronous reset. |
// |
// The flops are placed, using the ASYNC_REG atrtribute, into the |
// same slice. |
// |
// ----------------------------------------------------------------------------- |
// (c) Copyright 2006-2008 Xilinx, Inc. All rights reserved. |
// |
// This file contains confidential and proprietary information |
// of Xilinx, Inc. and is protected under U.S. and |
// international copyright and other intellectual property |
// laws. |
// |
// DISCLAIMER |
// This disclaimer is not a license and does not grant any |
// rights to the materials distributed herewith. Except as |
// otherwise provided in a valid license issued to you by |
// Xilinx, and to the maximum extent permitted by applicable |
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND |
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES |
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING |
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- |
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and |
// (2) Xilinx shall not be liable (whether in contract or tort, |
// including negligence, or under any other theory of |
// liability) for any loss or damage of any kind or nature |
// related to, arising under or in connection with these |
// materials, including for any direct, or any indirect, |
// special, incidental, or consequential loss or damage |
// (including loss of data, profits, goodwill, or any type of |
// loss or damage suffered as a result of any action brought |
// by a third party) even if such damage or loss was |
// reasonably foreseeable or Xilinx had been advised of the |
// possibility of the same. |
// |
// CRITICAL APPLICATIONS |
// Xilinx products are not designed or intended to be fail- |
// safe, or for use in any application requiring fail-safe |
// performance, such as life-support or safety devices or |
// systems, Class III medical devices, nuclear facilities, |
// applications related to the deployment of airbags, or any |
// other applications that could lead to death, personal |
// injury, or severe property or environmental damage |
// (individually and collectively, "Critical |
// Applications"). Customer assumes the sole risk and |
// liability of any use of Xilinx products in Critical |
// Applications, subject only to applicable laws and |
// regulations governing limitations on product liability. |
// |
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS |
// PART OF THIS FILE AT ALL TIMES. |
// ----------------------------------------------------------------------------- |
|
`timescale 1ps/1ps |
|
(* dont_touch = "yes" *) |
module tri_mode_ethernet_mac_0_reset_sync #( |
parameter INITIALISE = 1'b1, |
parameter DEPTH = 5 |
) |
( |
input reset_in, |
input clk, |
input enable, |
output reset_out |
); |
|
|
wire reset_sync_reg0; |
wire reset_sync_reg1; |
wire reset_sync_reg2; |
wire reset_sync_reg3; |
wire reset_sync_reg4; |
|
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *) |
FDPE #( |
.INIT (INITIALISE[0]) |
) reset_sync0 ( |
.C (clk), |
.CE (enable), |
.PRE(reset_in), |
.D (1'b0), |
.Q (reset_sync_reg0) |
); |
|
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *) |
FDPE #( |
.INIT (INITIALISE[0]) |
) reset_sync1 ( |
.C (clk), |
.CE (enable), |
.PRE(reset_in), |
.D (reset_sync_reg0), |
.Q (reset_sync_reg1) |
); |
|
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *) |
FDPE #( |
.INIT (INITIALISE[0]) |
) reset_sync2 ( |
.C (clk), |
.CE (enable), |
.PRE(reset_in), |
.D (reset_sync_reg1), |
.Q (reset_sync_reg2) |
); |
|
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *) |
FDPE #( |
.INIT (INITIALISE[0]) |
) reset_sync3 ( |
.C (clk), |
.CE (enable), |
.PRE(reset_in), |
.D (reset_sync_reg2), |
.Q (reset_sync_reg3) |
); |
|
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *) |
FDPE #( |
.INIT (INITIALISE[0]) |
) reset_sync4 ( |
.C (clk), |
.CE (enable), |
.PRE(reset_in), |
.D (reset_sync_reg3), |
.Q (reset_sync_reg4) |
); |
|
|
assign reset_out = reset_sync_reg4; |
|
|
endmodule |
/trunk/hw/src/rtl/tri_mode_emac_support/common/tri_mode_ethernet_mac_0_sync_block.v
0,0 → 1,141
//------------------------------------------------------------------------------ |
// Title : CDC Sync Block |
// Project : Tri-Mode Ethernet MAC |
//------------------------------------------------------------------------------ |
// File : tri_mode_ethernet_mac_0_sync_block.v |
// Author : Xilinx Inc. |
//------------------------------------------------------------------------------ |
// Description: Used on signals crossing from one clock domain to another, this |
// is a multiple flip-flop pipeline, with all flops placed together |
// into the same slice. Thus the routing delay between the two is |
// minimum to safe-guard against metastability issues. |
// ----------------------------------------------------------------------------- |
// (c) Copyright 2001-2013 Xilinx, Inc. All rights reserved. |
// |
// This file contains confidential and proprietary information |
// of Xilinx, Inc. and is protected under U.S. and |
// international copyright and other intellectual property |
// laws. |
// |
// DISCLAIMER |
// This disclaimer is not a license and does not grant any |
// rights to the materials distributed herewith. Except as |
// otherwise provided in a valid license issued to you by |
// Xilinx, and to the maximum extent permitted by applicable |
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND |
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES |
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING |
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- |
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and |
// (2) Xilinx shall not be liable (whether in contract or tort, |
// including negligence, or under any other theory of |
// liability) for any loss or damage of any kind or nature |
// related to, arising under or in connection with these |
// materials, including for any direct, or any indirect, |
// special, incidental, or consequential loss or damage |
// (including loss of data, profits, goodwill, or any type of |
// loss or damage suffered as a result of any action brought |
// by a third party) even if such damage or loss was |
// reasonably foreseeable or Xilinx had been advised of the |
// possibility of the same. |
// |
// CRITICAL APPLICATIONS |
// Xilinx products are not designed or intended to be fail- |
// safe, or for use in any application requiring fail-safe |
// performance, such as life-support or safety devices or |
// systems, Class III medical devices, nuclear facilities, |
// applications related to the deployment of airbags, or any |
// other applications that could lead to death, personal |
// injury, or severe property or environmental damage |
// (individually and collectively, "Critical |
// Applications"). Customer assumes the sole risk and |
// liability of any use of Xilinx products in Critical |
// Applications, subject only to applicable laws and |
// regulations governing limitations on product liability. |
// |
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS |
// PART OF THIS FILE AT ALL TIMES. |
// ----------------------------------------------------------------------------- |
|
`timescale 1ps / 1ps |
|
(* dont_touch = "yes" *) |
module tri_mode_ethernet_mac_0_sync_block #( |
parameter INITIALISE = 1'b0, |
parameter DEPTH = 5 |
) |
( |
input clk, // clock to be sync'ed to |
input data_in, // Data to be 'synced' |
output data_out // synced data |
); |
|
// Internal Signals |
wire data_sync0; |
wire data_sync1; |
wire data_sync2; |
wire data_sync3; |
wire data_sync4; |
|
|
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *) |
FDRE #( |
.INIT (INITIALISE[0]) |
) data_sync_reg0 ( |
.C (clk), |
.D (data_in), |
.Q (data_sync0), |
.CE (1'b1), |
.R (1'b0) |
); |
|
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *) |
FDRE #( |
.INIT (INITIALISE[0]) |
) data_sync_reg1 ( |
.C (clk), |
.D (data_sync0), |
.Q (data_sync1), |
.CE (1'b1), |
.R (1'b0) |
); |
|
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *) |
FDRE #( |
.INIT (INITIALISE[0]) |
) data_sync_reg2 ( |
.C (clk), |
.D (data_sync1), |
.Q (data_sync2), |
.CE (1'b1), |
.R (1'b0) |
); |
|
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *) |
FDRE #( |
.INIT (INITIALISE[0]) |
) data_sync_reg3 ( |
.C (clk), |
.D (data_sync2), |
.Q (data_sync3), |
.CE (1'b1), |
.R (1'b0) |
); |
|
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *) |
FDRE #( |
.INIT (INITIALISE[0]) |
) data_sync_reg4 ( |
.C (clk), |
.D (data_sync3), |
.Q (data_sync4), |
.CE (1'b1), |
.R (1'b0) |
); |
|
assign data_out = data_sync4; |
|
|
endmodule |
|
|
/trunk/hw/src/rtl/tri_mode_emac_support/tri_mode_ethernet_mac_0_clk_wiz.v
0,0 → 1,186
// file: tri_mode_ethernet_mac_0_clk_wiz.v |
// |
// ----------------------------------------------------------------------------- |
// (c) Copyright 2008-2013 Xilinx, Inc. All rights reserved. |
// |
// This file contains confidential and proprietary information |
// of Xilinx, Inc. and is protected under U.S. and |
// international copyright and other intellectual property |
// laws. |
// |
// DISCLAIMER |
// This disclaimer is not a license and does not grant any |
// rights to the materials distributed herewith. Except as |
// otherwise provided in a valid license issued to you by |
// Xilinx, and to the maximum extent permitted by applicable |
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND |
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES |
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING |
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- |
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and |
// (2) Xilinx shall not be liable (whether in contract or tort, |
// including negligence, or under any other theory of |
// liability) for any loss or damage of any kind or nature |
// related to, arising under or in connection with these |
// materials, including for any direct, or any indirect, |
// special, incidental, or consequential loss or damage |
// (including loss of data, profits, goodwill, or any type of |
// loss or damage suffered as a result of any action brought |
// by a third party) even if such damage or loss was |
// reasonably foreseeable or Xilinx had been advised of the |
// possibility of the same. |
// |
// CRITICAL APPLICATIONS |
// Xilinx products are not designed or intended to be fail- |
// safe, or for use in any application requiring fail-safe |
// performance, such as life-support or safety devices or |
// systems, Class III medical devices, nuclear facilities, |
// applications related to the deployment of airbags, or any |
// other applications that could lead to death, personal |
// injury, or severe property or environmental damage |
// (individually and collectively, "Critical |
// Applications"). Customer assumes the sole risk and |
// liability of any use of Xilinx products in Critical |
// Applications, subject only to applicable laws and |
// regulations governing limitations on product liability. |
// |
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS |
// PART OF THIS FILE AT ALL TIMES. |
// ----------------------------------------------------------------------------- |
//---------------------------------------------------------------------------- |
// User entered comments |
//---------------------------------------------------------------------------- |
// None |
// |
//---------------------------------------------------------------------------- |
// Output Output Phase Duty Cycle Pk-to-Pk Phase |
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) |
//---------------------------------------------------------------------------- |
// CLK_OUT1 125.000 0.000 50.0 91.364 85.928 |
// CLK_OUT2 100.000 0.000 50.0 70.716 85.928 |
|
// CLK_OUT2 200.000 0.000 50.0 |
|
// |
//---------------------------------------------------------------------------- |
// Input Clock Input Freq (MHz) Input Jitter (UI) |
//---------------------------------------------------------------------------- |
// primary 200.000 0.010 |
|
`timescale 1ps/1ps |
|
module tri_mode_ethernet_mac_0_clk_wiz |
(// Clock in ports |
input CLK_IN1, |
// Clock out ports |
output CLK_OUT1, |
output CLK_OUT2, |
output CLK_OUT3, |
// Status and control signals |
input RESET, |
output LOCKED |
); |
|
// Clocking primitive |
//------------------------------------ |
// Instantiation of the MMCM primitive |
// * Unused inputs are tied off |
// * Unused outputs are labeled unused |
wire [15:0] do_unused; |
wire drdy_unused; |
wire psdone_unused; |
wire clkfbout; |
wire clkfboutb_unused; |
wire clkout0b_unused; |
wire clkout1b_unused; |
wire clkout2b_unused; |
wire clkout3_unused; |
wire clkout3b_unused; |
wire clkout4_unused; |
wire clkout5_unused; |
wire clkout6_unused; |
wire clkfbstopped_unused; |
wire clkinstopped_unused; |
|
MMCME2_ADV |
|
#(.BANDWIDTH ("OPTIMIZED"), |
.COMPENSATION ("ZHOLD"), |
|
.DIVCLK_DIVIDE (1), |
.CLKFBOUT_MULT_F (5.000), |
.CLKFBOUT_PHASE (0.000), |
.CLKOUT0_DIVIDE_F (8.000), |
.CLKOUT0_PHASE (0.000), |
.CLKOUT0_DUTY_CYCLE (0.500), |
.CLKOUT1_DIVIDE (10), |
.CLKOUT1_PHASE (0.000), |
.CLKOUT1_DUTY_CYCLE (0.500), |
|
.CLKOUT2_DIVIDE (5), |
|
.CLKOUT2_PHASE (0.000), |
.CLKOUT2_DUTY_CYCLE (0.500), |
.CLKIN1_PERIOD (5.000), |
.REF_JITTER1 (0.010)) |
mmcm_adv_inst |
// Output clocks |
(.CLKFBOUT (clkfbout), |
.CLKFBOUTB (clkfboutb_unused), |
.CLKOUT0 (clkout0), |
.CLKOUT0B (clkout0b_unused), |
.CLKOUT1 (clkout1), |
.CLKOUT1B (clkout1b_unused), |
.CLKOUT2 (clkout2), |
.CLKOUT2B (clkout2b_unused), |
.CLKOUT3 (clkout3_unused), |
.CLKOUT3B (clkout3b_unused), |
.CLKOUT4 (clkout4_unused), |
.CLKOUT5 (clkout5_unused), |
.CLKOUT6 (clkout6_unused), |
// Input clock control |
.CLKFBIN (clkfbout), |
.CLKIN1 (CLK_IN1), |
.CLKIN2 (1'b0), |
// Tied to always select the primary input clock |
.CLKINSEL (1'b1), |
// Ports for dynamic reconfiguration |
.DADDR (7'h0), |
.DCLK (1'b0), |
.DEN (1'b0), |
.DI (16'h0), |
.DO (do_unused), |
.DRDY (drdy_unused), |
.DWE (1'b0), |
// Ports for dynamic phase shift |
.PSCLK (1'b0), |
.PSEN (1'b0), |
.PSINCDEC (1'b0), |
.PSDONE (psdone_unused), |
|
// Other control and status signals |
.LOCKED (LOCKED), |
.CLKINSTOPPED (clkinstopped_unused), |
.CLKFBSTOPPED (clkfbstopped_unused), |
.PWRDWN (1'b0), |
.RST (RESET)); |
|
// Output buffering |
//----------------------------------- |
|
BUFGCE clkout1_buf |
(.O (CLK_OUT1), |
.CE (1'b1), |
.I (clkout0)); |
|
BUFGCE clkout2_buf |
(.O (CLK_OUT2), |
.CE (1'b1), |
.I (clkout1)); |
|
BUFGCE clkout3_buf |
(.O (CLK_OUT3), |
.CE (1'b1), |
.I (clkout2)); |
|
endmodule |
/trunk/hw/src/rtl/tri_mode_emac_support/tri_mode_ethernet_mac_0_example_design_clocks.v
0,0 → 1,137
//------------------------------------------------------------------------------ |
// File : tri_mode_ethernet_mac_0_example_design_clock.v |
// Author : Xilinx Inc. |
// ----------------------------------------------------------------------------- |
// (c) Copyright 2012 Xilinx, Inc. All rights reserved. |
// |
// This file contains confidential and proprietary information |
// of Xilinx, Inc. and is protected under U.S. and |
// international copyright and other intellectual property |
// laws. |
// |
// DISCLAIMER |
// This disclaimer is not a license and does not grant any |
// rights to the materials distributed herewith. Except as |
// otherwise provided in a valid license issued to you by |
// Xilinx, and to the maximum extent permitted by applicable |
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND |
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES |
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING |
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- |
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and |
// (2) Xilinx shall not be liable (whether in contract or tort, |
// including negligence, or under any other theory of |
// liability) for any loss or damage of any kind or nature |
// related to, arising under or in connection with these |
// materials, including for any direct, or any indirect, |
// special, incidental, or consequential loss or damage |
// (including loss of data, profits, goodwill, or any type of |
// loss or damage suffered as a result of any action brought |
// by a third party) even if such damage or loss was |
// reasonably foreseeable or Xilinx had been advised of the |
// possibility of the same. |
// |
// CRITICAL APPLICATIONS |
// Xilinx products are not designed or intended to be fail- |
// safe, or for use in any application requiring fail-safe |
// performance, such as life-support or safety devices or |
// systems, Class III medical devices, nuclear facilities, |
// applications related to the deployment of airbags, or any |
// other applications that could lead to death, personal |
// injury, or severe property or environmental damage |
// (individually and collectively, "Critical |
// Applications"). Customer assumes the sole risk and |
// liability of any use of Xilinx products in Critical |
// Applications, subject only to applicable laws and |
// regulations governing limitations on product liability. |
// |
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS |
// PART OF THIS FILE AT ALL TIMES. |
// ----------------------------------------------------------------------------- |
// Description: This block generates the clocking logic required for the |
// example design. |
|
`timescale 1 ps/1 ps |
|
module tri_mode_ethernet_mac_0_example_design_clocks |
( |
// differential clock inputs |
input clk_in_p, |
input clk_in_n, |
|
// asynchronous control/resets |
input glbl_rst, |
output dcm_locked, |
|
// clock outputs |
output gtx_clk_bufg, |
output refclk_bufg, |
output s_axi_aclk |
); |
|
|
wire clkin1; |
wire mmcm_rst; |
wire clkin1_bufg; |
wire dcm_locked_int; |
wire dcm_locked_sync; |
reg dcm_locked_reg = 1; |
reg dcm_locked_edge = 1; |
|
// Input buffering |
//------------------------------------ |
IBUFDS clkin1_buf |
(.O (clkin1), |
.I (clk_in_p), |
.IB (clk_in_n)); |
|
// route clkin1 through a BUFGCE for the MMCM reset generation logic |
BUFGCE bufg_clkin1 (.I(clkin1), .CE (1'b1), .O(clkin1_bufg)); |
|
// detect a falling edge on dcm_locked (after resyncing to this domain) |
tri_mode_ethernet_mac_0_sync_block lock_sync ( |
.clk (clkin1_bufg), |
.data_in (dcm_locked_int), |
.data_out (dcm_locked_sync) |
); |
|
// for the falling edge detect we want to force this at power on so init the flop to 1 |
always @(posedge clkin1_bufg) |
begin |
dcm_locked_reg <= dcm_locked_sync; |
dcm_locked_edge <= dcm_locked_reg & !dcm_locked_sync; |
end |
|
// the MMCM reset should be at least 5ns - that is one cycle of the input clock - |
// since the source of the input reset is unknown (a push switch in board design) |
// this needs to be debounced |
tri_mode_ethernet_mac_0_reset_sync mmcm_reset_gen ( |
.clk (clkin1_bufg), |
.enable (1'b1), |
.reset_in (glbl_rst | dcm_locked_edge), |
.reset_out (mmcm_rst) |
); |
|
|
//---------------------------------------------------------------------------- |
// Generate clocks using the clock wizard |
//---------------------------------------------------------------------------- |
|
tri_mode_ethernet_mac_0_clk_wiz clock_generator |
( |
// Clock in ports |
.CLK_IN1 (clkin1), |
// Clock out ports |
.CLK_OUT1 (gtx_clk_bufg), |
.CLK_OUT2 (s_axi_aclk), |
.CLK_OUT3 (refclk_bufg), |
// Status and control signals |
.RESET (mmcm_rst), |
.LOCKED (dcm_locked_int) |
); |
|
assign dcm_locked = dcm_locked_int; |
|
|
|
endmodule |
/trunk/hw/src/rtl/tri_mode_emac_support/tri_mode_ethernet_mac_0_example_design_resets.v
0,0 → 1,220
//------------------------------------------------------------------------------ |
// File : tri_mode_ethernet_mac_0_example_design_resets.v |
// Author : Xilinx Inc. |
// ----------------------------------------------------------------------------- |
// (c) Copyright 2012 Xilinx, Inc. All rights reserved. |
// |
// This file contains confidential and proprietary information |
// of Xilinx, Inc. and is protected under U.S. and |
// international copyright and other intellectual property |
// laws. |
// |
// DISCLAIMER |
// This disclaimer is not a license and does not grant any |
// rights to the materials distributed herewith. Except as |
// otherwise provided in a valid license issued to you by |
// Xilinx, and to the maximum extent permitted by applicable |
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND |
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES |
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING |
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- |
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and |
// (2) Xilinx shall not be liable (whether in contract or tort, |
// including negligence, or under any other theory of |
// liability) for any loss or damage of any kind or nature |
// related to, arising under or in connection with these |
// materials, including for any direct, or any indirect, |
// special, incidental, or consequential loss or damage |
// (including loss of data, profits, goodwill, or any type of |
// loss or damage suffered as a result of any action brought |
// by a third party) even if such damage or loss was |
// reasonably foreseeable or Xilinx had been advised of the |
// possibility of the same. |
// |
// CRITICAL APPLICATIONS |
// Xilinx products are not designed or intended to be fail- |
// safe, or for use in any application requiring fail-safe |
// performance, such as life-support or safety devices or |
// systems, Class III medical devices, nuclear facilities, |
// applications related to the deployment of airbags, or any |
// other applications that could lead to death, personal |
// injury, or severe property or environmental damage |
// (individually and collectively, "Critical |
// Applications"). Customer assumes the sole risk and |
// liability of any use of Xilinx products in Critical |
// Applications, subject only to applicable laws and |
// regulations governing limitations on product liability. |
// |
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS |
// PART OF THIS FILE AT ALL TIMES. |
// ----------------------------------------------------------------------------- |
// Description: This block generates fully synchronous resets for each clock domain |
`timescale 1 ps/1 ps |
|
module tri_mode_ethernet_mac_0_example_design_resets |
( |
// clocks |
input s_axi_aclk, |
input gtx_clk, |
|
// asynchronous resets |
input glbl_rst, |
input reset_error, |
input rx_reset, |
input tx_reset, |
|
input dcm_locked, |
|
// synchronous reset outputs |
|
output glbl_rst_intn, |
|
output reg gtx_resetn = 0, |
|
output reg s_axi_resetn = 0, |
output phy_resetn, |
output reg chk_resetn = 0 |
); |
|
// define internal signals |
reg s_axi_pre_resetn = 0; |
wire s_axi_reset_int; |
|
reg gtx_pre_resetn = 0; |
wire gtx_clk_reset_int; |
|
reg chk_pre_resetn = 0; |
wire chk_reset_int; |
wire dcm_locked_sync; |
reg phy_resetn_int; |
reg [5:0] phy_reset_count; |
|
//---------------------------------------------------------------------------- |
// Synchronise the async dcm_locked into the gtx_clk clock domain |
//---------------------------------------------------------------------------- |
tri_mode_ethernet_mac_0_sync_block dcm_sync ( |
.clk (gtx_clk), |
.data_in (dcm_locked), |
.data_out (dcm_locked_sync) |
); |
|
|
//---------------------------------------------------------------------------- |
// Generate resets required for the fifo side signals etc |
//---------------------------------------------------------------------------- |
// in each case the async reset is first captured and then synchronised |
|
//--------------- |
// global reset |
tri_mode_ethernet_mac_0_reset_sync glbl_reset_gen ( |
.clk (gtx_clk), |
.enable (dcm_locked_sync), |
.reset_in (glbl_rst), |
.reset_out (glbl_rst_int) |
); |
|
assign glbl_rst_intn = !glbl_rst_int; |
|
|
|
//--------------- |
// AXI-Lite reset |
tri_mode_ethernet_mac_0_reset_sync axi_lite_reset_gen ( |
.clk (s_axi_aclk), |
.enable (phy_resetn_int), |
.reset_in (glbl_rst), |
.reset_out (s_axi_reset_int) |
); |
|
// Create fully synchronous reset in the s_axi clock domain. |
always @(posedge s_axi_aclk) |
begin |
if (s_axi_reset_int) begin |
s_axi_pre_resetn <= 0; |
s_axi_resetn <= 0; |
end |
else begin |
s_axi_pre_resetn <= 1; |
s_axi_resetn <= s_axi_pre_resetn; |
end |
end |
|
//--------------- |
|
// gtx_clk reset |
|
tri_mode_ethernet_mac_0_reset_sync gtx_reset_gen ( |
|
.clk (gtx_clk), |
|
.enable (dcm_locked_sync), |
.reset_in (glbl_rst || rx_reset || tx_reset), |
|
.reset_out (gtx_clk_reset_int) |
|
); |
|
|
// Create fully synchronous reset in the gtx_clk domain. |
always @(posedge gtx_clk) |
begin |
if (gtx_clk_reset_int) begin |
gtx_pre_resetn <= 0; |
gtx_resetn <= 0; |
end |
else begin |
gtx_pre_resetn <= 1; |
gtx_resetn <= gtx_pre_resetn; |
end |
end |
|
//--------------- |
// data check reset |
tri_mode_ethernet_mac_0_reset_sync chk_reset_gen ( |
|
.clk (gtx_clk), |
|
.enable (dcm_locked_sync), |
.reset_in (glbl_rst || reset_error), |
.reset_out (chk_reset_int) |
); |
|
|
// Create fully synchronous reset in the gtx_clk domain. |
always @(posedge gtx_clk) |
|
begin |
if (chk_reset_int) begin |
chk_pre_resetn <= 0; |
chk_resetn <= 0; |
end |
else begin |
chk_pre_resetn <= 1; |
chk_resetn <= chk_pre_resetn; |
end |
end |
|
|
//--------------- |
// PHY reset |
// the phy reset output (active low) needs to be held for at least 10x25MHZ cycles |
// this is derived using the 125MHz available and a 6 bit counter |
always @(posedge gtx_clk) |
begin |
if (glbl_rst_int) begin |
phy_resetn_int <= 0; |
phy_reset_count <= 0; |
end |
else begin |
if (!(&phy_reset_count)) begin |
phy_reset_count <= phy_reset_count + 1; |
end |
else begin |
phy_resetn_int <= 1; |
end |
end |
end |
|
assign phy_resetn = phy_resetn_int; |
|
endmodule |
/trunk/hw/src/rtl/microb_top.v
0,0 → 1,109
//-------------------------------------------------------------------------------- |
`timescale 1 ps / 1 ps |
|
module microb_top |
( |
output [7:0] led_8bits_tri_o, |
input glbl_rst, |
input rs232_uart_rxd, |
output rs232_uart_txd, |
// 200MHz clock input from board |
input sys_diff_clock_clk_n, |
input sys_diff_clock_clk_p, |
// PHY rst |
output phy_resetn, |
// RGMII Interface |
output [3:0] rgmii_txd, |
output rgmii_tx_ctl, |
output rgmii_txc, |
input [3:0] rgmii_rxd, |
input rgmii_rx_ctl, |
input rgmii_rxc, |
// MDIO Interface |
inout mdio, |
output mdc |
|
); |
//-------------------------------------------------------------------------------- |
// Clock logic to generate required clocks from the 200MHz on board |
tri_mode_ethernet_mac_0_example_design_clocks example_clocks |
( |
// differential clock inputs |
.clk_in_p (sys_diff_clock_clk_p), |
.clk_in_n (sys_diff_clock_clk_n), |
|
// asynchronous control/resets |
.glbl_rst (glbl_rst), // in |
.dcm_locked (dcm_locked), // out |
|
// clock outputs |
.gtx_clk_bufg (gtx_clk_bufg),// 125MHz |
.refclk_bufg (refclk_bufg), // 200 MHZ |
.s_axi_aclk (s_axi_aclk) // 100MHz |
); |
|
assign tx_fifo_clock = gtx_clk_bufg; |
assign rx_fifo_clock = gtx_clk_bufg; |
//-------------------------------------------------------------------------------- |
// Generate resets required for the fifo side signals etc |
tri_mode_ethernet_mac_0_example_design_resets example_resets |
( |
// clocks |
.s_axi_aclk (s_axi_aclk), |
.gtx_clk (gtx_clk_bufg), |
|
// asynchronous resets |
.glbl_rst (glbl_rst), |
.reset_error (reset_error), |
.rx_reset (rx_reset), |
.tx_reset (tx_reset), |
|
.dcm_locked (dcm_locked), |
|
// synchronous reset outputs |
|
.glbl_rst_intn (glbl_rst_intn), |
|
|
.gtx_resetn (gtx_resetn), |
|
.s_axi_resetn (s_axi_resetn), |
.phy_resetn (phy_resetn), |
.chk_resetn () |
); |
|
assign tx_fifo_resetn = gtx_resetn; |
assign rx_fifo_resetn = gtx_resetn; |
//-------------------------------------------------------------------------------- |
base_microblaze_design u0 |
( |
// SYS_CON |
.Clk (s_axi_aclk), |
.reset (!s_axi_resetn), |
// LED |
.led_8bits_tri_o (led_8bits_tri_o), |
// UART |
.rs232_uart_rxd (rs232_uart_rxd), |
.rs232_uart_txd (rs232_uart_txd), |
// TMEMAC |
.tmemac_1_glbl_rstn (glbl_rst_intn), |
.tmemac_1_gtx_clk (gtx_clk_bufg), |
.tmemac_1_inband_clock_speed (), |
.tmemac_1_inband_duplex_status (), |
.tmemac_1_inband_link_status (), |
// mdio |
.tmemac_1_mdc (mdc), // output |
.tmemac_1_mdio (mdio), // inout |
// IDELAYCTRL-clk |
.tmemac_1_refclk (refclk_bufg), |
// RGMII-rx |
.tmemac_1_rgmii_rx_ctl (rgmii_rx_ctl), |
.tmemac_1_rgmii_rxc (rgmii_rxc), |
.tmemac_1_rgmii_rxd (rgmii_rxd), |
// RGMII-tx |
.tmemac_1_rgmii_tx_ctl (rgmii_tx_ctl), |
.tmemac_1_rgmii_txc (rgmii_txc), |
.tmemac_1_rgmii_txd (rgmii_txd) |
); |
//-------------------------------------------------------------------------------- |
endmodule |
/trunk/hw/src/tb/bfm_eth_log/bfm_eth_log_cl.sv
0,0 → 1,149
////////////////////////////////////////////////////////////////////////////////// |
// Company: |
// Engineer: IK |
// |
// Create Date: 11:35:01 03/21/2013 |
// Design Name: |
// Module Name: bfm_eth_log_cl |
// Project Name: |
// Target Devices: |
// Tool versions: |
// Description: |
// |
// |
// Revision: |
// Revision 0.01 - File Created, |
// |
////////////////////////////////////////////////////////////////////////////////// |
`timescale 1ns / 1ps |
|
typedef virtual interface rgmii_rx_if virt_rx_if_t; |
|
class bfm_eth_log_cl; |
////////////////////////////////////////////////////////////////////////////////// |
// |
virt_rx_if_t vif_rx; |
virt_rx_if_t vif_tx; |
// |
string name; |
bit verbose; |
// |
int fd, fd_idx; |
pcap_pkg::u_pcap_hdr_t sv_pcap_hdr_u; |
pcap_pkg::u_pcaprec_hdr_t sv_pcaprec_hdr_u; |
// |
static int idx=0; |
|
////////////////////////////////////////////////////////////////////////////////// |
|
static function int next_id; |
next_id = idx++; |
endfunction : next_id |
|
function new (string name = "logger", virt_rx_if_t rx, virt_rx_if_t tx, bit i_verbose=0); |
string str; |
// name |
str.itoa(next_id()); |
this.name = {name, "#" ,str}; |
this.verbose = i_verbose; |
// |
this.fd = 0; this.fd_idx = 0; |
// fill-in pcap_hdr |
sv_pcap_hdr_u.pcap_hdr.magic_number = 32'ha1b2c3d4; |
sv_pcap_hdr_u.pcap_hdr.version_major = 2; |
sv_pcap_hdr_u.pcap_hdr.version_minor = 4; |
sv_pcap_hdr_u.pcap_hdr.thiszone = 0; |
sv_pcap_hdr_u.pcap_hdr.sigfigs = 0; |
sv_pcap_hdr_u.pcap_hdr.snaplen = 256*1024; // 256KB |
sv_pcap_hdr_u.pcap_hdr.network = 1; |
// if |
this.vif_rx = rx; |
this.vif_tx = tx; |
// Final |
endfunction : new |
|
////////////////////////////////////////////////////////////////////////////////// |
|
task init; |
vif_rx.init(); |
vif_tx.init(); |
$display("%s ready", this.name); |
// Final |
endtask : init |
|
task log_run; |
// dec var |
int rx_pkt_len, tx_pkt_len; |
// if we are in RUN |
if (fd_idx) |
begin : _RE |
$fclose(fd); |
$display("[%t]: %m: re-open PCAP, last frm can be dropped!", $time); |
end |
// pcap-open |
fd = $fopen($sformatf("%s_%02d.pcap", name, fd_idx++), "wb"); |
// write pcap-hdr |
for (int i = 0; i < pcap_pkg::pcap_hdr_sz; i++) |
$fwrite(fd, "%c", 8'(sv_pcap_hdr_u.data[i])); |
// sta RX-LOG |
fork |
forever |
begin : LOG_RX |
// get ETH-pkt |
vif_rx.rx_pkt(); |
// get pkt-id |
rx_pkt_len = vif_rx.rx_pkt_len(); |
// prep-hdr |
sv_pcaprec_hdr_u.pcaprec_hdr.ts_sec = ($time/1_000_000); |
sv_pcaprec_hdr_u.pcaprec_hdr.ts_usec = ($time%1_000_000); |
sv_pcaprec_hdr_u.pcaprec_hdr.incl_len = rx_pkt_len; |
sv_pcaprec_hdr_u.pcaprec_hdr.orig_len = rx_pkt_len; |
// wr-hdr |
for (int i = 0; i < pcap_pkg::pcaprec_hdr_sz; i++) |
$fwrite(fd, "%c", 8'(sv_pcaprec_hdr_u.data[i])); |
// wr-data |
for (int i = 0; i < rx_pkt_len; i++) |
$fwrite(fd, "%c", 8'(vif_rx.rx_pkt_data(i))); |
// |
if (verbose) |
$display("[%t]: %m: rx-pkt_len=%h", $time, rx_pkt_len); |
end |
join_none |
// sta TX-LOG |
fork |
forever |
begin : LOG_TX |
// get ETH-pkt |
vif_tx.rx_pkt(); |
// get pkt-id |
tx_pkt_len = vif_tx.rx_pkt_len(); |
// prep-hdr |
sv_pcaprec_hdr_u.pcaprec_hdr.ts_sec = ($time/1_000_000); |
sv_pcaprec_hdr_u.pcaprec_hdr.ts_usec = ($time%1_000_000); |
sv_pcaprec_hdr_u.pcaprec_hdr.incl_len = tx_pkt_len; |
sv_pcaprec_hdr_u.pcaprec_hdr.orig_len = tx_pkt_len; |
// wr-hdr |
for (int i = 0; i < pcap_pkg::pcaprec_hdr_sz; i++) |
$fwrite(fd, "%c", 8'(sv_pcaprec_hdr_u.data[i])); |
// wr-data |
for (int i = 0; i < tx_pkt_len; i++) |
$fwrite(fd, "%c", 8'(vif_tx.rx_pkt_data(i))); |
// |
if (verbose) |
$display("[%t]: %m: tx-pkt_len=%h", $time, tx_pkt_len); |
end |
join_none |
// |
endtask : log_run |
|
task log_stop; |
if (fd) |
begin : STOP_LOG |
// close pcap-file |
$fclose(fd); fd = 0; |
// fd=INVALID, so we must stop logging NOW |
disable log_run; |
end |
endtask : log_stop |
////////////////////////////////////////////////////////////////////////////////// |
endclass : bfm_eth_log_cl |
/trunk/hw/src/tb/bfm_eth_log/pcap_pkg.sv
0,0 → 1,50
////////////////////////////////////////////////////////////////////////////////// |
// Company: |
// Engineer: IK |
// |
// Create Date: 11:35:01 03/21/2013 |
// Design Name: |
// Module Name: pcap_pkg |
// Project Name: |
// Target Devices: |
// Tool versions: |
// Description: |
// |
// |
// Revision: |
// Revision 0.01 - File Created, |
// |
////////////////////////////////////////////////////////////////////////////////// |
|
package pcap_pkg; |
////////////////////////////////////////////////////////////////////////////////// |
// |
localparam pcap_hdr_sz = 6*4; // 6DW |
typedef struct packed { |
bit [31:0] magic_number; /* magic number */ |
bit [15:0] version_major; /* major version number */ |
bit [15:0] version_minor; /* minor version number */ |
bit [31:0] thiszone; /* GMT to local correction */ |
bit [31:0] sigfigs; /* accuracy of timestamps */ |
bit [31:0] snaplen; /* max length of captured packets, in octets */ |
bit [31:0] network; /* data link type */ |
} pcap_hdr_t; |
typedef union packed { |
pcap_hdr_t pcap_hdr; |
bit [0:pcap_hdr_sz-1] [7:0] data; |
//bit [pcap_hdr_sz-1:0] data; |
} u_pcap_hdr_t; |
// |
localparam pcaprec_hdr_sz = 4*4; // 4DW |
typedef struct packed { |
bit [31:0] ts_sec; /* timestamp seconds */ |
bit [31:0] ts_usec; /* timestamp microseconds */ |
bit [31:0] incl_len; /* number of octets of packet saved in file */ |
bit [31:0] orig_len; /* actual length of packet */ |
} pcaprec_hdr_t; |
typedef union packed { |
pcaprec_hdr_t pcaprec_hdr; |
bit [0:pcaprec_hdr_sz-1] [7:0] data; |
} u_pcaprec_hdr_t; |
////////////////////////////////////////////////////////////////////////////////// |
endpackage : pcap_pkg |
/trunk/hw/src/tb/bfm_eth_log/rgmii_rx_if.sv
0,0 → 1,101
////////////////////////////////////////////////////////////////////////////////// |
// Company: |
// Engineer: IK |
// |
// Create Date: 11:35:01 03/21/2013 |
// Design Name: |
// Module Name: rgmii_rx_if |
// Project Name: |
// Target Devices: |
// Tool versions: |
// Description: |
// |
// |
// Revision: |
// Revision 0.01 - File Created, |
// |
////////////////////////////////////////////////////////////////////////////////// |
`timescale 1ns / 1ps |
|
interface rgmii_rx_if |
( |
input i_clk |
); |
////////////////////////////////////////////////////////////////////////////////// |
// |
localparam lp_MTU = 1500; |
// |
localparam lp_ETH_SFD_LEN = 8; // ...the corresponding hexadecimal representation is 0x55 0x55 0x55 0x55 0x55 0x55 0x55 0xD5. |
////////////////////////////////////////////////////////////////////////////////// |
// |
logic i_rxc; |
logic [ 3:0] iv_rxd; |
// |
bit [ 7:0] sv_rx_pkt[lp_MTU]; |
int sv_bpos; |
int sv_rx_len; |
// |
bit s_verbose; |
|
////////////////////////////////////////////////////////////////////////////////// |
// |
default clocking cb @(posedge i_clk or negedge i_clk); |
endclocking : cb |
|
////////////////////////////////////////////////////////////////////////////////// |
// |
task init(input i_verbose=0); |
// |
sv_bpos = 0; |
sv_rx_len = 0; |
s_verbose = i_verbose; |
// |
foreach(sv_rx_pkt[i]) |
sv_rx_pkt[i] = 0; |
// Final |
endtask : init |
|
task rx_pkt; |
// |
do @cb; |
while (i_rxc == 0); |
// |
sv_bpos = 0; |
sv_rx_len = 0; |
foreach(sv_rx_pkt[i]) |
sv_rx_pkt[i] = 0; |
// |
do begin : RX_PKT |
// |
if (sv_bpos == 0) |
begin |
sv_rx_pkt[sv_rx_len][3:0] = iv_rxd; |
sv_bpos = 1; |
end |
else |
begin |
sv_rx_pkt[sv_rx_len++][7:4] = iv_rxd; |
sv_bpos = 0; |
end |
// |
@cb; |
end while(i_rxc == 1); |
if (s_verbose) |
$display("[%t]: %m: rx-done", $time); |
// |
endtask : rx_pkt |
////////////////////////////////////////////////////////////////////////////////// |
// |
// |
// |
|
function int rx_pkt_len; |
return(sv_rx_len-lp_ETH_SFD_LEN); |
endfunction : rx_pkt_len |
|
function [7:0] rx_pkt_data(input int ii_idx); |
return(sv_rx_pkt[lp_ETH_SFD_LEN+ii_idx]); |
endfunction : rx_pkt_data |
|
////////////////////////////////////////////////////////////////////////////////// |
endinterface : rgmii_rx_if |
/trunk/hw/src/tb/bfm_host/eth_host_bfm.sv
0,0 → 1,344
////////////////////////////////////////////////////////////////////////////////// |
// Company: |
// Engineer: IK |
// |
// Create Date: 11:35:01 03/21/2013 |
// Design Name: |
// Module Name: eth_host_bfm |
// Project Name: |
// Target Devices: |
// Tool versions: |
// Description: |
// |
// DPC-C import: |
// -> 'test_bfm' / {net-adapt} |
// |
// DPI-C export: |
// |
// -> host_initial |
// -> host_delay |
// -> host_final |
// |
// -> eth_frm_read_len |
// -> eth_frm_read |
// |
// -> eth_frm_write_len |
// -> eth_frm_write |
// |
// Revision: |
// Revision 0.01 - File Created, |
// |
////////////////////////////////////////////////////////////////////////////////// |
`timescale 1ns / 1ps |
|
module eth_host_bfm #(parameter p_ETH_MTU = 1536) |
( |
// RSTi |
input i_arst, |
// RGMII-RX |
input i_rgmii_rx_clk, |
input i_rgmii_rx_ctrl, |
input [ 3:0] iv_rgmii_rxd, |
// RGMII-TX |
output logic o_rgmii_tx_clk, |
output logic o_rgmii_tx_ctrl, |
output logic [ 3:0] ov_rgmii_txd |
); |
////////////////////////////////////////////////////////////////////////////////// |
localparam lp_BQNTY = 8; |
////////////////////////////////////////////////////////////////////////////////// |
// eth-pkt record |
typedef struct { |
bit [7:0] data[]; |
int len; |
} packet_t; |
// mbox for eth-pkt |
typedef mailbox#(packet_t) pkt_mbox_t; |
////////////////////////////////////////////////////////////////////////////////// |
// PKT-mboxes / TX+RX parts |
pkt_mbox_t tx_pkt_mailbox = new(/*lp_BQNTY*/); |
pkt_mbox_t rx_pkt_mailbox = new(lp_BQNTY); |
// 4dbg-tx |
packet_t tx_pkt; |
int tx_pkt_idx; |
// 4dbg-rx |
packet_t rx_pkt; |
int rx_pkt_idx; |
|
bit [7:0] data0 [256]; |
int len0; |
|
// low-tx |
packet_t tx_pkt_low; |
bit [ 7:0] sv_rgmii_txd; |
int si_eth_tx_frm_cnt; |
// low-rx |
packet_t rx_pkt_low; |
bit [ 7:0] sv_rgmii_rxd; |
bit s_rgmii_rx_frm_end; |
int si_eth_rx_frm_cnt; |
|
////////////////////////////////////////////////////////////////////////////////// |
// |
// RGMII RX-TX Init |
// |
initial |
begin : INIT |
// tx-ctrl |
o_rgmii_tx_clk = 0; |
o_rgmii_tx_ctrl = 0; |
ov_rgmii_txd = 0; |
// pkt |
tx_pkt_low.data = new [p_ETH_MTU]; |
tx_pkt_low.len = -1; |
|
rx_pkt_low.data = new [p_ETH_MTU]; |
rx_pkt_low.len = -1; |
|
rx_pkt.data = new [p_ETH_MTU]; |
rx_pkt.len = -1; |
rx_pkt_idx = 0; |
|
tx_pkt_idx = 0; |
tx_pkt.data = new [p_ETH_MTU]; |
tx_pkt.len = -1; |
|
// init-data |
tx_pkt.data[0] = 8'h55; |
tx_pkt.data[1] = 8'h55; |
tx_pkt.data[2] = 8'h55; |
tx_pkt.data[3] = 8'h55; |
tx_pkt.data[4] = 8'h55; |
tx_pkt.data[5] = 8'h55; |
tx_pkt.data[6] = 8'h55; |
tx_pkt.data[7] = 8'hD5; |
|
// Final |
end |
////////////////////////////////////////////////////////////////////////////////// |
// |
// RGMII RX-TX Clocking |
// |
clocking cb_rx @(posedge i_rgmii_rx_clk); |
endclocking : cb_rx; |
|
clocking cb_tx @(posedge o_rgmii_tx_clk); |
endclocking : cb_tx; |
|
always |
begin : TX_CLK |
#(4ns) o_rgmii_tx_clk <= !o_rgmii_tx_clk; |
end |
|
////////////////////////////////////////////////////////////////////////////////// |
// |
// HDL RGMII |
// |
task run_tx; |
// |
forever |
eth_tx_frm(); |
// Final |
endtask : run_tx |
|
task run_rx; |
// |
forever |
eth_rx_frm(); |
// Final |
endtask : run_rx |
////////////////////////////////////////////////////////////////////////////////// |
// |
// RGMII-TX |
// |
task eth_tx_frm; |
// |
// |
@cb_tx; |
if (tx_pkt_mailbox.num()) |
begin : ETH_TX |
// init |
sv_rgmii_txd = 0; |
si_eth_tx_frm_cnt = 0; |
// get |
tx_pkt_mailbox.get(tx_pkt_low); |
// chk |
/*if ((tx_pkt_low.len + 8) < (64 + 8)) |
tx_pkt_low.len = 64;*/ |
// out |
do begin : OUT |
sv_rgmii_txd = tx_pkt_low.data[si_eth_tx_frm_cnt++]; |
write_byte(sv_rgmii_txd, (si_eth_tx_frm_cnt == (tx_pkt_low.len + 8))); |
end while (si_eth_tx_frm_cnt != (tx_pkt_low.len + 8)); |
end |
// Final |
endtask : eth_tx_frm |
|
task write_byte(input bit [7:0] iv_data, input bit i_final); |
// |
@(negedge o_rgmii_tx_clk); #2ns; |
o_rgmii_tx_ctrl <= 1; |
ov_rgmii_txd <= iv_data[3:0]; |
@(posedge o_rgmii_tx_clk); #2ns; |
ov_rgmii_txd <= iv_data[7:4]; |
if (i_final) |
begin : END |
@(negedge o_rgmii_tx_clk); #2ns; |
o_rgmii_tx_ctrl <= 0; |
ov_rgmii_txd <= 0; |
end |
// Final |
endtask : write_byte |
////////////////////////////////////////////////////////////////////////////////// |
// |
// RGMII-RX |
// |
task eth_rx_frm; |
// |
// wait for RXC rise |
do @(posedge i_rgmii_rx_clk or negedge i_rgmii_rx_clk); |
while(i_rgmii_rx_ctrl == 0); |
// init |
sv_rgmii_rxd = 0; |
s_rgmii_rx_frm_end = 0; |
si_eth_rx_frm_cnt = 0; |
// rx-proc |
do begin : RX |
read_byte((si_eth_rx_frm_cnt == 0), sv_rgmii_rxd, s_rgmii_rx_frm_end); |
if (!s_rgmii_rx_frm_end) |
begin : WRK |
if (si_eth_rx_frm_cnt > 7) // !=> cut {55, .., D5} here |
begin : WR_RX_PKT |
rx_pkt_low.data[(si_eth_rx_frm_cnt - 8)] = sv_rgmii_rxd; |
end |
si_eth_rx_frm_cnt++; |
end |
end while (s_rgmii_rx_frm_end == 0); |
s_rgmii_rx_frm_end = 0; |
rx_pkt_low.len = (si_eth_rx_frm_cnt - 8); $display("[%t]: %m: len=%x", $time, rx_pkt_low.len); |
rx_pkt_mailbox.put(rx_pkt_low); |
// final-dly |
@cb_rx; |
// Final |
endtask : eth_rx_frm |
|
task read_byte(input bit i_init, output bit [7:0] ov_data, output bit o_end); |
// init |
ov_data = -1; |
o_end = 0; |
// rx-dly |
if (i_init == 0) // 2nd, 3rd, .. starts |
@(posedge i_rgmii_rx_clk or negedge i_rgmii_rx_clk); // initial start - NO-DLY (eth_rx_frm -> 'wait for RXC rise') |
// lsb / prev detected RXC == 1 {RXEN-marker} |
ov_data[3:0] = iv_rgmii_rxd; |
// msb |
@(posedge i_rgmii_rx_clk or negedge i_rgmii_rx_clk); |
ov_data[7:4] = iv_rgmii_rxd; |
// frm-end chk |
if (i_rgmii_rx_ctrl == 0) |
o_end = 1; |
// Final |
endtask : read_byte |
////////////////////////////////////////////////////////////////////////////////// |
// |
// DPC-C routines |
// => GLBL |
// |
|
// DPI-C export / cpp-hdl |
export "DPI-C" task host_initial; |
export "DPI-C" task host_delay; |
export "DPI-C" task host_final; |
|
task host_initial; |
// |
do @cb_tx; // use our stable TX-CLK |
while (i_arst == 1); |
repeat(100) @cb_tx; |
$display("[%t]: %m: START", $time); |
// Final |
endtask : host_initial |
|
task host_delay(input int ii_value); |
// |
repeat(ii_value) |
@cb_tx; |
// Final |
endtask : host_delay |
|
task host_final; |
// |
repeat(10) @cb_tx; |
$finish;//$stop; |
// Final |
endtask : host_final |
|
|
// DPC-C import / MAIN |
import "DPI-C" context task test_bfm(); |
|
initial |
begin : MAIN_NET_ADAPT |
test_bfm(); |
end |
|
////////////////////////////////////////////////////////////////////////////////// |
// |
// DPC-C routines |
// => RGMII-RX |
// |
|
export "DPI-C" task eth_frm_read_len; |
export "DPI-C" task eth_frm_read; |
|
task eth_frm_read_len(output int ov_len); |
// |
@cb_rx; // !!! |
if (rx_pkt_mailbox.num()) |
begin : HAVE_RXD |
rx_pkt_mailbox.get(rx_pkt); |
ov_len = rx_pkt.len; |
rx_pkt_idx++; $display("[%t]: %m: len=%x", $time, rx_pkt.len); |
end |
else |
ov_len = -1; |
// Final |
endtask : eth_frm_read_len |
|
task eth_frm_read(output int ov_data, input int iv_position); |
// |
ov_data = rx_pkt.data[iv_position]; |
// Final |
endtask : eth_frm_read |
////////////////////////////////////////////////////////////////////////////////// |
// |
// DPC-C routines |
// => RGMII-TX |
// |
|
export "DPI-C" task eth_frm_write_len; // !=> init pkt-PUT |
export "DPI-C" task eth_frm_write; |
|
task eth_frm_write_len(input int iv_len); |
|
len0 = iv_len; |
for (int i = 0; i < iv_len; i++) begin data0[i] = tx_pkt.data[i]; end |
|
// put |
tx_pkt.len = iv_len; |
tx_pkt_mailbox.put(tx_pkt); |
// nxt-idx |
tx_pkt_idx++; |
// Final |
endtask : eth_frm_write_len; |
|
task eth_frm_write(input int iv_data, input int iv_position); |
// wr |
@cb_tx; // !!! |
tx_pkt.data[iv_position+8] = iv_data; |
// Final |
endtask : eth_frm_write |
|
|
////////////////////////////////////////////////////////////////////////////////// |
endmodule |
/trunk/hw/src/tb/bfm_ublaze/axi4_lite_master_bfm.sv
0,0 → 1,238
////////////////////////////////////////////////////////////////////////////////// |
// Company: ;) |
// Engineer: IK |
// |
// Create Date: 11:35:01 03/21/2013 |
// Design Name: |
// Module Name: axi4_lite_master_bfm |
// Project Name: |
// Target Devices: |
// Tool versions: |
// Description: |
// USAGE: |
// READ() |
// WRITE() |
// |
// |
// Revision: |
// Revision 0.01 - File Created, |
// |
////////////////////////////////////////////////////////////////////////////////// |
`timescale 1ns / 1ps |
|
module axi4_lite_master_bfm # |
( |
parameter p_ADDRESS_BUS_WIDTH = 32, |
parameter p_DATA_BUS_WIDTH = 32, |
parameter p_AXI4_LITE_PROT_BUS_WIDTH = 3, |
parameter p_AXI4_LITE_RESP_BUS_WIDTH = 2, |
parameter p_RESPONSE_TIMEOUT = 64 |
) |
( |
// SYS_CON |
input ACLK, |
input ARESETn, |
// |
// Write Address Channel Signals |
output logic [p_ADDRESS_BUS_WIDTH-1:0] AWADDR, // Master Write address |
output logic [p_AXI4_LITE_PROT_BUS_WIDTH-1:0] AWPROT, // Master Protection type |
output logic AWVALID,// Master Write address valid |
input AWREADY,// Slave Write address ready |
// Write Data Channel Signals |
output logic [p_DATA_BUS_WIDTH-1:0] WDATA, // Master Write data |
output logic [(p_DATA_BUS_WIDTH/8)-1:0] WSTRB, // Master Write strobes |
output logic WVALID, // Master Write valid |
input WREADY, // Slave Write ready |
// Write Response Channel Signals |
input [p_AXI4_LITE_RESP_BUS_WIDTH-1:0] BRESP, // Slave Write response |
input BVALID, // Slave Write response valid |
output logic BREADY, // Master Response ready |
// |
// Read Address Channel Signals |
output logic [p_ADDRESS_BUS_WIDTH-1:0] ARADDR, // Master Read address |
output logic [p_AXI4_LITE_PROT_BUS_WIDTH-1:0] ARPROT, // Master Protection type |
output logic ARVALID,// Master Read address valid |
input ARREADY,// Slave Read address ready |
// Read Data Channel Signals |
input [p_DATA_BUS_WIDTH-1:0] RDATA, // Slave Read data |
input [p_AXI4_LITE_RESP_BUS_WIDTH-1:0] RRESP, // Slave Read response |
input RVALID, // Slave Read valid |
output logic RREADY // Master Read ready |
); |
////////////////////////////////////////////////////////////////////////////////// |
// AXI-internals |
int timeout_counter; |
|
////////////////////////////////////////////////////////////////////////////////// |
// |
// BFM CLOCKING |
// |
default clocking cb @(posedge ACLK); |
input #1ns AWREADY, WREADY, BVALID; |
input #1ns ARREADY, RVALID, RDATA, RRESP; |
endclocking : cb |
////////////////////////////////////////////////////////////////////////////////// |
// |
// Initialize AXI-signals/internals |
// |
initial |
begin : INIT |
// axi-signals |
AWADDR = 0; |
AWPROT = 0; // !!! |
AWVALID = 0; |
WDATA = 0; |
WSTRB = 0; |
WVALID = 0; |
BREADY = 0; |
|
ARADDR = 0; |
ARPROT = 0; // !!! |
ARVALID = 0; |
RREADY = 0; |
// axi-internal |
timeout_counter = 0; |
// Final |
end |
////////////////////////////////////////////////////////////////////////////////// |
// |
// AXI4-LITE READ |
// |
task READ ( input [p_ADDRESS_BUS_WIDTH-1:0] iv_addr, |
output [p_DATA_BUS_WIDTH-1:0] ov_data, |
output [p_AXI4_LITE_RESP_BUS_WIDTH-1:0] ov_resp); |
// addr |
PROC_RADDR(iv_addr); |
// data |
PROC_RDATA(ov_data, ov_resp); |
// Final |
endtask : READ |
////////////////////////////////////////////////////////////////////////////////// |
// |
// AXI4-LITE WRITE |
// |
task WRITE (input [p_ADDRESS_BUS_WIDTH-1:0] iv_addr, |
input [p_DATA_BUS_WIDTH-1:0] iv_data, |
input [(p_DATA_BUS_WIDTH/8)-1:0] iv_be, |
output [p_AXI4_LITE_RESP_BUS_WIDTH-1:0] ov_resp); |
// addr |
PROC_WADDR(iv_addr); |
// data |
PROC_WDATA(iv_data, iv_be); |
// resp |
PROC_WRESP(ov_resp); |
// Final |
endtask : WRITE |
////////////////////////////////////////////////////////////////////////////////// |
// |
// SUPPORT: READ() |
// |
task PROC_RADDR(input [p_ADDRESS_BUS_WIDTH-1:0] iv_addr); |
// |
// #0 - Drive the Read Address Channel with ARVALID asserted |
ARADDR <= iv_addr; |
ARPROT <= 0; // !!!TBD |
ARVALID <= 1; |
// #1 - Wait for handshake on the next clk edge |
do begin @cb; end |
while (cb.ARREADY == 0); |
// #2 - de-assert ARVALID |
ARVALID <= 0; |
// #3 - clr on exit |
//ARADDR <= 0; |
ARPROT <= 0; @cb; |
// Final |
endtask : PROC_RADDR |
|
task PROC_RDATA(output [p_DATA_BUS_WIDTH-1:0] ov_data, output [p_AXI4_LITE_RESP_BUS_WIDTH-1:0] ov_resp); |
// |
// #0 - Drive RREADY and Wait for RVALID to be asserted |
timeout_counter = 0; |
RREADY <= 1; |
do begin : RDATA_RVALID |
@cb; |
// t-out check |
if (timeout_counter++ == p_RESPONSE_TIMEOUT) |
begin : TOUT |
$display("[%t]: %m: READ DATA transfer ERROR!!!", $time); |
$stop; |
end |
|
end while (cb.RVALID == 0); |
// #1 - sample RDATA and RRESP |
ov_data = cb.RDATA; |
ov_resp = cb.RRESP; |
// #2 - check RRESP |
if (ov_resp) // {RRESP_OK == 0} |
begin : RRESP |
$display("[%t]: %m: READ DATA transfer ERROR!!!", $time); |
$stop; |
end |
// #3 - if RRESP == OK, then de-assert RREADY |
RREADY <= 0; |
// Final |
endtask : PROC_RDATA |
////////////////////////////////////////////////////////////////////////////////// |
// |
// SUPPORT: WRITE() |
// |
task PROC_WADDR(input [p_ADDRESS_BUS_WIDTH-1:0] iv_addr); |
// |
// #0 - Drive the Write Address Channel with AWVALID asserted |
AWADDR <= iv_addr; |
AWPROT <= 0; // !!!TBD |
AWVALID <= 1; |
// #1 - Wait for handshake on the next clk edge |
@cb; |
while (cb.AWREADY == 0) @cb; |
// #2 - de-assert AWVALID |
AWVALID <= 0; |
// Final |
endtask : PROC_WADDR |
|
task PROC_WDATA(input [p_DATA_BUS_WIDTH-1:0] iv_data, input [(p_DATA_BUS_WIDTH/8)-1:0] iv_be); |
// |
// #0 - Drive the Write Data Channel with WVALID asserted |
WSTRB <= iv_be; |
WDATA <= iv_data; |
WVALID <= 1; |
// #1 - Wait for handshake on the next clk edge |
@cb; |
while (cb.WREADY == 0) @cb; |
// #2 - de-assert WVALID |
WVALID <= 0; |
// #3 - clr on exit |
//WSTRB <= 0; |
//WDATA <= 0; |
@cb; |
// Final |
endtask : PROC_WDATA |
|
task PROC_WRESP(output [p_AXI4_LITE_RESP_BUS_WIDTH-1:0] ov_resp); |
// |
// #0 - Drive BREADY and Wait for BVALID to be asserted |
timeout_counter = 0; |
BREADY <= 1; |
do begin : WRESP_BVALID |
@cb; |
// t-out check |
if (timeout_counter++ == p_RESPONSE_TIMEOUT) |
begin : TOUT |
$display("[%t]: %m: WRITE RESPONSE transfer ERROR!!!", $time); |
$stop; |
end |
end while(cb.BVALID == 0); |
// #1 - Sample the BRESP signal |
ov_resp = BRESP; |
// #2 - check RRESP |
if (ov_resp) // {BRESP_OK == 0} |
begin : RRESP |
$display("[%t]: %m: WRITE RESPONSE transfer ERROR!!!", $time); |
$stop; |
end |
// #3 - if BRESP == OK, then de-assert BREADY |
BREADY <= 0; |
// Final |
endtask : PROC_WRESP |
////////////////////////////////////////////////////////////////////////////////// |
endmodule |
/trunk/hw/src/tb/bfm_ublaze/base_microblaze_design_microblaze_0_0.sv
0,0 → 1,262
//ENTITY base_microblaze_design_microblaze_0_0 |
module base_microblaze_design_microblaze_0_0 |
( |
input Clk ,// IN STD_LOGIC; |
input Reset ,// IN STD_LOGIC; |
input Interrupt ,// IN STD_LOGIC; |
input [0:31] Interrupt_Address ,// IN STD_LOGIC_VECTOR(0 TO 31); |
output [0: 1] Interrupt_Ack ,// OUT STD_LOGIC_VECTOR(0 TO 1); |
output [0:31] Instr_Addr ,// OUT STD_LOGIC_VECTOR(0 TO 31); |
input [0:31] Instr ,// IN STD_LOGIC_VECTOR(0 TO 31); |
output IFetch ,// OUT STD_LOGIC; |
output I_AS ,// OUT STD_LOGIC; |
input IReady ,// IN STD_LOGIC; |
input IWAIT ,// IN STD_LOGIC; |
input ICE ,// IN STD_LOGIC; |
input IUE ,// IN STD_LOGIC; |
output [0:31] Data_Addr ,// OUT STD_LOGIC_VECTOR(0 TO 31); |
output [0:31] Data_Read ,// IN STD_LOGIC_VECTOR(0 TO 31); |
output [0:31] Data_Write ,// OUT STD_LOGIC_VECTOR(0 TO 31); |
output D_AS ,// OUT STD_LOGIC; |
output Read_Strobe ,// OUT STD_LOGIC; |
output Write_Strobe ,// OUT STD_LOGIC; |
input DReady ,// IN STD_LOGIC; |
input DWait ,// IN STD_LOGIC; |
input DCE ,// IN STD_LOGIC; |
input DUE ,// IN STD_LOGIC; |
output [0:3] Byte_Enable ,// OUT STD_LOGIC_VECTOR(0 TO 3); |
|
output [31:0] M_AXI_DP_AWADDR ,// OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
output [ 2:0] M_AXI_DP_AWPROT ,// OUT STD_LOGIC_VECTOR(2 DOWNTO 0); |
output M_AXI_DP_AWVALID ,// OUT STD_LOGIC; |
input M_AXI_DP_AWREADY ,// IN STD_LOGIC; |
output [31:0] M_AXI_DP_WDATA ,// OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
output [ 3:0] M_AXI_DP_WSTRB ,// OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
output M_AXI_DP_WVALID ,// OUT STD_LOGIC; |
input M_AXI_DP_WREADY ,// IN STD_LOGIC; |
input [ 1:0] M_AXI_DP_BRESP ,// IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
input M_AXI_DP_BVALID ,// IN STD_LOGIC; |
output M_AXI_DP_BREADY ,// OUT STD_LOGIC; |
output [31:0] M_AXI_DP_ARADDR ,// OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
output [ 2:0] M_AXI_DP_ARPROT ,// OUT STD_LOGIC_VECTOR(2 DOWNTO 0); |
output M_AXI_DP_ARVALID ,// OUT STD_LOGIC; |
input M_AXI_DP_ARREADY ,// IN STD_LOGIC; |
input [31:0] M_AXI_DP_RDATA ,// IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
input [ 1:0] M_AXI_DP_RRESP ,// IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
input M_AXI_DP_RVALID ,// IN STD_LOGIC; |
output M_AXI_DP_RREADY ,// OUT STD_LOGIC; |
|
input Dbg_Clk ,// IN STD_LOGIC; |
input Dbg_TDI ,// IN STD_LOGIC; |
output Dbg_TDO ,// OUT STD_LOGIC; |
output [0:7] Dbg_Reg_En ,// IN STD_LOGIC_VECTOR(0 TO 7); |
input Dbg_Shift ,// IN STD_LOGIC; |
input Dbg_Capture ,// IN STD_LOGIC; |
input Dbg_Update ,// IN STD_LOGIC; |
input Debug_Rst // IN STD_LOGIC |
); |
////////////////////////////////////////////////////////////////////////////////// |
// axi-req/resp def |
import bfm_ublaze_pkg::*; |
////////////////////////////////////////////////////////////////////////////////// |
// axi-req/resp mbox |
typedef mailbox#(mailbox_t) mbox_t; |
// ?? |
mbox_t axi_req_mailbox = new(1); |
mbox_t axi_resp_mailbox = new(1); |
int axi_trans_idx=0; |
|
////////////////////////////////////////////////////////////////////////////////// |
// |
// SYS-CLK |
// |
default clocking cb @(posedge Clk); |
endclocking : cb |
////////////////////////////////////////////////////////////////////////////////// |
// |
// AXI4-LITE MASTER BFM |
// |
axi4_lite_master_bfm // use DEFAULT-params |
U_AXI_BFM |
( |
// Global Clock Input. All signals are sampled on the rising edge. |
.ACLK (Clk), |
// Global Reset Input. Active Low. |
.ARESETn (!Reset), |
|
// Write Address Channel Signals |
.AWADDR (M_AXI_DP_AWADDR), // Master Write address |
.AWPROT (M_AXI_DP_AWPROT), // Master Protection type |
.AWVALID (M_AXI_DP_AWVALID), // Master Write address valid |
.AWREADY (M_AXI_DP_AWREADY), // Slave Write address ready |
|
// Write Data Channel Signals |
.WDATA (M_AXI_DP_WDATA), // Master Write data |
.WSTRB (M_AXI_DP_WSTRB), // Master Write strobes |
.WVALID (M_AXI_DP_WVALID), // Master Write valid |
.WREADY (M_AXI_DP_WREADY), // Slave Write ready |
|
// Write Response Channel Signals |
.BRESP (M_AXI_DP_BRESP), // Slave Write response |
.BVALID (M_AXI_DP_BVALID), // Slave Write response valid |
.BREADY (M_AXI_DP_BREADY), // Master Response ready |
|
// Read Address Channel Signals |
.ARADDR (M_AXI_DP_ARADDR), // Master Read address |
.ARPROT (M_AXI_DP_ARPROT), // Master Protection type |
.ARVALID (M_AXI_DP_ARVALID), // Master Read address valid |
.ARREADY (M_AXI_DP_ARREADY), // Slave Read address ready |
|
// Read Data Channel Signals |
.RDATA (M_AXI_DP_RDATA), // Slave Read data |
.RRESP (M_AXI_DP_RRESP), // Slave Read response |
.RVALID (M_AXI_DP_RVALID), // Slave Read valid |
.RREADY (M_AXI_DP_RREADY) // Master Read ready |
); |
////////////////////////////////////////////////////////////////////////////////// |
// |
// uBLAZE internal AXI logic |
// |
|
initial |
begin : AXI_LOGIC |
// proc axi-req |
forever |
begin : WRK |
@cb; proc_axi_req(); |
end |
end |
|
task proc_axi_req; |
// declare |
mailbox_t axi_req; |
mailbox_t axi_resp; |
logic [1:0] responce; |
int sv_data; |
// chk-req |
if (axi_req_mailbox.num()) // req-posted by nios2-sw |
begin : WRK |
// get-req |
axi_req_mailbox.get(axi_req); |
// proc-cmd |
if (axi_req.trans == READ) |
U_AXI_BFM.READ(axi_req.trans_param.addr, sv_data, responce); |
else // axi_req.trans == WRITE |
U_AXI_BFM.WRITE(axi_req.trans_param.addr, axi_req.trans_param.data, axi_req.trans_param.be, responce); |
// cre resp |
axi_resp.trans = axi_req.trans; |
axi_resp.trans_idx = axi_req.trans_idx; |
axi_resp.trans_param.addr = axi_req.trans_param.addr; |
axi_resp.trans_param.be = axi_req.trans_param.be; |
axi_resp.trans_param.data = (axi_req.trans == READ)? (sv_data) : (-1); |
// post resp |
axi_resp_mailbox.put(axi_resp); |
end |
// Final |
endtask : proc_axi_req |
////////////////////////////////////////////////////////////////////////////////// |
// |
// C/CPP-MAIN / uBLAZE-SW |
// |
|
// DPC-C import / MAIN |
import "DPI-C" context task main(); |
|
initial |
begin : MAIN |
main(); |
end |
////////////////////////////////////////////////////////////////////////////////// |
// |
// CPP-HDL AXI routines |
// |
|
// DPI-C export / AXI |
export "DPI-C" task axi_read; |
export "DPI-C" task axi_write; |
|
task automatic axi_read (input int iv_addr, input int iv_be, output int ov_data); |
// declare |
mailbox_t rd_req; |
mailbox_t rd_resp; |
// init-req |
rd_req.trans = READ; |
rd_req.trans_idx = ++axi_trans_idx; |
rd_req.trans_param.addr = iv_addr; |
rd_req.trans_param.be = iv_be; |
rd_req.trans_param.data = -1; |
// post-req |
axi_req_mailbox.put(rd_req); // method places a message in a mailbox |
// wait |
do begin : WAIT_RD_RESP |
// prep |
rd_resp.trans_idx = 0; @cb; |
// chk resp |
if (axi_resp_mailbox.num()) // obtain number of messages in a mailbox |
axi_resp_mailbox.peek(rd_resp); // copies a message from a mailbox without removing the message from the queue. |
end while(rd_resp.trans_idx != rd_req.trans_idx); |
// get rd-data |
axi_resp_mailbox.get(rd_resp); // retrieves a message from a mailbox |
ov_data = rd_resp.trans_param.data; |
//$display("[%t]: %m: iv_addr=%x, ov_data=%x", $time, iv_addr, ov_data); |
// Final |
endtask : axi_read |
|
task automatic axi_write (input int iv_addr, input int iv_be, input int iv_data); |
// declare |
mailbox_t wr_req; |
mailbox_t wr_resp; |
// init |
wr_req.trans = WRITE; |
wr_req.trans_idx = ++axi_trans_idx; |
wr_req.trans_param.addr = iv_addr; |
wr_req.trans_param.be = iv_be; |
wr_req.trans_param.data = iv_data; |
// post-req |
axi_req_mailbox.put(wr_req); |
// wait |
do begin : WAIT_WR_RESP |
// prep |
wr_resp.trans_idx = 0; @cb; |
// chk resp |
if (axi_resp_mailbox.num()) |
axi_resp_mailbox.peek(wr_resp); |
end while (wr_resp.trans_idx != wr_req.trans_idx); |
axi_resp_mailbox.get(wr_resp); // dummy-read REQ!!! |
// Final |
endtask : axi_write |
////////////////////////////////////////////////////////////////////////////////// |
// |
// CPP-HDL sync |
// |
|
// DPI-C export / cpp-hdl |
export "DPI-C" task ublaze_initial; |
export "DPI-C" task ublaze_final; |
export "DPI-C" task ublaze_wait; |
|
task ublaze_initial; |
// |
do @cb; |
while (Reset == 1); |
##100; |
$display("[%t]: %m: START", $time); |
// Final |
endtask : ublaze_initial |
|
task ublaze_final; |
// |
##100; |
$display("[%t]: %m: STOP", $time); |
$finish; |
// Final |
endtask : ublaze_final |
|
task ublaze_wait(input int iv_value); |
// simple-bfm-dly |
repeat(iv_value) |
@cb; |
// Final |
endtask : ublaze_wait |
////////////////////////////////////////////////////////////////////////////////// |
endmodule |
/trunk/hw/src/tb/bfm_ublaze/bfm_ublaze_pkg.sv
0,0 → 1,40
////////////////////////////////////////////////////////////////////////////////// |
// Company: |
// Engineer: IK |
// |
// Create Date: 11:35:01 03/21/2013 |
// Design Name: |
// Module Name: bfm_ublaze_pkg |
// Project Name: |
// Target Devices: |
// Tool versions: |
// Description: |
// |
// |
// Revision: |
// Revision 0.01 - File Created, |
// |
////////////////////////////////////////////////////////////////////////////////// |
|
package bfm_ublaze_pkg; |
////////////////////////////////////////////////////////////////////////////////// |
// |
typedef enum { |
READ, |
WRITE |
} trans_t; |
|
typedef struct { |
int addr; |
int be; |
int data; // in-write => in case of {axi-trans == AXI-WRITE} / out-read => in case of {axi-trans == AXI-READ} |
} trans_param_t; |
|
typedef struct { |
trans_t trans; // type |
int trans_idx; // idx |
trans_param_t trans_param; // io-param |
} mailbox_t; |
|
////////////////////////////////////////////////////////////////////////////////// |
endpackage : bfm_ublaze_pkg |
/trunk/hw/src/tb/tb.sv
0,0 → 1,165
////////////////////////////////////////////////////////////////////////////////// |
// Company: |
// Engineer: IK |
// |
// Create Date: 11:35:01 03/21/2013 |
// Design Name: |
// Module Name: tb |
// Project Name: |
// Target Devices: |
// Tool versions: |
// Description: |
// |
// |
// Revision: |
// Revision 0.01 - File Created, |
// |
////////////////////////////////////////////////////////////////////////////////// |
`timescale 1ns / 1ps |
|
module tb; |
////////////////////////////////////////////////////////////////////////////////// |
// |
parameter p_Tclk = 5ns; // 50MHz |
parameter p_Trst = 120ns; |
// Eth MTU |
parameter p_ETH_MTU = 8*1024; // Jumbo frame |
|
////////////////////////////////////////////////////////////////////////////////// |
// SYS_CON |
reg s_sys_clk; |
reg s_eth_clk; |
reg s_rst; |
// TSE-MDIO |
wire s_tse_mdio; |
// TSE-RGMII |
wire s_tse_rx_clk_i; |
wire s_tse_rx_ctrl_i; |
wire [ 3:0] sv_tse_rxd_i; |
|
wire s_tse_tx_clk_o; |
wire s_tse_tx_ctrl_o; |
wire [ 3:0] sv_tse_txd_o; |
|
////////////////////////////////////////////////////////////////////////////////// |
// |
// |
// |
always |
begin : SYS_CLK |
#(p_Tclk / 2.0) s_sys_clk <= !s_sys_clk; |
end |
|
always |
begin : ETH_CLK |
#(8ns / 2.0) s_eth_clk <= !s_eth_clk; |
end |
|
initial |
begin : init_POR |
// |
|
// clr |
s_sys_clk = 0; |
s_eth_clk = 0; |
s_rst = 0; |
|
// Final |
end |
////////////////////////////////////////////////////////////////////////////////// |
// |
// Instantiate DUT |
// |
microb_top dut |
( |
// SYS_CON |
.glbl_rst (s_rst), |
.sys_diff_clock_clk_n (!s_sys_clk), // 200MHz clock input from board |
.sys_diff_clock_clk_p ( s_sys_clk), |
// LED |
.led_8bits_tri_o (), |
// UART |
.rs232_uart_rxd (1'b1), |
.rs232_uart_txd (), |
// PHY rst |
.phy_resetn (), |
// RGMII Interface |
.rgmii_txd (sv_tse_txd_o), |
.rgmii_tx_ctl (s_tse_tx_ctrl_o), |
.rgmii_txc (s_tse_tx_clk_o), |
.rgmii_rxd (sv_tse_rxd_i), |
.rgmii_rx_ctl (s_tse_rx_ctrl_i), |
.rgmii_rxc (s_tse_rx_clk_i), |
// MDIO Interface |
.mdio (s_tse_mdio), |
.mdc () |
|
); |
////////////////////////////////////////////////////////////////////////////////// |
// |
// ETH-PHY-MDIO BFM / ;) |
// |
pullup (s_tse_mdio); |
|
////////////////////////////////////////////////////////////////////////////////// |
// |
// HOST BFM |
// |
eth_host_bfm #(2*1024) // p_ETH_MTU |
U_HOST_BFM |
( |
// RSTi |
.i_arst (s_tse_rst_n), |
// RGMII-RX |
.i_rgmii_rx_clk (s_tse_tx_clk_o), |
.i_rgmii_rx_ctrl (s_tse_tx_ctrl_o), |
.iv_rgmii_rxd (sv_tse_txd_o), |
// RGMII-TX |
.o_rgmii_tx_clk (s_tse_rx_clk_i), |
.o_rgmii_tx_ctrl (s_tse_rx_ctrl_i), |
.ov_rgmii_txd (sv_tse_rxd_i) |
); |
initial |
begin : HOST_BFM_RUN |
#(p_Trst); |
fork |
U_HOST_BFM.run_tx(); |
U_HOST_BFM.run_rx(); |
join_none |
end |
////////////////////////////////////////////////////////////////////////////////// |
// |
// ETH logger / PCAP |
// |
rgmii_rx_if U_RGMII_RX (U_HOST_BFM.i_rgmii_rx_clk); // U_HOST_BFM-rx |
assign U_RGMII_RX.i_rxc = U_HOST_BFM.i_rgmii_rx_ctrl; |
assign U_RGMII_RX.iv_rxd = U_HOST_BFM.iv_rgmii_rxd; |
|
rgmii_rx_if U_RGMII_TX (U_HOST_BFM.o_rgmii_tx_clk); // U_HOST_BFM-tx |
assign U_RGMII_TX.i_rxc = U_HOST_BFM.o_rgmii_tx_ctrl; |
assign U_RGMII_TX.iv_rxd = U_HOST_BFM.ov_rgmii_txd; |
|
`include "bfm_eth_log_cl.sv" |
bfm_eth_log_cl s_bfm_eth_log; |
initial |
begin : ETH_LOG_INIT |
s_bfm_eth_log = new("elog_hrx", U_RGMII_RX, U_RGMII_TX); |
s_bfm_eth_log.init(); ##10; |
s_bfm_eth_log.log_run(); |
end |
////////////////////////////////////////////////////////////////////////////////// |
// |
// TB Tasks |
// |
task dut_arst; |
// simple async |
s_rst <= 1; #(p_Tclk); |
s_rst <= 0; |
// Final |
endtask : dut_arst |
|
default clocking cb @(s_sys_clk); |
endclocking : cb |
|
////////////////////////////////////////////////////////////////////////////////// |
endmodule |
/trunk/hw/src/tc/testcase.sv
0,0 → 1,48
////////////////////////////////////////////////////////////////////////////////// |
// Company: |
// Engineer: IK |
// |
// Create Date: 11:35:01 03/21/2013 |
// Design Name: |
// Module Name: testcase |
// Project Name: |
// Target Devices: |
// Tool versions: |
// Description: |
// |
// |
// Revision: |
// Revision 0.01 - File Created, |
// |
////////////////////////////////////////////////////////////////////////////////// |
`timescale 1ns / 1ps |
|
module testcase; |
////////////////////////////////////////////////////////////////////////////////// |
|
////////////////////////////////////////////////////////////////////////////////// |
// |
// Instantiate TB |
// |
tb tb(); |
|
////////////////////////////////////////////////////////////////////////////////// |
// |
// |
// |
initial |
begin : TC |
// init-msg |
$display("[%t]: %m: START", $time); |
// init-clr |
tb.dut_arst(); |
|
// proc |
#500ms; |
// Final |
#1us; |
$display("[%t]: %m: STOP", $time); |
$finish; |
end |
////////////////////////////////////////////////////////////////////////////////// |
endmodule |
/trunk/sw/app/gtest/Makefile
0,0 → 1,46
# |
# makefile |
# |
|
TARGET = gtest_vtest |
|
all: $(TARGET) |
|
CC = g++ -xc |
CPP= g++ -xc++ |
LD = g++ |
OBJDUMP = objdump |
DEFAULT_CP := cp -f |
DEFAULT_MKDIR := mkdir -p |
DEFAULT_RM := rm -rf |
LIBRARIES := -lgtest -lpthread -L../src -lethlc |
|
INCDIR := ./ \ |
../src |
INCLUDE := $(addprefix -I, $(INCDIR)) |
CFLAGS += -g |
CFLAGS += $(INCLUDE) |
|
OBJ_DIR = obj |
OBJECTS = gtest_unittest.o \ |
gtest_0.o \ |
gtest_1.o |
|
OBJ_FILES := $(addprefix $(OBJ_DIR)/, $(OBJECTS)) |
|
$(TARGET): prep $(OBJ_FILES) |
$(LD) $(LFLAGS) -o $(TARGET) $(OBJ_FILES) $(LIBRARIES) |
@echo DONE: app |
|
$(OBJ_DIR)/%.o: %.cpp |
$(CPP) -c $(CFLAGS) -o $@ $< |
|
prep: |
make all -C ../src |
$(DEFAULT_RM) $(OBJ_DIR) |
$(DEFAULT_MKDIR) $(OBJ_DIR) |
|
clean: |
make clean -C ../src |
$(DEFAULT_RM) $(OBJ_DIR) |
$(DEFAULT_RM) $(TARGET) |
/trunk/sw/app/gtest/gtest_0.cpp
0,0 → 1,32
#include <gtest/gtest.h> |
#include <string> |
|
#include "ethlc.hpp" |
|
//TEST_F(TestDev, test_0) |
TEST(TestDev, test_0) |
{ |
// dec vars |
std::string dev_addr; |
std::string details; |
bool result; |
|
// prep CORRECT ipv4-addr |
dev_addr = "192.168.43.5"; // ..\vtest\sw\dev\test_main\src\main\test_main.c |
|
// proc |
try { |
// ?? |
ethlc dev(dev_addr); // auto-destr later / -> leave visibility-region |
|
// proc |
result = dev.ethlc_proc(); |
dev.ethlc_gdet(details); |
ASSERT_EQ(result, true) << std::endl << details; |
} |
catch (int val) { |
FAIL() << "-> ethlc-init problem#0" << std::endl; |
} |
|
// Final |
} |
/trunk/sw/app/gtest/gtest_1.cpp
0,0 → 1,27
#include <gtest/gtest.h> |
#include <string> |
|
#include "ethlc.hpp" |
|
//TEST_F(TestDev, test_1) |
TEST(TestDev, test_1) |
{ |
// dec vars |
std::string dev_addr; |
std::string details; |
bool result; |
|
// prep WRONG ipv4-addr |
dev_addr = "192.168.43.6"; |
|
// proc |
try { |
ethlc dev(dev_addr); |
// if there are here == ERR |
FAIL() << "-> ethlc-init problem#1" << std::endl; |
} |
catch (int val) { // no device found == OK |
SUCCEED(); |
} |
// Final |
} |
/trunk/sw/app/gtest/gtest_unittest.cpp
0,0 → 1,7
#include <stdio.h> |
#include "gtest/gtest.h" |
|
int main(int argc, char **argv) { |
testing::InitGoogleTest(&argc, argv); |
return RUN_ALL_TESTS(); |
} |
/trunk/sw/app/src/Makefile
0,0 → 1,43
# |
# makefile |
# |
|
# |
# TBD |
# |
|
TARGET = libethlc.a |
|
all: $(TARGET) |
|
CC = g++ -xc |
CPP= g++ -xc++ |
LD = g++ |
AR = ar cqs |
DEFAULT_CP := cp -f |
DEFAULT_MKDIR := mkdir -p |
DEFAULT_RM := rm -rf |
|
INCDIR := ./ |
|
INCLUDE := $(addprefix -I, $(INCDIR)) |
CFLAGS := -g |
CFLAGS += $(INCLUDE) |
|
OBJ_DIR := obj |
OBJECTS := ethlc.o |
OBJ_FILES := $(addprefix $(OBJ_DIR)/, $(OBJECTS)) |
|
$(OBJ_DIR)/%.o: %.cpp |
$(CPP) -c $(CFLAGS) -o $@ $< |
|
$(TARGET): prep $(OBJ_FILES) |
$(AR) $(TARGET) $(OBJ_FILES) |
@echo DONE: AR |
|
prep: clean |
$(DEFAULT_MKDIR) $(OBJ_DIR) |
|
clean: |
$(DEFAULT_RM) $(OBJ_DIR) |
$(DEFAULT_RM) $(TARGET) |
/trunk/sw/app/src/ethlc.cpp
0,0 → 1,116
#include "ethlc.hpp" |
|
/** |
* @brief private: Execute Generic Shell Command |
* |
* @param[in] command Command to execute. |
* @param[out] output Shell output. |
* @param[in] mode read/write access |
* |
* @return 0 for success, 1 otherwise. |
* |
*/ |
bool ethlc::exec_shell_cmd( const std::string& command, |
std::string& output, |
const std::string& mode = "r") |
{ |
// Create the stringstream |
std::stringstream sout; |
// Run Popen |
FILE *in; |
char buff[512]; |
// Test output |
if(!(in = popen(command.c_str(), mode.c_str()))){ |
return 1; |
} |
// Parse output |
while(fgets(buff, sizeof(buff), in)!=NULL){ |
sout << buff; |
} |
// Close |
int exit_code = pclose(in); |
// set output |
output = sout.str(); |
// Return exit code |
return exit_code; |
} |
|
|
|
/** |
* @brief public: Open-dev / class-constr / |
* |
* @param[in] address dev IPv4-addr |
* |
* @return 0 for success, 1 otherwise. |
* |
*/ |
ethlc::ethlc(const std::string& addr) |
{ |
// dec vars |
int code_sim, code_hw; |
std::string command; |
std::string details_sim, details_hw; |
|
// record addr |
address = addr; |
|
// ARPING it / sim |
command = "arping -c 1 " + address + " -I tap0"+ " 2>&1"; // !!!redirecting stderr to stdout |
code_sim = exec_shell_cmd(command, details_sim); |
|
// ARPING it / hw |
command = "arping -c 1 " + address + " -I eth0"+ " 2>&1"; // .. |
code_hw = exec_shell_cmd(command, details_hw); |
|
// final deal |
if ((code_hw != 0) && (code_sim != 0)) { // no device found |
std::cout << "no device found - 'ethlc::ethlc'" << std::endl; |
throw 7; |
} else { |
// if we are here - OK |
if (code_hw == -1) { |
details = details_sim; |
} else { |
details = details_hw; |
} |
} |
} |
|
/** |
* @brief public: Close-dev / class-destr / |
* |
* @return 0 for success, 1 otherwise. |
* |
*/ |
ethlc::~ethlc() |
{ |
// placeholder |
} |
|
|
/** |
* @brief public: Work with dev |
* |
* @return 0 for success, 1 otherwise. |
* |
*/ |
bool ethlc::ethlc_proc(void) |
{ |
// just PING it / ;) |
std::string command = "ping -c 1 " + address + " 2>&1"; // !!!redirecting stderr to stdout |
int code = exec_shell_cmd(command, details); |
return (code == 0); |
} |
|
|
/** |
* @brief public: Out2usr detailes of shell output |
* |
* @param[out] output Shell output. |
* |
*/ |
void ethlc::ethlc_gdet(std::string& pdetails) |
{ |
pdetails = details; |
} |
/trunk/sw/app/src/ethlc.hpp
0,0 → 1,30
#ifndef _ETHLC_HPP_ |
#define _ETHLC_HPP_ |
|
#include <cstdio> |
#include <iostream> |
#include <sstream> |
#include <string> |
|
class ethlc { |
public: |
|
ethlc(const std::string& addr); // contr+init |
virtual ~ethlc(); |
|
bool ethlc_proc(void); |
void ethlc_gdet(std::string& pdetails); |
|
private: |
// PROC: |
ethlc(); // 'hide' std-constr |
|
bool exec_shell_cmd(const std::string& command, |
std::string& output, |
const std::string& mode); |
// DATA: |
std::string address; |
std::string details; |
}; |
|
#endif // _ETHLC_HPP_ |
/trunk/sw/dev/test_bfm/dpi/eth_host_bfm.h
0,0 → 1,50
/* MTI_DPI */ |
#ifndef INCLUDED_ETH_HOST_BFM |
#define INCLUDED_ETH_HOST_BFM |
|
#ifdef __cplusplus |
#define DPI_LINK_DECL extern "C" |
#else |
#define DPI_LINK_DECL |
#endif |
|
#include "svdpi.h" |
|
// |
// test-bfm / used in hdl-backend for Lin-tap IF |
DPI_LINK_DECL DPI_DLLESPEC |
int |
test_bfm(); |
// |
// BFM ETH READ, from HDL |
DPI_LINK_DECL int |
eth_frm_read_len( |
int* ov_len); |
|
DPI_LINK_DECL int |
eth_frm_read( |
int* ov_data, |
int iv_position); |
// |
// BFM ETH WRITE, to HDL |
DPI_LINK_DECL int |
eth_frm_write_len( |
int iv_len); |
|
DPI_LINK_DECL int |
eth_frm_write( |
int iv_data, |
int iv_position); |
// |
// CPP-HDL sync |
DPI_LINK_DECL int |
host_initial(); |
|
DPI_LINK_DECL int |
host_delay( |
int iv_data); |
|
DPI_LINK_DECL int |
host_final(); |
|
#endif // INCLUDED_ETH_HOST_BFM |
/trunk/sw/dev/test_bfm/ether/crc_ether.c
0,0 → 1,60
////////////////////////////////////////////////////////////////////////////////// |
#include <stdlib.h> |
#include <stdio.h> |
|
////////////////////////////////////////////////////////////////////////////////// |
|
// AUTODIN II, Ethernet, & FDDI |
#define CRC32_POLY 0x04c11db7 |
|
// Generating polynomial: |
typedef unsigned int uint32_t; |
typedef unsigned char u8_t; |
const uint32_t ethernet_polynomial_le = 0xedb88320U; |
////////////////////////////////////////////////////////////////////////////////// |
|
long crc_ether(char *buf, int len) { // Ethernet FCS, 32bit |
int length; u8_t *data; int foxes; |
length = len; |
data = buf; |
foxes = 1; |
|
unsigned int crc = (foxes) ? 0xffffffff: 0; /* Initial value. */ |
while(--length >= 0) |
{ |
unsigned char current_octet = *data++; |
int bit; |
// printf("%02X, %08X, inv %08X\n", current_octet, crc, ~crc); |
|
for (bit = 8; --bit >= 0; current_octet >>= 1) { |
if ((crc ^ current_octet) & 1) { |
crc >>= 1; |
crc ^= ethernet_polynomial_le; |
} else |
crc >>= 1; |
} |
} |
return ~crc; |
} |
|
/* |
The CRC algorithm implementation by C language is as follows: This algorithm is often used as the Ethernet FCS(Frame Check Sequence). |
|
#define CRCPOLY2 0xEDB88320UL // left-right reversal |
|
static unsigned long crc2(int n, unsigned char c[]) |
{ |
int i, j; |
unsigned long r; |
|
r = 0xFFFFFFFFUL; |
for (i = 0; i < n; i++) { |
r ^= c[i]; |
for (j = 0; j < CHAR_BIT; j++) |
if (r & 1) r = (r >> 1) ^ CRCPOLY2; |
else r >>= 1; |
} |
return r ^ 0xFFFFFFFFUL; |
} |
*/ |
////////////////////////////////////////////////////////////////////////////////// |
/trunk/sw/dev/test_bfm/ether/crc_ip.c
0,0 → 1,46
////////////////////////////////////////////////////////////////////////////////// |
#include <stdlib.h> |
#include <stdio.h> |
|
////////////////////////////////////////////////////////////////////////////////// |
|
unsigned short crc_ip(void * ptr, unsigned count) |
{ |
unsigned short checksum; |
unsigned short * addr = (unsigned short *)ptr; |
|
/********** code from rfc1071 **********/ |
{ |
/* Compute Internet Checksum for "count" bytes |
* beginning at location "addr". |
*/ |
|
long sum = 0; |
count += count; /* make passed word count into byte count */ |
|
while( count > 1 ) |
{ |
/* This is the inner loop */ |
sum += *addr++; |
count -= 2; |
} |
|
/* Add left-over byte, if any */ |
if( count > 0 ) |
sum += * (unsigned char *) addr; |
|
/* Fold 32-bit sum to 16 bits */ |
while (sum>>16) |
sum = (sum & 0xffff) + (sum >> 16); |
|
// curr CRC realisation expects to do the final 1s complement of the checksum in the raw-code |
checksum = (unsigned short)sum; |
// or? |
//checksum = ~sum; |
} |
/******** end of RFC 1071 code **********/ |
|
return checksum; |
} |
|
////////////////////////////////////////////////////////////////////////////////// |
/trunk/sw/dev/test_bfm/ether/ether.h
0,0 → 1,96
#ifndef _ETHER_H_ |
#define _ETHER_H_ |
|
|
#ifdef __cplusplus |
extern "C" |
{ |
#endif// __cplusplus |
|
// net-order macros |
#define lswap(x) ((((x) & 0xff000000) >> 24) | \ |
(((x) & 0x00ff0000) >> 8) | \ |
(((x) & 0x0000ff00) << 8) | \ |
(((x) & 0x000000ff) << 24)) |
#define htonl(l) (lswap(l)) |
#define ntohl(l) (lswap(l)) |
#define htons(s) ((((s) >> 8) & 0xff) | \ |
(((s) << 8) & 0xff00)) |
#define ntohs(s) htons(s) |
|
// prep IP-addr for PRINT |
#define PUSH_IPADDR(ip)\ |
(unsigned)(ip&0xff),\ |
(unsigned)((ip>>8)&0xff),\ |
(unsigned)((ip>>16)&0xff),\ |
(unsigned)(ip>>24) |
// |
#define ETH_PKT_MAC_ADDR_LEN (6) |
#define ETH_PKT_IP_ADDR_LEN (4) |
#define ETH_HDR_LEN (ETH_PKT_MAC_ADDR_LEN + ETH_PKT_MAC_ADDR_LEN + 2) // ..+ pkt_type |
#define ETH_IPv4_HDR_LEN (20) // -> 20 Bytes |
// TU-val |
#define ETH_MIN_TU (60) |
#define ETH_MAX_TU (1500) // Eth MTU |
// ETH# |
#define ETH_PKT_ARP ntohs(0x0806) |
#define ETH_PKT_IPv4 ntohs(0x0800) |
#define ETH_PKT_IPv6 ntohs(0x86dd) |
// IPv4# |
#define IPv4_ICMP 0x01 |
#define IPv4_IGMP 0x02 |
#define IPv4_TCP 0x06 |
#define IPv4_UDP 0x11 |
#define IPv4_RDP 0x1B |
#define IPv4_IRTP 0x1C |
#define IPv4_IPv6Encaps 0x29 |
#define IPv4_IPv6Route 0x2B |
#define IPv4_IPv6Frag 0x2C |
#define IPv4_VISA 0x46 |
#define IPv4_QNX 0x6A |
#define IPv4_SMP 0x79 |
#define IPv4_SCTP 0x84 |
#define IPv4_UDPLite 0x88 |
|
|
|
|
// |
typedef unsigned short u16; |
typedef unsigned int ip_addr; |
// |
typedef struct { |
char ip_ver_ihl; // 4 bit version, 4 bit hdr len in 32bit words |
char ip_tos; // Type of Service, RFC 2474 -> {DSCP[5:0], ECN[1:0]} |
u16 ip_len; // Total packet length including header |
u16 ip_id; // ID for fragmentation |
u16 ip_flgs_foff; // mask in flags as needed |
unsigned char ip_time; // Time to live (secs) |
char ip_prot; // protocol |
u16 ip_chksum; // Header checksum |
ip_addr ip_src; // Source Addr |
ip_addr ip_dest; // Destination Addr |
} ip_hdr_t; |
// |
typedef struct |
{ |
u16 ud_srcp; /* source port */ |
u16 ud_dstp; /* dest port */ |
u16 ud_len; /* length of UDP packet */ |
u16 ud_cksum; /* UDP checksum */ |
} udp_hdr_t; |
|
|
|
// tx |
void ether_tx(char *ibuff, int ilen); |
// rx |
int ether_rx_ok(void); |
void ether_rx(char *obuff, int *olen); |
|
|
#ifdef __cplusplus |
} |
#endif// __cplusplus |
|
#endif // _ETHER_H_ |
/trunk/sw/dev/test_bfm/ether/ether_rx.c
0,0 → 1,63
////////////////////////////////////////////////////////////////////////////////// |
#include <stdlib.h> |
#include <stdio.h> |
|
#include "ether.h" // ETH_PKT_MAC_ADDR_LEN, .. |
#include "eth_host_bfm.h" // eth_frm_read_wait, .. |
|
////////////////////////////////////////////////////////////////////////////////// |
// PKT-LEN |
int pkt_len; |
////////////////////////////////////////////////////////////////////////////////// |
// |
// Ethernet RX routine |
// |
|
int ether_rx_ok(void) |
{ |
eth_frm_read_len(&pkt_len); |
return(pkt_len != -1); |
} |
|
void ether_rx(char *obuff, int *olen) // !!!only after 'ether_rx_ok' + 'obuff' must be pre-allocated |
{ |
// dec vars |
int i, pkt_data; |
// proc |
*olen = pkt_len; |
for (i = 0; i < pkt_len; i++) { |
eth_frm_read(&pkt_data, i); |
*(obuff+i) = pkt_data; |
} |
// msg2usr |
unsigned short pkt_type = *((unsigned short *)((obuff)+ETH_PKT_MAC_ADDR_LEN*2)); |
switch(pkt_type) { |
case ETH_PKT_ARP : { |
printf("ether_rx: ETH_PKT_ARP, len=%04x\n", pkt_len); |
break; |
} |
case ETH_PKT_IPv4 : { |
ip_hdr_t *ptr_ipv4_hdr = (ip_hdr_t *)(obuff+ETH_HDR_LEN); |
switch(ptr_ipv4_hdr->ip_prot) { |
case IPv4_ICMP : { |
printf("ether_rx: ETH_PKT_IPv4-ICMP, len=%04x\n", pkt_len); |
break; |
} |
case IPv4_UDP : { |
printf("ether_rx: ETH_PKT_IPv4-UDP, len=%04x\n", pkt_len); |
break; |
} |
default : { |
printf("ether_rx: ETH_PKT_IPv4: IP protocol number = %x, len=%04x\n", ptr_ipv4_hdr->ip_prot, pkt_len); |
break; |
} |
} |
break; |
} |
default : { |
printf("ether_rx: pkt-type=%04x, len=%04x\n", ntohs(pkt_type), pkt_len); |
break; |
} |
} |
} |
////////////////////////////////////////////////////////////////////////////////// |
/trunk/sw/dev/test_bfm/ether/ether_tx.c
0,0 → 1,173
////////////////////////////////////////////////////////////////////////////////// |
#include <stdlib.h> |
#include <stdio.h> |
|
#include "ether.h" // ETH_PKT_MAC_ADDR_LEN, .. |
#include "eth_host_bfm.h" // eth_frm_write_wait, .. |
|
////////////////////////////////////////////////////////////////////////////////// |
// IPv4: name+id LIST |
typedef struct { |
char id; |
char name[20]; |
} ipv4_prot_map_t; |
const ipv4_prot_map_t ipv4_prot_map[] = { |
{IPv4_ICMP, "IPv4_ICMP"}, |
{IPv4_IGMP, "IPv4_IGMP"}, |
{IPv4_TCP, "IPv4_TCP"}, |
{IPv4_UDP, "IPv4_UDP"}, |
{IPv4_RDP, "IPv4_RDP"}, |
{IPv4_IRTP, "IPv4_IRTP"}, |
{IPv4_IPv6Encaps, "IPv4_IPv6Encaps"}, |
{IPv4_IPv6Route, "IPv4_IPv6Route"}, |
{IPv4_IPv6Frag, "IPv4_IPv6Frag"}, |
{IPv4_QNX, "IPv4_QNX"}, |
{IPv4_SMP, "IPv4_SMP"}, |
{IPv4_SCTP, "IPv4_SCTP"}, |
{IPv4_UDPLite, "IPv4_UDPLite"} |
}; |
////////////////////////////////////////////////////////////////////////////////// |
// |
extern unsigned short crc_ip(void * ptr, unsigned count); |
extern long crc_ether(char *buf, int len); |
|
// |
void ether_tx_raw(char *ibuff, int ilen); |
void ether_tx_ipv4(char *ibuff, int ilen); |
|
////////////////////////////////////////////////////////////////////////////////// |
// |
// Ethernet TX routine |
// |
void ether_tx(char *ibuff, int ilen) |
{ |
// |
unsigned short pkt_type = *((unsigned short *)((ibuff)+ETH_PKT_MAC_ADDR_LEN*2)); |
switch(pkt_type) { |
case ETH_PKT_ARP : { |
printf("ether_tx: ETH_PKT_ARP, len=%04x\n", ilen); |
ether_tx_raw(ibuff, ilen); |
break; |
} |
case ETH_PKT_IPv4 : { |
ip_hdr_t *ptr_ipv4_hdr = (ip_hdr_t *)(ibuff+ETH_HDR_LEN); |
int i, prot=0; |
for (i = 0; i < (sizeof(ipv4_prot_map))/(sizeof(ipv4_prot_map_t)); i++) { |
if (ipv4_prot_map[i].id == ptr_ipv4_hdr->ip_prot) { |
printf("ether_tx: %s, len=%04x\n", ipv4_prot_map[i].name, ilen); |
prot++; |
} |
} |
if (prot == 0) { // not found in list |
printf("ether_tx: ETH_PKT_IPv4: IP protocol number = %x, len=%04x\n", ptr_ipv4_hdr->ip_prot, ilen); |
} |
|
/* |
switch(ptr_ipv4_hdr->ip_prot) { |
case IPv4_ICMP : { |
printf("ether_tx: ETH_PKT_IPv4-ICMP, len=%04x\n", ilen); |
break; |
} |
case IPv4_UDP : { |
printf("ether_tx: ETH_PKT_IPv4-UDP, len=%04x\n", ilen); |
break; |
} |
default : { |
printf("ether_tx: ETH_PKT_IPv4: IP protocol number = %x, len=%04x\n", ptr_ipv4_hdr->ip_prot, ilen); |
break; |
} |
} |
*/ |
ether_tx_ipv4(ibuff, ilen); |
break; |
}/* |
case ETH_PKT_IPv6 : { |
printf("ether_tx: ETH_PKT_IPv6, len=%04x\n", ilen); |
ether_tx_raw(ibuff, ilen); |
}*/ |
default : { |
/*printf("ether_tx: pkt-type=%04x, len=%04x\n", ntohs(pkt_type), ilen); |
ether_tx_raw(ibuff, ilen);*/ |
break; |
} |
} |
} |
////////////////////////////////////////////////////////////////////////////////// |
// |
// ARP+others |
// |
void ether_tx_raw(char *ibuff, int ilen) |
{ |
int i; |
// apr-len == 42 in case if {apr-len < ETH_MIN_TU} -> we will have rejection inside MAC |
int len_raw = (ilen < ETH_MIN_TU)? ETH_MIN_TU : ilen; |
char *ptr_raw = (char *)calloc(len_raw, sizeof(char)); // <- MEM-alloc |
if (ptr_raw == NULL) { return; } |
for (i = 0; i < ETH_MIN_TU; i++) { *(ptr_raw+i) = 0; } |
// data-copy |
for (i = 0; i < ilen; i++) { |
*(ptr_raw+i) = *(ibuff+i); |
} |
// upld |
for (i = 0; i < len_raw; i++) { |
eth_frm_write(*(ptr_raw+i), i); |
} |
// fcs |
int fcs = crc_ether(ptr_raw, len_raw); |
eth_frm_write(((fcs >> 0) & 0xFF), len_raw+0); |
eth_frm_write(((fcs >> 8) & 0xFF), len_raw+1); |
eth_frm_write(((fcs >> 16) & 0xFF), len_raw+2); |
eth_frm_write(((fcs >> 24) & 0xFF), len_raw+3); |
// len + STA |
eth_frm_write_len(len_raw+4); //+ FCS |
// |
free(ptr_raw); // -> MEM-free |
} |
////////////////////////////////////////////////////////////////////////////////// |
// |
// IPv4-UDP |
// |
void ether_tx_ipv4(char *ibuff, int ilen) |
{ |
// check len |
char *ptr_ipv4; |
int i, tx_len; |
|
if (ilen < ETH_MIN_TU){ |
ptr_ipv4 = (char *)calloc(ETH_MIN_TU, sizeof(char)); // <- MEM-alloc |
if (ptr_ipv4 == NULL) { return; } |
for (i = 0; i < ETH_MIN_TU; i++) { *(ptr_ipv4+i) = 0; } |
for (i = 0; i < ilen; i++) { *(ptr_ipv4+i) = *(ibuff+i); } |
tx_len = ETH_MIN_TU; |
} else { |
ptr_ipv4 = ibuff; |
tx_len = ilen; |
} |
|
// ipv4-csum |
ip_hdr_t *ptr_ipv4_hdr = (ip_hdr_t *)(ibuff+ETH_HDR_LEN); |
ptr_ipv4_hdr->ip_chksum = 0; |
unsigned short ipv4_xsum = ~crc_ip((char *)ptr_ipv4_hdr, ETH_IPv4_HDR_LEN >> 1); |
ptr_ipv4_hdr->ip_chksum = ipv4_xsum; |
// udp-csum |
udp_hdr_t *ptr_udp_hdr = (udp_hdr_t *)(ibuff+ETH_HDR_LEN+ETH_IPv4_HDR_LEN); |
ptr_udp_hdr->ud_cksum = 0; |
|
// upld |
for (i = 0; i < tx_len; i++) { |
eth_frm_write(*(ptr_ipv4+i), i); |
} |
// fcs |
int fcs = crc_ether(ptr_ipv4, tx_len); |
eth_frm_write(((fcs >> 0) & 0xFF), tx_len+0); |
eth_frm_write(((fcs >> 8) & 0xFF), tx_len+1); |
eth_frm_write(((fcs >> 16) & 0xFF), tx_len+2); |
eth_frm_write(((fcs >> 24) & 0xFF), tx_len+3); |
// len + STA |
eth_frm_write_len(tx_len+4); //+ FCS |
// |
if (ilen < ETH_MIN_TU){ |
free(ptr_ipv4); // -> MEM-free |
} |
} |
////////////////////////////////////////////////////////////////////////////////// |
/trunk/sw/dev/test_bfm/Makefile
0,0 → 1,57
# |
# makefile |
# |
|
# |
# TBD |
# |
|
TARGET_NAME = test_bfm |
|
all: clean $(TARGET_NAME) |
|
CC = g++ -xc |
CPP= g++ -xc++ |
LD = g++ |
OBJDUMP = objdump |
DEFAULT_CP := cp -f |
DEFAULT_MKDIR := mkdir -p |
DEFAULT_RM := rm -rf |
|
MSIM_INCLUDES ?= /opt/modelsim/modeltech/include |
|
INCDIR := ./ \ |
$(MSIM_INCLUDES) \ |
./dpi \ |
./ether |
|
INCLUDE := $(addprefix -I, $(INCDIR)) |
CFLAGS := -DMSIM |
CFLAGS := -g |
CFLAGS += $(INCLUDE) |
|
C_SRCS := $(wildcard *.c) |
C_SRCS += $(wildcard ./ether/*.c) |
|
OBJFILE_C := $(patsubst %.c,%.o, $(C_SRCS)) |
|
$(TARGET_NAME): $(OBJFILE_C) |
echo $(MSIM_INCLUDES) |
@echo C_SRCS: $(C_SRCS) |
$(LD) -shared -o $(TARGET_NAME).so $(notdir $^) $(LFLAGS) $(LIBRARIES) |
$(OBJDUMP) -S -d $(TARGET_NAME).so > $(TARGET_NAME).objdump |
rm -f *.o *~ core |
rm -f *.d *~ core |
@echo DONE: DPI-C so-lib |
|
%.o: %.c |
@echo Compiling $<: |
$(CC) $(CFLAGS) $(LIBRARIES) -fPIC -c $< |
|
clean: |
@echo clean: |
$(DEFAULT_RM) *.o *~ core |
$(DEFAULT_RM) *.d *~ core |
$(DEFAULT_RM) *.objdump |
$(DEFAULT_RM) *.pcap |
$(DEFAULT_RM) $(TARGET_NAME).so |
/trunk/sw/dev/test_bfm/test_bfm.c
0,0 → 1,148
#include <stdio.h> |
|
#include <arpa/inet.h> // sockaddr, .. / ?? net/if.h |
#include <linux/if.h> |
#include <linux/if_tun.h> |
#include <string.h> // memset, .. |
|
#include <sys/types.h> |
#include <sys/stat.h> |
#include <fcntl.h> // open, .. |
|
#include <sys/ioctl.h> // ioctl |
#include <errno.h> // |
|
#include <stdlib.h> // system |
|
|
/* */ |
#include "eth_host_bfm.h" // DPI-C |
#include "ether.h" // ether_tx, ether_rx_ok, ether_rx |
/* */ |
|
|
// ?? |
#define BUFSIZE 2048 // 2KB |
// ?? |
char buffer[BUFSIZE]; |
|
|
// tap-if READ |
int cread(int fd, char *buf, int n){ |
|
int nread; |
|
if((nread=read(fd, buf, n))<0){ |
perror("Reading data"); |
exit(1); |
} |
return nread; |
} |
// tap-if WRITE |
int cwrite(int fd, char *buf, int n){ |
|
int nwrite; |
|
if((nwrite=write(fd, buf, n))<0){ |
perror("Writing data"); |
exit(1); |
} |
return nwrite; |
} |
|
// MAIN |
int test_bfm(void) |
{ // dec vars |
struct ifreq ifr; |
int tap_fd, err; |
char tap_nm[IFNAMSIZ] = "tap0"; |
|
// prep |
memset(&ifr, 0, sizeof(ifr)); |
tap_fd = -1; |
|
// open |
tap_fd = open("/dev/net/tun", O_RDWR); |
if( tap_fd < 0 ) { |
printf("ERR0: fd=%x\n", tap_fd); |
return -1; |
} |
// cfg: {tap-if} + {no-packet-info} |
ifr.ifr_flags = IFF_TAP | IFF_NO_PI; |
strncpy(ifr.ifr_name, tap_nm, IFNAMSIZ); |
err = ioctl(tap_fd, TUNSETIFF, (void *)&ifr); // tun_set_iff: name + flags |
if( err < 0 ) { |
int errsv = errno; |
printf("ERR1: fd=%x, errsv=%x : %s\n", tap_fd, errsv, strerror(errsv)); |
close(tap_fd); |
return -2; |
} |
// msg2usr |
printf("ifr_name=%s\n", ifr.ifr_name); |
//printf("ifr_flags=%x\n", ifr.ifr_flags); |
|
// tap_fd == 'O_NONBLOCK' |
int flags = fcntl(tap_fd, F_GETFL, 0); |
fcntl(tap_fd, F_SETFL, flags | O_NONBLOCK); |
|
// main-loop |
int idx=0; |
while (1) { |
|
int ret; |
fd_set rd_set; |
struct timeval timeout; |
|
timeout.tv_sec=0; // no-wait, just check |
timeout.tv_usec=0; |
FD_ZERO(&rd_set); |
FD_SET(tap_fd, &rd_set); |
|
// HDL-time-consumption!!! |
host_delay(10); |
|
// sw-wait |
ret = select(tap_fd + 1, &rd_set, NULL, NULL, &timeout); // man7.org: if timeout is NULL, select() can block indefinitely... |
if ( ret < 0 ) { |
int errsv = errno; |
if (errsv == EINTR) { // EINTR -> not an ERR in curr situation |
//printf("EINTR\n"); |
continue; |
} |
if (errsv == EAGAIN) { // EAGAIN -> nothing to read |
// printf("EAGAIN\n"); |
continue; |
} else { // all others -> ERR-case |
printf("ERR4: fd=%x, errsv=%x : %s\n", tap_fd, errsv, strerror(errsv)); |
close(tap_fd); |
return -5; |
} |
} |
|
// check TAP-RX |
if(FD_ISSET(tap_fd, &rd_set)) { |
int nread = cread(tap_fd, &buffer[0], BUFSIZE); |
//printf("TAP-RD: nread=%03x\n", nread); |
if (nread) { |
ether_tx(&buffer[0], nread); |
} else { |
printf("FD_ISSET: nread=%x\n", nread); |
} |
//if (idx == 32) break; |
} |
|
// check TAP-TX |
if (ether_rx_ok()) { |
int nwrite_0; |
ether_rx(&buffer[0], &nwrite_0); |
int nwrite_1 = cwrite(tap_fd, &buffer[0], nwrite_0); |
} |
|
} |
// end / ;) |
printf("close TAP\n"); |
close(tap_fd); |
|
// Final |
return 0; |
} |
/trunk/sw/dev/test_main/src/_hdl/bsp/include/xil_assert.h
0,0 → 1,189
/****************************************************************************** |
* |
* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. |
* |
* Permission is hereby granted, free of charge, to any person obtaining a copy |
* of this software and associated documentation files (the "Software"), to deal |
* in the Software without restriction, including without limitation the rights |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
* copies of the Software, and to permit persons to whom the Software is |
* furnished to do so, subject to the following conditions: |
* |
* The above copyright notice and this permission notice shall be included in |
* all copies or substantial portions of the Software. |
* |
* Use of the Software is limited solely to applications: |
* (a) running on a Xilinx device, or |
* (b) that interact with a Xilinx device through a bus or interconnect. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF |
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
* SOFTWARE. |
* |
* Except as contained in this notice, the name of the Xilinx shall not be used |
* in advertising or otherwise to promote the sale, use or other dealings in |
* this Software without prior written authorization from Xilinx. |
* |
******************************************************************************/ |
/*****************************************************************************/ |
/** |
* |
* @file xil_assert.h |
* |
* This file contains assert related functions. |
* |
* <pre> |
* MODIFICATION HISTORY: |
* |
* Ver Who Date Changes |
* ----- ---- -------- ------------------------------------------------------- |
* 1.00a hbm 07/14/09 First release |
* </pre> |
* |
******************************************************************************/ |
|
#ifndef XIL_ASSERT_H /* prevent circular inclusions */ |
#define XIL_ASSERT_H /* by using protection macros */ |
|
#include "xil_types.h" |
|
#ifdef __cplusplus |
extern "C" { |
#endif |
|
|
/***************************** Include Files *********************************/ |
|
|
/************************** Constant Definitions *****************************/ |
|
#define XIL_ASSERT_NONE 0U |
#define XIL_ASSERT_OCCURRED 1U |
#define XNULL NULL |
|
extern u32 Xil_AssertStatus; |
extern void Xil_Assert(const char8 *File, s32 Line); |
void XNullHandler(void *NullParameter); |
|
/** |
* This data type defines a callback to be invoked when an |
* assert occurs. The callback is invoked only when asserts are enabled |
*/ |
typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line); |
|
/***************** Macros (Inline Functions) Definitions *********************/ |
|
#ifndef NDEBUG |
|
/*****************************************************************************/ |
/** |
* This assert macro is to be used for functions that do not return anything |
* (void). This in conjunction with the Xil_AssertWait boolean can be used to |
* accomodate tests so that asserts which fail allow execution to continue. |
* |
* @param Expression is the expression to evaluate. If it evaluates to |
* false, the assert occurs. |
* |
* @return Returns void unless the Xil_AssertWait variable is true, in which |
* case no return is made and an infinite loop is entered. |
* |
* @note None. |
* |
******************************************************************************/ |
#define Xil_AssertVoid(Expression) \ |
{ \ |
if (Expression) { \ |
Xil_AssertStatus = XIL_ASSERT_NONE; \ |
} else { \ |
Xil_Assert(__FILE__, __LINE__); \ |
Xil_AssertStatus = XIL_ASSERT_OCCURRED; \ |
return; \ |
} \ |
} |
|
/*****************************************************************************/ |
/** |
* This assert macro is to be used for functions that do return a value. This in |
* conjunction with the Xil_AssertWait boolean can be used to accomodate tests |
* so that asserts which fail allow execution to continue. |
* |
* @param Expression is the expression to evaluate. If it evaluates to false, |
* the assert occurs. |
* |
* @return Returns 0 unless the Xil_AssertWait variable is true, in which |
* case no return is made and an infinite loop is entered. |
* |
* @note None. |
* |
******************************************************************************/ |
#define Xil_AssertNonvoid(Expression) \ |
{ \ |
if (Expression) { \ |
Xil_AssertStatus = XIL_ASSERT_NONE; \ |
} else { \ |
Xil_Assert(__FILE__, __LINE__); \ |
Xil_AssertStatus = XIL_ASSERT_OCCURRED; \ |
return 0; \ |
} \ |
} |
|
/*****************************************************************************/ |
/** |
* Always assert. This assert macro is to be used for functions that do not |
* return anything (void). Use for instances where an assert should always |
* occur. |
* |
* @return Returns void unless the Xil_AssertWait variable is true, in which |
* case no return is made and an infinite loop is entered. |
* |
* @note None. |
* |
******************************************************************************/ |
#define Xil_AssertVoidAlways() \ |
{ \ |
Xil_Assert(__FILE__, __LINE__); \ |
Xil_AssertStatus = XIL_ASSERT_OCCURRED; \ |
return; \ |
} |
|
/*****************************************************************************/ |
/** |
* Always assert. This assert macro is to be used for functions that do return |
* a value. Use for instances where an assert should always occur. |
* |
* @return Returns void unless the Xil_AssertWait variable is true, in which |
* case no return is made and an infinite loop is entered. |
* |
* @note None. |
* |
******************************************************************************/ |
#define Xil_AssertNonvoidAlways() \ |
{ \ |
Xil_Assert(__FILE__, __LINE__); \ |
Xil_AssertStatus = XIL_ASSERT_OCCURRED; \ |
return 0; \ |
} |
|
|
#else |
|
#define Xil_AssertVoid(Expression) |
#define Xil_AssertVoidAlways() |
#define Xil_AssertNonvoid(Expression) |
#define Xil_AssertNonvoidAlways() |
|
#endif |
|
/************************** Function Prototypes ******************************/ |
|
//void Xil_AssertSetCallback(Xil_AssertCallback Routine); |
|
#ifdef __cplusplus |
} |
#endif |
|
#endif /* end of protection macro */ |
/trunk/sw/dev/test_main/src/_hdl/bsp/include/xil_cache.h
0,0 → 1,447
/****************************************************************************** |
* |
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. |
* |
* Permission is hereby granted, free of charge, to any person obtaining a copy |
* of this software and associated documentation files (the "Software"), to deal |
* in the Software without restriction, including without limitation the rights |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
* copies of the Software, and to permit persons to whom the Software is |
* furnished to do so, subject to the following conditions: |
* |
* The above copyright notice and this permission notice shall be included in |
* all copies or substantial portions of the Software. |
* |
* Use of the Software is limited solely to applications: |
* (a) running on a Xilinx device, or |
* (b) that interact with a Xilinx device through a bus or interconnect. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF |
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
* SOFTWARE. |
* |
* Except as contained in this notice, the name of the Xilinx shall not be used |
* in advertising or otherwise to promote the sale, use or other dealings in |
* this Software without prior written authorization from Xilinx. |
* |
******************************************************************************/ |
/*****************************************************************************/ |
/** |
* |
* @file xil_cache.h |
* |
* This header file contains cache related driver functions (or macros) |
* that can be used to access the device. The user should refer to the |
* hardware device specification for more details of the device operation. |
* The functions in this header file can be used across all Xilinx supported |
* processors. |
* |
* <pre> |
* MODIFICATION HISTORY: |
* |
* Ver Who Date Changes |
* ----- ---- -------- ------------------------------------------------------- |
* 1.00 hbm 07/28/09 Initial release |
* 3.02a sdm 10/24/11 Updated the file to include xparameters.h so that |
* the correct cache flush routines are used based on |
* whether the write-back or write-through caches are |
* used (cr #630532). |
* 3.10a asa 05/04/13 This version of MicroBlaze BSP adds support for system |
* cache/L2 cache. The existing/old APIs/macros in this |
* file are renamed to imply that they deal with L1 cache. |
* New macros/APIs are added to address similar features for |
* L2 cache. Users can include this file in their application |
* to use the various cache related APIs. These changes are |
* done for implementing PR #697214. |
* |
* </pre> |
* |
* @note |
* |
* None. |
* |
******************************************************************************/ |
|
#ifndef XIL_CACHE_H |
#define XIL_CACHE_H |
|
#if defined XENV_VXWORKS |
/* VxWorks environment */ |
#error "Unknown processor / architecture. Must be PPC for VxWorks." |
#else |
/* standalone environment */ |
|
//#include "mb_interface.h" |
#include "xil_types.h" |
#include "xparameters.h" |
|
#ifdef __cplusplus |
extern "C" { |
#endif |
|
/****************************************************************************/ |
/** |
* |
* Invalidate the entire L1 data cache. If the cacheline is modified (dirty), |
* the modified contents are lost. |
* |
* @param None. |
* |
* @return None. |
* |
* @note |
* |
* Processor must be in real mode. |
****************************************************************************/ |
#define Xil_L1DCacheInvalidate() //microblaze_invalidate_dcache() |
|
/****************************************************************************/ |
/** |
* |
* Invalidate the entire L2 data cache. If the cacheline is modified (dirty), |
* the modified contents are lost. |
* |
* @param None. |
* |
* @return None. |
* |
* @note |
* |
* Processor must be in real mode. |
****************************************************************************/ |
#define Xil_L2CacheInvalidate() //microblaze_invalidate_cache_ext() |
|
/****************************************************************************/ |
/** |
* |
* Invalidate the L1 data cache for the given address range. |
* If the bytes specified by the address (Addr) are cached by the L1 data cache, |
* the cacheline containing that byte is invalidated. If the cacheline |
* is modified (dirty), the modified contents are lost. |
* |
* @param Addr is address of ragne to be invalidated. |
* @param Len is the length in bytes to be invalidated. |
* |
* @return None. |
* |
* @note |
* |
* Processor must be in real mode. |
****************************************************************************/ |
#define Xil_L1DCacheInvalidateRange(Addr, Len) /*\ |
microblaze_invalidate_dcache_range((Addr), (Len))*/ |
|
/****************************************************************************/ |
/** |
* |
* Invalidate the L1 data cache for the given address range. |
* If the bytes specified by the address (Addr) are cached by the L1 data cache, |
* the cacheline containing that byte is invalidated. If the cacheline |
* is modified (dirty), the modified contents are lost. |
* |
* @param Addr is address of ragne to be invalidated. |
* @param Len is the length in bytes to be invalidated. |
* |
* @return None. |
* |
* @note |
* |
* Processor must be in real mode. |
****************************************************************************/ |
#define Xil_L2CacheInvalidateRange(Addr, Len) /*\ |
microblaze_invalidate_cache_ext_range((Addr), (Len))*/ |
|
/****************************************************************************/ |
/** |
* Flush the L1 data cache for the given address range. |
* If the bytes specified by the address (Addr) are cached by the data cache, |
* and is modified (dirty), the cacheline will be written to system memory. |
* The cacheline will also be invalidated. |
* |
* @param Addr is the starting address of the range to be flushed. |
* @param Len is the length in byte to be flushed. |
* |
* @return None. |
* |
****************************************************************************/ |
#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1) |
# define Xil_L1DCacheFlushRange(Addr, Len) /*\ |
microblaze_flush_dcache_range((Addr), (Len))*/ |
#else |
# define Xil_L1DCacheFlushRange(Addr, Len) /*\ |
microblaze_invalidate_dcache_range((Addr), (Len))*/ |
#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK */ |
|
/****************************************************************************/ |
/** |
* Flush the L2 data cache for the given address range. |
* If the bytes specified by the address (Addr) are cached by the data cache, |
* and is modified (dirty), the cacheline will be written to system memory. |
* The cacheline will also be invalidated. |
* |
* @param Addr is the starting address of the range to be flushed. |
* @param Len is the length in byte to be flushed. |
* |
* @return None. |
* |
****************************************************************************/ |
#define Xil_L2CacheFlushRange(Addr, Len) /*\ |
microblaze_flush_cache_ext_range((Addr), (Len))*/ |
|
/****************************************************************************/ |
/** |
* Flush the entire L1 data cache. If any cacheline is dirty, the cacheline will be |
* written to system memory. The entire data cache will be invalidated. |
* |
* @return None. |
* |
* @note |
* |
****************************************************************************/ |
#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1) |
# define Xil_L1DCacheFlush() microblaze_flush_dcache() |
#else |
# define Xil_L1DCacheFlush() //microblaze_invalidate_dcache() |
#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK */ |
|
/****************************************************************************/ |
/** |
* Flush the entire L2 data cache. If any cacheline is dirty, the cacheline will be |
* written to system memory. The entire data cache will be invalidated. |
* |
* @return None. |
* |
* @note |
* |
****************************************************************************/ |
#define Xil_L2CacheFlush() //microblaze_flush_cache_ext() |
|
/****************************************************************************/ |
/** |
* |
* Invalidate the instruction cache for the given address range. |
* |
* @param Addr is address of ragne to be invalidated. |
* @param Len is the length in bytes to be invalidated. |
* |
* @return None. |
* |
****************************************************************************/ |
#define Xil_L1ICacheInvalidateRange(Addr, Len) /*\ |
microblaze_invalidate_icache_range((Addr), (Len))*/ |
|
/****************************************************************************/ |
/** |
* |
* Invalidate the entire instruction cache. |
* |
* @param None |
* |
* @return None. |
* |
****************************************************************************/ |
#define Xil_L1ICacheInvalidate() /*\ |
microblaze_invalidate_icache()*/ |
|
|
/****************************************************************************/ |
/** |
* |
* Enable the L1 data cache. |
* |
* @return None. |
* |
* @note This is processor specific. |
* |
****************************************************************************/ |
#define Xil_L1DCacheEnable() /*\ |
microblaze_enable_dcache()*/ |
|
/****************************************************************************/ |
/** |
* |
* Disable the L1 data cache. |
* |
* @return None. |
* |
* @note This is processor specific. |
* |
****************************************************************************/ |
#define Xil_L1DCacheDisable() /*\ |
microblaze_disable_dcache()*/ |
|
/****************************************************************************/ |
/** |
* |
* Enable the instruction cache. |
* |
* @return None. |
* |
* @note This is processor specific. |
* |
****************************************************************************/ |
#define Xil_L1ICacheEnable() /*\ |
microblaze_enable_icache()*/ |
|
/****************************************************************************/ |
/** |
* |
* Disable the L1 Instruction cache. |
* |
* @return None. |
* |
* @note This is processor specific. |
* |
****************************************************************************/ |
#define Xil_L1ICacheDisable() /*\ |
microblaze_disable_icache()*/ |
|
/****************************************************************************/ |
/** |
* |
* Enable the data cache. |
* |
* @param None |
* |
* @return None. |
* |
****************************************************************************/ |
#define Xil_DCacheEnable() Xil_L1DCacheEnable() |
|
/****************************************************************************/ |
/** |
* |
* Enable the instruction cache. |
* |
* @param None |
* |
* @return None. |
* |
* @note |
* |
* |
****************************************************************************/ |
#define Xil_ICacheEnable() Xil_L1ICacheEnable() |
|
/**************************************************************************** |
* |
* Invalidate the entire Data cache. |
* |
* @param None. |
* |
* @return None. |
* |
* @note None. |
* |
****************************************************************************/ |
#define Xil_DCacheInvalidate() \ |
Xil_L2CacheInvalidate(); \ |
Xil_L1DCacheInvalidate(); |
|
|
/**************************************************************************** |
* |
* Invalidate the Data cache for the given address range. |
* If the bytes specified by the address (adr) are cached by the Data cache, |
* the cacheline containing that byte is invalidated. If the cacheline |
* is modified (dirty), the modified contents are lost and are NOT |
* written to system memory before the line is invalidated. |
* |
* @param Start address of ragne to be invalidated. |
* @param Length of range to be invalidated in bytes. |
* |
* @return None. |
* |
* @note None. |
* |
****************************************************************************/ |
#define Xil_DCacheInvalidateRange(Addr, Len) \ |
Xil_L2CacheInvalidateRange((Addr), (Len)); \ |
Xil_L1DCacheInvalidateRange((Addr), (Len)); |
|
|
/**************************************************************************** |
* |
* Flush the entire Data cache. |
* |
* @param None. |
* |
* @return None. |
* |
* @note None. |
* |
****************************************************************************/ |
#define Xil_DCacheFlush() \ |
Xil_L2CacheFlush(); \ |
Xil_L1DCacheFlush(); |
|
/**************************************************************************** |
* Flush the Data cache for the given address range. |
* If the bytes specified by the address (adr) are cached by the Data cache, |
* the cacheline containing that byte is invalidated. If the cacheline |
* is modified (dirty), the written to system memory first before the |
* before the line is invalidated. |
* |
* @param Start address of range to be flushed. |
* @param Length of range to be flushed in bytes. |
* |
* @return None. |
* |
* @note None. |
* |
****************************************************************************/ |
#define Xil_DCacheFlushRange(Addr, Len) \ |
Xil_L2CacheFlushRange((Addr), (Len)); \ |
Xil_L1DCacheFlushRange((Addr), (Len)); |
|
|
/**************************************************************************** |
* |
* Invalidate the entire instruction cache. |
* |
* @param None. |
* |
* @return None. |
* |
* @note None. |
* |
****************************************************************************/ |
#define Xil_ICacheInvalidate() \ |
Xil_L2CacheInvalidate(); \ |
Xil_L1ICacheInvalidate(); |
|
|
/**************************************************************************** |
* |
* Invalidate the instruction cache for the given address range. |
* If the bytes specified by the address (adr) are cached by the Data cache, |
* the cacheline containing that byte is invalidated. If the cacheline |
* is modified (dirty), the modified contents are lost and are NOT |
* written to system memory before the line is invalidated. |
* |
* @param Start address of ragne to be invalidated. |
* @param Length of range to be invalidated in bytes. |
* |
* @return None. |
* |
* @note None. |
* |
****************************************************************************/ |
#define Xil_ICacheInvalidateRange(Addr, Len) \ |
Xil_L2CacheInvalidateRange((Addr), (Len)); \ |
Xil_L1ICacheInvalidateRange((Addr), (Len)); |
|
void Xil_DCacheDisable(void); |
void Xil_ICacheDisable(void); |
|
#ifdef __cplusplus |
} |
#endif |
|
#endif |
|
#endif |
/trunk/sw/dev/test_main/src/_hdl/bsp/include/xil_io.h
0,0 → 1,270
/****************************************************************************** |
* |
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. |
* |
* Permission is hereby granted, free of charge, to any person obtaining a copy |
* of this software and associated documentation files (the "Software"), to deal |
* in the Software without restriction, including without limitation the rights |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
* copies of the Software, and to permit persons to whom the Software is |
* furnished to do so, subject to the following conditions: |
* |
* The above copyright notice and this permission notice shall be included in |
* all copies or substantial portions of the Software. |
* |
* Use of the Software is limited solely to applications: |
* (a) running on a Xilinx device, or |
* (b) that interact with a Xilinx device through a bus or interconnect. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF |
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
* SOFTWARE. |
* |
* Except as contained in this notice, the name of the Xilinx shall not be used |
* in advertising or otherwise to promote the sale, use or other dealings in |
* this Software without prior written authorization from Xilinx. |
* |
******************************************************************************/ |
/*****************************************************************************/ |
/** |
* |
* @file xil_io.h |
* |
* This file contains the interface for the general IO component, which |
* encapsulates the Input/Output functions for processors that do not |
* require any special I/O handling. |
* |
* <pre> |
* MODIFICATION HISTORY: |
* |
* Ver Who Date Changes |
* ----- ---- -------- ------------------------------------------------------- |
* 3.00a hbm 07/28/09 Initial release |
* 3.00a hbm 07/21/10 Added Xil_EndianSwap32/16, Xil_Htonl/s, Xil_Ntohl/s |
* 3.03a sdm 08/18/11 Added INST_SYNC and DATA_SYNC macros. |
* 3.07a asa 08/31/12 Added xil_printf.h include |
* |
* </pre> |
* |
* @note |
* |
* This file may contain architecture-dependent items. |
* |
******************************************************************************/ |
|
#ifndef XIL_IO_H /* prevent circular inclusions */ |
#define XIL_IO_H /* by using protection macros */ |
|
#ifdef __cplusplus |
extern "C" { |
#endif |
|
/***************************** Include Files *********************************/ |
|
#include "xil_types.h" |
//#include "mb_interface.h" |
#include "xil_printf.h" |
#include "simple.h" |
|
/************************** Constant Definitions *****************************/ |
|
/**************************** Function Prototypes ****************************/ |
|
u8 Xil_In8(u32 Addr); |
u16 Xil_In16(u32 Addr); |
u32 Xil_In32(u32 Addr); |
|
void Xil_Out8(u32 Addr, u8 Value); |
void Xil_Out16(u32 Addr, u16 Value); |
void Xil_Out32(u32 Addr, u32 Value); |
|
/***************** Macros (Inline Functions) Definitions *********************/ |
|
#if defined __GNUC__ |
# define INST_SYNC //mbar(0) |
# define DATA_SYNC //mbar(1) |
#else |
# define INST_SYNC |
# define DATA_SYNC |
#endif /* __GNUC__ */ |
|
/* |
* The following macros allow optimized I/O operations for memory mapped I/O. |
* It should be noted that macros cannot be used if synchronization of the I/O |
* operation is needed as it will likely break some code. |
*/ |
|
|
|
extern u16 Xil_EndianSwap16(u16 Data); |
extern u32 Xil_EndianSwap32(u32 Data); |
|
#ifndef __LITTLE_ENDIAN__ |
extern u16 Xil_In16LE(u32 Addr); |
extern u32 Xil_In32LE(u32 Addr); |
extern void Xil_Out16LE(u32 Addr, u16 Value); |
extern void Xil_Out32LE(u32 Addr, u32 Value); |
|
/** |
* |
* Perform an big-endian input operation for a 16-bit memory location |
* by reading from the specified address and returning the value read from |
* that address. |
* |
* @param addr contains the address to perform the input operation at. |
* |
* @return The value read from the specified input address with the |
* proper endianness. The return value has the same endianness |
* as that of the processor, i.e. if the processor is |
* little-engian, the return value is the byte-swapped value read |
* from the address. |
* |
* @note None. |
* |
******************************************************************************/ |
#define Xil_In16BE(Addr) Xil_In16((Addr)) |
|
/** |
* |
* Perform a big-endian input operation for a 32-bit memory location |
* by reading from the specified address and returning the value read from |
* that address. |
* |
* @param Addr contains the address to perform the input operation at. |
* |
* @return The value read from the specified input address with the |
* proper endianness. The return value has the same endianness |
* as that of the processor, i.e. if the processor is |
* little-engian, the return value is the byte-swapped value read |
* from the address. |
* |
* |
* @note None. |
* |
******************************************************************************/ |
#define Xil_In32BE(Addr) Xil_In32((Addr)) |
|
/*****************************************************************************/ |
/** |
* |
* Perform a big-endian output operation for a 16-bit memory location |
* by writing the specified value to the specified address. |
* |
* @param Addr contains the address to perform the output operation at. |
* @param Value contains the value to be output at the specified address. |
* The value has the same endianness as that of the processor. |
* If the processor is little-endian, the byte-swapped value is |
* written to the address. |
* |
* |
* @return None |
* |
* @note None. |
* |
******************************************************************************/ |
#define Xil_Out16BE(Addr, Value) Xil_Out16((Addr), (Value)) |
|
/*****************************************************************************/ |
/** |
* |
* Perform a big-endian output operation for a 32-bit memory location |
* by writing the specified value to the specified address. |
* |
* @param Addr contains the address to perform the output operation at. |
* @param Value contains the value to be output at the specified address. |
* The value has the same endianness as that of the processor. |
* If the processor is little-endian, the byte-swapped value is |
* written to the address. |
* |
* @return None |
* |
* @note None. |
* |
******************************************************************************/ |
#define Xil_Out32BE(Addr, Value) Xil_Out32((Addr), (Value)) |
|
#define Xil_Htonl(Data) (Data) |
#define Xil_Htons(Data) (Data) |
#define Xil_Ntohl(Data) (Data) |
#define Xil_Ntohs(Data) (Data) |
|
#else |
|
extern u16 Xil_In16BE(u32 Addr); |
extern u32 Xil_In32BE(u32 Addr); |
extern void Xil_Out16BE(u32 Addr, u16 Value); |
extern void Xil_Out32BE(u32 Addr, u32 Value); |
|
#define Xil_In16LE(Addr) Xil_In16((Addr)) |
#define Xil_In32LE(Addr) Xil_In32((Addr)) |
#define Xil_Out16LE(Addr, Value) Xil_Out16((Addr), (Value)) |
#define Xil_Out32LE(Addr, Value) Xil_Out32((Addr), (Value)) |
|
|
/*****************************************************************************/ |
/** |
* |
* Convert a 32-bit number from host byte order to network byte order. |
* |
* @param Data the 32-bit number to be converted. |
* |
* @return The converted 32-bit number in network byte order. |
* |
* @note None. |
* |
******************************************************************************/ |
#define Xil_Htonl(Data) Xil_EndianSwap32((Data)) |
|
/*****************************************************************************/ |
/** |
* |
* Convert a 16-bit number from host byte order to network byte order. |
* |
* @param Data the 16-bit number to be converted. |
* |
* @return The converted 16-bit number in network byte order. |
* |
* @note None. |
* |
******************************************************************************/ |
#define Xil_Htons(Data) Xil_EndianSwap16((Data)) |
|
/*****************************************************************************/ |
/** |
* |
* Convert a 32-bit number from network byte order to host byte order. |
* |
* @param Value the 32-bit number to be converted. |
* |
* @return The converted 32-bit number in host byte order. |
* |
* @note None. |
* |
******************************************************************************/ |
#define Xil_Ntohl(Data) Xil_EndianSwap32((Data)) |
|
/*****************************************************************************/ |
/** |
* |
* Convert a 16-bit number from network byte order to host byte order. |
* |
* @param Value the 16-bit number to be converted. |
* |
* @return The converted 16-bit number in host byte order. |
* |
* @note None. |
* |
******************************************************************************/ |
#define Xil_Ntohs(Data) Xil_EndianSwap16((Data)) |
|
#endif |
|
#ifdef __cplusplus |
} |
#endif |
|
#endif /* end of protection macro */ |
/trunk/sw/dev/test_main/src/_hdl/bsp/include/xil_printf.h
0,0 → 1,50
/****************************************************************************** |
* |
* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. |
* |
* Permission is hereby granted, free of charge, to any person obtaining a copy |
* of this software and associated documentation files (the "Software"), to deal |
* in the Software without restriction, including without limitation the rights |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
* copies of the Software, and to permit persons to whom the Software is |
* furnished to do so, subject to the following conditions: |
* |
* The above copyright notice and this permission notice shall be included in |
* all copies or substantial portions of the Software. |
* |
* Use of the Software is limited solely to applications: |
* (a) running on a Xilinx device, or |
* (b) that interact with a Xilinx device through a bus or interconnect. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF |
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
* SOFTWARE. |
* |
* Except as contained in this notice, the name of the Xilinx shall not be used |
* in advertising or otherwise to promote the sale, use or other dealings in |
* this Software without prior written authorization from Xilinx. |
* |
******************************************************************************/ |
#ifndef XIL_PRINTF_H |
#define XIL_PRINTF_H |
|
#include "xil_types.h" |
|
#ifdef __cplusplus |
extern "C" { |
#endif |
/* |
void xil_printf(const char8 *ctrl1, ...); |
void print(char *ptr); |
*/ |
#define xil_printf printf |
|
#ifdef __cplusplus |
} |
#endif |
|
#endif /* end of protection macro */ |
/trunk/sw/dev/test_main/src/_hdl/bsp/include/xil_types.h
0,0 → 1,200
/****************************************************************************** |
* |
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. |
* |
* Permission is hereby granted, free of charge, to any person obtaining a copy |
* of this software and associated documentation files (the "Software"), to deal |
* in the Software without restriction, including without limitation the rights |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
* copies of the Software, and to permit persons to whom the Software is |
* furnished to do so, subject to the following conditions: |
* |
* The above copyright notice and this permission notice shall be included in |
* all copies or substantial portions of the Software. |
* |
* Use of the Software is limited solely to applications: |
* (a) running on a Xilinx device, or |
* (b) that interact with a Xilinx device through a bus or interconnect. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF |
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
* SOFTWARE. |
* |
* Except as contained in this notice, the name of the Xilinx shall not be used |
* in advertising or otherwise to promote the sale, use or other dealings in |
* this Software without prior written authorization from Xilinx. |
* |
******************************************************************************/ |
/*****************************************************************************/ |
/** |
* |
* @file xil_types.h |
* |
* This file contains basic types for Xilinx software IP. |
|
* |
* <pre> |
* MODIFICATION HISTORY: |
* |
* Ver Who Date Changes |
* ----- ---- -------- ------------------------------------------------------- |
* 1.00a hbm 07/14/09 First release |
* 3.03a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros |
* 5.00 pkp 05/29/14 Made changes for 64 bit architecture |
* srt 07/14/14 Use standard definitions from stdint.h and stddef.h |
* Define LONG and ULONG datatypes and mask values |
* </pre> |
* |
******************************************************************************/ |
|
#ifndef XIL_TYPES_H /* prevent circular inclusions */ |
#define XIL_TYPES_H /* by using protection macros */ |
|
#include <stdint.h> |
#include <stddef.h> |
|
/************************** Constant Definitions *****************************/ |
|
#ifndef TRUE |
# define TRUE 1U |
#endif |
|
#ifndef FALSE |
# define FALSE 0U |
#endif |
|
#ifndef NULL |
#define NULL 0U |
#endif |
|
#define XIL_COMPONENT_IS_READY 0x11111111U /**< component has been initialized */ |
#define XIL_COMPONENT_IS_STARTED 0x22222222U /**< component has been started */ |
|
/** @name New types |
* New simple types. |
* @{ |
*/ |
#ifndef __KERNEL__ |
#ifndef XBASIC_TYPES_H |
/** |
* guarded against xbasic_types.h. |
*/ |
typedef uint8_t u8; |
typedef uint16_t u16; |
typedef uint32_t u32; |
|
#define __XUINT64__ |
typedef struct |
{ |
u32 Upper; |
u32 Lower; |
} Xuint64; |
|
|
/*****************************************************************************/ |
/** |
* Return the most significant half of the 64 bit data type. |
* |
* @param x is the 64 bit word. |
* |
* @return The upper 32 bits of the 64 bit word. |
* |
* @note None. |
* |
******************************************************************************/ |
#define XUINT64_MSW(x) ((x).Upper) |
|
/*****************************************************************************/ |
/** |
* Return the least significant half of the 64 bit data type. |
* |
* @param x is the 64 bit word. |
* |
* @return The lower 32 bits of the 64 bit word. |
* |
* @note None. |
* |
******************************************************************************/ |
#define XUINT64_LSW(x) ((x).Lower) |
|
#endif /* XBASIC_TYPES_H */ |
|
/** |
* xbasic_types.h does not typedef s* or u64 |
*/ |
|
typedef char char8; |
typedef int8_t s8; |
typedef int16_t s16; |
typedef int32_t s32; |
typedef int64_t s64; |
typedef uint64_t u64; |
typedef int sint32; |
|
typedef intptr_t INTPTR; |
typedef uintptr_t UINTPTR; |
typedef ptrdiff_t PTRDIFF; |
|
#if !defined(LONG) || !defined(ULONG) |
typedef long LONG; |
typedef unsigned long ULONG; |
#endif |
|
#define ULONG64_HI_MASK 0xFFFFFFFF00000000U |
#define ULONG64_LO_MASK ~ULONG64_HI_MASK |
|
#else |
#include <linux/types.h> |
#endif |
|
|
/** |
* This data type defines an interrupt handler for a device. |
* The argument points to the instance of the component |
*/ |
typedef void (*XInterruptHandler) (void *InstancePtr); |
|
/** |
* This data type defines an exception handler for a processor. |
* The argument points to the instance of the component |
*/ |
typedef void (*XExceptionHandler) (void *InstancePtr); |
|
/** |
* UPPER_32_BITS - return bits 32-63 of a number |
* @n: the number we're accessing |
* |
* A basic shift-right of a 64- or 32-bit quantity. Use this to suppress |
* the "right shift count >= width of type" warning when that quantity is |
* 32-bits. |
*/ |
#define UPPER_32_BITS(n) ((u32)(((n) >> 16) >> 16)) |
|
/** |
* LOWER_32_BITS - return bits 0-31 of a number |
* @n: the number we're accessing |
*/ |
#define LOWER_32_BITS(n) ((u32)(n)) |
|
/*@}*/ |
|
|
/************************** Constant Definitions *****************************/ |
|
#ifndef TRUE |
#define TRUE 1U |
#endif |
|
#ifndef FALSE |
#define FALSE 0U |
#endif |
|
#ifndef NULL |
#define NULL 0U |
#endif |
|
#endif /* end of protection macro */ |
/trunk/sw/dev/test_main/src/_hdl/bsp/include/xstatus.h
0,0 → 1,430
/****************************************************************************** |
* |
* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved. |
* |
* Permission is hereby granted, free of charge, to any person obtaining a copy |
* of this software and associated documentation files (the "Software"), to deal |
* in the Software without restriction, including without limitation the rights |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
* copies of the Software, and to permit persons to whom the Software is |
* furnished to do so, subject to the following conditions: |
* |
* The above copyright notice and this permission notice shall be included in |
* all copies or substantial portions of the Software. |
* |
* Use of the Software is limited solely to applications: |
* (a) running on a Xilinx device, or |
* (b) that interact with a Xilinx device through a bus or interconnect. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF |
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
* SOFTWARE. |
* |
* Except as contained in this notice, the name of the Xilinx shall not be used |
* in advertising or otherwise to promote the sale, use or other dealings in |
* this Software without prior written authorization from Xilinx. |
* |
******************************************************************************/ |
/*****************************************************************************/ |
/** |
* |
* @file xstatus.h |
* |
* This file contains Xilinx software status codes. Status codes have their |
* own data type called int. These codes are used throughout the Xilinx |
* device drivers. |
* |
******************************************************************************/ |
|
#ifndef XSTATUS_H /* prevent circular inclusions */ |
#define XSTATUS_H /* by using protection macros */ |
|
#ifdef __cplusplus |
extern "C" { |
#endif |
|
/***************************** Include Files *********************************/ |
|
#include "xil_types.h" |
#include "xil_assert.h" |
|
/************************** Constant Definitions *****************************/ |
|
/*********************** Common statuses 0 - 500 *****************************/ |
|
#define XST_SUCCESS 0L |
#define XST_FAILURE 1L |
#define XST_DEVICE_NOT_FOUND 2L |
#define XST_DEVICE_BLOCK_NOT_FOUND 3L |
#define XST_INVALID_VERSION 4L |
#define XST_DEVICE_IS_STARTED 5L |
#define XST_DEVICE_IS_STOPPED 6L |
#define XST_FIFO_ERROR 7L /* an error occurred during an |
operation with a FIFO such as |
an underrun or overrun, this |
error requires the device to |
be reset */ |
#define XST_RESET_ERROR 8L /* an error occurred which requires |
the device to be reset */ |
#define XST_DMA_ERROR 9L /* a DMA error occurred, this error |
typically requires the device |
using the DMA to be reset */ |
#define XST_NOT_POLLED 10L /* the device is not configured for |
polled mode operation */ |
#define XST_FIFO_NO_ROOM 11L /* a FIFO did not have room to put |
the specified data into */ |
#define XST_BUFFER_TOO_SMALL 12L /* the buffer is not large enough |
to hold the expected data */ |
#define XST_NO_DATA 13L /* there was no data available */ |
#define XST_REGISTER_ERROR 14L /* a register did not contain the |
expected value */ |
#define XST_INVALID_PARAM 15L /* an invalid parameter was passed |
into the function */ |
#define XST_NOT_SGDMA 16L /* the device is not configured for |
scatter-gather DMA operation */ |
#define XST_LOOPBACK_ERROR 17L /* a loopback test failed */ |
#define XST_NO_CALLBACK 18L /* a callback has not yet been |
registered */ |
#define XST_NO_FEATURE 19L /* device is not configured with |
the requested feature */ |
#define XST_NOT_INTERRUPT 20L /* device is not configured for |
interrupt mode operation */ |
#define XST_DEVICE_BUSY 21L /* device is busy */ |
#define XST_ERROR_COUNT_MAX 22L /* the error counters of a device |
have maxed out */ |
#define XST_IS_STARTED 23L /* used when part of device is |
already started i.e. |
sub channel */ |
#define XST_IS_STOPPED 24L /* used when part of device is |
already stopped i.e. |
sub channel */ |
#define XST_DATA_LOST 26L /* driver defined error */ |
#define XST_RECV_ERROR 27L /* generic receive error */ |
#define XST_SEND_ERROR 28L /* generic transmit error */ |
#define XST_NOT_ENABLED 29L /* a requested service is not |
available because it has not |
been enabled */ |
|
/***************** Utility Component statuses 401 - 500 *********************/ |
|
#define XST_MEMTEST_FAILED 401L /* memory test failed */ |
|
|
/***************** Common Components statuses 501 - 1000 *********************/ |
|
/********************* Packet Fifo statuses 501 - 510 ************************/ |
|
#define XST_PFIFO_LACK_OF_DATA 501L /* not enough data in FIFO */ |
#define XST_PFIFO_NO_ROOM 502L /* not enough room in FIFO */ |
#define XST_PFIFO_BAD_REG_VALUE 503L /* self test, a register value |
was invalid after reset */ |
#define XST_PFIFO_ERROR 504L /* generic packet FIFO error */ |
#define XST_PFIFO_DEADLOCK 505L /* packet FIFO is reporting |
* empty and full simultaneously |
*/ |
|
/************************** DMA statuses 511 - 530 ***************************/ |
|
#define XST_DMA_TRANSFER_ERROR 511L /* self test, DMA transfer |
failed */ |
#define XST_DMA_RESET_REGISTER_ERROR 512L /* self test, a register value |
was invalid after reset */ |
#define XST_DMA_SG_LIST_EMPTY 513L /* scatter gather list contains |
no buffer descriptors ready |
to be processed */ |
#define XST_DMA_SG_IS_STARTED 514L /* scatter gather not stopped */ |
#define XST_DMA_SG_IS_STOPPED 515L /* scatter gather not running */ |
#define XST_DMA_SG_LIST_FULL 517L /* all the buffer desciptors of |
the scatter gather list are |
being used */ |
#define XST_DMA_SG_BD_LOCKED 518L /* the scatter gather buffer |
descriptor which is to be |
copied over in the scatter |
list is locked */ |
#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /* no buffer descriptors have been |
put into the scatter gather |
list to be commited */ |
#define XST_DMA_SG_COUNT_EXCEEDED 521L /* the packet count threshold |
specified was larger than the |
total # of buffer descriptors |
in the scatter gather list */ |
#define XST_DMA_SG_LIST_EXISTS 522L /* the scatter gather list has |
already been created */ |
#define XST_DMA_SG_NO_LIST 523L /* no scatter gather list has |
been created */ |
#define XST_DMA_SG_BD_NOT_COMMITTED 524L /* the buffer descriptor which was |
being started was not committed |
to the list */ |
#define XST_DMA_SG_NO_DATA 525L /* the buffer descriptor to start |
has already been used by the |
hardware so it can't be reused |
*/ |
#define XST_DMA_SG_LIST_ERROR 526L /* general purpose list access |
error */ |
#define XST_DMA_BD_ERROR 527L /* general buffer descriptor |
error */ |
|
/************************** IPIF statuses 531 - 550 ***************************/ |
|
#define XST_IPIF_REG_WIDTH_ERROR 531L /* an invalid register width |
was passed into the function */ |
#define XST_IPIF_RESET_REGISTER_ERROR 532L /* the value of a register at |
reset was not valid */ |
#define XST_IPIF_DEVICE_STATUS_ERROR 533L /* a write to the device interrupt |
status register did not read |
back correctly */ |
#define XST_IPIF_DEVICE_ACK_ERROR 534L /* the device interrupt status |
register did not reset when |
acked */ |
#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /* the device interrupt enable |
register was not updated when |
other registers changed */ |
#define XST_IPIF_IP_STATUS_ERROR 536L /* a write to the IP interrupt |
status register did not read |
back correctly */ |
#define XST_IPIF_IP_ACK_ERROR 537L /* the IP interrupt status register |
did not reset when acked */ |
#define XST_IPIF_IP_ENABLE_ERROR 538L /* IP interrupt enable register was |
not updated correctly when other |
registers changed */ |
#define XST_IPIF_DEVICE_PENDING_ERROR 539L /* The device interrupt pending |
register did not indicate the |
expected value */ |
#define XST_IPIF_DEVICE_ID_ERROR 540L /* The device interrupt ID register |
did not indicate the expected |
value */ |
#define XST_IPIF_ERROR 541L /* generic ipif error */ |
|
/****************** Device specific statuses 1001 - 4095 *********************/ |
|
/********************* Ethernet statuses 1001 - 1050 *************************/ |
|
#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /* Memory space is not big enough |
* to hold the minimum number of |
* buffers or descriptors */ |
#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /* Memory allocation failed */ |
#define XST_EMAC_MII_READ_ERROR 1003L /* MII read error */ |
#define XST_EMAC_MII_BUSY 1004L /* An MII operation is in progress */ |
#define XST_EMAC_OUT_OF_BUFFERS 1005L /* Driver is out of buffers */ |
#define XST_EMAC_PARSE_ERROR 1006L /* Invalid driver init string */ |
#define XST_EMAC_COLLISION_ERROR 1007L /* Excess deferral or late |
* collision on polled send */ |
|
/*********************** UART statuses 1051 - 1075 ***************************/ |
#define XST_UART |
|
#define XST_UART_INIT_ERROR 1051L |
#define XST_UART_START_ERROR 1052L |
#define XST_UART_CONFIG_ERROR 1053L |
#define XST_UART_TEST_FAIL 1054L |
#define XST_UART_BAUD_ERROR 1055L |
#define XST_UART_BAUD_RANGE 1056L |
|
|
/************************ IIC statuses 1076 - 1100 ***************************/ |
|
#define XST_IIC_SELFTEST_FAILED 1076 /* self test failed */ |
#define XST_IIC_BUS_BUSY 1077 /* bus found busy */ |
#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /* mastersend attempted with */ |
/* general call address */ |
#define XST_IIC_STAND_REG_RESET_ERROR 1079 /* A non parameterizable reg */ |
/* value after reset not valid */ |
#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /* Tx fifo included in design */ |
/* value after reset not valid */ |
#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /* Rx fifo included in design */ |
/* value after reset not valid */ |
#define XST_IIC_TBA_REG_RESET_ERROR 1082 /* 10 bit addr incl in design */ |
/* value after reset not valid */ |
#define XST_IIC_CR_READBACK_ERROR 1083 /* Read of the control register */ |
/* didn't return value written */ |
#define XST_IIC_DTR_READBACK_ERROR 1084 /* Read of the data Tx reg */ |
/* didn't return value written */ |
#define XST_IIC_DRR_READBACK_ERROR 1085 /* Read of the data Receive reg */ |
/* didn't return value written */ |
#define XST_IIC_ADR_READBACK_ERROR 1086 /* Read of the data Tx reg */ |
/* didn't return value written */ |
#define XST_IIC_TBA_READBACK_ERROR 1087 /* Read of the 10 bit addr reg */ |
/* didn't return written value */ |
#define XST_IIC_NOT_SLAVE 1088 /* The device isn't a slave */ |
|
/*********************** ATMC statuses 1101 - 1125 ***************************/ |
|
#define XST_ATMC_ERROR_COUNT_MAX 1101L /* the error counters in the ATM |
controller hit the max value |
which requires the statistics |
to be cleared */ |
|
/*********************** Flash statuses 1126 - 1150 **************************/ |
|
#define XST_FLASH_BUSY 1126L /* Flash is erasing or programming |
*/ |
#define XST_FLASH_READY 1127L /* Flash is ready for commands */ |
#define XST_FLASH_ERROR 1128L /* Flash had detected an internal |
error. Use XFlash_DeviceControl |
to retrieve device specific codes |
*/ |
#define XST_FLASH_ERASE_SUSPENDED 1129L /* Flash is in suspended erase state |
*/ |
#define XST_FLASH_WRITE_SUSPENDED 1130L /* Flash is in suspended write state |
*/ |
#define XST_FLASH_PART_NOT_SUPPORTED 1131L /* Flash type not supported by |
driver */ |
#define XST_FLASH_NOT_SUPPORTED 1132L /* Operation not supported */ |
#define XST_FLASH_TOO_MANY_REGIONS 1133L /* Too many erase regions */ |
#define XST_FLASH_TIMEOUT_ERROR 1134L /* Programming or erase operation |
aborted due to a timeout */ |
#define XST_FLASH_ADDRESS_ERROR 1135L /* Accessed flash outside its |
addressible range */ |
#define XST_FLASH_ALIGNMENT_ERROR 1136L /* Write alignment error */ |
#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /* Couldn't return immediately from |
write/erase function with |
XFL_NON_BLOCKING_WRITE/ERASE |
option cleared */ |
#define XST_FLASH_CFI_QUERY_ERROR 1138L /* Failed to query the device */ |
|
/*********************** SPI statuses 1151 - 1175 ****************************/ |
|
#define XST_SPI_MODE_FAULT 1151 /* master was selected as slave */ |
#define XST_SPI_TRANSFER_DONE 1152 /* data transfer is complete */ |
#define XST_SPI_TRANSMIT_UNDERRUN 1153 /* slave underruns transmit register */ |
#define XST_SPI_RECEIVE_OVERRUN 1154 /* device overruns receive register */ |
#define XST_SPI_NO_SLAVE 1155 /* no slave has been selected yet */ |
#define XST_SPI_TOO_MANY_SLAVES 1156 /* more than one slave is being |
* selected */ |
#define XST_SPI_NOT_MASTER 1157 /* operation is valid only as master */ |
#define XST_SPI_SLAVE_ONLY 1158 /* device is configured as slave-only |
*/ |
#define XST_SPI_SLAVE_MODE_FAULT 1159 /* slave was selected while disabled */ |
#define XST_SPI_SLAVE_MODE 1160 /* device has been addressed as slave */ |
#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /* device received data in slave mode */ |
|
#define XST_SPI_COMMAND_ERROR 1162 /* unrecognised command - qspi only */ |
|
/********************** OPB Arbiter statuses 1176 - 1200 *********************/ |
|
#define XST_OPBARB_INVALID_PRIORITY 1176 /* the priority registers have either |
* one master assigned to two or more |
* priorities, or one master not |
* assigned to any priority |
*/ |
#define XST_OPBARB_NOT_SUSPENDED 1177 /* an attempt was made to modify the |
* priority levels without first |
* suspending the use of priority |
* levels |
*/ |
#define XST_OPBARB_PARK_NOT_ENABLED 1178 /* bus parking by id was enabled but |
* bus parking was not enabled |
*/ |
#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /* the arbiter must be in fixed |
* priority mode to allow the |
* priorities to be changed |
*/ |
|
/************************ Intc statuses 1201 - 1225 **************************/ |
|
#define XST_INTC_FAIL_SELFTEST 1201 /* self test failed */ |
#define XST_INTC_CONNECT_ERROR 1202 /* interrupt already in use */ |
|
/********************** TmrCtr statuses 1226 - 1250 **************************/ |
|
#define XST_TMRCTR_TIMER_FAILED 1226 /* self test failed */ |
|
/********************** WdtTb statuses 1251 - 1275 ***************************/ |
|
#define XST_WDTTB_TIMER_FAILED 1251L |
|
/********************** PlbArb statuses 1276 - 1300 **************************/ |
|
#define XST_PLBARB_FAIL_SELFTEST 1276L |
|
/********************** Plb2Opb statuses 1301 - 1325 *************************/ |
|
#define XST_PLB2OPB_FAIL_SELFTEST 1301L |
|
/********************** Opb2Plb statuses 1326 - 1350 *************************/ |
|
#define XST_OPB2PLB_FAIL_SELFTEST 1326L |
|
/********************** SysAce statuses 1351 - 1360 **************************/ |
|
#define XST_SYSACE_NO_LOCK 1351L /* No MPU lock has been granted */ |
|
/********************** PCI Bridge statuses 1361 - 1375 **********************/ |
|
#define XST_PCI_INVALID_ADDRESS 1361L |
|
/********************** FlexRay constants 1400 - 1409 *************************/ |
|
#define XST_FR_TX_ERROR 1400 |
#define XST_FR_TX_BUSY 1401 |
#define XST_FR_BUF_LOCKED 1402 |
#define XST_FR_NO_BUF 1403 |
|
/****************** USB constants 1410 - 1420 *******************************/ |
|
#define XST_USB_ALREADY_CONFIGURED 1410 |
#define XST_USB_BUF_ALIGN_ERROR 1411 |
#define XST_USB_NO_DESC_AVAILABLE 1412 |
#define XST_USB_BUF_TOO_BIG 1413 |
#define XST_USB_NO_BUF 1414 |
|
/****************** HWICAP constants 1421 - 1429 *****************************/ |
|
#define XST_HWICAP_WRITE_DONE 1421 |
|
|
/****************** AXI VDMA constants 1430 - 1440 *****************************/ |
|
#define XST_VDMA_MISMATCH_ERROR 1430 |
|
/*********************** NAND Flash statuses 1441 - 1459 *********************/ |
|
#define XST_NAND_BUSY 1441L /* Flash is erasing or |
* programming |
*/ |
#define XST_NAND_READY 1442L /* Flash is ready for commands |
*/ |
#define XST_NAND_ERROR 1443L /* Flash had detected an |
* internal error. |
*/ |
#define XST_NAND_PART_NOT_SUPPORTED 1444L /* Flash type not supported by |
* driver |
*/ |
#define XST_NAND_OPT_NOT_SUPPORTED 1445L /* Operation not supported |
*/ |
#define XST_NAND_TIMEOUT_ERROR 1446L /* Programming or erase |
* operation aborted due to a |
* timeout |
*/ |
#define XST_NAND_ADDRESS_ERROR 1447L /* Accessed flash outside its |
* addressible range |
*/ |
#define XST_NAND_ALIGNMENT_ERROR 1448L /* Write alignment error |
*/ |
#define XST_NAND_PARAM_PAGE_ERROR 1449L /* Failed to read parameter |
* page of the device |
*/ |
#define XST_NAND_CACHE_ERROR 1450L /* Flash page buffer error |
*/ |
|
#define XST_NAND_WRITE_PROTECTED 1451L /* Flash is write protected |
*/ |
|
/**************************** Type Definitions *******************************/ |
|
typedef s32 XStatus; |
|
/***************** Macros (Inline Functions) Definitions *********************/ |
|
|
/************************** Function Prototypes ******************************/ |
|
#ifdef __cplusplus |
} |
#endif |
|
#endif /* end of protection macro */ |
/trunk/sw/dev/test_main/src/_hdl/bsp/libsrc/axidma_v9_0/src/xaxidma.c
0,0 → 1,974
/****************************************************************************** |
* |
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. |
* |
* Permission is hereby granted, free of charge, to any person obtaining a copy |
* of this software and associated documentation files (the "Software"), to deal |
* in the Software without restriction, including without limitation the rights |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
* copies of the Software, and to permit persons to whom the Software is |
* furnished to do so, subject to the following conditions: |
* |
* The above copyright notice and this permission notice shall be included in |
* all copies or substantial portions of the Software. |
* |
* Use of the Software is limited solely to applications: |
* (a) running on a Xilinx device, or |
* (b) that interact with a Xilinx device through a bus or interconnect. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF |
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
* SOFTWARE. |
* |
* Except as contained in this notice, the name of the Xilinx shall not be used |
* in advertising or otherwise to promote the sale, use or other dealings in |
* this Software without prior written authorization from Xilinx. |
* |
******************************************************************************/ |
/*****************************************************************************/ |
/** |
* |
* @file xaxidma.c |
* @addtogroup axidma_v9_0 |
* @{ |
* |
* This file implements DMA engine-wise initialization and control functions. |
* For more information on the implementation of this driver, see xaxidma.h. |
* |
* <pre> |
* MODIFICATION HISTORY: |
* |
* Ver Who Date Changes |
* ----- ---- -------- ------------------------------------------------------- |
* 1.00a jz 05/18/10 First release |
* 2.00a jz 08/10/10 Second release, added in xaxidma_g.c, xaxidma_sinit.c, |
* updated tcl file, added xaxidma_porting_guide.h |
* 3.00a jz 11/22/10 Support IP core parameters change |
* 4.00a rkv 02/22/11 Added support for simple DMA mode |
* New API added for simple DMA mode are |
* - XAxiDma_Busy |
* - XAxiDma_SimpleTransfer |
* 6.00a srt 01/24/12 Added support for Multi-Channel DMA mode. |
* - Changed APIs: |
* * XAxiDma_Start(XAxiDma * InstancePtr, int RingIndex) |
* * XAxiDma_Started(XAxiDma * InstancePtr, int RingIndex) |
* * XAxiDma_Pause(XAxiDma * InstancePtr, int RingIndex) |
* * XAxiDma_Resume(XAxiDma * InstancePtr, int RingIndex) |
* * XAxiDma_SimpleTransfer(XAxiDma *InstancePtr, |
* u32 BuffAddr, u32 Length, |
* int Direction, int RingIndex) |
* - New API: |
* * XAxiDma_SelectKeyHole(XAxiDma *InstancePtr, |
* int Direction, int Select) |
* 7.00a srt 06/18/12 All the APIs changed in v6_00_a are reverted back for |
* backward compatibility. |
* 7.01a srt 10/26/12 Fixed issue with driver as it fails with IP version |
* < 6.00a as the parameter C_NUM_*_CHANNELS is not |
* applicable. |
* 8.0 srt 01/29/14 Added support for Micro DMA Mode and Cyclic mode of |
* operations. |
* - New API: |
* * XAxiDma_SelectCyclicMode(XAxiDma *InstancePtr, |
* int Direction, int Select) |
* |
* </pre> |
******************************************************************************/ |
|
/***************************** Include Files *********************************/ |
|
#include "xaxidma.h" |
|
/************************** Constant Definitions *****************************/ |
|
/* Loop counter to check reset done |
*/ |
#define XAXIDMA_RESET_TIMEOUT 500 |
|
/**************************** Type Definitions *******************************/ |
|
|
/***************** Macros (Inline Functions) Definitions *********************/ |
|
|
/************************** Function Prototypes ******************************/ |
static int XAxiDma_Start(XAxiDma * InstancePtr); |
static int XAxiDma_Started(XAxiDma * InstancePtr); |
|
/************************** Variable Definitions *****************************/ |
|
/*****************************************************************************/ |
/** |
* This function initializes a DMA engine. This function must be called |
* prior to using a DMA engine. Initializing a engine includes setting |
* up the register base address, setting up the instance data, and ensuring the |
* hardware is in a quiescent state. |
* |
* @param InstancePtr is a pointer to the DMA engine instance to be |
* worked on. |
* @param Config is a pointer to an XAxiDma_Config structure. It contains |
* the information about the hardware build, including base |
* address,and whether status control stream (StsCntrlStrm), MM2S |
* and S2MM are included in the build. |
* |
* @return |
* - XST_SUCCESS for successful initialization |
* - XST_INVALID_PARAM if pointer to the configuration structure |
* is NULL |
* - XST_DMA_ERROR if reset operation failed at the end of |
* initialization |
* |
* @note We assume the hardware building tool will check and error out |
* for a hardware build that has no transfer channels. |
*****************************************************************************/ |
int XAxiDma_CfgInitialize(XAxiDma * InstancePtr, XAxiDma_Config *Config) |
{ |
u32 BaseAddr; |
int TimeOut; |
int Index; |
u32 MaxTransferLen; |
|
InstancePtr->Initialized = 0; |
|
if(!Config) { |
return XST_INVALID_PARAM; |
} |
|
BaseAddr = Config->BaseAddr; |
|
/* Setup the instance */ |
memset(InstancePtr, 0, sizeof(XAxiDma)); |
InstancePtr->RegBase = BaseAddr; |
|
/* Get hardware setting information from the configuration structure |
*/ |
InstancePtr->HasMm2S = Config->HasMm2S; |
InstancePtr->HasS2Mm = Config->HasS2Mm; |
|
InstancePtr->HasSg = Config->HasSg; |
|
InstancePtr->MicroDmaMode = Config->MicroDmaMode; |
InstancePtr->AddrWidth = Config->AddrWidth; |
|
/* Get the number of channels */ |
InstancePtr->TxNumChannels = Config->Mm2sNumChannels; |
InstancePtr->RxNumChannels = Config->S2MmNumChannels; |
|
/* This condition is for IP version < 6.00a */ |
if (!InstancePtr->TxNumChannels) |
InstancePtr->TxNumChannels = 1; |
if (!InstancePtr->RxNumChannels) |
InstancePtr->RxNumChannels = 1; |
|
if ((InstancePtr->RxNumChannels > 1) || |
(InstancePtr->TxNumChannels > 1)) { |
MaxTransferLen = |
XAXIDMA_MCHAN_MAX_TRANSFER_LEN; |
} |
else { |
MaxTransferLen = |
XAXIDMA_MAX_TRANSFER_LEN; |
} |
|
/* Initialize the ring structures */ |
InstancePtr->TxBdRing.RunState = AXIDMA_CHANNEL_HALTED; |
InstancePtr->TxBdRing.IsRxChannel = 0; |
if (!InstancePtr->MicroDmaMode) { |
InstancePtr->TxBdRing.MaxTransferLen = MaxTransferLen; |
} |
else { |
/* In MicroDMA mode, Maximum length that can be transferred |
* is '(Memory Data Width / 4) * Burst Size' |
*/ |
InstancePtr->TxBdRing.MaxTransferLen = |
((Config->Mm2SDataWidth / 4) * |
Config->Mm2SBurstSize); |
} |
InstancePtr->TxBdRing.RingIndex = 0; |
|
for (Index = 0; Index < InstancePtr->RxNumChannels; Index++) { |
InstancePtr->RxBdRing[Index].RunState |
= AXIDMA_CHANNEL_HALTED; |
InstancePtr->RxBdRing[Index].IsRxChannel = 1; |
InstancePtr->RxBdRing[Index].RingIndex = Index; |
} |
|
if (InstancePtr->HasMm2S) { |
InstancePtr->TxBdRing.ChanBase = |
BaseAddr + XAXIDMA_TX_OFFSET; |
InstancePtr->TxBdRing.HasStsCntrlStrm = |
Config->HasStsCntrlStrm; |
if (InstancePtr->AddrWidth > 32) |
InstancePtr->TxBdRing.Addr_ext = 1; |
else |
InstancePtr->TxBdRing.Addr_ext = 0; |
|
InstancePtr->TxBdRing.HasDRE = Config->HasMm2SDRE; |
InstancePtr->TxBdRing.DataWidth = |
((unsigned int)Config->Mm2SDataWidth >> 3); |
} |
|
if (InstancePtr->HasS2Mm) { |
for (Index = 0; |
Index < InstancePtr->RxNumChannels; Index++) { |
InstancePtr->RxBdRing[Index].ChanBase = |
BaseAddr + XAXIDMA_RX_OFFSET; |
InstancePtr->RxBdRing[Index].HasStsCntrlStrm = |
Config->HasStsCntrlStrm; |
InstancePtr->RxBdRing[Index].HasDRE = |
Config->HasS2MmDRE; |
InstancePtr->RxBdRing[Index].DataWidth = |
((unsigned int)Config->S2MmDataWidth >> 3); |
|
if (!InstancePtr->MicroDmaMode) { |
InstancePtr->RxBdRing[Index].MaxTransferLen = |
MaxTransferLen; |
} |
else { |
/* In MicroDMA mode, Maximum length that can be transferred |
* is '(Memory Data Width / 4) * Burst Size' |
*/ |
InstancePtr->RxBdRing[Index].MaxTransferLen = |
((Config->S2MmDataWidth / 4) * |
Config->S2MmBurstSize); |
} |
if (InstancePtr->AddrWidth > 32) |
InstancePtr->RxBdRing[Index].Addr_ext = 1; |
else |
InstancePtr->RxBdRing[Index].Addr_ext = 0; |
} |
} |
|
/* Reset the engine so the hardware starts from a known state |
*/ |
XAxiDma_Reset(InstancePtr); |
|
/* At the initialization time, hardware should finish reset quickly |
*/ |
TimeOut = XAXIDMA_RESET_TIMEOUT; |
|
while (TimeOut) { |
|
if(XAxiDma_ResetIsDone(InstancePtr)) { |
break; |
} |
|
TimeOut -= 1; |
|
} |
|
if (!TimeOut) { |
xdbg_printf(XDBG_DEBUG_ERROR, "Failed reset in" |
"initialize\r\n"); |
|
/* Need system hard reset to recover |
*/ |
InstancePtr->Initialized = 0; |
return XST_DMA_ERROR; |
} |
|
/* Initialization is successful |
*/ |
InstancePtr->Initialized = 1; |
|
return XST_SUCCESS; |
} |
|
/*****************************************************************************/ |
/** |
* Reset both TX and RX channels of a DMA engine. |
* |
* Reset one channel resets the whole AXI DMA engine. |
* |
* Any DMA transaction in progress will finish gracefully before engine starts |
* reset. Any other transactions that have been submitted to hardware will be |
* discarded by the hardware. |
* |
* @param InstancePtr is a pointer to the DMA engine instance to be |
* worked on. |
* |
* @return None |
* |
* @note After the reset: |
* - All interrupts are disabled. |
* - Engine is halted |
* |
******************************************************************************/ |
void XAxiDma_Reset(XAxiDma * InstancePtr) |
{ |
u32 RegBase; |
XAxiDma_BdRing *TxRingPtr; |
XAxiDma_BdRing *RxRingPtr; |
int RingIndex; |
|
TxRingPtr = XAxiDma_GetTxRing(InstancePtr); |
|
/* Save the locations of current BDs both rings are working on |
* before the reset so later we can resume the rings smoothly. |
*/ |
if(XAxiDma_HasSg(InstancePtr)){ |
XAxiDma_BdRingSnapShotCurrBd(TxRingPtr); |
|
for (RingIndex = 0; RingIndex < InstancePtr->RxNumChannels; |
RingIndex++) { |
RxRingPtr = XAxiDma_GetRxIndexRing(InstancePtr, |
RingIndex); |
XAxiDma_BdRingSnapShotCurrBd(RxRingPtr); |
} |
} |
|
/* Reset |
*/ |
if (InstancePtr->HasMm2S) { |
RegBase = InstancePtr->RegBase + XAXIDMA_TX_OFFSET; |
} |
else { |
RegBase = InstancePtr->RegBase + XAXIDMA_RX_OFFSET; |
} |
|
XAxiDma_WriteReg(RegBase, XAXIDMA_CR_OFFSET, XAXIDMA_CR_RESET_MASK); |
|
/* Set TX/RX Channel state */ |
if (InstancePtr->HasMm2S) { |
TxRingPtr->RunState = AXIDMA_CHANNEL_HALTED; |
} |
|
for (RingIndex = 0; RingIndex < InstancePtr->RxNumChannels; |
RingIndex++) { |
RxRingPtr = XAxiDma_GetRxIndexRing(InstancePtr, RingIndex); |
if (InstancePtr->HasS2Mm) { |
RxRingPtr->RunState = AXIDMA_CHANNEL_HALTED; |
} |
} |
} |
|
/*****************************************************************************/ |
/** |
* |
* Check whether reset is done |
* |
* @param InstancePtr is a pointer to the DMA engine instance to be |
* worked on. |
* |
* @return |
* - 1 if reset is done. |
* - 0 if reset is not done |
* |
* @note None |
* |
******************************************************************************/ |
int XAxiDma_ResetIsDone(XAxiDma * InstancePtr) |
{ |
u32 RegisterValue; |
XAxiDma_BdRing *TxRingPtr; |
XAxiDma_BdRing *RxRingPtr; |
|
TxRingPtr = XAxiDma_GetTxRing(InstancePtr); |
RxRingPtr = XAxiDma_GetRxRing(InstancePtr); |
|
/* Check transmit channel |
*/ |
if (InstancePtr->HasMm2S) { |
RegisterValue = XAxiDma_ReadReg(TxRingPtr->ChanBase, |
XAXIDMA_CR_OFFSET); |
|
/* Reset is done when the reset bit is low |
*/ |
if(RegisterValue & XAXIDMA_CR_RESET_MASK) { |
|
return 0; |
} |
} |
|
/* Check receive channel |
*/ |
if (InstancePtr->HasS2Mm) { |
RegisterValue = XAxiDma_ReadReg(RxRingPtr->ChanBase, |
XAXIDMA_CR_OFFSET); |
|
/* Reset is done when the reset bit is low |
*/ |
if(RegisterValue & XAXIDMA_CR_RESET_MASK) { |
|
return 0; |
} |
} |
|
return 1; |
} |
/*****************************************************************************/ |
/* |
* Start the DMA engine. |
* |
* Start a halted engine. Processing of BDs is not started. |
* |
* @param InstancePtr is a pointer to the DMA engine instance to be |
* worked on. |
* |
* @return |
* - XST_SUCCESS for success |
* - XST_NOT_SGDMA if the driver instance has not been initialized |
* - XST_DMA_ERROR if starting the hardware channel fails |
* |
* @note None |
* |
*****************************************************************************/ |
static int XAxiDma_Start(XAxiDma * InstancePtr) |
{ |
XAxiDma_BdRing *TxRingPtr; |
XAxiDma_BdRing *RxRingPtr; |
int Status; |
int RingIndex = 0; |
|
if (!InstancePtr->Initialized) { |
|
xdbg_printf(XDBG_DEBUG_ERROR, "Start: Driver not initialized " |
"%d\r\n", InstancePtr->Initialized); |
|
return XST_NOT_SGDMA; |
} |
|
if (InstancePtr->HasMm2S) { |
TxRingPtr = XAxiDma_GetTxRing(InstancePtr); |
|
if (TxRingPtr->RunState == AXIDMA_CHANNEL_HALTED) { |
|
/* Start the channel |
*/ |
if(XAxiDma_HasSg(InstancePtr)) { |
Status = XAxiDma_BdRingStart(TxRingPtr); |
if (Status != XST_SUCCESS) { |
xdbg_printf(XDBG_DEBUG_ERROR, |
"Start hw tx channel failed %d\r\n", |
Status); |
|
return XST_DMA_ERROR; |
} |
} |
else { |
XAxiDma_WriteReg(TxRingPtr->ChanBase, |
XAXIDMA_CR_OFFSET, |
XAxiDma_ReadReg(TxRingPtr->ChanBase, |
XAXIDMA_CR_OFFSET) |
| XAXIDMA_CR_RUNSTOP_MASK); |
} |
TxRingPtr->RunState = AXIDMA_CHANNEL_NOT_HALTED; |
} |
} |
|
if (InstancePtr->HasS2Mm) { |
|
for (RingIndex = 0; RingIndex < InstancePtr->RxNumChannels; |
RingIndex++) { |
RxRingPtr = XAxiDma_GetRxIndexRing(InstancePtr, |
RingIndex); |
|
if (RxRingPtr->RunState != AXIDMA_CHANNEL_HALTED) { |
return XST_SUCCESS; |
} |
|
/* Start the channel |
*/ |
if(XAxiDma_HasSg(InstancePtr)) { |
Status = XAxiDma_BdRingStart(RxRingPtr); |
if (Status != XST_SUCCESS) { |
xdbg_printf(XDBG_DEBUG_ERROR, |
"Start hw tx channel failed %d\r\n", |
Status); |
|
return XST_DMA_ERROR; |
} |
} |
else { |
XAxiDma_WriteReg(RxRingPtr->ChanBase, |
XAXIDMA_CR_OFFSET, |
XAxiDma_ReadReg(RxRingPtr->ChanBase, |
XAXIDMA_CR_OFFSET) | |
XAXIDMA_CR_RUNSTOP_MASK); |
} |
|
RxRingPtr->RunState = AXIDMA_CHANNEL_NOT_HALTED; |
} |
} |
|
return XST_SUCCESS; |
} |
/*****************************************************************************/ |
/** |
* Pause DMA transactions on both channels. |
* |
* If the engine is running and doing transfers, this function does not stop |
* the DMA transactions immediately, because then hardware will throw away |
* our previously queued transfers. All submitted transfers will finish. |
* Transfers submitted after this function will not start until |
* XAxiDma_BdRingStart() or XAxiDma_Resume() is called. |
* |
* @param InstancePtr is a pointer to the DMA engine instance to be |
* worked on. |
* |
* @return |
* - XST_SUCCESS if successful |
* - XST_NOT_SGDMA, if the driver instance is not initialized |
* |
* @note None |
* |
*****************************************************************************/ |
int XAxiDma_Pause(XAxiDma * InstancePtr) |
{ |
XAxiDma_BdRing *TxRingPtr; |
XAxiDma_BdRing *RxRingPtr; |
int RingIndex = 0; |
|
if (!InstancePtr->Initialized) { |
|
xdbg_printf(XDBG_DEBUG_ERROR, "Pause: Driver not initialized" |
" %d\r\n",InstancePtr->Initialized); |
|
return XST_NOT_SGDMA; |
} |
|
if (InstancePtr->HasMm2S) { |
TxRingPtr = XAxiDma_GetTxRing(InstancePtr); |
|
/* If channel is halted, then we do not need to do anything |
*/ |
if(!XAxiDma_HasSg(InstancePtr)) { |
XAxiDma_WriteReg(TxRingPtr->ChanBase, |
XAXIDMA_CR_OFFSET, |
XAxiDma_ReadReg(TxRingPtr->ChanBase, |
XAXIDMA_CR_OFFSET) |
& ~XAXIDMA_CR_RUNSTOP_MASK); |
} |
|
TxRingPtr->RunState = AXIDMA_CHANNEL_HALTED; |
} |
|
if (InstancePtr->HasS2Mm) { |
for (RingIndex = 0; RingIndex < InstancePtr->RxNumChannels; |
RingIndex++) { |
RxRingPtr = XAxiDma_GetRxIndexRing(InstancePtr, RingIndex); |
|
/* If channel is halted, then we do not need to do anything |
*/ |
|
if(!XAxiDma_HasSg(InstancePtr) && !RingIndex) { |
XAxiDma_WriteReg(RxRingPtr->ChanBase, |
XAXIDMA_CR_OFFSET, |
XAxiDma_ReadReg(RxRingPtr->ChanBase, |
XAXIDMA_CR_OFFSET) |
& ~XAXIDMA_CR_RUNSTOP_MASK); |
} |
|
RxRingPtr->RunState = AXIDMA_CHANNEL_HALTED; |
} |
} |
|
return XST_SUCCESS; |
|
} |
|
/*****************************************************************************/ |
/** |
* Resume DMA transactions on both channels. |
* |
* @param InstancePtr is a pointer to the DMA engine instance to be |
* worked on. |
* |
* @return |
* - XST_SUCCESS for success |
* - XST_NOT_SGDMA if the driver instance has not been initialized |
* - XST_DMA_ERROR if one of the channels fails to start |
* |
* @note None |
* |
*****************************************************************************/ |
int XAxiDma_Resume(XAxiDma * InstancePtr) |
{ |
XAxiDma_BdRing *TxRingPtr; |
XAxiDma_BdRing *RxRingPtr; |
int Status; |
int RingIndex = 0; |
|
if (!InstancePtr->Initialized) { |
|
xdbg_printf(XDBG_DEBUG_ERROR, "Resume: Driver not initialized" |
" %d\r\n",InstancePtr->Initialized); |
|
return XST_NOT_SGDMA; |
} |
|
/* If the DMA engine is not running, start it. Start may fail. |
*/ |
if (!XAxiDma_Started(InstancePtr)) { |
Status = XAxiDma_Start(InstancePtr); |
|
if (Status != XST_SUCCESS) { |
xdbg_printf(XDBG_DEBUG_ERROR, "Resume: failed to start" |
" engine %d\r\n", Status); |
|
return Status; |
} |
} |
|
/* Mark the state to be not halted |
*/ |
if (InstancePtr->HasMm2S) { |
TxRingPtr = XAxiDma_GetTxRing(InstancePtr); |
|
if(XAxiDma_HasSg(InstancePtr)) { |
Status = XAxiDma_BdRingStart(TxRingPtr); |
if (Status != XST_SUCCESS) { |
xdbg_printf(XDBG_DEBUG_ERROR, "Resume: failed" |
" to start tx ring %d\r\n", Status); |
|
return XST_DMA_ERROR; |
} |
} |
|
TxRingPtr->RunState = AXIDMA_CHANNEL_NOT_HALTED; |
} |
|
if (InstancePtr->HasS2Mm) { |
for (RingIndex = 0 ; RingIndex < InstancePtr->RxNumChannels; |
RingIndex++) { |
RxRingPtr = XAxiDma_GetRxIndexRing(InstancePtr, RingIndex); |
|
if(XAxiDma_HasSg(InstancePtr)) { |
Status = XAxiDma_BdRingStart(RxRingPtr); |
if (Status != XST_SUCCESS) { |
xdbg_printf(XDBG_DEBUG_ERROR, "Resume: failed" |
"to start rx ring %d\r\n", Status); |
|
return XST_DMA_ERROR; |
} |
} |
|
RxRingPtr->RunState = AXIDMA_CHANNEL_NOT_HALTED; |
} |
} |
|
return XST_SUCCESS; |
} |
|
/*****************************************************************************/ |
/* |
* Check whether the DMA engine is started. |
* |
* @param InstancePtr is a pointer to the DMA engine instance to be |
* worked on. |
* |
* @return |
* - 1 if engine is started |
* - 0 otherwise. |
* |
* @note None |
* |
*****************************************************************************/ |
static int XAxiDma_Started(XAxiDma * InstancePtr) |
{ |
XAxiDma_BdRing *TxRingPtr; |
XAxiDma_BdRing *RxRingPtr; |
|
if (!InstancePtr->Initialized) { |
|
xdbg_printf(XDBG_DEBUG_ERROR, "Started: Driver not initialized" |
" %d\r\n",InstancePtr->Initialized); |
|
return 0; |
} |
|
if (InstancePtr->HasMm2S) { |
TxRingPtr = XAxiDma_GetTxRing(InstancePtr); |
|
if (!XAxiDma_BdRingHwIsStarted(TxRingPtr)) { |
xdbg_printf(XDBG_DEBUG_ERROR, |
"Started: tx ring not started\r\n"); |
|
return 0; |
} |
} |
|
if (InstancePtr->HasS2Mm) { |
RxRingPtr = XAxiDma_GetRxRing(InstancePtr); |
|
if (!XAxiDma_BdRingHwIsStarted(RxRingPtr)) { |
xdbg_printf(XDBG_DEBUG_ERROR, |
"Started: rx ring not started\r\n"); |
|
return 0; |
} |
} |
|
return 1; |
} |
|
/*****************************************************************************/ |
/** |
* This function checks whether specified DMA channel is busy |
* |
* @param InstancePtr is the driver instance we are working on |
* |
* @param Direction is DMA transfer direction, valid values are |
* - XAXIDMA_DMA_TO_DEVICE. |
* - XAXIDMA_DEVICE_TO_DMA. |
* |
* @return - TRUE if channel is busy |
* - FALSE if channel is idle |
* |
* @note None. |
* |
*****************************************************************************/ |
u32 XAxiDma_Busy(XAxiDma *InstancePtr, int Direction) |
{ |
|
return ((XAxiDma_ReadReg(InstancePtr->RegBase + |
(XAXIDMA_RX_OFFSET * Direction), |
XAXIDMA_SR_OFFSET) & |
XAXIDMA_IDLE_MASK) ? FALSE : TRUE); |
} |
|
|
/*****************************************************************************/ |
/** |
* This function Enable or Disable KeyHole Feature |
* |
* @param InstancePtr is the driver instance we are working on |
* |
* @param Direction is DMA transfer direction, valid values are |
* - XAXIDMA_DMA_TO_DEVICE. |
* - XAXIDMA_DEVICE_TO_DMA. |
* @Select Select is the option to enable (TRUE) or disable (FALSE). |
* |
* @return - XST_SUCCESS for success |
* |
* @note None. |
* |
*****************************************************************************/ |
int XAxiDma_SelectKeyHole(XAxiDma *InstancePtr, int Direction, int Select) |
{ |
u32 Value; |
|
Value = XAxiDma_ReadReg(InstancePtr->RegBase + |
(XAXIDMA_RX_OFFSET * Direction), |
XAXIDMA_CR_OFFSET); |
|
if (Select) |
Value |= XAXIDMA_CR_KEYHOLE_MASK; |
else |
Value &= ~XAXIDMA_CR_KEYHOLE_MASK; |
|
XAxiDma_WriteReg(InstancePtr->RegBase + |
(XAXIDMA_RX_OFFSET * Direction), |
XAXIDMA_CR_OFFSET, Value); |
|
return XST_SUCCESS; |
|
} |
|
/*****************************************************************************/ |
/** |
* This function Enable or Disable Cyclic Mode Feature |
* |
* @param InstancePtr is the driver instance we are working on |
* |
* @param Direction is DMA transfer direction, valid values are |
* - XAXIDMA_DMA_TO_DEVICE. |
* - XAXIDMA_DEVICE_TO_DMA. |
* @Select Select is the option to enable (TRUE) or disable (FALSE). |
* |
* @return - XST_SUCCESS for success |
* |
* @note None. |
* |
*****************************************************************************/ |
int XAxiDma_SelectCyclicMode(XAxiDma *InstancePtr, int Direction, int Select) |
{ |
u32 Value; |
|
Value = XAxiDma_ReadReg(InstancePtr->RegBase + |
(XAXIDMA_RX_OFFSET * Direction), |
XAXIDMA_CR_OFFSET); |
|
if (Select) |
Value |= XAXIDMA_CR_CYCLIC_MASK; |
else |
Value &= ~XAXIDMA_CR_CYCLIC_MASK; |
|
XAxiDma_WriteReg(InstancePtr->RegBase + |
(XAXIDMA_RX_OFFSET * Direction), |
XAXIDMA_CR_OFFSET, Value); |
|
return XST_SUCCESS; |
} |
|
/*****************************************************************************/ |
/** |
* This function does one simple transfer submission |
* |
* It checks in the following sequence: |
* - if engine is busy, cannot submit |
* - if engine is in SG mode , cannot submit |
* |
* @param InstancePtr is the pointer to the driver instance |
* @param BuffAddr is the address of the source/destination buffer |
* @param Length is the length of the transfer |
* @param Direction is DMA transfer direction, valid values are |
* - XAXIDMA_DMA_TO_DEVICE. |
* - XAXIDMA_DEVICE_TO_DMA. |
|
* @return |
* - XST_SUCCESS for success of submission |
* - XST_FAILURE for submission failure, maybe caused by: |
* Another simple transfer is still going |
* - XST_INVALID_PARAM if:Length out of valid range [1:8M] |
* Or, address not aligned when DRE is not built in |
* |
* @note This function is used only when system is configured as |
* Simple mode. |
* |
*****************************************************************************/ |
u32 XAxiDma_SimpleTransfer(XAxiDma *InstancePtr, UINTPTR BuffAddr, u32 Length, |
int Direction) |
{ |
u32 WordBits; |
int RingIndex = 0; |
|
/* If Scatter Gather is included then, cannot submit |
*/ |
if (XAxiDma_HasSg(InstancePtr)) { |
xdbg_printf(XDBG_DEBUG_ERROR, "Simple DMA mode is not" |
" supported\r\n"); |
|
return XST_FAILURE; |
} |
|
if(Direction == XAXIDMA_DMA_TO_DEVICE){ |
if ((Length < 1) || |
(Length > InstancePtr->TxBdRing.MaxTransferLen)) { |
return XST_INVALID_PARAM; |
} |
|
if (!InstancePtr->HasMm2S) { |
xdbg_printf(XDBG_DEBUG_ERROR, "MM2S channel is not" |
"supported\r\n"); |
|
return XST_FAILURE; |
} |
|
/* If the engine is doing transfer, cannot submit |
*/ |
|
if(!(XAxiDma_ReadReg(InstancePtr->TxBdRing.ChanBase, |
XAXIDMA_SR_OFFSET) & XAXIDMA_HALTED_MASK)) { |
if (XAxiDma_Busy(InstancePtr,Direction)) { |
xdbg_printf(XDBG_DEBUG_ERROR, |
"Engine is busy\r\n"); |
return XST_FAILURE; |
} |
} |
|
if (!InstancePtr->MicroDmaMode) { |
WordBits = (u32)((InstancePtr->TxBdRing.DataWidth) - 1); |
} |
else { |
WordBits = XAXIDMA_MICROMODE_MIN_BUF_ALIGN; |
} |
|
if ((BuffAddr & WordBits)) { |
|
if (!InstancePtr->TxBdRing.HasDRE) { |
xdbg_printf(XDBG_DEBUG_ERROR, |
"Unaligned transfer without" |
" DRE %x\r\n",(unsigned int)BuffAddr); |
|
return XST_INVALID_PARAM; |
} |
} |
|
|
XAxiDma_WriteReg(InstancePtr->TxBdRing.ChanBase, |
XAXIDMA_SRCADDR_OFFSET, LOWER_32_BITS(BuffAddr)); |
if (InstancePtr->AddrWidth > 32) |
XAxiDma_WriteReg(InstancePtr->TxBdRing.ChanBase, |
XAXIDMA_SRCADDR_MSB_OFFSET, |
UPPER_32_BITS(BuffAddr)); |
|
XAxiDma_WriteReg(InstancePtr->TxBdRing.ChanBase, |
XAXIDMA_CR_OFFSET, |
XAxiDma_ReadReg( |
InstancePtr->TxBdRing.ChanBase, |
XAXIDMA_CR_OFFSET)| XAXIDMA_CR_RUNSTOP_MASK); |
|
/* Writing to the BTT register starts the transfer |
*/ |
XAxiDma_WriteReg(InstancePtr->TxBdRing.ChanBase, |
XAXIDMA_BUFFLEN_OFFSET, Length); |
} |
else if(Direction == XAXIDMA_DEVICE_TO_DMA){ |
if ((Length < 1) || |
(Length > |
InstancePtr->RxBdRing[RingIndex].MaxTransferLen)) { |
return XST_INVALID_PARAM; |
} |
|
|
if (!InstancePtr->HasS2Mm) { |
xdbg_printf(XDBG_DEBUG_ERROR, "S2MM channel is not" |
" supported\r\n"); |
|
return XST_FAILURE; |
} |
|
if(!(XAxiDma_ReadReg(InstancePtr->RxBdRing[RingIndex].ChanBase, |
XAXIDMA_SR_OFFSET) & XAXIDMA_HALTED_MASK)) { |
if (XAxiDma_Busy(InstancePtr,Direction)) { |
xdbg_printf(XDBG_DEBUG_ERROR, |
"Engine is busy\r\n"); |
return XST_FAILURE; |
} |
} |
|
if (!InstancePtr->MicroDmaMode) { |
WordBits = |
(u32)((InstancePtr->RxBdRing[RingIndex].DataWidth) - 1); |
} |
else { |
WordBits = XAXIDMA_MICROMODE_MIN_BUF_ALIGN; |
} |
|
if ((BuffAddr & WordBits)) { |
|
if (!InstancePtr->RxBdRing[RingIndex].HasDRE) { |
xdbg_printf(XDBG_DEBUG_ERROR, |
"Unaligned transfer without" |
" DRE %x\r\n", (unsigned int)BuffAddr); |
|
return XST_INVALID_PARAM; |
} |
} |
|
|
XAxiDma_WriteReg(InstancePtr->RxBdRing[RingIndex].ChanBase, |
XAXIDMA_DESTADDR_OFFSET, LOWER_32_BITS(BuffAddr)); |
if (InstancePtr->AddrWidth > 32) |
XAxiDma_WriteReg(InstancePtr->RxBdRing[RingIndex].ChanBase, |
XAXIDMA_DESTADDR_MSB_OFFSET, |
UPPER_32_BITS(BuffAddr)); |
|
XAxiDma_WriteReg(InstancePtr->RxBdRing[RingIndex].ChanBase, |
XAXIDMA_CR_OFFSET, |
XAxiDma_ReadReg(InstancePtr->RxBdRing[RingIndex].ChanBase, |
XAXIDMA_CR_OFFSET)| XAXIDMA_CR_RUNSTOP_MASK); |
/* Writing to the BTT register starts the transfer |
*/ |
XAxiDma_WriteReg(InstancePtr->RxBdRing[RingIndex].ChanBase, |
XAXIDMA_BUFFLEN_OFFSET, Length); |
|
} |
|
return XST_SUCCESS; |
} |
/** @} */ |
/trunk/sw/dev/test_main/src/_hdl/bsp/libsrc/axidma_v9_0/src/xaxidma.h
0,0 → 1,741
/****************************************************************************** |
* |
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. |
* |
* Permission is hereby granted, free of charge, to any person obtaining a copy |
* of this software and associated documentation files (the "Software"), to deal |
* in the Software without restriction, including without limitation the rights |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
* copies of the Software, and to permit persons to whom the Software is |
* furnished to do so, subject to the following conditions: |
* |
* The above copyright notice and this permission notice shall be included in |
* all copies or substantial portions of the Software. |
* |
* Use of the Software is limited solely to applications: |
* (a) running on a Xilinx device, or |
* (b) that interact with a Xilinx device through a bus or interconnect. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF |
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
* SOFTWARE. |
* |
* Except as contained in this notice, the name of the Xilinx shall not be used |
* in advertising or otherwise to promote the sale, use or other dealings in |
* this Software without prior written authorization from Xilinx. |
* |
******************************************************************************/ |
/*****************************************************************************/ |
/** |
* |
* @file xaxidma.h |
* @addtogroup axidma_v9_0 |
* @{ |
* @details |
* |
* This is the driver API for the AXI DMA engine. |
* |
* For a full description of DMA features, please see the hardware spec. This |
* driver supports the following features: |
* |
* - Scatter-Gather DMA (SGDMA) |
* - Simple DMA |
* - Interrupts |
* - Programmable interrupt coalescing for SGDMA |
* - APIs to manage Buffer Descriptors (BD) movement to and from the SGDMA |
* engine |
* |
* <b>Simple DMA</b> |
* |
* Simple DMA allows the application to define a single transaction between DMA |
* and Device. It has two channels: one from the DMA to Device and the other |
* from Device to DMA. Application has to set the buffer address and |
* length fields to initiate the transfer in respective channel. |
* |
* <b>Transactions</b> |
* |
* The object used to describe a transaction is referred to as a Buffer |
* Descriptor (BD). Buffer descriptors are allocated in the user application. |
* The user application needs to set buffer address, transfer length, and |
* control information for this transfer. The control information includes |
* SOF and EOF. Definition of those masks are in xaxidma_hw.h |
* |
* <b>Scatter-Gather DMA</b> |
* |
* SGDMA allows the application to define a list of transactions in memory which |
* the hardware will process without further application intervention. During |
* this time, the application is free to continue adding more work to keep the |
* Hardware busy. |
* |
* User can check for the completion of transactions through polling the |
* hardware, or interrupts. |
* |
* SGDMA processes whole packets. A packet is defined as a series of |
* data bytes that represent a message. SGDMA allows a packet of data to be |
* broken up into one or more transactions. For example, take an Ethernet IP |
* packet which consists of a 14 byte header followed by a 1 or more bytes of |
* payload. With SGDMA, the application may point a BD to the header and another |
* BD to the payload, then transfer them as a single message. This strategy can |
* make a TCP/IP stack more efficient by allowing it to keep packet header and |
* data in different memory regions instead of assembling packets into |
* contiguous blocks of memory. |
* |
* <b>BD Ring Management</b> |
* |
* BD rings are shared by the software and the hardware. |
* |
* The hardware expects BDs to be setup as a linked list. The DMA hardware walks |
* through the list by following the next pointer field of a completed BD. |
* The hardware stops processing when the just completed BD is the same as the |
* BD specified in the Tail Ptr register in the hardware. |
* |
* The last BD in the ring is linked to the first BD in the ring. |
* |
* All BD management are done inside the driver. The user application should not |
* directly modify the BD fields. Modifications to the BD fields should always |
* go through the specific API functions. |
* |
* Within the ring, the driver maintains four groups of BDs. Each group consists |
* of 0 or more adjacent BDs: |
* |
* - Free: The BDs that can be allocated by the application with |
* XAxiDma_BdRingAlloc(). |
* |
* - Pre-process: The BDs that have been allocated with |
* XAxiDma_BdRingAlloc(). These BDs are under application control. The |
* application modifies these BDs through driver API to prepare them |
* for DMA transactions. |
* |
* - Hardware: The BDs that have been enqueued to hardware with |
* XAxiDma_BdRingToHw(). These BDs are under hardware control and may be in a |
* state of awaiting hardware processing, in process, or processed by |
* hardware. It is considered an error for the application to change BDs |
* while they are in this group. Doing so can cause data corruption and lead |
* to system instability. |
* |
* - Post-process: The BDs that have been processed by hardware and have |
* been extracted from the Hardware group with XAxiDma_BdRingFromHw(). |
* These BDs are under application control. The application can check the |
* transfer status of these BDs. The application use XAxiDma_BdRingFree() |
* to put them into the Free group. |
* |
* BDs are expected to transition in the following way for continuous |
* DMA transfers: |
* <pre> |
* |
* XAxiDma_BdRingAlloc() XAxiDma_BdRingToHw() |
* Free ------------------------> Pre-process ----------------------> Hardware |
* | |
* /|\ | |
* | XAxiDma_BdRingFree() XAxiDma_BdRingFromHw() | |
* +--------------------------- Post-process <----------------------+ |
* |
* </pre> |
* |
* When a DMA transfer is to be cancelled before enqueuing to hardware, |
* application can return the requested BDs to the Free group using |
* XAxiDma_BdRingUnAlloc(), as shown below: |
* <pre> |
* |
* XAxiDma_BdRingUnAlloc() |
* Free <----------------------- Pre-process |
* |
* </pre> |
* |
* The API provides functions for BD list traversal: |
* - XAxiDma_BdRingNext() |
* - XAxiDma_BdRingPrev() |
* |
* These functions should be used with care as they do not understand where |
* one group ends and another begins. |
* |
* <b>SGDMA Descriptor Ring Creation</b> |
* |
* BD ring is created using XAxiDma_BdRingCreate(). The memory for the BD ring |
* is allocated by the application, and it has to be contiguous. Physical |
* address is required to setup the BD ring. |
* |
* The applicaiton can use XAxiDma_BdRingMemCalc() to find out the amount of |
* memory needed for a certain number of BDs. XAxiDma_BdRingCntCalc() can be |
* used to find out how many BDs can be allocated for certain amount of memory. |
* |
* A helper function, XAxiDma_BdRingClone(), can speed up the BD ring setup if |
* the BDs have same types of controls, for example, SOF and EOF. After |
* using the XAxiDma_BdRingClone(), the application only needs to setup the |
* buffer address and transfer length. Note that certain BDs in one packet, |
* for example, the first BD and the last BD, may need to setup special |
* control information. |
* |
* <b>Descriptor Ring State Machine</b> |
* |
* There are two states of the BD ring: |
* |
* - HALTED (H), where hardware is not running |
* |
* - NOT HALTED (NH), where hardware is running |
* |
* The following diagram shows the state transition for the DMA engine: |
* |
* <pre> |
* _____ XAxiDma_StartBdRingHw(), or XAxiDma_BdRingStart(), ______ |
* | | or XAxiDma_Resume() | | |
* | H |----------------------------------------------------->| NH | |
* | |<-----------------------------------------------------| | |
* ----- XAxiDma_Pause() or XAxiDma_Reset() ------ |
* </pre> |
* |
* <b>Interrupt Coalescing</b> |
* |
* SGDMA provides control over the frequency of interrupts through interrupt |
* coalescing. The DMA engine provides two ways to tune the interrupt |
* coalescing: |
* |
* - The packet threshold counter. Interrupt will fire once the |
* programmable number of packets have been processed by the engine. |
* |
* - The packet delay timer counter. Interrupt will fire once the |
* programmable amount of time has passed after processing the last packet, |
* and no new packets to process. Note that the interrupt will only fire if |
* at least one packet has been processed. |
* |
* <b> Interrupt </b> |
* |
* Interrupts are handled by the user application. Each DMA channel has its own |
* interrupt ID. The driver provides APIs to enable/disable interrupt, |
* and tune the interrupt frequency regarding to packet processing frequency. |
* |
* <b> Software Initialization </b> |
* |
* |
* To use the Simple mode DMA engine for transfers, the following setup is |
* required: |
* |
* - DMA Initialization using XAxiDma_CfgInitialize() function. This step |
* initializes a driver instance for the given DMA engine and resets the |
* engine. |
* |
* - Enable interrupts if chosen to use interrupt mode. The application is |
* responsible for setting up the interrupt system, which includes providing |
* and connecting interrupt handlers and call back functions, before |
* enabling the interrupts. |
* |
* - Set the buffer address and length field in respective channels to start |
* the DMA transfer |
* |
* To use the SG mode DMA engine for transfers, the following setup are |
* required: |
* |
* - DMA Initialization using XAxiDma_CfgInitialize() function. This step |
* initializes a driver instance for the given DMA engine and resets the |
* engine. |
* |
* - BD Ring creation. A BD ring is needed per DMA channel and can be built by |
* calling XAxiDma_BdRingCreate(). |
* |
* - Enable interrupts if chose to use interrupt mode. The application is |
* responsible for setting up the interrupt system, which includes providing |
* and connecting interrupt handlers and call back functions, before |
* enabling the interrupts. |
* |
* - Start a DMA transfer: Call XAxiDma_BdRingStart() to start a transfer for |
* the first time or after a reset, and XAxiDma_BdRingToHw() if the channel |
* is already started. Calling XAxiDma_BdRingToHw() when a DMA channel is not |
* running will not put the BDs to the hardware, and the BDs will be processed |
* later when the DMA channel is started through XAxiDma_BdRingStart(). |
* |
* <b> How to start DMA transactions </b> |
* |
* The user application uses XAxiDma_BdRingToHw() to submit BDs to the hardware |
* to start DMA transfers. |
* |
* For both channels, if the DMA engine is currently stopped (using |
* XAxiDma_Pause()), the newly added BDs will be accepted but not processed |
* until the DMA engine is started, using XAxiDma_BdRingStart(), or resumed, |
* using XAxiDma_Resume(). |
* |
* <b> Software Post-Processing on completed DMA transactions </b> |
* |
* If the interrupt system has been set up and the interrupts are enabled, |
* a DMA channels notifies the software about the completion of a transfer |
* through interrupts. Otherwise, the user application can poll for |
* completions of the BDs, using XAxiDma_BdRingFromHw() or |
* XAxiDma_BdHwCompleted(). |
* |
* - Once BDs are finished by a channel, the application first needs to fetch |
* them from the channel using XAxiDma_BdRingFromHw(). |
* |
* - On the TX side, the application now could free the data buffers attached to |
* those BDs as the data in the buffers has been transmitted. |
* |
* - On the RX side, the application now could use the received data in the |
* buffers attached to those BDs. |
* |
* - For both channels, completed BDs need to be put back to the Free group |
* using XAxiDma_BdRingFree(), so they can be used for future transactions. |
* |
* - On the RX side, it is the application's responsibility to have BDs ready |
* to receive data at any time. Otherwise, the RX channel refuses to |
* accept any data if it has no RX BDs. |
* |
* <b> Examples </b> |
* |
* We provide five examples to show how to use the driver API: |
* - One for SG interrupt mode (xaxidma_example_sg_intr.c), multiple BD/packets transfer |
* - One for SG polling mode (xaxidma_example_sg_poll.c), single BD transfer. |
* - One for SG polling mode (xaxidma_poll_multi_pkts.c), multiple BD/packets transfer |
* - One for simple polling mode (xaxidma_example_simple_poll.c) |
* - One for simple Interrupt mode (xaxidma_example_simple_intr.c) |
* |
* <b> Address Translation </b> |
* |
* All buffer addresses and BD addresses for the hardware are physical |
* addresses. The user application is responsible to provide physical buffer |
* address for the BD upon BD ring creation. The user application accesses BD |
* through its virtual addess. The driver maintains the address translation |
* between the physical and virtual address for BDs. |
* |
* <b> Cache Coherency </b> |
* |
* This driver expects all application buffers attached to BDs to be in cache |
* coherent memory. If cache is used in the system, buffers for transmit MUST |
* be flushed from the cache before passing the associated BD to this driver. |
* Buffers for receive MUST be invalidated before accessing the data. |
* |
* <b> Alignment </b> |
* |
* For BDs: |
* |
* Minimum alignment is defined by the constant XAXIDMA_BD_MINIMUM_ALIGNMENT. |
* This is the smallest alignment allowed by both hardware and software for them |
* to properly work. |
* |
* If the descriptor ring is to be placed in cached memory, alignment also MUST |
* be at least the processor's cache-line size. Otherwise, system instability |
* occurs. For alignment larger than the cache line size, multiple cache line |
* size alignment is required. |
* |
* Aside from the initial creation of the descriptor ring (see |
* XAxiDma_BdRingCreate()), there are no other run-time checks for proper |
* alignment of BDs. |
* |
* For application data buffers: |
* |
* Application data buffers may reside on any alignment if DRE is built into the |
* hardware. Otherwise, application data buffer must be word-aligned. The word |
* is defined by XPAR_AXIDMA_0_M_AXIS_MM2S_TDATA_WIDTH for transmit and |
* XPAR_AXIDMA_0_S_AXIS_S2MM_TDATA_WIDTH for receive. |
* |
* For scatter gather transfers that have more than one BDs in the chain of BDs, |
* Each BD transfer length must be multiple of word too. Otherwise, internal |
* error happens in the hardware. |
* |
* <b> Error Handling </b> |
* |
* The DMA engine will halt on all error conditions. It requires the software |
* to do a reset before it can start process new transfer requests. |
* |
* <b> Restart After Stopping </b> |
* |
* After the DMA engine has been stopped (through reset or reset after an error) |
* the software keeps track of the current BD pointer when reset happens, and |
* processing of BDs can be resumed through XAxiDma_BdRingStart(). |
* |
* <b> Limitations </b> |
* |
* This driver does not have any mechanisms for mutual exclusion. It is up to |
* the application to provide this protection. |
* |
* <b> Hardware Defaults & Exclusive Use </b> |
* |
* After the initialization or reset, the DMA engine is in the following |
* default mode: |
* - All interrupts are disabled. |
* |
* - Interrupt coalescing counter is 1. |
* |
* - The DMA engine is not running (halted). Each DMA channel is started |
* separately, using XAxiDma_StartBdRingHw() if no BDs are setup for transfer |
* yet, or XAxiDma_BdRingStart() otherwise. |
* |
* The driver has exclusive use of the registers and BDs. All accesses to the |
* registers and BDs should go through the driver interface. |
* |
* <b> Debug Print </b> |
* |
* To see the debug print for the driver, please put "-DDEBUG" as the extra |
* compiler flags in software platform settings. Also comment out the line in |
* xdebug.h: "#undef DEBUG". |
* |
* <b>Changes From v1.00a</b> |
* |
* . We have changes return type for XAxiDma_BdSetBufAddr() from void to int |
* . We added XAxiDma_LookupConfig() so that user does not need to look for the |
* hardware settings anymore. |
* |
* <pre> |
* MODIFICATION HISTORY: |
* |
* Ver Who Date Changes |
* ----- ---- -------- ------------------------------------------------------- |
* 1.00a jz 05/18/10 First release |
* 2.00a jz 08/10/10 Second release, added in xaxidma_g.c, xaxidma_sinit.c, |
* updated tcl file, added xaxidma_porting_guide.h |
* 3.00a jz 11/22/10 Support IP core parameters change |
* 4.00a rkv 02/22/11 Added support for simple DMA mode |
* New API added for simple DMA mode are |
* - XAxiDma_Busy |
* - XAxiDma_SimpleTransfer |
* New Macros added for simple DMA mode are |
* - XAxiDma_HasSg |
* - XAxiDma_IntrEnable |
* - XAxiDma_IntrGetEnabled |
* - XAxiDma_IntrDisable |
* - XAxiDma_IntrGetIrq |
* - XAxiDma_IntrAckIrq |
* 5.00a srt 08/25/11 Added support for memory barrier and modified |
* Cache Macros to have a common API for Microblaze |
* and Zynq. |
* 6.00a srt 01/24/12 Added support for Multi-Channel DMA mode. |
* - Changed APIs: |
* * XAxiDma_GetRxRing(InstancePtr, RingIndex) |
* * XAxiDma_Start(XAxiDma * InstancePtr, int RingIndex) |
* * XAxiDma_Started(XAxiDma * InstancePtr, int RingIndex) |
* * XAxiDma_Pause(XAxiDma * InstancePtr, int RingIndex) |
* * XAxiDma_Resume(XAxiDma * InstancePtr, int RingIndex) |
* * XAxiDma_SimpleTransfer(XAxiDma *InstancePtr, |
* u32 BuffAddr, u32 Length, |
* int Direction, int RingIndex) |
* * XAxiDma_StartBdRingHw(XAxiDma_BdRing * RingPtr, |
* int RingIndex) |
* * XAxiDma_BdRingStart(XAxiDma_BdRing * RingPtr, |
* int RingIndex) |
* * XAxiDma_BdRingToHw(XAxiDma_BdRing * RingPtr, |
* int NumBd, XAxiDma_Bd * BdSetPtr, int RingIndex) |
* * XAxiDma_BdRingDumpRegs(XAxiDma_BdRing * RingPtr, |
* int RingIndex) |
* * XAxiDma_BdRingSnapShotCurrBd(XAxiDma_BdRing * RingPtr, |
* int RingIndex) |
* * XAxiDma_BdSetLength(XAxiDma_Bd *BdPtr, |
* u32 LenBytes, u32 LengthMask) |
* * XAxiDma_BdGetActualLength(BdPtr, LengthMask) |
* * XAxiDma_BdGetLength(BdPtr, LengthMask) |
* - New APIs |
* * XAxiDma_SelectKeyHole(XAxiDma *InstancePtr, |
* int Direction, int Select) |
* * XAxiDma_UpdateBdRingCDesc(XAxiDma_BdRing * RingPtr, |
* int RingIndex) |
* 7.00a srt 06/18/12 All the APIs changed in v6_00_a are reverted back for |
* backward compatibility. |
* - New API: |
* XAxiDma_GetRxIndexRing(InstancePtr, RingIndex) |
* 7.01a srt 10/26/12 - Fixed issue with driver as it fails with IP version |
* < 6.00a as the parameter C_NUM_*_CHANNELS is not |
* applicable. |
* - Changed the logic of MCDMA BD fields Set APIs, to |
* clear the field first and then set it. |
* 7.02a srt 01/23/13 Replaced *_TDATA_WIDTH parameters to *_DATA_WIDTH |
* (CR 691867) |
* Updated DDR base address for IPI designs (CR 703656). |
* 8.0 adk 19/12/13 Updated as per the New Tcl API's |
* srt 01/29/14 Added support for Micro DMA Mode and cyclic mode of |
* operations. |
* - New APIs: |
* * XAxiDma_SelectCyclicMode(XAxiDma *InstancePtr, |
* int Direction, int Select) |
* * XAxiDma_BdSetBufAddrMicroMode(XAxiDma_Bd*, u32) |
* 8.1 adk 20/01/15 Added support for peripheral test. Created the self |
* test example to include it on peripheral test's(CR#823144). |
* 8.1 adk 29/01/15 Added the sefltest api (XAxiDma_Selftest) to the driver source files |
* (xaxidma_selftest.c) and called this from the selftest example |
* 9.0 adk 27/07/15 Added support for 64-bit Addressing. |
* 9.0 adk 19/08/15 Fixed CR#873125 DMA SG Mode example tests are failing on |
* HW in 2015.3. |
* |
* </pre> |
* |
******************************************************************************/ |
|
#ifndef XAXIDMA_H_ /* prevent circular inclusions */ |
#define XAXIDMA_H_ |
|
#ifdef __cplusplus |
extern "C" { |
#endif |
|
/***************************** Include Files *********************************/ |
#include "xaxidma_bdring.h" |
#ifdef __MICROBLAZE__ |
#include "xenv.h" |
#else |
#include <string.h> |
#include "xil_cache.h" |
#endif |
|
/************************** Constant Definitions *****************************/ |
|
|
/**************************** Type Definitions *******************************/ |
|
/** |
* The XAxiDma driver instance data. An instance must be allocated for each DMA |
* engine in use. |
*/ |
typedef struct XAxiDma { |
u32 RegBase; /* Virtual base address of DMA engine */ |
|
int HasMm2S; /* Has transmit channel */ |
int HasS2Mm; /* Has receive channel */ |
int Initialized; /* Driver has been initialized */ |
int HasSg; |
|
XAxiDma_BdRing TxBdRing; /* BD container management for TX channel */ |
XAxiDma_BdRing RxBdRing[16]; /* BD container management for RX channel */ |
int TxNumChannels; |
int RxNumChannels; |
int MicroDmaMode; |
int AddrWidth; /**< Address Width */ |
} XAxiDma; |
|
/** |
* The configuration structure for AXI DMA engine |
* |
* This structure passes the hardware building information to the driver |
*/ |
typedef struct { |
u32 DeviceId; |
u32 BaseAddr; |
|
int HasStsCntrlStrm; |
int HasMm2S; |
int HasMm2SDRE; |
int Mm2SDataWidth; |
int HasS2Mm; |
int HasS2MmDRE; |
int S2MmDataWidth; |
int HasSg; |
int Mm2sNumChannels; |
int S2MmNumChannels; |
int Mm2SBurstSize; |
int S2MmBurstSize; |
int MicroDmaMode; |
int AddrWidth; /**< Address Width */ |
} XAxiDma_Config; |
|
|
/***************** Macros (Inline Functions) Definitions *********************/ |
/*****************************************************************************/ |
/** |
* Get Transmit (Tx) Ring ptr |
* |
* Warning: This has a different API than the LLDMA driver. It now returns |
* the pointer to the BD ring. |
* |
* @param InstancePtr is a pointer to the DMA engine instance to be |
* worked on. |
* |
* @return Pointer to the Tx Ring |
* |
* @note C-style signature: |
* XAxiDma_BdRing * XAxiDma_GetTxRing(XAxiDma * InstancePtr) |
* This function is used only when system is configured as SG mode |
* |
*****************************************************************************/ |
#define XAxiDma_GetTxRing(InstancePtr) \ |
(&((InstancePtr)->TxBdRing)) |
|
/*****************************************************************************/ |
/** |
* Get Receive (Rx) Ring ptr |
* |
* Warning: This has a different API than the LLDMA driver. It now returns |
* the pointer to the BD ring. |
* |
* @param InstancePtr is a pointer to the DMA engine instance to be |
* worked on. |
* |
* @return Pointer to the Rx Ring |
* |
* @note |
* C-style signature: |
* XAxiDma_BdRing * XAxiDma_GetRxRing(XAxiDma * InstancePtr) |
* This function is used only when system is configured as SG mode |
* |
*****************************************************************************/ |
#define XAxiDma_GetRxRing(InstancePtr) \ |
(&((InstancePtr)->RxBdRing[0])) |
|
/*****************************************************************************/ |
/** |
* Get Receive (Rx) Ring ptr of a Index |
* |
* Warning: This has a different API than the LLDMA driver. It now returns |
* the pointer to the BD ring. |
* |
* @param InstancePtr is a pointer to the DMA engine instance to be |
* worked on. |
* @param RingIndex is the channel Index. |
* |
* @return Pointer to the Rx Ring |
* |
* @note |
* C-style signature: |
* XAxiDma_BdRing * XAxiDma_GetRxIndexRing(XAxiDma * InstancePtr, |
int RingIndex) |
* This function is used only when system is configured as SG mode |
* |
*****************************************************************************/ |
#define XAxiDma_GetRxIndexRing(InstancePtr, RingIndex) \ |
(&((InstancePtr)->RxBdRing[RingIndex])) |
|
/*****************************************************************************/ |
/** |
* This function checks whether system is configured as Simple or |
* Scatter Gather mode |
* |
* @param InstancePtr is a pointer to the DMA engine instance to be |
* worked on. |
* |
* @return |
* - TRUE if configured as SG mode |
* - FALSE if configured as simple mode |
* |
* @note None |
* |
*****************************************************************************/ |
#define XAxiDma_HasSg(InstancePtr) ((InstancePtr)->HasSg) ? TRUE : FALSE |
|
/*****************************************************************************/ |
/** |
* This function enables interrupts specified by the Mask in specified |
* direction, Interrupts that are not in the mask are not affected. |
* |
* @param InstancePtr is the driver instance we are working on |
* @param Mask is the mask for the interrupts to be enabled |
* @param Direction is DMA transfer direction, valid values are |
* - XAXIDMA_DMA_TO_DEVICE. |
* - XAXIDMA_DEVICE_TO_DMA. |
* @return None |
* |
* @note None |
* |
*****************************************************************************/ |
#define XAxiDma_IntrEnable(InstancePtr, Mask, Direction) \ |
XAxiDma_WriteReg((InstancePtr)->RegBase + \ |
(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_CR_OFFSET, \ |
(XAxiDma_ReadReg((InstancePtr)->RegBase + \ |
(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_CR_OFFSET)) \ |
| (Mask & XAXIDMA_IRQ_ALL_MASK)) |
|
|
/*****************************************************************************/ |
/** |
* This function gets the mask for the interrupts that are currently enabled |
* |
* @param InstancePtr is the driver instance we are working on |
* @param Direction is DMA transfer direction, valid values are |
* - XAXIDMA_DMA_TO_DEVICE. |
* - XAXIDMA_DEVICE_TO_DMA. |
* |
* @return The bit mask for the interrupts that are currently enabled |
* |
* @note None |
* |
*****************************************************************************/ |
#define XAxiDma_IntrGetEnabled(InstancePtr, Direction) \ |
XAxiDma_ReadReg((InstancePtr)->RegBase + \ |
(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_CR_OFFSET) &\ |
XAXIDMA_IRQ_ALL_MASK) |
|
|
|
/*****************************************************************************/ |
/** |
* This function disables interrupts specified by the Mask. Interrupts that |
* are not in the mask are not affected. |
* |
* @param InstancePtr is the driver instance we are working on |
* @param Mask is the mask for the interrupts to be disabled |
* @param Direction is DMA transfer direction, valid values are |
* - XAXIDMA_DMA_TO_DEVICE. |
* - XAXIDMA_DEVICE_TO_DMA. |
* @return None |
* |
* @note None |
* |
*****************************************************************************/ |
#define XAxiDma_IntrDisable(InstancePtr, Mask, Direction) \ |
XAxiDma_WriteReg((InstancePtr)->RegBase + \ |
(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_CR_OFFSET, \ |
(XAxiDma_ReadReg((InstancePtr)->RegBase + \ |
(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_CR_OFFSET)) \ |
& ~(Mask & XAXIDMA_IRQ_ALL_MASK)) |
|
|
/*****************************************************************************/ |
/** |
* This function gets the interrupts that are asserted. |
* |
* @param InstancePtr is the driver instance we are working on |
* @param Direction is DMA transfer direction, valid values are |
* - XAXIDMA_DMA_TO_DEVICE. |
* - XAXIDMA_DEVICE_TO_DMA. |
* |
* @return The bit mask for the interrupts asserted. |
* |
* @note None |
* |
*****************************************************************************/ |
#define XAxiDma_IntrGetIrq(InstancePtr, Direction) \ |
(XAxiDma_ReadReg((InstancePtr)->RegBase + \ |
(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_SR_OFFSET) &\ |
XAXIDMA_IRQ_ALL_MASK) |
|
/*****************************************************************************/ |
/** |
* This function acknowledges the interrupts that are specified in Mask |
* |
* @param InstancePtr is the driver instance we are working on |
* @param Mask is the mask for the interrupts to be acknowledge |
* @param Direction is DMA transfer direction, valid values are |
* - XAXIDMA_DMA_TO_DEVICE. |
* - XAXIDMA_DEVICE_TO_DMA. |
* |
* @return None |
* |
* @note None. |
* |
*****************************************************************************/ |
#define XAxiDma_IntrAckIrq(InstancePtr, Mask, Direction) \ |
XAxiDma_WriteReg((InstancePtr)->RegBase + \ |
(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_SR_OFFSET, \ |
(Mask) & XAXIDMA_IRQ_ALL_MASK) |
|
|
|
/************************** Function Prototypes ******************************/ |
|
/* |
* Initialization and control functions in xaxidma.c |
*/ |
XAxiDma_Config *XAxiDma_LookupConfig(u32 DeviceId); |
int XAxiDma_CfgInitialize(XAxiDma * InstancePtr, XAxiDma_Config *Config); |
void XAxiDma_Reset(XAxiDma * InstancePtr); |
int XAxiDma_ResetIsDone(XAxiDma * InstancePtr); |
int XAxiDma_Pause(XAxiDma * InstancePtr); |
int XAxiDma_Resume(XAxiDma * InstancePtr); |
u32 XAxiDma_Busy(XAxiDma *InstancePtr,int Direction); |
u32 XAxiDma_SimpleTransfer(XAxiDma *InstancePtr, UINTPTR BuffAddr, u32 Length, |
int Direction); |
int XAxiDma_SelectKeyHole(XAxiDma *InstancePtr, int Direction, int Select); |
int XAxiDma_SelectCyclicMode(XAxiDma *InstancePtr, int Direction, int Select); |
int XAxiDma_Selftest(XAxiDma * InstancePtr); |
#ifdef __cplusplus |
} |
#endif |
|
#endif /* end of protection macro */ |
/** @} */ |
/trunk/sw/dev/test_main/src/_hdl/bsp/libsrc/axidma_v9_0/src/xaxidma_bd.c
0,0 → 1,354
/****************************************************************************** |
* |
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. |
* |
* Permission is hereby granted, free of charge, to any person obtaining a copy |
* of this software and associated documentation files (the "Software"), to deal |
* in the Software without restriction, including without limitation the rights |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
* copies of the Software, and to permit persons to whom the Software is |
* furnished to do so, subject to the following conditions: |
* |
* The above copyright notice and this permission notice shall be included in |
* all copies or substantial portions of the Software. |
* |
* Use of the Software is limited solely to applications: |
* (a) running on a Xilinx device, or |
* (b) that interact with a Xilinx device through a bus or interconnect. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF |
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
* SOFTWARE. |
* |
* Except as contained in this notice, the name of the Xilinx shall not be used |
* in advertising or otherwise to promote the sale, use or other dealings in |
* this Software without prior written authorization from Xilinx. |
* |
******************************************************************************/ |
/*****************************************************************************/ |
/** |
* |
* @file xaxidma_bd.c |
* @addtogroup axidma_v9_0 |
* @{ |
* |
* Buffer descriptor (BD) management API implementation. |
* |
* <pre> |
* MODIFICATION HISTORY: |
* |
* Ver Who Date Changes |
* ----- ---- -------- ------------------------------------------------------- |
* 1.00a jz 05/18/10 First release |
* 2.00a jz 08/10/10 Second release, added in xaxidma_g.c, xaxidma_sinit.c, |
* updated tcl file, added xaxidma_porting_guide.h |
* 3.00a jz 11/22/10 Support IP core parameters change |
* 6.00a srt 01/24/12 Added support for Multi-Channel DMA. |
* - Changed APIs |
* * XAxiDma_BdSetLength(XAxiDma_Bd *BdPtr, |
* u32 LenBytes, u32 LengthMask) |
* * XAxiDma_BdGetActualLength(BdPtr, LengthMask) |
* * XAxiDma_BdGetLength(BdPtr, LengthMask) |
* 8.0 srt 01/29/14 Added support for Micro DMA Mode: |
* - New API |
* XAxiDma_BdSetBufAddrMicroMode(XAxiDma_Bd*, u32) |
* |
* </pre> |
* |
*****************************************************************************/ |
|
#include "xaxidma_bd.h" |
|
/************************** Function Prototypes ******************************/ |
|
/*****************************************************************************/ |
/** |
* Set the length field for the given BD. |
* |
* Length has to be non-zero and less than LengthMask. |
* |
* For TX channels, the value passed in should be the number of bytes to |
* transmit from the TX buffer associated with the given BD. |
* |
* For RX channels, the value passed in should be the size of the RX buffer |
* associated with the given BD in bytes. This is to notify the RX channel |
* the capability of the RX buffer to avoid buffer overflow. |
* |
* The actual receive length can be equal or smaller than the specified length. |
* The actual transfer length will be updated by the hardware in the |
* XAXIDMA_BD_STS_OFFSET word in the BD. |
* |
* @param BdPtr is the BD to operate on. |
* @param LenBytes is the requested transfer length |
* @param LengthMask is the maximum transfer length |
* |
* @returns |
* - XST_SUCCESS for success |
* - XST_INVALID_PARAM for invalid BD length |
* |
* @note This function can be used only when DMA is in SG mode |
* |
*****************************************************************************/ |
int XAxiDma_BdSetLength(XAxiDma_Bd *BdPtr, u32 LenBytes, u32 LengthMask) |
{ |
if (LenBytes <= 0 || (LenBytes > LengthMask)) { |
|
xdbg_printf(XDBG_DEBUG_ERROR, "invalid length %d\n", |
(int)LenBytes); |
|
return XST_INVALID_PARAM; |
} |
|
XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_CTRL_LEN_OFFSET, |
((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_CTRL_LEN_OFFSET) & \ |
~LengthMask)) | LenBytes); |
|
return XST_SUCCESS; |
} |
/*****************************************************************************/ |
/** |
* Set the BD's buffer address. |
* |
* @param BdPtr is the BD to operate on |
* @param Addr is the address to set |
* |
* @return |
* - XST_SUCCESS if buffer address set successfully |
* - XST_INVALID_PARAM if hardware has no DRE and address is not |
* aligned |
* |
* @note This function can be used only when DMA is in SG mode |
* |
*****************************************************************************/ |
u32 XAxiDma_BdSetBufAddr(XAxiDma_Bd* BdPtr, UINTPTR Addr) |
{ |
u32 HasDRE; |
u8 WordLen; |
u32 Addrlen; |
|
HasDRE = XAxiDma_BdRead(BdPtr, XAXIDMA_BD_HAS_DRE_OFFSET); |
WordLen = HasDRE & XAXIDMA_BD_WORDLEN_MASK; |
Addrlen = XAxiDma_BdRead(BdPtr, XAXIDMA_BD_ADDRLEN_OFFSET); |
|
|
if (Addr & (WordLen - 1)) { |
if ((HasDRE & XAXIDMA_BD_HAS_DRE_MASK) == 0) { |
xil_printf("Error set buf addr %x with %x and %x," |
" %x\r\n",Addr, HasDRE, (WordLen - 1), |
Addr & (WordLen - 1)); |
|
return XST_INVALID_PARAM; |
} |
} |
|
XAxiDma_BdWrite(BdPtr, XAXIDMA_BD_BUFA_OFFSET, LOWER_32_BITS(Addr)); |
if (Addrlen) |
XAxiDma_BdWrite(BdPtr, XAXIDMA_BD_BUFA_MSB_OFFSET, |
UPPER_32_BITS(Addr)); |
|
return XST_SUCCESS; |
} |
|
/*****************************************************************************/ |
/** |
* Set the BD's buffer address when configured for Micro Mode. The buffer |
* address should be 4K aligned. |
* |
* @param BdPtr is the BD to operate on |
* @param Addr is the address to set |
* |
* @return |
* - XST_SUCCESS if buffer address set successfully |
* - XST_INVALID_PARAM if hardware has no DRE and address is not |
* aligned |
* |
* @note This function can be used only when DMA is in SG mode |
* |
*****************************************************************************/ |
u32 XAxiDma_BdSetBufAddrMicroMode(XAxiDma_Bd* BdPtr, UINTPTR Addr) |
{ |
u32 Addrlen; |
Addrlen = XAxiDma_BdRead(BdPtr, XAXIDMA_BD_ADDRLEN_OFFSET); |
|
if (Addr & XAXIDMA_MICROMODE_MIN_BUF_ALIGN) { |
xil_printf("Error set buf addr %x and %x," |
" %x\r\n", Addr, XAXIDMA_MICROMODE_MIN_BUF_ALIGN, |
Addr & XAXIDMA_MICROMODE_MIN_BUF_ALIGN); |
|
return XST_INVALID_PARAM; |
} |
|
XAxiDma_BdWrite(BdPtr, XAXIDMA_BD_BUFA_OFFSET, |
LOWER_32_BITS(Addr)); |
if (Addrlen) |
XAxiDma_BdWrite(BdPtr, XAXIDMA_BD_BUFA_MSB_OFFSET, |
UPPER_32_BITS(Addr)); |
|
return XST_SUCCESS; |
} |
|
/*****************************************************************************/ |
/** |
* Set the APP word at the specified APP word offset for a BD. |
* |
* @param BdPtr is the BD to operate on. |
* @param Offset is the offset inside the APP word, it is valid from |
* 0 to 4 |
* @param Word is the value to set |
* |
* @returns |
* - XST_SUCCESS for success |
* - XST_INVALID_PARAM under following error conditions: |
* 1) StsCntrlStrm is not built in hardware |
* 2) Offset is not in valid range |
* |
* @note |
* If the hardware build has C_SG_USE_STSAPP_LENGTH set to 1, |
* then the last APP word, XAXIDMA_LAST_APPWORD, must have |
* non-zero value when AND with 0x7FFFFF. Not doing so will cause |
* the hardware to stall. |
* This function can be used only when DMA is in SG mode |
* |
*****************************************************************************/ |
int XAxiDma_BdSetAppWord(XAxiDma_Bd* BdPtr, int Offset, u32 Word) |
{ |
if (XAxiDma_BdRead(BdPtr, XAXIDMA_BD_HAS_STSCNTRL_OFFSET) == 0) { |
|
xdbg_printf(XDBG_DEBUG_ERROR, "BdRingSetAppWord: no sts cntrl" |
"stream in hardware build, cannot set app word\r\n"); |
|
return XST_INVALID_PARAM; |
} |
|
if ((Offset < 0) || (Offset > XAXIDMA_LAST_APPWORD)) { |
|
xdbg_printf(XDBG_DEBUG_ERROR, "BdRingSetAppWord: invalid" |
"offset %d",Offset); |
|
return XST_INVALID_PARAM; |
} |
|
XAxiDma_BdWrite(BdPtr, XAXIDMA_BD_USR0_OFFSET + Offset * 4, Word); |
|
return XST_SUCCESS; |
} |
/*****************************************************************************/ |
/** |
* Get the APP word at the specified APP word offset for a BD. |
* |
* @param BdPtr is the BD to operate on. |
* @param Offset is the offset inside the APP word, it is valid from |
* 0 to 4 |
* @param Valid is to tell the caller whether parameters are valid |
* |
* @returns |
* The APP word. Passed in parameter Valid holds 0 for failure, |
* and 1 for success. |
* |
* @note This function can be used only when DMA is in SG mode |
* |
*****************************************************************************/ |
u32 XAxiDma_BdGetAppWord(XAxiDma_Bd* BdPtr, int Offset, int *Valid) |
{ |
*Valid = 0; |
|
if (XAxiDma_BdRead(BdPtr, XAXIDMA_BD_HAS_STSCNTRL_OFFSET) == 0) { |
|
xdbg_printf(XDBG_DEBUG_ERROR, "BdRingGetAppWord: no sts cntrl " |
"stream in hardware build, no app word available\r\n"); |
|
return (u32)0; |
} |
|
if((Offset < 0) || (Offset > XAXIDMA_LAST_APPWORD)) { |
|
xdbg_printf(XDBG_DEBUG_ERROR, "BdRingGetAppWord: invalid" |
" offset %d", Offset); |
|
return (u32)0; |
} |
|
*Valid = 1; |
|
return XAxiDma_BdRead(BdPtr, XAXIDMA_BD_USR0_OFFSET + Offset * 4); |
} |
|
/*****************************************************************************/ |
/** |
* Set the control bits for a BD. |
* |
* @param BdPtr is the BD to operate on. |
* @param Data is the bit value to set |
* |
* @return None |
* |
* @note This function can be used only when DMA is in SG mode |
* |
*****************************************************************************/ |
void XAxiDma_BdSetCtrl(XAxiDma_Bd* BdPtr, u32 Data) |
{ |
u32 RegValue = XAxiDma_BdRead(BdPtr, XAXIDMA_BD_CTRL_LEN_OFFSET); |
|
RegValue &= ~XAXIDMA_BD_CTRL_ALL_MASK; |
|
RegValue |= (Data & XAXIDMA_BD_CTRL_ALL_MASK); |
|
XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_CTRL_LEN_OFFSET, RegValue); |
|
return; |
} |
/*****************************************************************************/ |
/** |
* Dump the fields of a BD. |
* |
* @param BdPtr is the BD to operate on. |
* |
* @return None |
* |
* @note This function can be used only when DMA is in SG mode |
* |
*****************************************************************************/ |
void XAxiDma_DumpBd(XAxiDma_Bd* BdPtr) |
{ |
|
xil_printf("Dump BD %x:\r\n", (UINTPTR)BdPtr); |
xil_printf("\tNext Bd Ptr: %x\r\n", |
(unsigned int)XAxiDma_BdRead(BdPtr, XAXIDMA_BD_NDESC_OFFSET)); |
xil_printf("\tBuff addr: %x\r\n", |
(unsigned int)XAxiDma_BdRead(BdPtr, XAXIDMA_BD_BUFA_OFFSET)); |
xil_printf("\tMCDMA Fields: %x\r\n", |
(unsigned int)XAxiDma_BdRead(BdPtr, XAXIDMA_BD_MCCTL_OFFSET)); |
xil_printf("\tVSIZE_STRIDE: %x\r\n", |
(unsigned int)XAxiDma_BdRead(BdPtr, |
XAXIDMA_BD_STRIDE_VSIZE_OFFSET)); |
xil_printf("\tContrl len: %x\r\n", |
(unsigned int)XAxiDma_BdRead(BdPtr, XAXIDMA_BD_CTRL_LEN_OFFSET)); |
xil_printf("\tStatus: %x\r\n", |
(unsigned int)XAxiDma_BdRead(BdPtr, XAXIDMA_BD_STS_OFFSET)); |
|
xil_printf("\tAPP 0: %x\r\n", |
(unsigned int)XAxiDma_BdRead(BdPtr, XAXIDMA_BD_USR0_OFFSET)); |
xil_printf("\tAPP 1: %x\r\n", |
(unsigned int)XAxiDma_BdRead(BdPtr, XAXIDMA_BD_USR1_OFFSET)); |
xil_printf("\tAPP 2: %x\r\n", |
(unsigned int)XAxiDma_BdRead(BdPtr, XAXIDMA_BD_USR2_OFFSET)); |
xil_printf("\tAPP 3: %x\r\n", |
(unsigned int)XAxiDma_BdRead(BdPtr, XAXIDMA_BD_USR3_OFFSET)); |
xil_printf("\tAPP 4: %x\r\n", |
(unsigned int)XAxiDma_BdRead(BdPtr, XAXIDMA_BD_USR4_OFFSET)); |
|
xil_printf("\tSW ID: %x\r\n", |
(unsigned int)XAxiDma_BdRead(BdPtr, XAXIDMA_BD_ID_OFFSET)); |
xil_printf("\tStsCtrl: %x\r\n", |
(unsigned int)XAxiDma_BdRead(BdPtr, |
XAXIDMA_BD_HAS_STSCNTRL_OFFSET)); |
xil_printf("\tDRE: %x\r\n", |
(unsigned int)XAxiDma_BdRead(BdPtr, XAXIDMA_BD_HAS_DRE_OFFSET)); |
|
xil_printf("\r\n"); |
} |
/** @} */ |
/trunk/sw/dev/test_main/src/_hdl/bsp/libsrc/axidma_v9_0/src/xaxidma_bd.h
0,0 → 1,681
/****************************************************************************** |
* |
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. |
* |
* Permission is hereby granted, free of charge, to any person obtaining a copy |
* of this software and associated documentation files (the "Software"), to deal |
* in the Software without restriction, including without limitation the rights |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
* copies of the Software, and to permit persons to whom the Software is |
* furnished to do so, subject to the following conditions: |
* |
* The above copyright notice and this permission notice shall be included in |
* all copies or substantial portions of the Software. |
* |
* Use of the Software is limited solely to applications: |
* (a) running on a Xilinx device, or |
* (b) that interact with a Xilinx device through a bus or interconnect. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF |
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
* SOFTWARE. |
* |
* Except as contained in this notice, the name of the Xilinx shall not be used |
* in advertising or otherwise to promote the sale, use or other dealings in |
* this Software without prior written authorization from Xilinx. |
* |
******************************************************************************/ |
/*****************************************************************************/ |
/** |
* |
* @file xaxidma_bd.h |
* @addtogroup axidma_v9_0 |
* @{ |
* |
* Buffer descriptor (BD) management API. |
* |
* <b> Buffer Descriptors </b> |
* |
* A BD defines a DMA transaction (see "Transaction" section in xaxidma.h). |
* All accesses to a BD go through this set of API. |
* |
* The XAxiDma_Bd structure defines a BD. The first XAXIDMA_BD_HW_NUM_BYTES |
* are shared between hardware and software. |
* |
* <b> Actual Transfer Length </b> |
* |
* The actual transfer length for receive could be smaller than the requested |
* transfer length. The hardware sets the actual transfer length in the |
* completed BD. The API to retrieve the actual transfer length is |
* XAxiDma_GetActualLength(). |
* |
* <b> User IP words </b> |
* |
* There are 5 user IP words in each BD. |
* |
* If hardware does not have the StsCntrl stream built in, then these words |
* are not usable. Retrieving these words get a NULL pointer and setting |
* these words results an error. |
* |
* <b> Performance </b> |
* |
* BDs are typically in a non-cached memory space. Reducing the number of |
* I/O operations to BDs can improve overall performance of the DMA channel. |
* |
* <pre> |
* MODIFICATION HISTORY: |
* |
* Ver Who Date Changes |
* ----- ---- -------- ------------------------------------------------------ |
* 1.00a jz 05/18/10 First release |
* 2.00a jz 08/10/10 Second release, added in xaxidma_g.c, xaxidma_sinit.c, |
* updated tcl file, added xaxidma_porting_guide.h |
* 3.00a jz 11/22/10 Support IP core parameters change |
* 5.00a srt 08/25/11 Changed Cache Macros to have a common API for Zynq |
* and Microblaze. |
* 6.00a srt 01/24/12 Added APIs to support Multi-Channel DMA: |
* XAxiDma_BdSetTId() |
* XAxiDma_BdGetTId() |
* XAxiDma_BdSetTDest() |
* XAxiDma_BdGetTDest() |
* XAxiDma_BdSetTUser() |
* XAxiDma_BdGetTUser() |
* XAxiDma_BdSetARCache() |
* XAxiDma_BdGetARCache() |
* XAxiDma_BdSetARUser() |
* XAxiDma_BdGetARUser() |
* XAxiDma_BdSetStride() |
* XAxiDma_BdGetStride() |
* XAxiDma_BdSetVSize() |
* XAxiDma_BdGetVSize() |
* - Changed APIs |
* XAxiDma_BdGetActualLength(BdPtr, LengthMask) |
* XAxiDma_BdGetLength(BdPtr, LengthMask) |
* XAxiDma_BdSetLength(XAxiDma_Bd* BdPtr, |
* u32 LenBytes, u32 LengthMask) |
* 7.01a srt 10/26/12 Changed the logic of MCDMA BD fields Set APIs, to |
* clear the field first and set it. |
* 8.0 srt 01/29/14 Added support for Micro DMA Mode. |
* |
* </pre> |
*****************************************************************************/ |
|
#ifndef XAXIDMA_BD_H_ /* To prevent circular inclusions */ |
#define XAXIDMA_BD_H_ |
|
#ifdef __cplusplus |
extern "C" { |
#endif |
|
/***************************** Include Files *********************************/ |
|
#include "xaxidma_hw.h" |
#include "xstatus.h" |
#include "xdebug.h" |
#include "xil_cache.h" |
|
#ifdef __MICROBLAZE__ |
#include "xenv.h" |
#else |
#include <string.h> |
#endif |
|
/************************** Constant Definitions *****************************/ |
|
/**************************** Type Definitions *******************************/ |
|
/** |
* The XAxiDma_Bd is the type for a buffer descriptor (BD). |
*/ |
|
typedef UINTPTR XAxiDma_Bd[XAXIDMA_BD_NUM_WORDS]; |
|
|
/***************** Macros (Inline Functions) Definitions *********************/ |
|
/****************************************************************************** |
* Define methods to flush and invalidate cache for BDs should they be |
* located in cached memory. |
*****************************************************************************/ |
#ifdef __aarch64__ |
#define XAXIDMA_CACHE_FLUSH(BdPtr) |
#define XAXIDMA_CACHE_INVALIDATE(BdPtr) |
#else |
#define XAXIDMA_CACHE_FLUSH(BdPtr) \ |
Xil_DCacheFlushRange((UINTPTR)(BdPtr), XAXIDMA_BD_HW_NUM_BYTES) |
|
#define XAXIDMA_CACHE_INVALIDATE(BdPtr) \ |
Xil_DCacheInvalidateRange((UINTPTR)(BdPtr), XAXIDMA_BD_HW_NUM_BYTES) |
#endif |
|
/*****************************************************************************/ |
/** |
* |
* Read the given Buffer Descriptor word. |
* |
* @param BaseAddress is the base address of the BD to read |
* @param Offset is the word offset to be read |
* |
* @return The 32-bit value of the field |
* |
* @note |
* C-style signature: |
* u32 XAxiDma_BdRead(u32 BaseAddress, u32 Offset) |
* |
******************************************************************************/ |
#define XAxiDma_BdRead(BaseAddress, Offset) \ |
(*(u32 *)((UINTPTR)((void *)(BaseAddress)) + (u32)(Offset))) |
|
|
/*****************************************************************************/ |
/** |
* |
* Write the given Buffer Descriptor word. |
* |
* @param BaseAddress is the base address of the BD to write |
* @param Offset is the word offset to be written |
* @param Data is the 32-bit value to write to the field |
* |
* @return None. |
* |
* @note |
* C-style signature: |
* void XAxiDma_BdWrite(u32 BaseAddress, u32 RegOffset, u32 Data) |
* |
******************************************************************************/ |
#define XAxiDma_BdWrite(BaseAddress, Offset, Data) \ |
(*(u32 *)((UINTPTR)(void *)(BaseAddress) + (u32)(Offset))) = (u32)(Data) |
|
|
/*****************************************************************************/ |
/** |
* Zero out BD specific fields. BD fields that are for the BD ring or for the |
* system hardware build information are not touched. |
* |
* @param BdPtr is the BD to operate on |
* |
* @return None |
* |
* @note |
* C-style signature: |
* void XAxiDma_BdClear(XAxiDma_Bd* BdPtr) |
* |
*****************************************************************************/ |
#define XAxiDma_BdClear(BdPtr) \ |
memset((void *)(((UINTPTR)(BdPtr)) + XAXIDMA_BD_START_CLEAR), 0, \ |
XAXIDMA_BD_BYTES_TO_CLEAR) |
|
/*****************************************************************************/ |
/** |
* Get the control bits for the BD |
* |
* @param BdPtr is the BD to operate on |
* |
* @return The bit mask for the control of the BD |
* |
* @note |
* C-style signature: |
* u32 XAxiDma_BdGetCtrl(XAxiDma_Bd* BdPtr) |
* |
*****************************************************************************/ |
#define XAxiDma_BdGetCtrl(BdPtr) \ |
(XAxiDma_BdRead((BdPtr), XAXIDMA_BD_CTRL_LEN_OFFSET) \ |
& XAXIDMA_BD_CTRL_ALL_MASK) |
/*****************************************************************************/ |
/** |
* Retrieve the status of a BD |
* |
* @param BdPtr is the BD to operate on |
* |
* @return Word at offset XAXIDMA_BD_DMASR_OFFSET. Use XAXIDMA_BD_STS_*** |
* values defined in xaxidma_hw.h to interpret the returned value |
* |
* @note |
* C-style signature: |
* u32 XAxiDma_BdGetSts(XAxiDma_Bd* BdPtr) |
* |
*****************************************************************************/ |
#define XAxiDma_BdGetSts(BdPtr) \ |
(XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STS_OFFSET) & \ |
XAXIDMA_BD_STS_ALL_MASK) |
/*****************************************************************************/ |
/** |
* Retrieve the length field value from the given BD. The returned value is |
* the same as what was written with XAxiDma_BdSetLength(). Note that in the |
* this value does not reflect the real length of received data. |
* See the comments of XAxiDma_BdSetLength() for more details. To obtain the |
* actual transfer length, use XAxiDma_BdGetActualLength(). |
* |
* @param BdPtr is the BD to operate on. |
* @param LengthMask is the Maximum Transfer Length. |
* |
* @return The length value set in the BD. |
* |
* @note |
* C-style signature: |
* u32 XAxiDma_BdGetLength(XAxiDma_Bd* BdPtr) |
* |
*****************************************************************************/ |
#define XAxiDma_BdGetLength(BdPtr, LengthMask) \ |
(XAxiDma_BdRead((BdPtr), XAXIDMA_BD_CTRL_LEN_OFFSET) & \ |
LengthMask) |
|
|
/*****************************************************************************/ |
/** |
* Set the ID field of the given BD. The ID is an arbitrary piece of data the |
* application can associate with a specific BD. |
* |
* @param BdPtr is the BD to operate on |
* @param Id is a 32 bit quantity to set in the BD |
* |
* @return None |
* |
* @note |
* C-style signature: |
* void XAxiDma_BdSetId(XAxiDma_Bd* BdPtr, void Id) |
* |
*****************************************************************************/ |
#define XAxiDma_BdSetId(BdPtr, Id) \ |
(XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_ID_OFFSET, (u32)(Id))) |
|
|
/*****************************************************************************/ |
/** |
* Retrieve the ID field of the given BD previously set with XAxiDma_BdSetId. |
* |
* @param BdPtr is the BD to operate on |
* |
* @return None |
* |
* @note |
* C-style signature: |
* u32 XAxiDma_BdGetId(XAxiDma_Bd* BdPtr) |
* |
*****************************************************************************/ |
#define XAxiDma_BdGetId(BdPtr) (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_ID_OFFSET)) |
|
/*****************************************************************************/ |
/** |
* Get the BD's buffer address |
* |
* @param BdPtr is the BD to operate on |
* |
* @return None |
* |
* @note |
* C-style signature: |
* u32 XAxiDma_BdGetBufAddr(XAxiDma_Bd* BdPtr) |
* |
*****************************************************************************/ |
#define XAxiDma_BdGetBufAddr(BdPtr) \ |
(XAxiDma_BdRead((BdPtr), XAXIDMA_BD_BUFA_OFFSET)) |
|
/*****************************************************************************/ |
/** |
* Check whether a BD has completed in hardware. This BD has been submitted |
* to hardware. The application can use this function to poll for the |
* completion of the BD. |
* |
* This function may not work if the BD is in cached memory. |
* |
* @param BdPtr is the BD to check on |
* |
* @return |
* - 0 if not complete |
* - XAXIDMA_BD_STS_COMPLETE_MASK if completed, may contain |
* XAXIDMA_BD_STS_*_ERR_MASK bits. |
* |
* @note |
* C-style signature: |
* int XAxiDma_BdHwCompleted(XAxiDma_Bd* BdPtr) |
* |
*****************************************************************************/ |
#define XAxiDma_BdHwCompleted(BdPtr) \ |
(XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STS_OFFSET) & \ |
XAXIDMA_BD_STS_COMPLETE_MASK) |
|
/*****************************************************************************/ |
/** |
* Get the actual transfer length of a BD. The BD has completed in hw. |
* |
* This function may not work if the BD is in cached memory. |
* |
* @param BdPtr is the BD to check on |
* @param LengthMask is the Maximum Transfer Length. |
* |
* @return None |
* |
* @note |
* C-style signature: |
* int XAxiDma_BdGetActualLength(XAxiDma_Bd* BdPtr) |
* |
*****************************************************************************/ |
#define XAxiDma_BdGetActualLength(BdPtr, LengthMask) \ |
(XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STS_OFFSET) & \ |
LengthMask) |
|
/*****************************************************************************/ |
/** |
* Set the TID field of the TX BD. |
* Provides a stream identifier and can be used to differentiate between |
* multiple streams of data that are being transferred across the same |
* interface. |
* |
* @param BdPtr is the BD to operate on |
* @param TId is a 8 bit quantity to set in the BD |
* |
* @return None |
* |
* @note |
* C-style signature: |
* void XAxiDma_BdSetTId(XAxiDma_Bd* BdPtr, void TId) |
* |
*****************************************************************************/ |
#define XAxiDma_BdSetTId(BdPtr, TId) \ |
{ \ |
u32 val; \ |
val = (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_MCCTL_OFFSET) & \ |
~XAXIDMA_BD_TID_FIELD_MASK); \ |
val |= ((u32)(TId) << XAXIDMA_BD_TID_FIELD_SHIFT); \ |
XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_MCCTL_OFFSET, val); \ |
} |
|
/*****************************************************************************/ |
/** |
* Retrieve the TID field of the RX BD previously set with XAxiDma_BdSetTId. |
* |
* @param BdPtr is the BD to operate on |
* |
* @return None |
* |
* @note |
* C-style signature: |
* u32 XAxiDma_BdGetTId(XAxiDma_Bd* BdPtr) |
* |
*****************************************************************************/ |
#define XAxiDma_BdGetTId(BdPtr) \ |
((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STS_OFFSET)) & \ |
XAXIDMA_BD_TID_FIELD_MASK) |
|
/*****************************************************************************/ |
/** |
* Set the TDEST field of the TX BD. |
* Provides coarse routing information for the data stream. |
* |
* @param BdPtr is the BD to operate on |
* @param TDest is a 8 bit quantity to set in the BD |
* |
* @return None |
* |
* @note |
* C-style signature: |
* void XAxiDma_BdSetTDest(XAxiDma_Bd* BdPtr, void TDest) |
* |
*****************************************************************************/ |
#define XAxiDma_BdSetTDest(BdPtr, TDest) \ |
{ \ |
u32 val; \ |
val = (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_MCCTL_OFFSET) & \ |
~XAXIDMA_BD_TDEST_FIELD_MASK); \ |
val |= ((u32)(TDest) << XAXIDMA_BD_TDEST_FIELD_SHIFT); \ |
XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_MCCTL_OFFSET, val); \ |
} |
|
/*****************************************************************************/ |
/** |
* Retrieve the TDest field of the RX BD previously set with i |
* XAxiDma_BdSetTDest. |
* |
* @param BdPtr is the BD to operate on |
* |
* @return None |
* |
* @note |
* C-style signature: |
* u32 XAxiDma_BdGetTDest(XAxiDma_Bd* BdPtr) |
* |
*****************************************************************************/ |
#define XAxiDma_BdGetTDest(BdPtr) \ |
((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STS_OFFSET)) & \ |
XAXIDMA_BD_TDEST_FIELD_MASK) |
|
/*****************************************************************************/ |
/** |
* Set the TUSER field of the TX BD. |
* User defined sideband signaling. |
* |
* @param BdPtr is the BD to operate on |
* @param TUser is a 8 bit quantity to set in the BD |
* |
* @return None |
* |
* @note |
* C-style signature: |
* void XAxiDma_BdSetTUser(XAxiDma_Bd* BdPtr, void TUser) |
* |
*****************************************************************************/ |
#define XAxiDma_BdSetTUser(BdPtr, TUser) \ |
{ \ |
u32 val; \ |
val = (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_MCCTL_OFFSET) & \ |
~XAXIDMA_BD_TUSER_FIELD_MASK); \ |
val |= ((u32)(TUser) << XAXIDMA_BD_TUSER_FIELD_SHIFT); \ |
XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_MCCTL_OFFSET, val); \ |
} |
|
/*****************************************************************************/ |
/** |
* Retrieve the TUSER field of the RX BD previously set with |
* XAxiDma_BdSetTUser. |
* |
* @param BdPtr is the BD to operate on |
* |
* @return None |
* |
* @note |
* C-style signature: |
* u32 XAxiDma_BdGetTUser(XAxiDma_Bd* BdPtr) |
* |
*****************************************************************************/ |
#define XAxiDma_BdGetTUser(BdPtr) \ |
((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STS_OFFSET)) & \ |
XAXIDMA_BD_TUSER_FIELD_MASK) |
|
/*****************************************************************************/ |
/** |
* Set the ARCACHE field of the given BD. |
* This signal provides additional information about the cacheable |
* characteristics of the transfer. |
* |
* @param BdPtr is the BD to operate on |
* @param ARCache is a 8 bit quantity to set in the BD |
* |
* @return None |
* |
* @note |
* C-style signature: |
* void XAxiDma_BdSetARCache(XAxiDma_Bd* BdPtr, void ARCache) |
* |
*****************************************************************************/ |
#define XAxiDma_BdSetARCache(BdPtr, ARCache) \ |
{ \ |
u32 val; \ |
val = (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_MCCTL_OFFSET) & \ |
~XAXIDMA_BD_ARCACHE_FIELD_MASK); \ |
val |= ((u32)(ARCache) << XAXIDMA_BD_ARCACHE_FIELD_SHIFT); \ |
XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_MCCTL_OFFSET, val); \ |
} |
|
/*****************************************************************************/ |
/** |
* Retrieve the ARCACHE field of the given BD previously set with |
* XAxiDma_BdSetARCache. |
* |
* @param BdPtr is the BD to operate on |
* |
* @return None |
* |
* @note |
* C-style signature: |
* u32 XAxiDma_BdGetARCache(XAxiDma_Bd* BdPtr) |
* |
*****************************************************************************/ |
#define XAxiDma_BdGetARCache(BdPtr) \ |
((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_MCCTL_OFFSET)) & \ |
XAXIDMA_BD_ARCACHE_FIELD_MASK) |
|
|
/*****************************************************************************/ |
/** |
* Set the ARUSER field of the given BD. |
* Sideband signals used for user defined information. |
* |
* @param BdPtr is the BD to operate on |
* @param ARUser is a 8 bit quantity to set in the BD |
* |
* @return None |
* |
* @note |
* C-style signature: |
* void XAxiDma_BdSetARUser(XAxiDma_Bd* BdPtr, void ARUser) |
* |
*****************************************************************************/ |
#define XAxiDma_BdSetARUser(BdPtr, ARUser) \ |
{ \ |
u32 val; \ |
val = (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_MCCTL_OFFSET) & \ |
~XAXIDMA_BD_ARUSER_FIELD_MASK); \ |
val |= ((u32)(ARUser) << XAXIDMA_BD_ARUSER_FIELD_SHIFT); \ |
XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_MCCTL_OFFSET, val); \ |
} |
|
|
/*****************************************************************************/ |
/** |
* Retrieve the ARUSER field of the given BD previously set with |
* XAxiDma_BdSetARUser. |
* |
* @param BdPtr is the BD to operate on |
* |
* @return None |
* |
* @note |
* C-style signature: |
* u32 XAxiDma_BdGetARUser(XAxiDma_Bd* BdPtr) |
* |
*****************************************************************************/ |
#define XAxiDma_BdGetARUser(BdPtr) \ |
((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_MCCTL_OFFSET)) & \ |
XAXIDMA_BD_ARUSER_FIELD_MASK) |
|
/*****************************************************************************/ |
/** |
* Set the STRIDE field of the given BD. |
* It is the address distance between the first address of successive |
* horizontal reads. |
* |
* @param BdPtr is the BD to operate on |
* @param Stride is a 32 bit quantity to set in the BD |
* |
* @return None |
* |
* @note |
* C-style signature: |
* void XAxiDma_BdSetStride(XAxiDma_Bd* BdPtr, void Stride) |
* |
*****************************************************************************/ |
#define XAxiDma_BdSetStride(BdPtr, Stride) \ |
{ \ |
u32 val; \ |
val = (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STRIDE_VSIZE_OFFSET) & \ |
~XAXIDMA_BD_STRIDE_FIELD_MASK); \ |
val |= ((u32)(Stride) << XAXIDMA_BD_STRIDE_FIELD_SHIFT); \ |
XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_STRIDE_VSIZE_OFFSET, val); \ |
} |
|
/*****************************************************************************/ |
/** |
* Retrieve the STRIDE field of the given BD previously set with |
* XAxiDma_BdSetStride. |
* |
* @param BdPtr is the BD to operate on |
* |
* @return None |
* |
* @note |
* C-style signature: |
* u32 XAxiDma_BdGetStride(XAxiDma_Bd* BdPtr) |
* |
*****************************************************************************/ |
#define XAxiDma_BdGetStride(BdPtr) \ |
((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STRIDE_VSIZE_OFFSET)) & \ |
XAXIDMA_BD_STRIDE_FIELD_MASK) |
|
/*****************************************************************************/ |
/** |
* Set the VSIZE field of the given BD. |
* Number of horizontal lines for strided access. |
* |
* @param BdPtr is the BD to operate on |
* @param VSize is a 32 bit quantity to set in the BD |
* |
* @return None |
* |
* @note |
* C-style signature: |
* void XAxiDma_BdSetVSize(XAxiDma_Bd* BdPtr, void VSize) |
* |
*****************************************************************************/ |
#define XAxiDma_BdSetVSize(BdPtr, VSize) \ |
{ \ |
u32 val; \ |
val = (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STRIDE_VSIZE_OFFSET) & \ |
~XAXIDMA_BD_VSIZE_FIELD_MASK); \ |
val |= ((u32)(VSize) << XAXIDMA_BD_VSIZE_FIELD_SHIFT); \ |
XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_STRIDE_VSIZE_OFFSET, val); \ |
} |
|
/*****************************************************************************/ |
/** |
* Retrieve the STRIDE field of the given BD previously set with |
* XAxiDma_BdSetVSize. |
* |
* @param BdPtr is the BD to operate on |
* |
* @return None |
* |
* @note |
* C-style signature: |
* u32 XAxiDma_BdGetVSize(XAxiDma_Bd* BdPtr) |
* |
*****************************************************************************/ |
#define XAxiDma_BdGetVSize(BdPtr) \ |
((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STRIDE_VSIZE_OFFSET)) & \ |
XAXIDMA_BD_VSIZE_FIELD_MASK) |
|
/*****************************************************************************/ |
|
/************************** Function Prototypes ******************************/ |
|
int XAxiDma_BdSetLength(XAxiDma_Bd* BdPtr, u32 LenBytes, u32 LengthMask); |
u32 XAxiDma_BdSetBufAddr(XAxiDma_Bd* BdPtr, UINTPTR Addr); |
u32 XAxiDma_BdSetBufAddrMicroMode(XAxiDma_Bd* BdPtr, UINTPTR Addr); |
int XAxiDma_BdSetAppWord(XAxiDma_Bd * BdPtr, int Offset, u32 Word); |
u32 XAxiDma_BdGetAppWord(XAxiDma_Bd * BdPtr, int Offset, int *Valid); |
void XAxiDma_BdSetCtrl(XAxiDma_Bd *BdPtr, u32 Data); |
|
/* Debug utility |
*/ |
void XAxiDma_DumpBd(XAxiDma_Bd* BdPtr); |
|
#ifdef __cplusplus |
} |
#endif |
|
#endif /* end of protection macro */ |
/** @} */ |
/trunk/sw/dev/test_main/src/_hdl/bsp/libsrc/axidma_v9_0/src/xaxidma_bdring.c
0,0 → 1,1587
/****************************************************************************** |
* |
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. |
* |
* Permission is hereby granted, free of charge, to any person obtaining a copy |
* of this software and associated documentation files (the "Software"), to deal |
* in the Software without restriction, including without limitation the rights |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
* copies of the Software, and to permit persons to whom the Software is |
* furnished to do so, subject to the following conditions: |
* |
* The above copyright notice and this permission notice shall be included in |
* all copies or substantial portions of the Software. |
* |
* Use of the Software is limited solely to applications: |
* (a) running on a Xilinx device, or |
* (b) that interact with a Xilinx device through a bus or interconnect. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF |
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
* SOFTWARE. |
* |
* Except as contained in this notice, the name of the Xilinx shall not be used |
* in advertising or otherwise to promote the sale, use or other dealings in |
* this Software without prior written authorization from Xilinx. |
* |
******************************************************************************/ |
/*****************************************************************************/ |
/** |
* |
* @file xaxidma_bdring.c |
* @addtogroup axidma_v9_0 |
* @{ |
* |
* This file implements buffer descriptor ring related functions. For more |
* information on how to manage the BD ring, please see xaxidma.h. |
* |
* <pre> |
* MODIFICATION HISTORY: |
* |
* Ver Who Date Changes |
* ----- ---- -------- ------------------------------------------------------- |
* 1.00a jz 05/18/10 First release |
* 2.00a jz 08/10/10 Second release, added in xaxidma_g.c, xaxidma_sinit.c, |
* updated tcl file, added xaxidma_porting_guide.h |
* 3.00a jz 11/22/10 Support IP core parameters change |
* 5.00a srt 08/25/11 Added support for memory barrier. |
* 6.00a srt 01/24/12 Added support for Multi-Channel DMA. |
* - New API |
* * XAxiDma_UpdateBdRingCDesc(XAxiDma_BdRing * RingPtr, |
* int RingIndex) |
* - Changed APIs |
* * XAxiDma_StartBdRingHw(XAxiDma_BdRing * RingPtr, |
* int RingIndex) |
* * XAxiDma_BdRingStart(XAxiDma_BdRing * RingPtr, |
* int RingIndex) |
* * XAxiDma_BdRingToHw(XAxiDma_BdRing * RingPtr, |
* int NumBd, XAxiDma_Bd * BdSetPtr, int RingIndex) |
* * XAxiDma_BdRingDumpRegs(XAxiDma_BdRing * RingPtr, |
* int RingIndex) |
* * XAxiDma_BdRingSnapShotCurrBd(XAxiDma_BdRing * RingPtr, |
* int RingIndex) |
* 7.00a srt 06/18/12 All the APIs changed in v6_00_a are reverted back for |
* backward compatibility. |
* |
* |
* </pre> |
******************************************************************************/ |
|
/***************************** Include Files *********************************/ |
|
#include "xaxidma_bdring.h" |
|
/************************** Constant Definitions *****************************/ |
/* Use 100 milliseconds for 100 MHz |
* This interval is sufficient for hardware to finish 40MB transfer with |
* 32-bit bus. |
*/ |
#define XAXIDMA_STOP_TIMEOUT 500000 /* about 100 milliseconds on 100MHz */ |
|
/**************************** Type Definitions *******************************/ |
|
|
/***************** Macros (Inline Functions) Definitions *********************/ |
/* The following macros are helper functions inside this file. |
*/ |
|
/****************************************************************************** |
* Compute the physical address of a descriptor from its virtual address |
* |
* @param BdPtr is the virtual address of the BD |
* |
* @returns Physical address of BdPtr |
* |
* @note Assume virtual and physical mapping is flat. |
* RingPtr is an implicit parameter |
* |
*****************************************************************************/ |
#define XAXIDMA_VIRT_TO_PHYS(BdPtr) \ |
((UINTPTR)(BdPtr) + (RingPtr->FirstBdPhysAddr - RingPtr->FirstBdAddr)) |
|
/****************************************************************************** |
* Move the BdPtr argument ahead an arbitrary number of BDs wrapping around |
* to the beginning of the ring if needed. |
* |
* We know if a wraparound should occur if the new BdPtr is greater than |
* the high address in the ring OR if the new BdPtr crosses the 0xFFFFFFFF |
* to 0 boundary. |
* |
* @param RingPtr is the ring BdPtr appears in |
* @param BdPtr on input is the starting BD position and on output is the |
* final BD position |
* @param NumBd is the number of BD spaces to increment |
* |
* @returns None |
* |
* @note This function can be used only when DMA is in SG mode |
* |
*****************************************************************************/ |
#define XAXIDMA_RING_SEEKAHEAD(RingPtr, BdPtr, NumBd) \ |
{ \ |
UINTPTR Addr = (UINTPTR)(void *)(BdPtr); \ |
\ |
Addr += ((RingPtr)->Separation * (NumBd)); \ |
if ((Addr > (RingPtr)->LastBdAddr) || ((UINTPTR)(BdPtr) > Addr)) \ |
{ \ |
Addr -= (RingPtr)->Length; \ |
} \ |
\ |
(BdPtr) = (XAxiDma_Bd*)(void *)Addr; \ |
} |
/****************************************************************************** |
* Move the BdPtr argument backwards an arbitrary number of BDs wrapping |
* around to the end of the ring if needed. |
* |
* We know if a wraparound should occur if the new BdPtr is less than |
* the base address in the ring OR if the new BdPtr crosses the 0xFFFFFFFF |
* to 0 boundary. |
* |
* @param RingPtr is the ring BdPtr appears in |
* @param BdPtr on input is the starting BD position and on output is the |
* final BD position |
* @param NumBd is the number of BD spaces to increment |
* |
* @returns None |
* |
* @note This function can be used only when DMA is in SG mode |
* |
*****************************************************************************/ |
#define XAXIDMA_RING_SEEKBACK(RingPtr, BdPtr, NumBd) \ |
{ \ |
UINTPTR Addr = (UINTPTR)(BdPtr); \ |
\ |
Addr -= ((RingPtr)->Separation * (NumBd)); \ |
if ((Addr < (RingPtr)->FirstBdAddr) || ((UINTPTR)(BdPtr) < Addr)) \ |
{ \ |
Addr += (RingPtr)->Length; \ |
} \ |
\ |
(BdPtr) = (XAxiDma_Bd*)Addr; \ |
} |
|
/************************** Function Prototypes ******************************/ |
|
/************************** Variable Definitions *****************************/ |
|
|
/*****************************************************************************/ |
/** |
* Update Current Descriptor |
* |
* @param RingPtr is the Channel instance to be worked on |
* |
* @return |
* - XST_SUCCESS upon success |
* - XST_DMA_ERROR if no valid BD available to put into current |
* BD register |
* |
* @note This function can be used only when DMA is in SG mode |
* |
*****************************************************************************/ |
int XAxiDma_UpdateBdRingCDesc(XAxiDma_BdRing* RingPtr) |
{ |
u32 RegBase; |
UINTPTR BdPtr; |
int RingIndex = RingPtr->RingIndex; |
|
/* BD list has yet to be created for this channel */ |
if (RingPtr->AllCnt == 0) { |
|
xdbg_printf(XDBG_DEBUG_ERROR, "BdRingStart: no bds\r\n"); |
|
return XST_DMA_SG_NO_LIST; |
} |
|
/* Do nothing if already started */ |
if (RingPtr->RunState == AXIDMA_CHANNEL_NOT_HALTED) { |
/* Need to update tail pointer if needed (Engine is not |
* transferring) |
*/ |
return XST_SUCCESS; |
} |
|
if (!XAxiDma_BdRingHwIsStarted(RingPtr)) { |
/* If hardware is not running, then we need to put a valid current |
* BD pointer to the current BD register before start the hardware |
*/ |
RegBase = RingPtr->ChanBase; |
|
/* Put a valid BD pointer in the current BD pointer register |
* So, the hardware is ready to go when tail BD pointer is updated |
*/ |
BdPtr = (UINTPTR)(void *)(RingPtr->BdaRestart); |
|
if (!XAxiDma_BdHwCompleted(BdPtr)) { |
if (RingPtr->IsRxChannel) { |
if (!RingIndex) { |
XAxiDma_WriteReg(RegBase, |
XAXIDMA_CDESC_OFFSET, |
(u32)(BdPtr & XAXIDMA_DESC_LSB_MASK)); |
if (RingPtr->Addr_ext) |
XAxiDma_WriteReg(RegBase, |
XAXIDMA_CDESC_MSB_OFFSET, |
UPPER_32_BITS(BdPtr)); |
} |
else { |
XAxiDma_WriteReg(RegBase, |
(XAXIDMA_RX_CDESC0_OFFSET + |
(RingIndex - 1) * XAXIDMA_RX_NDESC_OFFSET), |
(u32)(BdPtr & XAXIDMA_DESC_LSB_MASK)); |
if (RingPtr->Addr_ext) |
XAxiDma_WriteReg(RegBase, |
(XAXIDMA_RX_CDESC0_MSB_OFFSET + |
(RingIndex - 1) * XAXIDMA_RX_NDESC_OFFSET), |
UPPER_32_BITS(BdPtr)); |
} |
} |
else { |
XAxiDma_WriteReg(RegBase, |
XAXIDMA_CDESC_OFFSET, |
(u32)(BdPtr & XAXIDMA_DESC_LSB_MASK)); |
if (RingPtr->Addr_ext) |
XAxiDma_WriteReg(RegBase, XAXIDMA_CDESC_MSB_OFFSET, |
UPPER_32_BITS(BdPtr)); |
} |
} |
else { |
/* Look for an uncompleted BD |
*/ |
while (XAxiDma_BdHwCompleted(BdPtr)) { |
BdPtr = XAxiDma_BdRingNext(RingPtr, BdPtr); |
|
if ((UINTPTR)BdPtr == (UINTPTR) RingPtr->BdaRestart) { |
xdbg_printf(XDBG_DEBUG_ERROR, |
"StartBdRingHw: Cannot find valid cdesc\r\n"); |
|
return XST_DMA_ERROR; |
} |
|
if (!XAxiDma_BdHwCompleted(BdPtr)) { |
if (RingPtr->IsRxChannel) { |
if (!RingIndex) { |
XAxiDma_WriteReg(RegBase, |
XAXIDMA_CDESC_OFFSET,(u32) (BdPtr & XAXIDMA_DESC_LSB_MASK)); |
if (RingPtr->Addr_ext) |
XAxiDma_WriteReg(RegBase, XAXIDMA_CDESC_MSB_OFFSET, |
UPPER_32_BITS(BdPtr)); |
} |
else { |
XAxiDma_WriteReg(RegBase, |
(XAXIDMA_RX_CDESC0_OFFSET + |
(RingIndex - 1) * XAXIDMA_RX_NDESC_OFFSET), |
(u32)(BdPtr & XAXIDMA_DESC_LSB_MASK)); |
if (RingPtr->Addr_ext) |
XAxiDma_WriteReg(RegBase, |
(XAXIDMA_RX_CDESC0_MSB_OFFSET + |
(RingIndex - 1) * XAXIDMA_RX_NDESC_OFFSET), |
UPPER_32_BITS(BdPtr)); |
} |
} |
else { |
XAxiDma_WriteReg(RegBase, |
XAXIDMA_CDESC_OFFSET, (u32)(BdPtr & XAXIDMA_DESC_LSB_MASK)); |
if (RingPtr->Addr_ext) |
XAxiDma_WriteReg(RegBase, XAXIDMA_CDESC_MSB_OFFSET, |
UPPER_32_BITS(BdPtr)); |
} |
break; |
} |
} |
} |
|
} |
|
return XST_SUCCESS; |
} |
|
/*****************************************************************************/ |
/** |
* Using a memory segment allocated by the caller, This fundtion creates and |
* setup the BD ring. |
* |
* @param RingPtr is the BD ring instance to be worked on. |
* @param PhysAddr is the physical base address of application memory |
* region. |
* @param VirtAddr is the virtual base address of the application memory |
* region.If address translation is not being utilized, then |
* VirtAddr should be equivalent to PhysAddr. |
* @param Alignment governs the byte alignment of individual BDs. This |
* function will enforce a minimum alignment of |
* XAXIDMA_BD_MINIMUM_ALIGNMENT bytes with no maximum as long as |
* it is specified as a power of 2. |
* @param BdCount is the number of BDs to setup in the application memory |
* region. It is assumed the region is large enough to contain the |
* BDs.Refer to the "SGDMA Ring Creation" section in xaxidma.h |
* for more information. The minimum valid value for this |
* parameter is 1. |
* |
* @return |
* - XST_SUCCESS if initialization was successful |
* - XST_NO_FEATURE if the provided instance is a non SGDMA type |
* of DMA channel. |
* - XST_INVALID_PARAM under any of the following conditions: |
* 1) BdCount is not positive |
* |
* 2) PhysAddr and/or VirtAddr are not aligned to the given |
* Alignment parameter; |
* |
* 3) Alignment parameter does not meet minimum requirements or |
* is not a power of 2 value. |
* |
* - XST_DMA_SG_LIST_ERROR if the memory segment containing the |
* list spans over address 0x00000000 in virtual address space. |
* |
* @note This function can be used only when DMA is in SG mode |
* |
*****************************************************************************/ |
u32 XAxiDma_BdRingCreate(XAxiDma_BdRing *RingPtr, UINTPTR PhysAddr, |
UINTPTR VirtAddr, u32 Alignment, int BdCount) |
{ |
int i; |
UINTPTR BdVirtAddr; |
UINTPTR BdPhysAddr; |
|
if (BdCount <= 0) { |
|
xdbg_printf(XDBG_DEBUG_ERROR, "BdRingCreate: non-positive BD" |
" number %d\r\n", BdCount); |
|
return XST_INVALID_PARAM; |
} |
|
/* In case there is a failure prior to creating list, make sure the |
* following attributes are 0 to prevent calls to other SG functions |
* from doing anything |
*/ |
RingPtr->AllCnt = 0; |
RingPtr->FreeCnt = 0; |
RingPtr->HwCnt = 0; |
RingPtr->PreCnt = 0; |
RingPtr->PostCnt = 0; |
|
/* Make sure Alignment parameter meets minimum requirements */ |
if (Alignment < XAXIDMA_BD_MINIMUM_ALIGNMENT) { |
|
xdbg_printf(XDBG_DEBUG_ERROR, "BdRingCreate: alignment too " |
"small %d, need to be at least %d\r\n", (int)Alignment, |
XAXIDMA_BD_MINIMUM_ALIGNMENT); |
|
return XST_INVALID_PARAM; |
} |
|
/* Make sure Alignment is a power of 2 */ |
if ((Alignment - 1) & Alignment) { |
|
xdbg_printf(XDBG_DEBUG_ERROR, "BdRingCreate: alignment not" |
" valid %d\r\n", (int)Alignment); |
|
return XST_INVALID_PARAM; |
} |
|
/* Make sure PhysAddr and VirtAddr are on same Alignment */ |
if ((PhysAddr % Alignment) || (VirtAddr % Alignment)) { |
|
xdbg_printf(XDBG_DEBUG_ERROR, "BdRingCreate: Physical address" |
" %x and virtual address %x have different alignment\r\n", |
(unsigned int)PhysAddr, (unsigned int)VirtAddr); |
|
return XST_INVALID_PARAM; |
} |
|
/* Compute how many bytes will be between the start of adjacent BDs */ |
RingPtr->Separation = |
(sizeof(XAxiDma_Bd) + (Alignment - 1)) & ~(Alignment - 1); |
|
/* Must make sure the ring doesn't span address 0x00000000. If it does, |
* then the next/prev BD traversal macros will fail. |
*/ |
if (VirtAddr > (VirtAddr + (RingPtr->Separation * BdCount) - 1)) { |
|
xdbg_printf(XDBG_DEBUG_ERROR, "BdRingCreate: BD space cross " |
"0x0\r\n"); |
|
return XST_DMA_SG_LIST_ERROR; |
} |
|
/* Initial ring setup: |
* - Clear the entire space |
* - Setup each BD's next pointer with the physical address of the |
* next BD |
* - Put hardware information in each BD |
*/ |
memset((void *) VirtAddr, 0, (RingPtr->Separation * BdCount)); |
|
BdVirtAddr = VirtAddr; |
BdPhysAddr = PhysAddr + RingPtr->Separation; |
for (i = 1; i < BdCount; i++) { |
XAxiDma_BdWrite(BdVirtAddr, XAXIDMA_BD_ADDRLEN_OFFSET, |
RingPtr->Addr_ext); |
XAxiDma_BdWrite(BdVirtAddr, XAXIDMA_BD_NDESC_OFFSET, |
(BdPhysAddr & XAXIDMA_DESC_LSB_MASK)); |
XAxiDma_BdWrite(BdVirtAddr, XAXIDMA_BD_NDESC_MSB_OFFSET, |
UPPER_32_BITS(BdPhysAddr)); |
|
/* Put hardware information in the BDs |
*/ |
XAxiDma_BdWrite(BdVirtAddr, XAXIDMA_BD_HAS_STSCNTRL_OFFSET, |
(u32)RingPtr->HasStsCntrlStrm); |
|
XAxiDma_BdWrite(BdVirtAddr, XAXIDMA_BD_HAS_DRE_OFFSET, |
(((u32)(RingPtr->HasDRE)) << XAXIDMA_BD_HAS_DRE_SHIFT) | |
RingPtr->DataWidth); |
|
XAXIDMA_CACHE_FLUSH(BdVirtAddr); |
BdVirtAddr += RingPtr->Separation; |
BdPhysAddr += RingPtr->Separation; |
} |
|
/* At the end of the ring, link the last BD back to the top */ |
XAxiDma_BdWrite(BdVirtAddr, XAXIDMA_BD_ADDRLEN_OFFSET, |
RingPtr->Addr_ext); |
XAxiDma_BdWrite(BdVirtAddr, XAXIDMA_BD_NDESC_OFFSET, |
(PhysAddr & XAXIDMA_DESC_LSB_MASK)); |
XAxiDma_BdWrite(BdVirtAddr, XAXIDMA_BD_NDESC_MSB_OFFSET, |
UPPER_32_BITS(PhysAddr)); |
|
|
/* Setup the last BD's hardware information */ |
XAxiDma_BdWrite(BdVirtAddr, XAXIDMA_BD_HAS_STSCNTRL_OFFSET, |
(u32)RingPtr->HasStsCntrlStrm); |
|
XAxiDma_BdWrite(BdVirtAddr, XAXIDMA_BD_HAS_DRE_OFFSET, |
(((u32)(RingPtr->HasDRE)) << XAXIDMA_BD_HAS_DRE_SHIFT) | |
RingPtr->DataWidth); |
|
/* Setup and initialize pointers and counters */ |
RingPtr->RunState = AXIDMA_CHANNEL_HALTED; |
RingPtr->FirstBdAddr = VirtAddr; |
RingPtr->FirstBdPhysAddr = PhysAddr; |
RingPtr->LastBdAddr = BdVirtAddr; |
RingPtr->Length = RingPtr->LastBdAddr - RingPtr->FirstBdAddr + |
RingPtr->Separation; |
RingPtr->AllCnt = BdCount; |
RingPtr->FreeCnt = BdCount; |
RingPtr->FreeHead = (XAxiDma_Bd *) VirtAddr; |
RingPtr->PreHead = (XAxiDma_Bd *) VirtAddr; |
RingPtr->HwHead = (XAxiDma_Bd *) VirtAddr; |
RingPtr->HwTail = (XAxiDma_Bd *) VirtAddr; |
RingPtr->PostHead = (XAxiDma_Bd *) VirtAddr; |
RingPtr->BdaRestart = (XAxiDma_Bd *) PhysAddr; |
|
return XST_SUCCESS; |
} |
|
/*****************************************************************************/ |
/** |
* Clone the given BD into every BD in the ring. Only the fields offset from |
* XAXIDMA_BD_START_CLEAR are copied, for XAXIDMA_BD_BYTES_TO_CLEAR bytes. |
* This covers: BufferAddr, Control/Buffer length, status, APP words 0 - 4, |
* and software ID fields. |
* |
* This function can be called only when all BDs are in the free group such as |
* immediately after creation of the ring. This prevents modification |
* of BDs while they are in use by hardware or the application. |
* |
* @param RingPtr is the BD ring instance to be worked on. |
* @param SrcBdPtr is the source BD template to be cloned into the list. |
* |
* @return |
* - XST_SUCCESS if the list was modified. |
* - XST_DMA_SG_NO_LIST if a list has not been created. |
* - XST_DEVICE_IS_STARTED if the DMA channel has not been stopped. |
* - XST_DMA_SG_LIST_ERROR if some of the BDs in this channel are |
* under hardware or application control. |
* |
* @note This function can be used only when DMA is in SG mode |
* |
*****************************************************************************/ |
int XAxiDma_BdRingClone(XAxiDma_BdRing * RingPtr, XAxiDma_Bd * SrcBdPtr) |
{ |
int i; |
UINTPTR CurBd; |
u32 Save; |
XAxiDma_Bd TmpBd; |
|
/* Can't do this function if there isn't a ring */ |
if (RingPtr->AllCnt == 0) { |
|
xdbg_printf(XDBG_DEBUG_ERROR, "BdRingClone: no bds\r\n"); |
|
return XST_DMA_SG_NO_LIST; |
} |
|
/* Can't do this function with the channel running */ |
if (RingPtr->RunState == AXIDMA_CHANNEL_NOT_HALTED) { |
|
xdbg_printf(XDBG_DEBUG_ERROR, "BdRingClone: bd ring started " |
"already, cannot do\r\n"); |
|
return XST_DEVICE_IS_STARTED; |
} |
|
/* Can't do this function with some of the BDs in use */ |
if (RingPtr->FreeCnt != RingPtr->AllCnt) { |
|
xdbg_printf(XDBG_DEBUG_ERROR, "BdRingClone: some bds already " |
"in use %d/%d\r\n",RingPtr->FreeCnt, RingPtr->AllCnt); |
|
return XST_DMA_SG_LIST_ERROR; |
} |
|
/* Make a copy of the template then modify it by clearing |
* the complete bit in status/control field |
*/ |
memcpy(&TmpBd, SrcBdPtr, sizeof(XAxiDma_Bd)); |
|
Save = XAxiDma_BdRead(&TmpBd, XAXIDMA_BD_STS_OFFSET); |
Save &= ~XAXIDMA_BD_STS_COMPLETE_MASK; |
XAxiDma_BdWrite(&TmpBd, XAXIDMA_BD_STS_OFFSET, Save); |
|
for (i = 0, CurBd = RingPtr->FirstBdAddr; |
i < RingPtr->AllCnt; i++, CurBd += RingPtr->Separation) { |
|
memcpy((void *)((UINTPTR)CurBd + XAXIDMA_BD_START_CLEAR), |
(void *)((UINTPTR)(&TmpBd) + XAXIDMA_BD_START_CLEAR), |
XAXIDMA_BD_BYTES_TO_CLEAR); |
|
XAXIDMA_CACHE_FLUSH(CurBd); |
} |
|
return XST_SUCCESS; |
} |
|
/*****************************************************************************/ |
/** |
* Start a DMA channel and |
* Allow DMA transactions to commence on a given channel if descriptors are |
* ready to be processed. |
* |
* After a DMA channel is started, it is not halted, and it is idle (no active |
* DMA transfers). |
* |
* @param RingPtr is the Channel instance to be worked on |
* |
* @return |
* - XST_SUCCESS upon success |
* - XST_DMA_ERROR if no valid BD available to put into current |
* BD register |
* |
* @note This function can be used only when DMA is in SG mode |
* |
*****************************************************************************/ |
int XAxiDma_StartBdRingHw(XAxiDma_BdRing * RingPtr) |
{ |
u32 RegBase; |
int RingIndex = RingPtr->RingIndex; |
|
if (!XAxiDma_BdRingHwIsStarted(RingPtr)) { |
/* Start the hardware |
*/ |
RegBase = RingPtr->ChanBase; |
XAxiDma_WriteReg(RegBase, XAXIDMA_CR_OFFSET, |
XAxiDma_ReadReg(RegBase, XAXIDMA_CR_OFFSET) |
| XAXIDMA_CR_RUNSTOP_MASK); |
} |
|
if (XAxiDma_BdRingHwIsStarted(RingPtr)) { |
/* Note as started */ |
RingPtr->RunState = AXIDMA_CHANNEL_NOT_HALTED; |
|
/* If there are unprocessed BDs then we want the channel to begin |
* processing right away |
*/ |
if (RingPtr->HwCnt > 0) { |
|
XAXIDMA_CACHE_INVALIDATE(RingPtr->HwTail); |
|
if ((XAxiDma_BdRead(RingPtr->HwTail, |
XAXIDMA_BD_STS_OFFSET) & |
XAXIDMA_BD_STS_COMPLETE_MASK) == 0) { |
if (RingPtr->IsRxChannel) { |
if (!RingIndex) { |
XAxiDma_WriteReg(RingPtr->ChanBase, |
XAXIDMA_TDESC_OFFSET, (XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail) & XAXIDMA_DESC_LSB_MASK)); |
if (RingPtr->Addr_ext) |
XAxiDma_WriteReg(RingPtr->ChanBase, XAXIDMA_TDESC_MSB_OFFSET, |
UPPER_32_BITS(XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail))); |
} |
else { |
XAxiDma_WriteReg(RingPtr->ChanBase, |
(XAXIDMA_RX_TDESC0_OFFSET + |
(RingIndex - 1) * XAXIDMA_RX_NDESC_OFFSET), |
(XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail) & XAXIDMA_DESC_LSB_MASK )); |
if (RingPtr->Addr_ext) |
XAxiDma_WriteReg(RingPtr->ChanBase, |
(XAXIDMA_RX_TDESC0_MSB_OFFSET + |
(RingIndex - 1) * XAXIDMA_RX_NDESC_OFFSET), |
UPPER_32_BITS(XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail))); |
} |
} |
else { |
XAxiDma_WriteReg(RingPtr->ChanBase, |
XAXIDMA_TDESC_OFFSET, (XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail) & XAXIDMA_DESC_LSB_MASK)); |
if (RingPtr->Addr_ext) |
XAxiDma_WriteReg(RingPtr->ChanBase, XAXIDMA_TDESC_MSB_OFFSET, |
UPPER_32_BITS(XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail))); |
} |
} |
} |
|
return XST_SUCCESS; |
} |
|
return XST_DMA_ERROR; |
} |
|
/*****************************************************************************/ |
/** |
* Start a DMA channel, updates current descriptors and |
* Allow DMA transactions to commence on a given channel if descriptors are |
* ready to be processed. |
* |
* After a DMA channel is started, it is not halted, and it is idle (no active |
* DMA transfers). |
* |
* @param RingPtr is the Channel instance to be worked on |
* |
* @return |
* - XST_SUCCESS upon success |
* - XST_DMA_ERROR if no valid BD available to put into current |
* BD register |
* |
* @note This function can be used only when DMA is in SG mode |
* |
*****************************************************************************/ |
int XAxiDma_BdRingStart(XAxiDma_BdRing * RingPtr) |
{ |
int Status; |
|
Status = XAxiDma_UpdateBdRingCDesc(RingPtr); |
if (Status != XST_SUCCESS) { |
xdbg_printf(XDBG_DEBUG_ERROR, "BdRingStart: " |
"Updating Current Descriptor Failed\n\r"); |
return Status; |
} |
|
Status = XAxiDma_StartBdRingHw(RingPtr); |
if (Status != XST_SUCCESS) { |
xdbg_printf(XDBG_DEBUG_ERROR, "BdRingStart: " |
"Starting Hardware Failed\n\r"); |
return Status; |
} |
|
return XST_SUCCESS; |
} |
|
/*****************************************************************************/ |
/** |
* Set interrupt coalescing parameters for the given descriptor ring channel. |
* |
* @param RingPtr is a pointer to the descriptor ring instance to be |
* worked on. |
* @param Counter sets the packet counter on the channel. Valid range is |
* - 1..255. |
* - XAXIDMA_NO_CHANGE to leave this setting unchanged. |
* @param Timer sets the waitbound timer on the channel. Valid range is |
* - 0..255. |
* - XAXIDMA_NO_CHANGE to leave this setting unchanged. |
* Each unit depend on hardware building parameter |
* C_DLYTMR_RESOLUTION,which is in the range from 0 to 100,000 |
* clock cycles. A value of 0 disables the delay interrupt. |
* |
* @return |
* - XST_SUCCESS if interrupt coalescing settings updated |
* - XST_FAILURE if Counter or Timer parameters are out of range |
* |
* @note This function can be used only when DMA is in SG mode |
* |
*****************************************************************************/ |
int XAxiDma_BdRingSetCoalesce(XAxiDma_BdRing *RingPtr, u32 Counter, u32 Timer) |
{ |
u32 Cr; |
|
Cr = XAxiDma_ReadReg(RingPtr->ChanBase, XAXIDMA_CR_OFFSET); |
|
if (Counter != XAXIDMA_NO_CHANGE) { |
if ((Counter == 0) || (Counter > 0xFF)) { |
|
xdbg_printf(XDBG_DEBUG_ERROR, "BdRingSetCoalesce: " |
"invalid coalescing threshold %d", (int)Counter); |
return XST_FAILURE; |
} |
|
Cr = (Cr & ~XAXIDMA_COALESCE_MASK) | |
(Counter << XAXIDMA_COALESCE_SHIFT); |
} |
|
if (Timer != XAXIDMA_NO_CHANGE) { |
if (Timer > 0xFF) { |
|
xdbg_printf(XDBG_DEBUG_ERROR, "BdRingSetCoalesce: " |
"invalid delay counter %d", (int)Timer); |
|
return XST_FAILURE; |
} |
|
Cr = (Cr & ~XAXIDMA_DELAY_MASK) | |
(Timer << XAXIDMA_DELAY_SHIFT); |
} |
|
XAxiDma_WriteReg(RingPtr->ChanBase, XAXIDMA_CR_OFFSET, Cr); |
|
return XST_SUCCESS; |
} |
/*****************************************************************************/ |
/** |
* Retrieve current interrupt coalescing parameters from the given descriptor |
* ring channel. |
* |
* @param RingPtr is a pointer to the descriptor ring instance to be |
* worked on. |
* @param CounterPtr points to a memory location where the current packet |
* counter will be written. |
* @param TimerPtr points to a memory location where the current |
* waitbound timer will be written. |
* |
* @return The passed in parameters, CounterPtr and TimerPtr, holds the |
* references to the return values. |
* |
* @note This function can be used only when DMA is in SG mode |
* |
*****************************************************************************/ |
void XAxiDma_BdRingGetCoalesce(XAxiDma_BdRing * RingPtr, |
u32 *CounterPtr, u32 *TimerPtr) |
{ |
u32 Cr; |
|
Cr = XAxiDma_ReadReg(RingPtr->ChanBase, XAXIDMA_CR_OFFSET); |
|
*CounterPtr = ((Cr & XAXIDMA_COALESCE_MASK) >> XAXIDMA_COALESCE_SHIFT); |
*TimerPtr = ((Cr & XAXIDMA_DELAY_MASK) >> XAXIDMA_DELAY_SHIFT); |
} |
|
/*****************************************************************************/ |
/** |
* Reserve locations in the BD ring. The set of returned BDs may be modified in |
* preparation for future DMA transactions. Once the BDs are ready to be |
* submitted to hardware, the application must call XAxiDma_BdRingToHw() in the |
* same order which they were allocated here. Example: |
* |
* <pre> |
* NumBd = 2; |
* Status = XDsma_RingBdAlloc(MyRingPtr, NumBd, &MyBdSet); |
* |
* if (Status != XST_SUCCESS) |
* { |
* // Not enough BDs available for the request |
* } |
* |
* CurBd = MyBdSet; |
* for (i=0; i<NumBd; i++) |
* { |
* // Prepare CurBd..... |
* |
* // Onto next BD |
* CurBd = XAxiDma_BdRingNext(MyRingPtr, CurBd); |
* } |
* |
* // Give list to hardware |
* Status = XAxiDma_BdRingToHw(MyRingPtr, NumBd, MyBdSet); |
* </pre> |
* |
* A more advanced use of this function may allocate multiple sets of BDs. |
* They must be allocated and given to hardware in the correct sequence: |
* <pre> |
* // Legal |
* XAxiDma_BdRingAlloc(MyRingPtr, NumBd1, &MySet1); |
* XAxiDma_BdRingToHw(MyRingPtr, NumBd1, MySet1); |
* |
* // Legal |
* XAxiDma_BdRingAlloc(MyRingPtr, NumBd1, &MySet1); |
* XAxiDma_BdRingAlloc(MyRingPtr, NumBd2, &MySet2); |
* XAxiDma_BdRingToHw(MyRingPtr, NumBd1, MySet1); |
* XAxiDma_BdRingToHw(MyRingPtr, NumBd2, MySet2); |
* |
* // Not legal |
* XAxiDma_BdRingAlloc(MyRingPtr, NumBd1, &MySet1); |
* XAxiDma_BdRingAlloc(MyRingPtr, NumBd2, &MySet2); |
* XAxiDma_BdRingToHw(MyRingPtr, NumBd2, MySet2); |
* XAxiDma_BdRingToHw(MyRingPtr, NumBd1, MySet1); |
* </pre> |
* |
* Use the API defined in xaxidmabd.h to modify individual BDs. Traversal of |
* the BD set can be done using XAxiDma_BdRingNext() and XAxiDma_BdRingPrev(). |
* |
* @param RingPtr is a pointer to the descriptor ring instance to be |
* worked on. |
* @param NumBd is the number of BDs to allocate |
* @param BdSetPtr is an output parameter, it points to the first BD |
* available for modification. |
* |
* @return |
* - XST_SUCCESS if the requested number of BDs were returned in |
* the BdSetPtr parameter. |
* - XST_INVALID_PARAM if passed in NumBd is not positive |
* - XST_FAILURE if there were not enough free BDs to satisfy |
* the request. |
* |
* @note This function should not be preempted by another XAxiDma_BdRing |
* function call that modifies the BD space. It is the caller's |
* responsibility to provide a mutual exclusion mechanism. |
* |
* Do not modify more BDs than the number requested with the NumBd |
* parameter. Doing so will lead to data corruption and system |
* instability. |
* |
* This function can be used only when DMA is in SG mode |
* |
*****************************************************************************/ |
int XAxiDma_BdRingAlloc(XAxiDma_BdRing * RingPtr, int NumBd, |
XAxiDma_Bd ** BdSetPtr) |
{ |
if (NumBd <= 0) { |
|
xdbg_printf(XDBG_DEBUG_ERROR, "BdRingAlloc: negative BD " |
"number %d\r\n", NumBd); |
|
return XST_INVALID_PARAM; |
} |
|
/* Enough free BDs available for the request? */ |
if (RingPtr->FreeCnt < NumBd) { |
xdbg_printf(XDBG_DEBUG_ERROR, |
"Not enough BDs to alloc %d/%d\r\n", NumBd, RingPtr->FreeCnt); |
|
return XST_FAILURE; |
} |
|
/* Set the return argument and move FreeHead forward */ |
*BdSetPtr = RingPtr->FreeHead; |
XAXIDMA_RING_SEEKAHEAD(RingPtr, RingPtr->FreeHead, NumBd); |
RingPtr->FreeCnt -= NumBd; |
RingPtr->PreCnt += NumBd; |
|
return XST_SUCCESS; |
} |
/*****************************************************************************/ |
/** |
* Fully or partially undo an XAxiDma_BdRingAlloc() operation. Use this |
* function if all the BDs allocated by XAxiDma_BdRingAlloc() could not be |
* transferred to hardware with XAxiDma_BdRingToHw(). |
* |
* This function releases the BDs after they have been allocated but before |
* they have been given to hardware. |
* |
* This function is not the same as XAxiDma_BdRingFree(). The Free function |
* returns BDs to the free list after they have been processed by hardware, |
* while UnAlloc returns them before being processed by hardware. |
* |
* There are two scenarios where this function can be used. Full UnAlloc or |
* Partial UnAlloc. A Full UnAlloc means all the BDs Alloc'd will be returned: |
* |
* <pre> |
* Status = XAxiDma_BdRingAlloc(MyRingPtr, 10, &BdPtr); |
* ... |
* ... |
* if (Error) |
* { |
* Status = XAxiDma_BdRingUnAlloc(MyRingPtr, 10, &BdPtr); |
* } |
* </pre> |
* |
* A partial UnAlloc means some of the BDs Alloc'd will be returned: |
* |
* <pre> |
* Status = XAxiDma_BdRingAlloc(MyRingPtr, 10, &BdPtr); |
* BdsLeft = 10; |
* CurBdPtr = BdPtr; |
* |
* while (BdsLeft) |
* { |
* if (Error) |
* { |
* Status = XAxiDma_BdRingUnAlloc(MyRingPtr, BdsLeft, CurBdPtr); |
* } |
* |
* CurBdPtr = XAxiDma_BdRingNext(MyRingPtr, CurBdPtr); |
* BdsLeft--; |
* } |
* </pre> |
* |
* A partial UnAlloc must include the last BD in the list that was Alloc'd. |
* |
* @param RingPtr is a pointer to the descriptor ring instance to be |
* worked on. |
* @param NumBd is the number of BDs to unallocate |
* @param BdSetPtr points to the first of the BDs to be returned. |
* |
* @return |
* - XST_SUCCESS if the BDs were unallocated. |
* - XST_INVALID_PARAM if passed in NumBd is negative |
* - XST_FAILURE if NumBd parameter was greater that the number of |
* BDs in the preprocessing state. |
* |
* @note This function should not be preempted by another XAxiDma ring |
* function call that modifies the BD space. It is the caller's |
* responsibility to provide a mutual exclusion mechanism. |
* |
* This function can be used only when DMA is in SG mode |
* |
*****************************************************************************/ |
int XAxiDma_BdRingUnAlloc(XAxiDma_BdRing * RingPtr, int NumBd, |
XAxiDma_Bd * BdSetPtr) |
{ |
XAxiDma_Bd *TmpBd; |
|
if (NumBd <= 0) { |
|
xdbg_printf(XDBG_DEBUG_ERROR, "BdRingUnAlloc: negative BD" |
" number %d\r\n", NumBd); |
|
return XST_INVALID_PARAM; |
} |
|
/* Enough BDs in the preprocessing state for the request? */ |
if (RingPtr->PreCnt < NumBd) { |
xdbg_printf(XDBG_DEBUG_ERROR, |
"Pre-allocated BDs less than requested %d/%d\r\n", |
RingPtr->PreCnt, NumBd); |
|
return XST_FAILURE; |
} |
|
/* The last BD in the BD set must has the FreeHead as its next BD. |
* Otherwise, this is not a valid operation. |
*/ |
TmpBd = BdSetPtr; |
XAXIDMA_RING_SEEKAHEAD(RingPtr, TmpBd, NumBd); |
|
if (TmpBd != RingPtr->FreeHead) { |
xdbg_printf(XDBG_DEBUG_ERROR, |
"Unalloc does not go back to free head\r\n"); |
|
return XST_FAILURE; |
} |
|
/* Set the return argument and move FreeHead backward */ |
XAXIDMA_RING_SEEKBACK(RingPtr, RingPtr->FreeHead, NumBd); |
RingPtr->FreeCnt += NumBd; |
RingPtr->PreCnt -= NumBd; |
|
return XST_SUCCESS; |
} |
/*****************************************************************************/ |
/** |
* Enqueue a set of BDs to hardware that were previously allocated by |
* XAxiDma_BdRingAlloc(). Once this function returns, the argument BD set goes |
* under hardware control. Changes to these BDs should be held until they are |
* finished by hardware to avoid data corruption and system instability. |
* |
* For transmit, the set will be rejected if the last BD of the set does not |
* mark the end of a packet or the first BD does not mark the start of a packet. |
* |
* @param RingPtr is a pointer to the descriptor ring instance to be |
* worked on. |
* @param NumBd is the number of BDs in the set. |
* @param BdSetPtr is the first BD of the set to commit to hardware. |
* |
* @return |
* - XST_SUCCESS if the set of BDs was accepted and enqueued to |
* hardware |
* - XST_INVALID_PARAM if passed in NumBd is negative |
* - XST_FAILURE if the set of BDs was rejected because the first |
* BD does not have its start-of-packet bit set, or the last BD |
* does not have its end-of-packet bit set, or any one of the BDs |
* has 0 length. |
* - XST_DMA_SG_LIST_ERROR if this function was called out of |
* sequence with XAxiDma_BdRingAlloc() |
* |
* @note This function should not be preempted by another XAxiDma ring |
* function call that modifies the BD space. It is the caller's |
* responsibility to provide a mutual exclusion mechanism. |
* |
* This function can be used only when DMA is in SG mode |
* |
*****************************************************************************/ |
int XAxiDma_BdRingToHw(XAxiDma_BdRing * RingPtr, int NumBd, |
XAxiDma_Bd * BdSetPtr) |
{ |
XAxiDma_Bd *CurBdPtr; |
int i; |
u32 BdCr; |
u32 BdSts; |
int RingIndex = RingPtr->RingIndex; |
|
if (NumBd < 0) { |
|
xdbg_printf(XDBG_DEBUG_ERROR, "BdRingToHw: negative BD number " |
"%d\r\n", NumBd); |
|
return XST_INVALID_PARAM; |
} |
|
/* If the commit set is empty, do nothing */ |
if (NumBd == 0) { |
return XST_SUCCESS; |
} |
|
/* Make sure we are in sync with XAxiDma_BdRingAlloc() */ |
if ((RingPtr->PreCnt < NumBd) || (RingPtr->PreHead != BdSetPtr)) { |
|
xdbg_printf(XDBG_DEBUG_ERROR, "Bd ring has problems\r\n"); |
return XST_DMA_SG_LIST_ERROR; |
} |
|
CurBdPtr = BdSetPtr; |
BdCr = XAxiDma_BdGetCtrl(CurBdPtr); |
BdSts = XAxiDma_BdGetSts(CurBdPtr); |
|
/* In case of Tx channel, the first BD should have been marked |
* as start-of-frame |
*/ |
if (!(RingPtr->IsRxChannel) && !(BdCr & XAXIDMA_BD_CTRL_TXSOF_MASK)) { |
|
xdbg_printf(XDBG_DEBUG_ERROR, "Tx first BD does not have " |
"SOF\r\n"); |
|
return XST_FAILURE; |
} |
|
/* Clear the completed status bit |
*/ |
for (i = 0; i < NumBd - 1; i++) { |
|
/* Make sure the length value in the BD is non-zero. */ |
if (XAxiDma_BdGetLength(CurBdPtr, |
RingPtr->MaxTransferLen) == 0) { |
|
xdbg_printf(XDBG_DEBUG_ERROR, "0 length bd\r\n"); |
|
return XST_FAILURE; |
} |
|
BdSts &= ~XAXIDMA_BD_STS_COMPLETE_MASK; |
XAxiDma_BdWrite(CurBdPtr, XAXIDMA_BD_STS_OFFSET, BdSts); |
|
/* Flush the current BD so DMA core could see the updates */ |
XAXIDMA_CACHE_FLUSH(CurBdPtr); |
|
CurBdPtr = (XAxiDma_Bd *)((void *)XAxiDma_BdRingNext(RingPtr, CurBdPtr)); |
BdCr = XAxiDma_BdRead(CurBdPtr, XAXIDMA_BD_CTRL_LEN_OFFSET); |
BdSts = XAxiDma_BdRead(CurBdPtr, XAXIDMA_BD_STS_OFFSET); |
} |
|
/* In case of Tx channel, the last BD should have EOF bit set */ |
if (!(RingPtr->IsRxChannel) && !(BdCr & XAXIDMA_BD_CTRL_TXEOF_MASK)) { |
|
xdbg_printf(XDBG_DEBUG_ERROR, "Tx last BD does not have " |
"EOF\r\n"); |
|
return XST_FAILURE; |
} |
|
/* Make sure the length value in the last BD is non-zero. */ |
if (XAxiDma_BdGetLength(CurBdPtr, |
RingPtr->MaxTransferLen) == 0) { |
|
xdbg_printf(XDBG_DEBUG_ERROR, "0 length bd\r\n"); |
|
return XST_FAILURE; |
} |
|
/* The last BD should also have the completed status bit cleared |
*/ |
BdSts &= ~XAXIDMA_BD_STS_COMPLETE_MASK; |
XAxiDma_BdWrite(CurBdPtr, XAXIDMA_BD_STS_OFFSET, BdSts); |
|
/* Flush the last BD so DMA core could see the updates */ |
XAXIDMA_CACHE_FLUSH(CurBdPtr); |
DATA_SYNC; |
|
/* This set has completed pre-processing, adjust ring pointers and |
* counters |
*/ |
XAXIDMA_RING_SEEKAHEAD(RingPtr, RingPtr->PreHead, NumBd); |
RingPtr->PreCnt -= NumBd; |
RingPtr->HwTail = CurBdPtr; |
RingPtr->HwCnt += NumBd; |
|
/* If it is running, signal the engine to begin processing */ |
if (RingPtr->RunState == AXIDMA_CHANNEL_NOT_HALTED) { |
if (RingPtr->IsRxChannel) { |
if (!RingIndex) { |
XAxiDma_WriteReg(RingPtr->ChanBase, |
XAXIDMA_TDESC_OFFSET, (XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail) & XAXIDMA_DESC_LSB_MASK)); |
if (RingPtr->Addr_ext) |
XAxiDma_WriteReg(RingPtr->ChanBase, XAXIDMA_TDESC_MSB_OFFSET, |
UPPER_32_BITS(XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail))); |
} |
else { |
XAxiDma_WriteReg(RingPtr->ChanBase, |
(XAXIDMA_RX_TDESC0_OFFSET + |
(RingIndex - 1) * XAXIDMA_RX_NDESC_OFFSET), |
(XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail) & XAXIDMA_DESC_LSB_MASK )); |
if (RingPtr->Addr_ext) |
XAxiDma_WriteReg(RingPtr->ChanBase, |
(XAXIDMA_RX_TDESC0_MSB_OFFSET + |
(RingIndex - 1) * XAXIDMA_RX_NDESC_OFFSET), |
UPPER_32_BITS(XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail))); |
} |
} |
else { |
XAxiDma_WriteReg(RingPtr->ChanBase, |
XAXIDMA_TDESC_OFFSET, (XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail) & XAXIDMA_DESC_LSB_MASK)); |
if (RingPtr->Addr_ext) |
XAxiDma_WriteReg(RingPtr->ChanBase, XAXIDMA_TDESC_MSB_OFFSET, |
UPPER_32_BITS(XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail))); |
} |
} |
|
return XST_SUCCESS; |
} |
|
/*****************************************************************************/ |
/** |
* Returns a set of BD(s) that have been processed by hardware. The returned |
* BDs may be examined by the application to determine the outcome of the DMA |
* transactions. Once the BDs have been examined, the application must call |
* XAxiDma_BdRingFree() in the same order which they were retrieved here. |
* |
* Example: |
* |
* <pre> |
* NumBd = XAxiDma_BdRingFromHw(MyRingPtr, XAXIDMA_ALL_BDS, &MyBdSet); |
* |
* if (NumBd == 0) |
* { |
* // hardware has nothing ready for us yet |
* } |
* |
* CurBd = MyBdSet; |
* for (i=0; i<NumBd; i++) |
* { |
* // Examine CurBd for post processing..... |
* |
* // Onto next BD |
* CurBd = XAxiDma_BdRingNext(MyRingPtr, CurBd); |
* } |
* |
* XAxiDma_BdRingFree(MyRingPtr, NumBd, MyBdSet); // Return the list |
* </pre> |
* |
* A more advanced use of this function may allocate multiple sets of BDs. |
* They must be retrieved from hardware and freed in the correct sequence: |
* <pre> |
* // Legal |
* XAxiDma_BdRingFromHw(MyRingPtr, NumBd1, &MySet1); |
* XAxiDma_BdRingFree(MyRingPtr, NumBd1, MySet1); |
* |
* // Legal |
* XAxiDma_BdRingFromHw(MyRingPtr, NumBd1, &MySet1); |
* XAxiDma_BdRingFromHw(MyRingPtr, NumBd2, &MySet2); |
* XAxiDma_BdRingFree(MyRingPtr, NumBd1, MySet1); |
* XAxiDma_BdRingFree(MyRingPtr, NumBd2, MySet2); |
* |
* // Not legal |
* XAxiDma_BdRingFromHw(MyRingPtr, NumBd1, &MySet1); |
* XAxiDma_BdRingFromHw(MyRingPtr, NumBd2, &MySet2); |
* XAxiDma_BdRingFree(MyRingPtr, NumBd2, MySet2); |
* XAxiDma_BdRingFree(MyRingPtr, NumBd1, MySet1); |
* </pre> |
* |
* If hardware has partially completed a packet spanning multiple BDs, then |
* none of the BDs for that packet will be included in the results. |
* |
* @param RingPtr is a pointer to the descriptor ring instance to be |
* worked on. |
* @param BdLimit is the maximum number of BDs to return in the set. Use |
* XAXIDMA_ALL_BDS to return all BDs that have been processed. |
* @param BdSetPtr is an output parameter, it points to the first BD |
* available for examination. |
* |
* @return The number of BDs processed by hardware. A value of 0 indicates |
* that no data is available. No more than BdLimit BDs will be |
* returned. |
* |
* @note Treat BDs returned by this function as read-only. |
* |
* This function should not be preempted by another XAxiDma ring |
* function call that modifies the BD space. It is the caller's |
* responsibility to provide a mutual exclusion mechanism. |
* |
* This function can be used only when DMA is in SG mode |
* |
*****************************************************************************/ |
int XAxiDma_BdRingFromHw(XAxiDma_BdRing * RingPtr, int BdLimit, |
XAxiDma_Bd ** BdSetPtr) |
{ |
XAxiDma_Bd *CurBdPtr; |
int BdCount; |
int BdPartialCount; |
u32 BdSts; |
u32 BdCr; |
|
CurBdPtr = RingPtr->HwHead; |
BdCount = 0; |
BdPartialCount = 0; |
BdSts = 0; |
BdCr = 0; |
|
/* If no BDs in work group, then there's nothing to search */ |
if (RingPtr->HwCnt == 0) { |
*BdSetPtr = (XAxiDma_Bd *)NULL; |
|
return 0; |
} |
|
if (BdLimit > RingPtr->HwCnt) { |
BdLimit = RingPtr->HwCnt; |
} |
|
/* Starting at HwHead, keep moving forward in the list until: |
* - A BD is encountered with its completed bit clear in the status |
* word which means hardware has not completed processing of that |
* BD. |
* - RingPtr->HwTail is reached |
* - The number of requested BDs has been processed |
*/ |
|
while (BdCount < BdLimit) { |
/* Read the status */ |
XAXIDMA_CACHE_INVALIDATE(CurBdPtr); |
BdSts = XAxiDma_BdRead(CurBdPtr, XAXIDMA_BD_STS_OFFSET); |
BdCr = XAxiDma_BdRead(CurBdPtr, XAXIDMA_BD_CTRL_LEN_OFFSET); |
|
/* If the hardware still hasn't processed this BD then we are |
* done |
*/ |
if (!(BdSts & XAXIDMA_BD_STS_COMPLETE_MASK)) { |
break; |
} |
|
BdCount++; |
|
/* Hardware has processed this BD so check the "last" bit. If |
* it is clear, then there are more BDs for the current packet. |
* Keep a count of these partial packet BDs. |
* |
* For tx BDs, EOF bit is in the control word |
* For rx BDs, EOF bit is in the status word |
*/ |
if (((!(RingPtr->IsRxChannel) && |
(BdCr & XAXIDMA_BD_CTRL_TXEOF_MASK)) || |
((RingPtr->IsRxChannel) && (BdSts & |
XAXIDMA_BD_STS_RXEOF_MASK)))) { |
|
BdPartialCount = 0; |
} |
else { |
BdPartialCount++; |
} |
|
/* Reached the end of the work group */ |
if (CurBdPtr == RingPtr->HwTail) { |
break; |
} |
|
/* Move on to the next BD in work group */ |
CurBdPtr = (XAxiDma_Bd *)((void *)XAxiDma_BdRingNext(RingPtr, CurBdPtr)); |
} |
|
/* Subtract off any partial packet BDs found */ |
BdCount -= BdPartialCount; |
|
/* If BdCount is non-zero then BDs were found to return. Set return |
* parameters, update pointers and counters, return success |
*/ |
if (BdCount) { |
*BdSetPtr = RingPtr->HwHead; |
RingPtr->HwCnt -= BdCount; |
RingPtr->PostCnt += BdCount; |
XAXIDMA_RING_SEEKAHEAD(RingPtr, RingPtr->HwHead, BdCount); |
|
return BdCount; |
} |
else { |
*BdSetPtr = (XAxiDma_Bd *)NULL; |
|
return 0; |
} |
} |
/*****************************************************************************/ |
/** |
* Frees a set of BDs that had been previously retrieved with |
* XAxiDma_BdRingFromHw(). |
* |
* @param RingPtr is a pointer to the descriptor ring instance to be |
* worked on. |
* @param NumBd is the number of BDs to free. |
* @param BdSetPtr is the head of a list of BDs returned by |
* XAxiDma_BdRingFromHw(). |
* |
* @return |
* - XST_SUCCESS if the set of BDs was freed. |
* - XST_INVALID_PARAM if NumBd is negative |
* - XST_DMA_SG_LIST_ERROR if this function was called out of |
* sequence with XAxiDma_BdRingFromHw(). |
* |
* @note This function should not be preempted by another XAxiDma |
* function call that modifies the BD space. It is the caller's |
* responsibility to ensure mutual exclusion. |
* |
* This function can be used only when DMA is in SG mode |
* |
*****************************************************************************/ |
int XAxiDma_BdRingFree(XAxiDma_BdRing * RingPtr, int NumBd, |
XAxiDma_Bd * BdSetPtr) |
{ |
if (NumBd < 0) { |
|
xdbg_printf(XDBG_DEBUG_ERROR, |
"BdRingFree: negative BDs %d\r\n", NumBd); |
|
return XST_INVALID_PARAM; |
} |
|
/* If the BD Set to free is empty, do nothing |
*/ |
if (NumBd == 0) { |
return XST_SUCCESS; |
} |
|
/* Make sure we are in sync with XAxiDma_BdRingFromHw() */ |
if ((RingPtr->PostCnt < NumBd) || (RingPtr->PostHead != BdSetPtr)) { |
|
xdbg_printf(XDBG_DEBUG_ERROR, "BdRingFree: Error free BDs: " |
"post count %d to free %d, PostHead %x to free ptr %x\r\n", |
RingPtr->PostCnt, NumBd, |
(UINTPTR)RingPtr->PostHead, |
(UINTPTR)BdSetPtr); |
|
return XST_DMA_SG_LIST_ERROR; |
} |
|
/* Update pointers and counters */ |
RingPtr->FreeCnt += NumBd; |
RingPtr->PostCnt -= NumBd; |
XAXIDMA_RING_SEEKAHEAD(RingPtr, RingPtr->PostHead, NumBd); |
|
return XST_SUCCESS; |
} |
/*****************************************************************************/ |
/** |
* Check the internal data structures of the BD ring for the provided channel. |
* The following checks are made: |
* |
* - The BD ring is linked correctly in physical address space. |
* - The internal pointers point to BDs in the ring. |
* - The internal counters add up. |
* |
* The channel should be stopped (through XAxiDma_Pause() or XAxiDma_Reset()) |
* prior to calling this function. |
* |
* @param RingPtr is a pointer to the descriptor ring to be worked on. |
* |
* @return |
* - XST_SUCCESS if no errors were found. |
* - XST_DMA_SG_NO_LIST if the ring has not been created. |
* - XST_IS_STARTED if the channel is not stopped. |
* - XST_DMA_SG_LIST_ERROR if a problem is found with the internal |
* data structures. If this value is returned, the channel should |
* be reset,and the BD ring should be recreated through |
* XAxiDma_BdRingCreate() to avoid data corruption or system |
* instability. |
* |
* @note This function can be used only when DMA is in SG mode |
* |
*****************************************************************************/ |
int XAxiDma_BdRingCheck(XAxiDma_BdRing * RingPtr) |
{ |
u32 AddrV; |
u32 AddrP; |
int i; |
|
/* Is the list created */ |
if (RingPtr->AllCnt == 0) { |
|
xdbg_printf(XDBG_DEBUG_ERROR, "BdRingCheck: no BDs\r\n"); |
|
return XST_DMA_SG_NO_LIST; |
} |
|
/* Can't check if channel is running */ |
if (RingPtr->RunState == AXIDMA_CHANNEL_NOT_HALTED) { |
|
xdbg_printf(XDBG_DEBUG_ERROR, "BdRingCheck: Bd ring is " |
"running, cannot check it\r\n"); |
|
return XST_IS_STARTED; |
} |
|
/* RunState doesn't make sense */ |
else if (RingPtr->RunState != AXIDMA_CHANNEL_HALTED) { |
|
xdbg_printf(XDBG_DEBUG_ERROR, "BdRingCheck: unknown BD ring " |
"state %d ", RingPtr->RunState); |
|
return XST_DMA_SG_LIST_ERROR; |
} |
|
/* Verify internal pointers point to correct memory space */ |
AddrV = (UINTPTR) RingPtr->FreeHead; |
if ((AddrV < RingPtr->FirstBdAddr) || (AddrV > RingPtr->LastBdAddr)) { |
|
xdbg_printf(XDBG_DEBUG_ERROR, "BdRingCheck: FreeHead wrong " |
"%x, should be in range of %x/%x\r\n", |
(unsigned int)AddrV, |
(unsigned int)RingPtr->FirstBdAddr, |
(unsigned int)RingPtr->LastBdAddr); |
|
return XST_DMA_SG_LIST_ERROR; |
} |
|
AddrV = (UINTPTR) RingPtr->PreHead; |
if ((AddrV < RingPtr->FirstBdAddr) || (AddrV > RingPtr->LastBdAddr)) { |
|
xdbg_printf(XDBG_DEBUG_ERROR, "BdRingCheck: PreHead wrong %x, " |
"should be in range of %x/%x\r\n", |
(unsigned int)AddrV, |
(unsigned int)RingPtr->FirstBdAddr, |
(unsigned int)RingPtr->LastBdAddr); |
|
return XST_DMA_SG_LIST_ERROR; |
} |
|
AddrV = (UINTPTR) RingPtr->HwHead; |
if ((AddrV < RingPtr->FirstBdAddr) || (AddrV > RingPtr->LastBdAddr)) { |
|
xdbg_printf(XDBG_DEBUG_ERROR, "BdRingCheck: HwHead wrong %x, " |
"should be in range of %x/%x\r\n", |
(unsigned int)AddrV, |
(unsigned int)RingPtr->FirstBdAddr, |
(unsigned int)RingPtr->LastBdAddr); |
|
return XST_DMA_SG_LIST_ERROR; |
} |
|
AddrV = (UINTPTR) RingPtr->HwTail; |
if ((AddrV < RingPtr->FirstBdAddr) || (AddrV > RingPtr->LastBdAddr)) { |
|
xdbg_printf(XDBG_DEBUG_ERROR, "BdRingCheck: HwTail wrong %x, " |
"should be in range of %x/%x\r\n", |
(unsigned int)AddrV, |
(unsigned int)RingPtr->FirstBdAddr, |
(unsigned int)RingPtr->LastBdAddr); |
|
return XST_DMA_SG_LIST_ERROR; |
} |
|
AddrV = (UINTPTR) RingPtr->PostHead; |
if ((AddrV < RingPtr->FirstBdAddr) || (AddrV > RingPtr->LastBdAddr)) { |
|
xdbg_printf(XDBG_DEBUG_ERROR, "BdRingCheck: PostHead wrong " |
"%x, should be in range of %x/%x\r\n", |
(unsigned int)AddrV, |
(unsigned int)RingPtr->FirstBdAddr, |
(unsigned int)RingPtr->LastBdAddr); |
|
return XST_DMA_SG_LIST_ERROR; |
} |
|
/* Verify internal counters add up */ |
if ((RingPtr->HwCnt + RingPtr->PreCnt + RingPtr->FreeCnt + |
RingPtr->PostCnt) != RingPtr->AllCnt) { |
|
xdbg_printf(XDBG_DEBUG_ERROR, "BdRingCheck: internal counter " |
"error\r\n"); |
|
return XST_DMA_SG_LIST_ERROR; |
} |
|
/* Verify BDs are linked correctly */ |
AddrV = RingPtr->FirstBdAddr; |
AddrP = RingPtr->FirstBdPhysAddr + RingPtr->Separation; |
for (i = 1; i < RingPtr->AllCnt; i++) { |
XAXIDMA_CACHE_INVALIDATE(AddrV); |
/* Check next pointer for this BD. It should equal to the |
* physical address of next BD |
*/ |
if (XAxiDma_BdRead(AddrV, XAXIDMA_BD_NDESC_OFFSET) != AddrP) { |
|
xdbg_printf(XDBG_DEBUG_ERROR, "BdRingCheck: Next Bd " |
"ptr %x wrong, expect %x\r\n", |
(unsigned int)XAxiDma_BdRead(AddrV, |
XAXIDMA_BD_NDESC_OFFSET), |
(unsigned int)AddrP); |
|
return XST_DMA_SG_LIST_ERROR; |
} |
|
/* Move on to next BD */ |
AddrV += RingPtr->Separation; |
AddrP += RingPtr->Separation; |
} |
|
XAXIDMA_CACHE_INVALIDATE(AddrV); |
/* Last BD should point back to the beginning of ring */ |
if (XAxiDma_BdRead(AddrV, XAXIDMA_BD_NDESC_OFFSET) != |
RingPtr->FirstBdPhysAddr) { |
|
xdbg_printf(XDBG_DEBUG_ERROR, "BdRingCheck: last Bd Next BD " |
"ptr %x wrong, expect %x\r\n", |
(unsigned int)XAxiDma_BdRead(AddrV, |
XAXIDMA_BD_NDESC_OFFSET), |
(unsigned int)RingPtr->FirstBdPhysAddr); |
|
return XST_DMA_SG_LIST_ERROR; |
} |
|
/* No problems found */ |
return XST_SUCCESS; |
} |
/*****************************************************************************/ |
/** |
* Dump the registers for a channel. |
* |
* @param RingPtr is a pointer to the descriptor ring to be worked on. |
* |
* @return None |
* |
* @note This function can be used only when DMA is in SG mode |
* |
*****************************************************************************/ |
void XAxiDma_BdRingDumpRegs(XAxiDma_BdRing *RingPtr) { |
u32 RegBase = RingPtr->ChanBase; |
int RingIndex = RingPtr->RingIndex; |
|
xil_printf("Dump registers %x:\r\n", (unsigned int)RegBase); |
xil_printf("Control REG: %08x\r\n", |
(unsigned int)XAxiDma_ReadReg(RegBase, XAXIDMA_CR_OFFSET)); |
xil_printf("Status REG: %08x\r\n", |
(unsigned int)XAxiDma_ReadReg(RegBase, XAXIDMA_SR_OFFSET)); |
|
if (RingIndex) { |
xil_printf("Cur BD REG: %08x\r\n", |
(unsigned int)XAxiDma_ReadReg(RegBase, |
XAXIDMA_RX_CDESC0_OFFSET + ((RingIndex - 1) * |
XAXIDMA_RX_NDESC_OFFSET))); |
xil_printf("Tail BD REG: %08x\r\n", |
(unsigned int)XAxiDma_ReadReg(RegBase, |
XAXIDMA_RX_TDESC0_OFFSET + ((RingIndex - 1) * |
XAXIDMA_RX_NDESC_OFFSET))); |
} |
else { |
xil_printf("Cur BD REG: %08x\r\n", |
(unsigned int)XAxiDma_ReadReg(RegBase, XAXIDMA_CDESC_OFFSET)); |
xil_printf("Tail BD REG: %08x\r\n", |
(unsigned int)XAxiDma_ReadReg(RegBase, XAXIDMA_TDESC_OFFSET)); |
} |
|
xil_printf("\r\n"); |
} |
/** @} */ |
/trunk/sw/dev/test_main/src/_hdl/bsp/libsrc/axidma_v9_0/src/xaxidma_bdring.h
0,0 → 1,526
/****************************************************************************** |
* |
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. |
* |
* Permission is hereby granted, free of charge, to any person obtaining a copy |
* of this software and associated documentation files (the "Software"), to deal |
* in the Software without restriction, including without limitation the rights |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
* copies of the Software, and to permit persons to whom the Software is |
* furnished to do so, subject to the following conditions: |
* |
* The above copyright notice and this permission notice shall be included in |
* all copies or substantial portions of the Software. |
* |
* Use of the Software is limited solely to applications: |
* (a) running on a Xilinx device, or |
* (b) that interact with a Xilinx device through a bus or interconnect. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF |
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
* SOFTWARE. |
* |
* Except as contained in this notice, the name of the Xilinx shall not be used |
* in advertising or otherwise to promote the sale, use or other dealings in |
* this Software without prior written authorization from Xilinx. |
* |
******************************************************************************/ |
/*****************************************************************************/ |
/** |
* |
* @file xaxidma_bdring.h |
* @addtogroup axidma_v9_0 |
* @{ |
* |
* This file contains DMA channel related structure and constant definition |
* as well as function prototypes. Each DMA channel is managed by a Buffer |
* Descriptor ring, and XAxiDma_BdRing is chosen as the symbol prefix used in |
* this file. See xaxidma.h for more information on how a BD ring is managed. |
* |
* <pre> |
* MODIFICATION HISTORY: |
* |
* Ver Who Date Changes |
* ----- ---- -------- ------------------------------------------------------- |
* 1.00a jz 05/18/10 First release |
* 2.00a jz 08/10/10 Second release, added in xaxidma_g.c, xaxidma_sinit.c, |
* updated tcl file, added xaxidma_porting_guide.h |
* 3.00a jz 11/22/10 Support IP core parameters change |
* 6.00a srt 01/24/12 Added support for Multi-Channel DMA. |
* - New API |
* * XAxiDma_UpdateBdRingCDesc(XAxiDma_BdRing * RingPtr, |
* int RingIndex) |
* - Changed APIs |
* * XAxiDma_StartBdRingHw(XAxiDma_BdRing * RingPtr, |
* int RingIndex) |
* * XAxiDma_BdRingStart(XAxiDma_BdRing * RingPtr, |
* int RingIndex) |
* * XAxiDma_BdRingToHw(XAxiDma_BdRing * RingPtr, |
* int NumBd, XAxiDma_Bd * BdSetPtr, int RingIndex) |
* * XAxiDma_BdRingDumpRegs(XAxiDma_BdRing * RingPtr, |
* int RingIndex) |
* * XAxiDma_BdRingSnapShotCurrBd(XAxiDma_BdRing * RingPtr, |
* int RingIndex) |
* 7.00a srt 06/18/12 All the APIs changed in v6_00_a are reverted back for |
* backward compatibility. |
* |
* |
* </pre> |
* |
******************************************************************************/ |
|
#ifndef XAXIDMA_BDRING_H_ /* prevent circular inclusions */ |
#define XAXIDMA_BDRING_H_ |
|
#ifdef __cplusplus |
extern "C" { |
#endif |
|
/***************************** Include Files *********************************/ |
|
#include "xstatus.h" |
#include "xaxidma_bd.h" |
|
|
|
/************************** Constant Definitions *****************************/ |
/* State of a DMA channel |
*/ |
#define AXIDMA_CHANNEL_NOT_HALTED 1 |
#define AXIDMA_CHANNEL_HALTED 2 |
|
/* Argument constant to simplify argument setting |
*/ |
#define XAXIDMA_NO_CHANGE 0xFFFFFFFF |
#define XAXIDMA_ALL_BDS 0x0FFFFFFF /* 268 Million */ |
|
/**************************** Type Definitions *******************************/ |
|
/** Container structure for descriptor storage control. If address translation |
* is enabled, then all addresses and pointers excluding FirstBdPhysAddr are |
* expressed in terms of the virtual address. |
*/ |
typedef struct { |
u32 ChanBase; /**< physical base address*/ |
|
int IsRxChannel; /**< Is this a receive channel */ |
volatile int RunState; /**< Whether channel is running */ |
int HasStsCntrlStrm; /**< Whether has stscntrl stream */ |
int HasDRE; |
int DataWidth; |
int Addr_ext; |
u32 MaxTransferLen; |
|
UINTPTR FirstBdPhysAddr; /**< Physical address of 1st BD in list */ |
UINTPTR FirstBdAddr; /**< Virtual address of 1st BD in list */ |
UINTPTR LastBdAddr; /**< Virtual address of last BD in the list */ |
u32 Length; /**< Total size of ring in bytes */ |
UINTPTR Separation; /**< Number of bytes between the starting |
address of adjacent BDs */ |
XAxiDma_Bd *FreeHead; /**< First BD in the free group */ |
XAxiDma_Bd *PreHead; /**< First BD in the pre-work group */ |
XAxiDma_Bd *HwHead; /**< First BD in the work group */ |
XAxiDma_Bd *HwTail; /**< Last BD in the work group */ |
XAxiDma_Bd *PostHead; /**< First BD in the post-work group */ |
XAxiDma_Bd *BdaRestart; /**< BD to load when channel is started */ |
int FreeCnt; /**< Number of allocatable BDs in free group */ |
int PreCnt; /**< Number of BDs in pre-work group */ |
int HwCnt; /**< Number of BDs in work group */ |
int PostCnt; /**< Number of BDs in post-work group */ |
int AllCnt; /**< Total Number of BDs for channel */ |
int RingIndex; /**< Ring Index */ |
} XAxiDma_BdRing; |
|
/***************** Macros (Inline Functions) Definitions *********************/ |
|
/*****************************************************************************/ |
/** |
* Use this macro at initialization time to determine how many BDs will fit |
* within the given memory constraints. |
* |
* The results of this macro can be provided to XAxiDma_BdRingCreate(). |
* |
* @param Alignment specifies what byte alignment the BDs must fall |
* on and must be a power of 2 to get an accurate calculation |
* (32, 64, 126,...) |
* @param Bytes is the number of bytes to be used to store BDs. |
* |
* @return Number of BDs that can fit in the given memory area |
* |
* @note |
* C-style signature: |
* int XAxiDma_BdRingCntCalc(u32 Alignment, u32 Bytes) |
* This function is used only when system is configured as SG mode |
* |
******************************************************************************/ |
#define XAxiDma_BdRingCntCalc(Alignment, Bytes) \ |
(uint32_t)((Bytes)/((sizeof(XAxiDma_Bd)+((Alignment)-1))&~((Alignment)-1))) |
|
/*****************************************************************************/ |
/** |
* Use this macro at initialization time to determine how many bytes of memory |
* are required to contain a given number of BDs at a given alignment. |
* |
* @param Alignment specifies what byte alignment the BDs must fall on. |
* This parameter must be a power of 2 to get an accurate |
* calculation (32, 64,128,...) |
* @param NumBd is the number of BDs to calculate memory size |
* requirements |
* |
* @return The number of bytes of memory required to create a BD list |
* with the given memory constraints. |
* |
* @note |
* C-style signature: |
* int XAxiDma_BdRingMemCalc(u32 Alignment, u32 NumBd) |
* This function is used only when system is configured as SG mode |
* |
******************************************************************************/ |
#define XAxiDma_BdRingMemCalc(Alignment, NumBd) \ |
(int)((sizeof(XAxiDma_Bd)+((Alignment)-1)) & ~((Alignment)-1))*(NumBd) |
|
/****************************************************************************/ |
/** |
* Return the total number of BDs allocated by this channel with |
* XAxiDma_BdRingCreate(). |
* |
* @param RingPtr is the BD ring to operate on. |
* |
* @return The total number of BDs allocated for this channel. |
* |
* @note |
* C-style signature: |
* int XAxiDma_BdRingGetCnt(XAxiDma_BdRing* RingPtr) |
* This function is used only when system is configured as SG mode |
* |
*****************************************************************************/ |
#define XAxiDma_BdRingGetCnt(RingPtr) ((RingPtr)->AllCnt) |
|
/****************************************************************************/ |
/** |
* Return the number of BDs allocatable with XAxiDma_BdRingAlloc() for pre- |
* processing. |
* |
* @param RingPtr is the BD ring to operate on. |
* |
* @return The number of BDs currently allocatable. |
* |
* @note |
* C-style signature: |
* int XAxiDma_BdRingGetFreeCnt(XAxiDma_BdRing* RingPtr) |
* This function is used only when system is configured as SG mode |
* |
*****************************************************************************/ |
#define XAxiDma_BdRingGetFreeCnt(RingPtr) ((RingPtr)->FreeCnt) |
|
|
/****************************************************************************/ |
/** |
* Snap shot the latest BD a BD ring is processing. |
* |
* @param RingPtr is the BD ring to operate on. |
* |
* @return None |
* |
* @note |
* C-style signature: |
* void XAxiDma_BdRingSnapShotCurrBd(XAxiDma_BdRing* RingPtr) |
* This function is used only when system is configured as SG mode |
* |
*****************************************************************************/ |
#define XAxiDma_BdRingSnapShotCurrBd(RingPtr) \ |
{ \ |
if (!RingPtr->IsRxChannel) { \ |
(RingPtr)->BdaRestart = \ |
XAxiDma_ReadReg((RingPtr)->ChanBase, \ |
XAXIDMA_CDESC_OFFSET); \ |
} else { \ |
if (!RingPtr->RingIndex) { \ |
(RingPtr)->BdaRestart = \ |
XAxiDma_ReadReg( \ |
(RingPtr)->ChanBase, \ |
XAXIDMA_CDESC_OFFSET); \ |
} else { \ |
(RingPtr)->BdaRestart = \ |
XAxiDma_ReadReg( \ |
(RingPtr)->ChanBase, \ |
(XAXIDMA_RX_CDESC0_OFFSET + \ |
(RingPtr->RingIndex - 1) * \ |
XAXIDMA_RX_NDESC_OFFSET)); \ |
} \ |
} \ |
} |
|
/****************************************************************************/ |
/** |
* Get the BD a BD ring is processing. |
* |
* @param RingPtr is the BD ring to operate on. |
* |
* @return The current BD that the BD ring is working on |
* |
* @note |
* C-style signature: |
* XAxiDma_Bd * XAxiDma_BdRingGetCurrBd(XAxiDma_BdRing* RingPtr) |
* This function is used only when system is configured as SG mode |
* |
*****************************************************************************/ |
#define XAxiDma_BdRingGetCurrBd(RingPtr) \ |
(XAxiDma_Bd *)XAxiDma_ReadReg((RingPtr)->ChanBase, \ |
XAXIDMA_CDESC_OFFSET) \ |
|
/****************************************************************************/ |
/** |
* Return the next BD in the ring. |
* |
* @param RingPtr is the BD ring to operate on. |
* @param BdPtr is the current BD. |
* |
* @return The next BD in the ring relative to the BdPtr parameter. |
* |
* @note |
* C-style signature: |
* XAxiDma_Bd *XAxiDma_BdRingNext(XAxiDma_BdRing* RingPtr, |
* XAxiDma_Bd *BdPtr) |
* This function is used only when system is configured as SG mode |
* |
*****************************************************************************/ |
#define XAxiDma_BdRingNext(RingPtr, BdPtr) \ |
(((UINTPTR)(BdPtr) >= (RingPtr)->LastBdAddr) ? \ |
(UINTPTR)(RingPtr)->FirstBdAddr : \ |
(UINTPTR)((UINTPTR)(BdPtr) + (RingPtr)->Separation)) |
|
/****************************************************************************/ |
/** |
* Return the previous BD in the ring. |
* |
* @param RingPtr is the DMA channel to operate on. |
* @param BdPtr is the current BD. |
* |
* @return The previous BD in the ring relative to the BdPtr parameter. |
* |
* @note |
* C-style signature: |
* XAxiDma_Bd *XAxiDma_BdRingPrev(XAxiDma_BdRing* RingPtr, |
* XAxiDma_Bd *BdPtr) |
* This function is used only when system is configured as SG mode |
* |
*****************************************************************************/ |
#define XAxiDma_BdRingPrev(RingPtr, BdPtr) \ |
(((u32)(BdPtr) <= (RingPtr)->FirstBdAddr) ? \ |
(XAxiDma_Bd*)(RingPtr)->LastBdAddr : \ |
(XAxiDma_Bd*)((u32)(BdPtr) - (RingPtr)->Separation)) |
|
/****************************************************************************/ |
/** |
* Retrieve the contents of the channel status register |
* |
* @param RingPtr is the channel instance to operate on. |
* |
* @return Current contents of status register |
* |
* @note |
* C-style signature: |
* u32 XAxiDma_BdRingGetSr(XAxiDma_BdRing* RingPtr) |
* This function is used only when system is configured as SG mode |
* |
*****************************************************************************/ |
#define XAxiDma_BdRingGetSr(RingPtr) \ |
XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_SR_OFFSET) |
|
/****************************************************************************/ |
/** |
* Get error bits of a DMA channel |
* |
* @param RingPtr is the channel instance to operate on. |
* |
* @return Rrror bits in the status register, they should be interpreted |
* with XAXIDMA_ERR_*_MASK defined in xaxidma_hw.h |
* |
* @note |
* C-style signature: |
* u32 XAxiDma_BdRingGetError(XAxiDma_BdRing* RingPtr) |
* This function is used only when system is configured as SG mode |
* |
*****************************************************************************/ |
#define XAxiDma_BdRingGetError(RingPtr) \ |
(XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_SR_OFFSET) \ |
& XAXIDMA_ERR_ALL_MASK) |
|
/****************************************************************************/ |
/** |
* Check whether a DMA channel is started, meaning the channel is not halted. |
* |
* @param RingPtr is the channel instance to operate on. |
* |
* @return |
* - 1 if channel is started |
* - 0 otherwise |
* |
* @note |
* C-style signature: |
* int XAxiDma_BdRingHwIsStarted(XAxiDma_BdRing* RingPtr) |
* |
*****************************************************************************/ |
#define XAxiDma_BdRingHwIsStarted(RingPtr) \ |
((XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_SR_OFFSET) \ |
& XAXIDMA_HALTED_MASK) ? FALSE : TRUE) |
|
/****************************************************************************/ |
/** |
* Check if the current DMA channel is busy with a DMA operation. |
* |
* @param RingPtr is the channel instance to operate on. |
* |
* @return |
* - 1 if the DMA is busy. |
* - 0 otherwise |
* |
* @note |
* C-style signature: |
* int XAxiDma_BdRingBusy(XAxiDma_BdRing* RingPtr) |
* This function is used only when system is configured as SG mode |
* |
*****************************************************************************/ |
#define XAxiDma_BdRingBusy(RingPtr) \ |
(XAxiDma_BdRingHwIsStarted(RingPtr) && \ |
((XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_SR_OFFSET) \ |
& XAXIDMA_IDLE_MASK) ? FALSE : TRUE)) |
|
/****************************************************************************/ |
/** |
* Set interrupt enable bits for a channel. This operation will modify the |
* XAXIDMA_CR_OFFSET register. |
* |
* @param RingPtr is the channel instance to operate on. |
* @param Mask consists of the interrupt signals to enable.Bits not |
* specified in the mask are not affected. |
* |
* @note |
* C-style signature: |
* void XAxiDma_BdRingIntEnable(XAxiDma_BdRing* RingPtr, u32 Mask) |
* This function is used only when system is configured as SG mode |
* |
*****************************************************************************/ |
#define XAxiDma_BdRingIntEnable(RingPtr, Mask) \ |
(XAxiDma_WriteReg((RingPtr)->ChanBase, XAXIDMA_CR_OFFSET, \ |
XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_CR_OFFSET) \ |
| ((Mask) & XAXIDMA_IRQ_ALL_MASK))) |
|
/****************************************************************************/ |
/** |
* Get enabled interrupts of a channel. It is in XAXIDMA_CR_OFFSET register. |
* |
* @param RingPtr is the channel instance to operate on. |
* @return Enabled interrupts of a channel. Use XAXIDMA_IRQ_* defined in |
* xaxidma_hw.h to interpret this returned value. |
* |
* @note |
* C-style signature: |
* u32 XAxiDma_BdRingIntGetEnabled(XAxiDma_BdRing* RingPtr) |
* This function is used only when system is configured as SG mode |
* |
*****************************************************************************/ |
#define XAxiDma_BdRingIntGetEnabled(RingPtr) \ |
(XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_CR_OFFSET) \ |
& XAXIDMA_IRQ_ALL_MASK) |
|
/****************************************************************************/ |
/** |
* Clear interrupt enable bits for a channel. It modifies the |
* XAXIDMA_CR_OFFSET register. |
* |
* @param RingPtr is the channel instance to operate on. |
* @param Mask consists of the interrupt signals to disable.Bits not |
* specified in the Mask are not affected. |
* |
* @note |
* C-style signature: |
* void XAxiDma_BdRingIntDisable(XAxiDma_BdRing* RingPtr, |
* u32 Mask) |
* This function is used only when system is configured as SG mode |
* |
*****************************************************************************/ |
#define XAxiDma_BdRingIntDisable(RingPtr, Mask) \ |
(XAxiDma_WriteReg((RingPtr)->ChanBase, XAXIDMA_CR_OFFSET, \ |
XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_CR_OFFSET) & \ |
~((Mask) & XAXIDMA_IRQ_ALL_MASK))) |
|
/****************************************************************************/ |
/** |
* Retrieve the contents of the channel's IRQ register XAXIDMA_SR_OFFSET. This |
* operation can be used to see which interrupts are pending. |
* |
* @param RingPtr is the channel instance to operate on. |
* |
* @return Current contents of the IRQ_OFFSET register. Use |
* XAXIDMA_IRQ_*** values defined in xaxidma_hw.h to interpret |
* the returned value. |
* |
* @note |
* C-style signature: |
* u32 XAxiDma_BdRingGetIrq(XAxiDma_BdRing* RingPtr) |
* This function is used only when system is configured as SG mode |
* |
*****************************************************************************/ |
#define XAxiDma_BdRingGetIrq(RingPtr) \ |
(XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_SR_OFFSET) \ |
& XAXIDMA_IRQ_ALL_MASK) |
|
/****************************************************************************/ |
/** |
* Acknowledge asserted interrupts. It modifies XAXIDMA_SR_OFFSET register. |
* A mask bit set for an unasserted interrupt has no effect. |
* |
* @param RingPtr is the channel instance to operate on. |
* @param Mask are the interrupt signals to acknowledge |
* |
* @note |
* C-style signature: |
* void XAxiDma_BdRingAckIrq(XAxiDma_BdRing* RingPtr) |
* This function is used only when system is configured as SG mode |
* |
*****************************************************************************/ |
#define XAxiDma_BdRingAckIrq(RingPtr, Mask) \ |
XAxiDma_WriteReg((RingPtr)->ChanBase, XAXIDMA_SR_OFFSET,\ |
(Mask) & XAXIDMA_IRQ_ALL_MASK) |
|
/************************* Function Prototypes ******************************/ |
|
/* |
* Descriptor ring functions xaxidma_bdring.c |
*/ |
int XAxiDma_StartBdRingHw(XAxiDma_BdRing* RingPtr); |
int XAxiDma_UpdateBdRingCDesc(XAxiDma_BdRing* RingPtr); |
u32 XAxiDma_BdRingCreate(XAxiDma_BdRing * RingPtr, UINTPTR PhysAddr, |
UINTPTR VirtAddr, u32 Alignment, int BdCount); |
int XAxiDma_BdRingClone(XAxiDma_BdRing * RingPtr, XAxiDma_Bd * SrcBdPtr); |
int XAxiDma_BdRingAlloc(XAxiDma_BdRing * RingPtr, int NumBd, |
XAxiDma_Bd ** BdSetPtr); |
int XAxiDma_BdRingUnAlloc(XAxiDma_BdRing * RingPtr, int NumBd, |
XAxiDma_Bd * BdSetPtr); |
int XAxiDma_BdRingToHw(XAxiDma_BdRing * RingPtr, int NumBd, |
XAxiDma_Bd * BdSetPtr); |
int XAxiDma_BdRingFromHw(XAxiDma_BdRing * RingPtr, int BdLimit, |
XAxiDma_Bd ** BdSetPtr); |
int XAxiDma_BdRingFree(XAxiDma_BdRing * RingPtr, int NumBd, |
XAxiDma_Bd * BdSetPtr); |
int XAxiDma_BdRingStart(XAxiDma_BdRing * RingPtr); |
int XAxiDma_BdRingSetCoalesce(XAxiDma_BdRing * RingPtr, u32 Counter, u32 Timer); |
void XAxiDma_BdRingGetCoalesce(XAxiDma_BdRing * RingPtr, |
u32 *CounterPtr, u32 *TimerPtr); |
|
/* The following functions are for debug only |
*/ |
int XAxiDma_BdRingCheck(XAxiDma_BdRing * RingPtr); |
void XAxiDma_BdRingDumpRegs(XAxiDma_BdRing *RingPtr); |
#ifdef __cplusplus |
} |
#endif |
|
#endif /* end of protection macro */ |
/** @} */ |
/trunk/sw/dev/test_main/src/_hdl/bsp/libsrc/axidma_v9_0/src/xaxidma_g.c
0,0 → 1,69
|
/******************************************************************* |
* |
* CAUTION: This file is automatically generated by HSI. |
* Version: |
* DO NOT EDIT. |
* |
* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.* |
*Permission is hereby granted, free of charge, to any person obtaining a copy |
*of this software and associated documentation files (the Software), to deal |
*in the Software without restriction, including without limitation the rights |
*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
*copies of the Software, and to permit persons to whom the Software is |
*furnished to do so, subject to the following conditions: |
* |
*The above copyright notice and this permission notice shall be included in |
*all copies or substantial portions of the Software. |
* |
* Use of the Software is limited solely to applications: |
*(a) running on a Xilinx device, or |
*(b) that interact with a Xilinx device through a bus or interconnect. |
* |
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT |
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
* |
*Except as contained in this notice, the name of the Xilinx shall not be used |
*in advertising or otherwise to promote the sale, use or other dealings in |
*this Software without prior written authorization from Xilinx. |
* |
|
* |
* Description: Driver configuration |
* |
*******************************************************************/ |
|
#include "xparameters.h" |
#include "xaxidma.h" |
|
/* |
* The configuration table for devices |
*/ |
|
XAxiDma_Config XAxiDma_ConfigTable[] = |
{ |
{ |
XPAR_AXI_DMA_0_DEVICE_ID, |
XPAR_AXI_DMA_0_BASEADDR, |
XPAR_AXI_DMA_0_SG_INCLUDE_STSCNTRL_STRM, |
XPAR_AXI_DMA_0_INCLUDE_MM2S, |
XPAR_AXI_DMA_0_INCLUDE_MM2S_DRE, |
XPAR_AXI_DMA_0_M_AXI_MM2S_DATA_WIDTH, |
XPAR_AXI_DMA_0_INCLUDE_S2MM, |
XPAR_AXI_DMA_0_INCLUDE_S2MM_DRE, |
XPAR_AXI_DMA_0_M_AXI_S2MM_DATA_WIDTH, |
XPAR_AXI_DMA_0_INCLUDE_SG, |
XPAR_AXI_DMA_0_NUM_MM2S_CHANNELS, |
XPAR_AXI_DMA_0_NUM_S2MM_CHANNELS, |
XPAR_AXI_DMA_0_MM2S_BURST_SIZE, |
XPAR_AXI_DMA_0_S2MM_BURST_SIZE, |
XPAR_AXI_DMA_0_MICRO_DMA, |
XPAR_AXI_DMA_0_ADDR_WIDTH |
} |
}; |
|
|
/trunk/sw/dev/test_main/src/_hdl/bsp/libsrc/axidma_v9_0/src/xaxidma_hw.h
0,0 → 1,344
/****************************************************************************** |
* |
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. |
* |
* Permission is hereby granted, free of charge, to any person obtaining a copy |
* of this software and associated documentation files (the "Software"), to deal |
* in the Software without restriction, including without limitation the rights |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
* copies of the Software, and to permit persons to whom the Software is |
* furnished to do so, subject to the following conditions: |
* |
* The above copyright notice and this permission notice shall be included in |
* all copies or substantial portions of the Software. |
* |
* Use of the Software is limited solely to applications: |
* (a) running on a Xilinx device, or |
* (b) that interact with a Xilinx device through a bus or interconnect. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF |
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
* SOFTWARE. |
* |
* Except as contained in this notice, the name of the Xilinx shall not be used |
* in advertising or otherwise to promote the sale, use or other dealings in |
* this Software without prior written authorization from Xilinx. |
* |
******************************************************************************/ |
/*****************************************************************************/ |
/** |
* @file xaxidma_hw.h |
* @addtogroup axidma_v9_0 |
* @{ |
* |
* Hardware definition file. It defines the register interface and Buffer |
* Descriptor (BD) definitions. |
* |
* <pre> |
* MODIFICATION HISTORY: |
* |
* Ver Who Date Changes |
* ----- ---- -------- ------------------------------------------------------- |
* 1.00a jz 05/18/10 First release |
* 2.00a jz 08/10/10 Second release, added in xaxidma_g.c, xaxidma_sinit.c, |
* updated tcl file, added xaxidma_porting_guide.h |
* 3.00a jz 11/22/10 Support IP core parameters change |
* 4.00a rkv 02/22/11 Added support for simple DMA mode |
* 6.00a srt 01/24/12 Added support for Multi-Channel DMA mode |
* 8.0 srt 01/29/14 Added support for Micro DMA Mode and Cyclic mode of |
* operations. |
* |
* </pre> |
* |
*****************************************************************************/ |
|
#ifndef XAXIDMA_HW_H_ /* prevent circular inclusions */ |
#define XAXIDMA_HW_H_ |
|
#ifdef __cplusplus |
extern "C" { |
#endif |
|
#include "xil_types.h" |
#include "xil_io.h" |
|
/************************** Constant Definitions *****************************/ |
|
/** @name DMA Transfer Direction |
* @{ |
*/ |
#define XAXIDMA_DMA_TO_DEVICE 0x00 |
#define XAXIDMA_DEVICE_TO_DMA 0x01 |
|
|
/** @name Buffer Descriptor Alignment |
* @{ |
*/ |
#define XAXIDMA_BD_MINIMUM_ALIGNMENT 0x40 /**< Minimum byte alignment |
requirement for descriptors to |
satisfy both hardware/software |
needs */ |
/*@}*/ |
|
/** @name Micro DMA Buffer Address Alignment |
* @{ |
*/ |
#define XAXIDMA_MICROMODE_MIN_BUF_ALIGN 0xFFF /**< Minimum byte alignment |
requirement for buffer address |
in Micro DMA mode */ |
/*@}*/ |
|
/** @name Maximum transfer length |
* This is determined by hardware |
* @{ |
*/ |
#define XAXIDMA_MAX_TRANSFER_LEN 0x7FFFFF /* Max length hw supports */ |
#define XAXIDMA_MCHAN_MAX_TRANSFER_LEN 0x00FFFF /* Max length MCDMA |
hw supports */ |
/*@}*/ |
|
/* Register offset definitions. Register accesses are 32-bit. |
*/ |
/** @name Device registers |
* Register sets on TX and RX channels are identical |
* @{ |
*/ |
#define XAXIDMA_TX_OFFSET 0x00000000 /**< TX channel registers base |
* offset */ |
#define XAXIDMA_RX_OFFSET 0x00000030 /**< RX channel registers base |
* offset */ |
|
/* This set of registers are applicable for both channels. Add |
* XAXIDMA_TX_OFFSET to get to TX channel, and XAXIDMA_RX_OFFSET to get to RX |
* channel |
*/ |
#define XAXIDMA_CR_OFFSET 0x00000000 /**< Channel control */ |
#define XAXIDMA_SR_OFFSET 0x00000004 /**< Status */ |
#define XAXIDMA_CDESC_OFFSET 0x00000008 /**< Current descriptor pointer */ |
#define XAXIDMA_CDESC_MSB_OFFSET 0x0000000C /**< Current descriptor pointer */ |
#define XAXIDMA_TDESC_OFFSET 0x00000010 /**< Tail descriptor pointer */ |
#define XAXIDMA_TDESC_MSB_OFFSET 0x00000014 /**< Tail descriptor pointer */ |
#define XAXIDMA_SRCADDR_OFFSET 0x00000018 /**< Simple mode source address |
pointer */ |
#define XAXIDMA_SRCADDR_MSB_OFFSET 0x0000001C /**< Simple mode source address |
pointer */ |
#define XAXIDMA_DESTADDR_OFFSET 0x00000018 /**< Simple mode destination address pointer */ |
#define XAXIDMA_DESTADDR_MSB_OFFSET 0x0000001C /**< Simple mode destination address pointer */ |
#define XAXIDMA_BUFFLEN_OFFSET 0x00000028 /**< Tail descriptor pointer */ |
#define XAXIDMA_SGCTL_OFFSET 0x0000002c /**< SG Control Register */ |
|
/** Multi-Channel DMA Descriptor Offsets **/ |
#define XAXIDMA_RX_CDESC0_OFFSET 0x00000040 /**< Rx Current Descriptor 0 */ |
#define XAXIDMA_RX_CDESC0_MSB_OFFSET 0x00000044 /**< Rx Current Descriptor 0 */ |
#define XAXIDMA_RX_TDESC0_OFFSET 0x00000048 /**< Rx Tail Descriptor 0 */ |
#define XAXIDMA_RX_TDESC0_MSB_OFFSET 0x0000004C /**< Rx Tail Descriptor 0 */ |
#define XAXIDMA_RX_NDESC_OFFSET 0x00000020 /**< Rx Next Descriptor Offset */ |
/*@}*/ |
|
/** @name Bitmasks of XAXIDMA_CR_OFFSET register |
* @{ |
*/ |
#define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /**< Start/stop DMA channel */ |
#define XAXIDMA_CR_RESET_MASK 0x00000004 /**< Reset DMA engine */ |
#define XAXIDMA_CR_KEYHOLE_MASK 0x00000008 /**< Keyhole feature */ |
#define XAXIDMA_CR_CYCLIC_MASK 0x00000010 /**< Cyclic Mode */ |
/*@}*/ |
|
/** @name Bitmasks of XAXIDMA_SR_OFFSET register |
* |
* This register reports status of a DMA channel, including |
* run/stop/idle state, errors, and interrupts (note that interrupt |
* masks are shared with XAXIDMA_CR_OFFSET register, and are defined |
* in the _IRQ_ section. |
* |
* The interrupt coalescing threshold value and delay counter value are |
* also shared with XAXIDMA_CR_OFFSET register, and are defined in a |
* later section. |
* @{ |
*/ |
#define XAXIDMA_HALTED_MASK 0x00000001 /**< DMA channel halted */ |
#define XAXIDMA_IDLE_MASK 0x00000002 /**< DMA channel idle */ |
#define XAXIDMA_ERR_INTERNAL_MASK 0x00000010 /**< Datamover internal |
* err */ |
#define XAXIDMA_ERR_SLAVE_MASK 0x00000020 /**< Datamover slave err */ |
#define XAXIDMA_ERR_DECODE_MASK 0x00000040 /**< Datamover decode |
* err */ |
#define XAXIDMA_ERR_SG_INT_MASK 0x00000100 /**< SG internal err */ |
#define XAXIDMA_ERR_SG_SLV_MASK 0x00000200 /**< SG slave err */ |
#define XAXIDMA_ERR_SG_DEC_MASK 0x00000400 /**< SG decode err */ |
#define XAXIDMA_ERR_ALL_MASK 0x00000770 /**< All errors */ |
|
/** @name Bitmask for interrupts |
* These masks are shared by XAXIDMA_CR_OFFSET register and |
* XAXIDMA_SR_OFFSET register |
* @{ |
*/ |
#define XAXIDMA_IRQ_IOC_MASK 0x00001000 /**< Completion intr */ |
#define XAXIDMA_IRQ_DELAY_MASK 0x00002000 /**< Delay interrupt */ |
#define XAXIDMA_IRQ_ERROR_MASK 0x00004000 /**< Error interrupt */ |
#define XAXIDMA_IRQ_ALL_MASK 0x00007000 /**< All interrupts */ |
/*@}*/ |
|
/** @name Bitmask and shift for delay and coalesce |
* These masks are shared by XAXIDMA_CR_OFFSET register and |
* XAXIDMA_SR_OFFSET register |
* @{ |
*/ |
#define XAXIDMA_DELAY_MASK 0xFF000000 /**< Delay timeout |
* counter */ |
#define XAXIDMA_COALESCE_MASK 0x00FF0000 /**< Coalesce counter */ |
|
#define XAXIDMA_DELAY_SHIFT 24 |
#define XAXIDMA_COALESCE_SHIFT 16 |
/*@}*/ |
|
|
/* Buffer Descriptor (BD) definitions |
*/ |
|
/** @name Buffer Descriptor offsets |
* USR* fields are defined by higher level IP. |
* setup for EMAC type devices. The first 13 words are used by hardware. |
* All words after the 13rd word are for software use only. |
* @{ |
*/ |
#define XAXIDMA_BD_NDESC_OFFSET 0x00 /**< Next descriptor pointer */ |
#define XAXIDMA_BD_NDESC_MSB_OFFSET 0x04 /**< Next descriptor pointer */ |
#define XAXIDMA_BD_BUFA_OFFSET 0x08 /**< Buffer address */ |
#define XAXIDMA_BD_BUFA_MSB_OFFSET 0x0C /**< Buffer address */ |
#define XAXIDMA_BD_MCCTL_OFFSET 0x10 /**< Multichannel Control Fields */ |
#define XAXIDMA_BD_STRIDE_VSIZE_OFFSET 0x14 /**< 2D Transfer Sizes */ |
#define XAXIDMA_BD_CTRL_LEN_OFFSET 0x18 /**< Control/buffer length */ |
#define XAXIDMA_BD_STS_OFFSET 0x1C /**< Status */ |
|
#define XAXIDMA_BD_USR0_OFFSET 0x20 /**< User IP specific word0 */ |
#define XAXIDMA_BD_USR1_OFFSET 0x24 /**< User IP specific word1 */ |
#define XAXIDMA_BD_USR2_OFFSET 0x28 /**< User IP specific word2 */ |
#define XAXIDMA_BD_USR3_OFFSET 0x2C /**< User IP specific word3 */ |
#define XAXIDMA_BD_USR4_OFFSET 0x30 /**< User IP specific word4 */ |
|
#define XAXIDMA_BD_ID_OFFSET 0x34 /**< Sw ID */ |
#define XAXIDMA_BD_HAS_STSCNTRL_OFFSET 0x38 /**< Whether has stscntrl strm */ |
#define XAXIDMA_BD_HAS_DRE_OFFSET 0x3C /**< Whether has DRE */ |
#define XAXIDMA_BD_ADDRLEN_OFFSET 0x40 /**< Check for BD Addr */ |
|
#define XAXIDMA_BD_HAS_DRE_MASK 0xF00 /**< Whether has DRE mask */ |
#define XAXIDMA_BD_WORDLEN_MASK 0xFF /**< Whether has DRE mask */ |
|
#define XAXIDMA_BD_HAS_DRE_SHIFT 8 /**< Whether has DRE shift */ |
#define XAXIDMA_BD_WORDLEN_SHIFT 0 /**< Whether has DRE shift */ |
|
#define XAXIDMA_BD_START_CLEAR 8 /**< Offset to start clear */ |
#define XAXIDMA_BD_BYTES_TO_CLEAR 48 /**< BD specific bytes to be |
* cleared */ |
|
#define XAXIDMA_BD_NUM_WORDS 20U /**< Total number of words for |
* one BD*/ |
#define XAXIDMA_BD_HW_NUM_BYTES 52 /**< Number of bytes hw used */ |
|
/* The offset of the last app word. |
*/ |
#define XAXIDMA_LAST_APPWORD 4 |
|
/*@}*/ |
#define XAXIDMA_DESC_LSB_MASK (0xFFFFFFC0U) /**< LSB Address mask */ |
|
/** @name Bitmasks of XAXIDMA_BD_CTRL_OFFSET register |
* @{ |
*/ |
#define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /**< First tx packet */ |
#define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /**< Last tx packet */ |
#define XAXIDMA_BD_CTRL_ALL_MASK 0x0C000000 /**< All control bits */ |
/*@}*/ |
|
/** @name Bitmasks of XAXIDMA_BD_STS_OFFSET register |
* @{ |
*/ |
#define XAXIDMA_BD_STS_COMPLETE_MASK 0x80000000 /**< Completed */ |
#define XAXIDMA_BD_STS_DEC_ERR_MASK 0x40000000 /**< Decode error */ |
#define XAXIDMA_BD_STS_SLV_ERR_MASK 0x20000000 /**< Slave error */ |
#define XAXIDMA_BD_STS_INT_ERR_MASK 0x10000000 /**< Internal err */ |
#define XAXIDMA_BD_STS_ALL_ERR_MASK 0x70000000 /**< All errors */ |
#define XAXIDMA_BD_STS_RXSOF_MASK 0x08000000 /**< First rx pkt */ |
#define XAXIDMA_BD_STS_RXEOF_MASK 0x04000000 /**< Last rx pkt */ |
#define XAXIDMA_BD_STS_ALL_MASK 0xFC000000 /**< All status bits */ |
/*@}*/ |
|
/** @name Bitmasks and shift values for XAXIDMA_BD_MCCTL_OFFSET register |
* @{ |
*/ |
#define XAXIDMA_BD_TDEST_FIELD_MASK 0x0000000F |
#define XAXIDMA_BD_TID_FIELD_MASK 0x00000F00 |
#define XAXIDMA_BD_TUSER_FIELD_MASK 0x000F0000 |
#define XAXIDMA_BD_ARCACHE_FIELD_MASK 0x0F000000 |
#define XAXIDMA_BD_ARUSER_FIELD_MASK 0xF0000000 |
|
#define XAXIDMA_BD_TDEST_FIELD_SHIFT 0 |
#define XAXIDMA_BD_TID_FIELD_SHIFT 8 |
#define XAXIDMA_BD_TUSER_FIELD_SHIFT 16 |
#define XAXIDMA_BD_ARCACHE_FIELD_SHIFT 24 |
#define XAXIDMA_BD_ARUSER_FIELD_SHIFT 28 |
|
/** @name Bitmasks and shift values for XAXIDMA_BD_STRIDE_VSIZE_OFFSET register |
* @{ |
*/ |
#define XAXIDMA_BD_STRIDE_FIELD_MASK 0x0000FFFF |
#define XAXIDMA_BD_VSIZE_FIELD_MASK 0xFFF80000 |
|
#define XAXIDMA_BD_STRIDE_FIELD_SHIFT 0 |
#define XAXIDMA_BD_VSIZE_FIELD_SHIFT 19 |
|
/**************************** Type Definitions *******************************/ |
|
/***************** Macros (Inline Functions) Definitions *********************/ |
|
#define XAxiDma_In32 Xil_In32 |
#define XAxiDma_Out32 Xil_Out32 |
|
/*****************************************************************************/ |
/** |
* |
* Read the given register. |
* |
* @param BaseAddress is the base address of the device |
* @param RegOffset is the register offset to be read |
* |
* @return The 32-bit value of the register |
* |
* @note |
* C-style signature: |
* u32 XAxiDma_ReadReg(u32 BaseAddress, u32 RegOffset) |
* |
******************************************************************************/ |
#define XAxiDma_ReadReg(BaseAddress, RegOffset) \ |
XAxiDma_In32((BaseAddress) + (RegOffset)) |
|
/*****************************************************************************/ |
/** |
* |
* Write the given register. |
* |
* @param BaseAddress is the base address of the device |
* @param RegOffset is the register offset to be written |
* @param Data is the 32-bit value to write to the register |
* |
* @return None. |
* |
* @note |
* C-style signature: |
* void XAxiDma_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) |
* |
******************************************************************************/ |
#define XAxiDma_WriteReg(BaseAddress, RegOffset, Data) \ |
XAxiDma_Out32((BaseAddress) + (RegOffset), (Data)) |
|
#ifdef __cplusplus |
} |
#endif |
|
#endif |
/** @} */ |
/trunk/sw/dev/test_main/src/_hdl/bsp/libsrc/axidma_v9_0/src/xaxidma_porting_guide.h
0,0 → 1,254
/****************************************************************************** |
* |
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. |
* |
* Permission is hereby granted, free of charge, to any person obtaining a copy |
* of this software and associated documentation files (the "Software"), to deal |
* in the Software without restriction, including without limitation the rights |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
* copies of the Software, and to permit persons to whom the Software is |
* furnished to do so, subject to the following conditions: |
* |
* The above copyright notice and this permission notice shall be included in |
* all copies or substantial portions of the Software. |
* |
* Use of the Software is limited solely to applications: |
* (a) running on a Xilinx device, or |
* (b) that interact with a Xilinx device through a bus or interconnect. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF |
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
* SOFTWARE. |
* |
* Except as contained in this notice, the name of the Xilinx shall not be used |
* in advertising or otherwise to promote the sale, use or other dealings in |
* this Software without prior written authorization from Xilinx. |
* |
******************************************************************************/ |
/*****************************************************************************/ |
/** |
* |
* @file xaxidma_porting_guide.h |
* @addtogroup axidma_v9_0 |
* @{ |
* |
* This is a guide on how to move from using the xlldma driver to use xaxidma |
* driver. |
* |
* <pre> |
* MODIFICATION HISTORY: |
* |
* Ver Who Date Changes |
* ----- ---- -------- ------------------------------------------------------- |
* 1.00a jz 05/18/10 First release |
* 2.00a jz 08/10/10 Second release, added in xaxidma_g.c, xaxidma_sinit.c, |
* updated tcl file, added xaxidma_porting_guide.h |
* 4.00a rkv 02/22/11 Added support for simple DMA mode |
* 6.00a srt 03/27/12 Added support for MCDMA mode |
* 7.00a srt 06/18/12 API calls are reverted back for backward compatibility. |
* |
* </pre> |
* |
* <b>Overview</b> |
* |
* The API for xaxidma driver is similar to xlldma driver. The prefix for the |
* API functions and structures is XAxiDma_ for the xaxidma driver. |
* |
* Due to hardware feature changes, signatures of some API functions are a |
* little bit different from the xlldma API functions. |
* |
* We present API functions: |
* - That only have prefix changes |
* - That have different return type |
* - That are new API functions |
* - That have been removed |
* |
* Note that data structures have different prefix of XAxiDma_. Those API |
* functions, that have data structures with prefix change, are considered as |
* prefix change. |
* |
* <b>API Functions That Only Have Prefix Changes</b> |
* |
* <pre> |
* xlldma driver | xaxidma driver (upto v5_00_a) |
* ----------------------------------------------------------------------- |
* XLlDma_Reset(...) | XAxiDma_Reset(...) |
* XLlDma_BdRingSnapShotCurrBd(...)| XAxiDma_BdRingSnapShotCurrBd(...) |
* XLlDma_BdRingNext(...) | XAxiDma_BdRingNext(...) |
* XLlDma_BdRingPrev(...) | XAxiDma_BdRingPrev(...) |
* XLlDma_BdRingGetSr(...) | XAxiDma_BdRingGetSr(...) |
* XLlDma_BdRingBusy(...) | XAxiDma_BdRingBusy(...) |
* XLlDma_BdRingIntEnable(...) | XAxiDma_BdRingIntEnable(...) |
* XLlDma_BdRingIntDisable(...) | XAxiDma_BdRingIntDisable(...) |
* XLlDma_BdRingIntGetEnabled(...) | XAxiDma_BdRingIntGetEnabled(...) |
* XLlDma_BdRingGetIrq(...) | XAxiDma_BdRingGetIrq(...) |
* XLlDma_BdRingAckIrq(...) | XAxiDma_BdRingAckIrq(...) |
* XLlDma_BdRingCreate(...) | XAxiDma_BdRingCreate(...) |
* XLlDma_BdRingClone(...) | XAxiDma_BdRingClone(...) |
* XLlDma_BdRingAlloc(...) | XAxiDma_BdRingAlloc(...) |
* XLlDma_BdRingUnAlloc(...) | XAxiDma_BdRingUnAlloc(...) |
* XLlDma_BdRingToHw(...) | XAxiDma_BdRingToHw(...) |
* XLlDma_BdRingFromHw(...) | XAxiDma_BdRingFromHw(...) |
* XLlDma_BdRingFree(...) | XAxiDma_BdRingFree(...) |
* XLlDma_BdRingStart(...) | XAxiDma_BdRingStart(...) |
* XLlDma_BdRingCheck(...) | XAxiDma_BdRingCheck(...) |
* XLlDma_BdRingSetCoalesce(...) | XAxiDma_BdRingSetCoalesce(...) |
* XLlDma_BdRingGetCoalesce(...) | XAxiDma_BdRingGetCoalesce(...) |
* XLlDma_BdRead(...) | XAxiDma_BdRead(...) |
* XLlDma_BdWrite(...) | XAxiDma_BdWrite(...) |
* XLlDma_BdClear(...) | XAxiDma_BdClear(...) |
* XLlDma_BdSetId(...) | XAxiDma_BdSetId(...) |
* XLlDma_BdGetId(...) | XAxiDma_BdGetId(...) |
* XLlDma_BdGetLength(...) | XAxiDma_BdGetLength(...) |
* XLlDma_BdGetBufAddr(...) | XAxiDma_BdGetBufAddr(...) |
* |
*</pre> |
* |
* <b>API Functions That Have Different Return Type</b> |
* |
* Due to possible hardware failures, The caller should check the return value |
* of the following functions. |
* |
* <pre> |
* xlldma driver | xaxidma driver |
* ----------------------------------------------------------------------- |
* void XLlDma_Pause(...) | int XAxiDma_Pause(...) |
* void XLlDma_Resume(...) | int XAxiDma_Resume(...) |
* </pre> |
* |
* The following functions have return type changed: |
* |
* <pre> |
* xlldma driver | xaxidma driver |
* ----------------------------------------------------------------------- |
* XLlDma_BdRing XLlDma_GetRxRing(...)| XAxiDma_BdRing * XAxiDma_GetRxRing(...) |
* XLlDma_BdRing XLlDma_GetTxRing(...)| XAxiDma_BdRing * XAxiDma_GetTxRing(...) |
* u32 XLlDma_BdRingMemCalc(...) | int XAxiDma_BdRingMemCalc(...) |
* u32 XLlDma_BdRingCntCalc(...) | int XAxiDma_BdRingCntCalc(...) |
* u32 XLlDma_BdRingGetCnt(...) | int XAxiDma_BdRingGetCnt(...) |
* u32 XLlDma_BdRingGetFreeCnt(...) | int XAxiDma_BdRingGetFreeCnt(...) |
* void XLlDma_BdSetLength(...) | int XAxiDma_BdSetLength(...) |
* void XLlDma_BdSetBufAddr(...) | int XAxiDma_BdSetBufAddr(...) |
*</pre> |
* |
* <b>API Functions That Are New API Functions</b> |
* |
* Now that the AXI DMA core is a standalone core, some new API are intrduced. |
* Some other functions are added due to hardware interface change, so to |
* replace old API functions. |
* |
* - XAxiDma_Config *XAxiDma_LookupConfig(u32 DeviceId); |
* - int XAxiDma_CfgInitialize(XAxiDma * InstancePtr, XAxiDma_Config *Config); |
* - int XAxiDma_ResetIsDone(XAxiDma * InstancePtr); |
* - XAxiDma_Bd * XAxiDma_BdRingGetCurrBd(XAxiDma_BdRing* RingPtr); |
* - int XAxiDma_BdRingHwIsStarted(XAxiDma_BdRing* RingPtr); |
* - void XAxiDma_BdRingDumpRegs(XAxiDma_BdRing *RingPtr); |
* - int XAxiDma_StartBdRingHw(XAxiDma_BdRing* RingPtr); |
* - void XAxiDma_BdSetCtrl(XAxiDma_Bd *BdPtr, u32 Data); |
* - u32 XAxiDma_BdGetCtrl(XAxiDma_Bd* BdPtr); |
* - u32 XAxiDma_BdGetSts(XAxiDma_Bd* BdPtr); |
* - int XAxiDma_BdHwCompleted(XAxiDma_Bd* BdPtr); |
* - int XAxiDma_BdGetActualLength(XAxiDma_Bd* BdPtr); |
* - int XAxiDma_BdSetAppWord(XAxiDma_Bd * BdPtr, int Offset, u32 Word); |
* - u32 XAxiDma_BdGetAppWord(XAxiDma_Bd * BdPtr, int Offset, int *Valid); |
* |
* <b>API Functions That Have Been Removed</b> |
* |
* Please see individual function comments for how to replace the removed API |
* function with new API functions. |
* |
* - void XLlDma_Initialize(XLlDma * InstancePtr, u32 BaseAddress). |
* This function is replaced by XAxiDma_LookupConfig()/XAxiDma_CfgInitialize() |
* |
* - u32 XLlDma_BdRingGetCr(XLlDma_BdRing* RingPtr). |
* This is replaced by XAxiDma_BdRingGetError(XAxiDma_BdRing* RingPtr) |
* |
* - u32 XLlDma_BdRingSetCr(XLlDma_BdRing* RingPtr, u32 Data). |
* This function is covered by other API functions: |
* - void XAxiDma_BdRingIntEnable(XAxiDma_BdRing* RingPtr, u32 Mask) |
* - void XAxiDma_BdRingIntDisable(XAxiDma_BdRing* RingPtr, u32 Mask) |
* - int XAxiDma_BdRingSetCoalesce(XAxiDma_BdRing * RingPtr, u32 Counter, |
* u32 Timer) |
* |
* - u32 XLlDma_BdSetStsCtrl(XLlDma_Bd* BdPtr, u32 Data). |
* Replaced by XAxiDma_BdSetCtrl(XAxiDma_Bd *BdPtr, u32 Data); |
* |
* - u32 XLlDma_BdGetStsCtrl(XLlDma_Bd* BdPtr). |
* Replaced by XAxiDma_BdGetCtrl(XAxiDma_Bd* BdPtr) and |
* XAxiDma_BdGetSts(XAxiDma_Bd* BdPtr). |
* |
* <b>API Functions That Have Been Added to support simple DMA mode</b> |
* |
* - u32 XAxiDma_Busy(XAxiDma *InstancePtr,int Direction); |
* - int XAxiDma_SimpleTransfer(XAxiDma *InstancePtr, u32 BuffAddr, int Length, |
* int Direction); |
* - XAxiDma_HasSg(InstancePtr); |
* - XAxiDma_IntrEnable(InstancePtr,Mask,Direction); |
* - XAxiDma_IntrGetEnabled(InstancePtr, Direction); |
* - XAxiDma_IntrDisable(InstancePtr, Mask, Direction); |
* - XAxiDma_IntrGetIrq(InstancePtr, Direction); |
* - XAxiDma_IntrAckIrq(InstancePtr, Mask, Direction); |
* |
* <b> For xaxidma driver v6_00_a Multiple Channel Support |
* --------------------------------------------------- |
* This driver supports Multi-channel mode and accordingly some APIs are |
* changed to index multiple channels. Few new APIs are added. |
* - Changed APIs |
* * XAxiDma_GetRxRing(InstancePtr, RingIndex) |
* * XAxiDma_Start(XAxiDma * InstancePtr, int RingIndex) |
* * XAxiDma_Started(XAxiDma * InstancePtr, int RingIndex) |
* * XAxiDma_Pause(XAxiDma * InstancePtr, int RingIndex) |
* * XAxiDma_Resume(XAxiDma * InstancePtr, int RingIndex) |
* * XAxiDma_SimpleTransfer(XAxiDma *InstancePtr, |
* u32 BuffAddr, u32 Length, |
* int Direction, int RingIndex) |
* * XAxiDma_StartBdRingHw(XAxiDma_BdRing * RingPtr, |
* int RingIndex) |
* * XAxiDma_BdRingStart(XAxiDma_BdRing * RingPtr, |
* int RingIndex) |
* * XAxiDma_BdRingToHw(XAxiDma_BdRing * RingPtr, |
* int NumBd, XAxiDma_Bd * BdSetPtr, int RingIndex) |
* * XAxiDma_BdRingDumpRegs(XAxiDma_BdRing * RingPtr, |
* int RingIndex) |
* * XAxiDma_BdRingSnapShotCurrBd(XAxiDma_BdRing * RingPtr, |
* int RingIndex) |
* * XAxiDma_BdSetLength(XAxiDma_Bd *BdPtr, |
* u32 LenBytes, u32 LengthMask) |
* * XAxiDma_BdGetActualLength(BdPtr, LengthMask) |
* * XAxiDma_BdGetLength(BdPtr, LengthMask) |
* |
* - New APIs |
* * XAxiDma_SelectKeyHole(XAxiDma *InstancePtr, |
* int Direction, int Select) |
* * XAxiDma_UpdateBdRingCDesc(XAxiDma_BdRing * RingPtr, |
* int RingIndex) |
* * XAxiDma_BdSetTId() |
* * XAxiDma_BdGetTId() |
* * XAxiDma_BdSetTDest() |
* * XAxiDma_BdGetTDest() |
* * XAxiDma_BdSetTUser() |
* * XAxiDma_BdGetTUser() |
* * XAxiDma_BdSetARCache() |
* * XAxiDma_BdGetARCache() |
* * XAxiDma_BdSetARUser() |
* * XAxiDma_BdGetARUser() |
* * XAxiDma_BdSetStride() |
* * XAxiDma_BdGetStride() |
* * XAxiDma_BdSetVSize() |
* * XAxiDma_BdGetVSize() |
* <b> For xaxidma driver v7_00_a |
* --------------------------------------------------- |
* - New API |
* * XAxiDma_GetRxIndexRing(InstancePtr, RingIndex) |
* |
* - Changed APIs |
* All the APIs changed in v6_00_a are reverted back for backward |
* compatibility. |
*</pre> |
* |
******************************************************************************/ |
/** @} */ |
/trunk/sw/dev/test_main/src/_hdl/bsp/libsrc/axidma_v9_0/src/xaxidma_selftest.c
0,0 → 1,115
/****************************************************************************** |
* |
* Copyright (C) 2015 Xilinx, Inc. All rights reserved. |
* |
* Permission is hereby granted, free of charge, to any person obtaining a copy |
* of this software and associated documentation files (the "Software"), to deal |
* in the Software without restriction, including without limitation the rights |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
* copies of the Software, and to permit persons to whom the Software is |
* furnished to do so, subject to the following conditions: |
* |
* The above copyright notice and this permission notice shall be included in |
* all copies or substantial portions of the Software. |
* |
* Use of the Software is limited solely to applications: |
* (a) running on a Xilinx device, or |
* (b) that interact with a Xilinx device through a bus or interconnect. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF |
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
* SOFTWARE. |
* |
* Except as contained in this notice, the name of the Xilinx shall not be used |
* in advertising or otherwise to promote the sale, use or other dealings in |
* this Software without prior written authorization from Xilinx. |
* |
******************************************************************************/ |
/*****************************************************************************/ |
/** |
* |
* @file xaxidma_selftest.c |
* @addtogroup axidma_v9_0 |
* @{ |
* |
* Contains diagnostic/self-test functions for the XAxiDma component. |
* |
* <pre> |
* MODIFICATION HISTORY: |
* |
* Ver Who Date Changes |
* ----- ---- -------- ----------------------------------------------- |
* 8.1 adk 29/01/15 First release |
* </pre> |
* |
******************************************************************************/ |
|
/***************************** Include Files *********************************/ |
|
#include "xil_io.h" |
#include "xaxidma.h" |
|
|
/************************** Constant Definitions *****************************/ |
#define XAXIDMA_RESET_TIMEOUT 500 |
|
/**************************** Type Definitions *******************************/ |
|
|
/***************** Macros (Inline Functions) Definitions *********************/ |
|
|
/************************** Function Prototypes ******************************/ |
|
|
/************************** Variable Definitions *****************************/ |
|
|
/*****************************************************************************/ |
/** |
* |
* Runs a self-test on the driver/device. This test perform a |
* reset of the DMA device and checks the device is coming out of reset or not |
* |
* @param InstancePtr is a pointer to the XAxiDma instance. |
* |
* @return |
* - XST_SUCCESS if self-test was successful |
* - XST_FAILURE if the device is not coming out of reset. |
* |
* @note |
* None. |
* |
******************************************************************************/ |
int XAxiDma_Selftest(XAxiDma * InstancePtr) |
{ |
int TimeOut; |
|
Xil_AssertNonvoid(InstancePtr != NULL); |
|
XAxiDma_Reset(InstancePtr); |
|
/* At the initialization time, hardware should finish reset quickly |
*/ |
TimeOut = XAXIDMA_RESET_TIMEOUT; |
|
while (TimeOut) { |
|
if(XAxiDma_ResetIsDone(InstancePtr)) { |
break; |
} |
|
TimeOut -= 1; |
|
} |
|
if (!TimeOut) |
return XST_FAILURE; |
|
return XST_SUCCESS; |
} |
/** @} */ |
/trunk/sw/dev/test_main/src/_hdl/bsp/libsrc/axidma_v9_0/src/xaxidma_sinit.c
0,0 → 1,95
/****************************************************************************** |
* |
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. |
* |
* Permission is hereby granted, free of charge, to any person obtaining a copy |
* of this software and associated documentation files (the "Software"), to deal |
* in the Software without restriction, including without limitation the rights |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
* copies of the Software, and to permit persons to whom the Software is |
* furnished to do so, subject to the following conditions: |
* |
* The above copyright notice and this permission notice shall be included in |
* all copies or substantial portions of the Software. |
* |
* Use of the Software is limited solely to applications: |
* (a) running on a Xilinx device, or |
* (b) that interact with a Xilinx device through a bus or interconnect. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF |
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
* SOFTWARE. |
* |
* Except as contained in this notice, the name of the Xilinx shall not be used |
* in advertising or otherwise to promote the sale, use or other dealings in |
* this Software without prior written authorization from Xilinx. |
* |
******************************************************************************/ |
/*****************************************************************************/ |
/** |
* |
* @file xaxidma_sinit.c |
* @addtogroup axidma_v9_0 |
* @{ |
* |
* Look up the hardware settings using device ID. The hardware setting is inside |
* the configuration table in xaxidma_g.c, generated automatically by XPS or |
* manually by the user. |
* |
* <pre> |
* MODIFICATION HISTORY: |
* |
* Ver Who Date Changes |
* ----- ---- -------- ------------------------------------------------------- |
* 1.00a jz 08/16/10 First release |
* 2.00a jz 08/10/10 Second release, added in xaxidma_g.c, xaxidma_sinit.c, |
* updated tcl file, added xaxidma_porting_guide.h |
* 3.00a jz 11/22/10 Support IP core parameters change |
* 5.00a srt 08/29/11 Removed a compiler warning |
* |
* </pre> |
* |
******************************************************************************/ |
|
/***************************** Include Files *********************************/ |
|
#include "xparameters.h" |
#include "xaxidma.h" |
|
|
/*****************************************************************************/ |
/** |
* Look up the hardware configuration for a device instance |
* |
* @param DeviceId is the unique device ID of the device to lookup for |
* |
* @return |
* The configuration structure for the device. If the device ID is |
* not found,a NULL pointer is returned. |
* |
* @note None |
* |
******************************************************************************/ |
XAxiDma_Config *XAxiDma_LookupConfig(u32 DeviceId) |
{ |
extern XAxiDma_Config XAxiDma_ConfigTable[]; |
XAxiDma_Config *CfgPtr; |
u32 Index; |
|
CfgPtr = NULL; |
|
for (Index = 0; Index < XPAR_XAXIDMA_NUM_INSTANCES; Index++) { |
if (XAxiDma_ConfigTable[Index].DeviceId == DeviceId) { |
|
CfgPtr = &XAxiDma_ConfigTable[Index]; |
break; |
} |
} |
|
return CfgPtr; |
} |
/** @} */ |
/trunk/sw/dev/test_main/src/_hdl/bsp/libsrc/axidma_v9_0/src/xdebug.h
0,0 → 1,94
/****************************************************************************** |
* |
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. |
* |
* Permission is hereby granted, free of charge, to any person obtaining a copy |
* of this software and associated documentation files (the "Software"), to deal |
* in the Software without restriction, including without limitation the rights |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
* copies of the Software, and to permit persons to whom the Software is |
* furnished to do so, subject to the following conditions: |
* |
* The above copyright notice and this permission notice shall be included in |
* all copies or substantial portions of the Software. |
* |
* Use of the Software is limited solely to applications: |
* (a) running on a Xilinx device, or |
* (b) that interact with a Xilinx device through a bus or interconnect. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF |
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
* SOFTWARE. |
* |
* Except as contained in this notice, the name of the Xilinx shall not be used |
* in advertising or otherwise to promote the sale, use or other dealings in |
* this Software without prior written authorization from Xilinx. |
* |
******************************************************************************/ |
#ifndef _XDEBUG_H |
#define _XDEBUG_H |
|
#include "xil_printf.h" |
#if defined(DEBUG) && !defined(NDEBUG) |
|
#include <stdio.h> |
|
#ifndef XDEBUG_WARNING |
#define XDEBUG_WARNING |
#warning DEBUG is enabled |
#endif |
|
#define XDBG_DEBUG_ERROR 0x00000001 /* error condition messages */ |
#define XDBG_DEBUG_GENERAL 0x00000002 /* general debug messages */ |
#define XDBG_DEBUG_ALL 0xFFFFFFFF /* all debugging data */ |
|
#define XDBG_DEBUG_FIFO_REG 0x00000100 /* display register reads/writes */ |
#define XDBG_DEBUG_FIFO_RX 0x00000101 /* receive debug messages */ |
#define XDBG_DEBUG_FIFO_TX 0x00000102 /* transmit debug messages */ |
#define XDBG_DEBUG_FIFO_ALL 0x0000010F /* all fifo debug messages */ |
|
#define XDBG_DEBUG_TEMAC_REG 0x00000400 /* display register reads/writes */ |
#define XDBG_DEBUG_TEMAC_RX 0x00000401 /* receive debug messages */ |
#define XDBG_DEBUG_TEMAC_TX 0x00000402 /* transmit debug messages */ |
#define XDBG_DEBUG_TEMAC_ALL 0x0000040F /* all temac debug messages */ |
|
#define XDBG_DEBUG_TEMAC_ADPT_RX 0x00000800 /* receive debug messages */ |
#define XDBG_DEBUG_TEMAC_ADPT_TX 0x00000801 /* transmit debug messages */ |
#define XDBG_DEBUG_TEMAC_ADPT_IOCTL 0x00000802 /* ioctl debug messages */ |
#define XDBG_DEBUG_TEMAC_ADPT_MISC 0x00000803 /* debug msg for other routines */ |
#define XDBG_DEBUG_TEMAC_ADPT_ALL 0x0000080F /* all temac adapter debug messages */ |
|
#define xdbg_current_types (XDBG_DEBUG_ERROR) |
|
#define xdbg_stmnt(x) x |
|
/* In VxWorks, if _WRS_GNU_VAR_MACROS is defined, special syntax is needed for |
* macros that accept variable number of arguments |
*/ |
#if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS) |
#define xdbg_printf(type, args...) (((type) & xdbg_current_types) ? printf (## args) : 0) |
|
#else /* ANSI Syntax */ |
|
#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0) |
|
#endif |
|
#else /* defined(DEBUG) && !defined(NDEBUG) */ |
|
#define xdbg_stmnt(x) |
|
/* See VxWorks comments above */ |
#if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS) |
#define xdbg_printf(type, args...) |
#else /* ANSI Syntax */ |
#define xdbg_printf(...) |
#endif |
|
#endif /* defined(DEBUG) && !defined(NDEBUG) */ |
|
#endif /* _XDEBUG_H */ |
/trunk/sw/dev/test_main/src/_hdl/bsp/libsrc/standalone_v5_3/src/xil_assert.c
0,0 → 1,151
/****************************************************************************** |
* |
* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. |
* |
* Permission is hereby granted, free of charge, to any person obtaining a copy |
* of this software and associated documentation files (the "Software"), to deal |
* in the Software without restriction, including without limitation the rights |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
* copies of the Software, and to permit persons to whom the Software is |
* furnished to do so, subject to the following conditions: |
* |
* The above copyright notice and this permission notice shall be included in |
* all copies or substantial portions of the Software. |
* |
* Use of the Software is limited solely to applications: |
* (a) running on a Xilinx device, or |
* (b) that interact with a Xilinx device through a bus or interconnect. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF |
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
* SOFTWARE. |
* |
* Except as contained in this notice, the name of the Xilinx shall not be used |
* in advertising or otherwise to promote the sale, use or other dealings in |
* this Software without prior written authorization from Xilinx. |
* |
******************************************************************************/ |
/*****************************************************************************/ |
/** |
* |
* @file xil_assert.c |
* |
* This file contains basic assert related functions for Xilinx software IP. |
* |
* <pre> |
* MODIFICATION HISTORY: |
* |
* Ver Who Date Changes |
* ----- ---- -------- ------------------------------------------------------- |
* 1.00a hbm 07/14/09 Initial release |
* </pre> |
* |
******************************************************************************/ |
|
/***************************** Include Files *********************************/ |
|
#include "xil_types.h" |
#include "xil_assert.h" |
|
#include <stdio.h> |
#include "simple.h" // ublaze_final |
|
/************************** Constant Definitions *****************************/ |
|
/**************************** Type Definitions *******************************/ |
|
/***************** Macros (Inline Functions) Definitions *********************/ |
|
/************************** Variable Definitions *****************************/ |
|
/** |
* This variable allows testing to be done easier with asserts. An assert |
* sets this variable such that a driver can evaluate this variable |
* to determine if an assert occurred. |
*/ |
u32 Xil_AssertStatus; |
|
/** |
* This variable allows the assert functionality to be changed for testing |
* such that it does not wait infinitely. Use the debugger to disable the |
* waiting during testing of asserts. |
*/ |
/*s32 Xil_AssertWait = 1*/ |
|
/* The callback function to be invoked when an assert is taken */ |
static Xil_AssertCallback Xil_AssertCallbackRoutine = NULL; |
|
/************************** Function Prototypes ******************************/ |
|
/*****************************************************************************/ |
/** |
* |
* Implement assert. Currently, it calls a user-defined callback function |
* if one has been set. Then, it potentially enters an infinite loop depending |
* on the value of the Xil_AssertWait variable. |
* |
* @param file is the name of the filename of the source |
* @param line is the linenumber within File |
* |
* @return None. |
* |
* @note None. |
* |
******************************************************************************/ |
void Xil_Assert(const char8 *File, s32 Line) |
{ |
//s32 Xil_AssertWait = 1; |
/* if the callback has been set then invoke it */ |
/*if (Xil_AssertCallbackRoutine != 0) { |
(*Xil_AssertCallbackRoutine)(File, Line); |
}*/ |
|
/* if specified, wait indefinitely such that the assert will show up |
* in testing |
*/ |
/*while (Xil_AssertWait != 0) { |
}*/ |
printf("Xil_Assert: %i: ", Line); printf(File); |
ublaze_final(); |
} |
|
/*****************************************************************************/ |
/** |
* |
* Set up a callback function to be invoked when an assert occurs. If there |
* was already a callback installed, then it is replaced. |
* |
* @param routine is the callback to be invoked when an assert is taken |
* |
* @return None. |
* |
* @note This function has no effect if NDEBUG is set |
* |
******************************************************************************/ |
void Xil_AssertSetCallback(Xil_AssertCallback Routine) |
{ |
Xil_AssertCallbackRoutine = Routine; |
} |
|
/*****************************************************************************/ |
/** |
* |
* Null handler function. This follows the XInterruptHandler signature for |
* interrupt handlers. It can be used to assign a null handler (a stub) to an |
* interrupt controller vector table. |
* |
* @param NullParameter is an arbitrary void pointer and not used. |
* |
* @return None. |
* |
* @note None. |
* |
******************************************************************************/ |
void XNullHandler(void *NullParameter) |
{ |
(void *) NullParameter; |
} |
/trunk/sw/dev/test_main/src/_hdl/bsp/libsrc/standalone_v5_3/src/xil_cache.c
0,0 → 1,94
/****************************************************************************** |
* |
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. |
* |
* Permission is hereby granted, free of charge, to any person obtaining a copy |
* of this software and associated documentation files (the "Software"), to deal |
* in the Software without restriction, including without limitation the rights |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
* copies of the Software, and to permit persons to whom the Software is |
* furnished to do so, subject to the following conditions: |
* |
* The above copyright notice and this permission notice shall be included in |
* all copies or substantial portions of the Software. |
* |
* Use of the Software is limited solely to applications: |
* (a) running on a Xilinx device, or |
* (b) that interact with a Xilinx device through a bus or interconnect. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF |
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
* SOFTWARE. |
* |
* Except as contained in this notice, the name of the Xilinx shall not be used |
* in advertising or otherwise to promote the sale, use or other dealings in |
* this Software without prior written authorization from Xilinx. |
* |
******************************************************************************/ |
/*****************************************************************************/ |
/** |
* |
* @file xil_cache.c |
* |
* This contains implementation of cache related driver functions. |
* |
* <pre> |
* MODIFICATION HISTORY: |
* |
* Ver Who Date Changes |
* ----- ---- -------- ------------------------------------------------------- |
* 1.00 hbm 07/28/09 Initial release |
* 3.10 asa 05/04/13 This version of MicroBlaze BSP adds support for system |
* cache/L2 cache. Existing APIs in this file are modified |
* to add support for L2 cache. |
* These changes are done for implementing PR #697214. |
* </pre> |
* |
* @note |
* |
* None. |
* |
******************************************************************************/ |
|
#include "xil_cache.h" |
|
|
/****************************************************************************/ |
/** |
* |
* Disable the data cache. |
* |
* @param None |
* |
* @return None. |
* |
****************************************************************************/ |
void Xil_DCacheDisable(void) |
{ |
Xil_DCacheFlush(); |
Xil_DCacheInvalidate(); |
Xil_L1DCacheDisable(); |
} |
|
/****************************************************************************/ |
/** |
* |
* Disable the instruction cache. |
* |
* @param None |
* |
* @return None. |
* |
* @note |
* |
* |
****************************************************************************/ |
void Xil_ICacheDisable(void) |
{ |
Xil_ICacheInvalidate(); |
Xil_L1ICacheDisable(); |
} |
/trunk/sw/dev/test_main/src/_hdl/bsp/libsrc/standalone_v5_3/src/xil_io.c
0,0 → 1,364
/****************************************************************************** |
* |
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. |
* |
* Permission is hereby granted, free of charge, to any person obtaining a copy |
* of this software and associated documentation files (the "Software"), to deal |
* in the Software without restriction, including without limitation the rights |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
* copies of the Software, and to permit persons to whom the Software is |
* furnished to do so, subject to the following conditions: |
* |
* The above copyright notice and this permission notice shall be included in |
* all copies or substantial portions of the Software. |
* |
* Use of the Software is limited solely to applications: |
* (a) running on a Xilinx device, or |
* (b) that interact with a Xilinx device through a bus or interconnect. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF |
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
* SOFTWARE. |
* |
* Except as contained in this notice, the name of the Xilinx shall not be used |
* in advertising or otherwise to promote the sale, use or other dealings in |
* this Software without prior written authorization from Xilinx. |
* |
******************************************************************************/ |
/*****************************************************************************/ |
/** |
* |
* @file xil_io.c |
* |
* Contains I/O functions for memory-mapped architectures. These functions |
* encapsulate generic CPU I/O requirements. |
* |
* <pre> |
* MODIFICATION HISTORY: |
* |
* Ver Who Date Changes |
* ----- ---- -------- ------------------------------------------------------- |
* 3.00a hbm 07/28/09 Initial release |
* 3.00a hbm 07/21/10 Added Xil_EndianSwap32/16, Xil_Htonl/s, Xil_Ntohl/s |
* |
* </pre> |
* |
* @note |
* |
* This file may contain architecture-dependent code. |
* |
******************************************************************************/ |
|
/***************************** Include Files *********************************/ |
|
#include "xil_io.h" |
#include "xil_types.h" |
|
/************************** Constant Definitions *****************************/ |
|
|
/**************************** Type Definitions *******************************/ |
|
|
/***************** Macros (Inline Functions) Definitions *********************/ |
|
|
/************************** Function Prototypes ******************************/ |
|
|
/***************** Macros (Inline Functions) and Functions Definitions *******/ |
|
/*****************************************************************************/ |
/** |
* |
* Perform an input operation for an 8-bit memory location by reading from the |
* specified address and returning the value read from that address. |
* |
* @param Addr contains the address to perform the input operation at. |
* |
* @return The value read from the specified input address. |
* |
* @note None. |
* |
******************************************************************************/ |
u8 Xil_In8(u32 Addr) { |
// return *(volatile u8 *)Addr; |
return( (u8)(axi_read_(Addr, 0x01)) ); |
} |
|
/*****************************************************************************/ |
/** |
* |
* Perform an input operation for a 16-bit memory location by reading from the |
* specified address and returning the value read from that address. |
* |
* @param Addr contains the address to perform the input operation at. |
* |
* @return The value read from the specified input address. |
* |
* @note None. |
* |
******************************************************************************/ |
u16 Xil_In16(u32 Addr) { |
// return *(volatile u16 *)Addr; |
return( (u16)(axi_read_(Addr, 0x03)) ); |
} |
|
/*****************************************************************************/ |
/** |
* |
* Performs an input operation for a 32-bit memory location by reading from the |
* specified address and returning the Value read from that address. |
* |
* @param Addr contains the address to perform the input operation at. |
* |
* @return The value read from the specified input address. |
* |
* @note None. |
* |
******************************************************************************/ |
u32 Xil_In32(u32 Addr) { |
// return *(volatile u32 *)Addr; |
return( (u32)(axi_read_(Addr, 0x0F)) ); |
} |
|
|
/*****************************************************************************/ |
/** |
* |
* Perform an output operation for an 8-bit memory location by writing the |
* specified value to the specified address. |
* |
* @param Addr contains the address to perform the output operation at. |
* @param value contains the value to be output at the specified address. |
* |
* @return None |
* |
* @note None. |
* |
******************************************************************************/ |
void Xil_Out8(u32 Addr, u8 Value) { |
// u8 *LocalAddr = (u8 *)Addr; |
// *LocalAddr = Value; |
axi_write(Addr, 0x01 , Value); |
} |
|
/*****************************************************************************/ |
/** |
* |
* Perform an output operation for a 16-bit memory location by writing the |
* specified value to the specified address. |
* |
* @param Addr contains the address to perform the output operation at. |
* @param value contains the value to be output at the specified address. |
* |
* @return None |
* |
* @note None. |
* |
******************************************************************************/ |
void Xil_Out16(u32 Addr, u16 Value) { |
// u16 *LocalAddr = (u16 *)Addr; |
// *LocalAddr = Value; |
axi_write(Addr, 0x03, Value); |
} |
|
/*****************************************************************************/ |
/** |
* |
* Perform an output operation for a 32-bit memory location by writing the |
* specified value to the specified address. |
* |
* @param addr contains the address to perform the output operation at. |
* @param value contains the value to be output at the specified address. |
* |
* @return None |
* |
* @note None. |
* |
******************************************************************************/ |
void Xil_Out32(u32 Addr, u32 Value) { |
// u32 *LocalAddr = (u32 *)Addr; |
// *LocalAddr = Value; |
axi_write(Addr, 0x0F, Value); |
} |
|
/*****************************************************************************/ |
/** |
* |
* Perform a 16-bit endian converion. |
* |
* @param Data contains the value to be converted. |
* |
* @return converted value. |
* |
* @note None. |
* |
******************************************************************************/ |
u16 Xil_EndianSwap16(u16 Data) |
{ |
return (u16) (((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U)); |
} |
|
/*****************************************************************************/ |
/** |
* |
* Perform a 32-bit endian converion. |
* |
* @param Data contains the value to be converted. |
* |
* @return converted value. |
* |
* @note None. |
* |
******************************************************************************/ |
u32 Xil_EndianSwap32(u32 Data) |
{ |
u16 LoWord; |
u16 HiWord; |
|
/* get each of the half words from the 32 bit word */ |
|
LoWord = (u16) (Data & 0x0000FFFFU); |
HiWord = (u16) ((Data & 0xFFFF0000U) >> 16U); |
|
/* byte swap each of the 16 bit half words */ |
|
LoWord = (((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U)); |
HiWord = (((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U)); |
|
/* swap the half words before returning the value */ |
|
return ((((u32)LoWord) << (u32)16U) | (u32)HiWord); |
} |
|
/*****************************************************************************/ |
/** |
* |
* Perform a little-endian input operation for a 16-bit memory location |
* by reading from the specified address and returning the byte-swapped value |
* read from that address. |
* |
* @param Addr contains the address to perform the input operation at. |
* |
* @return The value read from the specified input address with the |
* proper endianness. The return value has the same endianness |
* as that of the processor, i.e. if the processor is big-engian, |
* the return value is the byte-swapped value read from the |
* address. |
* |
* |
* @note None. |
* |
******************************************************************************/ |
#ifndef __LITTLE_ENDIAN__ |
u16 Xil_In16LE(u32 Addr) |
#else |
u16 Xil_In16BE(u32 Addr) |
#endif |
{ |
u16 Value; |
|
/* get the data then swap it */ |
Value = Xil_In16(Addr); |
|
return Xil_EndianSwap16(Value); |
} |
|
/*****************************************************************************/ |
/** |
* |
* Perform a little-endian input operation for a 32-bit memory location |
* by reading from the specified address and returning the byte-swapped value |
* read from that address. |
* |
* @param Addr contains the address to perform the input operation at. |
* |
* @return The value read from the specified input address with the |
* proper endianness. The return value has the same endianness |
* as that of the processor, i.e. if the processor is big-engian, |
* the return value is the byte-swapped value read from the |
* address. |
* |
* @note None. |
* |
******************************************************************************/ |
#ifndef __LITTLE_ENDIAN__ |
u32 Xil_In32LE(u32 Addr) |
#else |
u32 Xil_In32BE(u32 Addr) |
#endif |
{ |
u32 InValue; |
|
/* get the data then swap it */ |
InValue = Xil_In32(Addr); |
return Xil_EndianSwap32(InValue); |
} |
|
/*****************************************************************************/ |
/** |
* |
* Perform a little-endian output operation for a 16-bit memory location by |
* writing the specified value to the the specified address. The value is |
* byte-swapped before being written. |
* |
* @param Addr contains the address to perform the output operation at. |
* @param Value contains the value to be output at the specified address. |
* The value has the same endianness as that of the processor. |
* If the processor is big-endian, the byte-swapped value is |
* written to the address. |
* |
* @return None. |
* |
* @note None. |
* |
******************************************************************************/ |
#ifndef __LITTLE_ENDIAN__ |
void Xil_Out16LE(u32 Addr, u16 Value) |
#else |
void Xil_Out16BE(u32 Addr, u16 Value) |
#endif |
{ |
u16 OutValue; |
|
/* swap the data then output it */ |
OutValue = Xil_EndianSwap16(Value); |
|
Xil_Out16(Addr, OutValue); |
} |
|
/*****************************************************************************/ |
/** |
* |
* Perform a little-endian output operation for a 32-bit memory location |
* by writing the specified value to the the specified address. The value is |
* byte-swapped before being written. |
* |
* @param Addr contains the address at which the output operation at. |
* @param Value contains the value to be output at the specified address. |
* The value has the same endianness as that of the processor. |
* If the processor is big-endian, the byte-swapped value is |
* written to the address. |
* |
* @return None. |
* |
* @note None. |
* |
******************************************************************************/ |
#ifndef __LITTLE_ENDIAN__ |
void Xil_Out32LE(u32 Addr, u32 Value) |
#else |
void Xil_Out32BE(u32 Addr, u32 Value) |
#endif |
{ |
u32 OutValue; |
|
/* swap the data then output it */ |
OutValue = Xil_EndianSwap32(Value); |
Xil_Out32(Addr, OutValue); |
} |
/trunk/sw/dev/test_main/src/_hdl/dpi/simple.c
0,0 → 1,6
|
#include "simple.h" |
|
/*AXI-wrap*/ |
unsigned int axi_read_(int iv_addr, int iv_be) |
{ int ov_data=-1; axi_read(iv_addr, iv_be, &ov_data); return ov_data; } |
/trunk/sw/dev/test_main/src/_hdl/dpi/simple.h
0,0 → 1,48
/* MTI_DPI */ |
#ifndef INCLUDED_SIMPLE |
#define INCLUDED_SIMPLE |
|
#ifdef __cplusplus |
#define DPI_LINK_DECL extern "C" |
#else |
#define DPI_LINK_DECL |
#endif |
|
#include "svdpi.h" |
|
// |
// main |
DPI_LINK_DECL DPI_DLLESPEC |
int |
main(); |
// |
// axi-direct |
DPI_LINK_DECL int |
axi_read( |
int iv_addr, |
int iv_be, |
int* ov_data); |
|
DPI_LINK_DECL int |
axi_write( |
int iv_addr, |
int iv_be, |
int ov_data); |
// |
// sw-hdl sync |
DPI_LINK_DECL int |
ublaze_initial(); |
|
DPI_LINK_DECL int |
ublaze_final(); |
|
DPI_LINK_DECL int |
ublaze_wait( |
int iv_value); |
|
/*AXI-wrap*/ |
DPI_LINK_DECL |
unsigned int axi_read_(int iv_addr, int iv_be); |
/*AXI-wrap*/ |
|
#endif // INCLUDED_SIMPLE |
/trunk/sw/dev/test_main/src/main/test_main.c
0,0 → 1,107
/* |
* simple test application |
* |
* UART baud rate == 115200 |
* |
*/ |
|
#include <stdio.h> |
#ifndef MSIM |
#include "platform.h" |
#else |
#include "xil_printf.h" |
#endif // MSIM |
|
|
#include "xparameters.h" // XPAR_TMEMAC_0_BASEADDR, XPAR_AXIDMA_0_DEVICE_ID, XPAR_BRAM_0_BASEADDR |
#include "tri_mode_emac.h" // tmemac_cfg_t |
|
#include "xil_lib.h" // xil_malloc, xil_free |
|
#include "net.h" // net_init, net_input |
#include "arp.h" |
#include "ip.h" |
|
// CFG: |
// eth pkt |
#define ETH_MIN_PKT_LEN 64 |
#define ETH_MAX_PKT_LEN 1024 |
// tri_mode_emac |
tmemac_cfg_t tmemac_cfg; |
|
// lightweight version of stdio-GETCHAR / !!!no HDR-file for inbyte.c!!! |
char inbyte(void); |
|
// MAIN |
int main(void) |
{ |
// dec vars |
int result; |
|
// init |
#ifndef MSIM |
init_platform(); |
#else |
ublaze_initial(); ublaze_wait(100); |
#endif // MSIM |
|
// msg2usr |
xil_printf("Hello from MICROB\n\r"); |
// w8 |
#ifndef MSIM |
inbyte();// w8 4 user |
#endif // MSIM |
|
// prep cfg / MAC: {locally administered address}!!! |
tmemac_cfg.base = XPAR_TMEMAC_0_BASEADDR; |
tmemac_cfg.mac_high = _MAC_ADDR_HIGH(0x02, 0x05); // 02-05 |
tmemac_cfg.mac_low = _MAC_ADDR_LOW( 0x69, 0x03, 0x04, 0x05); // 69-03-04-05 |
tmemac_cfg.ip_addr = _IP_ADDR(192,168,43,5); // !!!RFC6890: Priv-16 / RFC1918 |
|
// net init |
result = net_init( &tmemac_cfg, |
(XPAR_BRAM_0_BASEADDR + 0), |
(XPAR_BRAM_0_BASEADDR + ETH_MAX_PKT_LEN)); |
if (result) { |
xil_printf("ERR: net_init: %x\n\r", result); |
xil_printf("MICROB: exit\n\r"); |
return -1; |
} |
|
// rx-buff-malloc |
char *buff = (char *)xil_malloc(ETH_MAX_PKT_LEN); |
if (!buff){ |
xil_printf("ERR: xil_malloc\n\r"); |
xil_printf("MICROB: exit\n\r"); |
return -1; |
} |
|
// proc-loop |
while (1) { |
// proc |
result = net_input(buff); |
// check err |
if (result < 0) { |
xil_printf("ERR: net_input: %x\n\r", result); |
break; |
} |
// check rxd |
if (result) { |
// ARP |
eth_arp(buff); |
// IP-ICMP |
eth_ip(buff); |
} |
} |
// if we are here -> clean+msg2usr |
xil_free(buff); |
xil_printf("MICROB: exit\n\r"); |
|
// Final |
#ifndef MSIM |
cleanup_platform(); |
#else |
//ublaze_final(); |
#endif // MSIM |
return 0; |
} |
/trunk/sw/dev/test_main/src/net/arp.c
0,0 → 1,73
|
#include <stdio.h> |
|
#include "xil_types.h" |
#include "xil_io.h" |
|
#include "xil_lib.h" // xil_malloc, xil_free |
|
#include "eth.h" |
#include "arp.h" |
|
// net-if |
net_if_t *ifp; |
|
// ?? |
void eth_arp_init(net_if_t *ip_net_if) |
{ |
ifp = ip_net_if; |
// Final |
} |
// simple arp req-resp logic: |
void eth_arp(char *iv_data) |
{ |
// extract Eth-Type |
char *ethin = iv_data; |
u16 etype = ETH_TYPE_GET(ethin); |
// chk ARP-proto |
if (etype != ntohs(ETH_ARP)) { |
return; |
} |
|
// chk ipkt |
arp_hdr_t *in = (arp_hdr_t *)(iv_data + ETH_HDR_SZ); |
if (in->ar_pro != ARP_IPv4) { |
return; |
} |
if (in->ar_op != ARP_REQ) { |
return; |
} |
if (in->ar_tpa != ifp->ip_addr) { |
return; |
} |
|
// alloc/init opkt |
char *ethout = xil_malloc(ARP_SZ); // <- |
arp_hdr_t *out = (arp_hdr_t *)(ethout + ETH_HDR_SZ); |
if (!ethout) { // xil_malloc-ERR |
return; |
} |
xil_memset(ethout, 0, ARP_SZ); |
|
// fill opkt |
xil_memmove(ethout + ETH_DST_OFST, ethin + ETH_SRC_OFST, 6); |
xil_memmove(ethout + ETH_SRC_OFST, ifp->mac_addr, 6); |
ETH_TYPE_SET(ethout, ntohs(ETH_ARP)); |
|
out->ar_hd = ARP_HW_ETH; |
out->ar_pro = ARP_IPv4; |
out->ar_hln = 6; |
out->ar_pln = 4; |
out->ar_op = ARP_RESP; |
|
xil_memmove((char *)out->ar_sha, (char *)ifp->mac_addr, 6); |
out->ar_spa = in->ar_tpa; |
xil_memmove((char *)out->ar_tha, (char *)in->ar_sha, 6); |
out->ar_tpa = in->ar_spa; |
|
// tx |
ifp->net_raw_send(ethout, ETH_HDR_SZ+sizeof(arp_hdr_t)); |
|
// Final |
xil_free(ethout); // -> |
} |
/trunk/sw/dev/test_main/src/net/arp.h
0,0 → 1,46
#ifndef _ARP_H_ |
#define _ARP_H_ |
|
#ifdef __cplusplus |
extern "C" |
{ |
#endif// __cplusplus |
|
#include "xil_types.h" |
#include "tri_mode_emac.h" // tmemac_cfg_t |
|
#include "eth.h" // _packed_struct |
#include "net.h" // net_if_t |
|
// ?? |
#define ARP_SZ (64) |
|
// APR-proto definitions / net endian |
#define ETH_ARP htons(0x0806) // Eth-Protocol-Type |
#define ARP_HW_ETH htons(1) // arp hardware type for ethernet |
#define ARP_IPv4 htons(0x0800) // IPv4 type |
#define ARP_REQ htons(1) // byte swapped request opcode |
#define ARP_RESP htons(2) // byte swapped reply opcode |
// tbd |
struct arp_hdr_ { |
u16 ar_hd; /* hardware type */ |
u16 ar_pro; /* protcol type */ |
u8 ar_hln; /* hardware addr length */ |
u8 ar_pln; /* protocol header length */ |
u16 ar_op; /* opcode */ |
u8 ar_sha[6]; /* sender hardware address */ |
u32 ar_spa; /* sender protocol address */ |
u8 ar_tha[6]; /* target hardware address */ |
u32 ar_tpa; /* target protocol address */ |
} _packed_struct; |
typedef struct arp_hdr_ arp_hdr_t; |
|
// Ext: |
void eth_arp_init(net_if_t *ip_net_if); |
void eth_arp(char *iv_data); |
|
#ifdef __cplusplus |
} |
#endif// __cplusplus |
|
#endif // _ARP_H_ |
/trunk/sw/dev/test_main/src/net/cksum.c
0,0 → 1,43
/* |
* |
* Portable C implementation of the Internet checksum, derived |
* from Braden, Borman, and Partridge's example implementation |
* in RFC 1071. |
* |
*/ |
|
unsigned short cksum(void * ptr, int count) |
{ |
unsigned short checksum; |
unsigned short *addr = (unsigned short *)ptr; |
|
/********** code from rfc1071 **********/ |
{ |
/* Compute Internet Checksum for "count" bytes |
* beginning at location "addr". |
*/ |
|
long sum = 0; |
|
while( count > 1 ) |
{ |
/* This is the inner loop */ |
sum += *addr++; |
count -= 2; |
} |
|
/* Add left-over byte, if any */ |
if( count > 0 ) |
sum += * (unsigned char *) addr; |
|
/* Fold 32-bit sum to 16 bits */ |
while (sum>>16) |
sum = (sum & 0xffff) + (sum >> 16); |
|
checksum = ~sum; |
} |
/******** end of RFC 1071 code **********/ |
|
return checksum; |
} |
|
/trunk/sw/dev/test_main/src/net/eth.h
0,0 → 1,55
#ifndef _ETH_H_ |
#define _ETH_H_ |
|
#ifdef __cplusplus |
extern "C" |
{ |
#endif// __cplusplus |
|
#include "xil_types.h" |
|
// ?? |
#define _packed_struct __attribute__ ((__packed__)) |
|
// eth hdr |
struct ethhdr_ { |
u8 e_dst[6]; // ETH_DST_OFST |
u8 e_src[6]; // ETH_SRC_OFST |
u16 e_type; // ETH_TYPE_OFST |
} _packed_struct; |
typedef struct ethhdr_ ethhdr_t; |
|
// define Ethernet header size |
#define ETH_HDR_SZ (sizeof(ethhdr_t)) |
|
// Offset of destination address within Ethernet header |
#define ETH_DST_OFST (0) |
|
// Offset of source address within Ethernet header |
#define ETH_SRC_OFST (6) |
|
// Offset of Ethernet type within Ethernet header |
#define ETH_TYPE_OFST (12) |
|
/* Get Ethernet type from Ethernet header pointed by char * e |
* !!!returned Ethernet type is in host order!!! |
*/ |
#define ETH_TYPE_GET(e) \ |
(((unsigned)(*((e) + ETH_TYPE_OFST)) << 8) + \ |
(*((e) + ETH_TYPE_OFST + 1) & 0xff)) |
|
/* Set Ethernet type in Ethernet header pointed by char * e to value (type) |
* !!!Ethernet type is value is expected to be in host order!!! |
*/ |
#define ETH_TYPE_SET(e, type) \ |
*((e) + ETH_TYPE_OFST) = (unsigned char)(((type) >> 8) & 0xff); \ |
*((e) + ETH_TYPE_OFST + 1) = (unsigned char)((type) & 0xff); |
|
// rfc1071 internet checksum |
unsigned short cksum(void * ptr, int count); |
|
#ifdef __cplusplus |
} |
#endif// __cplusplus |
|
#endif // _ETH_H_ |
/trunk/sw/dev/test_main/src/net/icmp.c
0,0 → 1,52
|
#include "xil_lib.h" |
#include "ip.h" |
#include "icmp.h" |
|
// net-if |
net_if_t *ifp; |
|
// ?? |
void eth_icmp_init(net_if_t *ip_net_if) |
{ |
ifp = ip_net_if; |
// Final |
} |
// {ICMP_ECHO_REQ+ICMP_ECHO_RESP} only!!! |
void eth_icmp(char *iv_data) |
{ |
|
// |
ip_hdr_t *pip = ip_head(iv_data); |
|
// chk ipkt |
icmp_hdr_t *in = (icmp_hdr_t *)(ip_data(pip)); |
int len = htons(pip->ip_len) - ip_hlen(pip); |
|
// !check ICMP Header checksum |
|
// pass pkt to proper ICMP routine |
switch(in->ptype) { |
case ICMP_ECHO_REQ : { |
// mac |
xil_memmove(iv_data + ETH_DST_OFST, iv_data + ETH_SRC_OFST, 6); |
xil_memmove(iv_data + ETH_SRC_OFST, ifp->mac_addr, 6); |
// ptype |
in->ptype = ICMP_ECHO_RESP; |
// checksum |
in->pchksum = 0; |
in->pchksum = cksum(in, len); |
// ip-addr |
pip->ip_dest = pip->ip_src; |
pip->ip_src = ifp->ip_addr; |
// |
ifp->net_raw_send(iv_data, ETH_HDR_SZ+htons(pip->ip_len)); |
break; |
} |
default : { |
//printf("eth_icmp: ptype=%x\n", in->ptype); |
break; |
} |
} |
// Final |
} |
/trunk/sw/dev/test_main/src/net/icmp.h
0,0 → 1,39
#ifndef _ICMP_H_ |
#define _ICMP_H_ |
|
#ifdef __cplusplus |
extern "C" |
{ |
#endif// __cplusplus |
|
#include "eth.h" // _packed_struct |
#include "net.h" |
|
|
#define ICMP_ECHO_RESP 0 // ICMP Echo reply |
#define ICMP_ECHO_REQ 8 // ICMP Echo request |
|
|
#define ICMP_DU_DATA_VOL 8 // RFC792, page#4: 64 bits of Original Data Datagram |
|
#define ICMP_PROT 1 // ICMP Protocol number on IP |
|
// ICMP Echo request/reply header |
struct _icmp_hdr { |
u8 ptype; |
u8 pcode; |
u16 pchksum; |
u16 pid; |
u16 pseq; |
} _packed_struct; |
typedef struct _icmp_hdr icmp_hdr_t; |
|
// Ext: |
void eth_icmp_init(net_if_t *ip_net_if); |
void eth_icmp(char *iv_data); |
|
#ifdef __cplusplus |
} |
#endif// __cplusplus |
|
#endif // _ICMP_H_ |
/trunk/sw/dev/test_main/src/net/ip.c
0,0 → 1,75
|
#include "xil_lib.h" |
#include "ip.h" |
#include "icmp.h" |
|
// net-if |
net_if_t *ifp; |
|
// ?? |
void eth_ip_init(net_if_t *ip_net_if) |
{ |
ifp = ip_net_if; |
// Final |
} |
// simple IP-parser: for {ICMP_PROT} only!!! |
void eth_ip(char *iv_data) |
{ |
|
ip_hdr_t * pip; // the internet header |
u16 ffo; // IP hdr: {flags + fragment_offset} |
|
// |
pip = ip_head(iv_data); |
|
// !check IP version |
if ( ((pip->ip_ver_ihl & 0xf0) >> 4) != IP_VER) { |
//printf("ip_rcv: bad version number\n"); |
return; |
} |
|
// !check IP Header Checksum |
|
// !check our own IP addr / NET IF |
if (pip->ip_dest != ifp->ip_addr) { |
if (pip->ip_dest != 0xFFFFFFFF) { // broadcast for all nets |
//printf("ip_rcv: got pkt not for me; for %x\n", pip->ip_dest); |
return; |
} |
} |
|
// !check TTL |
if (pip->ip_time == 0) { // expired? |
//printf("ip_rcv: bad ttl\n"); |
return; |
} |
|
// Test for fragment: |
ffo = htons(pip->ip_flgs_foff); |
if (ffo & IP_FLG_MASK){ |
if ((ffo & IP_FLG_DF) == 0){ |
//printf("ip_rcv: bad ip-frag\n"); |
return; |
} |
} |
|
// !check IHL |
if ((pip->ip_ver_ihl & 0x0F) != IP_LEN) { |
//printf("ip_rcv: bad IHL\n"); |
return; |
} |
|
// |
// pass pkt to upper layer |
switch(pip->ip_prot) { |
case ICMP_PROT : { // Internet Control Message Protocol type |
eth_icmp(iv_data); |
break; |
} |
default : { // unsupported type |
//printf("ip_rcv: ip_prot=%x\n", pip->ip_prot); |
break; |
} |
} |
// Final |
} |
/trunk/sw/dev/test_main/src/net/ip.h
0,0 → 1,51
#ifndef _IP_H_ |
#define _IP_H_ |
|
#ifdef __cplusplus |
extern "C" |
{ |
#endif// __cplusplus |
|
#include "eth.h" |
#include "net.h" |
|
#define ETH_IP ntohs(0x0800) // IP type, net endian |
|
// tbd |
struct _ip_hdr { |
u8 ip_ver_ihl; // 4 bit version, 4 bit hdr len in 32bit words |
u8 ip_tos; // Type of Service, RFC 2474 -> {DSCP[5:0], ECN[1:0]} |
u16 ip_len; // Total packet length including header |
u16 ip_id; // ID for fragmentation |
u16 ip_flgs_foff; // mask in flags as needed |
u8 ip_time; // Time to live (secs) |
u8 ip_prot; // protocol |
u16 ip_chksum; // Header checksum |
u32 ip_src; // Source Addr |
u32 ip_dest; // Destination Addr |
} _packed_struct; |
typedef struct _ip_hdr ip_hdr_t; |
|
// Some macros for finding IP offsets in incoming packets |
#define ip_head(p) (ip_hdr_t *)(p + ETH_HDR_SZ) |
#define ip_hlen(pip) (((pip)->ip_ver_ihl & 0x0f) << 2) |
#define ip_data(pip) ((char *)(pip) + ip_hlen(pip)) |
|
// fragmentation flag bits, for masking into 16bit flags/offset word |
#define IP_FLG_DF 0x4000 // Don't Fragment (DF) bit |
#define IP_FLG_MF 0x2000 // More Fragments (MF) bit |
#define IP_FLG_MASK 0xe000 // for masking out all flags from word |
|
// IPv4 def: |
#define IP_VER 4 // IPv4 -> 4 / RFC#791 |
#define IP_LEN 5 // RFC#791 -> 5 |
|
// Ext: |
void eth_ip_init(net_if_t *ip_net_if); |
void eth_ip(char *iv_data); |
|
#ifdef __cplusplus |
} |
#endif// __cplusplus |
|
#endif // _IP_H_ |
/trunk/sw/dev/test_main/src/net/net.c
0,0 → 1,174
|
#include <stdio.h> |
|
#include "xil_types.h" |
#include "xil_io.h" |
|
#include "xparameters.h" // XPAR_TMEMAC_0_BASEADDR, XPAR_AXIDMA_0_DEVICE_ID, XPAR_BRAM_0_BASEADDR |
#include "xaxidma.h" // XAxiDma_LookupConfig, .. |
|
#include "net.h" |
#include "arp.h" |
#include "ip.h" |
#include "icmp.h" |
|
// NET-IF |
net_if_t net_if; |
u8 mac_addr[8]; |
|
// DMA |
XAxiDma AxiDma; |
XAxiDma_Config *CfgPtr; |
|
// BUFF |
UINTPTR tx_buff; |
UINTPTR rx_buff; |
int rx_len; |
|
// ?? |
int mac_raw_send(char *data_i, int data_bytes); // net_init |
void low_level_input(char *buff); // net_input |
|
|
// net-stack INIT |
int net_init(tmemac_cfg_t *iv_tmemac_cfg, u32 pkt_tx, u32 pkt_rx) |
{ |
int result; |
|
// DMA init |
CfgPtr = XAxiDma_LookupConfig(XPAR_AXIDMA_0_DEVICE_ID); |
if (!CfgPtr) { return -1; } |
|
result = XAxiDma_CfgInitialize(&AxiDma, CfgPtr); |
if (result != XST_SUCCESS) { return -2; } |
|
XAxiDma_IntrDisable(&AxiDma, XAXIDMA_IRQ_ALL_MASK, XAXIDMA_DEVICE_TO_DMA); // Disable interrupts, we use polling mode |
XAxiDma_IntrDisable(&AxiDma, XAXIDMA_IRQ_ALL_MASK, XAXIDMA_DMA_TO_DEVICE); // .. |
|
tx_buff = (UINTPTR)pkt_tx; |
rx_buff = (UINTPTR)pkt_rx; |
rx_len = 0; |
|
result = XAxiDma_SimpleTransfer(&AxiDma,(UINTPTR)rx_buff, 1024, XAXIDMA_DEVICE_TO_DMA); |
if (result) { |
return -3; |
} |
|
// ETH init |
result = tri_mode_emac_init(iv_tmemac_cfg); |
if (result) { |
return -4; |
} |
|
// NET-IF init |
// ip |
net_if.ip_addr = htonl(iv_tmemac_cfg->ip_addr); |
// mac |
mac_addr[0] = ((iv_tmemac_cfg->mac_high) >> 8) & 0xFF; |
mac_addr[1] = ((iv_tmemac_cfg->mac_high) >> 0) & 0xFF; |
mac_addr[2] = ((iv_tmemac_cfg->mac_low ) >> 24) & 0xFF; |
mac_addr[3] = ((iv_tmemac_cfg->mac_low ) >> 16) & 0xFF; |
mac_addr[4] = ((iv_tmemac_cfg->mac_low ) >> 8) & 0xFF; |
mac_addr[5] = ((iv_tmemac_cfg->mac_low ) >> 0) & 0xFF; |
net_if.mac_addr = &mac_addr[0]; |
// raw_send |
net_if.net_raw_send = mac_raw_send; |
|
// ARP |
eth_arp_init(&net_if); |
// IP |
eth_ip_init(&net_if); |
// ICMP |
eth_icmp_init(&net_if); |
|
// Final |
return 0; |
} |
// poll income-pkt |
int net_input(char *buff) |
{ |
// rx |
low_level_input(buff); |
// prep-len |
int len = rx_len; |
rx_len = 0; |
// Final |
return len; |
} |
|
|
// tbd |
void low_level_input(char *buff) |
{ |
// dec vars |
int i, result; |
|
// check Dma_Busy |
if (XAxiDma_Busy(&AxiDma, XAXIDMA_DEVICE_TO_DMA)) { |
return; |
} |
|
// if we are here -> check dma-status |
result = XAxiDma_IntrGetIrq(&AxiDma, XAXIDMA_DEVICE_TO_DMA); |
if (result & XAXIDMA_IRQ_ERROR_MASK) { |
rx_len = -1; |
return; |
} |
if (result & XAXIDMA_IRQ_IOC_MASK){ |
// if we are here we have rxd / cp 1st 512B to USER-buff |
u32 *tmp = (u32 *)buff; |
for (i = 0; i < 512/4; i++){ |
*tmp = Xil_In32(rx_buff+(i*4)); |
tmp++; |
} |
rx_len = 512/4; |
} |
|
// irq-ack |
XAxiDma_IntrAckIrq(&AxiDma, XAXIDMA_IRQ_ALL_MASK, XAXIDMA_DEVICE_TO_DMA); |
// restart dma |
result = XAxiDma_SimpleTransfer(&AxiDma,(UINTPTR)rx_buff, 1024, XAXIDMA_DEVICE_TO_DMA); |
// Final |
rx_len = (result == XST_SUCCESS)? rx_len : -2; |
} |
// eth-tx data via {DMA+MAC} |
int mac_raw_send(char *data_i, int data_bytes) |
{ |
// dec vars |
int i, len_dw, len_b; |
u32 *odata_dw, *idata_dw; |
u8 *odata_b, *idata_b; |
|
// chk |
if ((long)data_i & 0x03) { // DW-align |
xil_printf("ERR: tx-buff addr\n\r"); |
return -1; |
} |
// prep |
len_dw = data_bytes / 4; |
len_b = data_bytes & (4-1); |
// #0 - copy main DW-body |
odata_dw = (u32 *)tx_buff; |
idata_dw = (u32 *)data_i; |
for (i = 0; i < len_dw; i++) { |
Xil_Out32((long)odata_dw, *idata_dw); |
odata_dw++; idata_dw++; |
} |
// #1 - copy BYTE-tail |
if (len_b) { // always DW-aligned |
Xil_Out32((long)odata_dw, *idata_dw); |
} |
/* |
odata_b = (u8 *)odata_dw; |
idata_b = (u8 *)idata_dw; |
for (i = 0; i < len_b; i++) { |
Xil_Out8((long)odata_b, *idata_b); |
odata_b++; idata_b++; |
} |
*/ |
|
// tx |
i = XAxiDma_SimpleTransfer(&AxiDma, tx_buff, data_bytes, XAXIDMA_DMA_TO_DEVICE); |
// Final |
return i; |
} |
/trunk/sw/dev/test_main/src/net/net.h
0,0 → 1,59
#ifndef _NET_H_ |
#define _NET_H_ |
|
#ifdef __cplusplus |
extern "C" |
{ |
#endif// __cplusplus |
|
#include "xil_types.h" |
#include "tri_mode_emac.h" // tmemac_cfg_t, tri_mode_emac_init |
|
/* |
#ifndef NULL |
#define NULL ((void*)0) |
#endif // NULL |
*/ |
|
// net-order macros |
#define lswap(x) ((((x) & 0xff000000) >> 24) | \ |
(((x) & 0x00ff0000) >> 8) | \ |
(((x) & 0x0000ff00) << 8) | \ |
(((x) & 0x000000ff) << 24)) |
#define htonl(l) (lswap(l)) |
#define ntohl(l) (lswap(l)) |
#define htons(s) ((((s) >> 8) & 0xff) | \ |
(((s) << 8) & 0xff00)) |
#define ntohs(s) htons(s) |
|
// mac macros |
#define _MAC_ADDR_HIGH(a,b) ((a & 0xFF) << 8) | \ |
((b & 0xFF) << 0) |
#define _MAC_ADDR_LOW(a,b,c,d) ((a & 0xFF) << 24) | \ |
((b & 0xFF) << 16) | \ |
((c & 0xFF) << 8) | \ |
((d & 0xFF) << 0) |
// ip macro |
#define _IP_ADDR(a,b,c,d) ((a & 0xFF) << 24) | \ |
((b & 0xFF) << 16) | \ |
((c & 0xFF) << 8) | \ |
((d & 0xFF) << 0) |
|
// tbd |
typedef struct { |
// eth-tx routine |
int (*net_raw_send)(char *, int); |
// cfg |
u8 *mac_addr; |
u32 ip_addr; |
} net_if_t; |
|
// Ext: |
int net_init(tmemac_cfg_t *iv_tmemac_cfg, u32 pkt_tx, u32 pkt_rx); |
int net_input(char *buff); |
|
#ifdef __cplusplus |
} |
#endif// __cplusplus |
|
#endif // _NET_H_ |
/trunk/sw/dev/test_main/src/platform/platform.c
0,0 → 1,105
/****************************************************************************** |
* |
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. |
* |
* Permission is hereby granted, free of charge, to any person obtaining a copy |
* of this software and associated documentation files (the "Software"), to deal |
* in the Software without restriction, including without limitation the rights |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
* copies of the Software, and to permit persons to whom the Software is |
* furnished to do so, subject to the following conditions: |
* |
* The above copyright notice and this permission notice shall be included in |
* all copies or substantial portions of the Software. |
* |
* Use of the Software is limited solely to applications: |
* (a) running on a Xilinx device, or |
* (b) that interact with a Xilinx device through a bus or interconnect. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF |
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
* SOFTWARE. |
* |
* Except as contained in this notice, the name of the Xilinx shall not be used |
* in advertising or otherwise to promote the sale, use or other dealings in |
* this Software without prior written authorization from Xilinx. |
* |
******************************************************************************/ |
|
#include "xparameters.h" |
#include "xil_cache.h" |
|
#include "platform_config.h" |
|
/* |
* Uncomment one of the following two lines, depending on the target, |
* if ps7/psu init source files are added in the source directory for |
* compiling example outside of SDK. |
*/ |
/*#include "ps7_init.h"*/ |
/*#include "psu_init.h"*/ |
|
#ifdef STDOUT_IS_16550 |
#include "xuartns550_l.h" |
|
#define UART_BAUD 9600 |
#endif |
|
void |
enable_caches() |
{ |
#ifdef __PPC__ |
Xil_ICacheEnableRegion(CACHEABLE_REGION_MASK); |
Xil_DCacheEnableRegion(CACHEABLE_REGION_MASK); |
#elif __MICROBLAZE__ |
#ifdef XPAR_MICROBLAZE_USE_ICACHE |
Xil_ICacheEnable(); |
#endif |
#ifdef XPAR_MICROBLAZE_USE_DCACHE |
Xil_DCacheEnable(); |
#endif |
#endif |
} |
|
void |
disable_caches() |
{ |
Xil_DCacheDisable(); |
Xil_ICacheDisable(); |
} |
|
void |
init_uart() |
{ |
#ifdef STDOUT_IS_16550 |
XUartNs550_SetBaud(STDOUT_BASEADDR, XPAR_XUARTNS550_CLOCK_HZ, UART_BAUD); |
XUartNs550_SetLineControlReg(STDOUT_BASEADDR, XUN_LCR_8_DATA_BITS); |
#endif |
/* Bootrom/BSP configures PS7/PSU UART to 115200 bps */ |
} |
|
void |
init_platform() |
{ |
/* |
* If you want to run this example outside of SDK, |
* uncomment one of the following two lines and also #include "ps7_init.h" |
* or #include "ps7_init.h" at the top, depending on the target. |
* Make sure that the ps7/psu_init.c and ps7/psu_init.h files are included |
* along with this example source files for compilation. |
*/ |
/* ps7_init();*/ |
/* psu_init();*/ |
enable_caches(); |
init_uart(); |
} |
|
void |
cleanup_platform() |
{ |
disable_caches(); |
} |
/trunk/sw/dev/test_main/src/platform/platform.h
0,0 → 1,41
/****************************************************************************** |
* |
* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. |
* |
* Permission is hereby granted, free of charge, to any person obtaining a copy |
* of this software and associated documentation files (the "Software"), to deal |
* in the Software without restriction, including without limitation the rights |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
* copies of the Software, and to permit persons to whom the Software is |
* furnished to do so, subject to the following conditions: |
* |
* The above copyright notice and this permission notice shall be included in |
* all copies or substantial portions of the Software. |
* |
* Use of the Software is limited solely to applications: |
* (a) running on a Xilinx device, or |
* (b) that interact with a Xilinx device through a bus or interconnect. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF |
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
* SOFTWARE. |
* |
* Except as contained in this notice, the name of the Xilinx shall not be used |
* in advertising or otherwise to promote the sale, use or other dealings in |
* this Software without prior written authorization from Xilinx. |
* |
******************************************************************************/ |
|
#ifndef __PLATFORM_H_ |
#define __PLATFORM_H_ |
|
#include "platform_config.h" |
|
void init_platform(); |
void cleanup_platform(); |
|
#endif |
/trunk/sw/dev/test_main/src/platform/platform_config.h
0,0 → 1,4
#ifndef __PLATFORM_CONFIG_H_ |
#define __PLATFORM_CONFIG_H_ |
// ?? |
#endif |
/trunk/sw/dev/test_main/src/xil_lib/xil_lib.h
0,0 → 1,19
#ifndef _XIL_LIB_H_ |
#define _XIL_LIB_H_ |
|
|
// custom funct: |
void *xil_memset(void *s, int c, unsigned int count); |
void *xil_memmove(void *d, const void *s, unsigned int count); |
// libgloss (xil_malloc.c): |
#ifndef MSIM |
void *xil_malloc(unsigned int nbytes); |
void xil_free(void *ap); |
#else |
#include "stdlib.h" |
#define xil_malloc(x) malloc(x) |
#define xil_free(x) free(x) |
#endif // MSIM |
|
|
#endif // _XIL_LIB_H_ |
/trunk/sw/dev/test_main/src/xil_lib/xil_memmove.c
0,0 → 1,73
/* |
* tbd |
* |
*/ |
|
void *xil_memmove(void *d, const void *s, unsigned int count) |
{ |
unsigned long dst, src; |
|
if (!count) |
return d; |
|
if (d < s) { |
dst = (unsigned long) d; |
src = (unsigned long) s; |
|
if ((count < 8) || ((dst ^ src) & 3)) |
goto restup; |
|
if (dst & 1) { |
*(char *)dst++ = *(char *)src++; |
count--; |
} |
if (dst & 2) { |
*(short *)dst = *(short *)src; |
src += 2; |
dst += 2; |
count -= 2; |
} |
while (count > 3) { |
*(long *)dst = *(long *)src; |
src += 4; |
dst += 4; |
count -= 4; |
} |
restup: |
while (count--) |
*(char *)dst++ = *(char *)src++; |
} else { |
dst = (unsigned long) d + count; |
src = (unsigned long) s + count; |
|
if ((count < 8) || ((dst ^ src) & 3)) |
goto restdown; |
|
if (dst & 1) { |
src--; |
dst--; |
count--; |
*(char *)dst = *(char *)src; |
} |
if (dst & 2) { |
src -= 2; |
dst -= 2; |
count -= 2; |
*(short *)dst = *(short *)src; |
} |
while (count > 3) { |
src -= 4; |
dst -= 4; |
count -= 4; |
*(long *)dst = *(long *)src; |
} |
restdown: |
while (count--) { |
src--; |
dst--; |
*(char *)dst = *(char *)src; |
} |
} |
|
return d; |
} |
/trunk/sw/dev/test_main/src/xil_lib/xil_memset.c
0,0 → 1,20
/* |
* tbd |
* |
*/ |
|
void *xil_memset(void *s, int c, unsigned int count) |
{ |
|
if (!count) |
return s; |
|
c &= 0xFF; |
// |
char *xs = (char *) s; |
|
while (count--) |
*xs++ = c; |
return s; |
// |
} |
/trunk/sw/dev/test_main/src/Makefile
0,0 → 1,68
# |
# makefile |
# |
|
TARGET_NAME = test_main |
|
all: clean bsp_prep $(TARGET_NAME) |
|
CC = gcc |
CPP= g++ |
LD = g++ |
OBJDUMP = objdump |
DEFAULT_CP := cp -f |
DEFAULT_MKDIR := mkdir -p |
DEFAULT_RM := rm -rf |
BSP_ROOT_DIR := ../process/bsp_0/microblaze_0/include |
BSP_COSIM_DIR := ./_hdl/bsp |
|
INCDIR := ./ \ |
/usr/local/modelsim/modelsim_dlx/include \ |
./_hdl/dpi \ |
./_hdl/bsp \ |
./_hdl/bsp/include \ |
./_hdl/bsp/libsrc/axidma_v9_0/src \ |
./xil_lib \ |
./net \ |
../../../../hw/src/rtl/tri_mode_emac/sw/src |
|
|
INCLUDE := $(addprefix -I, $(INCDIR)) |
CFLAGS := -DMSIM |
CFLAGS += -g |
CFLAGS += -rdynamic |
CFLAGS += $(INCLUDE) |
|
C_SRCS := $(wildcard ./_hdl/dpi/*.c) |
C_SRCS += $(wildcard ./_hdl/bsp/libsrc/standalone_v5_3/src/*.c) |
C_SRCS += $(wildcard ./_hdl/bsp/libsrc/axidma_v9_0/src/*.c) |
C_SRCS += $(wildcard ../../../../hw/src/rtl/tri_mode_emac/sw/src/*.c) |
C_SRCS += $(wildcard ./xil_lib/*.c) |
C_SRCS += $(wildcard ./net/*.c) |
C_SRCS += $(wildcard ./main/*.c) |
|
OBJFILE_C := $(patsubst %.c,%.o, $(C_SRCS)) |
|
|
$(TARGET_NAME): $(OBJFILE_C) |
@echo C_SRCS: $(C_SRCS) |
$(LD) -shared -o $(TARGET_NAME).so $(notdir $^) $(LDFLAGS) $(LIBRARIES) |
$(OBJDUMP) -S -d $(TARGET_NAME).so > $(TARGET_NAME).objdump |
rm -f *.o *~ core |
rm -f *.d *~ core |
@echo DONE: so-lib DPI-C |
|
%.o: %.c |
@echo Compiling $<: |
$(CC) $(CFLAGS) $(LIBRARIES) -fPIC -c $< |
|
clean: |
@echo clean: |
$(DEFAULT_RM) $(BSP_COSIM_DIR)/xparameters.h |
$(DEFAULT_RM) *.objdump |
$(DEFAULT_RM) $(TARGET_NAME).so |
|
bsp_prep: |
@echo bsp_prep: |
$(DEFAULT_RM) $(BSP_COSIM_DIR)/xparameters.h |
$(DEFAULT_CP) $(BSP_ROOT_DIR)/xparameters.h $(BSP_COSIM_DIR) |
/trunk/sw/dev/test_main/process.sh
0,0 → 1,26
#!/bin/bash |
|
# USAGE: ./process.sh |
# ARGs: |
# <none> |
|
# clr |
rm -rf *.jou |
rm -rf *.log |
rm -rf process |
if [ "$1" == "-clr" ]; then |
exit 0 |
fi |
|
# cre |
mkdir process |
cd process |
|
# prj-hwdef |
vivado -mode batch -source ../source_hwdef.tcl |
|
# prj-run |
xsdk -batch -source ../source_xsdk.tcl $1 |
|
# Final |
exit 0 |
/trunk/sw/dev/test_main/source_hwdef.tcl
0,0 → 1,5
open_project ../../../../hw/layout/process/project_n1.xpr |
update_compile_order -fileset sources_1 |
generate_target all [get_files ../../../../hw/layout/process/project_n1.srcs/sources_1/bd/bd/base_microblaze_design.bd] |
write_hwdef -force -file ./base_microblaze_design_wrapper.hdf |
close_project |
/trunk/sw/dev/test_main/source_xsdk.tcl
0,0 → 1,13
sdk set_workspace ./ |
#sdk set_user_repo_path ./src |
sdk create_hw_project -name hw_0 -hwspec ./base_microblaze_design_wrapper.hdf |
sdk create_bsp_project -name bsp_0 -proc microblaze_0 -hwproject hw_0 -os standalone |
sdk create_app_project -name app_0 -proc microblaze_0 -hwproject hw_0 -bsp bsp_0 -os standalone -app {Empty Application} |
sdk import_sources -name app_0 -path ../src/platform |
sdk import_sources -name app_0 -path ../src/xil_lib |
sdk import_sources -name app_0 -path ../src/net |
sdk import_sources -name app_0 -path ../src/main |
|
if {[lindex $argv 0] != "-bsp"} { |
sdk build_project |
} |
/trunk/process.sh
0,0 → 1,90
#!/bin/bash |
|
# USAGE: ./process.sh |
# ARGs: |
# <none> |
# -clr |
# -arch |
# -bit |
# -elf |
# -cp |
# |
|
ROOT_DIR=$PWD |
CP_DIR=~/vbox_share/WORK/Xilinx/upld |
|
function run_clr { |
echo "CLR:" |
|
cd $ROOT_DIR/hw/layout |
./process.sh -clr &> /dev/null |
|
cd $ROOT_DIR/hw/msim |
./process.sh -clr &> /dev/null |
|
cd $ROOT_DIR/sw/dev/test_main |
./process.sh -clr &> /dev/null |
make clean -C $ROOT_DIR/sw/dev/test_bfm &> /dev/null |
make clean -C $ROOT_DIR/sw/dev/test_main/src &> /dev/null |
make clean -C $ROOT_DIR/sw/app/gtest &> /dev/null |
} |
|
function run_arch { |
echo "ARCH:" |
cd $ROOT_DIR/../ |
tar cfJ vtest_$(date +"%Y-%m-%d_%H-%M-%S").tar.xz vtest &> /dev/null |
echo "=> done" |
} |
|
function run_bit { |
echo "BIT:" |
cd $ROOT_DIR/hw/layout |
./process.sh |
} |
|
function run_elf { |
echo "ELF:" |
cd $ROOT_DIR/sw/dev/test_main |
./process.sh |
} |
|
function run_cp { |
echo "CP:" |
local BIT_LIST=`find ./hw/layout/process/project_n1.runs/impl_1/*.bit` |
local BIT_FILE=${BIT_LIST[0]} |
local ELF_LIST=`find ./sw/dev/test_main/process/app_0/Debug/*.elf` |
local ELF_FILE=${ELF_LIST[0]} |
local HDF_LIST=`find ./sw/dev/test_main/process/*.hdf` |
local HDF_FILE=${HDF_LIST[0]} |
|
rm -rf $CP_DIR/*.bit |
rm -rf $CP_DIR/*.elf |
rm -rf $CP_DIR/*.hdf |
|
cp $BIT_FILE $CP_DIR |
cp $ELF_FILE $CP_DIR |
cp $HDF_FILE $CP_DIR |
} |
|
echo "START: $(date)" |
# proc NO-ARG |
if [ "$1" == "" ]; then |
run_clr |
run_bit |
run_elf |
fi |
# proc 1ST-ARG |
if [ "$1" == "-clr" ]; then run_clr ; fi |
if [ "$1" == "-arch" ]; then run_arch ; fi |
if [ "$1" == "-bit" ]; then run_bit ; fi |
if [ "$1" == "-elf" ]; then run_elf ; fi |
if [ "$1" == "-cp" ]; then run_cp ; fi |
# proc 2ND-ARG |
if [ "$2" == "-arch" ]; then run_arch ; fi |
if [ "$2" == "-bit" ]; then run_bit ; fi |
if [ "$2" == "-elf" ]; then run_elf ; fi |
if [ "$2" == "-cp" ]; then run_cp ; fi |
echo "STOP : $(date)" |
|
# Final |
exit 0 |