OpenCores
URL https://opencores.org/ocsvn/1g_ethernet_dpi/1g_ethernet_dpi/trunk

Subversion Repositories 1g_ethernet_dpi

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    /1g_ethernet_dpi
    from Rev 6 to Rev 7
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  •

Rev 6 → Rev 7

/tags/vmblite_base/hw/layout/tcl/vgsim.tcl
0,0 → 1,14
 
open_project ./project_n1.xpr
 
config_webtalk -user off
 
update_compile_order -fileset sources_1
update_compile_order -fileset sim_1
 
open_run impl_1
write_verilog -force -mode timesim -sdf_anno true -sdf_file project_n1.sdf project_n1_impl_timing.v
#write_verilog -force -mode timesim -sdf_file project_n1.sdf project_n1_impl_timing.v
write_sdf project_n1.sdf
 
close_project
/tags/vmblite_base/hw/layout/tcl/vrun.tcl
0,0 → 1,12
 
open_project ./project_n1.xpr
 
config_webtalk -user off
 
update_compile_order -fileset sources_1
update_compile_order -fileset sim_1
 
launch_runs impl_1 -to_step write_bitstream
wait_on_run impl_1
 
close_project
/tags/vmblite_base/hw/layout/tcl/vsetup.tcl
0,0 → 1,50
 
create_project project_n1 ./ -part xc7k325tffg900-2
 
set obj [get_projects project_n1]
 
set_property "board_part" "xilinx.com:kc705:part0:1.2" $obj
set_property "default_lib" "mblite" $obj
set_property "sim.ip.auto_export_scripts" "1" $obj
set_property "simulator_language" "Mixed" $obj
set_property "target_language" "Verilog" $obj
set_property "target_simulator" "ModelSim" $obj
 
add_files -norecurse ../xdc/project_n1_b.sdc
add_files -norecurse ../xdc/project_n1_p.sdc
add_files -norecurse ../xdc/project_n1_t.sdc
 
add_files -norecurse ../../src/rtl/mblite_top.sv
add_files -norecurse ../../src/rtl/mblite_soc.sv
add_files -norecurse ../../src/rtl/misc/clk_module.sv
add_files -norecurse ../../src/rtl/misc/por_module.sv
add_files -norecurse ../../src/rtl/misc/rst_sync.sv
add_files -norecurse ../../src/rtl/wb_pio/hdl/wb_pio_top.sv
add_files -norecurse ../../src/rtl/wb_uart/hdl/async.v
add_files -norecurse ../../src/rtl/wb_uart/hdl/wb_uart_mscfifo.v
add_files -norecurse ../../src/rtl/wb_uart/hdl/wb_uart_sdpram.v
add_files -norecurse ../../src/rtl/wb_uart/hdl/wb_uart_slv.sv
add_files -norecurse ../../src/rtl/wb_uart/hdl/wb_uart_top.sv
add_files -norecurse ../../src/rtl/mblite/config_Pkg.vhd
add_files -norecurse ../../src/rtl/mblite/std/std_Pkg.vhd
add_files -norecurse ../../src/rtl/mblite/std/dsram.vhd
add_files -norecurse ../../src/rtl/mblite/std/sram.vhd
add_files -norecurse ../../src/rtl/mblite/std/sram_4en.vhd
add_files -norecurse ../../src/rtl/mblite/core/core_Pkg.vhd
add_files -norecurse ../../src/rtl/mblite/core/core.vhd
add_files -norecurse ../../src/rtl/mblite/core/core_address_decoder.vhd
add_files -norecurse ../../src/rtl/mblite/core/core_wb_adapter.vhd
add_files -norecurse ../../src/rtl/mblite/core/decode.vhd
add_files -norecurse ../../src/rtl/mblite/core/execute.vhd
add_files -norecurse ../../src/rtl/mblite/core/fetch.vhd
add_files -norecurse ../../src/rtl/mblite/core/gprf.vhd
add_files -norecurse ../../src/rtl/mblite/core/mem.vhd
add_files -norecurse ../../src/rtl/mblite/mblite_unit.vhd
 
set obj [get_filesets sources_1]
set_property "top" "mblite_top" $obj
 
update_compile_order -fileset sources_1
update_compile_order -fileset sim_1
 
close_project
/tags/vmblite_base/hw/layout/xdc/project_n1_b.sdc
0,0 → 1,2
# bit
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]
/tags/vmblite_base/hw/layout/xdc/project_n1_p.sdc
0,0 → 1,36
# clk
set_property LOC AD12 [ get_ports sys_diff_clock_clk_p]
set_property IOSTANDARD DIFF_SSTL15 [ get_ports sys_diff_clock_clk_p]
# ext-rst
#set_property LOC AB7 [ get_ports glbl_rst]
#set_property IOSTANDARD LVCMOS15 [ get_ports glbl_rst]
# led
set_property LOC AB8 [ get_ports led_8bits_tri_o[0]]
set_property IOSTANDARD LVCMOS15 [ get_ports led_8bits_tri_o[0]]
 
set_property LOC AA8 [ get_ports led_8bits_tri_o[1]]
set_property IOSTANDARD LVCMOS15 [ get_ports led_8bits_tri_o[1]]
 
set_property LOC AC9 [ get_ports led_8bits_tri_o[2]]
set_property IOSTANDARD LVCMOS15 [ get_ports led_8bits_tri_o[2]]
 
set_property LOC AB9 [ get_ports led_8bits_tri_o[3]]
set_property IOSTANDARD LVCMOS15 [ get_ports led_8bits_tri_o[3]]
 
set_property LOC AE26 [ get_ports led_8bits_tri_o[4]]
set_property IOSTANDARD LVCMOS25 [ get_ports led_8bits_tri_o[4]]
 
set_property LOC G19 [ get_ports led_8bits_tri_o[5]]
set_property IOSTANDARD LVCMOS25 [ get_ports led_8bits_tri_o[5]]
 
set_property LOC E18 [ get_ports led_8bits_tri_o[6]]
set_property IOSTANDARD LVCMOS25 [ get_ports led_8bits_tri_o[6]]
 
set_property LOC F16 [ get_ports led_8bits_tri_o[7]]
set_property IOSTANDARD LVCMOS25 [ get_ports led_8bits_tri_o[7]]
# uart
set_property LOC M19 [ get_ports rs232_uart_rxd]
set_property IOSTANDARD LVCMOS25 [ get_ports rs232_uart_rxd]
 
set_property LOC K24 [ get_ports rs232_uart_txd]
set_property IOSTANDARD LVCMOS25 [ get_ports rs232_uart_txd]
/tags/vmblite_base/hw/layout/xdc/project_n1_t.sdc
0,0 → 1,3
# clk
create_clock -name sys_clk_pin -period "5.0" [get_ports "sys_diff_clock_clk_p"]
set_input_jitter sys_clk_pin 0.050
/tags/vmblite_base/hw/layout/process.sh
0,0 → 1,57
#!/bin/bash
 
# USAGE: ./process.sh
# ARGs:
# <none>
# -o
# -clr
# -asm
# -gsim
 
# gui-open
if [ "$1" == "-o" ]; then
cd process
vivado ./project_n1.xpr
exit 0
fi
 
# gate-sim
if [ "$1" == "-gsim" ]; then
cd process
vivado -mode batch -source ../tcl/vgsim.tcl
exit 0
fi
 
# clr
rm -rf .Xil
rm -rf process
rm -rf *.jou
rm -rf *.log
rm -rf ../src/rtl/mblite/std/*.mem
if [ "$1" == "-clr" ]; then
exit 0
fi
 
# prep
mkdir process
cd process
if [ ! -d ../../../sw/test_main/_bmm ]; then
cmd="make -C ../../../sw/test_main"
$cmd &> mbl-main.log || {
echo "test_main MAKE failed"
exit 1
}
fi
cp -f ../../../sw/test_main/_bmm/*.mem ../../src/rtl/mblite/std
 
# prj-cre
vivado -mode batch -source ../tcl/vsetup.tcl
if [ "$1" == "-asm" ]; then
exit 0
fi
 
# prj-asm
vivado -mode batch -source ../tcl/vrun.tcl
 
# Final
exit 0
/tags/vmblite_base/hw/msim/process.sh
0,0 → 1,83
#!/bin/bash
#
# USAGE: ./process.sh
# ARGs:
# <none>
# -clr
# -reasm
# -fast
 
 
GATE_SIM=0
#GATE_SIM=1
#GATE_SIM=2
ROOT_DIR=$PWD
 
#
# view
if [ "$1" == "-view" ]; then
vsim -view vsim.wlf -do wave.do
exit 0
fi
 
#
# clr
rm -rf work
rm -rf mblite
rm -rf *.h
rm -rf *.tr
rm -rf *wlf*
rm -rf *.hex
rm -rf *.mem
rm -rf *.ver
rm -rf *.so
rm -rf *.log
rm -rf *.pcap
rm -rf *.vstf
rm -rf *.ini
rm -rf *.v
rm -rf *.sdf
rm -rf *transcript*
if [ "$1" == "-clr" ]; then
exit 0
fi
 
# deal with GATE-LEVEL sim
if [ ! -d ../../sw/test_main/_bmm ] || [ "$1" == "-reasm" ]; then
cmd="make -C ../../sw/test_main/"
$cmd &> mbl-main.log || {
echo "test_main MAKE failed"
exit 1
}
fi
if [ $GATE_SIM == 0 ]; then
cp -f ../../sw/test_main/_bmm/*.mem ./
fi
 
#
if [ $GATE_SIM != 0 ]; then
cd $ROOT_DIR/../layout
if [ ! -d ./process ]; then
./process.sh &> /dev/null
fi
./process.sh -gsim &> /dev/null
cd $ROOT_DIR
mv -f ../layout/process/*.sdf ./
mv -f ../layout/process/*.v ./
fi
 
 
# start
export GATE_SIM=$GATE_SIM
if [ "$1" == "-fast" ] || [ "$2" == "-fast" ]
then
export FAST_SIM=1
vsim -c -do start_sim.tcl
else
export FAST_SIM=0
vsim -do start_sim.tcl
fi
 
#
#Final
exit 0
/tags/vmblite_base/hw/msim/start_sim.tcl
0,0 → 1,55
#
quit -sim
 
#
quietly set SYS_PATH "~/Xilinx/Vivado/2015.4/data/verilog/src"
 
# cfg-env
quietly set FAST_SIM $::env(FAST_SIM)
quietly set GATE_SIM $::env(GATE_SIM)
 
#
if { [file exists "work"] } { file delete -force "work" }
vlib work
if { [file exists "mblite"] } { file delete -force "mblite" }
vlib mblite
 
#
if { $GATE_SIM > 0 } {
vlog -quiet *.v
} else {
vlog -quiet -work work $SYS_PATH/glbl.v
 
vcom -quiet -work mblite -f vcom_synth.f
vlog -quiet -sv -work work -f vlog_synth.f
}
#
if { $GATE_SIM > 0 } {
vlog -quiet -sv -work work +define+GATE_LEVEL=1 -f vlog_sim.f
} else {
vlog -quiet -sv -work work -f vlog_sim.f
}
 
# sim
if { $GATE_SIM == 1 } {
vsim -t ps -L secureip -L simprims_ver work.testcase work.glbl
log -r /*
do wave.do
} elseif { $GATE_SIM == 2 } {
vsim -novopt +sdf_verbose -t 1ps +transport_int_delays +pulse_r/0 +pulse_int_r/0 -L simprims_ver -L secureip -L mblite work.testcase work.glbl
log -r /*
do wave.do
} else {
if { $FAST_SIM == 1 } {
vsim -quiet -t ps -L unisims_ver -L mblite work.testcase work.glbl
} else {
vsim -novopt -t ps -L unisims_ver -L mblite work.testcase work.glbl
 
log -r /*
do wave.do
}
}
quietly set StdArithNoWarnings 1
quietly set NumericStdNoWarnings 1
 
run -all
/tags/vmblite_base/hw/msim/vcom_synth.f
0,0 → 1,15
../src/rtl/mblite/config_Pkg.vhd
../src/rtl/mblite/std/std_Pkg.vhd
../src/rtl/mblite/std/dsram.vhd
../src/rtl/mblite/std/sram.vhd
../src/rtl/mblite/std/sram_4en.vhd
../src/rtl/mblite/core/core_Pkg.vhd
../src/rtl/mblite/core/core.vhd
../src/rtl/mblite/core/core_address_decoder.vhd
../src/rtl/mblite/core/core_wb_adapter.vhd
../src/rtl/mblite/core/decode.vhd
../src/rtl/mblite/core/execute.vhd
../src/rtl/mblite/core/fetch.vhd
../src/rtl/mblite/core/gprf.vhd
../src/rtl/mblite/core/mem.vhd
../src/rtl/mblite/mblite_unit.vhd
/tags/vmblite_base/hw/msim/vlog_sim.f
0,0 → 1,4
../src/tb/uart_rx_if.sv
../src/tb/tb.sv
 
../src/tc/testcase.sv
/tags/vmblite_base/hw/msim/vlog_synth.f
0,0 → 1,14
../src/rtl/mblite_top.sv
../src/rtl/mblite_soc.sv
 
../src/rtl/misc/clk_module.sv
../src/rtl/misc/por_module.sv
../src/rtl/misc/rst_sync.sv
../src/rtl/wb_pio/hdl/wb_pio_top.sv
 
../src/rtl/wb_uart/hdl/async.v
../src/rtl/wb_uart/hdl/wb_uart_mscfifo.v
../src/rtl/wb_uart/hdl/wb_uart_sdpram.v
../src/rtl/wb_uart/hdl/wb_uart_slv.sv
../src/rtl/wb_uart/hdl/wb_uart_top.sv
/tags/vmblite_base/hw/msim/wave.do
0,0 → 1,66
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /testcase/tb/dut/s_clk_200
add wave -noupdate /testcase/tb/dut/s_clk_50
add wave -noupdate /testcase/tb/dut/U_POR/o_por
add wave -noupdate /testcase/tb/dut/u0/i_clk_50
add wave -noupdate /testcase/tb/dut/u0/i_arst
add wave -noupdate -expand -group dut.IO /testcase/tb/dut/led_8bits_tri_o
add wave -noupdate -expand -group dut.IO /testcase/tb/dut/rs232_uart_rxd
add wave -noupdate -expand -group dut.IO /testcase/tb/dut/rs232_uart_txd
add wave -noupdate -divider {New Divider}
add wave -noupdate -group dut.soc.pu.MBL-WBM.IF /testcase/tb/dut/u0/U_MBLITE/wbm_dat_i
add wave -noupdate -group dut.soc.pu.MBL-WBM.IF /testcase/tb/dut/u0/U_MBLITE/wbm_ack_i
add wave -noupdate -group dut.soc.pu.MBL-WBM.IF /testcase/tb/dut/u0/U_MBLITE/wbm_adr_o
add wave -noupdate -group dut.soc.pu.MBL-WBM.IF /testcase/tb/dut/u0/U_MBLITE/wbm_dat_o
add wave -noupdate -group dut.soc.pu.MBL-WBM.IF /testcase/tb/dut/u0/U_MBLITE/wbm_we_o
add wave -noupdate -group dut.soc.pu.MBL-WBM.IF /testcase/tb/dut/u0/U_MBLITE/wbm_stb_o
add wave -noupdate -group dut.soc.pu.MBL-WBM.IF /testcase/tb/dut/u0/U_MBLITE/wbm_sel_o
add wave -noupdate -group dut.soc.pu.MBL-WBM.IF /testcase/tb/dut/u0/U_MBLITE/wbm_cyc_o
add wave -noupdate -group dut.soc.pu.imem.IF /testcase/tb/dut/u0/U_MBLITE/imem/dat_o
add wave -noupdate -group dut.soc.pu.imem.IF /testcase/tb/dut/u0/U_MBLITE/imem/dat_i
add wave -noupdate -group dut.soc.pu.imem.IF /testcase/tb/dut/u0/U_MBLITE/imem/adr_i
add wave -noupdate -group dut.soc.pu.imem.IF /testcase/tb/dut/u0/U_MBLITE/imem/wre_i
add wave -noupdate -group dut.soc.pu.imem.IF /testcase/tb/dut/u0/U_MBLITE/imem/ena_i
add wave -noupdate -group dut.soc.pu.imem.IF /testcase/tb/dut/u0/U_MBLITE/imem/clk_i
add wave -noupdate -group dut.soc.pu.dmem.IF /testcase/tb/dut/u0/U_MBLITE/dmem/dat_o
add wave -noupdate -group dut.soc.pu.dmem.IF /testcase/tb/dut/u0/U_MBLITE/dmem/dat_i
add wave -noupdate -group dut.soc.pu.dmem.IF /testcase/tb/dut/u0/U_MBLITE/dmem/adr_i
add wave -noupdate -group dut.soc.pu.dmem.IF /testcase/tb/dut/u0/U_MBLITE/dmem/wre_i
add wave -noupdate -group dut.soc.pu.dmem.IF /testcase/tb/dut/u0/U_MBLITE/dmem/ena_i
add wave -noupdate -group dut.soc.pu.dmem.IF /testcase/tb/dut/u0/U_MBLITE/dmem/clk_i
add wave -noupdate -group dut.soc.PIO.WBS /testcase/tb/dut/u0/U_PIO/iv_wbs_adr
add wave -noupdate -group dut.soc.PIO.WBS /testcase/tb/dut/u0/U_PIO/iv_wbs_dat
add wave -noupdate -group dut.soc.PIO.WBS /testcase/tb/dut/u0/U_PIO/i_wbs_we
add wave -noupdate -group dut.soc.PIO.WBS /testcase/tb/dut/u0/U_PIO/i_wbs_stb
add wave -noupdate -group dut.soc.PIO.WBS /testcase/tb/dut/u0/U_PIO/iv_wbs_sel
add wave -noupdate -group dut.soc.PIO.WBS /testcase/tb/dut/u0/U_PIO/i_wbs_cyc
add wave -noupdate -group dut.soc.PIO.WBS /testcase/tb/dut/u0/U_PIO/ov_wbs_dat
add wave -noupdate -group dut.soc.PIO.WBS /testcase/tb/dut/u0/U_PIO/o_wbs_ack
add wave -noupdate -expand -group dut.soc.UART.WBS /testcase/tb/dut/u0/U_UART/iv_wbs_adr
add wave -noupdate -expand -group dut.soc.UART.WBS /testcase/tb/dut/u0/U_UART/iv_wbs_dat
add wave -noupdate -expand -group dut.soc.UART.WBS /testcase/tb/dut/u0/U_UART/i_wbs_we
add wave -noupdate -expand -group dut.soc.UART.WBS /testcase/tb/dut/u0/U_UART/i_wbs_stb
add wave -noupdate -expand -group dut.soc.UART.WBS /testcase/tb/dut/u0/U_UART/iv_wbs_sel
add wave -noupdate -expand -group dut.soc.UART.WBS /testcase/tb/dut/u0/U_UART/i_wbs_cyc
add wave -noupdate -expand -group dut.soc.UART.WBS /testcase/tb/dut/u0/U_UART/ov_wbs_dat
add wave -noupdate -expand -group dut.soc.UART.WBS /testcase/tb/dut/u0/U_UART/o_wbs_ack
add wave -noupdate -divider {New Divider}
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {641014064 ps} 0}
quietly wave cursor active 1
configure wave -namecolwidth 324
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {871613675 ps} {5474257175 ps}
/tags/vmblite_base/hw/src/rtl/mblite/core/core.vhd
0,0 → 1,156
----------------------------------------------------------------------------------------------
--
-- Input file : core.vhd
-- Design name : core
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Top level entity of the integer unit
--
--
----------------------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
 
entity core is generic
(
G_INTERRUPT : boolean := CFG_INTERRUPT;
G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
G_USE_BARREL : boolean := CFG_USE_BARREL;
G_DEBUG : boolean := CFG_DEBUG
);
port
(
imem_o : out imem_out_type;
dmem_o : out dmem_out_type;
imem_i : in imem_in_type;
dmem_i : in dmem_in_type;
int_i : in std_logic;
rst_i : in std_logic;
clk_i : in std_logic
);
end core;
 
architecture arch of core is
 
signal fetch_i : fetch_in_type;
signal fetch_o : fetch_out_type;
 
signal decode_i : decode_in_type;
signal decode_o : decode_out_type;
 
signal gprf_o : gprf_out_type;
 
signal exec_i : execute_in_type;
signal exec_o : execute_out_type;
 
signal mem_i : mem_in_type;
signal mem_o : mem_out_type;
 
signal ena_i : std_logic;
 
begin
 
ena_i <= dmem_i.ena_i;
 
fetch_i.hazard <= decode_o.hazard;
fetch_i.branch <= exec_o.branch;
fetch_i.branch_target <= exec_o.alu_result(CFG_IMEM_SIZE - 1 downto 0);
 
fetch0 : fetch port map
(
fetch_o => fetch_o,
imem_o => imem_o,
fetch_i => fetch_i,
rst_i => rst_i,
ena_i => ena_i,
clk_i => clk_i
);
 
decode_i.program_counter <= fetch_o.program_counter;
decode_i.instruction <= imem_i.dat_i;
decode_i.ctrl_wrb <= mem_o.ctrl_wrb;
decode_i.ctrl_mem_wrb <= mem_o.ctrl_mem_wrb;
decode_i.mem_result <= dmem_i.dat_i;
decode_i.alu_result <= mem_o.alu_result;
decode_i.interrupt <= int_i;
decode_i.flush_id <= exec_o.flush_id;
 
decode0: decode generic map
(
G_INTERRUPT => G_INTERRUPT,
G_USE_HW_MUL => G_USE_HW_MUL,
G_USE_BARREL => G_USE_BARREL,
G_DEBUG => G_DEBUG
)
port map
(
decode_o => decode_o,
decode_i => decode_i,
gprf_o => gprf_o,
ena_i => ena_i,
rst_i => rst_i,
clk_i => clk_i
);
 
exec_i.fwd_dec <= decode_o.fwd_dec;
exec_i.fwd_dec_result <= decode_o.fwd_dec_result;
 
exec_i.dat_a <= gprf_o.dat_a_o;
exec_i.dat_b <= gprf_o.dat_b_o;
exec_i.dat_d <= gprf_o.dat_d_o;
exec_i.reg_a <= decode_o.reg_a;
exec_i.reg_b <= decode_o.reg_b;
 
exec_i.imm <= decode_o.imm;
exec_i.program_counter <= decode_o.program_counter;
exec_i.ctrl_wrb <= decode_o.ctrl_wrb;
exec_i.ctrl_mem <= decode_o.ctrl_mem;
exec_i.ctrl_ex <= decode_o.ctrl_ex;
 
exec_i.fwd_mem <= mem_o.ctrl_wrb;
exec_i.mem_result <= dmem_i.dat_i;
exec_i.alu_result <= mem_o.alu_result;
exec_i.ctrl_mem_wrb <= mem_o.ctrl_mem_wrb;
 
execute0 : execute generic map
(
G_USE_HW_MUL => G_USE_HW_MUL,
G_USE_BARREL => G_USE_BARREL
)
port map
(
exec_o => exec_o,
exec_i => exec_i,
ena_i => ena_i,
rst_i => rst_i,
clk_i => clk_i
);
 
mem_i.alu_result <= exec_o.alu_result;
mem_i.program_counter <= exec_o.program_counter;
mem_i.branch <= exec_o.branch;
mem_i.dat_d <= exec_o.dat_d;
mem_i.ctrl_wrb <= exec_o.ctrl_wrb;
mem_i.ctrl_mem <= exec_o.ctrl_mem;
mem_i.mem_result <= dmem_i.dat_i;
 
mem0 : mem port map
(
mem_o => mem_o,
dmem_o => dmem_o,
mem_i => mem_i,
ena_i => ena_i,
rst_i => rst_i,
clk_i => clk_i
);
 
end arch;
/tags/vmblite_base/hw/src/rtl/mblite/core/core_Pkg.vhd
0,0 → 1,451
----------------------------------------------------------------------------------------------
--
-- Input file : core_Pkg.vhd
-- Design name : core_Pkg
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Package with components and type definitions for the interface
-- of the components
--
--
----------------------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
library mblite;
use mblite.config_Pkg.all;
use mblite.std_Pkg.all;
 
package core_Pkg is
 
constant C_8_ZEROS : std_logic_vector ( 7 downto 0) := (others => '0');
constant C_16_ZEROS : std_logic_vector (15 downto 0) := (others => '0');
constant C_24_ZEROS : std_logic_vector (23 downto 0) := (others => '0');
constant C_32_ZEROS : std_logic_vector (31 downto 0) := (others => '0');
----------------------------------------------------------------------------------------------
-- TYPES USED IN MB-LITE
----------------------------------------------------------------------------------------------
 
type alu_operation is (ALU_ADD, ALU_OR, ALU_AND, ALU_XOR, ALU_SHIFT, ALU_SEXT8, ALU_SEXT16, ALU_MUL, ALU_BS);
type src_type_a is (ALU_SRC_REGA, ALU_SRC_NOT_REGA, ALU_SRC_PC, ALU_SRC_ZERO);
type src_type_b is (ALU_SRC_REGB, ALU_SRC_NOT_REGB, ALU_SRC_IMM, ALU_SRC_NOT_IMM);
type carry_type is (CARRY_ZERO, CARRY_ONE, CARRY_ALU, CARRY_ARITH);
type carry_keep_type is (CARRY_NOT_KEEP, CARRY_KEEP);
type branch_condition is (NOP, BNC, BEQ, BNE, BLT, BLE, BGT, BGE);
type transfer_size is (WORD, HALFWORD, BYTE);
 
type ctrl_execution is record
alu_op : alu_operation;
alu_src_a : src_type_a;
alu_src_b : src_type_b;
operation : std_logic;
carry : carry_type;
carry_keep : carry_keep_type;
branch_cond : branch_condition;
delay : std_logic;
end record;
 
type ctrl_memory is record
mem_write : std_logic;
mem_read : std_logic;
transfer_size : transfer_size;
end record;
 
type ctrl_memory_writeback_type is record
mem_read : std_logic;
transfer_size : transfer_size;
end record;
 
type forward_type is record
reg_d : std_logic_vector(CFG_GPRF_SIZE - 1 downto 0);
reg_write : std_logic;
end record;
 
type imem_in_type is record
dat_i : std_logic_vector(CFG_IMEM_WIDTH - 1 downto 0);
end record;
 
type imem_out_type is record
adr_o : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
ena_o : std_logic;
end record;
 
type fetch_in_type is record
hazard : std_logic;
branch : std_logic;
branch_target : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
end record;
 
type fetch_out_type is record
program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
end record;
 
type gprf_out_type is record
dat_a_o : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
dat_b_o : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
dat_d_o : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
end record;
 
type decode_in_type is record
program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
instruction : std_logic_vector(CFG_IMEM_WIDTH - 1 downto 0);
ctrl_wrb : forward_type;
ctrl_mem_wrb : ctrl_memory_writeback_type;
mem_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
alu_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
interrupt : std_logic;
flush_id : std_logic;
end record;
 
type decode_out_type is record
reg_a : std_logic_vector(CFG_GPRF_SIZE - 1 downto 0);
reg_b : std_logic_vector(CFG_GPRF_SIZE - 1 downto 0);
imm : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
hazard : std_logic;
ctrl_ex : ctrl_execution;
ctrl_mem : ctrl_memory;
ctrl_wrb : forward_type;
fwd_dec_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
fwd_dec : forward_type;
end record;
 
type gprf_in_type is record
adr_a_i : std_logic_vector(CFG_GPRF_SIZE - 1 downto 0);
adr_b_i : std_logic_vector(CFG_GPRF_SIZE - 1 downto 0);
adr_d_i : std_logic_vector(CFG_GPRF_SIZE - 1 downto 0);
dat_w_i : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
adr_w_i : std_logic_vector(CFG_GPRF_SIZE - 1 downto 0);
wre_i : std_logic;
end record;
 
type execute_out_type is record
alu_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
dat_d : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
branch : std_logic;
program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
flush_id : std_logic;
ctrl_mem : ctrl_memory;
ctrl_wrb : forward_type;
end record;
 
type execute_in_type is record
reg_a : std_logic_vector(CFG_GPRF_SIZE - 1 downto 0);
dat_a : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
reg_b : std_logic_vector(CFG_GPRF_SIZE - 1 downto 0);
dat_b : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
dat_d : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
imm : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
fwd_dec : forward_type;
fwd_dec_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
fwd_mem : forward_type;
ctrl_ex : ctrl_execution;
ctrl_mem : ctrl_memory;
ctrl_wrb : forward_type;
ctrl_mem_wrb : ctrl_memory_writeback_type;
mem_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
alu_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
 
end record;
 
type mem_in_type is record
dat_d : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
alu_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
mem_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
branch : std_logic;
ctrl_mem : ctrl_memory;
ctrl_wrb : forward_type;
end record;
 
type mem_out_type is record
alu_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
ctrl_wrb : forward_type;
ctrl_mem_wrb : ctrl_memory_writeback_type;
end record;
 
type dmem_in_type is record
dat_i : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
ena_i : std_logic;
end record;
 
type dmem_out_type is record
dat_o : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
adr_o : std_logic_vector(CFG_DMEM_SIZE - 1 downto 0);
sel_o : std_logic_vector(3 downto 0);
we_o : std_logic;
ena_o : std_logic;
end record;
 
type dmem_in_array_type is array(natural range <>) of dmem_in_type;
type dmem_out_array_type is array(natural range <>) of dmem_out_type;
 
-- WB-master inputs from the wb-slaves
type wb_mst_in_type is record
clk_i : std_logic; -- master clock input
rst_i : std_logic; -- synchronous active high reset
dat_i : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0); -- databus input
ack_i : std_logic; -- buscycle acknowledge input
int_i : std_logic; -- interrupt request input
end record;
 
-- WB-master outputs to the wb-slaves
type wb_mst_out_type is record
adr_o : std_logic_vector(CFG_DMEM_SIZE - 1 downto 0); -- address bits
dat_o : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0); -- databus output
we_o : std_logic; -- write enable output
stb_o : std_logic; -- strobe signals
sel_o : std_logic_vector(3 downto 0); -- select output array
cyc_o : std_logic; -- valid BUS cycle output
end record;
 
-- WB-slave inputs, from the WB-master
type wb_slv_in_type is record
clk_i : std_logic; -- master clock input
rst_i : std_logic; -- synchronous active high reset
adr_i : std_logic_vector(CFG_DMEM_SIZE - 1 downto 0); -- address bits
dat_i : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0); -- Databus input
we_i : std_logic; -- Write enable input
stb_i : std_logic; -- strobe signals / core select signal
sel_i : std_logic_vector(3 downto 0); -- select output array
cyc_i : std_logic; -- valid BUS cycle input
end record;
 
-- WB-slave outputs to the WB-master
type wb_slv_out_type is record
dat_o : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0); -- Databus output
ack_o : std_logic; -- Bus cycle acknowledge output
int_o : std_logic; -- interrupt request output
end record;
 
----------------------------------------------------------------------------------------------
-- COMPONENTS USED IN MB-LITE
----------------------------------------------------------------------------------------------
 
component core
generic (
G_INTERRUPT : boolean := CFG_INTERRUPT;
G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
G_USE_BARREL : boolean := CFG_USE_BARREL;
G_DEBUG : boolean := CFG_DEBUG
);
port (
imem_o : out imem_out_type;
dmem_o : out dmem_out_type;
imem_i : in imem_in_type;
dmem_i : in dmem_in_type;
int_i : in std_logic;
rst_i : in std_logic;
clk_i : in std_logic
);
end component;
 
component core_wb
generic (
G_INTERRUPT : boolean := CFG_INTERRUPT;
G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
G_USE_BARREL : boolean := CFG_USE_BARREL;
G_DEBUG : boolean := CFG_DEBUG
);
port (
imem_o : out imem_out_type;
wb_o : out wb_mst_out_type;
imem_i : in imem_in_type;
wb_i : in wb_mst_in_type
);
end component;
 
component core_wb_adapter
port (
dmem_i : out dmem_in_type;
wb_o : out wb_mst_out_type;
dmem_o : in dmem_out_type;
wb_i : in wb_mst_in_type
);
end component;
 
component core_wb_async_adapter
port (
dmem_i : out dmem_in_type;
wb_o : out wb_mst_out_type;
dmem_o : in dmem_out_type;
wb_i : in wb_mst_in_type
);
end component;
 
component fetch
port (
fetch_o : out fetch_out_type;
imem_o : out imem_out_type;
fetch_i : in fetch_in_type;
rst_i : in std_logic;
ena_i : in std_logic;
clk_i : in std_logic
);
end component;
 
component decode
generic (
G_INTERRUPT : boolean := CFG_INTERRUPT;
G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
G_USE_BARREL : boolean := CFG_USE_BARREL;
G_DEBUG : boolean := CFG_DEBUG
);
port (
decode_o : out decode_out_type;
gprf_o : out gprf_out_type;
decode_i : in decode_in_type;
ena_i : in std_logic;
rst_i : in std_logic;
clk_i : in std_logic
);
end component;
 
component gprf
port (
gprf_o : out gprf_out_type;
gprf_i : in gprf_in_type;
ena_i : in std_logic;
clk_i : in std_logic
);
end component;
 
component execute
generic (
G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
G_USE_BARREL : boolean := CFG_USE_BARREL
);
port (
exec_o : out execute_out_type;
exec_i : in execute_in_type;
ena_i : in std_logic;
rst_i : in std_logic;
clk_i : in std_logic
);
end component;
 
component mem
port (
mem_o : out mem_out_type;
dmem_o : out dmem_out_type;
mem_i : in mem_in_type;
ena_i : in std_logic;
rst_i : in std_logic;
clk_i : in std_logic
);
end component;
 
component core_address_decoder
generic (
G_NUM_SLAVES : positive := CFG_NUM_SLAVES
);
port (
m_dmem_i : out dmem_in_type;
s_dmem_o : out dmem_out_array_type;
m_dmem_o : in dmem_out_type;
s_dmem_i : in dmem_in_array_type;
clk_i : in std_logic
);
end component;
----------------------------------------------------------------------------------------------
-- FUNCTIONS USED IN MB-LITE
----------------------------------------------------------------------------------------------
 
function select_register_data (reg_dat, reg, wb_dat : std_logic_vector; write : std_logic) return std_logic_vector;
function forward_condition (reg_write : std_logic; reg_a, reg_d : std_logic_vector) return std_logic;
function align_mem_load (data : std_logic_vector; size : transfer_size; address : std_logic_vector) return std_logic_vector;
function align_mem_store (data : std_logic_vector; size : transfer_size) return std_logic_vector;
function decode_mem_store (address : std_logic_vector(1 downto 0); size : transfer_size) return std_logic_vector;
 
end core_Pkg;
 
package body core_Pkg is
 
-- This function select the register value:
-- A) zero
-- B) bypass value read from register file
-- C) value from register file
function select_register_data (reg_dat, reg, wb_dat : std_logic_vector; write : std_logic) return std_logic_vector is
variable tmp : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
begin
if CFG_REG_FORCE_ZERO = true and is_zero(reg) = '1' then
tmp := (others => '0');
elsif CFG_REG_FWD_WRB = true and write = '1' then
tmp := wb_dat;
else
tmp := reg_dat;
end if;
return tmp;
end select_register_data;
 
-- This function checks if a forwarding condition is met. The condition is met of register A and D match
-- and the signal needs to be written back to the register file.
function forward_condition (reg_write : std_logic; reg_a, reg_d : std_logic_vector ) return std_logic is
begin
return reg_write and compare(reg_a, reg_d);
end forward_condition;
 
-- This function aligns the memory load operation (Big endian decoding).
function align_mem_load (data : std_logic_vector; size : transfer_size; address : std_logic_vector ) return std_logic_vector is
begin
case size is
when byte =>
case address(1 downto 0) is
when "00" => return C_24_ZEROS & data(31 downto 24);
when "01" => return C_24_ZEROS & data(23 downto 16);
when "10" => return C_24_ZEROS & data(15 downto 8);
when "11" => return C_24_ZEROS & data( 7 downto 0);
when others => return C_32_ZEROS;
end case;
when halfword =>
case address(1 downto 0) is
when "00" => return C_16_ZEROS & data(31 downto 16);
when "10" => return C_16_ZEROS & data(15 downto 0);
when others => return C_32_ZEROS;
end case;
when others =>
return data;
end case;
end align_mem_load;
 
-- This function repeats the operand to all positions in a memory store operation.
function align_mem_store (data : std_logic_vector; size : transfer_size) return std_logic_vector is
begin
case size is
when byte => return data( 7 downto 0) & data( 7 downto 0) & data(7 downto 0) & data(7 downto 0);
when halfword => return data(15 downto 0) & data(15 downto 0);
when others => return data;
end case;
end align_mem_store;
 
-- This function selects the correct bytes for memory writes (Big endian encoding).
function decode_mem_store (address : std_logic_vector(1 downto 0); size : transfer_size) return std_logic_vector is
begin
case size is
when BYTE =>
case address is
when "00" => return "1000";
when "01" => return "0100";
when "10" => return "0010";
when "11" => return "0001";
when others => return "0000";
end case;
when HALFWORD =>
case address is
-- Big endian encoding
when "10" => return "0011";
when "00" => return "1100";
when others => return "0000";
end case;
when others =>
return "1111";
end case;
end decode_mem_store;
 
end core_Pkg;
/tags/vmblite_base/hw/src/rtl/mblite/core/core_address_decoder.vhd
0,0 → 1,97
----------------------------------------------------------------------------------------------
--
-- Input file : core_address_decoder.vhd
-- Design name : core_address_decoder
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Wishbone adapter for the MB-Lite microprocessor
--
----------------------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
 
entity core_address_decoder is generic
(
G_NUM_SLAVES : positive := CFG_NUM_SLAVES;
G_MEMORY_MAP : memory_map_type := CFG_MEMORY_MAP
);
port
(
m_dmem_i : out dmem_in_type;
s_dmem_o : out dmem_out_array_type(G_NUM_SLAVES - 1 downto 0);
m_dmem_o : in dmem_out_type;
s_dmem_i : in dmem_in_array_type(G_NUM_SLAVES - 1 downto 0);
clk_i : std_logic
);
end core_address_decoder;
 
architecture arch of core_address_decoder is
 
-- Decodes the address based on the memory map. Returns "1" if 0 or 1 slave is attached.
function decode(adr : std_logic_vector) return std_logic_vector is
variable result : std_logic_vector(G_NUM_SLAVES - 1 downto 0);
begin
if G_NUM_SLAVES > 1 and notx(adr) then
for i in G_NUM_SLAVES - 1 downto 0 loop
if (adr >= G_MEMORY_MAP(i) and adr < G_MEMORY_MAP(i+1)) then
result(i) := '1';
else
result(i) := '0';
end if;
end loop;
else
result := (others => '1');
end if;
return result;
end function;
 
function demux(dmem_i : dmem_in_array_type; ce, r_ce : std_logic_vector) return dmem_in_type is
variable dmem : dmem_in_type;
begin
dmem := dmem_i(0);
if notx(ce) then
for i in G_NUM_SLAVES - 1 downto 0 loop
if ce(i) = '1' then
dmem.ena_i := dmem_i(i).ena_i;
end if;
if r_ce(i) = '1' then
dmem.dat_i := dmem_i(i).dat_i;
end if;
end loop;
end if;
return dmem;
end function;
 
signal r_ce, ce : std_logic_vector(G_NUM_SLAVES - 1 downto 0) := (others => '1');
 
begin
 
ce <= decode(m_dmem_o.adr_o);
m_dmem_i <= demux(s_dmem_i, ce, r_ce);
 
CON: for i in G_NUM_SLAVES-1 downto 0 generate
begin
s_dmem_o(i).dat_o <= m_dmem_o.dat_o;
s_dmem_o(i).adr_o <= m_dmem_o.adr_o;
s_dmem_o(i).sel_o <= m_dmem_o.sel_o;
s_dmem_o(i).we_o <= m_dmem_o.we_o and ce(i);
s_dmem_o(i).ena_o <= m_dmem_o.ena_o and ce(i);
end generate;
 
process(clk_i)
begin
if rising_edge(clk_i) then
r_ce <= ce;
end if;
end process;
end arch;
/tags/vmblite_base/hw/src/rtl/mblite/core/core_wb.vhd
0,0 → 1,71
----------------------------------------------------------------------------------------------
--
-- Input file : core_wb.vhd
-- Design name : core_wb
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Top level module of the MB-Lite microprocessor with connected
-- wishbone data bus
--
----------------------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
 
entity core_wb is generic
(
G_INTERRUPT : boolean := CFG_INTERRUPT;
G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
G_USE_BARREL : boolean := CFG_USE_BARREL;
G_DEBUG : boolean := CFG_DEBUG
);
port
(
imem_o : out imem_out_type;
wb_o : out wb_mst_out_type;
imem_i : in imem_in_type;
wb_i : in wb_mst_in_type
);
end core_wb;
 
architecture arch of core_wb is
signal dmem_i : dmem_in_type;
signal dmem_o : dmem_out_type;
begin
 
wb_adapter0 : core_wb_adapter port map
(
dmem_i => dmem_i,
wb_o => wb_o,
dmem_o => dmem_o,
wb_i => wb_i
);
 
core0 : core generic map
(
G_INTERRUPT => G_INTERRUPT,
G_USE_HW_MUL => G_USE_HW_MUL,
G_USE_BARREL => G_USE_BARREL,
G_DEBUG => G_DEBUG
)
port map
(
imem_o => imem_o,
dmem_o => dmem_o,
imem_i => imem_i,
dmem_i => dmem_i,
int_i => wb_i.int_i,
rst_i => wb_i.rst_i,
clk_i => wb_i.clk_i
);
 
end arch;
/tags/vmblite_base/hw/src/rtl/mblite/core/core_wb_adapter.vhd
0,0 → 1,98
----------------------------------------------------------------------------------------------
--
-- Input file : core_wb_adapter.vhd
-- Design name : core_wb_adapter.vhd
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Wishbone adapter for the MB-Lite microprocessor. The data output
-- is registered for multicycle transfers. This adapter implements
-- the synchronous Wishbone Bus protocol, Rev3B.
--
----------------------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
 
entity core_wb_adapter is port
(
dmem_i : out dmem_in_type;
wb_o : out wb_mst_out_type;
dmem_o : in dmem_out_type;
wb_i : in wb_mst_in_type
);
end core_wb_adapter;
 
architecture arch of core_wb_adapter is
 
signal r_cyc_o : std_logic;
signal rin_cyc_o : std_logic;
signal r_data, rin_data : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
signal s_wait : std_logic;
 
begin
 
-- Direct input-output connections
wb_o.adr_o <= dmem_o.adr_o;
wb_o.sel_o <= dmem_o.sel_o;
wb_o.we_o <= dmem_o.we_o;
dmem_i.dat_i <= wb_i.dat_i;
 
-- synchronous bus control connections
wb_o.cyc_o <= r_cyc_o or wb_i.ack_i;
wb_o.stb_o <= r_cyc_o;
 
-- asynchronous core enable connection
dmem_i.ena_i <= '0' when (dmem_o.ena_o = '1' and rin_cyc_o = '1') or s_wait = '1' else '1';
wb_o.dat_o <= rin_data;
 
-- logic for wishbone master
wb_adapter_comb: process(wb_i, dmem_o, r_cyc_o, r_data)
begin
 
if wb_i.rst_i = '1' then
-- reset bus
rin_data <= r_data;
rin_cyc_o <= '0';
s_wait <= '0';
elsif r_cyc_o = '1' and wb_i.ack_i = '1' then
-- terminate wishbone cycle
rin_data <= r_data;
rin_cyc_o <= '0';
s_wait <= '0';
elsif dmem_o.ena_o = '1' and wb_i.ack_i = '1' then
-- wishbone bus is occuppied
rin_data <= r_data;
rin_cyc_o <= '1';
s_wait <= '1';
elsif r_cyc_o = '0' and dmem_o.ena_o = '1' and wb_i.ack_i = '0' then
-- start wishbone cycle
rin_data <= dmem_o.dat_o;
rin_cyc_o <= '1';
s_wait <= '0';
else
-- maintain wishbone cycle
rin_data <= r_data;
rin_cyc_o <= r_cyc_o;
s_wait <= '0';
end if;
 
end process;
 
wb_adapter_seq: process(wb_i.clk_i)
begin
if rising_edge(wb_i.clk_i) then
r_cyc_o <= rin_cyc_o;
r_data <= rin_data;
end if;
end process;
 
end arch;
/tags/vmblite_base/hw/src/rtl/mblite/core/decode.vhd
0,0 → 1,499
----------------------------------------------------------------------------------------------
--
-- Input file : decode.vhd
-- Design name : decode
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : This combined register file and decoder uses three Dual Port
-- read after write Random Access Memory components. Every clock
-- cycle three data values can be read (ra, rb and rd) and one value
-- can be stored.
--
----------------------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
 
entity decode is generic
(
G_INTERRUPT : boolean := CFG_INTERRUPT;
G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
G_USE_BARREL : boolean := CFG_USE_BARREL;
G_DEBUG : boolean := CFG_DEBUG
);
port
(
decode_o : out decode_out_type;
gprf_o : out gprf_out_type;
decode_i : in decode_in_type;
ena_i : in std_logic;
rst_i : in std_logic;
clk_i : in std_logic
);
end decode;
 
architecture arch of decode is
 
type decode_reg_type is record
instruction : std_logic_vector(CFG_IMEM_WIDTH - 1 downto 0);
program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
immediate : std_logic_vector(15 downto 0);
is_immediate : std_logic;
msr_interrupt_enable : std_logic;
interrupt : std_logic;
delay_interrupt : std_logic;
end record;
 
signal r, rin : decode_out_type;
signal reg, regin : decode_reg_type;
 
signal wb_dat_d : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
 
begin
 
decode_o.imm <= r.imm;
 
decode_o.ctrl_ex <= r.ctrl_ex;
decode_o.ctrl_mem <= r.ctrl_mem;
decode_o.ctrl_wrb <= r.ctrl_wrb;
 
decode_o.reg_a <= r.reg_a;
decode_o.reg_b <= r.reg_b;
decode_o.hazard <= r.hazard;
decode_o.program_counter <= r.program_counter;
 
decode_o.fwd_dec_result <= r.fwd_dec_result;
decode_o.fwd_dec <= r.fwd_dec;
 
decode_comb: process(decode_i,decode_i.ctrl_wrb,
decode_i.ctrl_mem_wrb,
decode_i.instruction,
decode_i.ctrl_mem_wrb.transfer_size,
r,r.ctrl_ex,r.ctrl_mem,
r.ctrl_mem.transfer_size,r.ctrl_wrb,
r.ctrl_wrb.reg_d,
r.fwd_dec,reg)
 
variable v : decode_out_type;
variable v_reg : decode_reg_type;
variable opcode : std_logic_vector(5 downto 0);
variable instruction : std_logic_vector(CFG_IMEM_WIDTH - 1 downto 0);
variable program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
variable mem_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
 
begin
v := r;
v_reg := reg;
 
-- Default register values (NOP)
v_reg.immediate := (others => '0');
v_reg.is_immediate := '0';
v_reg.program_counter := decode_i.program_counter;
v_reg.instruction := decode_i.instruction;
 
if decode_i.ctrl_mem_wrb.mem_read = '1' then
mem_result := align_mem_load(decode_i.mem_result, decode_i.ctrl_mem_wrb.transfer_size, decode_i.alu_result(1 downto 0));
else
mem_result := decode_i.alu_result;
end if;
 
wb_dat_d <= mem_result;
 
if G_INTERRUPT = true then
v_reg.delay_interrupt := '0';
end if;
 
if CFG_REG_FWD_WRB = true then
v.fwd_dec_result := mem_result;
v.fwd_dec := decode_i.ctrl_wrb;
else
v.fwd_dec_result := (others => '0');
v.fwd_dec.reg_d := (others => '0');
v.fwd_dec.reg_write := '0';
end if;
 
if (not decode_i.flush_id and r.ctrl_mem.mem_read and (compare(decode_i.instruction(20 downto 16), r.ctrl_wrb.reg_d) or compare(decode_i.instruction(15 downto 11), r.ctrl_wrb.reg_d))) = '1' then
-- A hazard occurred on register a or b
 
-- set current instruction and program counter to 0
instruction := (others => '0');
program_counter := (others => '0');
 
v.hazard := '1';
 
elsif CFG_MEM_FWD_WRB = false and (not decode_i.flush_id and r.ctrl_mem.mem_read and compare(decode_i.instruction(25 downto 21), r.ctrl_wrb.reg_d)) = '1' then
-- A hazard occurred on register d
 
-- set current instruction and program counter to 0
instruction := (others => '0');
program_counter := (others => '0');
 
v.hazard := '1';
 
elsif r.hazard = '1' then
-- Recover from hazard. Insert latched instruction
 
instruction := reg.instruction;
program_counter := reg.program_counter;
v.hazard := '0';
 
else
 
instruction := decode_i.instruction;
program_counter := decode_i.program_counter;
v.hazard := '0';
 
end if;
 
v.program_counter := program_counter;
opcode := instruction(31 downto 26);
v.ctrl_wrb.reg_d := instruction(25 downto 21);
v.reg_a := instruction(20 downto 16);
v.reg_b := instruction(15 downto 11);
 
-- SET IMM value
if reg.is_immediate = '1' then
v.imm := reg.immediate & instruction(15 downto 0);
else
v.imm := sign_extend(instruction(15 downto 0), instruction(15), 32);
end if;
 
-- Register if an interrupt occurs
if G_INTERRUPT = true then
if v_reg.msr_interrupt_enable = '1' and decode_i.interrupt = '1' then
v_reg.interrupt := '1';
v_reg.msr_interrupt_enable := '0';
end if;
end if;
 
v.ctrl_ex.alu_op := ALU_ADD;
v.ctrl_ex.alu_src_a := ALU_SRC_REGA;
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
v.ctrl_ex.operation := '0';
v.ctrl_ex.carry := CARRY_ZERO;
v.ctrl_ex.carry_keep := CARRY_KEEP;
v.ctrl_ex.delay := '0';
v.ctrl_ex.branch_cond := NOP;
v.ctrl_mem.mem_write := '0';
v.ctrl_mem.transfer_size := WORD;
v.ctrl_mem.mem_read := '0';
v.ctrl_wrb.reg_write := '0';
 
if G_INTERRUPT = true and (v_reg.interrupt = '1' and reg.delay_interrupt = '0' and decode_i.flush_id = '0' and v.hazard = '0' and r.ctrl_ex.delay = '0' and reg.is_immediate = '0') then
-- IF an interrupt occured
-- AND the current instruction is not a branch or return instruction,
-- AND the current instruction is not in a delay slot,
-- AND this is instruction is not preceded by an IMM instruction, than handle the interrupt.
v_reg.msr_interrupt_enable := '0';
v_reg.interrupt := '0';
 
v.reg_a := (others => '0');
v.reg_b := (others => '0');
 
v.imm := X"00000010";
v.ctrl_wrb.reg_d := "01110";
 
v.ctrl_ex.branch_cond := BNC;
v.ctrl_ex.alu_src_a := ALU_SRC_ZERO;
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
v.ctrl_wrb.reg_write := '1';
 
elsif (decode_i.flush_id or v.hazard) = '1' then
-- clearing these registers is not necessary, but facilitates debugging.
-- On the other hand performance improves when disabled.
if G_DEBUG = true then
v.program_counter := (others => '0');
v.ctrl_wrb.reg_d := (others => '0');
v.reg_a := (others => '0');
v.reg_b := (others => '0');
v.imm := (others => '0');
end if;
 
elsif is_zero(opcode(5 downto 4)) = '1' then
-- ADD, SUBTRACT OR COMPARE
 
-- Alu operation
v.ctrl_ex.alu_op := ALU_ADD;
 
-- Source operand A
if opcode(0) = '1' then
v.ctrl_ex.alu_src_a := ALU_SRC_NOT_REGA;
else
v.ctrl_ex.alu_src_a := ALU_SRC_REGA;
end if;
 
-- Source operand B
if opcode(3) = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
else
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
end if;
 
if (compare(opcode, "000101") and instruction(1)) = '1' then
v.ctrl_ex.operation := '1';
end if;
 
-- Carry
case opcode(1 downto 0) is
when "00" => v.ctrl_ex.carry := CARRY_ZERO;
when "01" => v.ctrl_ex.carry := CARRY_ONE;
when others => v.ctrl_ex.carry := CARRY_ALU;
end case;
 
-- Carry keep
if opcode(2) = '1' then
v.ctrl_ex.carry_keep := CARRY_KEEP;
else
v.ctrl_ex.carry_keep := CARRY_NOT_KEEP;
end if;
 
-- Flag writeback if reg_d != 0
v.ctrl_wrb.reg_write := is_not_zero(v.ctrl_wrb.reg_d);
 
elsif (compare(opcode(5 downto 2), "1000") or compare(opcode(5 downto 2), "1010")) = '1' then
-- OR, AND, XOR, ANDN
-- ORI, ANDI, XORI, ANDNI
case opcode(1 downto 0) is
when "00" => v.ctrl_ex.alu_op := ALU_OR;
when "10" => v.ctrl_ex.alu_op := ALU_XOR;
when others => v.ctrl_ex.alu_op := ALU_AND;
end case;
 
if opcode(3) = '1' and compare(opcode(1 downto 0), "11") = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_NOT_IMM;
elsif opcode(3) = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
elsif opcode(3) = '0' and compare(opcode(1 downto 0), "11") = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_NOT_REGB;
else
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
end if;
 
-- Flag writeback if reg_d != 0
v.ctrl_wrb.reg_write := is_not_zero(v.ctrl_wrb.reg_d);
 
elsif compare(opcode, "101100") = '1' then
-- IMM instruction
v_reg.immediate := instruction(15 downto 0);
v_reg.is_immediate := '1';
 
elsif compare(opcode, "100100") = '1' then
-- SHIFT, SIGN EXTEND
if compare(instruction(6 downto 5), "11") = '1' then
if instruction(0) = '1' then
v.ctrl_ex.alu_op:= ALU_SEXT16;
else
v.ctrl_ex.alu_op:= ALU_SEXT8;
end if;
else
v.ctrl_ex.alu_op:= ALU_SHIFT;
v.ctrl_ex.carry_keep := CARRY_NOT_KEEP;
case instruction(6 downto 5) is
when "10" => v.ctrl_ex.carry := CARRY_ZERO;
when "01" => v.ctrl_ex.carry := CARRY_ALU;
when others => v.ctrl_ex.carry := CARRY_ARITH;
end case;
end if;
 
-- Flag writeback if reg_d != 0
v.ctrl_wrb.reg_write := is_not_zero(v.ctrl_wrb.reg_d);
 
elsif (compare(opcode, "100110") or compare(opcode, "101110")) = '1' then
-- BRANCH UNCONDITIONAL
 
v.ctrl_ex.branch_cond := BNC;
 
if opcode(3) = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
else
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
end if;
 
-- WRITE THE RESULT ALSO TO REGISTER D
if v.reg_a(2) = '1' then
-- Flag writeback if reg_d != 0
v.ctrl_wrb.reg_write := is_not_zero(v.ctrl_wrb.reg_d);
end if;
 
if v.reg_a(3) = '1' then
v.ctrl_ex.alu_src_a := ALU_SRC_ZERO;
else
v.ctrl_ex.alu_src_a := ALU_SRC_PC;
end if;
 
if G_INTERRUPT = true then
v_reg.delay_interrupt := '1';
end if;
v.ctrl_ex.delay := v.reg_a(4);
 
elsif (compare(opcode, "100111") or compare(opcode, "101111")) = '1' then
-- BRANCH CONDITIONAL
v.ctrl_ex.alu_op := ALU_ADD;
v.ctrl_ex.alu_src_a := ALU_SRC_PC;
 
if opcode(3) = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
else
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
end if;
 
case v.ctrl_wrb.reg_d(2 downto 0) is
when "000" => v.ctrl_ex.branch_cond := BEQ;
when "001" => v.ctrl_ex.branch_cond := BNE;
when "010" => v.ctrl_ex.branch_cond := BLT;
when "011" => v.ctrl_ex.branch_cond := BLE;
when "100" => v.ctrl_ex.branch_cond := BGT;
when others => v.ctrl_ex.branch_cond := BGE;
end case;
 
if G_INTERRUPT = true then
v_reg.delay_interrupt := '1';
end if;
v.ctrl_ex.delay := v.ctrl_wrb.reg_d(4);
 
elsif compare(opcode, "101101") = '1' then
-- RETURN
 
v.ctrl_ex.branch_cond := BNC;
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
v.ctrl_ex.delay := '1';
 
if G_INTERRUPT = true then
if v.ctrl_wrb.reg_d(0) = '1' then
v_reg.msr_interrupt_enable := '1';
end if;
v_reg.delay_interrupt := '1';
end if;
 
elsif compare(opcode(5 downto 4), "11") = '1' then
-- SW, LW
v.ctrl_ex.alu_op := ALU_ADD;
v.ctrl_ex.alu_src_a := ALU_SRC_REGA;
 
if opcode(3) = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
else
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
end if;
 
v.ctrl_ex.carry := CARRY_ZERO;
 
if opcode(2) = '1' then
-- Store
v.ctrl_mem.mem_write := '1';
v.ctrl_mem.mem_read := '0';
v.ctrl_wrb.reg_write := '0';
else
-- Load
v.ctrl_mem.mem_write := '0';
v.ctrl_mem.mem_read := '1';
v.ctrl_wrb.reg_write := is_not_zero(v.ctrl_wrb.reg_d);
end if;
 
case opcode(1 downto 0) is
when "00" => v.ctrl_mem.transfer_size := BYTE;
when "01" => v.ctrl_mem.transfer_size := HALFWORD;
when others => v.ctrl_mem.transfer_size := WORD;
end case;
 
v.ctrl_ex.delay := '0';
 
elsif G_USE_HW_MUL = true and (compare(opcode, "010000") or compare(opcode, "011000")) = '1' then
 
v.ctrl_ex.alu_op := ALU_MUL;
 
if opcode(3) = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
else
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
end if;
 
v.ctrl_wrb.reg_write := is_not_zero(v.ctrl_wrb.reg_d);
 
elsif G_USE_BARREL = true and (compare(opcode, "010001") or compare(opcode, "011001")) = '1' then
 
v.ctrl_ex.alu_op := ALU_BS;
 
if opcode(3) = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
else
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
end if;
 
v.ctrl_wrb.reg_write := is_not_zero(v.ctrl_wrb.reg_d);
 
else
-- UNKNOWN OPCODE
null;
end if;
 
rin <= v;
regin <= v_reg;
 
end process;
 
decode_seq: process(clk_i)
procedure proc_reset_decode is
begin
r.reg_a <= (others => '0');
r.reg_b <= (others => '0');
r.imm <= (others => '0');
r.program_counter <= (others => '0');
r.hazard <= '0';
r.ctrl_ex.alu_op <= ALU_ADD;
r.ctrl_ex.alu_src_a <= ALU_SRC_REGA;
r.ctrl_ex.alu_src_b <= ALU_SRC_REGB;
r.ctrl_ex.operation <= '0';
r.ctrl_ex.carry <= CARRY_ZERO;
r.ctrl_ex.carry_keep <= CARRY_NOT_KEEP;
r.ctrl_ex.delay <= '0';
r.ctrl_ex.branch_cond <= NOP;
r.ctrl_mem.mem_write <= '0';
r.ctrl_mem.transfer_size <= WORD;
r.ctrl_mem.mem_read <= '0';
r.ctrl_wrb.reg_d <= (others => '0');
r.ctrl_wrb.reg_write <= '0';
r.fwd_dec_result <= (others => '0');
r.fwd_dec.reg_d <= (others => '0');
r.fwd_dec.reg_write <= '0';
reg.instruction <= (others => '0');
reg.program_counter <= (others => '0');
reg.immediate <= (others => '0');
reg.is_immediate <= '0';
reg.msr_interrupt_enable <= '1';
reg.interrupt <= '0';
reg.delay_interrupt <= '0';
end procedure proc_reset_decode;
begin
if rising_edge(clk_i) then
if rst_i = '1' then
proc_reset_decode;
elsif ena_i = '1' then
r <= rin;
reg <= regin;
end if;
end if;
end process;
 
gprf0 : gprf port map
(
gprf_o => gprf_o,
gprf_i.adr_a_i => rin.reg_a,
gprf_i.adr_b_i => rin.reg_b,
gprf_i.adr_d_i => rin.ctrl_wrb.reg_d,
gprf_i.dat_w_i => wb_dat_d,
gprf_i.adr_w_i => decode_i.ctrl_wrb.reg_d,
gprf_i.wre_i => decode_i.ctrl_wrb.reg_write,
ena_i => ena_i,
clk_i => clk_i
);
end arch;
/tags/vmblite_base/hw/src/rtl/mblite/core/execute.vhd
0,0 → 1,257
----------------------------------------------------------------------------------------------
--
-- Input file : execute.vhd
-- Design name : execute
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : The Execution Unit performs all arithmetic operations and makes
-- the branch decision. Furthermore the forwarding logic is located
-- here. Everything is computed within a single clock-cycle
--
--
----------------------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
 
entity execute is generic
(
G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
G_USE_BARREL : boolean := CFG_USE_BARREL
);
port
(
exec_o : out execute_out_type;
exec_i : in execute_in_type;
ena_i : in std_logic;
rst_i : in std_logic;
clk_i : in std_logic
);
end execute;
 
architecture arch of execute is
 
type execute_reg_type is record
carry : std_logic;
flush_ex : std_logic;
end record;
 
signal r, rin : execute_out_type;
signal reg, regin : execute_reg_type;
 
begin
 
exec_o <= r;
 
execute_comb: process(exec_i,exec_i.fwd_mem,exec_i.ctrl_ex,
exec_i.ctrl_wrb,exec_i.ctrl_mem,
exec_i.ctrl_mem.transfer_size,
exec_i.ctrl_mem_wrb,exec_i.fwd_dec,
r,r.ctrl_mem,r.ctrl_mem.transfer_size,
r.ctrl_wrb,reg)
 
variable v : execute_out_type;
variable v_reg : execute_reg_type;
 
variable alu_src_a : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
variable alu_src_b : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
variable carry : std_logic;
 
variable result : std_logic_vector(CFG_DMEM_WIDTH downto 0);
variable result_add : std_logic_vector(CFG_DMEM_WIDTH downto 0);
variable zero : std_logic;
 
variable dat_a, dat_b : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
variable sel_dat_a, sel_dat_b, sel_dat_d : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
variable mem_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
 
begin
 
v := r;
 
sel_dat_a := select_register_data(exec_i.dat_a, exec_i.reg_a, exec_i.fwd_dec_result, forward_condition(exec_i.fwd_dec.reg_write, exec_i.fwd_dec.reg_d, exec_i.reg_a));
sel_dat_b := select_register_data(exec_i.dat_b, exec_i.reg_b, exec_i.fwd_dec_result, forward_condition(exec_i.fwd_dec.reg_write, exec_i.fwd_dec.reg_d, exec_i.reg_b));
sel_dat_d := select_register_data(exec_i.dat_d, exec_i.ctrl_wrb.reg_d, exec_i.fwd_dec_result, forward_condition(exec_i.fwd_dec.reg_write, exec_i.fwd_dec.reg_d, exec_i.ctrl_wrb.reg_d));
 
if reg.flush_ex = '1' then
v.ctrl_mem.mem_write := '0';
v.ctrl_mem.mem_read := '0';
v.ctrl_wrb.reg_write := '0';
v.ctrl_wrb.reg_d := (others => '0');
else
v.ctrl_mem := exec_i.ctrl_mem;
v.ctrl_wrb := exec_i.ctrl_wrb;
end if;
 
if exec_i.ctrl_mem_wrb.mem_read = '1' then
mem_result := align_mem_load(exec_i.mem_result, exec_i.ctrl_mem_wrb.transfer_size, exec_i.alu_result(1 downto 0));
else
mem_result := exec_i.alu_result;
end if;
 
if forward_condition(r.ctrl_wrb.reg_write, r.ctrl_wrb.reg_d, exec_i.reg_a) = '1' then
-- Forward Execution Result to REG a
dat_a := r.alu_result;
elsif forward_condition(exec_i.fwd_mem.reg_write, exec_i.fwd_mem.reg_d, exec_i.reg_a) = '1' then
-- Forward Memory Result to REG a
dat_a := mem_result;
else
-- DEFAULT: value of REG a
dat_a := sel_dat_a;
end if;
 
if forward_condition(r.ctrl_wrb.reg_write, r.ctrl_wrb.reg_d, exec_i.reg_b) = '1' then
-- Forward (latched) Execution Result to REG b
dat_b := r.alu_result;
elsif forward_condition(exec_i.fwd_mem.reg_write, exec_i.fwd_mem.reg_d, exec_i.reg_b) = '1' then
-- Forward Memory Result to REG b
dat_b := mem_result;
else
-- DEFAULT: value of REG b
dat_b := sel_dat_b;
end if;
 
if forward_condition(r.ctrl_wrb.reg_write, r.ctrl_wrb.reg_d, exec_i.ctrl_wrb.reg_d) = '1' then
-- Forward Execution Result to REG d
v.dat_d := align_mem_store(r.alu_result, exec_i.ctrl_mem.transfer_size);
elsif forward_condition(exec_i.fwd_mem.reg_write, exec_i.fwd_mem.reg_d, exec_i.ctrl_wrb.reg_d) = '1' then
-- Forward Memory Result to REG d
v.dat_d := align_mem_store(mem_result, exec_i.ctrl_mem.transfer_size);
else
-- DEFAULT: value of REG d
v.dat_d := align_mem_store(sel_dat_d, exec_i.ctrl_mem.transfer_size);
end if;
 
-- Set the first operand of the ALU
case exec_i.ctrl_ex.alu_src_a is
when ALU_SRC_PC => alu_src_a := sign_extend(exec_i.program_counter, '0', 32);
when ALU_SRC_NOT_REGA => alu_src_a := not dat_a;
when ALU_SRC_ZERO => alu_src_a := (others => '0');
when others => alu_src_a := dat_a;
end case;
 
-- Set the second operand of the ALU
case exec_i.ctrl_ex.alu_src_b is
when ALU_SRC_IMM => alu_src_b := exec_i.imm;
when ALU_SRC_NOT_IMM => alu_src_b := not exec_i.imm;
when ALU_SRC_NOT_REGB => alu_src_b := not dat_b;
when others => alu_src_b := dat_b;
end case;
 
-- Determine value of carry in
case exec_i.ctrl_ex.carry is
when CARRY_ALU => carry := reg.carry;
when CARRY_ONE => carry := '1';
when CARRY_ARITH => carry := alu_src_a(CFG_DMEM_WIDTH - 1);
when others => carry := '0';
end case;
 
result_add := add(alu_src_a, alu_src_b, carry);
 
case exec_i.ctrl_ex.alu_op is
when ALU_ADD => result := result_add;
when ALU_OR => result := '0' & (alu_src_a or alu_src_b);
when ALU_AND => result := '0' & (alu_src_a and alu_src_b);
when ALU_XOR => result := '0' & (alu_src_a xor alu_src_b);
when ALU_SHIFT => result := alu_src_a(0) & carry & alu_src_a(CFG_DMEM_WIDTH - 1 downto 1);
when ALU_SEXT8 => result := '0' & sign_extend(alu_src_a(7 downto 0), alu_src_a(7), 32);
when ALU_SEXT16 => result := '0' & sign_extend(alu_src_a(15 downto 0), alu_src_a(15), 32);
when ALU_MUL =>
if G_USE_HW_MUL = true then
result := '0' & multiply(alu_src_a, alu_src_b);
else
result := (others => '0');
end if;
when ALU_BS =>
if G_USE_BARREL = true then
result := '0' & shift(alu_src_a, alu_src_b(4 downto 0), exec_i.imm(10), exec_i.imm(9));
else
result := (others => '0');
end if;
when others =>
result := (others => '0');
report "Invalid ALU operation" severity FAILURE;
end case;
 
-- Set carry register
if exec_i.ctrl_ex.carry_keep = CARRY_KEEP then
v_reg.carry := reg.carry;
else
v_reg.carry := result(CFG_DMEM_WIDTH);
end if;
 
zero := is_zero(dat_a);
 
-- Overwrite branch condition
if reg.flush_ex = '1' then
v.branch := '0';
else
-- Determine branch condition
case exec_i.ctrl_ex.branch_cond is
when BNC => v.branch := '1';
when BEQ => v.branch := zero;
when BNE => v.branch := not zero;
when BLT => v.branch := dat_a(CFG_DMEM_WIDTH - 1);
when BLE => v.branch := dat_a(CFG_DMEM_WIDTH - 1) or zero;
when BGT => v.branch := not (dat_a(CFG_DMEM_WIDTH - 1) or zero);
when BGE => v.branch := not dat_a(CFG_DMEM_WIDTH - 1);
when others => v.branch := '0';
end case;
end if;
 
-- Handle CMPU
if ( exec_i.ctrl_ex.operation and not (alu_src_a(CFG_DMEM_WIDTH - 1) xor alu_src_b(CFG_DMEM_WIDTH - 1))) = '1' then
-- Set MSB
v.alu_result(CFG_DMEM_WIDTH - 1 downto 0) := (not result(CFG_DMEM_WIDTH - 1)) & result(CFG_DMEM_WIDTH - 2 downto 0);
else
-- Use ALU result
v.alu_result := result(CFG_DMEM_WIDTH - 1 downto 0);
end if;
 
v.program_counter := exec_i.program_counter;
 
-- Determine flush signals
v.flush_id := v.branch;
v_reg.flush_ex := v.branch and not exec_i.ctrl_ex.delay;
 
rin <= v;
regin <= v_reg;
 
end process;
 
execute_seq: process(clk_i)
procedure proc_execute_reset is
begin
r.alu_result <= (others => '0');
r.dat_d <= (others => '0');
r.branch <= '0';
r.program_counter <= (others => '0');
r.flush_id <= '0';
r.ctrl_mem.mem_write <= '0';
r.ctrl_mem.mem_read <= '0';
r.ctrl_mem.transfer_size <= WORD;
r.ctrl_wrb.reg_d <= (others => '0');
r.ctrl_wrb.reg_write <= '0';
reg.carry <= '0';
reg.flush_ex <= '0';
end procedure proc_execute_reset;
begin
if rising_edge(clk_i) then
if rst_i = '1' then
proc_execute_reset;
elsif ena_i = '1' then
r <= rin;
reg <= regin;
end if;
end if;
end process;
end arch;
/tags/vmblite_base/hw/src/rtl/mblite/core/fetch.vhd
0,0 → 1,72
----------------------------------------------------------------------------------------------
--
-- Input file : fetch.vhd
-- Design name : fetch
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Instruction Fetch Stage inserts instruction into the pipeline. It
-- uses a single port Random Access Memory component which holds
-- the instructions. The next instruction is computed in the decode
-- stage.
--
----------------------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
 
entity fetch is port
(
fetch_o : out fetch_out_type;
imem_o : out imem_out_type;
fetch_i : in fetch_in_type;
rst_i : in std_logic;
ena_i : in std_logic;
clk_i : in std_logic
);
end fetch;
 
architecture arch of fetch is
signal r, rin : fetch_out_type;
begin
 
fetch_o.program_counter <= r.program_counter;
imem_o.adr_o <= rin.program_counter;
imem_o.ena_o <= ena_i;
 
fetch_comb: process(fetch_i, r, rst_i)
variable v : fetch_out_type;
begin
v := r;
if rst_i = '1' then
v.program_counter := (OTHERS => '0');
elsif fetch_i.hazard = '1' then
v.program_counter := r.program_counter;
elsif fetch_i.branch = '1' then
v.program_counter := fetch_i.branch_target;
else
v.program_counter := increment(r.program_counter(CFG_IMEM_SIZE - 1 downto 2)) & "00";
end if;
rin <= v;
end process;
 
fetch_seq: process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' then
r.program_counter <= (others => '0');
elsif ena_i = '1' then
r <= rin;
end if;
end if;
end process;
 
end arch;
/tags/vmblite_base/hw/src/rtl/mblite/core/gprf.vhd
0,0 → 1,87
----------------------------------------------------------------------------------------------
--
-- Input file : gprf.vhd
-- Design name : gprf
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : The general purpose register infers memory blocks to implement
-- the register file. All outputs are registered, possibly by using
-- registered memory elements.
--
----------------------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
 
entity gprf is port
(
gprf_o : out gprf_out_type;
gprf_i : in gprf_in_type;
ena_i : in std_logic;
clk_i : in std_logic
);
end gprf;
 
-- This architecture is the default implementation. It
-- consists of three dual port memories. Other
-- architectures can be added while configurations can
-- control the implemented architecture.
architecture arch of gprf is
begin
a : dsram generic map
(
WIDTH => CFG_DMEM_WIDTH,
SIZE => CFG_GPRF_SIZE
)
port map
(
dat_o => gprf_o.dat_a_o,
adr_i => gprf_i.adr_a_i,
ena_i => ena_i,
dat_w_i => gprf_i.dat_w_i,
adr_w_i => gprf_i.adr_w_i,
wre_i => gprf_i.wre_i,
clk_i => clk_i
);
 
b : dsram generic map
(
WIDTH => CFG_DMEM_WIDTH,
SIZE => CFG_GPRF_SIZE
)
port map
(
dat_o => gprf_o.dat_b_o,
adr_i => gprf_i.adr_b_i,
ena_i => ena_i,
dat_w_i => gprf_i.dat_w_i,
adr_w_i => gprf_i.adr_w_i,
wre_i => gprf_i.wre_i,
clk_i => clk_i
);
 
d : dsram generic map
(
WIDTH => CFG_DMEM_WIDTH,
SIZE => CFG_GPRF_SIZE
)
port map
(
dat_o => gprf_o.dat_d_o,
adr_i => gprf_i.adr_d_i,
ena_i => ena_i,
dat_w_i => gprf_i.dat_w_i,
adr_w_i => gprf_i.adr_w_i,
wre_i => gprf_i.wre_i,
clk_i => clk_i
);
end arch;
/tags/vmblite_base/hw/src/rtl/mblite/core/mem.vhd
0,0 → 1,107
----------------------------------------------------------------------------------------------
--
-- Input file : mem.vhd
-- Design name : mem
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Memory retrieves data words from a data memory. Memory file
-- access of byte, halfword and word sizes is supported. The sel_o
-- signal indicates which bytes should be read or written. The
-- responsibility for writing the right memory address is not within
-- this integer unit but should be handled by the external memory
-- device. This facilitates the addition of devices with different
-- bus sizes.
--
-- The dmem_i signals are directly connected to the decode and
-- execute components.
--
----------------------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
 
entity mem is port
(
mem_o : out mem_out_type;
dmem_o : out dmem_out_type;
mem_i : in mem_in_type;
ena_i : in std_logic;
rst_i : in std_logic;
clk_i : in std_logic
);
end mem;
 
architecture arch of mem is
signal r, rin : mem_out_type;
signal mem_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
begin
-- connect pipline signals
mem_o.ctrl_wrb <= r.ctrl_wrb;
mem_o.ctrl_mem_wrb <= r.ctrl_mem_wrb;
mem_o.alu_result <= r.alu_result;
 
-- connect memory interface signals
dmem_o.dat_o <= mem_result;
dmem_o.sel_o <= decode_mem_store(mem_i.alu_result(1 downto 0), mem_i.ctrl_mem.transfer_size);
dmem_o.we_o <= mem_i.ctrl_mem.mem_write;
dmem_o.adr_o <= mem_i.alu_result(CFG_DMEM_SIZE - 1 downto 0);
dmem_o.ena_o <= mem_i.ctrl_mem.mem_read or mem_i.ctrl_mem.mem_write;
 
mem_comb: process(mem_i, mem_i.ctrl_wrb, mem_i.ctrl_mem, r, r.ctrl_wrb, r.ctrl_mem_wrb)
variable v : mem_out_type;
variable intermediate : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
begin
 
v := r;
v.ctrl_wrb := mem_i.ctrl_wrb;
 
if mem_i.branch = '1' then
-- set alu result for branch and load instructions
v.alu_result := sign_extend(mem_i.program_counter, '0', 32);
else
v.alu_result := mem_i.alu_result;
end if;
 
-- Forward memory result
if CFG_MEM_FWD_WRB = true and ( r.ctrl_mem_wrb.mem_read and compare(mem_i.ctrl_wrb.reg_d, r.ctrl_wrb.reg_d)) = '1' then
intermediate := align_mem_load(mem_i.mem_result, r.ctrl_mem_wrb.transfer_size, r.alu_result(1 downto 0));
mem_result <= align_mem_store(intermediate, mem_i.ctrl_mem.transfer_size);
else
mem_result <= mem_i.dat_d;
end if;
 
v.ctrl_mem_wrb.mem_read := mem_i.ctrl_mem.mem_read;
v.ctrl_mem_wrb.transfer_size := mem_i.ctrl_mem.transfer_size;
 
rin <= v;
 
end process;
 
mem_seq: process(clk_i)
procedure proc_mem_reset is
begin
r.alu_result <= (others => '0');
r.ctrl_wrb.reg_d <= (others => '0');
r.ctrl_wrb.reg_write <= '0';
r.ctrl_mem_wrb.mem_read <= '0';
r.ctrl_mem_wrb.transfer_size <= WORD;
end procedure proc_mem_reset;
begin
if rising_edge(clk_i) then
if rst_i = '1' then
proc_mem_reset;
elsif ena_i = '1' then
r <= rin;
end if;
end if;
end process;
end arch;
/tags/vmblite_base/hw/src/rtl/mblite/std/README
0,0 → 1,22
STD_PKG.VHD
==============
Package: std_Pkg
Description: Package containing standard MBLITE types, components and functions
 
DSRAM.VHD
=========
Package: std_Pkg
Entity: dsram
Description: Dual Port Synchronous RAM
 
SRAM_4EN.VHD
============
Package: std_Pkg
Entity: sram_4en
Description: Single Port Synchronous RAM with 4 write enable signals
 
SRAM.VHD
========
Package: std_Pkg
Entity: sram_4en
Description: Single Port RAM
/tags/vmblite_base/hw/src/rtl/mblite/std/dsram.vhd
0,0 → 1,55
----------------------------------------------------------------------------------------------
--
-- Input file : dsram.vhd
-- Design name : dsram
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Dual Port Synchronous 'read after write' Ram. 1 Read Port and 1
-- Write Port.
--
--
----------------------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
library mblite;
use mblite.std_Pkg.all;
 
entity dsram is generic
(
WIDTH : positive := 32;
SIZE : positive := 8
);
port
(
dat_o : out std_logic_vector(WIDTH - 1 downto 0);
adr_i : in std_logic_vector(SIZE - 1 downto 0);
ena_i : in std_logic;
dat_w_i : in std_logic_vector(WIDTH - 1 downto 0);
adr_w_i : in std_logic_vector(SIZE - 1 downto 0);
wre_i : in std_logic;
clk_i : in std_logic
);
end dsram;
 
architecture arch of dsram is
type ram_type is array(2 ** SIZE - 1 downto 0) of std_logic_vector(WIDTH - 1 downto 0);
signal ram : ram_type;
begin
process(clk_i)
begin
if rising_edge(clk_i) then
if ena_i = '1' then
if wre_i = '1' then
ram(my_conv_integer(adr_w_i)) <= dat_w_i;
end if;
dat_o <= ram(my_conv_integer(adr_i));
end if;
end if;
end process;
end arch;
/tags/vmblite_base/hw/src/rtl/mblite/std/sram.vhd
0,0 → 1,72
----------------------------------------------------------------------------------------------
--
-- Input file : sram.vhd
-- Design name : sram
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Single Port Synchronous Random Access Memory
--
----------------------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all; -- InitRamFromFile
 
library std;
use std.textio.all; -- InitRamFromFile
 
library mblite;
use mblite.std_Pkg.all;
 
entity sram is generic
(
FNAME : string;
WIDTH : positive := 32;
SIZE : positive := 16
);
port
(
dat_o : out std_logic_vector(WIDTH - 1 downto 0);
dat_i : in std_logic_vector(WIDTH - 1 downto 0);
adr_i : in std_logic_vector(SIZE - 1 downto 0);
wre_i : in std_logic;
ena_i : in std_logic;
clk_i : in std_logic
);
end sram;
 
architecture arch of sram is
type ram_type is array(2 ** SIZE - 1 downto 0) of std_logic_vector(WIDTH - 1 downto 0);
--
impure function InitRamFromFile (RamFileName : in string) return ram_type is
FILE ramfile : text is in RamFileName;
variable RamFileLine : line;
variable ram : ram_type;
variable i : natural := 0;
begin
while not endfile(ramfile) loop
readline(ramfile, RamFileLine);
hread(RamFileLine, ram(i));
i := i + 1;
end loop;
return ram;
end function;
--
signal ram : ram_type := InitRamFromFile(FNAME);
begin
process(clk_i)
begin
if rising_edge(clk_i) then
if ena_i = '1' then
if wre_i = '1' then
ram(my_conv_integer(adr_i)) <= dat_i;
end if;
dat_o <= ram(my_conv_integer(adr_i));
end if;
end if;
end process;
end arch;
/tags/vmblite_base/hw/src/rtl/mblite/std/sram_4en.vhd
0,0 → 1,65
----------------------------------------------------------------------------------------------
--
-- Input file : sram_4en.vhd
-- Design name : sram_4en
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Single Port Synchronous Random Access Memory with 4 write enable
-- ports.
--
----------------------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
library std;
use std.textio.all; -- string
 
library mblite;
use mblite.std_Pkg.all;
 
entity sram_4en is generic
(
WIDTH : positive := 32;
SIZE : positive := 16
);
port
(
dat_o : out std_logic_vector(WIDTH - 1 downto 0);
dat_i : in std_logic_vector(WIDTH - 1 downto 0);
adr_i : in std_logic_vector(SIZE - 1 downto 0);
wre_i : in std_logic_vector(WIDTH/8 - 1 downto 0);
ena_i : in std_logic;
clk_i : in std_logic
);
end sram_4en;
 
architecture arch of sram_4en is
--
type type_name is array (0 to 3) of string(1 to 8);
constant ram_fname : type_name := ("rom0.mem", "rom1.mem", "rom2.mem", "rom3.mem");
--
begin
mem: for i in 0 to WIDTH/8 - 1 generate
mem : sram
generic map
(
FNAME => ram_fname(i),
WIDTH => 8,
SIZE => SIZE
)
port map
(
dat_o => dat_o((i+1)*8 - 1 downto i*8),
dat_i => dat_i((i+1)*8 - 1 downto i*8),
adr_i => adr_i,
wre_i => wre_i(i),
ena_i => ena_i,
clk_i => clk_i
);
end generate;
end arch;
/tags/vmblite_base/hw/src/rtl/mblite/std/std_Pkg.vhd
0,0 → 1,266
----------------------------------------------------------------------------------------------
--
-- Input file : std_Pkg.vhd
-- Design name : std_Pkg
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Package with several standard components.
--
----------------------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
library std;
use std.textio.all; -- string
 
PACKAGE std_Pkg IS
 
----------------------------------------------------------------------------------------------
-- STANDARD COMPONENTS IN STD_PKG
----------------------------------------------------------------------------------------------
 
component sram generic
(
FNAME : string;
WIDTH : positive;
SIZE : positive
);
port
(
dat_o : out std_logic_vector(WIDTH - 1 downto 0);
dat_i : in std_logic_vector(WIDTH - 1 downto 0);
adr_i : in std_logic_vector(SIZE - 1 downto 0);
wre_i : in std_logic;
ena_i : in std_logic;
clk_i : in std_logic
);
end component;
 
component sram_4en generic
(
WIDTH : positive;
SIZE : positive
);
port
(
dat_o : out std_logic_vector(WIDTH - 1 downto 0);
dat_i : in std_logic_vector(WIDTH - 1 downto 0);
adr_i : in std_logic_vector(SIZE - 1 downto 0);
wre_i : in std_logic_vector(3 downto 0);
ena_i : in std_logic;
clk_i : in std_logic
);
end component;
 
component dsram generic
(
WIDTH : positive;
SIZE : positive
);
port
(
dat_o : out std_logic_vector(WIDTH - 1 downto 0);
adr_i : in std_logic_vector(SIZE - 1 downto 0);
ena_i : in std_logic;
dat_w_i : in std_logic_vector(WIDTH - 1 downto 0);
adr_w_i : in std_logic_vector(SIZE - 1 downto 0);
wre_i : in std_logic;
clk_i : in std_logic
);
end component;
 
----------------------------------------------------------------------------------------------
-- FUNCTIONS IN STD_PKG
----------------------------------------------------------------------------------------------
 
function v_or(d : std_logic_vector) return std_logic;
function is_zero(d : std_logic_vector) return std_logic;
function is_not_zero(d : std_logic_vector) return std_logic;
function my_conv_integer(a: std_logic_vector) return integer;
function notx(d : std_logic_vector) return boolean;
function compare(a, b : std_logic_vector) return std_logic;
function multiply(a, b : std_logic_vector) return std_logic_vector;
function sign_extend(value: std_logic_vector; fill: std_logic; size: positive) return std_logic_vector;
function add(a, b : std_logic_vector; ci: std_logic) return std_logic_vector;
function increment(a : std_logic_vector) return std_logic_vector;
function shift(value : std_logic_vector(31 downto 0); shamt: std_logic_vector(4 downto 0); s: std_logic; t: std_logic) return std_logic_vector;
function shift_left(value : std_logic_vector(31 downto 0); shamt : std_logic_vector(4 downto 0)) return std_logic_vector;
function shift_right(value : std_logic_vector(31 downto 0); shamt : std_logic_vector(4 downto 0); padding: std_logic) return std_logic_vector;
 
end std_Pkg;
 
PACKAGE BODY std_Pkg IS
 
-- Unary OR reduction
function v_or(d : std_logic_vector) return std_logic is
variable z : std_logic;
begin
z := '0';
if notx (d) then
for i in d'range loop
z := z or d(i);
end loop;
end if;
return z;
end;
 
-- Check for ones in the vector
function is_not_zero(d : std_logic_vector) return std_logic is
variable z : std_logic_vector(d'range);
begin
z := (others => '0');
if notx(d) then
 
if d = z then
return '0';
else
return '1';
end if;
 
else
return '0';
end if;
end;
 
-- Check for ones in the vector
function is_zero(d : std_logic_vector) return std_logic is
begin
return not is_not_zero(d);
end;
 
-- rewrite conv_integer to avoid modelsim warnings
function my_conv_integer(a : std_logic_vector) return integer is
variable res : integer range 0 to 2**a'length-1;
begin
res := 0;
if (notx(a)) then
res := to_integer(unsigned(a));
end if;
return res;
end;
 
function compare(a, b : std_logic_vector) return std_logic is
variable z : std_logic;
begin
if notx(a & b) and a = b then
return '1';
else
return '0';
end if;
end;
 
-- Unary NOT X test
function notx(d : std_logic_vector) return boolean is
variable res : boolean;
begin
res := true;
-- pragma translate_off
res := not is_x(d);
-- pragma translate_on
return (res);
end;
 
-- -- 32 bit shifter
-- -- SYNOPSIS:
-- -- value: value to be shifted
-- -- shamt: shift amount
-- -- s 0 / 1: shift right / left
-- -- t 0 / 1: shift logical / arithmetic
-- -- PSEUDOCODE (from microblaze reference guide)
-- -- if S = 1 then
-- -- (rD) = (rA) << (rB)[27:31]
-- -- else
-- -- if T = 1 then
-- -- if ((rB)[27:31]) != 0 then
-- -- (rD)[0:(rB)[27:31]-1] = (rA)[0]
-- -- (rD)[(rB)[27:31]:31] = (rA) >> (rB)[27:31]
-- -- else
-- -- (rD) = (rA)
-- -- else
-- -- (rD) = (rA) >> (rB)[27:31]
 
function shift(value: std_logic_vector(31 downto 0); shamt: std_logic_vector(4 downto 0); s: std_logic; t: std_logic) return std_logic_vector is
begin
if s = '1' then
-- left arithmetic or logical shift
return shift_left(value, shamt);
else
if t = '1' then
-- right arithmetic shift
return shift_right(value, shamt, value(31));
else
-- right logical shift
return shift_right(value, shamt, '0');
end if;
end if;
end;
 
function shift_left(value: std_logic_vector(31 downto 0); shamt: std_logic_vector(4 downto 0)) return std_logic_vector is
variable result: std_logic_vector(31 downto 0);
variable paddings: std_logic_vector(15 downto 0);
begin
paddings := (others => '0');
result := value;
if (shamt(4) = '1') then result := result(15 downto 0) & paddings(15 downto 0); end if;
if (shamt(3) = '1') then result := result(23 downto 0) & paddings( 7 downto 0); end if;
if (shamt(2) = '1') then result := result(27 downto 0) & paddings( 3 downto 0); end if;
if (shamt(1) = '1') then result := result(29 downto 0) & paddings( 1 downto 0); end if;
if (shamt(0) = '1') then result := result(30 downto 0) & paddings( 0 ); end if;
return result;
end;
 
function shift_right(value: std_logic_vector(31 downto 0); shamt: std_logic_vector(4 downto 0); padding: std_logic) return std_logic_vector is
variable result: std_logic_vector(31 downto 0);
variable paddings: std_logic_vector(15 downto 0);
begin
paddings := (others => padding);
result := value;
if (shamt(4) = '1') then result := paddings(15 downto 0) & result(31 downto 16); end if;
if (shamt(3) = '1') then result := paddings( 7 downto 0) & result(31 downto 8); end if;
if (shamt(2) = '1') then result := paddings( 3 downto 0) & result(31 downto 4); end if;
if (shamt(1) = '1') then result := paddings( 1 downto 0) & result(31 downto 2); end if;
if (shamt(0) = '1') then result := paddings( 0 ) & result(31 downto 1); end if;
return result;
end;
 
function multiply(a, b: std_logic_vector) return std_logic_vector is
variable x: std_logic_vector (a'length + b'length - 1 downto 0);
begin
x := std_logic_vector(signed(a) * signed(b));
return x(31 downto 0);
end;
 
function sign_extend(value: std_logic_vector; fill: std_logic; size: positive) return std_logic_vector is
variable a: std_logic_vector (size - 1 downto 0);
begin
a(size - 1 downto value'length) := (others => fill);
a(value'length - 1 downto 0) := value;
return a;
end;
 
function add(a, b : std_logic_vector; ci: std_logic) return std_logic_vector is
variable x : std_logic_vector(a'length + 1 downto 0);
begin
x := (others => '0');
if notx (a & b & ci) then
x := std_logic_vector(signed('0' & a & '1') + signed('0' & b & ci));
end if;
return x(a'length + 1 downto 1);
end;
 
function increment(a : std_logic_vector) return std_logic_vector is
variable x : std_logic_vector(a'length-1 downto 0);
begin
x := (others => '0');
if notx (a) then
x := std_logic_vector(signed(a) + 1);
end if;
return x;
end;
 
end std_Pkg;
/tags/vmblite_base/hw/src/rtl/mblite/config_Pkg.vhd
0,0 → 1,62
----------------------------------------------------------------------------------------------
--
-- Input file : config_Pkg.vhd
-- Design name : config_Pkg
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Configuration parameters for the design
--
----------------------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
package config_Pkg is
 
----------------------------------------------------------------------------------------------
-- CORE PARAMETERS
----------------------------------------------------------------------------------------------
-- Implement external interrupt
constant CFG_INTERRUPT : boolean := true; -- Disable or enable external interrupt [0,1]
 
-- Implement hardware multiplier
constant CFG_USE_HW_MUL : boolean := true; -- Disable or enable multiplier [0,1]
 
-- Implement hardware barrel shifter
constant CFG_USE_BARREL : boolean := true; -- Disable or enable barrel shifter [0,1]
 
-- Debug mode
constant CFG_DEBUG : boolean := true; -- Resets some extra registers for better readability
-- and enables feedback (report) [0,1]
-- Set CFG_DEBUG to zero to obtain best performance.
 
-- Memory parameters
constant CFG_DMEM_SIZE : positive := 32; -- Data memory bus size in 2LOG # elements
constant CFG_IMEM_SIZE : positive := 16; -- Instruction memory bus size in 2LOG # elements
constant CFG_BYTE_ORDER : boolean := true; -- Switch between MSB (1, default) and LSB (0) byte order policy
 
-- Register parameters
constant CFG_REG_FORCE_ZERO : boolean := true; -- Force data to zero if register address is zero [0,1]
constant CFG_REG_FWD_WRB : boolean := true; -- Forward writeback to loosen register memory requirements [0,1]
constant CFG_MEM_FWD_WRB : boolean := true; -- Forward memory result in stead of introducing stalls [0,1]
 
----------------------------------------------------------------------------------------------
-- CONSTANTS (currently not configurable / not tested)
----------------------------------------------------------------------------------------------
constant CFG_DMEM_WIDTH : positive := 32; -- Data memory width in bits
constant CFG_IMEM_WIDTH : positive := 32; -- Instruction memory width in bits
constant CFG_GPRF_SIZE : positive := 5; -- General Purpose Register File Size in 2LOG # elements
 
----------------------------------------------------------------------------------------------
-- BUS PARAMETERS
----------------------------------------------------------------------------------------------
 
type memory_map_type is array(natural range <>) of std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
constant CFG_NUM_SLAVES : positive := 2; -- [N] slaves: | <- int ->|<- ext ->|
constant CFG_MEMORY_MAP : memory_map_type(0 to CFG_NUM_SLAVES) := (X"00000000", X"0000FFFF", X"FFFFFFFF"); -- [0:65k-1], [65k:..]
 
end config_Pkg;
/tags/vmblite_base/hw/src/rtl/mblite/mblite_unit.vhd
0,0 → 1,150
----------------------------------------------------------------------------------------------
--
-- Input file :
-- Design name :
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description :
--
----------------------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
 
entity mblite_unit is port
( -- SYS_CON
sys_clk_i : in std_logic;
sys_rst_i : in std_logic;
-- IRQ
sys_int_i : in std_logic;
-- WB-master inputs from the wb-slaves
wbm_dat_i : in std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0); -- databus input
wbm_ack_i : in std_logic; -- buscycle acknowledge input
-- WB-master outputs to the wb-slaves
wbm_adr_o : out std_logic_vector(CFG_DMEM_SIZE - 1 downto 0); -- address bits
wbm_dat_o : out std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0); -- databus output
wbm_we_o : out std_logic; -- write enable output
wbm_stb_o : out std_logic; -- strobe signals
wbm_sel_o : out std_logic_vector(CFG_DMEM_WIDTH/8 - 1 downto 0); -- select output array
wbm_cyc_o : out std_logic -- valid BUS cycle output
);
end mblite_unit;
 
architecture arch of mblite_unit is
 
signal dmem_o : dmem_out_type;
signal dmem_i : dmem_in_type;
signal imem_o : imem_out_type;
signal imem_i : imem_in_type;
signal s_dmem_o : dmem_out_array_type(CFG_NUM_SLAVES - 1 downto 0);
signal s_dmem_i : dmem_in_array_type(CFG_NUM_SLAVES - 1 downto 0);
signal s_dmem_sel_o : std_logic_vector(3 downto 0);
signal s_dmem_ena_o : std_logic;
 
signal m_wb_i : wb_mst_in_type;
signal m_wb_o : wb_mst_out_type;
 
constant rom_size : integer := 16;
constant ram_size : integer := 16;
begin
 
--
-- WB route
--
wbm_adr_o <= m_wb_o.adr_o;
wbm_dat_o <= m_wb_o.dat_o;
wbm_we_o <= m_wb_o.we_o;
wbm_stb_o <= m_wb_o.stb_o;
wbm_sel_o <= m_wb_o.sel_o;
wbm_cyc_o <= m_wb_o.cyc_o;
m_wb_i.dat_i <= wbm_dat_i;
m_wb_i.ack_i <= wbm_ack_i;
m_wb_i.int_i <= sys_int_i;
m_wb_i.clk_i <= sys_clk_i;
m_wb_i.rst_i <= sys_rst_i;
 
--
-- ??
--
wb_adapter : core_wb_adapter
port map
(
dmem_i => s_dmem_i(1),
wb_o => m_wb_o,
dmem_o => s_dmem_o(1),
wb_i => m_wb_i
);
 
s_dmem_i(0).ena_i <= '1';
s_dmem_sel_o <= s_dmem_o(0).sel_o when s_dmem_o(0).we_o = '1' else (others => '0');
s_dmem_ena_o <= not sys_rst_i and s_dmem_o(0).ena_o;
 
dmem : sram_4en
generic map
(
WIDTH => CFG_DMEM_WIDTH,
SIZE => ram_size - 2
)
port map
(
dat_o => s_dmem_i(0).dat_i,
dat_i => s_dmem_o(0).dat_o,
adr_i => s_dmem_o(0).adr_o(ram_size - 1 downto 2),
wre_i => s_dmem_sel_o,
ena_i => s_dmem_ena_o,
clk_i => sys_clk_i
);
 
decoder : core_address_decoder
generic map
(
G_NUM_SLAVES => CFG_NUM_SLAVES
)
port map
(
m_dmem_i => dmem_i,
s_dmem_o => s_dmem_o,
m_dmem_o => dmem_o,
s_dmem_i => s_dmem_i,
clk_i => sys_clk_i
);
 
imem : sram
generic map
(
FNAME => "rom.mem",
WIDTH => CFG_IMEM_WIDTH,
SIZE => rom_size - 2
)
port map
(
dat_o => imem_i.dat_i,
dat_i => (others => '0'),
adr_i => imem_o.adr_o(rom_size - 1 downto 2),
wre_i => '0',
ena_i => imem_o.ena_o,
clk_i => sys_clk_i
);
 
core0 : core
port map
(
imem_o => imem_o,
dmem_o => dmem_o,
imem_i => imem_i,
dmem_i => dmem_i,
int_i => sys_int_i,
rst_i => sys_rst_i,
clk_i => sys_clk_i
);
end arch;
/tags/vmblite_base/hw/src/rtl/misc/clk_module.sv
0,0 → 1,130
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: IK
//
// Create Date:
// Design Name:
// Module Name: clk_module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
//
// Revision:
// Revision 0.01 - File Created,
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
 
module clk_module
(
// CLK-in
input i_clk_200,
// CLK-out
output o_clk_50,
// ??
input i_arst,
output o_locked
);
//////////////////////////////////////////////////////////////////////////////////
// ??
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire clkfbout_clk_wiz_0;
wire clkfbout_buf_clk_wiz_0;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
//////////////////////////////////////////////////////////////////////////////////
//
//
//
MMCME2_ADV #
(
.BANDWIDTH ("OPTIMIZED"),
.COMPENSATION ("ZHOLD"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (5.000),
.CLKFBOUT_PHASE (0.000),
.CLKOUT0_DIVIDE_F (20.000), // out-freq: 50MHz
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKIN1_PERIOD (5.000), // in-freq: 200MHz
.REF_JITTER1 (0.010)
)
mmcm_adv_inst
(
// Output clocks
.CLKFBOUT (clkfbout_clk_wiz_0),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clk_out1_clk_wiz_0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1_unused),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_clk_wiz_0),
.CLKIN1 (i_clk_200),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (o_locked),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (i_arst)
);
//////////////////////////////////////////////////////////////////////////////////
//
// CLK buffering
//
BUFG clkf_buf
(
.O (clkfbout_buf_clk_wiz_0),
.I (clkfbout_clk_wiz_0)
);
 
BUFG clkout1_buf
(
.O (o_clk_50),
.I (clk_out1_clk_wiz_0)
);
//////////////////////////////////////////////////////////////////////////////////
endmodule
/tags/vmblite_base/hw/src/rtl/misc/por_module.sv
0,0 → 1,43
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: IK
//
// Design Name:
// Module Name:
// Project Name: PowerOnReset Module
// Target Devices:
 
// Description:
//
//
// Revision:
// Revision 0.01 - File Created
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
 
module por_module #(parameter p_LEN = 0)
(
// SYS_CON
input i_clk,
// POR out
output reg o_por
);
//////////////////////////////////////////////////////////////////////////////////
// por-cnt
reg [p_LEN-1:0] sv_por_cnt=0;
//////////////////////////////////////////////////////////////////////////////////
//
// PowerOnReset logic
//
always @ (posedge i_clk)
begin : POR_LOGIC
// inner
if (!sv_por_cnt[p_LEN-1])
sv_por_cnt <= sv_por_cnt + 1'b1;
// out
o_por <= !sv_por_cnt[p_LEN-1];
end
//////////////////////////////////////////////////////////////////////////////////
endmodule
/tags/vmblite_base/hw/src/rtl/misc/rst_sync.sv
0,0 → 1,50
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: IK
//
// Create Date:
// Design Name:
// Module Name: clk_module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
//
// Revision:
// Revision 0.01 - File Created,
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
 
module rst_sync
(
// SYS_CON
input i_clk,
// iRST
input i_arst,
// oRST
output o_srst
);
//////////////////////////////////////////////////////////////////////////////////
// ??
localparam lp_RW = 4;
//////////////////////////////////////////////////////////////////////////////////
// sync-rst-chain
reg [lp_RW-1:0] sv_srst;
//////////////////////////////////////////////////////////////////////////////////
// oRST
assign o_srst = !sv_srst[lp_RW-1];
//////////////////////////////////////////////////////////////////////////////////
//
// ??
//
always @ (posedge i_clk or posedge i_arst)
begin : SRST_LOGIC
if (i_arst)
sv_srst <= 0;
else
sv_srst <= {sv_srst[2:0], 1'b1};
end
//////////////////////////////////////////////////////////////////////////////////
endmodule
/tags/vmblite_base/hw/src/rtl/wb_pio/drivers/wb_pio.c
0,0 → 1,21
 
#include "xil_types.h"
#include "wb_pio_regs.h"
#include "wb_pio.h"
 
u32 u32_wb_pio_base;
 
void wb_pio_init(int base)
{
u32_wb_pio_base = base;
}
 
int wb_pio_read(void)
{
return (IORD_WB_PIO_DATA(u32_wb_pio_base));
}
 
void wb_pio_write(int data)
{
IOWR_WB_PIO_DATA(u32_wb_pio_base, data);
}
/tags/vmblite_base/hw/src/rtl/wb_pio/drivers/wb_pio.h
0,0 → 1,17
#ifndef __WB_PIO_H__
#define __WB_PIO_H__
 
#ifdef __cplusplus
extern "C"
{
#endif
 
void wb_pio_init(int base);
int wb_pio_read(void);
void wb_pio_write(int data);
 
#ifdef __cplusplus
}
#endif
 
#endif
/tags/vmblite_base/hw/src/rtl/wb_pio/drivers/wb_pio_regs.h
0,0 → 1,15
#ifndef __WB_PIO_REGS_H__
#define __WB_PIO_REGS_H__
 
#include "xil_types.h"
#include "xil_io.h"
 
 
#define lp_PIO_IN_ADDR 0*4
#define lp_PIO_OUT_ADDR 1*4
 
#define IORD_WB_PIO_DATA(base) Xil_In32(base +lp_PIO_IN_ADDR)
#define IOWR_WB_PIO_DATA(base, data) Xil_Out32(base+lp_PIO_OUT_ADDR, (u32)data)
 
 
#endif
/tags/vmblite_base/hw/src/rtl/wb_pio/hdl/wb_pio_top.sv
0,0 → 1,96
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: IK
//
// Create Date: 11:35:01 03/21/2013
// Design Name:
// Module Name: wb_pio_top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
// simple pio-in/out, with DW-read/write
//
// WBS mem-map:
// 0: [in]
// 4: [out]
//
//
// Revision:
// Revision 0.01 - File Created,
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
 
module wb_pio_top #(parameter p_DW = 0)
(
// SYS_CON
input i_clk,
input i_srst,
// PIO
input [p_DW-1:0] iv_pio,
output reg [p_DW-1:0] ov_pio,
// WBS
input [ 3:0] iv_wbs_adr, // byte-addr
input [31:0] iv_wbs_dat,
input i_wbs_we,
input i_wbs_stb,
input [ 3:0] iv_wbs_sel, // NC, for now
input i_wbs_cyc,
output reg [31:0] ov_wbs_dat,
output reg o_wbs_ack
);
//////////////////////////////////////////////////////////////////////////////////
// mem-map def
localparam lp_IN_ADDR = 0*4; // byte-addr
localparam lp_OUT_ADDR = 1*4; // ..
 
//////////////////////////////////////////////////////////////////////////////////
// chip-select
wire s_wbs_ce;
// ireg
reg [p_DW-1:0] sv_pio_i;
//////////////////////////////////////////////////////////////////////////////////
// chip-select flag
assign s_wbs_ce = i_wbs_stb & i_wbs_cyc;
//////////////////////////////////////////////////////////////////////////////////
//
// WB-Slase
//
always @(posedge i_clk)
begin : WBS_LOGIC
if (i_srst)
begin : RST
ov_wbs_dat <= 0;
o_wbs_ack <= 0;
ov_pio <= 0;
end
else
begin : WRK
// wb-write
if (s_wbs_ce & i_wbs_we & (iv_wbs_adr == lp_OUT_ADDR))
ov_pio <= iv_wbs_dat;
// wb-read
case(iv_wbs_adr)
lp_IN_ADDR : ov_wbs_dat <= sv_pio_i;
lp_OUT_ADDR : ov_wbs_dat <= ov_pio;
default : ov_wbs_dat <= 0;
endcase
// wb-ask
o_wbs_ack <= (s_wbs_ce)? !o_wbs_ack :
1'b0 ;
end
end
//////////////////////////////////////////////////////////////////////////////////
//
// In-REG
//
always @(posedge i_clk)
begin : IREG_LOGIC
sv_pio_i <= iv_pio;
end
//////////////////////////////////////////////////////////////////////////////////
endmodule
/tags/vmblite_base/hw/src/rtl/wb_uart/drivers/wb_uart.c
0,0 → 1,48
 
#include "xil_types.h"
#include "wb_uart_regs.h"
#include "wb_uart.h"
 
u32 u32_wb_uart_base;
 
void wb_uart_init(int base)
{
u32_wb_uart_base = (u32)base;
}
 
/* sync */
int wb_uart_read_s(void)
{
int rxd;
 
IORD_WB_UART_STS(u32_wb_uart_base);
while (WB_UART_RX_EF(u32_wb_uart_base));
rxd = (IORD_WB_UART_DATA(u32_wb_uart_base) & 0xFF);
return (rxd);
}
void wb_uart_write_s(int data)
{
IORD_WB_UART_STS(u32_wb_uart_base);
while (WB_UART_TX_BUSY(u32_wb_uart_base));
IOWR_WB_UART_DATA(u32_wb_uart_base, data);
}
/* async */
int wb_uart_read_a(void)
{
if (WB_UART_RX_EF(u32_wb_uart_base)) {
return -1;
}
else {
int rxd = IORD_WB_UART_DATA(u32_wb_uart_base) & 0xFF;
return (rxd);
}
}
int wb_uart_write_a(int data)
{
if (WB_UART_TX_BUSY(u32_wb_uart_base)) {
return -1;
} else {
IOWR_WB_UART_DATA(u32_wb_uart_base, data);
return 0;
}
}
/tags/vmblite_base/hw/src/rtl/wb_uart/drivers/wb_uart.h
0,0 → 1,21
#ifndef __WB_UART_H__
#define __WB_UART_H__
 
#ifdef __cplusplus
extern "C"
{
#endif /* __cplusplus */
 
void wb_uart_init(int base);
/* sync */
int wb_uart_read_s(void);
void wb_uart_write_s(int data);
/* async */
int wb_uart_read_a(void);
int wb_uart_write_a(int data);
 
#ifdef __cplusplus
}
#endif /* __cplusplus */
 
#endif /* __WB_UART_H__ */
/tags/vmblite_base/hw/src/rtl/wb_uart/drivers/wb_uart_regs.h
0,0 → 1,21
#ifndef __WB_UART_REGS_H__
#define __WB_UART_REGS_H__
 
#include "xil_types.h"
#include "xil_io.h"
 
/* mem-map: */
#define lp_UART_RXD_ADDR 0*4 /* byte-addr */
#define lp_UART_TXD_ADDR 1*4
#define lp_UART_STS_ADDR 2*4
 
/* */
#define IORD_WB_UART_DATA(base) Xil_In32(base +lp_UART_RXD_ADDR)
#define IOWR_WB_UART_DATA(base, data) Xil_Out32(base+lp_UART_TXD_ADDR, (u32)data)
#define IORD_WB_UART_STS(base) Xil_In32(base +lp_UART_STS_ADDR)
/* */
#define WB_UART_TX_BUSY(base) (IORD_WB_UART_STS(base) & 0x01)
#define WB_UART_RX_EF(base) (IORD_WB_UART_STS(base) & 0x02)
 
 
#endif /* __WB_UART_REGS_H__ */
/tags/vmblite_base/hw/src/rtl/wb_uart/hdl/async.v
0,0 → 1,201
////////////////////////////////////////////////////////
// RS-232 RX and TX module
// (c) fpga4fun.com & KNJN LLC - 2003 to 2013
 
// The RS-232 settings are fixed
// TX: 8-bit data, 2 stop, no-parity
// RX: 8-bit data, 1 stop, no-parity (the receiver can accept more stop bits of course)
 
//`define SIMULATION // in this mode, TX outputs one bit per clock cycle
// and RX receives one bit per clock cycle (for fast simulations)
 
////////////////////////////////////////////////////////
module async_transmitter(
input clk,
input TxD_start,
input [7:0] TxD_data,
output TxD,
output TxD_busy
);
 
// Assert TxD_start for (at least) one clock cycle to start transmission of TxD_data
// TxD_data is latched so that it doesn't have to stay valid while it is being sent
 
parameter ClkFrequency = 25000000; // 25MHz
parameter Baud = 115200;
 
generate
if(ClkFrequency<Baud*8 && (ClkFrequency % Baud!=0)) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Frequency incompatible with requested Baud rate");
endgenerate
 
////////////////////////////////
`ifdef SIMULATION
wire BitTick = 1'b1; // output one bit per clock cycle
`else
wire BitTick;
BaudTickGen #(ClkFrequency, Baud) tickgen(.clk(clk), .enable(TxD_busy), .tick(BitTick));
`endif
 
reg [3:0] TxD_state = 0;
wire TxD_ready = (TxD_state==0);
assign TxD_busy = ~TxD_ready;
 
reg [7:0] TxD_shift = 0;
always @(posedge clk)
begin
if(TxD_ready & TxD_start)
TxD_shift <= TxD_data;
else
if(TxD_state[3] & BitTick)
TxD_shift <= (TxD_shift >> 1);
 
case(TxD_state)
4'b0000: if(TxD_start) TxD_state <= 4'b0100;
4'b0100: if(BitTick) TxD_state <= 4'b1000; // start bit
4'b1000: if(BitTick) TxD_state <= 4'b1001; // bit 0
4'b1001: if(BitTick) TxD_state <= 4'b1010; // bit 1
4'b1010: if(BitTick) TxD_state <= 4'b1011; // bit 2
4'b1011: if(BitTick) TxD_state <= 4'b1100; // bit 3
4'b1100: if(BitTick) TxD_state <= 4'b1101; // bit 4
4'b1101: if(BitTick) TxD_state <= 4'b1110; // bit 5
4'b1110: if(BitTick) TxD_state <= 4'b1111; // bit 6
4'b1111: if(BitTick) TxD_state <= 4'b0010; // bit 7
4'b0010: if(BitTick) TxD_state <= 4'b0011; // stop1
4'b0011: if(BitTick) TxD_state <= 4'b0000; // stop2
default: if(BitTick) TxD_state <= 4'b0000;
endcase
end
 
assign TxD = (TxD_state<4) | (TxD_state[3] & TxD_shift[0]); // put together the start, data and stop bits
endmodule
 
 
////////////////////////////////////////////////////////
module async_receiver(
input clk,
input RxD,
output reg RxD_data_ready = 0,
output reg [7:0] RxD_data = 0, // data received, valid only (for one clock cycle) when RxD_data_ready is asserted
 
// We also detect if a gap occurs in the received stream of characters
// That can be useful if multiple characters are sent in burst
// so that multiple characters can be treated as a "packet"
output RxD_idle, // asserted when no data has been received for a while
output reg RxD_endofpacket = 0 // asserted for one clock cycle when a packet has been detected (i.e. RxD_idle is going high)
);
 
parameter ClkFrequency = 25000000; // 25MHz
parameter Baud = 115200;
 
parameter Oversampling = 8; // needs to be a power of 2
// we oversample the RxD line at a fixed rate to capture each RxD data bit at the "right" time
// 8 times oversampling by default, use 16 for higher quality reception
 
generate
if(ClkFrequency<Baud*Oversampling) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Frequency too low for current Baud rate and oversampling");
if(Oversampling<8 || ((Oversampling & (Oversampling-1))!=0)) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Invalid oversampling value");
endgenerate
 
////////////////////////////////
reg [3:0] RxD_state = 0;
 
`ifdef SIMULATION
wire RxD_bit = RxD;
wire sampleNow = 1'b1; // receive one bit per clock cycle
 
`else
wire OversamplingTick;
BaudTickGen #(ClkFrequency, Baud, Oversampling) tickgen(.clk(clk), .enable(1'b1), .tick(OversamplingTick));
 
// synchronize RxD to our clk domain
reg [1:0] RxD_sync = 2'b11;
always @(posedge clk) if(OversamplingTick) RxD_sync <= {RxD_sync[0], RxD};
 
// and filter it
reg [1:0] Filter_cnt = 2'b11;
reg RxD_bit = 1'b1;
 
always @(posedge clk)
if(OversamplingTick)
begin
if(RxD_sync[1]==1'b1 && Filter_cnt!=2'b11) Filter_cnt <= Filter_cnt + 1'd1;
else
if(RxD_sync[1]==1'b0 && Filter_cnt!=2'b00) Filter_cnt <= Filter_cnt - 1'd1;
 
if(Filter_cnt==2'b11) RxD_bit <= 1'b1;
else
if(Filter_cnt==2'b00) RxD_bit <= 1'b0;
end
 
// and decide when is the good time to sample the RxD line
function integer log2(input integer v); begin log2=0; while(v>>log2) log2=log2+1; end endfunction
localparam l2o = log2(Oversampling);
reg [l2o-2:0] OversamplingCnt = 0;
always @(posedge clk) if(OversamplingTick) OversamplingCnt <= (RxD_state==0) ? 1'd0 : OversamplingCnt + 1'd1;
wire sampleNow = OversamplingTick && (OversamplingCnt==Oversampling/2-1);
`endif
 
// now we can accumulate the RxD bits in a shift-register
always @(posedge clk)
case(RxD_state)
4'b0000: if(~RxD_bit) RxD_state <= `ifdef SIMULATION 4'b1000 `else 4'b0001 `endif; // start bit found?
4'b0001: if(sampleNow) RxD_state <= 4'b1000; // sync start bit to sampleNow
4'b1000: if(sampleNow) RxD_state <= 4'b1001; // bit 0
4'b1001: if(sampleNow) RxD_state <= 4'b1010; // bit 1
4'b1010: if(sampleNow) RxD_state <= 4'b1011; // bit 2
4'b1011: if(sampleNow) RxD_state <= 4'b1100; // bit 3
4'b1100: if(sampleNow) RxD_state <= 4'b1101; // bit 4
4'b1101: if(sampleNow) RxD_state <= 4'b1110; // bit 5
4'b1110: if(sampleNow) RxD_state <= 4'b1111; // bit 6
4'b1111: if(sampleNow) RxD_state <= 4'b0010; // bit 7
4'b0010: if(sampleNow) RxD_state <= 4'b0000; // stop bit
default: RxD_state <= 4'b0000;
endcase
 
always @(posedge clk)
if(sampleNow && RxD_state[3]) RxD_data <= {RxD_bit, RxD_data[7:1]};
 
//reg RxD_data_error = 0;
always @(posedge clk)
begin
RxD_data_ready <= (sampleNow && RxD_state==4'b0010 && RxD_bit); // make sure a stop bit is received
//RxD_data_error <= (sampleNow && RxD_state==4'b0010 && ~RxD_bit); // error if a stop bit is not received
end
 
`ifndef SIMULATION
reg [l2o+1:0] GapCnt = 0;
always @(posedge clk) if (RxD_state!=0) GapCnt<=0; else if(OversamplingTick & ~GapCnt[log2(Oversampling)+1]) GapCnt <= GapCnt + 1'h1;
assign RxD_idle = GapCnt[l2o+1];
always @(posedge clk) RxD_endofpacket <= OversamplingTick & ~GapCnt[l2o+1] & &GapCnt[l2o:0];
`else
assign RxD_idle = 0;
`endif // SIMULATION
endmodule
 
 
////////////////////////////////////////////////////////
// dummy module used to be able to raise an assertion in Verilog
module ASSERTION_ERROR();
endmodule
 
 
////////////////////////////////////////////////////////
module BaudTickGen(
input clk, enable,
output tick // generate a tick at the specified baud rate * oversampling
);
parameter ClkFrequency = 25000000;
parameter Baud = 115200;
parameter Oversampling = 1;
 
function integer log2(input integer v); begin log2=0; while(v>>log2) log2=log2+1; end endfunction
localparam AccWidth = log2(ClkFrequency/Baud)+8; // +/- 2% max timing error over a byte
reg [AccWidth:0] Acc = 0;
localparam ShiftLimiter = log2(Baud*Oversampling >> (31-AccWidth)); // this makes sure Inc calculation doesn't overflow
localparam Inc = ((Baud*Oversampling << (AccWidth-ShiftLimiter))+(ClkFrequency>>(ShiftLimiter+1)))/(ClkFrequency>>ShiftLimiter);
always @(posedge clk) if(enable) Acc <= Acc[AccWidth-1:0] + Inc[AccWidth:0]; else Acc <= Inc[AccWidth:0];
assign tick = Acc[AccWidth];
endmodule
 
 
////////////////////////////////////////////////////////
/tags/vmblite_base/hw/src/rtl/wb_uart/hdl/wb_uart_mscfifo.v
0,0 → 1,144
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: IK
//
// Create Date:
// Design Name:
// Module Name: wb_uart_mscfifo
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// single clock FWFT FIFO
//
//
//
// Revision:
// Revision 0.01 - File Created,
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
 
module wb_uart_mscfifo #(parameter p_DW = 0, p_AW = 0)
(
// SYS_CON
input i_clk,
input i_arst,
// DIN
input i_wr,
input [p_DW-1:0] iv_data,
// DOUT
input i_rd,
output [p_DW-1:0] ov_data,
// STS-OUT
output [p_AW-1:0] ov_count,
output o_full,
output reg o_empty
);
//////////////////////////////////////////////////////////////////////////////////
// LEN
reg [p_AW-1:0] sv_length;
wire s_last_data;
// ADDR
reg [p_AW-1:0] sv_raddr;
reg [p_AW-1:0] sv_waddr;
wire s_rd;
reg s_1st_wr;
// FWFT
reg s_fwft_flag;
reg [p_DW-1:0] sv_fwft_data;
// BRAM
wire [p_DW-1:0] sv_data_bram;
//////////////////////////////////////////////////////////////////////////////////
// LAST-DATA flag
assign s_last_data = (sv_length == 1);
// inner-RD
assign s_rd = s_1st_wr | (i_rd & ((!s_last_data & !o_empty) | i_wr));
//
// DOUT
assign ov_data = (s_fwft_flag)? sv_fwft_data : sv_data_bram;
// FF
assign o_full = (sv_length == {p_AW{1'b1}});
// CNT
assign ov_count = sv_length;
//////////////////////////////////////////////////////////////////////////////////
//
// Construct FIFO-CTRL logic
//
always @ (posedge i_clk or posedge i_arst)
begin : FIFO_CTRL_LOGIC
if (i_arst)
begin : RST
sv_length <= 0;
s_1st_wr <= 0;
sv_raddr <= 0;
sv_waddr <= 0;
s_fwft_flag <= 0;
sv_fwft_data <= 0;
end
else
begin : WRK
// FIFO-LEN
if (i_wr & !i_rd & !o_full)
sv_length <= sv_length + 1'b1;
else if (!i_wr & i_rd & !o_empty)
sv_length <= sv_length - 1'b1;
// 1st-wr flag (in empty fifo)
s_1st_wr <= i_wr & (sv_length == 0);
// rd-addr
if (s_rd)
sv_raddr <= sv_raddr + 1'b1;
// wr-addr
if (i_wr)
sv_waddr <= sv_waddr + 1'b1;
// fwft-flag
if (i_rd & !i_wr)
s_fwft_flag <= 0;
else if (i_rd & i_wr & s_last_data)
s_fwft_flag <= 1;
// fwft-data
if (i_rd & i_wr & s_last_data)
sv_fwft_data <= iv_data;
end
end
//////////////////////////////////////////////////////////////////////////////////
//
// Construct EF
//
always @ (posedge i_clk or posedge i_arst)
begin : EF_LOGIC
if (i_arst)
begin : RST
o_empty <= 1;
end
else
begin : WRK
if (s_1st_wr)
o_empty <= 0;
else if (i_rd & !i_wr & s_last_data)
o_empty <= 1;
end
end
//////////////////////////////////////////////////////////////////////////////////
//
// Instantiate BRAM
//
sdpram #(p_DW, p_AW) // p_DW, p_AW
U_SDPRAM
(
// SYS_CON
.i_clk (i_clk),
// IN / port-a
.i_we_a (i_wr),
.iv_addr_a (sv_waddr),
.iv_data_a (iv_data),
// OUT / port-b
.i_rd_b (s_rd),
.iv_addr_b (sv_raddr),
.ov_data_b (sv_data_bram)
);
//////////////////////////////////////////////////////////////////////////////////
endmodule
/tags/vmblite_base/hw/src/rtl/wb_uart/hdl/wb_uart_sdpram.v
0,0 → 1,65
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: IK
//
// Create Date: 11:35:01 03/21/2013
// Design Name:
// Module Name: sdpram
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// MEM for FIFO
//
// USE "ram_style" for XILINX
// USE "ramstyle" for ALTERA
//
// Because FIFO-VOLUME quite small (8 is enought)
// -> no reasons for wasting BRAM on this [use LUTs]
//
// [
// q2 synth anyway will implement this mem on LUTs,
// becasue of small volume,
// but attr present for any case
// ]
//
// Revision:
// Revision 0.01 - File Created,
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
 
module sdpram #(parameter p_DW = 0, parameter p_AW = 0)
(
// SYS_CON
input i_clk,
// IN / port-a
input i_we_a,
input [p_AW-1:0] iv_addr_a,
input [p_DW-1:0] iv_data_a,
// OUT / port-b
input i_rd_b,
input [p_AW-1:0] iv_addr_b,
output reg [p_DW-1:0] ov_data_b
);
//////////////////////////////////////////////////////////////////////////////////
//synthesis attribute ram_style of sv_mem is distributed
reg [p_DW-1:0] sv_mem [2**p_AW-1:0] /* synthesis ramstyle = "logic" */;
//////////////////////////////////////////////////////////////////////////////////
//
// Construct "Simple Dual Port RAM" logic
//
always @ (posedge i_clk)
begin : RAM_LOGIC
// IN / port-a
if (i_we_a)
sv_mem[iv_addr_a] <= iv_data_a;
// OUT / port-b
if (i_rd_b)
ov_data_b <= sv_mem[iv_addr_b];
end
//////////////////////////////////////////////////////////////////////////////////
endmodule
/tags/vmblite_base/hw/src/rtl/wb_uart/hdl/wb_uart_slv.sv
0,0 → 1,102
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: IK
//
// Create Date: 11:35:01 03/21/2013
// Design Name:
// Module Name: wb_uart_slv
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
//
//
//
// Revision:
// Revision 0.01 - File Created,
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
 
module wb_uart_slv
(
// SYS_CON
input i_clk,
input i_srst,
// WBS
input [ 3:0] iv_wbs_adr, // byte-addr
input [31:0] iv_wbs_dat,
input i_wbs_we,
input i_wbs_stb,
input [ 3:0] iv_wbs_sel, // NC, for now
input i_wbs_cyc,
output reg [31:0] ov_wbs_dat,
output reg o_wbs_ack,
// out-ctrl
output o_ctrl_utx_start,
output [ 7:0] o_ctrl_utx_data,
output o_ctrl_rfifo_rd,
// in-sts
input i_sts_utx_busy,
input i_sts_rfifo_ef,
input [ 7:0] iv_sts_rfifo_data
);
//////////////////////////////////////////////////////////////////////////////////
// mem-map:
localparam lp_RXD_ADDR = 0*4; // byte-addr
localparam lp_TXD_ADDR = 1*4;
localparam lp_STS_ADDR = 2*4;
 
//////////////////////////////////////////////////////////////////////////////////
// csr
logic [31:0] sv_reg_sts;
// wb chip-select
wire s_wbs_ce;
//////////////////////////////////////////////////////////////////////////////////
// chip-select flag
assign s_wbs_ce = i_wbs_stb & i_wbs_cyc;
//
//
assign o_ctrl_utx_start = o_wbs_ack & (iv_wbs_adr == lp_TXD_ADDR);
assign o_ctrl_utx_data = iv_wbs_dat[7:0];
assign o_ctrl_rfifo_rd = o_wbs_ack & (iv_wbs_adr == lp_RXD_ADDR);
//////////////////////////////////////////////////////////////////////////////////
//
// WB-Slase
//
always @(posedge i_clk)
begin : WBS_LOGIC
if (i_srst)
begin : RST
ov_wbs_dat <= 0;
o_wbs_ack <= 0;
end
else
begin : WRK
// wb-write
// wb-read
case(iv_wbs_adr)
lp_RXD_ADDR : ov_wbs_dat <= iv_sts_rfifo_data;
lp_STS_ADDR : ov_wbs_dat <= sv_reg_sts;
default : ov_wbs_dat <= 0;
endcase
// wb-ask
o_wbs_ack <= (s_wbs_ce)? !o_wbs_ack :
1'b0 ;
end
end
 
always @(*)
begin : STATUS_LOGIC
// status
sv_reg_sts <= 0;
sv_reg_sts[0] <= i_sts_utx_busy;
sv_reg_sts[1] <= i_sts_rfifo_ef;
end
//////////////////////////////////////////////////////////////////////////////////
endmodule
/tags/vmblite_base/hw/src/rtl/wb_uart/hdl/wb_uart_top.sv
0,0 → 1,145
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: IK
//
// Create Date: 11:35:01 03/21/2013
// Design Name:
// Module Name: wb_uart_top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
//
// WBS mem-map:
//
//
//
//
// Revision:
// Revision 0.01 - File Created,
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
 
module wb_uart_top #
(
parameter p_FDEPTH = 0, // fifo-depth
parameter p_FREQ = 0, // input clk-freq
parameter p_BAUD = 0 // uaart baud-rate
)
(
// SYS_CON
input i_clk,
input i_srst,
// WBS [i_clk]
input [ 3:0] iv_wbs_adr, // byte-addr
input [31:0] iv_wbs_dat,
input i_wbs_we,
input i_wbs_stb,
input [ 3:0] iv_wbs_sel, // NC, for now
input i_wbs_cyc,
output [31:0] ov_wbs_dat,
output o_wbs_ack,
// UART [async]
input i_uart_rxd,
output reg o_uart_txd
);
//////////////////////////////////////////////////////////////////////////////////
// ctrl
wire s_ctrl_utx_start;
wire [ 7:0] s_ctrl_utx_data;
wire s_ctrl_rfifo_rd;
// sts
wire s_sts_utx_busy;
wire s_sts_rfifo_ef;
wire [ 7:0] sv_sts_rfifo_data;
// U_RX-if
wire s_urx_ready;
wire [ 7:0] sv_urx_data;
// U_TX
wire s_uart_txd;
//////////////////////////////////////////////////////////////////////////////////
//
// WBS
//
wb_uart_slv U_WBS
(
// SYS_CON
.i_clk (i_clk),
.i_srst (i_srst),
// WBS
.iv_wbs_adr (iv_wbs_adr), // byte-addr
.iv_wbs_dat (iv_wbs_dat),
.i_wbs_we (i_wbs_we),
.i_wbs_stb (i_wbs_stb),
.iv_wbs_sel (iv_wbs_sel),
.i_wbs_cyc (i_wbs_cyc),
.ov_wbs_dat (ov_wbs_dat),
.o_wbs_ack (o_wbs_ack),
// out-ctrl
.o_ctrl_utx_start (s_ctrl_utx_start),
.o_ctrl_utx_data (s_ctrl_utx_data),
.o_ctrl_rfifo_rd (s_ctrl_rfifo_rd),
// in-sts
.i_sts_utx_busy (s_sts_utx_busy),
.i_sts_rfifo_ef (s_sts_rfifo_ef),
.iv_sts_rfifo_data (sv_sts_rfifo_data)
);
//////////////////////////////////////////////////////////////////////////////////
//
// RX-FIFO
//
wb_uart_mscfifo #(8, $clog2(p_FDEPTH)) // p_DW, p_AW
U_RFIFO
(
// SYS_CON
.i_clk (i_clk),
.i_arst (i_srst),
// DIN
.i_wr (s_urx_ready),
.iv_data (sv_urx_data),
// DOUT
.i_rd (s_ctrl_rfifo_rd),
.ov_data (sv_sts_rfifo_data),
// STS-OUT
.ov_count (),
.o_full (),
.o_empty (s_sts_rfifo_ef)
);
//////////////////////////////////////////////////////////////////////////////////
//
// UART modules
//
async_transmitter #(p_FREQ, p_BAUD) // ClkFrequency, Baud
U_TX
(
// SYS_CON
.clk (i_clk),
// if
.TxD_start (s_ctrl_utx_start),
.TxD_data (s_ctrl_utx_data),
.TxD_busy (s_sts_utx_busy),
// out
.TxD (s_uart_txd) // output == LUT-out
);
always @(posedge i_clk) // top-output == REG-out
o_uart_txd <= s_uart_txd;
 
async_receiver #(p_FREQ, p_BAUD) // ClkFrequency, Baud
U_RX
(
// SYS_CON
.clk (i_clk),
// if
.RxD_data_ready (s_urx_ready),
.RxD_data (sv_urx_data),
// in
.RxD (i_uart_rxd),
// nc
.RxD_idle (),
.RxD_endofpacket ()
);
//////////////////////////////////////////////////////////////////////////////////
endmodule
/tags/vmblite_base/hw/src/rtl/mblite_soc.sv
0,0 → 1,183
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: IK
//
// Create Date: 11:35:01 03/21/2013
// Design Name:
// Module Name: mblite_soc
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// SoC mem-map:
// pu-internal: below 64KB
// pu-external: above 64KB
//
// pu-external details:
// 0x010000 - PIO / 4KB
// 0x010FFF
//
// 0x011000 - UART / 4KB
// 0x011FFF
//
//
// Revision:
// Revision 0.01 - File Created,
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
 
module mblite_soc
(
// SYS_CON
input i_clk_50, // 50MHz
input i_arst,
// UART [async]
input i_uart_rxd,
output o_uart_txd,
// GPIO [async]
input [ 7:0] iv_gpio, // BUTTON
output [ 7:0] ov_gpio // LED
);
//////////////////////////////////////////////////////////////////////////////////
// qnty of wbs
localparam lp_NWBS = 2;
 
//////////////////////////////////////////////////////////////////////////////////
// SYS_CON
wire s_sys_rst;
// U_MBLITE.WBM
wire [31:0] sv_wbm_adr_o;
wire [31:0] sv_wbm_dat_o;
wire s_wbm_we_o;
wire s_wbm_stb_o;
wire [ 3:0] sv_wbm_sel_o;
wire s_wbm_cyc_o;
wire [ 3:0] s_mwb_sel_o;
wire [31:0] sv_wbm_dat_i;
wire s_wbm_ack_i;
// WB-Slaves
wire [16:0] sv_wbs_iadr[lp_NWBS];
wire [31:0] sv_wbs_idat[lp_NWBS];
wire [lp_NWBS-1:0] sv_wbs_iwe;
wire [lp_NWBS-1:0] sv_wbs_istb;
wire [ 3:0] sv_wbs_isel[lp_NWBS];
wire [lp_NWBS-1:0] sv_wbs_icyc;
wire [31:0] sv_wbs_odat[lp_NWBS];
wire [lp_NWBS-1:0] sv_wbs_oack;
// WB-Cross
wire [lp_NWBS-1:0] sv_wbc_cs;
//////////////////////////////////////////////////////////////////////////////////
//
// RST_SYNC
//
rst_sync U_SRST
(
// SYS_CON
.i_clk (i_clk_50),
// iRST
.i_arst (i_arst),
// oRST
.o_srst (s_sys_rst)
);
//////////////////////////////////////////////////////////////////////////////////
//
// WBS[0]: PIO
//
wb_pio_top #(8) // p_DW
U_PIO
(
// SYS_CON
.i_clk (i_clk_50),
.i_srst (s_sys_rst),
// PIO
.iv_pio (iv_gpio),
.ov_pio (ov_gpio),
// WBS
.iv_wbs_adr (sv_wbs_iadr[0][3:0]), // byte-addr
.iv_wbs_dat (sv_wbs_idat[0]),
.i_wbs_we (sv_wbs_iwe[0]),
.i_wbs_stb (sv_wbs_istb[0]),
.iv_wbs_sel (sv_wbs_isel[0]),
.i_wbs_cyc (sv_wbs_icyc[0]),
.ov_wbs_dat (sv_wbs_odat[0]),
.o_wbs_ack (sv_wbs_oack[0])
);
//////////////////////////////////////////////////////////////////////////////////
//
// WBS[1]: UART
//
wb_uart_top #(64, 50_000_000, 115_200) // p_FDEPTH, p_FREQ, p_BAUD
U_UART
(
// SYS_CON
.i_clk (i_clk_50),
.i_srst (s_sys_rst),
// WBS [i_clk]
.iv_wbs_adr (sv_wbs_iadr[1][3:0]), // byte-addr
.iv_wbs_dat (sv_wbs_idat[1]),
.i_wbs_we (sv_wbs_iwe[1]),
.i_wbs_stb (sv_wbs_istb[1]),
.i_wbs_cyc (sv_wbs_icyc[1]),
.iv_wbs_sel (sv_wbs_isel[1]),
.ov_wbs_dat (sv_wbs_odat[1]),
.o_wbs_ack (sv_wbs_oack[1]),
// UART [async]
.i_uart_rxd (i_uart_rxd),
.o_uart_txd (o_uart_txd)
);
//////////////////////////////////////////////////////////////////////////////////
//
// WBM: MB-Lite unit
// => pu + imem + dmem
//
mblite_unit U_MBLITE
(
// SYS_CON
.sys_clk_i (i_clk_50),
.sys_rst_i (s_sys_rst),
// IRQ
.sys_int_i (1'b0), // interrupt input
// WB-master inputs from the wb-slaves
.wbm_dat_i (sv_wbm_dat_i), // databus input
.wbm_ack_i (s_wbm_ack_i), // buscycle acknowledge input
// WB-master outputs to the wb-slaves
.wbm_adr_o (sv_wbm_adr_o), // address bits
.wbm_dat_o (sv_wbm_dat_o), // databus output
.wbm_we_o (s_wbm_we_o), // write enable output
.wbm_stb_o (s_wbm_stb_o), // strobe signals
.wbm_sel_o (sv_wbm_sel_o), // select output array
.wbm_cyc_o (s_wbm_cyc_o) // valid BUS cycle output
);
//////////////////////////////////////////////////////////////////////////////////
//
// WB-Cross
// simple: {1 WB-Master} + {N WB-Slave}
//
assign sv_wbc_cs[0] = sv_wbm_adr_o[16:12] == 5'h10; // 0x010000
assign sv_wbc_cs[1] = sv_wbm_adr_o[16:12] == 5'h11; // 0x011000
 
assign sv_wbs_iwe[0] = s_wbm_we_o;
assign sv_wbs_iadr[0] = sv_wbm_adr_o;
assign sv_wbs_idat[0] = sv_wbm_dat_o;
assign sv_wbs_istb[0] = s_wbm_stb_o;
assign sv_wbs_isel[0] = sv_wbm_sel_o;
assign sv_wbs_icyc[0] = s_wbm_cyc_o & sv_wbc_cs[0];
 
assign sv_wbs_iwe[1] = s_wbm_we_o;
assign sv_wbs_iadr[1] = sv_wbm_adr_o;
assign sv_wbs_idat[1] = sv_wbm_dat_o;
assign sv_wbs_istb[1] = s_wbm_stb_o;
assign sv_wbs_isel[1] = sv_wbm_sel_o;
assign sv_wbs_icyc[1] = s_wbm_cyc_o & sv_wbc_cs[1];
 
 
assign sv_wbm_dat_i = (sv_wbc_cs[0])? sv_wbs_odat[0] :
sv_wbs_odat[1] ;
assign s_wbm_ack_i = (sv_wbc_cs[0])? sv_wbs_oack[0] :
sv_wbs_oack[1] ;
//////////////////////////////////////////////////////////////////////////////////
endmodule
/tags/vmblite_base/hw/src/rtl/mblite_top.sv
0,0 → 1,98
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: IK
//
// Create Date:
// Design Name:
// Module Name: mblite_top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
// KC705 FPGA design
//
// Revision:
// Revision 0.01 - File Created,
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
 
module mblite_top
(
//SYS_CON
input sys_diff_clock_clk_p, // 200MHz clock input from board
input sys_diff_clock_clk_n,
// LEG
output [ 7:0] led_8bits_tri_o,
// UART
input rs232_uart_rxd,
output rs232_uart_txd
);
//////////////////////////////////////////////////////////////////////////////////
// reset
wire s_por;
wire s_rst;
// clk_module
wire s_clk_200;
wire s_locked;
//////////////////////////////////////////////////////////////////////////////////
// RST
assign s_rst = s_por | !s_locked;
//////////////////////////////////////////////////////////////////////////////////
//
// ??
//
IBUFDS U_IBUFDS
(
.O (s_clk_200),
.I (sys_diff_clock_clk_p),
.IB (sys_diff_clock_clk_n)
);
//////////////////////////////////////////////////////////////////////////////////
//
// POR
//
por_module #(8) // p_LEN
U_POR
(
// SYS_CON
.i_clk (s_clk_200),
// POR out
.o_por (s_por)
);
 
//////////////////////////////////////////////////////////////////////////////////
//
// Clocking Block
//
clk_module U_CB
(
// CLK-in
.i_clk_200 (s_clk_200),
// CLK-out
.o_clk_50 (s_clk_50),
// ??
.i_arst (s_por),
.o_locked (s_locked)
);
//////////////////////////////////////////////////////////////////////////////////
//
//
//
mblite_soc u0
(
// SYS_CON
.i_clk_50 (s_clk_50), // 50MHz
.i_arst (s_rst),
// UART [async]
.i_uart_rxd (rs232_uart_rxd),
.o_uart_txd (rs232_uart_txd),
// GPIO [async]
.iv_gpio (8'b0), // BUTTON
.ov_gpio (led_8bits_tri_o) // LED
);
//////////////////////////////////////////////////////////////////////////////////
endmodule
 
/tags/vmblite_base/hw/src/tb/tb.sv
0,0 → 1,150
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: IK
//
// Create Date: 11:35:01 03/21/2013
// Design Name:
// Module Name: tb
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
//
// Revision:
// Revision 0.01 - File Created,
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
 
module tb;
//////////////////////////////////////////////////////////////////////////////////
//
parameter p_Tclk = 5ns; // 200MHz
parameter p_Trst = 120ns;
 
//////////////////////////////////////////////////////////////////////////////////
// SYS_CON
reg s_sys_clk;
reg s_rst;
//////////////////////////////////////////////////////////////////////////////////
//
//
//
always
begin : SYS_CLK
#(p_Tclk / 2.0) s_sys_clk <= !s_sys_clk;
end
 
initial
begin : init_POR
//
// clr
s_sys_clk = 0;
s_rst = 0;
// Final
end
//////////////////////////////////////////////////////////////////////////////////
//
// Instantiate DUT
//
mblite_top dut
(
//SYS_CON
.sys_diff_clock_clk_p ( s_sys_clk), // 200MHz clock input from board
.sys_diff_clock_clk_n (!s_sys_clk),
// LEG
.led_8bits_tri_o (),
// UART
.rs232_uart_rxd (1'b1),
.rs232_uart_txd ()
);
//////////////////////////////////////////////////////////////////////////////////
//
// UART BFM
//
uart_rx_if U_RXD (dut.rs232_uart_txd);
 
initial
begin : UART_RX
U_RXD.init();
#(p_Trst);
forever
U_RXD.rxd();
end
//////////////////////////////////////////////////////////////////////////////////
//
//
//
initial
begin : GPIO_POLL
#(p_Trst);
forever
begin : WRK
@(dut.led_8bits_tri_o);
$display("[%t]: %m: dut-gpio=%x", $time, dut.led_8bits_tri_o);
end
end
//////////////////////////////////////////////////////////////////////////////////
//
// {BREAK ON CPU-EXIT}
//
`ifndef GATE_LEVEL
initial
begin : _CPU // !!!RTL-sim
#(p_Trst);
do @(posedge dut.s_clk_50);
while (dut.u0.U_MBLITE.imem.dat_o != 32'hB8000000);
#100us; // tx byte via UART-115200
$display("[%t]: %m: BREAK ON CPU-EXIT", $time);
$stop;
end
`else
initial
begin : _GPIO // !!!GATE-sim
// dec var
time s_time;
logic [7:0] sv_gpio;
//
s_time = $time;
sv_gpio = dut.led_8bits_tri_o;
do begin : _POLL
// dly
@(posedge s_sys_clk);
// chk-upd
if (sv_gpio !== dut.led_8bits_tri_o) // gpio-activity
begin : _UPD
sv_gpio = dut.led_8bits_tri_o;
s_time = $time;
end
else // no activity
begin : _CHK
if (($time - s_time) > 1ms) // t-out
break;
end
end while(1);
//
$display("[%t]: %m: BREAK ON GPIO-TIMEOUT", $time);
$stop;
end
`endif // GATE_LEVEL
//////////////////////////////////////////////////////////////////////////////////
//
// TB Tasks
//
task dut_arst;
// simple async
s_rst <= 1; #(p_Tclk);
s_rst <= 0;
// Final
endtask : dut_arst
 
default clocking cb @(s_sys_clk);
endclocking : cb
 
//////////////////////////////////////////////////////////////////////////////////
endmodule
/tags/vmblite_base/hw/src/tb/uart_rx_if.sv
0,0 → 1,87
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: IK
//
// Create Date: 11:35:01 03/21/2013
// Design Name:
// Module Name: uart_rx_if
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
//
// Revision:
// Revision 0.01 - File Created, {8N1}-cfg
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
 
interface uart_rx_if
(
input i_rxd
);
//////////////////////////////////////////////////////////////////////////////////
//
typedef struct {
int speed_bod;
int speed_ns;
int speed_ns_half;
} cfg_t;
//////////////////////////////////////////////////////////////////////////////////
// RXD
bit [ 7:0] sv_rxd;
// ??
cfg_t sv_cfg;
//////////////////////////////////////////////////////////////////////////////////
//
task init(input int ii_speed=115_200);
//
sv_rxd = 0;
//
sv_cfg.speed_bod = ii_speed;
sv_cfg.speed_ns = (10**9)/ii_speed;
sv_cfg.speed_ns_half = sv_cfg.speed_ns/2;
// Final
endtask : init
 
task rxd;
// dec vars
bit s_done;
// wait
@(negedge i_rxd);
// Data framing
s_done = 0;
for (int i = 0 ; i < 1+8+1; i++) // => sta+[0:7]+stp
begin : DFRAME
case(i)
// START
0 : begin
#(sv_cfg.speed_ns_half*1ns);
if (i_rxd) // must be LOW
break; // exit-loop
end
// STOP
9 : begin
#(sv_cfg.speed_ns*1ns);
if (i_rxd) // must be HIGH
s_done = 1;
end
// DATA
default : begin
#(sv_cfg.speed_ns*1ns);
sv_rxd[i-1] = i_rxd;
end
endcase
end
//
if (s_done)
$display("[%t]: %m: rxd=%x / %c", $time, sv_rxd, (sv_rxd == 8'h0a)? " " : sv_rxd);
else
$display("[%t]: %m: rx-err", $time);
// Final
endtask : rxd
//////////////////////////////////////////////////////////////////////////////////
endinterface : uart_rx_if
/tags/vmblite_base/hw/src/tc/testcase.sv
0,0 → 1,45
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: IK
//
// Create Date: 11:35:01 03/21/2013
// Design Name:
// Module Name: testcase
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
//
// Revision:
// Revision 0.01 - File Created,
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
 
module testcase;
//////////////////////////////////////////////////////////////////////////////////
//
// Instantiate TB
//
tb tb();
 
//////////////////////////////////////////////////////////////////////////////////
//
//
//
initial
begin : TC
// init-msg
$display("[%t]: %m: START", $time);
// init-clr
tb.dut_arst();
// proc
#500ms;
// Final
#1us;
$display("[%t]: %m: STOP", $time);
$finish;
end
//////////////////////////////////////////////////////////////////////////////////
endmodule
/tags/vmblite_base/sw/test_main/microblaze/xil_io.c
0,0 → 1,99
 
#include "xil_io.h"
#include "xil_types.h"
 
u8 Xil_In8(u32 Addr) {
return *(volatile u8 *)Addr;
}
u16 Xil_In16(u32 Addr) {
return *(volatile u16 *)Addr;
}
u32 Xil_In32(u32 Addr) {
return *(volatile u32 *)Addr;
}
 
 
void Xil_Out8(u32 Addr, u8 Value) {
u8 *LocalAddr = (u8 *)Addr;
*LocalAddr = Value;
}
void Xil_Out16(u32 Addr, u16 Value) {
u16 *LocalAddr = (u16 *)Addr;
*LocalAddr = Value;
}
void Xil_Out32(u32 Addr, u32 Value) {
u32 *LocalAddr = (u32 *)Addr;
*LocalAddr = Value;
}
 
 
u16 Xil_EndianSwap16(u16 Data)
{
return (u16) (((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U));
}
u32 Xil_EndianSwap32(u32 Data)
{
u16 LoWord;
u16 HiWord;
 
 
LoWord = (u16) (Data & 0x0000FFFFU);
HiWord = (u16) ((Data & 0xFFFF0000U) >> 16U);
 
 
LoWord = (((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U));
HiWord = (((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U));
 
 
return ((((u32)LoWord) << (u32)16U) | (u32)HiWord);
}
 
#ifndef __LITTLE_ENDIAN__
u16 Xil_In16LE(u32 Addr)
#else
u16 Xil_In16BE(u32 Addr)
#endif
{
u16 Value;
 
Value = Xil_In16(Addr);
 
return Xil_EndianSwap16(Value);
}
 
#ifndef __LITTLE_ENDIAN__
u32 Xil_In32LE(u32 Addr)
#else
u32 Xil_In32BE(u32 Addr)
#endif
{
u32 InValue;
 
InValue = Xil_In32(Addr);
return Xil_EndianSwap32(InValue);
}
 
#ifndef __LITTLE_ENDIAN__
void Xil_Out16LE(u32 Addr, u16 Value)
#else
void Xil_Out16BE(u32 Addr, u16 Value)
#endif
{
u16 OutValue;
 
OutValue = Xil_EndianSwap16(Value);
 
Xil_Out16(Addr, OutValue);
}
 
#ifndef __LITTLE_ENDIAN__
void Xil_Out32LE(u32 Addr, u32 Value)
#else
void Xil_Out32BE(u32 Addr, u32 Value)
#endif
{
u32 OutValue;
 
OutValue = Xil_EndianSwap32(Value);
Xil_Out32(Addr, OutValue);
}
/tags/vmblite_base/sw/test_main/microblaze/xil_io.h
0,0 → 1,63
#ifndef XIL_IO_H
#define XIL_IO_H
 
#ifdef __cplusplus
extern "C" {
#endif
 
 
#include "xil_types.h"
 
u8 Xil_In8(u32 Addr);
u16 Xil_In16(u32 Addr);
u32 Xil_In32(u32 Addr);
 
void Xil_Out8(u32 Addr, u8 Value);
void Xil_Out16(u32 Addr, u16 Value);
void Xil_Out32(u32 Addr, u32 Value);
 
 
 
extern u16 Xil_EndianSwap16(u16 Data);
extern u32 Xil_EndianSwap32(u32 Data);
 
#ifndef __LITTLE_ENDIAN__
extern u16 Xil_In16LE(u32 Addr);
extern u32 Xil_In32LE(u32 Addr);
extern void Xil_Out16LE(u32 Addr, u16 Value);
extern void Xil_Out32LE(u32 Addr, u32 Value);
 
#define Xil_In16BE(Addr) Xil_In16((Addr))
#define Xil_In32BE(Addr) Xil_In32((Addr))
#define Xil_Out16BE(Addr, Value) Xil_Out16((Addr), (Value))
#define Xil_Out32BE(Addr, Value) Xil_Out32((Addr), (Value))
 
#define Xil_Htonl(Data) (Data)
#define Xil_Htons(Data) (Data)
#define Xil_Ntohl(Data) (Data)
#define Xil_Ntohs(Data) (Data)
 
#else
 
extern u16 Xil_In16BE(u32 Addr);
extern u32 Xil_In32BE(u32 Addr);
extern void Xil_Out16BE(u32 Addr, u16 Value);
extern void Xil_Out32BE(u32 Addr, u32 Value);
 
#define Xil_In16LE(Addr) Xil_In16((Addr))
#define Xil_In32LE(Addr) Xil_In32((Addr))
#define Xil_Out16LE(Addr, Value) Xil_Out16((Addr), (Value))
#define Xil_Out32LE(Addr, Value) Xil_Out32((Addr), (Value))
 
#define Xil_Htonl(Data) Xil_EndianSwap32((Data))
#define Xil_Htons(Data) Xil_EndianSwap16((Data))
#define Xil_Ntohl(Data) Xil_EndianSwap32((Data))
#define Xil_Ntohs(Data) Xil_EndianSwap16((Data))
 
#endif
 
#ifdef __cplusplus
}
#endif
 
#endif
/tags/vmblite_base/sw/test_main/microblaze/xil_stdio.c
0,0 → 1,15
/*
stdio
*/
#include "wb_uart.h"
 
void outbyte(char c)
{
wb_uart_write_s(c);
}
 
char inbyte()
{
char rxd = wb_uart_read_s();
return rxd;
}
/tags/vmblite_base/sw/test_main/microblaze/xil_types.h
0,0 → 1,69
#ifndef XIL_TYPES_H
#define XIL_TYPES_H
 
#include <stdint.h>
#include <stddef.h>
 
 
 
#ifndef TRUE
# define TRUE 1U
#endif
 
#ifndef FALSE
# define FALSE 0U
#endif
 
#ifndef NULL
#define NULL 0U
#endif
 
 
#ifndef __KERNEL__
#ifndef XBASIC_TYPES_H
 
typedef uint8_t u8;
typedef uint16_t u16;
typedef uint32_t u32;
 
#define __XUINT64__
typedef struct
{
u32 Upper;
u32 Lower;
} Xuint64;
#define XUINT64_MSW(x) ((x).Upper)
#define XUINT64_LSW(x) ((x).Lower)
 
#endif
 
 
typedef char char8;
typedef int8_t s8;
typedef int16_t s16;
typedef int32_t s32;
typedef int64_t s64;
typedef uint64_t u64;
typedef int sint32;
 
typedef intptr_t INTPTR;
typedef uintptr_t UINTPTR;
typedef ptrdiff_t PTRDIFF;
 
#if !defined(LONG) || !defined(ULONG)
typedef long LONG;
typedef unsigned long ULONG;
#endif
 
#define ULONG64_HI_MASK 0xFFFFFFFF00000000U
#define ULONG64_LO_MASK ~ULONG64_HI_MASK
 
#else
#include <linux/types.h>
#endif
 
 
#define UPPER_32_BITS(n) ((u32)(((n) >> 16) >> 16))
#define LOWER_32_BITS(n) ((u32)(n))
 
#endif
/tags/vmblite_base/sw/test_main/platform/platform.c
0,0 → 1,26
 
#include "platform.h"
 
#ifdef PLTFRM_WBS_PIO
#include "wb_pio.h"
#endif /* PLTFRM_WBS_PIO */
 
#ifdef PLTFRM_WBS_UART
#include "wb_uart.h"
#endif /* PLTFRM_WBS_UART */
 
void init_platform(void)
{
#ifdef PLTFRM_WBS_PIO
wb_pio_init(PLTFRM_WBS_PIO_BASEADDR);
#endif /* PLTFRM_WBS_PIO */
 
#ifdef PLTFRM_WBS_UART
wb_uart_init(PLTFRM_WBS_UART_BASEADDR);
#endif /* PLTFRM_WBS_UART */
}
 
void cleanup_platform(void)
{
 
}
/tags/vmblite_base/sw/test_main/platform/platform.h
0,0 → 1,30
#ifndef PLATFORM_H
#define PLATFORM_H
 
#define PLTFRM_MICROBLAZE_CORE_CLOCK_FREQ_HZ 50*1000*1000
#define PLTFRM_MICROBLAZE_INTERRUPT 0
#define PLTFRM_MICROBLAZE_DATA_SIZE 32
#define PLTFRM_MICROBLAZE_IMEM_VOL 2*1024
#define PLTFRM_MICROBLAZE_DMEM_VOL 2*1024
 
#define PLTFRM_WBS_PIO 1
#define PLTFRM_WBS_PIO_BASEADDR 0x00010000
#define PLTFRM_WBS_PIO_HIGHADDR 0x00010FFF
 
#define PLTFRM_WBS_UART 1
#define PLTFRM_WBS_UART_BASEADDR 0x00011000
#define PLTFRM_WBS_UART_HIGHADDR 0x00011FFF
#define PLTFRM_WBS_UART_BAUDRATE 115200
#define PLTFRM_WBS_UART_DATA_BITS 8 /* 8 */
#define PLTFRM_WBS_UART_USE_PARITY 0 /* N */
#define PLTFRM_WBS_UART_STOP_BITS 1 /* 1 */
 
/* SYSTEM */
#define PLTFRM_SYS_STDIN_TYPE PLTFRM_WBS_UART
#define PLTFRM_SYS_STDOUT_TYPE PLTFRM_WBS_UART
 
 
void init_platform();
void cleanup_platform();
 
#endif
/tags/vmblite_base/sw/test_main/Makefile
0,0 → 1,91
#
# makefile
#
 
 
# super-simple linker.ld / ;)
APP_STACK_SIZE := 0x400
APP_HEAP_SIZE := 0x400
 
#
MEM_DIR := _bmm
OBJ_DIR := _obj
 
#
TARGET_NAME = rom
 
#
all: clean cc listing bin mem
 
#
CC := mb-gcc
LD := mb-gcc
OBJDUMP := mb-objdump
OBJCOPY := mb-objcopy
DEFAULT_CP := cp -f
DEFAULT_MKDIR := mkdir -p
DEFAULT_RM := rm -rf
 
#
INCDIR := ./ \
./platform \
./microblaze \
../../hw/src/rtl/wb_pio/drivers \
../../hw/src/rtl/wb_uart/drivers
INCLUDE := $(addprefix -I, $(INCDIR))
 
XILFLAGS :=-mxl-soft-div -msoft-float -mxl-barrel-shift -mno-xl-soft-mul
CFLAGS :=-g -ansi -pedantic -Wall
CFLAGS += $(XILFLAGS)
LFLAGS=-Wl,-defsym -Wl,_STACK_SIZE=$(APP_STACK_SIZE) -Wl,-defsym -Wl,_HEAP_SIZE=$(APP_HEAP_SIZE)
 
C_SRCS := $(wildcard ./*.c)
C_SRCS += $(wildcard ./platform/*.c)
C_SRCS += $(wildcard ./microblaze/*.c)
C_SRCS += $(wildcard ../../hw/src/rtl/wb_pio/drivers/*.c)
C_SRCS += $(wildcard ../../hw/src/rtl/wb_uart/drivers/*.c)
 
OBJECTS_C := $(patsubst %.c,%.o, $(C_SRCS))
OBJFILES_C := $(addprefix $(OBJ_DIR)/, $(OBJECTS_C))
 
OBJECTS_O := $(patsubst %.c,%.o, $(notdir $(C_SRCS)))
OBJFILES_O := $(addprefix $(OBJ_DIR)/, $(OBJECTS_O))
 
 
$(OBJ_DIR)/%.o: %.c
@echo Compiling $<:
$(CC) -c $(CFLAGS) $(INCLUDE) -o $(OBJ_DIR)/$(notdir $@) $<
 
prep_cc:
$(DEFAULT_RM) $(OBJ_DIR)
$(DEFAULT_MKDIR) $(OBJ_DIR)
 
prep_mem:
$(DEFAULT_RM) $(MEM_DIR)
$(DEFAULT_MKDIR) $(MEM_DIR)
test -s ../util/bin2mem || { make -C ../util; }
 
cc: prep_cc $(OBJFILES_C)
@echo C_SRCS: $(C_SRCS)
$(LD) -o $(TARGET_NAME).elf $(OBJFILES_O) $(LFLAGS)
 
listing:
mb-size -t $(TARGET_NAME).elf
mb-objdump -DSsh $(TARGET_NAME).elf > $(TARGET_NAME).objdump
 
bin: prep_mem
mb-objcopy -O binary $(TARGET_NAME).elf $(MEM_DIR)/$(TARGET_NAME).bin
 
mem:
../util/bin2mem < $(MEM_DIR)/$(TARGET_NAME).bin > $(MEM_DIR)/$(TARGET_NAME).mem
../util/bin2mem4 < $(MEM_DIR)/$(TARGET_NAME).bin
$(DEFAULT_CP) *.mem ./$(MEM_DIR)
$(DEFAULT_RM) *.mem
 
clean:
@$(DEFAULT_RM) \
$(OBJ_DIR) \
$(MEM_DIR) \
*.objdump \
*.bak \
*.elf
/tags/vmblite_base/sw/test_main/test_main.c
0,0 → 1,24
/*
* simple test application
*
*
*/
 
#include <stdio.h> /* xil_printf, .. */
 
#include "platform.h"
#include "wb_pio.h" /* wb_pio_write */
 
 
int main(void)
{
 
init_platform();
/*fflush(stdin);*/
 
wb_pio_write(1);
xil_printf("Finished\n");
 
cleanup_platform();
return 0;
}
/tags/vmblite_base/sw/util/src/bin2mem.c
0,0 → 1,30
/******************************************************************************************
* syntax: bin2mem < filename1.bin > filename2.mem
* author: Rene van Leuken
* modified: Tamar Kranenburg
* February, 2008: header string provided, so ModelSim can recognize the file's format
* (= Veriloh hex) when 'Importing' into memory ... (Huib)
* September, 2008: prevent reversing byte order
*
*******************************************************************************************/
 
#include <stdio.h>
 
main()
{
unsigned char c1, c2, c3, c4;
 
int i=0;
while (!feof(stdin)) {
c1 = getchar() & 0x0ff;
c2 = getchar() & 0x0ff;
c3 = getchar() & 0x0ff;
c4 = getchar() & 0x0ff;
 
if (i==0) {i++;} else {printf("\n");}
 
printf ("%.2x%.2x%.2x%.2x", c1, c2, c3, c4);
}
 
return 0;
}
/tags/vmblite_base/sw/util/src/bin2mem4.c
0,0 → 1,44
/******************************************************************************************
* syntax: bin2mem < filename1.bin
* author: Rene van Leuken
* modified: Tamar Kranenburg
* February, 2008: header string provided, so ModelSim can recognize the file's format
* (= Veriloh hex) when 'Importing' into memory ... (Huib)
* September, 2008: prevent reversing byte order
*
*******************************************************************************************/
 
#include <stdio.h>
 
main()
{
unsigned char c0, c1, c2, c3;
 
FILE *fp0, *fp1, *fp2, *fp3;
fp0=fopen("rom0.mem", "wb");
fp1=fopen("rom1.mem", "wb");
fp2=fopen("rom2.mem", "wb");
fp3=fopen("rom3.mem", "wb");
 
int i=0;
while (!feof(stdin)) {
c0 = getchar() & 0x0ff;
c1 = getchar() & 0x0ff;
c2 = getchar() & 0x0ff;
c3 = getchar() & 0x0ff;
 
if (i==0) {i++;} else {
fprintf (fp0, "\n");
fprintf (fp1, "\n");
fprintf (fp2, "\n");
fprintf (fp3, "\n");
}
 
fprintf (fp0, "%.2x", c3);
fprintf (fp1, "%.2x", c2);
fprintf (fp2, "%.2x", c1);
fprintf (fp3, "%.2x", c0);
}
 
return 0;
}
/tags/vmblite_base/sw/util/src/mem2bin.c
0,0 → 1,70
/******************************************************************************************
* mem2bin: converts a mem file to a binary file
* syntax: mem2bin < filename_in.mem
* author: Tamar Kranenburg
* September, 2008
*******************************************************************************************/
 
#include <stdio.h>
 
main(int argc, char *argv[])
{
unsigned char ch;
unsigned char c1 = 255;
unsigned char c2 = 255;
 
FILE *fp;
fp=fopen("out.bin", "wb");
 
while (!feof(stdin))
{
ch = getchar() & 0x0ff;
if(ch >= 48 && ch <= 57)
{
/* ASCII digits */
ch -= 48;
}
else if(ch >= 65 && ch <= 70)
{
/* Upper case A to F */
ch -= 55;
}
else if(ch >= 97 && ch <= 102)
{
/* Lower case a to f */
ch -= 87;
}
else if(ch == 47 || ch == 64)
{
/* Comment line (/) or base address line (@) */
while(getchar() != 10)
{
continue;
}
continue;
}
else
{
continue;
}
if(c1 == 255)
{
c1 = ch;
continue;
}
else if(c2 == 255)
{
c2 = ch;
}
else
{
continue;
}
 
fputc(c1*16+c2, fp);
c1 = 255;
c2 = 255;
}
return 0;
}
/tags/vmblite_base/sw/util/Makefile
0,0 → 1,10
# Makefile for support utilities
 
all: clean cc
 
cc:
gcc ./src/bin2mem.c -o bin2mem
gcc ./src/bin2mem4.c -o bin2mem4
 
clean:
@rm -rf bin2mem bin2mem4
/tags/vmblite_base/sw/process.sh
0,0 → 1,40
#!/bin/bash
 
# USAGE: ./process.sh
# ARGs:
# <none>
# -clr
# -elf
#
 
ROOT_DIR=$PWD
 
 
function run_clr {
echo "CLR:"
make clean -C ./util
make clean -C ./test_main
}
 
function run_elf {
echo "ELF:"
make all -C ./util
make all -C ./test_main
}
 
 
echo "START: $(date)"
# proc NO-ARG
if [ "$1" == "" ]; then
run_clr
run_elf
fi
# proc 1ST-ARG
if [ "$1" == "-clr" ]; then run_clr ; fi
if [ "$1" == "-elf" ]; then run_elf ; fi
# proc 2ND-ARG
if [ "$2" == "-elf" ]; then run_elf ; fi
echo "STOP : $(date)"
 
# Final
exit 0
/tags/vmblite_base/process.sh
0,0 → 1,64
#!/bin/bash
 
# USAGE: ./process.sh
# ARGs:
# <none>
# -clr
# -arch
# -bit
# -elf
# -cp
#
 
ROOT_DIR=$PWD
CP_DIR=~/vbox_share/WORK/Xilinx/upld
 
function run_clr {
echo "CLR:"
cd $ROOT_DIR/hw/layout
./process.sh -clr &> /dev/null
cd $ROOT_DIR/hw/msim
./process.sh -clr &> /dev/null
cd $ROOT_DIR/sw
./process.sh -clr &> /dev/null
}
 
function run_arch {
echo "ARCH:"
cd $ROOT_DIR/../
tar cfJ vmblite_base_$(date +"%Y-%m-%d_%H-%M-%S").tar.xz vmblite_base &> /dev/null
echo "=> done"
}
 
function run_bit {
echo "BIT:"
cd $ROOT_DIR/hw/layout
./process.sh
}
 
function run_cp {
echo "CP:"
}
 
echo "START: $(date)"
# proc NO-ARG
if [ "$1" == "" ]; then
run_clr
run_bit
run_elf
fi
# proc 1ST-ARG
if [ "$1" == "-clr" ]; then run_clr ; fi
if [ "$1" == "-arch" ]; then run_arch ; fi
if [ "$1" == "-bit" ]; then run_bit ; fi
if [ "$1" == "-elf" ]; then run_elf ; fi
if [ "$1" == "-cp" ]; then run_cp ; fi
# proc 2ND-ARG
if [ "$2" == "-arch" ]; then run_arch ; fi
if [ "$2" == "-bit" ]; then run_bit ; fi
if [ "$2" == "-elf" ]; then run_elf ; fi
if [ "$2" == "-cp" ]; then run_cp ; fi
echo "STOP : $(date)"
 
# Final
exit 0

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