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/rtl/verilog/MC6809_cpu.v
0,0 → 1,953
/*
*
* MC6809/HD6309 Compatible code
* (c) 2013 R.A. Paz Schmidt
* distributed under the terms of the Lesser GPL, see LICENSE.TXT
*
*/
 
`include "defs.v"
module MC6809_cpu(
input wire cpu_clk,
input wire cpu_reset,
input wire cpu_nmi_n,
input wire cpu_irq_n,
input wire cpu_firq_n,
output wire [5:0] cpu_state_o,
output wire cpu_we_o,
output wire cpu_oe_o,
output wire [15:0] cpu_addr_o,
input wire [7:0] cpu_data_i,
output wire [7:0] cpu_data_o
);
 
wire k_reset;
wire k_clk;
assign k_clk = cpu_clk;
 
reg [7:0] k_opcode, k_postbyte0, k_ind_ea; /* all bytes of an instruction */
reg [7:0] k_pp_regs, k_pp_active_reg; // push/pull mask
reg [7:0] k_memhi, k_memlo, k_cpu_data_o; /* operand read from memory */
reg [7:0] k_ofslo, k_ofshi, k_eahi, k_ealo;
reg [5:0] state, // state of the main state machine
next_state, // next state to exit to from the read from [PC] state machine
next_mem_state, // next state to exit to from the read from memory state machine
next_push_state; // next state to exit to from push multiple state machine
reg k_cpu_oe, k_cpu_we, k_inc_pc, k_pull_reg_write;
reg [15:0] k_cpu_addr, k_new_pc;
reg k_write_pc, k_inc_su, k_dec_su, k_set_e, k_clear_e;
reg [1:0] k_mem_dest;
reg k_write_post_incdec; // asserted when in the last write cycle or in write back for loads
/****
* Decoder outputs
*/
wire [2:0] dec_o_p1_mode; // addressing mode
wire [2:0] dec_o_p1_optype; // k_opcode type
wire dec_o_use_s; // signals when S should be used instead of U
wire dec_o_alu_size;
/* ea decoder */
wire dec_o_ea_ofs8, dec_o_ea_ofs16, dec_o_ea_wpost, dec_o_ea_ofs0, dec_o_ea_indirect;
/* alu k_opcode decoder */
wire [4:0] dec_o_alu_opcode;
wire [1:0] dec_o_right_path_mod; /* Modifier for alu's right path input */
/* register decoder */
wire dec_o_wdest_8, dec_o_wdest_16, dec_o_write_flags;
wire [3:0] dec_o_left_path_addr, dec_o_right_path_addr, dec_o_dest_reg_addr;
/* test condition */
wire dec_o_cond_taken;
/* ALU outputs */
wire [15:0] alu_o_result;
wire [7:0] alu_o_CCR;
/* Register Module outputs */
wire [15:0] regs_o_left_path_data, regs_o_right_path_data, regs_o_eamem_addr, regs_o_su;
wire [7:0] regs_o_dp;
wire [15:0] regs_o_pc;
wire [7:0] regs_o_CCR;
/* Data Muxes */
reg [3:0] datamux_o_dest_reg_addr, datamux_o_alu_in_left_path_addr;
reg [15:0] datamux_o_alu_in_left_path_data, datamux_o_alu_in_right_path_data, datamux_o_dest;
 
reg k_p2_valid, k_p3_valid; /* 1 when k_postbyte0 has been loaded for page 2 or page 3 */
 
/* Interrupt sync registers */
 
reg [2:0] k_reg_nmi, k_reg_irq, k_reg_firq;
wire k_nmi_req, k_firq_req, k_irq_req;
 
assign k_nmi_req = k_reg_nmi[2] & k_reg_nmi[1];
assign k_firq_req = k_reg_firq[2] & k_reg_firq[1];
assign k_irq_req = k_reg_irq[2] & k_reg_irq[1];
 
alu16 alu(
.clk(k_clk),
.a_in(datamux_o_alu_in_left_path_data),
.b_in(datamux_o_alu_in_right_path_data),
.CCR(regs_o_CCR), /* flags */
.opcode_in(dec_o_alu_opcode), /* ALU k_opcode */
.sz_in(dec_o_alu_size), /* size, low 8 bit, high 16 bit */
.q_out(alu_o_result), /* ALU result */
.CCRo(alu_o_CCR)
);
regblock regs(
.clk_in(k_clk),
.path_left_addr(datamux_o_alu_in_left_path_addr),
.path_right_addr(dec_o_right_path_addr),
.write_reg_addr(datamux_o_dest_reg_addr),
.eapostbyte( k_ind_ea ),
.offset16({ k_ofshi, k_ofslo }),
.write_reg_8(dec_o_wdest_8 & (state == `SEQ_GRAL_WBACK)),
.write_reg_16(dec_o_wdest_16 & (state == `SEQ_GRAL_WBACK)),
.write_pull_reg(k_pull_reg_write),
.write_post(k_write_post_incdec),
.write_pc(k_write_pc),
.inc_pc(k_inc_pc),
.inc_su(k_inc_su),
.dec_su(k_dec_su),
.use_s(dec_o_use_s),
.data_w(datamux_o_dest),
.new_pc(k_new_pc),
.CCR_in(alu_o_CCR),
.write_flags(dec_o_write_flags & (state == `SEQ_GRAL_WBACK)),
.set_e(k_set_e),
.clear_e(k_clear_e),
.CCR_o(regs_o_CCR),
.path_left_data(regs_o_left_path_data),
.path_right_data(regs_o_right_path_data),
.eamem_addr(regs_o_eamem_addr),
.reg_pc(regs_o_pc),
.reg_dp(regs_o_dp),
.reg_su(regs_o_su)
);
 
decode_regs dec_regs(
.opcode(k_opcode),
.postbyte0(k_postbyte0),
.page2_valid(k_p2_valid),
.page3_valid(k_p3_valid),
.path_left_addr(dec_o_left_path_addr),
.path_right_addr(dec_o_right_path_addr),
.dest_reg(dec_o_dest_reg_addr),
.write_dest_8(dec_o_wdest_8),
.write_dest_16(dec_o_wdest_16),
.result_size(dec_o_alu_size)
);
 
decode_op dec_op(
.opcode(k_opcode),
.postbyte0(k_postbyte0),
.page2_valid(k_p2_valid),
.page3_valid(k_p3_valid),
.mode(dec_o_p1_mode),
.optype(dec_o_p1_optype),
.use_s(dec_o_use_s)
);
decode_ea dec_ea(
.eapostbyte( k_ind_ea ),
.noofs(dec_o_ea_ofs0),
.ofs8(dec_o_ea_ofs8),
.ofs16(dec_o_ea_ofs16),
.write_post(dec_o_ea_wpost),
.isind(dec_o_ea_indirect)
);
 
/* Opcodes for the ALU are decoded here
* Write Flags are also decoded here
*/
decode_alu dec_alu(
.opcode(k_opcode),
.postbyte0(k_postbyte0),
.page2_valid(k_p2_valid),
.page3_valid(k_p3_valid),
.alu_opcode(dec_o_alu_opcode),
.dec_alu_right_path_mod(dec_o_right_path_mod),
.dest_flags(dec_o_write_flags)
);
/* Condition decoder */
test_condition test_cond(
.opcode(k_opcode),
.postbyte0(k_postbyte0),
.page2_valid(k_p2_valid),
.CCR(regs_o_CCR),
.cond_taken(dec_o_cond_taken)
);
 
/* Module IO */
assign cpu_oe_o = k_cpu_oe; // we latch on the rising edge
assign cpu_we_o = k_cpu_we;
assign cpu_addr_o = k_cpu_addr;
assign cpu_data_o = k_cpu_data_o;
assign k_reset = cpu_reset;
assign cpu_state_o = state;
 
/* Left Register read mux
*/
always @(*)
begin
datamux_o_alu_in_left_path_addr = dec_o_left_path_addr;
case (k_pp_active_reg)
8'h80: datamux_o_alu_in_left_path_addr = `RN_PC;
8'h40: datamux_o_alu_in_left_path_addr = (dec_o_use_s) ? `RN_U:`RN_S;
8'h20: datamux_o_alu_in_left_path_addr = `RN_IY;
8'h10: datamux_o_alu_in_left_path_addr = `RN_IX;
8'h08: datamux_o_alu_in_left_path_addr = `RN_DP;
8'h04: datamux_o_alu_in_left_path_addr = `RN_ACCB;
8'h02: datamux_o_alu_in_left_path_addr = `RN_ACCA;
8'h01: datamux_o_alu_in_left_path_addr = `RN_CC;
endcase
end
 
/* Destination register address MUX
*/
always @(*)
begin
datamux_o_dest_reg_addr = dec_o_dest_reg_addr;
case (k_pp_active_reg)
8'h80: datamux_o_dest_reg_addr = `RN_PC;
8'h40: datamux_o_dest_reg_addr = (dec_o_use_s) ? `RN_U:`RN_S;
8'h20: datamux_o_dest_reg_addr = `RN_IY;
8'h10: datamux_o_dest_reg_addr = `RN_IX;
8'h08: datamux_o_dest_reg_addr = `RN_DP;
8'h04: datamux_o_dest_reg_addr = `RN_ACCB;
8'h02: datamux_o_dest_reg_addr = `RN_ACCA;
8'h01: datamux_o_dest_reg_addr = `RN_CC;
endcase
end
 
/* Destination register data mux
* selects the source to write to register. 16 bit registers have to be written at once after reading the low byte
*
*/
always @(*)
begin
datamux_o_dest = alu_o_result;
case (dec_o_p1_optype)
`OP_PULL, `OP_RTS: // destination register
datamux_o_dest = { k_memhi, k_memlo };
`OP_LEA:
if (dec_o_ea_indirect & dec_o_alu_size)
datamux_o_dest = { k_memhi, k_memlo };
else
datamux_o_dest = regs_o_eamem_addr;
endcase
end
 
/* ALU left input mux */
 
always @(*)
begin
if (dec_o_left_path_addr == `RN_MEM8)
datamux_o_alu_in_left_path_data = { k_memhi, k_memlo };
else
begin
datamux_o_alu_in_left_path_data = regs_o_left_path_data;
end
end
 
/* ALU right input mux */
always @(*)
begin
case (dec_o_right_path_addr)
`RN_MEM8:
datamux_o_alu_in_right_path_data = { 8'h00, k_memlo };
`RN_MEM16:
datamux_o_alu_in_right_path_data = { k_memhi, k_memlo };
`RN_IMM8:
datamux_o_alu_in_right_path_data = { 8'h0, k_memlo };
`RN_IMM16:
datamux_o_alu_in_right_path_data = { k_memhi, k_memlo };
default:
case (dec_o_right_path_mod)
`MOD_DEFAULT: datamux_o_alu_in_right_path_data = regs_o_right_path_data;
`MOD_ONE: datamux_o_alu_in_right_path_data = 16'h0001;
`MOD_ZERO: datamux_o_alu_in_right_path_data = 16'h0000;
`MOD_MINUS1: datamux_o_alu_in_right_path_data = 16'hffff;
endcase
endcase
end
 
always @(posedge k_clk or posedge k_reset)
begin
if (k_reset == 1'b1)
begin
state <= `SEQ_COLDRESET;
k_reg_nmi <= 0;
k_reg_firq <= 0;
k_reg_irq <= 0;
end
else
begin
/* Inrerrupt recognition and acknowledge */
if (!k_reg_nmi[2])
k_reg_nmi <= { k_reg_nmi[1:0], cpu_nmi_n };
if (!k_reg_irq[2])
k_reg_irq <= { k_reg_irq[1:0], cpu_irq_n };
if (!k_reg_firq[2])
k_reg_firq <= { k_reg_firq[1:0], cpu_firq_n };
/* modifier registers */
if (k_inc_pc)
k_inc_pc <= 0;
if (k_write_pc)
k_write_pc <= 0;
if (k_cpu_we)
k_cpu_we <= 0;
if (k_cpu_oe)
k_cpu_oe <= 0;
if (k_write_post_incdec)
k_write_post_incdec <= 0;
if (k_dec_su)
k_dec_su <= 0;
if (k_inc_su)
k_inc_su <= 0;
if (k_pull_reg_write)
k_pull_reg_write <= 0;
if (k_set_e)
k_set_e <= 0;
if (k_clear_e)
k_clear_e <= 0;
case (state)
`SEQ_COLDRESET:
begin
state <= `SEQ_MEM_READ_H;
k_eahi <= 8'hff;
k_ealo <= 8'hfe;
next_mem_state <= `SEQ_LOADPC;
end
`SEQ_NMI:
begin
k_reg_nmi <= 2'h0;
{ k_eahi, k_ealo } <= 16'hfffc;
k_pp_regs <= 8'hff;
k_set_e <= 1;
state <= `SEQ_PREPUSH; // first stack the registers
next_push_state <= `SEQ_MEM_READ_H; // than load new PC
next_mem_state <= `SEQ_FETCH; // than continue fetching instructions
end
`SEQ_SWI:
begin
state <= `SEQ_MEM_READ_H;
{ k_eahi, k_ealo } <= 16'hfffa;
k_pp_regs <= 8'hff;
state <= `SEQ_PREPUSH; // first stack the registers
next_push_state <= `SEQ_MEM_READ_H; // than load new PC
next_mem_state <= `SEQ_FETCH; // than continue fetching instructions
k_set_e <= 1;
end
`SEQ_IRQ:
begin
k_reg_irq <= 2'h0;
state <= `SEQ_MEM_READ_H;
{ k_eahi, k_ealo } <= 16'hfff8;
k_pp_regs <= 8'hff;
next_mem_state <= `SEQ_PREPUSH;
k_set_e <= 1;
state <= `SEQ_PREPUSH; // first stack the registers
next_push_state <= `SEQ_MEM_READ_H; // than load new PC
next_mem_state <= `SEQ_FETCH; // than continue fetching instructions
end
`SEQ_FIRQ:
begin
k_reg_firq <= 2'h0;
{ k_eahi, k_ealo } <= 16'hfff6;
k_pp_regs <= 8'h81; // PC & CC
k_clear_e <= 1;
state <= `SEQ_PREPUSH; // first stack the registers
next_push_state <= `SEQ_MEM_READ_H; // than load new PC
next_mem_state <= `SEQ_FETCH; // than continue fetching instructions
end
`SEQ_SWI2:
begin
{ k_eahi, k_ealo } <= 16'hfff4;
k_pp_regs <= 8'hff;
k_set_e <= 1;
state <= `SEQ_PREPUSH; // first stack the registers
next_push_state <= `SEQ_MEM_READ_H; // than load new PC
next_mem_state <= `SEQ_FETCH; // than continue fetching instructions
end
`SEQ_SWI3:
begin
{ k_eahi, k_ealo } <= 16'hfff2;
k_pp_regs <= 8'hff;
k_set_e <= 1;
state <= `SEQ_PREPUSH; // first stack the registers
next_push_state <= `SEQ_MEM_READ_H; // than load new PC
next_mem_state <= `SEQ_FETCH; // than continue fetching instructions
end
`SEQ_UNDEF:
begin
{ k_eahi, k_ealo } <= 16'hfff0;
k_pp_regs <= 8'hff;
k_set_e <= 1;
state <= `SEQ_PREPUSH; // first stack the registers
next_push_state <= `SEQ_MEM_READ_H; // than load new PC
next_mem_state <= `SEQ_FETCH; // than continue fetching instructions
end
`SEQ_LOADPC: /* loads the PC with the address taken from the reset vector */
begin
$display("cpu_data_i %02x %t", cpu_data_i, $time);
state <= `SEQ_FETCH;
end
`SEQ_FETCH: /* execution starts here */
begin
if (k_nmi_req)
state <= `SEQ_NMI;
else
if (k_firq_req)
state <= `SEQ_FIRQ;
else
if (k_irq_req)
state <= `SEQ_IRQ;
else
begin
state <= `SEQ_FETCH_1;
k_cpu_addr <= regs_o_pc;
end
end
`SEQ_FETCH_1:
begin
k_cpu_oe <= 1;
state <= `SEQ_FETCH_2;
end
`SEQ_FETCH_2:
begin
k_opcode <= cpu_data_i;
case (cpu_data_i[7:0]) /* page 2 & 3 opcodes are recognized here */
8'h10:
begin
k_p2_valid <= 1;
k_p3_valid <= 0;
state <= `SEQ_FETCH_3;
end
8'h11:
begin
k_p2_valid <= 0;
k_p3_valid <= 1;
state <= `SEQ_FETCH_3;
end
default:
begin
state <= `SEQ_DECODE;
k_p2_valid <= 0; // set when an k_opcode is page 2
k_p3_valid <= 0; // set when an k_opcode is page 3
end
endcase
k_pp_active_reg <= 8'h00; // prevents wrong register in left/dest data muxes
k_inc_pc <= 1;
end
`SEQ_FETCH_3:
begin
state <= `SEQ_FETCH_4;
k_cpu_addr <= regs_o_pc;
end
`SEQ_FETCH_4:
begin
k_cpu_oe <= 1;
state <= `SEQ_FETCH_5;
end
`SEQ_FETCH_5: /* fetches a page 2 or 3 opcode */
begin
k_postbyte0 <= cpu_data_i;
k_inc_pc <= 1;
state <= `SEQ_DECODE_P23;
end
`SEQ_DECODE:
begin
/* here we have the first byte of the k_opcode and should be decided to which state we jump
* inherent means that no extra info is needed
* ALU opcodes need routing of registers to/from the ALU to the registers
*/
case (dec_o_p1_mode)
`NONE: // unknown k_opcode and push/pull... refetch ?
begin
casex (k_opcode)
8'h39: // RTS
begin
state <= `SEQ_PREPULL;
k_pp_regs <= 8'h80; // Pull PC (RTS)all regs
end
8'h3B: // RTI
begin
state <= `SEQ_PREPULL;
k_pp_regs <= 8'hff; // all regs
end
8'b001101x0: // PUSH S&U
begin
state <= `SEQ_PC_READ_L;
next_state <= `SEQ_PREPUSH;
next_push_state <= `SEQ_FETCH;
end
8'b001101x1: // PULL S&U
begin
next_state <= `SEQ_PREPULL;
state <= `SEQ_PC_READ_L;
end
default: /* we ignore unknown opcodes */
state <= `SEQ_FETCH;
endcase
end
`IMMEDIATE: // 8 or 16 bits as result decides..
begin
if (dec_o_alu_size)
state <= `SEQ_PC_READ_H;
else
state <= `SEQ_PC_READ_L;
next_state <= `SEQ_GRAL_ALU;
end
`INHERENT:
begin
case (k_opcode)
8'h3f: state <= `SEQ_SWI;
default: state <= `SEQ_GRAL_ALU;
endcase
end
`DIRECT:
begin
state <= `SEQ_PC_READ_L;
k_mem_dest <= `MEMDEST_MH; // operand to memlo/memhi
if ((dec_o_right_path_addr == `RN_MEM8) || (dec_o_right_path_addr == `RN_MEM16) ||
(dec_o_left_path_addr == `RN_MEM8))
begin
if (dec_o_alu_size)
next_state <= `SEQ_MEM_READ_H;
else
next_state <= `SEQ_MEM_READ_L;
next_mem_state <= `SEQ_GRAL_ALU; // read then alu
end
else
next_state <= `SEQ_GRAL_ALU; // no read
k_eahi <= regs_o_dp;
end
`INDEXED:
state <= `SEQ_IND_READ_EA;
`EXTENDED:
begin
state <= `SEQ_PC_READ_H; // loads address
k_mem_dest <= `MEMDEST_MH; // operand to memlo/memhi
if ((dec_o_right_path_addr == `RN_MEM8) || (dec_o_right_path_addr == `RN_MEM16) ||
(dec_o_left_path_addr == `RN_MEM8))
begin
if (dec_o_alu_size)
next_state <= `SEQ_MEM_READ_H;
else
next_state <= `SEQ_MEM_READ_L;
next_mem_state <= `SEQ_GRAL_ALU; // read then alu
end
else
next_state <= `SEQ_GRAL_ALU; // no read
end
`REL8:
begin
state <= `SEQ_PC_READ_L; // loads address
if (dec_o_p1_optype == `OP_JSR) // bsr
next_state <= `SEQ_JSR_PUSH;
else
next_state <= `SEQ_JMP_LOAD_PC; // offset loaded in this cycle, jump if needed
end
`REL16:
begin
state <= `SEQ_PC_READ_H; // loads address
if (dec_o_p1_optype == `OP_JSR) // lbsr
next_state <= `SEQ_JSR_PUSH;
else
next_state <= `SEQ_JMP_LOAD_PC;
end
endcase
end
`SEQ_DECODE_P23:
begin // has prefix 10 or 11
k_inc_pc <= 0;
case (dec_o_p1_mode)
`NONE: // unknown k_opcode... re-fetch ?
state <= `SEQ_FETCH;
`IMMEDIATE: // 8 or 16 bits as result decides..
begin
if (dec_o_alu_size)
state <= `SEQ_PC_READ_H;
else
state <= `SEQ_PC_READ_L;
next_state <= `SEQ_GRAL_ALU;
end
`INHERENT:
case (k_opcode)
8'h3f: if (k_p2_valid) state <= `SEQ_SWI2;
else state <= `SEQ_SWI3;
default: state <= `SEQ_GRAL_ALU;
endcase
`DIRECT:
begin
state <= `SEQ_PC_READ_L;
k_mem_dest <= `MEMDEST_MH; // operand to memlo/memhi
if ((dec_o_right_path_addr == `RN_MEM8) || (dec_o_right_path_addr == `RN_MEM16) ||
(dec_o_left_path_addr == `RN_MEM8))
begin
if (dec_o_alu_size)
next_state <= `SEQ_MEM_READ_H;
else
next_state <= `SEQ_MEM_READ_L;
next_mem_state <= `SEQ_GRAL_ALU; // read then alu
end
else
next_state <= `SEQ_GRAL_ALU; // no read
k_eahi <= regs_o_dp;
end
`INDEXED:
state <= `SEQ_IND_READ_EA;
`EXTENDED:
begin
state <= `SEQ_PC_READ_H; // loads address
k_mem_dest <= `MEMDEST_MH; // operand to memlo/memhi
if ((dec_o_right_path_addr == `RN_MEM8) || (dec_o_right_path_addr == `RN_MEM16) ||
(dec_o_left_path_addr == `RN_MEM8))
begin
if (dec_o_alu_size)
next_state <= `SEQ_MEM_READ_H;
else
next_state <= `SEQ_MEM_READ_L;
next_mem_state <= `SEQ_GRAL_ALU; // read then alu
end
else
next_state <= `SEQ_GRAL_ALU; // no read
end
`REL16:
begin // long branches only
state <= `SEQ_PC_READ_H; // loads address
next_state <= `SEQ_JMP_LOAD_PC;
end
endcase
end
`SEQ_GRAL_ALU:
state <= `SEQ_GRAL_WBACK;
`SEQ_GRAL_WBACK:
begin
next_mem_state <= `SEQ_FETCH;
case (dec_o_dest_reg_addr)
`RN_MEM8: state <= `SEQ_MEM_WRITE_L;
`RN_MEM16: state <= `SEQ_MEM_WRITE_H;
default:
begin
state <= `SEQ_FETCH;
k_write_post_incdec <= dec_o_ea_wpost;
end
endcase
end
`SEQ_INH_ALU:
state <= `SEQ_GRAL_WBACK;
`SEQ_IND_READ_EA: // reads EA byte
begin
k_cpu_addr <= regs_o_pc;
state <= `SEQ_IND_READ_EA_1;
k_inc_pc <= 1;
end
`SEQ_IND_READ_EA_1:
begin
k_cpu_oe <= 1; // read
state <= `SEQ_IND_READ_EA_2;
end
`SEQ_IND_READ_EA_2:
begin
k_ind_ea <= cpu_data_i;
state <= `SEQ_IND_DECODE;
end
`SEQ_IND_DECODE: // here we have to see what we need for indexed...
begin
if (dec_o_ea_ofs8)
begin // load 1 byte offset
state <= `SEQ_PC_READ_L;
next_state <= `SEQ_IND_DECODE_OFS; // has some offset, load arg
end
else
if (dec_o_ea_ofs16)
begin // load 2 bytes offset
state <= `SEQ_PC_READ_H;
next_state <= `SEQ_IND_DECODE_OFS; // has some offset, load arg
end
else
//if (dec_o_ea_ofs0)
begin // no extra load...
if ((dec_o_right_path_addr == `RN_MEM8) || (dec_o_right_path_addr == `RN_MEM16) ||
(dec_o_left_path_addr == `RN_MEM8))
begin
k_mem_dest <= `MEMDEST_MH; // operand land in k_memhi/lo
next_mem_state <= `SEQ_GRAL_ALU;
if (dec_o_alu_size)
state <= `SEQ_MEM_READ_H;
else
state <= `SEQ_MEM_READ_L;
end
else
state <= `SEQ_GRAL_ALU; // no load, then store
end
end
`SEQ_IND_DECODE_OFS: // loads argument if needed
begin
if ((dec_o_right_path_addr == `RN_MEM8) || (dec_o_right_path_addr == `RN_MEM16) ||
(dec_o_left_path_addr == `RN_MEM8))
begin
k_mem_dest <= `MEMDEST_MH; // operand land in k_memhi/lo
next_mem_state <= `SEQ_GRAL_ALU;
if (dec_o_alu_size)
state <= `SEQ_MEM_READ_H;
else
state <= `SEQ_MEM_READ_L;
end
else
state <= `SEQ_GRAL_ALU; // no load, then store
end
`SEQ_JMP_LOAD_PC:
begin
case (dec_o_p1_mode)
`REL16:
begin
k_new_pc <= regs_o_pc + { k_memhi,k_memlo };
if (dec_o_cond_taken)
k_write_pc <= 1;
end
`REL8:
begin
k_new_pc <= regs_o_pc + { {8{k_memlo[7]}}, k_memlo };
if (dec_o_cond_taken)
k_write_pc <= 1;
end
`EXTENDED:
begin
k_new_pc <= { k_eahi,k_ealo };
k_write_pc <= 1;
end
`DIRECT:
begin
k_new_pc <= { regs_o_dp, k_ealo };
k_write_pc <= 1;
end
`INDEXED:
begin
if (dec_o_ea_indirect)
k_new_pc <= { k_memhi,k_memlo };
else
k_new_pc <= regs_o_eamem_addr;
k_write_pc <= 1;
end
endcase
state <= `SEQ_FETCH;
end
`SEQ_JSR_PUSH:
begin
k_pp_active_reg <= 8'h80; // push PC
state <= `SEQ_PUSH_WRITE_L;
next_state <= `SEQ_JMP_LOAD_PC;
end
`SEQ_PREPUSH:
begin
next_state <= `SEQ_PREPUSH;
if (k_pp_regs > 0)
state <= `SEQ_PUSH_WRITE_L;
else
state <= next_push_state;
if (k_pp_regs[7]) begin k_pp_regs[7] <= 0; k_pp_active_reg <= 8'h80; end
else
if (k_pp_regs[6]) begin k_pp_regs[6] <= 0; k_pp_active_reg <= 8'h40; end
else
if (k_pp_regs[5]) begin k_pp_regs[5] <= 0; k_pp_active_reg <= 8'h20; end
else
if (k_pp_regs[4]) begin k_pp_regs[4] <= 0; k_pp_active_reg <= 8'h10; end
else
if (k_pp_regs[3]) begin k_pp_regs[3] <= 0; k_pp_active_reg <= 8'h08; end
else
if (k_pp_regs[2]) begin k_pp_regs[2] <= 0; k_pp_active_reg <= 8'h04; end
else
if (k_pp_regs[1]) begin k_pp_regs[1] <= 0; k_pp_active_reg <= 8'h02; end
else
if (k_pp_regs[0]) begin k_pp_regs[0] <= 0; k_pp_active_reg <= 8'h01; end
end
`SEQ_PREPULL:
begin
k_inc_su <= 1;
k_mem_dest <= `MEMDEST_MH;
next_mem_state <= `SEQ_PREPULL;
if (k_pp_regs[0]) begin k_pp_active_reg <= 8'h01; k_pp_regs[0] <= 0; state <= `SEQ_MEM_READ_L; end
else
if (k_pp_regs[1]) begin k_pp_active_reg <= 8'h02; k_pp_regs[1] <= 0; state <= `SEQ_MEM_READ_L; end
else
if (k_pp_regs[2]) begin k_pp_active_reg <= 8'h04; k_pp_regs[2] <= 0; state <= `SEQ_MEM_READ_L; end
else
if (k_pp_regs[3]) begin k_pp_active_reg <= 8'h08; k_pp_regs[3] <= 0; state <= `SEQ_MEM_READ_L; end
else
if (k_pp_regs[4]) begin k_pp_active_reg <= 8'h10; k_pp_regs[4] <= 0; state <= `SEQ_MEM_READ_H;end
else
if (k_pp_regs[5]) begin k_pp_active_reg <= 8'h20; k_pp_regs[5] <= 0; state <= `SEQ_MEM_READ_H;end
else
if (k_pp_regs[6]) begin k_pp_active_reg <= 8'h40; k_pp_regs[6] <= 0; state <= `SEQ_MEM_READ_H; end
else
begin
next_mem_state <= `SEQ_FETCH; // end of sequence
if (k_pp_regs[7]) begin k_pp_active_reg <= 8'h80; k_pp_regs[7] <= 0; state <= `SEQ_MEM_READ_H; end
end
end
`SEQ_PUSH_WRITE_L: // first low byte push
begin
k_cpu_data_o <= regs_o_left_path_data[7:0];
state <= `SEQ_PUSH_WRITE_L_1;
k_cpu_we <= 1; // write
k_cpu_addr <= regs_o_su;
k_dec_su <= 1; // decrement stack pointer
end
`SEQ_PUSH_WRITE_L_1:
begin
if (k_pp_active_reg[7:4] > 0)
state <= `SEQ_PUSH_WRITE_H;
else
if (k_pp_regs[3:0] > 0)
state <= `SEQ_PREPUSH;
else
state <= next_push_state;
end
`SEQ_PUSH_WRITE_H: // reads high byte
begin
k_cpu_data_o <= regs_o_left_path_data[15:8];
state <= `SEQ_PUSH_WRITE_H_1;
k_cpu_we <= 1; // write
k_cpu_addr <= regs_o_su;
k_dec_su <= 1; // decrement stack pointer
end
`SEQ_PUSH_WRITE_H_1:
begin
state <= next_state;
end
`SEQ_PC_READ_H: // reads high byte for [PC], used by IMM, DIR, EXT
begin
k_cpu_addr <= regs_o_pc;
state <= `SEQ_PC_READ_H_1;
k_inc_pc <= 1;
end
`SEQ_PC_READ_H_1:
begin
k_cpu_oe <= 1; // read
state <= `SEQ_PC_READ_H_2;
end
`SEQ_PC_READ_H_2:
begin
case (dec_o_p1_mode)
`REL16, `IMMEDIATE: k_memhi <= cpu_data_i;
`EXTENDED: k_eahi <= cpu_data_i;
`INDEXED: k_ofshi <= cpu_data_i;
endcase
state <= `SEQ_PC_READ_L;
end
`SEQ_PC_READ_L: // reads low byte [PC]
begin
k_cpu_addr <= regs_o_pc;
state <= `SEQ_PC_READ_L_1;
k_inc_pc <= 1;
end
`SEQ_PC_READ_L_1:
begin
k_cpu_oe <= 1; // read
state <= `SEQ_PC_READ_L_2;
end
`SEQ_PC_READ_L_2:
begin
case (dec_o_p1_mode)
`NONE: k_pp_regs <= cpu_data_i; // push & pull
`REL8, `REL16, `IMMEDIATE: k_memlo <= cpu_data_i;
`DIRECT, `EXTENDED: k_ealo <= cpu_data_i;
`INDEXED: k_ofslo <= cpu_data_i;
endcase
state <= next_state;
end
`SEQ_MEM_READ_H: // reads high byte
begin
case (dec_o_p1_mode)
`NONE: begin k_cpu_addr <= regs_o_su; k_inc_su <= 1; end // pull, rts, rti
`INDEXED: k_cpu_addr <= regs_o_eamem_addr;
default: k_cpu_addr <= { k_eahi, k_ealo };
endcase
state <= `SEQ_MEM_READ_H_1;
end
`SEQ_MEM_READ_H_1:
begin
k_cpu_oe <= 1; // read
state <= `SEQ_MEM_READ_H_2;
end
`SEQ_MEM_READ_H_2:
begin
case (k_mem_dest)
`MEMDEST_PC: k_new_pc[15:8] <= cpu_data_i;
`MEMDEST_MH: k_memhi <= cpu_data_i;
`MEMDEST_AH: k_eahi <= cpu_data_i;
endcase
state <= `SEQ_MEM_READ_L_1;
k_cpu_addr <= k_cpu_addr + 16'h1;
end
`SEQ_MEM_READ_L: // reads high byte
begin
case (dec_o_p1_mode)
`NONE: k_cpu_addr <= regs_o_su; // pull, rts, rti
`INDEXED: k_cpu_addr <= regs_o_eamem_addr;
default: k_cpu_addr <= { k_eahi, k_ealo };
endcase
state <= `SEQ_MEM_READ_L_1;
end
`SEQ_MEM_READ_L_1:
begin
k_cpu_oe <= 1; // read
state <= `SEQ_MEM_READ_L_2;
end
`SEQ_MEM_READ_L_2:
begin
case (k_mem_dest)
`MEMDEST_PC: begin k_new_pc[7:0] <= cpu_data_i; k_write_pc <= 1; end
`MEMDEST_MH: k_memlo <= cpu_data_i;
`MEMDEST_AH: k_ealo <= cpu_data_i;
endcase
case (dec_o_p1_mode)
`NONE, `INHERENT: k_pull_reg_write <= 1; // pull, rts, rti
endcase
state <= next_mem_state;
end
`SEQ_MEM_WRITE_H: // writes high byte
begin
case (dec_o_p1_mode)
`INDEXED: k_cpu_addr <= regs_o_eamem_addr;
default: k_cpu_addr <= { k_eahi, k_ealo };
endcase
k_cpu_data_o <= datamux_o_dest[7:0];
state <= `SEQ_MEM_WRITE_H_1;
k_cpu_we <= 1; // read
end
`SEQ_MEM_WRITE_H_1:
begin
state <= `SEQ_MEM_WRITE_L;
k_cpu_addr <= k_cpu_addr + 16'h1;
end
`SEQ_MEM_WRITE_L: // reads high byte
begin
if (!dec_o_alu_size)
case (dec_o_p1_mode)
`INDEXED: k_cpu_addr <= regs_o_eamem_addr;
default: k_cpu_addr <= { k_eahi, k_ealo };
endcase
k_cpu_data_o <= datamux_o_dest[7:0];
state <= `SEQ_MEM_WRITE_L_1;
k_cpu_we <= 1; // write
end
`SEQ_MEM_WRITE_L_1:
begin
k_write_post_incdec <= dec_o_ea_wpost;
state <= next_mem_state;
end
endcase
end
end
initial
begin
k_cpu_oe = 0;
k_cpu_we = 0;
k_mem_dest = 0;
k_new_pc = 16'hffff;
end
endmodule
/rtl/verilog/TODO.txt
0,0 → 1,8
Unfinished tasks are described here
 
28.12.13
--------
 
- HD6309 compatibility totally missing. Only the ALU paths have been layed out.
- E flags not taken into account after RTI
- Z flag for LEAX/LEAY
/rtl/verilog/defs.v
0,0 → 1,171
 
`default_nettype none
 
`define RN_ACCD 4'h0
`define RN_IX 4'h1
`define RN_IY 4'h2
`define RN_U 4'h3
`define RN_S 4'h4
`define RN_PC 4'h5
`define RN_MEM16 4'h6
`define RN_IMM16 4'h7
`define RN_ACCA 4'h8
`define RN_ACCB 4'h9
`define RN_CC 4'ha
`define RN_DP 4'hb
`define RN_MEM8 4'hc
`define RN_IMM8 4'hd
`define RN_INV 4'hf
 
 
// opcodes that need an ALU result
`define NOP 5'b00000
`define CMP 5'b00001
`define SBC 5'b00010
`define ADD 5'b00011
`define AND 5'b00100
`define BIT 5'b00101
`define LD 5'b00110
`define ST 5'b00111
`define EOR 5'b01000
`define ADC 5'b01001
`define OR 5'b01010
`define SUB 5'b01011
`define T168L 5'b01100
`define T168H 5'b01101
`define SEXT 5'b01110
`define EXG 5'b01111
 
`define NEG 5'b10000
`define COM 5'b10011
`define LSR 5'b10100
`define ROR 5'b10110
`define ASR 5'b10111
`define LSL 5'b11000
`define ROL 5'b11001
`define ORCC 5'b11010
`define ANDCC 5'b11011
 
`define DAA 5'b11100
`define MUL 5'b11101
`define T816 5'b11110
 
/* Sequencer states */
 
`define SEQ_COLDRESET 'h00
`define SEQ_NMI 'h01
`define SEQ_SWI 'h02
`define SEQ_IRQ 'h03
`define SEQ_FIRQ 'h04
`define SEQ_SWI2 'h05
`define SEQ_SWI3 'h06
`define SEQ_UNDEF 'h07
`define SEQ_LOADPC 'h08
`define SEQ_FETCH 'h09
`define SEQ_FETCH_1 'h0a
`define SEQ_FETCH_2 'h0b
`define SEQ_FETCH_3 'h0c
`define SEQ_FETCH_4 'h0d
`define SEQ_FETCH_5 'h0e
 
`define SEQ_DECODE 'h0f
`define SEQ_DECODE_P23 'h10
 
`define SEQ_GRAL_ALU 'h11 // x
`define SEQ_GRAL_WBACK 'h12 // x
`define SEQ_INH_ALU 'h13
`define SEQ_INH_SWI 'h14
 
`define SEQ_IND_READ_EA 'h15 // offset 8 or 16 bits
`define SEQ_IND_READ_EA_1 'h16
`define SEQ_IND_READ_EA_2 'h17 // real operand from memory indirect
`define SEQ_IND_DECODE 'h18
`define SEQ_IND_DECODE_OFS 'h19 // used to load 8 or 16 bits offset
`define SEQ_JMP_LOAD_PC 'h1a
 
 
`define SEQ_JSR_PUSH 'h1b
`define SEQ_JSR_PUSH_L 'h1c
`define SEQ_RTS_POP_L 'h1d
`define SEQ_RTS_POP_H 'h1e
 
`define SEQ_PREPUSH 'h20
`define SEQ_PREPULL 'h21
`define SEQ_PUSH_WRITE_L 'h22
`define SEQ_PUSH_WRITE_L_1 'h23
`define SEQ_PUSH_WRITE_H 'h24
`define SEQ_PUSH_WRITE_H_1 'h25
 
`define SEQ_PC_READ_H 'h30
`define SEQ_PC_READ_H_1 'h31
`define SEQ_PC_READ_H_2 'h32
`define SEQ_PC_READ_L 'h33
`define SEQ_PC_READ_L_1 'h34
`define SEQ_PC_READ_L_2 'h35
 
`define SEQ_MEM_READ_H 'h36
`define SEQ_MEM_READ_H_1 'h37
`define SEQ_MEM_READ_H_2 'h38
`define SEQ_MEM_READ_L 'h39
`define SEQ_MEM_READ_L_1 'h3a
`define SEQ_MEM_READ_L_2 'h3b
`define SEQ_MEM_WRITE_H 'h3c
`define SEQ_MEM_WRITE_H_1 'h3d
`define SEQ_MEM_WRITE_L 'h3e
`define SEQ_MEM_WRITE_L_1 'h3f
 
 
//`define FLAGC regs_o_CCR[0]
//`define FLAGV regs_o_CCR[1]
//`define FLAGZ regs_o_CCR[2]
//`define FLAGN regs_o_CCR[3]
`define FLAGI regs_o_CCR[5]
`define FLAGF regs_o_CCR[6]
//`define FLAGE regs_o_CCR[7]
 
`define DFLAGC CCR[0]
`define DFLAGV CCR[1]
`define DFLAGZ CCR[2]
`define DFLAGN CCR[3]
// some wires exist only for simulation
`define SIMULATION 1
// Adressing modes
`define NONE 3'h0
`define IMMEDIATE 3'h1
`define INHERENT 3'h2
`define DIRECT 3'h3
`define INDEXED 3'h4
`define EXTENDED 3'h5
`define REL8 3'h6
`define REL16 3'h7
 
// Address size
 
// memory transfer size, read or written, used for addresses
`define MSZ_0 2'h0
`define MSZ_8 2'h1
`define MSZ_16 2'h2
// Data transfer size, to save to register, used for data from memory and to save results to memory/registers
`define DSZ_0 2'h0
`define DSZ_8 2'h1
`define DSZ_16 2'h2
 
`define OP_NONE 3'h0
`define OP_PUSH 3'h1
`define OP_PULL 3'h2
`define OP_RTS 3'h3
`define OP_JSR 3'h4
`define OP_ST 3'h5
`define OP_LD 3'h6
`define OP_LEA 3'h7
 
/* alu decoder right path modifier */
`define MOD_DEFAULT 2'h0
`define MOD_ONE 2'h1
`define MOD_ZERO 2'h2
`define MOD_MINUS1 2'h3
 
`define MEMDEST_PC 2'h0
`define MEMDEST_MH 2'h1
`define MEMDEST_AH 2'h2
`define MEMDEST_I16 2'h3
/rtl/verilog/regblock.v
0,0 → 1,224
/*
* MC6809 Register block, dual ported
*/
`include "defs.v"
 
 
module regblock(
input wire clk_in,
input wire [3:0] path_left_addr,
input wire [3:0] path_right_addr,
input wire [3:0] write_reg_addr,
input wire [7:0] eapostbyte, // effective address post byte
input wire [15:0] offset16, // up to 16 bit offset for effective address calculation
input wire write_reg_8,
input wire write_reg_16,
input wire write_pull_reg,
input wire write_post,
input wire write_pc,
input wire inc_pc,
input wire inc_su, /* increments S or U */
input wire dec_su, /* decrements s or u */
input wire use_s, /* increments S or U */
input wire [15:0] data_w,
input wire [15:0] new_pc,
input wire [7:0] CCR_in,
input wire write_flags,
input wire set_e,
input wire clear_e,
output wire [7:0] CCR_o,
output reg [15:0] path_left_data,
output reg [15:0] path_right_data,
output reg [15:0] eamem_addr,
output wire [15:0] reg_pc,
output wire [7:0] reg_dp,
output wire [15:0] reg_su
);
 
`define ACCD { ACCA, ACCB }
reg [15:0] IX;
reg [15:0] IY;
reg [15:0] SU;
reg [15:0] SS;
reg [15:0] PC;
 
reg [7:0] ACCA;
reg [7:0] ACCB;
reg [7:0] DP;
`define CCR { eflag, fflag, hflag, intff, nff, zff, vff, cff }
 
reg eflag, fflag, hflag;
reg intff, nff, zff, vff, cff;
reg [15:0] ea_reg, ea_reg_post;
 
assign CCR_o = `CCR;
assign reg_pc = PC;
assign reg_dp = DP;
assign reg_su = (use_s) ? SS:SU; /* stack pointer */
// left path output, always 16 bits
always @(*)
begin
case (path_left_addr)
`RN_ACCA: path_left_data = { 8'h0, ACCA };
`RN_ACCB: path_left_data = { 8'h0, ACCB };
`RN_ACCD: path_left_data = `ACCD;
`RN_IX: path_left_data = IX;
`RN_IY: path_left_data = IY;
`RN_U: path_left_data = SU;
`RN_S: path_left_data = SS;
`RN_PC: path_left_data = PC;
`RN_DP: path_left_data = { 8'h0, DP };
default:
path_left_data = 16'hBEEF;
endcase
end
// right path output, always 16 bits
always @(*)
begin
case (path_right_addr)
`RN_ACCA: path_right_data = { 8'h0, ACCA };
`RN_ACCB: path_right_data = { 8'h0, ACCB };
`RN_ACCD: path_right_data = `ACCD;
`RN_IX: path_right_data = IX;
`RN_IY: path_right_data = IY;
`RN_U: path_right_data = SU;
`RN_S: path_right_data = SS;
`RN_DP: path_right_data = { 8'h0, DP };
default:
path_right_data = 16'hBEEF;
endcase
end
 
always @(*)
begin
case (eapostbyte[6:5])
2'b00: ea_reg = IX;
2'b01: ea_reg = IY;
2'b10: ea_reg = SU;
2'b11: ea_reg = SS;
endcase
end
// pre-decrement/postincrement
always @(*)
begin
ea_reg_post = ea_reg;
casex (eapostbyte)
8'b1xxx0000: ea_reg_post = ea_reg + 16'h1;
8'b1xxx0001: ea_reg_post = ea_reg + 16'h2;
8'b1xxx0010: ea_reg_post = ea_reg - 16'h1;
8'b1xxx0011: ea_reg_post = ea_reg - 16'h2;
//default: ea_reg_post = ea_reg;
endcase
end
/* EA calculation
* postbyte bytes assembler
*
* 0RRnnnnn 0 n,R n is 5 bits signed
* 1RRi0000 0 ,R+
* 1RRi0001 0 ,R++
* 1RRi0010 0 ,-R
* 1RRi0011 0 ,--R
* 1RR00100 0 ,R no offset
* 1RRi0101 0 B,R
* 1RRi0110 0 A,R
* 1RRi1000 1 n,R n is signed 8 bit
* 1RRi1001 2 n,R n is signed 16 bit
* 1RRi1011 0 D,R
* 1xxi1100 1 n,PC n is signed 8 bit postbyte
* 1xxi1101 2 n,PC n is 16 bit postbytes
*
* RR
* 00 X
* 01 Y
* 10 U
* 11 S
*/
always @(*)
begin
eamem_addr = 16'hFEED; // for debug purposes
casex (eapostbyte)
8'b0xx0xxxx: // 5 bit signed offset +
eamem_addr = ea_reg + { 12'h0, eapostbyte[3:0] };
8'b0xx1xxxx: // 5 bit signed offset -
eamem_addr = ea_reg + { 12'hfff, eapostbyte[3:0] };
8'b1xx_x_0000, // post increment, increment occurs at a later stage
8'b1xx_x_0001, // post increment, increment occurs at a later stage
8'b1xx_x_0100: // no offset
eamem_addr = ea_reg;
8'b1xx_x_0010, // pre decrement
8'b1xx_x_0011: // pre decrement
eamem_addr = ea_reg_post; // gets precalculated pre-decremented address
8'b1xx_x_0101: // B,R
eamem_addr = ea_reg + { {8{ACCB[7]}}, ACCB };
8'b1xx_x_0110: // A,R
eamem_addr = ea_reg + { {8{ACCA[7]}}, ACCA };
8'b1xx_x_1011: // D,R
eamem_addr = ea_reg + `ACCD;
8'b1xx_x_1000: // n,R 8 bit offset
eamem_addr = ea_reg + { offset16[7] ? 8'hff:8'h0, offset16[7:0] }; // from postbyte1
8'b1xx_x_1001: // n,R // 16 bit offset
eamem_addr = ea_reg + offset16;
8'b1xx_x_1100: // n,PC
eamem_addr = PC + { offset16[7] ? 8'hff:8'h0, offset16[7:0] };
8'b1xx_x_1101: // n,PC
eamem_addr = PC + offset16;
endcase
end
 
always @(posedge clk_in)
begin
if (write_reg_8 | write_reg_16 | write_pull_reg)
case (write_reg_addr)
0: `ACCD <= data_w;
1: IX <= data_w;
2: IY <= data_w;
3: SU <= data_w;
4: SS <= data_w;
5: PC <= data_w;
8: ACCA <= data_w[7:0];
9: ACCB <= data_w[7:0];
10: `CCR <= data_w[7:0];
11: DP <= data_w[7:0];
endcase
if (write_post) // write back predecrement/postincremented values
begin
case (eapostbyte[6:5])
2'b00: IX <= ea_reg_post;
2'b01: IY <= ea_reg_post;
2'b10: SU <= ea_reg_post;
2'b11: SS <= ea_reg_post;
endcase
end
if (write_flags)
begin
`CCR <= CCR_in;
end
if (set_e)
eflag <= 1;
if (clear_e)
eflag <= 0;
if (write_pc) PC <= new_pc;
if (inc_pc) PC <= PC + 16'h1;
if (inc_su)
if (use_s) SS <= SS + 16'h1;
else SU <= SU + 16'h1;
if (dec_su)
if (use_s) SS <= SS - 16'h1;
else SU <= SU - 16'h1;
end
`ifdef SIMULATION
initial
begin
PC = 16'hfffe;
DP = 8'h00;
IX = 16'h0;
`CCR = 0;
IY = 16'hA55A;
SS = 16'h0f00;
SU = 16'h0e00;
end
`endif
endmodule
/rtl/verilog/decoders.v
0,0 → 1,370
 
/*
* Signals which registers have to be read/written for the current opcode
*
*
*
*/
`include "defs.v"
module decode_regs(
input wire [7:0] opcode,
input wire [7:0] postbyte0,
input wire page2_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)
input wire page3_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)
output reg [3:0] path_left_addr,
output reg [3:0] path_right_addr,
output reg [3:0] dest_reg,
output wire write_dest_8,
output wire write_dest_16,
output wire result_size
);
// for registers, memory writes are handled differently
assign write_dest_8 = ((dest_reg >= `RN_ACCA) && (dest_reg <= `RN_DP)) ? 1:0;
assign write_dest_16 = (dest_reg < `RN_IMM16) ? 1:0;
assign result_size = (dest_reg < `RN_IMM16) ? 1:0;
always @(opcode, postbyte0, page2_valid, page3_valid)
begin
path_left_addr = `RN_INV;
path_right_addr = `RN_INV;
dest_reg = `RN_INV;
if (page2_valid | page3_valid)
begin
casex(postbyte0)
8'h83, 8'h93, 8'ha3, 8'hb3: path_left_addr = `RN_ACCD;
8'h8c, 8'h9c, 8'hac, 8'hbc: path_left_addr = `RN_IY;
8'h8e, 8'h9e, 8'hae, 8'hbe: path_left_addr = `RN_IY;
8'h8f, 8'h9f, 8'haf, 8'hbf: path_left_addr = `RN_IY;
endcase
casex (postbyte0) // right arm
8'h83, 8'h8c, 8'h8e, 8'h8f: path_right_addr = `RN_IMM16;
8'h93, 8'ha3, 8'hb3: path_right_addr = `RN_MEM16;
8'h9c, 8'hac, 8'hbc: path_right_addr = `RN_MEM16;
8'h9e, 8'hae, 8'hbe: path_right_addr = `RN_MEM16;
8'h9f, 8'haf, 8'hbf: path_right_addr = `RN_MEM16;
endcase
casex(postbyte0) // dest
8'h83, 8'h93, 8'ha3, 8'hb3: begin end // only flags
8'h8c, 8'h9c, 8'hac, 8'hbc: begin end // only flags
8'h8e, 8'h9e, 8'hae, 8'hbe: dest_reg = `RN_IY;
8'h8f, 8'h9f, 8'haf, 8'hbf: dest_reg = `RN_MEM16;
endcase
end
// destination
casex(opcode)
8'h30: dest_reg = `RN_IX;
8'h31: dest_reg = `RN_IY;
8'h32: dest_reg = `RN_S;
8'h33: dest_reg = `RN_U;
8'h39: dest_reg = `RN_PC; // rts
8'h3d: begin path_left_addr = `RN_ACCA; path_right_addr = `RN_ACCB; dest_reg = `RN_ACCD; end // mul
8'h4x: begin path_left_addr = `RN_ACCA; dest_reg = `RN_ACCA; end
8'h5x: begin path_left_addr = `RN_ACCB; dest_reg = `RN_ACCB; end
8'h0x, 8'h7x: begin path_left_addr = `RN_MEM8; dest_reg = `RN_MEM8; end
8'h6x:
case (opcode[3:0])
4'hf: begin dest_reg = `RN_MEM8; end // CLR, only dest
default: begin path_left_addr = `RN_MEM8; dest_reg = `RN_MEM8; end
endcase
8'h4x, 8'h8x, 8'h9x, 8'hax, 8'hbx:
case (opcode[3:0])
4'h3: begin path_left_addr = `RN_ACCD; dest_reg = `RN_ACCD; end
4'h7: begin path_left_addr = `RN_ACCA; dest_reg = `RN_MEM8; end
4'hc, 4'he, 4'hf: begin path_left_addr = `RN_IX; dest_reg = `RN_IX; end
4'hd: begin end // nothing active, jsr
default: begin path_left_addr = `RN_ACCA; dest_reg = `RN_ACCA; end
endcase
8'h5x, 8'hcx, 8'hdx, 8'hex, 8'hfx:
case (opcode[3:0])
4'h3, 4'hc: begin path_left_addr = `RN_ACCD; dest_reg = `RN_ACCD; end
4'h7: begin path_left_addr = `RN_ACCB; dest_reg = `RN_MEM8; end // store to mem
4'he: begin path_left_addr = `RN_U; dest_reg = `RN_IX; end
4'hf: begin path_left_addr = `RN_IX; dest_reg = `RN_IX; end
4'hd: begin path_left_addr = `RN_ACCD; end
default: begin path_left_addr = `RN_ACCB; dest_reg = `RN_ACCB; end
endcase
endcase
casex (opcode) // right arm
// 8x and Cx
8'b1x00_000x, 8'b1x00_0010: path_right_addr = `RN_IMM8;
8'b1x00_0011, 8'b1x00_11x0, 8'b1x00_1111: path_right_addr = `RN_IMM16;
8'b1x00_010x, 8'b1x00_0110,
8'b1x00_10xx: path_right_addr = `RN_IMM8;
// 9, A, B, D, E, F
8'b1x01_000x, 8'b1x01_0010: path_right_addr = `RN_MEM8;
8'b1x01_0011, 8'b1x01_11x0, 8'b1x01_1111: path_right_addr = `RN_MEM16;
8'b1x01_010x, 8'b1x01_0110,
8'b1x01_10xx: path_right_addr = `RN_MEM8;
8'b1x1x_000x, 8'b1x1x_0010: path_right_addr = `RN_MEM8;
8'b1x1x_0011, 8'b1x1x_11x0, 8'b1x1x_1111: path_right_addr = `RN_MEM16;
8'b1x1x_010x, 8'b1x1x_0110,
8'b1x1x_10xx: path_right_addr = `RN_MEM8;
endcase
end
endmodule
 
/* Decodes module and addressing mode for page 1 opcodes */
module decode_op(
input wire [7:0] opcode,
input wire [7:0] postbyte0,
input wire page2_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)
input wire page3_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)
output reg [2:0] mode,
output reg [2:0] optype,
output reg use_s
);
wire [3:0] oplo;
reg size;
assign oplo = opcode[3:0];
 
always @(opcode, postbyte0, page2_valid, page3_valid, oplo)
begin
//dsize = `DSZ_8; // data operand size
//msize = `MSZ_8; // memory operand size
optype = `OP_NONE;
use_s = 1;
mode = `NONE;
size = 0;
// Addressing mode
casex(opcode)
8'h0x: begin mode = `DIRECT; end
8'h12, 8'h13, 8'h19: mode = `INHERENT;
8'h14, 8'h15, 8'h18, 8'h1b: mode = `NONE; // undefined opcodes
8'h16: mode = `REL16;
8'h17: begin mode = `REL16; optype = `OP_JSR; end
8'h1a, 8'h1c, 8'h1d, 8'h1e, 8'h1f: mode = `IMMEDIATE; // handled in ALU ORCC, ANDCC, SEX, EXG, TFR
8'h2x: mode = `REL8;
8'h30, 8'h31, 8'h32, 8'h33: begin mode = `INDEXED; optype = `OP_LEA; end
8'h34: begin optype = `OP_PUSH; mode = `NONE; end
8'h35: begin optype = `OP_PULL; mode = `NONE; end
8'h36: begin optype = `OP_PUSH; mode = `NONE; use_s = 0; end
8'h37: begin optype = `OP_PULL; mode = `NONE; use_s = 0; end
8'h38, 8'h3e: mode = `NONE;
// don't change to inh because SEQ_MEM_READ_x would not use register S as address
8'h39, 8'h3b: begin mode = `NONE; optype = `OP_RTS; end
8'h3a, 8'h3c, 8'h3d, 8'h3f: mode = `INHERENT;
8'h4x: begin mode = `INHERENT; end
8'h5x: begin mode = `INHERENT; end
8'h6x: begin mode = `INDEXED; end
8'h7x: begin mode = `EXTENDED; end
8'h8x:
begin
case (oplo)
4'h3, 4'hc, 4'he: begin mode = `IMMEDIATE; size = 1; end
4'hd: mode = `REL8; // bsr
default: mode = `IMMEDIATE;
endcase
end
8'hcx:
begin
case (oplo)
4'h3, 4'hc, 4'he: begin mode = `IMMEDIATE; size = 1; end
default: mode = `IMMEDIATE;
endcase
end
8'h9x, 8'hdx: begin mode = `DIRECT; end
8'hax, 8'hex: begin mode = `INDEXED; end
8'hbx, 8'hfx: begin mode = `EXTENDED; end
endcase
// Opcode type
casex(opcode)
8'b1xxx0110: optype = `OP_LD;
8'b1xxx0111: optype = `OP_ST;
8'b11xx1100: optype = `OP_LD; // LDD
8'b10xx1101: begin optype = `OP_JSR; end// bsr & jsr
8'b1xxx1110: optype = `OP_LD; // LDX, LDU
8'b1xxx1111, 8'b1xxx1101: optype = `OP_ST;
endcase
if (page2_valid == 1'b1)
begin
casex(postbyte0)
8'h1x: mode = `REL16;
8'h2f: mode = `INHERENT;
8'h83: begin mode = `IMMEDIATE; size = 1; end
//8'h93, 8'ha3, 8'hb3: begin mem16 = 1; size = 1; end
8'h8c: begin mode = `IMMEDIATE; size = 1; end
//8'h9c, 8'hac, 8'hbc: begin mem16 = 1; size = 1; end
8'h8e: begin mode = `IMMEDIATE; size = 1; end
//8'h9e, 8'hae, 8'hbe: begin mem16 = 1; size = 1; end
//8'h9f, 8'haf, 8'hbf: begin mem16 = 1; size = 1; end
8'hce: begin mode = `IMMEDIATE; size = 1; end
//8'hde, 8'hee, 8'hfe: begin mem16 = 1; size = 1; end
//8'hdf, 8'hef, 8'hff: begin mem16 = 1; size = 1; end
endcase
casex( postbyte0)
8'h9x, 8'hdx: mode = `DIRECT;
8'hax, 8'hex: mode = `INDEXED;
8'hbx, 8'hfx: mode = `EXTENDED;
endcase
casex( postbyte0)
8'b1xxx1110: optype = `OP_LD; // LDY, LDS
8'b1xxx1111, 8'b1xxx1101: optype = `OP_ST; // STY, STS
endcase
end
if (page3_valid == 1'b1)
begin
casex(postbyte0)
8'h2f: mode = `INHERENT;
8'h83: begin mode = `IMMEDIATE; size = 1; end // CMPD
//8'h93, 8'ha3, 8'hb3: begin mem16 = 1; size = 1; end // CMPD
8'h8c: begin mode = `IMMEDIATE; size = 1; end
//8'h9c, 8'hac, 8'hbc: begin mem16 = 1; size = 1; end
8'h8e: begin mode = `IMMEDIATE; size = 1; end
//8'h9e, 8'hae, 8'hbe: begin mem16 = 1; size = 1; end
//8'h9f, 8'haf, 8'hbf: begin mem16 = 1; size = 1; end
8'hce: begin mode = `IMMEDIATE; size = 1; end
//8'hde, 8'hee, 8'hfe: begin mem16 = 1; size = 1; end
//8'hdf, 8'hef, 8'hff: begin mem16 = 1; size = 1; end
endcase
casex( postbyte0)
8'h9x, 8'hdx: mode = `DIRECT;
8'hax, 8'hex: mode = `INDEXED;
8'hbx, 8'hfx: mode = `EXTENDED;
endcase
end
end
endmodule
 
/* Decodes the Effective Address postbyte
to recover size of offset to load and post-incr/pre-decr info
*/
module decode_ea(
input wire [7:0] eapostbyte,
output reg noofs,
output reg ofs8, // needs an 8 bit offset
output reg ofs16, // needs an 16 bit offset
output reg write_post, // needs to write back a predecr or post incr
output wire isind // signals when the mode is indirect, the memory at the address is read to load the real address
);
assign isind = (eapostbyte[7] & eapostbyte[4]) ? 1'b1:1'b0;
always @(*)
begin
noofs = 0;
ofs8 = 0;
ofs16 = 0;
write_post = 0;
casex (eapostbyte)
8'b0xxxxxxx, 8'b1xx00100: noofs = 1;
8'b1xxx1000, 8'b1xxx1100: ofs8 = 1;
8'b1xxx1001, 8'b1xxx1101: ofs16 = 1;
8'b1xx11111: ofs16 = 1; // extended indirect
8'b1xxx00xx: write_post = 1;
endcase
end
endmodule
 
module decode_alu(
input wire [7:0] opcode,
input wire [7:0] postbyte0,
input wire page2_valid, // is 1 when the postbyte0 was loaded and is page2 opcode
input wire page3_valid, // is 1 when the postbyte0 was loaded and is page3 opcode
output reg [4:0] alu_opcode,
output reg [1:0] dec_alu_right_path_mod,
output wire dest_flags
);
 
assign dest_flags = alu_opcode != `NOP;
always @(*)
begin
alu_opcode = `NOP;
dec_alu_right_path_mod = `MOD_DEFAULT;
casex (opcode)
8'b1xxx_0000: alu_opcode = `SUB;
8'b1xxx_0001: alu_opcode = `CMP;
8'b1xxx_0010: alu_opcode = `SBC;
8'b10xx_0011: alu_opcode = `SUB;
8'b11xx_0011: alu_opcode = `ADD;
8'b1xxx_0100: alu_opcode = `AND;
8'b1xxx_0101: alu_opcode = `BIT;
8'b1xxx_0110: alu_opcode = `LD;
8'b1xxx_0111: alu_opcode = `ST;
8'b1xxx_1000: alu_opcode = `EOR;
8'b1xxx_1001: alu_opcode = `ADC;
8'b1xxx_1010: alu_opcode = `OR;
8'b1xxx_1011: alu_opcode = `ADD;
8'b10xx_1100: alu_opcode = `CMP;
8'b11xx_1100: alu_opcode = `LD;
8'b11xx_1101: alu_opcode = `LD;
8'b1xxx_1110: alu_opcode = `LD;
8'b1xxx_1111: alu_opcode = `ST;
8'h00, 8'b01xx_0000: alu_opcode = `NEG;
8'h03, 8'b01xx_0011: alu_opcode = `COM;
8'h04, 8'b01xx_0100: alu_opcode = `LSR;
8'h06, 8'b01xx_0110: alu_opcode = `ROR;
8'h07, 8'b01xx_0111: alu_opcode = `ASR;
8'h08, 8'b01xx_1000: alu_opcode = `LSL;
8'h09, 8'b01xx_1001: alu_opcode = `ROL;
8'h0a, 8'b01xx_1010: begin alu_opcode = `SUB; dec_alu_right_path_mod = `MOD_MINUS1; end // dec
8'h0c, 8'b01xx_1100: begin alu_opcode = `ADD; dec_alu_right_path_mod = `MOD_ONE; end // inc
8'h0d, 8'b01xx_1101: alu_opcode = `AND;
8'h0f, 8'b01xx_1111: begin alu_opcode = `LD; dec_alu_right_path_mod = `MOD_ZERO; end // CLR
8'h19: alu_opcode = `DAA;
8'h1a: alu_opcode = `ORCC;
8'h1c: alu_opcode = `ANDCC;
8'h1d: alu_opcode = `SEXT;
8'h1e: alu_opcode = `EXG;
8'h3d: alu_opcode = `MUL;
endcase
if (page2_valid)
casex (postbyte0)
8'b10xx_0011,
8'b10xx_1010: alu_opcode = `CMP;
8'b1xxx_1110: alu_opcode = `LD;
8'b1xxx_1111: alu_opcode = `ST;
endcase
if (page3_valid)
casex (postbyte0)
8'b10xx_0011,
8'b10xx_1010: alu_opcode = `CMP;
8'b1xxx_1110: alu_opcode = `LD;
8'b1xxx_1111: alu_opcode = `ST;
endcase
end
endmodule
/* decodes the condition and checks the flags to see if it is met */
module test_condition(
input wire [7:0] opcode,
input wire [7:0] postbyte0,
input wire page2_valid,
input wire [7:0] CCR,
output reg cond_taken
);
 
wire [7:0] op = page2_valid ? postbyte0:opcode;
always @(*)
begin
cond_taken = 1'b0;
if ((op == 8'h16) || (op == 8'h17) || (op == 8'h8D))
cond_taken = 1'b1; // LBRA/LBSR, BSR
if (op[7:4] == 4'h2)
case (op[3:0])
4'h0: cond_taken = 1'b1; // BRA
4'h1: cond_taken = 0; // BRN
4'h2: cond_taken = !(`DFLAGC & `DFLAGZ); // BHI
4'h3: cond_taken = `DFLAGC | `DFLAGZ; // BLS
4'h4: cond_taken = !`DFLAGC; // BCC, BHS
4'h5: cond_taken = `DFLAGC; // BCS, BLO
4'h6: cond_taken = !`DFLAGZ; // BNE
4'h7: cond_taken = `DFLAGZ; // BEQ
4'h8: cond_taken = !`DFLAGV; // BVC
4'h9: cond_taken = `DFLAGV; // BVS
4'ha: cond_taken = !`DFLAGN; // BPL
4'hb: cond_taken = `DFLAGN; // BMI
4'hc: cond_taken = `DFLAGN == `DFLAGV; // BGE
4'hd: cond_taken = `DFLAGN != `DFLAGV; // BLT
4'he: cond_taken = (`DFLAGN == `DFLAGV) & (!`DFLAGZ); // BGT
4'hf: cond_taken = (`DFLAGN != `DFLAGV) | (`DFLAGZ); // BLE
endcase
end
endmodule
/rtl/verilog/alu16.v
0,0 → 1,519
/*
* (c) 2013 Alejandro Paz
*
*
* An alu core
*
* ADD, ADC, DAA, SUB, SBC, COM, NEG, CMP, ASR, ASL, ROR, ROL, RCR, RCL
*
*
*
*/
`include "defs.v"
module alu16(
input wire clk,
input wire [15:0] a_in,
input wire [15:0] b_in,
input wire [7:0] CCR, /* condition code register */
input wire [4:0] opcode_in, /* ALU opcode */
input wire sz_in, /* size, low 8 bit, high 16 bit */
output reg [15:0] q_out, /* ALU result */
output reg [7:0] CCRo
);
 
wire c_in, n_in, v_in, z_in, h_in;
assign c_in = CCR[0]; /* carry flag */
assign n_in = CCR[3]; /* neg flag */
assign v_in = CCR[1]; /* overflow flag */
assign z_in = CCR[2]; /* zero flag */
assign h_in = CCR[5]; /* halb-carry flag */
 
 
wire [7:0] add8_r, adc8_r, sub8_r, sbc8_r, com8_r, neg8_r;
wire [7:0] asr8_r, shr8_r, shl8_r, ror8_r, rol8_r, and8_r, or8_r, eor8_r;
wire [15:0] add16_r, adc16_r, sub16_r, sbc16_r, com16_r, neg16_r;
wire [15:0] asr16_r, shr16_r, shl16_r, ror16_r, rol16_r, and16_r, or16_r, eor16_r, mul16_r;
wire [3:0] daa8l_r, daa8h_r;
wire daa_lnm9;
 
wire [7:0] add8_w, adc8_w, com8_w, neg8_w, sub8_w, sbc8_w;
wire [7:0] asr8_w, shr8_w, shl8_w, ror8_w, rol8_w, and8_w, or8_w, eor8_w;
wire [15:0] add16_w, adc16_w, com16_w, neg16_w, sub16_w, sbc16_w;
wire [15:0] asr16_w, shr16_w, shl16_w, ror16_w, rol16_w, and16_w, or16_w, eor16_w, mul16_w;
 
wire cadd8_w, cadc8_w, csub8_w, csbc8_w;
wire cadd16_w, cadc16_w, csub16_w, csbc16_w;
 
wire cadd8_r, cadc8_r, csub8_r, csbc8_r, ccom8_r, cneg8_r;
wire casr8_r, cshr8_r, cshl8_r, cror8_r, crol8_r, cand8_r, cdaa8_r;
wire cadd16_r, cadc16_r, csub16_r, csbc16_r, ccom16_r, cneg16_r;
wire casr16_r, cshr16_r, cshl16_r, cror16_r, crol16_r, cand16_r, cmul16_r;
wire vadd8_r, vadc8_r, vsub8_r, vsbc8_r, vcom8_r, vneg8_r;
wire vasr8_r, vshr8_r, vshl8_r, vror8_r, vrol8_r, vand8_r;
wire vadd16_r, vadc16_r, vsub16_r, vsbc16_r, vcom16_r, vneg16_r;
wire vasr16_r, vshr16_r, vshl16_r, vror16_r, vrol16_r, vand16_r;
 
assign { cadd8_w, add8_w } = { 1'b0, a_in[7:0] } + { 1'b0, b_in[7:0] };
assign { cadd16_w, add16_w } = { 1'b0, a_in[15:0] } + { 1'b0, b_in[15:0] };
assign { cadc8_w, adc8_w } = { 1'b0, a_in[7:0] } + { 1'b0, b_in[7:0] } + { 8'h0, c_in };
assign { cadc16_w, adc16_w } = { 1'b0, a_in[15:0] } + { 1'b0, b_in[15:0] } + { 16'h0, c_in };
 
assign { csub8_w, sub8_w } = { 1'b0, a_in[7:0] } - { 1'b0, b_in[7:0] };
assign { csub16_w, sub16_w } = { 1'b0, a_in[15:0] } - { 1'b0, b_in[15:0] };
assign { csbc8_w, sbc8_w } = { 1'b0, a_in[7:0] } - { 1'b0, b_in[7:0] } - { 8'h0, c_in };
assign { csbc16_w, sbc16_w } = { 1'b0, a_in[15:0] } - { 1'b0, b_in[15:0] } - { 16'h0, c_in };
 
assign com8_w = ~a_in[7:0];
assign com16_w = ~a_in[15:0];
assign neg8_w = 8'h0 - a_in[7:0];
assign neg16_w = 16'h0 - a_in[15:0];
 
assign asr8_w = { a_in[7], a_in[7:1] };
assign asr16_w = { a_in[15], a_in[15:1] };
 
assign shr8_w = { 1'b0, a_in[7:1] };
assign shr16_w = { 1'b0, a_in[15:1] };
 
assign shl8_w = { a_in[6:0], 1'b0 };
assign shl16_w = { a_in[14:0], 1'b0 };
 
assign ror8_w = { c_in, a_in[7:1] };
assign ror16_w = { c_in, a_in[15:1] };
 
assign rol8_w = { a_in[6:0], c_in };
assign rol16_w = { a_in[14:0], c_in };
 
assign and8_w = a_in[7:0] & b_in[7:0];
assign and16_w = a_in[15:0] & b_in[15:0];
 
assign or8_w = a_in[7:0] | b_in[7:0];
assign or16_w = a_in[15:0] | b_in[15:0];
 
assign eor8_w = a_in[7:0] ^ b_in[7:0];
assign eor16_w = a_in[15:0] ^ b_in[15:0];
assign mul16_w = a_in[7:0] * b_in[7:0];
 
// ADD, ADC
assign { cadd8_r, add8_r } = { cadd8_w, add8_w };
assign vadd8_r = (a_in[7] & b_in[7] & (~add8_w[7])) | ((~a_in[7]) & (~b_in[7]) & add8_w[7]);
assign { cadd16_r, add16_r } = { cadd16_w, add16_w };
assign vadd16_r = (a_in[15] & b_in[15] & (~add16_w[15])) | ((~a_in[15]) & (~b_in[15]) & add16_w[15]);
assign { cadc8_r, adc8_r } = { cadd8_w, add8_w };
assign vadc8_r = (a_in[7] & b_in[7] & (~add8_w[7])) | ((~a_in[7]) & (~b_in[7]) & adc8_w[7]);
assign { cadc16_r, adc16_r } = { cadd16_w, add16_w };
assign vadc16_r = (a_in[15] & b_in[15] & (~add16_w[15])) | ((~a_in[15]) & (~b_in[15]) & adc16_w[15]);
// SUB, SUBC
assign { csub8_r, sub8_r } = { csub8_w, sub8_w };
assign vsub8_r = (a_in[7] & (~b_in[7]) & (~sub8_w[7])) | ((~a_in[7]) & b_in[7] & sub8_w[7]);
assign { csub16_r, sub16_r } = { csub16_w, sub16_w };
assign vsub16_r = (a_in[15] & b_in[15] & (~add16_w[15])) | ((~a_in[15]) & b_in[15] & sub16_w[15]);
assign { csbc8_r, sbc8_r } = { csbc8_w, sbc8_w };
assign vsbc8_r = (a_in[7] & b_in[7] | (~sbc8_w[7])) | ((~a_in[7]) & b_in[7] & sbc8_w[7]);
assign { csbc16_r, sbc16_r } = { csbc16_w, sbc16_w };
assign vsbc16_r = (a_in[15] & b_in[15] & (~sbc16_w[15])) | ((~a_in[15]) & b_in[15] & sbc16_w[15]);
// COM
assign com8_r = com8_w;
assign ccom8_r = com8_w != 8'h0 ? 1'b1:1'b0;
assign vcom8_r = 1'b0;
assign com16_r = com16_w;
assign ccom16_r = com16_w != 16'h0 ? 1'b1:1'b0;
assign vcom16_r = 1'b0;
// NEG
assign neg8_r = neg8_w;
assign cneg8_r = neg8_w[7] | neg8_w[6] | neg8_w[5] | neg8_w[4] | neg8_w[3] | neg8_w[2] | neg8_w[1] | neg8_w[0];
assign vneg8_r = neg8_w[7] & (~neg8_w[6]) & (~neg8_w[5]) & (~neg8_w[4]) & (~neg8_w[3]) & (~neg8_w[2]) & (~neg8_w[1]) & (~neg8_w[0]);
assign neg16_r = neg16_w;
assign vneg16_r = neg16_w[15] & (~neg16_w[14]) & (~neg16_w[13]) & (~neg16_w[12]) & (~neg16_w[11]) & (~neg16_w[10]) & (~neg16_w[9]) & (~neg16_w[8]) & (~neg16_w[7]) & (~neg16_w[6]) & (~neg16_w[5]) & (~neg16_w[4]) & (~neg16_w[3]) & (~neg16_w[2]) & (~neg16_w[1]) & (~neg16_w[0]);
assign cneg16_r = neg16_w[15] | neg16_w[14] | neg16_w[13] | neg16_w[12] | neg16_w[11] | neg16_w[10] | neg16_w[9] & neg16_w[8] | neg16_w[7] | neg16_w[6] | neg16_w[5] | neg16_w[4] | neg16_w[3] | neg16_w[2] | neg16_w[1] | neg16_w[0];
// ASR
assign asr8_r = asr8_w;
assign casr8_r = a_in[0];
assign vasr8_r = a_in[0] ^ asr8_w[7];
assign asr16_r = asr16_w;
assign casr16_r = a_in[0];
assign vasr16_r = a_in[0] ^ asr16_w[15];
// SHR
assign shr8_r = shr8_w;
assign cshr8_r = a_in[0];
assign vshr8_r = a_in[0] ^ shr8_w[7];
assign shr16_r = shr16_w;
assign cshr16_r = a_in[0];
assign vshr16_r = a_in[0] ^ shr16_w[15];
// SHL
assign shl8_r = shl8_w;
assign cshl8_r = a_in[7];
assign vshl8_r = a_in[7] ^ shl8_w[7];
assign shl16_r = shl16_w;
assign cshl16_r = a_in[15];
assign vshl16_r = a_in[15] ^ shl16_w[15];
// ROR
assign ror8_r = ror8_w;
assign cror8_r = a_in[0];
assign vror8_r = a_in[0] ^ shr8_w[7];
assign ror16_r = ror16_w;
assign cror16_r = a_in[0];
assign vror16_r = a_in[0] ^ ror16_w[15];
// ROL
assign rol8_r = shl8_w;
assign crol8_r = a_in[7];
assign vrol8_r = a_in[7] ^ rol8_w[7];
assign rol16_r = rol16_w;
assign crol16_r = a_in[15];
assign vrol16_r = a_in[15] ^ rol16_w[15];
// AND
assign and8_r = and8_w;
assign cand8_r = c_in;
assign vand8_r = 1'b0;
assign and16_r = and16_w;
assign cand16_r = c_in;
assign vand16_r = 1'b0;
// OR
assign or8_r = or8_w;
assign or16_r = or16_w;
// EOR
assign eor8_r = eor8_w;
assign eor16_r = eor16_w;
// MUL
assign mul16_r = mul16_w;
assign cmul16_r = mul16_w[7];
// DAA
assign daa_lnm9 = (a_in[3:0] > 9);
assign daa8l_r = (daa_lnm9 | h_in ) ? a_in[3:0] + 4'h6:a_in[3:0];
assign daa8h_r = ((a_in[7:4] > 9) || (c_in == 1'b1) || (a_in[7] & daa_lnm9)) ? a_in[7:4] + 4'h6:a_in[7:4];
assign cdaa8_r = daa8h_r < a_in[7:4];
 
reg c8, h8, n8, v8, z8, c16, n16, v16, z16;
reg [7:0] q8;
reg [15:0] q16;
always @(*)
begin
q8 = 8'h0;
q16 = 16'h0;
c8 = c_in;
h8 = h_in;
v8 = v_in;
c16 = c_in;
v16 = v_in;
case (opcode_in)
`ADD:
begin
q8 = add8_r;
c8 = cadd8_r;
v8 = vadd8_r;
q16 = add16_r;
c16 = cadd16_r;
v16 = vadd16_r;
end
`ADC:
begin
q8 = adc8_r;
c8 = cadc8_r;
v8 = vadc8_r;
q16 = adc16_r;
c16 = cadc16_r;
v16 = vadc16_r;
end
`CMP, `SUB: // for CMP no register result is written back
begin
q8 = sub8_r;
c8 = csub8_r;
v8 = vsub8_r;
q16 = sub16_r;
c16 = csub16_r;
v16 = vsub16_r;
end
`SBC:
begin
q8 = sbc8_r;
c8 = csbc8_r;
v8 = vsbc8_r;
q16 = sbc16_r;
c16 = csbc16_r;
v16 = vsbc16_r;
end
`COM:
begin
q8 = com8_r;
c8 = com8_r;
v8 = vcom8_r;
q16 = com16_r;
c16 = ccom16_r;
v16 = vcom16_r;
end
`NEG:
begin
q8 = neg8_r;
c8 = cneg8_r;
v8 = vneg8_r;
q16 = neg16_r;
c16 = cneg16_r;
v16 = vneg16_r;
end
`ASR:
begin
q8 = asr8_r;
c8 = casr8_r;
v8 = vasr8_r;
q16 = asr16_r;
c16 = casr16_r;
v16 = vasr16_r;
end
`LSR:
begin
q8 = shr8_r;
c8 = cshr8_r;
v8 = vshr8_r;
q16 = shr16_r;
c16 = cshr16_r;
v16 = vshr16_r;
end
`LSL:
begin
q8 = shl8_r;
c8 = cshl8_r;
v8 = vshl8_r;
q16 = shl16_r;
c16 = cshl16_r;
v16 = vshl16_r;
end
`ROR:
begin
q8 = ror8_r;
c8 = cror8_r;
v8 = vror8_r;
q16 = ror16_r;
c16 = cror16_r;
v16 = vror16_r;
end
`ROL:
begin
q8 = rol8_r;
c8 = crol8_r;
v8 = vrol8_r;
q16 = rol16_r;
c16 = crol16_r;
v16 = vrol16_r;
end
`AND:
begin
q8 = and8_r;
c8 = cand8_r;
v8 = vand8_r;
`ifdef HD6309
q16 = and16_r;
c16 = cand16_r;
v16 = vand16_r;
`endif
end
`OR:
begin
q8 = or8_r;
c8 = cand8_r;
v8 = vand8_r;
`ifdef HD6309
q16 = or16_r;
c16 = cand16_r;
v16 = vand16_r;
`endif
end
`EOR:
begin
q8 = eor8_r;
c8 = cand8_r;
v8 = vand8_r;
`ifdef HD6309
q16 = eor16_r;
c16 = cand16_r;
v16 = vand16_r;
`endif
end
`DAA:
begin // V is undefined, so we don't touch it
q8 = { daa8h_r, daa8l_r };
c8 = cdaa8_r;
end
`MUL:
begin
q16 = mul16_r;
c16 = cmul16_r;
end
`LD:
begin
v8 = 0;
v16 = 0;
q8 = b_in[7:0];
q16 = b_in[15:0];
end
`ST:
begin
q8 = a_in[7:0];
q16 = a_in[15:0];
end
`T816: // zero extend 8 -> 16
begin
q16 = { 8'h0, b_in[7:0] };
end
`T168L: // 16L -> 8
begin
q8 = b_in[7:0];
end
`T168H: // 16L -> 8
begin
q8 = b_in[15:8];
end
`SEXT: // sign extend
begin
q16 = { b_in[7] ? 8'hff:8'h00, b_in[7:0] };
end
endcase
end
 
reg [7:0] regq8;
reg [15:0] regq16;
reg reg_n_in, reg_z_in;
/* register before second mux */
always @(posedge clk)
begin
regq8 <= q8;
regq16 <= q16;
reg_n_in <= n_in;
reg_z_in <= z_in;
end
 
/* Negative & zero flags */
always @(*)
begin
n8 = regq8[7];
z8 = regq8 == 8'h0;
n16 = regq16[15];
z16 = regq16 == 16'h0;
case (opcode_in)
`ADD:
begin
end
`ADC:
begin
end
`CMP, `SUB: // for CMP no register result is written back
begin
end
`SBC:
begin
end
`COM:
begin
end
`NEG:
begin
end
`ASR:
begin
end
`LSR:
begin
end
`LSL:
begin
end
`ROR:
begin
end
`ROL:
begin
end
`AND:
begin
end
`OR:
begin
end
`EOR:
begin
end
`DAA:
begin // V is undefined, so we don't touch it
end
`MUL:
begin
n16 = reg_n_in;
z16 = reg_z_in;
end
`LD:
begin
end
`ST:
begin
end
`T816: // zero extend 8 -> 16
begin
n16 = reg_n_in;
z16 = reg_z_in;
end
`T168L: // 16L -> 8
begin
n8 = reg_n_in;
z8 = reg_z_in;
end
`T168H: // 16L -> 8
begin
n8 = reg_n_in;
z8 = reg_z_in;
end
`SEXT: // sign extend
begin
n16 = reg_n_in;
z16 = reg_z_in;
end
endcase
end
 
 
always @(*)
begin
q_out[15:8] = regq16[15:8];
if (sz_in)
q_out[7:0] = regq16[7:0];
else
q_out[7:0] = regq8;
case (opcode_in)
`ORCC:
CCRo = CCR | b_in[7:0];
`ANDCC:
CCRo = CCR & b_in[7:0];
default:
if (sz_in) // 16 bit
CCRo = { CCR[7:4], n16, z16, v16, c16 };
else
CCRo = { CCR[7:6], CCR[5], h8, n8, z8, v8, c8 };
endcase
end
 
initial
begin
end
endmodule
 
 
/*
TERMS OF USE: MIT License
 
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
 
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
 
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
/rtl/verilog/BUGS.txt
0,0 → 1,9
Known bugs are described here
 
28.12.13
--------
 
- EXG doesn't work, the register file can only be written once in the WriteBack cycle.
- LEAX/LEAY do not modify the Z flag
- The E flag is not read back when RTI is processed. This means that FIRQ will not return
correctly.
/sim/tb.v
0,0 → 1,237
/* MC6809/HD6309 Compatible core
* (c) 2013 R.A. Paz Schmidt rapazschmidt@gmail.com
*
* Distributed under the terms of the Lesser GPL
*/
`timescale 1ns/1ns
`include "MC6809_cpu.v"
`include "alu16.v"
`include "decoders.v"
`include "regblock.v"
 
module tb(output wire [15:0] addr_o, output wire [7:0] data_o_o);
 
reg clk, reset;
 
assign addr_o = addr;
assign data_o_o = data_o;
wire [15:0] addr;
wire [7:0] data_o, data_i;
wire oe, we;
always
#5 clk = ~clk;
MC6809_cpu cpu(
.cpu_clk(clk),
.cpu_reset_n(reset),
.cpu_we_o(we),
.cpu_oe_o(oe),
.cpu_addr_o(addr),
.cpu_data_i(data_i),
.cpu_data_o(data_o)
);
 
memory imem(addr, !oe, !we, data_i, data_o);
initial
begin
$dumpvars;
clk = 0;
reset = 0;
#0
#46
reset = 1;
#2000
$finish;
end
 
endmodule
 
module memory(
input wire [15:0] addr,
input wire oe,
input wire we,
output wire [7:0] data_o,
input wire [7:0] data_i
);
reg [7:0] mem[65535:0];
reg [7:0] latecheddata;
wire [7:0] mem0, mem1, mem2, mem3;
 
assign mem0 = mem[0];
assign mem1 = mem[1];
assign mem2 = mem[2];
assign mem3 = mem[3];
 
assign data_o = latecheddata;
always @(negedge oe)
latecheddata <= mem[addr];
always @(negedge we)
begin
mem[addr] <= data_i;
$display("W %04x = %02x %t", addr, data_i, $time);
end
 
always @(negedge oe)
begin
$display("R %04x = %02x %t", addr, mem[addr], $time);
end
//`define READTESTBIN
integer i;
initial
begin
`ifdef READTESTBIN
$readmemh("instructions_test.hex", mem);
$display("instructions_test.hex read");
mem[16'hfffe] = 8'h00; // setup reset
mem[16'hffff] = 8'h00;
`else
for (i = 0; i < 65536; i=i+1)
mem[i] = 8'ha5;
 
mem[16'h1000] = 8'h3f; // lda #$10
mem[16'h1001] = 8'h10; //
mem[16'h1002] = 8'hc6; // ldb #$12
mem[16'h1003] = 8'h12; //
mem[16'h1004] = 8'h3d; // mul
mem[16'h1005] = 8'h4c; // inca
mem[16'h1006] = 8'h5c; // incb
mem[16'h1007] = 8'h9d; // jsr
mem[16'h1008] = 8'h0e; //
mem[16'h1009] = 8'h12; // nop
mem[16'h100a] = 8'h20; // bre *
mem[16'h100b] = 8'hfe; //
mem[16'h100c] = 8'h12; //
mem[16'h100d] = 8'h39; //
mem[16'h100e] = 8'h39; //
 
mem[16'h2000] = 8'h3b; // rti
mem[16'h2002] = 8'h3b; // rti
mem[16'h2004] = 8'h3b; // rti
mem[16'h2006] = 8'h3b; // rti
mem[16'h2008] = 8'h3b; // rti
mem[16'h200a] = 8'h3b; // rti
mem[16'h200c] = 8'h3b; // rti
mem[16'h200e] = 8'h3b; // rti
/*
// test indexed store
mem[16'h1000] = 8'h86; // lda #$fe
mem[16'h1001] = 8'h02; //
mem[16'h1002] = 8'h9e; // ldx $00 (direct)
mem[16'h1003] = 8'h00; //
mem[16'h1004] = 8'ha7; // lda ,x
mem[16'h1005] = 8'b10000100; // ofs0
mem[16'h1006] = 8'ha7; // lda ,x+
mem[16'h1007] = 8'b10000000; //
 
mem[16'h1008] = 8'ha7; // lda ,x++
mem[16'h1009] = 8'b10000001; //
mem[16'h100a] = 8'ha6; // lda ,-x
mem[16'h100b] = 8'b10000010; //
mem[16'h100c] = 8'ha7; // lda ,--x
mem[16'h100d] = 8'b10000011; //
 
mem[16'h100e] = 8'ha7; // lda 0,x ofs 5
mem[16'h100f] = 8'h00; //
mem[16'h1010] = 8'ha7; // lda 0,x ofs 8
mem[16'h1011] = 8'b10001000; //
mem[16'h1012] = 8'h00; //
mem[16'h1013] = 8'ha7; // lda 0,x ofs 16
mem[16'h1014] = 8'b10001001; //
mem[16'h1015] = 8'h00; //
mem[16'h1016] = 8'h00; //
*/
 
/* test indexed load
mem[16'h1000] = 8'h86; // lda #$02
mem[16'h1001] = 8'h02; //
mem[16'h1002] = 8'h9e; // ldx $00 (direct)
mem[16'h1003] = 8'h00; //
mem[16'h1004] = 8'ha6; // lda ,x
mem[16'h1005] = 8'b10000100; // ofs0
mem[16'h1006] = 8'ha6; // lda ,x+
mem[16'h1007] = 8'b10000000; //
 
mem[16'h1008] = 8'ha6; // lda ,x++
mem[16'h1009] = 8'b10000001; //
mem[16'h100a] = 8'ha6; // lda ,-x
mem[16'h100b] = 8'b10000010; //
mem[16'h100c] = 8'ha6; // lda ,--x
mem[16'h100d] = 8'b10000011; //
 
mem[16'h100e] = 8'ha6; // lda 0,x ofs 5
mem[16'h100f] = 8'h00; //
mem[16'h1010] = 8'ha6; // lda 0,x ofs 8
mem[16'h1011] = 8'b10001000; //
mem[16'h1012] = 8'h00; //
mem[16'h1013] = 8'ha6; // lda 0,x ofs 16
mem[16'h1014] = 8'b10001001; //
mem[16'h1015] = 8'h00; //
mem[16'h1016] = 8'h00; //
*/
/* test extended
mem[16'h1000] = 8'hc6; // ldb #$fe
mem[16'h1001] = 8'hfe; //
mem[16'h1002] = 8'h86; // lda #$0
mem[16'h1003] = 8'h00; //
mem[16'h1004] = 8'h4c; // inca
mem[16'h1005] = 8'hb7; // sta $0000
mem[16'h1006] = 8'h00; //
mem[16'h1007] = 8'h00; //
 
mem[16'h1008] = 8'hb6; // lda $0000
mem[16'h1009] = 8'h00; //
mem[16'h100a] = 8'h00; //
 
mem[16'h100b] = 8'h26; // bne$.-5
mem[16'h100c] = 8'hf7; //
 
mem[16'h100d] = 8'h5c; // incb
 
mem[16'h100e] = 8'hf7; // stb $0001
mem[16'h100f] = 8'h00; //
mem[16'h1010] = 8'h01; //
mem[16'h1011] = 8'h20; // bra
mem[16'h1012] = 8'hec; // $.-18
*/
mem[16'hfff0] = 8'h20; // reset
mem[16'hfff1] = 8'h00;
mem[16'hfff2] = 8'h20; // reset
mem[16'hfff3] = 8'h02;
mem[16'hfff4] = 8'h20; // reset
mem[16'hfff5] = 8'h04;
mem[16'hfff6] = 8'h20; // reset
mem[16'hfff7] = 8'h06;
mem[16'hfff8] = 8'h20; // reset
mem[16'hfff9] = 8'h08;
mem[16'hfffa] = 8'h20; // reset
mem[16'hfffb] = 8'h0a;
mem[16'hfffc] = 8'h20; // reset
mem[16'hfffd] = 8'h0c;
mem[16'hfffe] = 8'h10; // reset
mem[16'hffff] = 8'h00;
`endif
end
endmodule
/sim/README.txt
0,0 → 1,9
MC6809/HD6309 compatible core.
 
Simulation can be done with icarus verilog.
 
$ iverilog tb.v ../rtl/verilog/*.v
$ vvp a.out
 
a dump file dump.vcd will be created. This file can be viewed with GTKWave.
Simulation with other tools is also possible.
/syn/lattice/logs/P6809_P6809_par.html
0,0 → 1,506
<HTML>
<HEAD><TITLE>Place & Route Report</TITLE>
<STYLE TYPE="text/css">
<!--
+} +--> + + +
PAR: Place And Route Diamond (64-bit) 2.2.0.101.








    +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.








    +Copyright (c) 1995 AT&T Corp.   All rights reserved.








    +Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.








    +Copyright (c) 2001 Agere Systems   All rights reserved.








    +Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.








    +Wed Dec 25 17:50:32 2013








    +








    +/usr/local/diamond/2.2_x64/ispfpga/bin/lin64/par -f P6809_P6809.p2t








    +P6809_P6809_map.ncd P6809_P6809.dir P6809_P6809.prf








    +








    +








    +Preference file: P6809_P6809.prf.








    +








    +Cost Table Summary








    +Level/      Number      Worst       Timing      Run         NCD








    +Cost [ncd]  Unrouted    Slack       Score       Time        Status








    +----------  --------    -----       --------    -----       ------








    +5_1   *     0           -4.091      12558270    28          Complete        








    +








    +








    +* : Design saved.








    +








    +Total (real) run time for 1-seed: 28 secs 








    +








    +par done!








    +








    +Lattice Place and Route Report for Design "P6809_P6809_map.ncd"








    +Wed Dec 25 17:50:32 2013








    +








    +








    +Best Par Run








    +PAR: Place And Route Diamond (64-bit) 2.2.0.101.








    +Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF P6809_P6809_map.ncd P6809_P6809.dir/5_1.ncd P6809_P6809.prf








    +Preference file: P6809_P6809.prf.








    +Placement level-cost: 5-1.








    +Routing Iterations: 6








    +








    +Loading design for application par from file P6809_P6809_map.ncd.








    +Design name: CC3_top








    +NCD version: 3.2








    +Vendor:      LATTICE








    +Device:      LCMXO2-7000HE








    +Package:     TQFP144








    +Performance: 4








    +Loading device for application par from file 'xo2c7000.nph' in environment: /usr/local/diamond/2.2_x64/ispfpga.








    +Package Status:                     Final          Version 1.36








    +Performance Hardware Data Status:   Final)         Version 23.4








    +License checked out.








    +








    +








    +Ignore Preference Error(s):  True








    +








    +Device utilization summary:








    +








    +   PIO (prelim)   49+4(JTAG)/336     14% used








    +                  49+4(JTAG)/115     42% bonded








    +   IOLOGIC            8/336           2% used








    +








    +   SLICE           1163/3432         33% used








    +








    +   GSR                1/1           100% used








    +   EBR                2/26            7% used








    +








    +








    +INFO: Design contains EBR with ASYNC Reset Mode that has a limitation: The use of the EBR block asynchronous reset requires that certain timing be met between the clock and the reset within the memory block. See the device specific datasheet for additional details.








    +INFO: Design contains pre-loadable EBR during configuration that has a requirement: Since the GSR is disabled for the EBR, make sure write enable and chip enable are inactive during wake-up, so that the pre-loaded initialization values will not be corrupted during wake-up state.








    +Number of Signals: 2675








    +Number of Connections: 8924








    +








    +Pin Constraint Summary:








    +   49 out of 49 pins locked (100% locked).








    +








    +The following 1 signal is selected to use the primary clock routing resources:








    +    cpu_clkgen (driver: clk40_i, clk load #: 315)








    +








    +








    +The following 6 signals are selected to use the secondary clock routing resources:








    +    cpu_clk (driver: SLICE_477, clk load #: 0, sr load #: 0, ce load #: 95)








    +    cpu0/cff_1_sqmuxa_0_RNIL5DT (driver: cpu0/SLICE_865, clk load #: 0, sr load #: 0, ce load #: 43)








    +    cpu0/regs/regh[4]_1_sqmuxa_1_1_RNI7MAL1 (driver: cpu0/regs/SLICE_829, clk load #: 0, sr load #: 0, ce load #: 12)








    +    cpu0/regs/regh[3]_1_sqmuxa_3_0_RNI9DKR1 (driver: cpu0/regs/SLICE_830, clk load #: 0, sr load #: 0, ce load #: 12)








    +    cpu0/regs/regh[2]_0_sqmuxa_i_a2_1_RNIJL6H2 (driver: cpu0/regs/SLICE_887, clk load #: 0, sr load #: 0, ce load #: 12)








    +    cpu0/regs/regh[1]_0_sqmuxa_1_i_a2_2_RNI192E2 (driver: cpu0/regs/SLICE_886, clk load #: 0, sr load #: 0, ce load #: 12)








    +








    +Signal cpu0.cpu_reset_i_2_i is selected as Global Set/Reset.








    +Starting Placer Phase 0.








    +..........








    +Finished Placer Phase 0.  REAL time: 4 secs 








    +








    +Starting Placer Phase 1.








    +......................








    +Placer score = 808498.








    +Finished Placer Phase 1.  REAL time: 12 secs 








    +








    +Starting Placer Phase 2.








    +.








    +Placer score =  797364








    +Finished Placer Phase 2.  REAL time: 13 secs 








    +








    +








    +








    +Clock Report








    +








    +Global Clock Resources:








    +  CLK_PIN    : 1 out of 8 (12%)








    +  PLL        : 0 out of 2 (0%)








    +  DCM        : 0 out of 2 (0%)








    +  DCC        : 0 out of 8 (0%)








    +








    +Quadrants All (TL, TR, BL, BR) - Global Clocks:








    +  PRIMARY "cpu_clkgen" from comp "clk40_i" on CLK_PIN site "27 (PL22A)", clk load = 315








    +  SECONDARY "cpu_clk" from Q0 on comp "SLICE_477" on site "R21C20B", clk load = 0, ce load = 95, sr load = 0








    +  SECONDARY "cpu0/cff_1_sqmuxa_0_RNIL5DT" from F0 on comp "cpu0/SLICE_865" on site "R14C18A", clk load = 0, ce load = 43, sr load = 0








    +  SECONDARY "cpu0/regs/regh[4]_1_sqmuxa_1_1_RNI7MAL1" from F1 on comp "cpu0/regs/SLICE_829" on site "R21C18C", clk load = 0, ce load = 12, sr load = 0








    +  SECONDARY "cpu0/regs/regh[3]_1_sqmuxa_3_0_RNI9DKR1" from F1 on comp "cpu0/regs/SLICE_830" on site "R14C18D", clk load = 0, ce load = 12, sr load = 0








    +  SECONDARY "cpu0/regs/regh[2]_0_sqmuxa_i_a2_1_RNIJL6H2" from F0 on comp "cpu0/regs/SLICE_887" on site "R14C18B", clk load = 0, ce load = 12, sr load = 0








    +  SECONDARY "cpu0/regs/regh[1]_0_sqmuxa_1_i_a2_2_RNI192E2" from F0 on comp "cpu0/regs/SLICE_886" on site "R14C18C", clk load = 0, ce load = 12, sr load = 0








    +








    +  PRIMARY  : 1 out of 8 (12%)








    +  SECONDARY: 6 out of 8 (75%)








    +








    +Edge Clocks:








    +  No edge clock selected.








    +








    +








    +








    +








    +I/O Usage Summary (final):








    +   49 out of 336 (14.6%) PIO sites used.








    +   49 out of 115 (42.6%) bonded PIO sites used.








    +   Number of PIO comps: 49; differential: 0








    +   Number of Vref pins used: 0








    +








    +I/O Bank Usage Summary:








    ++----------+----------------+------------+-----------+








    +| I/O Bank | Usage          | Bank Vccio | Bank Vref |








    ++----------+----------------+------------+-----------+








    +| 0        | 12 / 28 ( 42%) | 2.5V       | -         |








    +| 1        | 13 / 29 ( 44%) | 2.5V       | -         |








    +| 2        | 23 / 29 ( 79%) | 2.5V       | -         |








    +| 3        | 1 / 9 ( 11%)   | 2.5V       | -         |








    +| 4        | 0 / 10 (  0%)  | -          | -         |








    +| 5        | 0 / 10 (  0%)  | -          | -         |








    ++----------+----------------+------------+-----------+








    +








    +Total placer CPU time: 12 secs 








    +








    +Dumping design to file P6809_P6809.dir/5_1.ncd.








    +








    +0 connections routed; 8924 unrouted.








    +Starting router resource preassignment








    +








    +Completed router resource preassignment. Real time: 16 secs 








    +








    +Start NBR router at Wed Dec 25 17:50:48 CET 2013








    +








    +*****************************************************************








    +Info: NBR allows conflicts(one node used by more than one signal)








    +      in the earlier iterations. In each iteration, it tries to  








    +      solve the conflicts while keeping the critical connections 








    +      routed as short as possible. The routing process is said to








    +      be completed when no conflicts exist and all connections   








    +      are routed.                                                








    +Note: NBR uses a different method to calculate timing slacks. The








    +      worst slack and total negative slack may not be the same as








    +      that in TRCE report. You should always run TRCE to verify  








    +      your design. Thanks.                                       








    +*****************************************************************








    +








    +Start NBR special constraint process at Wed Dec 25 17:50:48 CET 2013








    +








    +Start NBR section for initial routing








    +Level 1, iteration 1








    +137(0.04%) conflicts; 7446(83.44%) untouched conns; 1425225 (nbr) score; 








    +Estimated worst slack/total negative slack: -3.332ns/-1425.225ns; real time: 18 secs 








    +Level 2, iteration 1








    +162(0.04%) conflicts; 6336(71.00%) untouched conns; 1178362 (nbr) score; 








    +Estimated worst slack/total negative slack: -3.339ns/-1178.363ns; real time: 19 secs 








    +Level 3, iteration 1








    +89(0.02%) conflicts; 5385(60.34%) untouched conns; 1500920 (nbr) score; 








    +Estimated worst slack/total negative slack: -3.347ns/-1500.921ns; real time: 20 secs 








    +Level 4, iteration 1








    +349(0.09%) conflicts; 0(0.00%) untouched conn; 1551317 (nbr) score; 








    +Estimated worst slack/total negative slack: -3.425ns/-1551.318ns; real time: 21 secs 








    +








    +Info: Initial congestion level at 75% usage is 0








    +Info: Initial congestion area  at 75% usage is 5 (0.50%)








    +








    +Start NBR section for normal routing








    +Level 1, iteration 1








    +88(0.02%) conflicts; 402(4.50%) untouched conns; 1210645 (nbr) score; 








    +Estimated worst slack/total negative slack: -3.167ns/-1210.645ns; real time: 21 secs 








    +Level 4, iteration 1








    +237(0.06%) conflicts; 0(0.00%) untouched conn; 1243629 (nbr) score; 








    +Estimated worst slack/total negative slack: -3.155ns/-1243.630ns; real time: 22 secs 








    +Level 4, iteration 2








    +131(0.03%) conflicts; 0(0.00%) untouched conn; 1252609 (nbr) score; 








    +Estimated worst slack/total negative slack: -3.245ns/-1252.609ns; real time: 23 secs 








    +Level 4, iteration 3








    +97(0.03%) conflicts; 0(0.00%) untouched conn; 1308083 (nbr) score; 








    +Estimated worst slack/total negative slack: -3.416ns/-1308.084ns; real time: 23 secs 








    +Level 4, iteration 4








    +71(0.02%) conflicts; 0(0.00%) untouched conn; 1308083 (nbr) score; 








    +Estimated worst slack/total negative slack: -3.416ns/-1308.084ns; real time: 23 secs 








    +Level 4, iteration 5








    +71(0.02%) conflicts; 0(0.00%) untouched conn; 1426563 (nbr) score; 








    +Estimated worst slack/total negative slack: -3.558ns/-1426.563ns; real time: 24 secs 








    +Level 4, iteration 6








    +50(0.01%) conflicts; 0(0.00%) untouched conn; 1426563 (nbr) score; 








    +Estimated worst slack/total negative slack: -3.558ns/-1426.563ns; real time: 24 secs 








    +Level 4, iteration 7








    +30(0.01%) conflicts; 0(0.00%) untouched conn; 1480393 (nbr) score; 








    +Estimated worst slack/total negative slack: -3.626ns/-1480.394ns; real time: 24 secs 








    +Level 4, iteration 8








    +23(0.01%) conflicts; 0(0.00%) untouched conn; 1480393 (nbr) score; 








    +Estimated worst slack/total negative slack: -3.626ns/-1480.394ns; real time: 24 secs 








    +Level 4, iteration 9








    +17(0.00%) conflicts; 0(0.00%) untouched conn; 1550078 (nbr) score; 








    +Estimated worst slack/total negative slack: -3.626ns/-1550.079ns; real time: 24 secs 








    +Level 4, iteration 10








    +16(0.00%) conflicts; 0(0.00%) untouched conn; 1550078 (nbr) score; 








    +Estimated worst slack/total negative slack: -3.626ns/-1550.079ns; real time: 24 secs 








    +Level 4, iteration 11








    +15(0.00%) conflicts; 0(0.00%) untouched conn; 1549789 (nbr) score; 








    +Estimated worst slack/total negative slack: -3.656ns/-1549.790ns; real time: 25 secs 








    +Level 4, iteration 12








    +17(0.00%) conflicts; 0(0.00%) untouched conn; 1549789 (nbr) score; 








    +Estimated worst slack/total negative slack: -3.656ns/-1549.790ns; real time: 25 secs 








    +Level 4, iteration 13








    +9(0.00%) conflicts; 0(0.00%) untouched conn; 1540315 (nbr) score; 








    +Estimated worst slack/total negative slack: -3.634ns/-1540.316ns; real time: 25 secs 








    +Level 4, iteration 14








    +7(0.00%) conflicts; 0(0.00%) untouched conn; 1540315 (nbr) score; 








    +Estimated worst slack/total negative slack: -3.634ns/-1540.316ns; real time: 25 secs 








    +Level 4, iteration 15








    +6(0.00%) conflicts; 0(0.00%) untouched conn; 1564368 (nbr) score; 








    +Estimated worst slack/total negative slack: -3.626ns/-1564.369ns; real time: 25 secs 








    +Level 4, iteration 16








    +6(0.00%) conflicts; 0(0.00%) untouched conn; 1564368 (nbr) score; 








    +Estimated worst slack/total negative slack: -3.626ns/-1564.369ns; real time: 25 secs 








    +Level 4, iteration 17








    +6(0.00%) conflicts; 0(0.00%) untouched conn; 1543739 (nbr) score; 








    +Estimated worst slack/total negative slack: -3.634ns/-1543.739ns; real time: 25 secs 








    +Level 4, iteration 18








    +7(0.00%) conflicts; 0(0.00%) untouched conn; 1543739 (nbr) score; 








    +Estimated worst slack/total negative slack: -3.634ns/-1543.739ns; real time: 25 secs 








    +Level 4, iteration 19








    +6(0.00%) conflicts; 0(0.00%) untouched conn; 1539700 (nbr) score; 








    +Estimated worst slack/total negative slack: -3.626ns/-1539.701ns; real time: 25 secs 








    +Level 4, iteration 20








    +4(0.00%) conflicts; 0(0.00%) untouched conn; 1539700 (nbr) score; 








    +Estimated worst slack/total negative slack: -3.626ns/-1539.701ns; real time: 25 secs 








    +Level 4, iteration 21








    +4(0.00%) conflicts; 0(0.00%) untouched conn; 1541625 (nbr) score; 








    +Estimated worst slack/total negative slack: -3.627ns/-1541.626ns; real time: 25 secs 








    +Level 4, iteration 22








    +2(0.00%) conflicts; 0(0.00%) untouched conn; 1541625 (nbr) score; 








    +Estimated worst slack/total negative slack: -3.627ns/-1541.626ns; real time: 26 secs 








    +Level 4, iteration 23








    +1(0.00%) conflict; 0(0.00%) untouched conn; 1553537 (nbr) score; 








    +Estimated worst slack/total negative slack: -3.627ns/-1553.538ns; real time: 26 secs 








    +Level 4, iteration 24








    +5(0.00%) conflicts; 0(0.00%) untouched conn; 1553537 (nbr) score; 








    +Estimated worst slack/total negative slack: -3.627ns/-1553.538ns; real time: 26 secs 








    +Level 4, iteration 25








    +3(0.00%) conflicts; 0(0.00%) untouched conn; 1631557 (nbr) score; 








    +Estimated worst slack/total negative slack: -3.805ns/-1631.557ns; real time: 26 secs 








    +Level 4, iteration 26








    +1(0.00%) conflict; 0(0.00%) untouched conn; 1631557 (nbr) score; 








    +Estimated worst slack/total negative slack: -3.805ns/-1631.557ns; real time: 26 secs 








    +Level 4, iteration 27








    +1(0.00%) conflict; 0(0.00%) untouched conn; 1553196 (nbr) score; 








    +Estimated worst slack/total negative slack: -3.627ns/-1553.197ns; real time: 26 secs 








    +Level 4, iteration 28








    +1(0.00%) conflict; 0(0.00%) untouched conn; 1553196 (nbr) score; 








    +Estimated worst slack/total negative slack: -3.627ns/-1553.197ns; real time: 26 secs 








    +Level 4, iteration 29








    +1(0.00%) conflict; 0(0.00%) untouched conn; 1553196 (nbr) score; 








    +Estimated worst slack/total negative slack: -3.627ns/-1553.197ns; real time: 26 secs 








    +Level 4, iteration 30








    +1(0.00%) conflict; 0(0.00%) untouched conn; 1553196 (nbr) score; 








    +Estimated worst slack/total negative slack: -3.627ns/-1553.197ns; real time: 26 secs 








    +Level 4, iteration 31








    +1(0.00%) conflict; 0(0.00%) untouched conn; 1553196 (nbr) score; 








    +Estimated worst slack/total negative slack: -3.627ns/-1553.197ns; real time: 26 secs 








    +Level 4, iteration 32








    +1(0.00%) conflict; 0(0.00%) untouched conn; 1553196 (nbr) score; 








    +Estimated worst slack/total negative slack: -3.627ns/-1553.197ns; real time: 26 secs 








    +Level 4, iteration 33








    +1(0.00%) conflict; 0(0.00%) untouched conn; 1553196 (nbr) score; 








    +Estimated worst slack/total negative slack: -3.627ns/-1553.197ns; real time: 26 secs 








    +Level 4, iteration 34








    +0(0.00%) conflict; 0(0.00%) untouched conn; 1553196 (nbr) score; 








    +Estimated worst slack/total negative slack: -3.627ns/-1553.197ns; real time: 26 secs 








    +








    +Start NBR section for performance tunning (iteration 1)








    +Level 4, iteration 1








    +4(0.00%) conflicts; 0(0.00%) untouched conn; 1791659 (nbr) score; 








    +Estimated worst slack/total negative slack: -4.091ns/-1791.660ns; real time: 27 secs 








    +








    +Start NBR section for re-routing








    +Level 4, iteration 1








    +0(0.00%) conflict; 0(0.00%) untouched conn; 1793776 (nbr) score; 








    +Estimated worst slack/total negative slack: -4.091ns/-1793.777ns; real time: 27 secs 








    +








    +Start NBR section for post-routing








    +








    +End NBR router with 0 unrouted connection








    +








    +NBR Summary








    +-----------








    +  Number of unrouted connections : 0 (0.00%)








    +  Number of connections with timing violations : 938 (10.51%)








    +  Estimated worst slack : -4.091ns








    +  Timing score : 12558270








    +-----------








    +Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.








    +








    +








    +








    +------------------------------------------------------------------------------------------------------------------------------------








    +WARNING - par: Hold timing correction is skipped because the worst (setup) slack(-4.091ns) is worse than the default value(0.000ns).








    +------------------------------------------------------------------------------------------------------------------------------------








    +








    +Total CPU time 28 secs 








    +Total REAL time: 28 secs 








    +Completely routed.








    +End of route.  8924 routed (100.00%); 0 unrouted.








    +Checking DRC ... 








    +No errors found.








    +








    +Hold time timing score: 0, hold timing errors: 0








    +








    +Timing score: 12558270 








    +








    +Dumping design to file P6809_P6809.dir/5_1.ncd.








    +








    +








    +All signals are completely routed.








    +








    +








    +PAR_SUMMARY::Run status = completed








    +PAR_SUMMARY::Number of unrouted conns = 0








    +PAR_SUMMARY::Worst  slack> = -4.091








    +PAR_SUMMARY::Timing score> = 12558.270








    +PAR_SUMMARY::Worst  slack> = 








    +PAR_SUMMARY::Timing score> = 








    +








    +Total CPU  time to completion: 28 secs 








    +Total REAL time to completion: 28 secs 








    +








    +par done!








    +








    +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.








    +Copyright (c) 1995 AT&T Corp.   All rights reserved.








    +Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.








    +Copyright (c) 2001 Agere Systems   All rights reserved.








    +Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.








    +








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/syn/lattice/logs/hdla_gen_hierarchy.html
0,0 → 1,32
<HTML> <HEAD><TITLE></TITLE> <STYLE TYPE="text/css"> <!-- body,pre{ font-family:'Courier New', monospace; color: #000000; font-size:88%; background-color: #ffffff; } h1 { font-weight: bold; margin-top: 24px; margin-bottom: 10px; border-bottom: 3px solid #000; font-size: 1em; } h2 { font-weight: bold; margin-top: 18px; margin-bottom: 5px; font-size: 0.90em; } h3 { font-weight: bold; margin-top: 12px; margin-bottom: 5px; font-size: 0.80em; } p { font-size:78%; } P.Table { margin-top: 4px; margin-bottom: 4px; margin-right: 4px; margin-left: 4px; } table { border-width: 1px 1px 1px 1px; border-style: solid solid solid solid; border-color: black black black black; border-collapse: collapse; } th { font-weight:bold; padding: 4px; border-width: 1px 1px 1px 1px; border-style: solid solid solid solid; border-color: black black black black; vertical-align:top; text-align:left; font-size:78%; } td { padding: 4px; border-width: 1px 1px 1px 1px; border-style: solid solid solid solid; border-color: black black black black; vertical-align:top; font-size:78%; } a { color:#013C9A; text-decoration:none; } a:visited { color:#013C9A; } a:hover, a:active { text-decoration:underline; color:#5BAFD4; } .pass { background-color: #00ff00; } .fail { background-color: #ff0000; } .comment { font-size: 90%; font-style: italic; } --> </STYLE> </HEAD> <BODY> <PRE>Setting log file to '/home/pacito/02_Elektronik/020_V6809/6809/lattice/P6809/hdla_gen_hierarchy.html'.
INFO: (VHDL-1504) The default vhdl library search path is now "/usr/local/diamond/2.2_x64/cae_library/vhdl_packages/vdbs"
-- (VERI-1482) Analyzing Verilog file /usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v
-- (VERI-1482) Analyzing Verilog file /home/pacito/02_Elektronik/020_V6809/6809/alu16.v
/home/pacito/02_Elektronik/020_V6809/6809/alu16.v(12,10-12,18) INFO: (VERI-1328) analyzing included file /home/pacito/02_Elektronik/020_V6809/6809/defs.v
-- (VERI-1482) Analyzing Verilog file /home/pacito/02_Elektronik/020_V6809/6809/decoders.v
/home/pacito/02_Elektronik/020_V6809/6809/decoders.v(8,10-8,18) INFO: (VERI-1328) analyzing included file /home/pacito/02_Elektronik/020_V6809/6809/defs.v
-- (VERI-1482) Analyzing Verilog file /home/pacito/02_Elektronik/020_V6809/6809/defs.v
-- (VERI-1482) Analyzing Verilog file /home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v
/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v(24,10-24,18) INFO: (VERI-1328) analyzing included file /home/pacito/02_Elektronik/020_V6809/6809/defs.v
-- (VERI-1482) Analyzing Verilog file /home/pacito/02_Elektronik/020_V6809/6809/regblock.v
/home/pacito/02_Elektronik/020_V6809/6809/regblock.v(4,10-4,18) INFO: (VERI-1328) analyzing included file /home/pacito/02_Elektronik/020_V6809/6809/defs.v
-- (VERI-1482) Analyzing Verilog file /home/pacito/02_Elektronik/020_V6809/6809/CC3_top.v
-- (VERI-1482) Analyzing Verilog file /home/pacito/02_Elektronik/020_V6809/6809/lattice/bios2k.v
/home/pacito/02_Elektronik/020_V6809/6809/CC3_top.v(7,8-7,15) INFO: (VERI-1018) compiling module CC3_top
/home/pacito/02_Elektronik/020_V6809/6809/CC3_top.v(7,1-106,10) INFO: (VERI-9000) elaborating module 'CC3_top'
/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v(25,1-968,10) INFO: (VERI-9000) elaborating module 'MC6809_cpu_uniq_1'
/home/pacito/02_Elektronik/020_V6809/6809/lattice/bios2k.v(8,1-171,10) INFO: (VERI-9000) elaborating module 'bios2k_uniq_1'
/home/pacito/02_Elektronik/020_V6809/6809/alu16.v(13,1-496,10) INFO: (VERI-9000) elaborating module 'alu16_uniq_1'
/home/pacito/02_Elektronik/020_V6809/6809/regblock.v(7,1-224,10) INFO: (VERI-9000) elaborating module 'regblock_uniq_1'
/home/pacito/02_Elektronik/020_V6809/6809/decoders.v(9,1-105,10) INFO: (VERI-9000) elaborating module 'decode_regs_uniq_1'
/home/pacito/02_Elektronik/020_V6809/6809/decoders.v(108,1-231,10) INFO: (VERI-9000) elaborating module 'decode_op_uniq_1'
/home/pacito/02_Elektronik/020_V6809/6809/decoders.v(236,1-260,10) INFO: (VERI-9000) elaborating module 'decode_ea_uniq_1'
/home/pacito/02_Elektronik/020_V6809/6809/decoders.v(262,1-332,10) INFO: (VERI-9000) elaborating module 'decode_alu_uniq_1'
/home/pacito/02_Elektronik/020_V6809/6809/decoders.v(334,1-370,10) INFO: (VERI-9000) elaborating module 'test_condition_uniq_1'
/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v(1120,1-1122,10) INFO: (VERI-9000) elaborating module 'VHI_uniq_1'
/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) INFO: (VERI-9000) elaborating module 'DP8KC_uniq_1'
/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) INFO: (VERI-9000) elaborating module 'DP8KC_uniq_2'
/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v(1124,1-1126,10) INFO: (VERI-9000) elaborating module 'VLO_uniq_1'
Design load finished with (0) errors, and (0) warnings.
 
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/syn/lattice/logs/P6809_P6809_pad.html
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<HTML>
<HEAD><TITLE>PAD Specification File</TITLE>
<STYLE TYPE="text/css">
<!--
+} +--> + + +
PAD Specification File








    +***************************








    +








    +PART TYPE:        LCMXO2-7000HE








    +Performance Grade:      4








    +PACKAGE:          TQFP144








    +Package Status:                     Final          Version 1.36








    +








    +Wed Dec 25 17:50:45 2013








    +








    +Pinout by Port Name:








    ++------------+----------+--------------+-------+-----------+-----------+--------------------------------------+








    +| Port Name  | Pin/Bank | Buffer Type  | Site  | PG Enable | BC Enable | Properties                           |








    ++------------+----------+--------------+-------+-----------+-----------+--------------------------------------+








    +| addr_o[0]  | 38/2     | LVCMOS25_OUT | PB4A  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW        |








    +| addr_o[10] | 48/2     | LVCMOS25_OUT | PB13B |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW        |








    +| addr_o[11] | 50/2     | LVCMOS25_OUT | PB16B |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW        |








    +| addr_o[12] | 52/2     | LVCMOS25_OUT | PB18A |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW        |








    +| addr_o[13] | 55/2     | LVCMOS25_OUT | PB23A |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW        |








    +| addr_o[14] | 54/2     | LVCMOS25_OUT | PB18B |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW        |








    +| addr_o[15] | 56/2     | LVCMOS25_OUT | PB23B |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW        |








    +| addr_o[1]  | 40/2     | LVCMOS25_OUT | PB6A  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW        |








    +| addr_o[2]  | 39/2     | LVCMOS25_OUT | PB4B  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW        |








    +| addr_o[3]  | 41/2     | LVCMOS25_OUT | PB6B  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW        |








    +| addr_o[4]  | 42/2     | LVCMOS25_OUT | PB9A  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW        |








    +| addr_o[5]  | 44/2     | LVCMOS25_OUT | PB12A |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW        |








    +| addr_o[6]  | 43/2     | LVCMOS25_OUT | PB9B  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW        |








    +| addr_o[7]  | 45/2     | LVCMOS25_OUT | PB12B |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW        |








    +| addr_o[8]  | 47/2     | LVCMOS25_OUT | PB13A |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW        |








    +| addr_o[9]  | 49/2     | LVCMOS25_OUT | PB16A |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW        |








    +| blue_o     | 74/1     | LVCMOS25_OUT | PR24A |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW        |








    +| cen_o      | 57/2     | LVCMOS25_OUT | PB26A |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW        |








    +| clk40_i    | 27/3     | LVCMOS25_IN  | PL22A |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL  |








    +| cpuclk_o   | 60/2     | LVCMOS25_OUT | PB29B |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW        |








    +| data_io[0] | 143/0    | LVCMOS25_OUT | PT9A  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW        |








    +| data_io[1] | 142/0    | LVCMOS25_OUT | PT9B  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW        |








    +| data_io[2] | 141/0    | LVCMOS25_OUT | PT10A |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW        |








    +| data_io[3] | 140/0    | LVCMOS25_OUT | PT10B |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW        |








    +| data_io[4] | 139/0    | LVCMOS25_OUT | PT11A |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW        |








    +| data_io[5] | 138/0    | LVCMOS25_OUT | PT11B |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW        |








    +| data_io[6] | 133/0    | LVCMOS25_OUT | PT15A |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW        |








    +| data_io[7] | 132/0    | LVCMOS25_OUT | PT15B |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW        |








    +| green_o    | 76/1     | LVCMOS25_OUT | PR23A |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW        |








    +| hsync_o    | 73/1     | LVCMOS25_OUT | PR24B |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW        |








    +| leds_o[0]  | 97/1     | LVCMOS25_OUT | PR7B  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW        |








    +| leds_o[1]  | 98/1     | LVCMOS25_OUT | PR7A  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW        |








    +| leds_o[2]  | 99/1     | LVCMOS25_OUT | PR5B  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW        |








    +| leds_o[3]  | 100/1    | LVCMOS25_OUT | PR5A  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW        |








    +| leds_o[4]  | 104/1    | LVCMOS25_OUT | PR3B  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW        |








    +| leds_o[5]  | 105/1    | LVCMOS25_OUT | PR3A  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW        |








    +| leds_o[6]  | 106/1    | LVCMOS25_OUT | PR2B  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW        |








    +| leds_o[7]  | 107/1    | LVCMOS25_OUT | PR2A  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW        |








    +| oen_o      | 58/2     | LVCMOS25_OUT | PB26B |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW        |








    +| red_o      | 78/1     | LVCMOS25_OUT | PR21A |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW        |








    +| reset_o    | 125/0    | LVCMOS25_OUT | PT22D |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW        |








    +| state_o[0] | 128/0    | LVCMOS25_OUT | PT18A |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW        |








    +| state_o[1] | 127/0    | LVCMOS25_OUT | PT18B |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW        |








    +| state_o[2] | 126/0    | LVCMOS25_OUT | PT22C |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW        |








    +| state_o[3] | 61/2     | LVCMOS25_OUT | PB31A |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW        |








    +| state_o[4] | 65/2     | LVCMOS25_OUT | PB35A |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW        |








    +| state_o[5] | 62/2     | LVCMOS25_OUT | PB31B |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW        |








    +| vsync_o    | 75/1     | LVCMOS25_OUT | PR23B |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW        |








    +| wen_o      | 59/2     | LVCMOS25_OUT | PB29A |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW        |








    ++------------+----------+--------------+-------+-----------+-----------+--------------------------------------+








    +








    +Vccio by Bank:








    ++------+-------+








    +| Bank | Vccio |








    ++------+-------+








    +| 0    | 2.5V  |








    +| 1    | 2.5V  |








    +| 2    | 2.5V  |








    +| 3    | 2.5V  |








    ++------+-------+








    +








    +








    +Vref by Bank:








    ++------+-----+-----------------+---------+








    +| Vref | Pin | Bank # / Vref # | Load(s) |








    ++------+-----+-----------------+---------+








    ++------+-----+-----------------+---------+








    +








    +Pinout by Pin Number:








    ++----------+-----------------------+------------+--------------+--------------+----------------+-----------+-----------+








    +| Pin/Bank | Pin Info              | Preference | Buffer Type  | Site         | Dual Function  | PG Enable | BC Enable |








    ++----------+-----------------------+------------+--------------+--------------+----------------+-----------+-----------+








    +| 1/5      |     unused, PULL:DOWN |            |              | PL3A         | L_GPLLT_FB     |           |           |








    +| 2/5      |     unused, PULL:DOWN |            |              | PL3B         | L_GPLLC_FB     |           |           |








    +| 3/5      |     unused, PULL:DOWN |            |              | PL4A         | L_GPLLT_IN     |           |           |








    +| 4/5      |     unused, PULL:DOWN |            |              | PL4B         | L_GPLLC_IN     |           |           |








    +| 5/5      |     unused, PULL:DOWN |            |              | PL6A         | PCLKT5_0       |           |           |








    +| 6/5      |     unused, PULL:DOWN |            |              | PL6B         | PCLKC5_0       |           |           |








    +| 9/5      |     unused, PULL:DOWN |            |              | PL8A         |                |           |           |








    +| 10/5     |     unused, PULL:DOWN |            |              | PL8B         |                |           |           |








    +| 11/5     |     unused, PULL:DOWN |            |              | PL9A         |                |           |           |








    +| 12/5     |     unused, PULL:DOWN |            |              | PL9B         |                |           |           |








    +| 13/4     |     unused, PULL:DOWN |            |              | PL10A        |                |           |           |








    +| 14/4     |     unused, PULL:DOWN |            |              | PL10B        |                |           |           |








    +| 15/4     |     unused, PULL:DOWN |            |              | PL11A        |                |           |           |








    +| 17/4     |     unused, PULL:DOWN |            |              | PL11B        |                |           |           |








    +| 19/4     |     unused, PULL:DOWN |            |              | PL12A        | PCLKT4_0       |           |           |








    +| 20/4     |     unused, PULL:DOWN |            |              | PL12B        | PCLKC4_0       |           |           |








    +| 21/4     |     unused, PULL:DOWN |            |              | PL15A        |                |           |           |








    +| 22/4     |     unused, PULL:DOWN |            |              | PL15B        |                |           |           |








    +| 23/4     |     unused, PULL:DOWN |            |              | PL17A        |                |           |           |








    +| 24/4     |     unused, PULL:DOWN |            |              | PL17B        |                |           |           |








    +| 25/3     |     unused, PULL:DOWN |            |              | PL19A        |                |           |           |








    +| 26/3     |     unused, PULL:DOWN |            |              | PL19B        |                |           |           |








    +| 27/3     | clk40_i               | LOCATED    | LVCMOS25_IN  | PL22A        | PCLKT3_0       |           |           |








    +| 28/3     |     unused, PULL:DOWN |            |              | PL22B        | PCLKC3_0       |           |           |








    +| 31/3     |     unused, PULL:DOWN |            |              | PL23D        |                |           |           |








    +| 32/3     |     unused, PULL:DOWN |            |              | PL24A        |                |           |           |








    +| 33/3     |     unused, PULL:DOWN |            |              | PL24B        |                |           |           |








    +| 34/3     |     unused, PULL:DOWN |            |              | PL25A        |                |           |           |








    +| 35/3     |     unused, PULL:DOWN |            |              | PL25B        |                |           |           |








    +| 38/2     | addr_o[0]             | LOCATED    | LVCMOS25_OUT | PB4A         |                |           |           |








    +| 39/2     | addr_o[2]             | LOCATED    | LVCMOS25_OUT | PB4B         |                |           |           |








    +| 40/2     | addr_o[1]             | LOCATED    | LVCMOS25_OUT | PB6A         | CSSPIN         |           |           |








    +| 41/2     | addr_o[3]             | LOCATED    | LVCMOS25_OUT | PB6B         |                |           |           |








    +| 42/2     | addr_o[4]             | LOCATED    | LVCMOS25_OUT | PB9A         |                |           |           |








    +| 43/2     | addr_o[6]             | LOCATED    | LVCMOS25_OUT | PB9B         |                |           |           |








    +| 44/2     | addr_o[5]             | LOCATED    | LVCMOS25_OUT | PB12A        | MCLK/CCLK      |           |           |








    +| 45/2     | addr_o[7]             | LOCATED    | LVCMOS25_OUT | PB12B        | SO/SPISO       |           |           |








    +| 47/2     | addr_o[8]             | LOCATED    | LVCMOS25_OUT | PB13A        |                |           |           |








    +| 48/2     | addr_o[10]            | LOCATED    | LVCMOS25_OUT | PB13B        |                |           |           |








    +| 49/2     | addr_o[9]             | LOCATED    | LVCMOS25_OUT | PB16A        | PCLKT2_0       |           |           |








    +| 50/2     | addr_o[11]            | LOCATED    | LVCMOS25_OUT | PB16B        | PCLKC2_0       |           |           |








    +| 52/2     | addr_o[12]            | LOCATED    | LVCMOS25_OUT | PB18A        |                |           |           |








    +| 54/2     | addr_o[14]            | LOCATED    | LVCMOS25_OUT | PB18B        |                |           |           |








    +| 55/2     | addr_o[13]            | LOCATED    | LVCMOS25_OUT | PB23A        | PCLKT2_1       |           |           |








    +| 56/2     | addr_o[15]            | LOCATED    | LVCMOS25_OUT | PB23B        | PCLKC2_1       |           |           |








    +| 57/2     | cen_o                 | LOCATED    | LVCMOS25_OUT | PB26A        |                |           |           |








    +| 58/2     | oen_o                 | LOCATED    | LVCMOS25_OUT | PB26B        |                |           |           |








    +| 59/2     | wen_o                 | LOCATED    | LVCMOS25_OUT | PB29A        |                |           |           |








    +| 60/2     | cpuclk_o              | LOCATED    | LVCMOS25_OUT | PB29B        |                |           |           |








    +| 61/2     | state_o[3]            | LOCATED    | LVCMOS25_OUT | PB31A        |                |           |           |








    +| 62/2     | state_o[5]            | LOCATED    | LVCMOS25_OUT | PB31B        |                |           |           |








    +| 63/2     |     unused, PULL:DOWN |            |              | PB31D        |                |           |           |








    +| 65/2     | state_o[4]            | LOCATED    | LVCMOS25_OUT | PB35A        |                |           |           |








    +| 67/2     |     unused, PULL:DOWN |            |              | PB35B        |                |           |           |








    +| 68/2     |     unused, PULL:DOWN |            |              | PB37A        |                |           |           |








    +| 69/2     |     unused, PULL:DOWN |            |              | PB37B        |                |           |           |








    +| 70/2     |     unused, PULL:DOWN |            |              | PB38A        | SN             |           |           |








    +| 71/2     |     unused, PULL:DOWN |            |              | PB38B        | SI/SISPI       |           |           |








    +| 73/1     | hsync_o               | LOCATED    | LVCMOS25_OUT | PR24B        | DQ1            |           |           |








    +| 74/1     | blue_o                | LOCATED    | LVCMOS25_OUT | PR24A        | DQ1            |           |           |








    +| 75/1     | vsync_o               | LOCATED    | LVCMOS25_OUT | PR23B        | DQ1            |           |           |








    +| 76/1     | green_o               | LOCATED    | LVCMOS25_OUT | PR23A        | DQ1            |           |           |








    +| 77/1     |     unused, PULL:DOWN |            |              | PR21B        | DQ1            |           |           |








    +| 78/1     | red_o                 | LOCATED    | LVCMOS25_OUT | PR21A        | DQ1            |           |           |








    +| 81/1     |     unused, PULL:DOWN |            |              | PR18B        | DQ1            |           |           |








    +| 82/1     |     unused, PULL:DOWN |            |              | PR18A        | DQ1            |           |           |








    +| 83/1     |     unused, PULL:DOWN |            |              | PR17B        | DQ1            |           |           |








    +| 84/1     |     unused, PULL:DOWN |            |              | PR17A        | DQ1            |           |           |








    +| 85/1     |     unused, PULL:DOWN |            |              | PR16B        | DQS1N          |           |           |








    +| 86/1     |     unused, PULL:DOWN |            |              | PR16A        | DQS1           |           |           |








    +| 87/1     |     unused, PULL:DOWN |            |              | PR15B        |                |           |           |








    +| 89/1     |     unused, PULL:DOWN |            |              | PR15A        |                |           |           |








    +| 91/1     |     unused, PULL:DOWN |            |              | PR12B        | PCLKC1_0/DQ0   |           |           |








    +| 92/1     |     unused, PULL:DOWN |            |              | PR12A        | PCLKT1_0/DQ0   |           |           |








    +| 93/1     |     unused, PULL:DOWN |            |              | PR11B        | DQS0N          |           |           |








    +| 94/1     |     unused, PULL:DOWN |            |              | PR11A        | DQS0           |           |           |








    +| 95/1     |     unused, PULL:DOWN |            |              | PR9B         | DQ0            |           |           |








    +| 96/1     |     unused, PULL:DOWN |            |              | PR9A         | DQ0            |           |           |








    +| 97/1     | leds_o[0]             | LOCATED    | LVCMOS25_OUT | PR7B         | DQ0            |           |           |








    +| 98/1     | leds_o[1]             | LOCATED    | LVCMOS25_OUT | PR7A         | DQ0            |           |           |








    +| 99/1     | leds_o[2]             | LOCATED    | LVCMOS25_OUT | PR5B         | DQ0            |           |           |








    +| 100/1    | leds_o[3]             | LOCATED    | LVCMOS25_OUT | PR5A         | DQ0            |           |           |








    +| 103/1    |     unused, PULL:DOWN |            |              | PR4C         |                |           |           |








    +| 104/1    | leds_o[4]             | LOCATED    | LVCMOS25_OUT | PR3B         | R_GPLLC_IN/DQ0 |           |           |








    +| 105/1    | leds_o[5]             | LOCATED    | LVCMOS25_OUT | PR3A         | R_GPLLT_IN/DQ0 |           |           |








    +| 106/1    | leds_o[6]             | LOCATED    | LVCMOS25_OUT | PR2B         | R_GPLLC_FB/DQ0 |           |           |








    +| 107/1    | leds_o[7]             | LOCATED    | LVCMOS25_OUT | PR2A         | R_GPLLT_FB/DQ0 |           |           |








    +| 109/0    |     unused, PULL:DOWN |            |              | PT36D        | DONE           |           |           |








    +| 110/0    |     unused, PULL:DOWN |            |              | PT36C        | INITN          |           |           |








    +| 111/0    |     unused, PULL:DOWN |            |              | PT35B        |                |           |           |








    +| 112/0    |     unused, PULL:DOWN |            |              | PT35A        |                |           |           |








    +| 113/0    |     unused, PULL:DOWN |            |              | PT33B        |                |           |           |








    +| 114/0    |     unused, PULL:DOWN |            |              | PT33A        |                |           |           |








    +| 115/0    |     unused, PULL:DOWN |            |              | PT28B        |                |           |           |








    +| 117/0    |     unused, PULL:DOWN |            |              | PT28A        |                |           |           |








    +| 119/0    |     unused, PULL:DOWN |            |              | PT27D        | PROGRAMN       |           |           |








    +| 120/0    |     unused, PULL:DOWN |            |              | PT27C        | JTAGENB        |           |           |








    +| 121/0    |     unused, PULL:DOWN |            |              | PT25B        |                |           |           |








    +| 122/0    |     unused, PULL:DOWN |            |              | PT25A        |                |           |           |








    +| 125/0    | reset_o               | LOCATED    | LVCMOS25_OUT | PT22D        | SDA/PCLKC0_0   |           |           |








    +| 126/0    | state_o[2]            | LOCATED    | LVCMOS25_OUT | PT22C        | SCL/PCLKT0_0   |           |           |








    +| 127/0    | state_o[1]            | LOCATED    | LVCMOS25_OUT | PT18B        | PCLKC0_1       |           |           |








    +| 128/0    | state_o[0]            | LOCATED    | LVCMOS25_OUT | PT18A        | PCLKT0_1       |           |           |








    +| 130/0    | Reserved: sysCONFIG   |            |              | TMS          | TMS            |           |           |








    +| 131/0    | Reserved: sysCONFIG   |            |              | TCK/TEST_CLK | TCK            |           |           |








    +| 132/0    | data_io[7]            | LOCATED    | LVCMOS25_OUT | PT15B        |                |           |           |








    +| 133/0    | data_io[6]            | LOCATED    | LVCMOS25_OUT | PT15A        |                |           |           |








    +| 136/0    | Reserved: sysCONFIG   |            |              | TDI          | TDI            |           |           |








    +| 137/0    | Reserved: sysCONFIG   |            |              | TDO          | TDO            |           |           |








    +| 138/0    | data_io[5]            | LOCATED    | LVCMOS25_OUT | PT11B        |                |           |           |








    +| 139/0    | data_io[4]            | LOCATED    | LVCMOS25_OUT | PT11A        |                |           |           |








    +| 140/0    | data_io[3]            | LOCATED    | LVCMOS25_OUT | PT10B        |                |           |           |








    +| 141/0    | data_io[2]            | LOCATED    | LVCMOS25_OUT | PT10A        |                |           |           |








    +| 142/0    | data_io[1]            | LOCATED    | LVCMOS25_OUT | PT9B         |                |           |           |








    +| 143/0    | data_io[0]            | LOCATED    | LVCMOS25_OUT | PT9A         |                |           |           |








    +| PB4C/2   |     unused, PULL:DOWN |            |              | PB4C         |                |           |           |








    +| PB4D/2   |     unused, PULL:DOWN |            |              | PB4D         |                |           |           |








    +| PB6C/2   |     unused, PULL:DOWN |            |              | PB6C         |                |           |           |








    +| PB6D/2   |     unused, PULL:DOWN |            |              | PB6D         |                |           |           |








    +| PB7A/2   |     unused, PULL:DOWN |            |              | PB7A         |                |           |           |








    +| PB7B/2   |     unused, PULL:DOWN |            |              | PB7B         |                |           |           |








    +| PB7C/2   |     unused, PULL:DOWN |            |              | PB7C         |                |           |           |








    +| PB7D/2   |     unused, PULL:DOWN |            |              | PB7D         |                |           |           |








    +| PB9C/2   |     unused, PULL:DOWN |            |              | PB9C         |                |           |           |








    +| PB9D/2   |     unused, PULL:DOWN |            |              | PB9D         |                |           |           |








    +| PB10A/2  |     unused, PULL:DOWN |            |              | PB10A        |                |           |           |








    +| PB10B/2  |     unused, PULL:DOWN |            |              | PB10B        |                |           |           |








    +| PB10C/2  |     unused, PULL:DOWN |            |              | PB10C        |                |           |           |








    +| PB10D/2  |     unused, PULL:DOWN |            |              | PB10D        |                |           |           |








    +| PB12C/2  |     unused, PULL:DOWN |            |              | PB12C        |                |           |           |








    +| PB12D/2  |     unused, PULL:DOWN |            |              | PB12D        |                |           |           |








    +| PB13C/2  |     unused, PULL:DOWN |            |              | PB13C        |                |           |           |








    +| PB13D/2  |     unused, PULL:DOWN |            |              | PB13D        |                |           |           |








    +| PB15A/2  |     unused, PULL:DOWN |            |              | PB15A        |                |           |           |








    +| PB15B/2  |     unused, PULL:DOWN |            |              | PB15B        |                |           |           |








    +| PB15C/2  |     unused, PULL:DOWN |            |              | PB15C        |                |           |           |








    +| PB15D/2  |     unused, PULL:DOWN |            |              | PB15D        |                |           |           |








    +| PB16C/2  |     unused, PULL:DOWN |            |              | PB16C        |                |           |           |








    +| PB16D/2  |     unused, PULL:DOWN |            |              | PB16D        |                |           |           |








    +| PB18C/2  |     unused, PULL:DOWN |            |              | PB18C        |                |           |           |








    +| PB18D/2  |     unused, PULL:DOWN |            |              | PB18D        |                |           |           |








    +| PB21A/2  |     unused, PULL:DOWN |            |              | PB21A        |                |           |           |








    +| PB21B/2  |     unused, PULL:DOWN |            |              | PB21B        |                |           |           |








    +| PB21C/2  |     unused, PULL:DOWN |            |              | PB21C        |                |           |           |








    +| PB21D/2  |     unused, PULL:DOWN |            |              | PB21D        |                |           |           |








    +| PB23C/2  |     unused, PULL:DOWN |            |              | PB23C        |                |           |           |








    +| PB23D/2  |     unused, PULL:DOWN |            |              | PB23D        |                |           |           |








    +| PB26C/2  |     unused, PULL:DOWN |            |              | PB26C        |                |           |           |








    +| PB26D/2  |     unused, PULL:DOWN |            |              | PB26D        |                |           |           |








    +| PB28A/2  |     unused, PULL:DOWN |            |              | PB28A        |                |           |           |








    +| PB28B/2  |     unused, PULL:DOWN |            |              | PB28B        |                |           |           |








    +| PB28C/2  |     unused, PULL:DOWN |            |              | PB28C        |                |           |           |








    +| PB28D/2  |     unused, PULL:DOWN |            |              | PB28D        |                |           |           |








    +| PB29C/2  |     unused, PULL:DOWN |            |              | PB29C        |                |           |           |








    +| PB29D/2  |     unused, PULL:DOWN |            |              | PB29D        |                |           |           |








    +| PB31C/2  |     unused, PULL:DOWN |            |              | PB31C        |                |           |           |








    +| PB32A/2  |     unused, PULL:DOWN |            |              | PB32A        |                |           |           |








    +| PB32B/2  |     unused, PULL:DOWN |            |              | PB32B        |                |           |           |








    +| PB32C/2  |     unused, PULL:DOWN |            |              | PB32C        |                |           |           |








    +| PB32D/2  |     unused, PULL:DOWN |            |              | PB32D        |                |           |           |








    +| PB34A/2  |     unused, PULL:DOWN |            |              | PB34A        |                |           |           |








    +| PB34B/2  |     unused, PULL:DOWN |            |              | PB34B        |                |           |           |








    +| PB34C/2  |     unused, PULL:DOWN |            |              | PB34C        |                |           |           |








    +| PB34D/2  |     unused, PULL:DOWN |            |              | PB34D        |                |           |           |








    +| PB35C/2  |     unused, PULL:DOWN |            |              | PB35C        |                |           |           |








    +| PB35D/2  |     unused, PULL:DOWN |            |              | PB35D        |                |           |           |








    +| PB37C/2  |     unused, PULL:DOWN |            |              | PB37C        |                |           |           |








    +| PB37D/2  |     unused, PULL:DOWN |            |              | PB37D        |                |           |           |








    +| PB38C/2  |     unused, PULL:DOWN |            |              | PB38C        |                |           |           |








    +| PB38D/2  |     unused, PULL:DOWN |            |              | PB38D        |                |           |           |








    +| PL2A/5   |     unused, PULL:DOWN |            |              | PL2A         |                |           |           |








    +| PL2B/5   |     unused, PULL:DOWN |            |              | PL2B         |                |           |           |








    +| PL2C/5   |     unused, PULL:DOWN |            |              | PL2C         |                |           |           |








    +| PL2D/5   |     unused, PULL:DOWN |            |              | PL2D         |                |           |           |








    +| PL3C/5   |     unused, PULL:DOWN |            |              | PL3C         |                |           |           |








    +| PL3D/5   |     unused, PULL:DOWN |            |              | PL3D         |                |           |           |








    +| PL4C/5   |     unused, PULL:DOWN |            |              | PL4C         |                |           |           |








    +| PL4D/5   |     unused, PULL:DOWN |            |              | PL4D         |                |           |           |








    +| PL5A/5   |     unused, PULL:DOWN |            |              | PL5A         |                |           |           |








    +| PL5B/5   |     unused, PULL:DOWN |            |              | PL5B         |                |           |           |








    +| PL5C/5   |     unused, PULL:DOWN |            |              | PL5C         |                |           |           |








    +| PL5D/5   |     unused, PULL:DOWN |            |              | PL5D         |                |           |           |








    +| PL6C/5   |     unused, PULL:DOWN |            |              | PL6C         |                |           |           |








    +| PL6D/5   |     unused, PULL:DOWN |            |              | PL6D         |                |           |           |








    +| PL7A/5   |     unused, PULL:DOWN |            |              | PL7A         |                |           |           |








    +| PL7B/5   |     unused, PULL:DOWN |            |              | PL7B         |                |           |           |








    +| PL7C/5   |     unused, PULL:DOWN |            |              | PL7C         |                |           |           |








    +| PL7D/5   |     unused, PULL:DOWN |            |              | PL7D         |                |           |           |








    +| PL8C/5   |     unused, PULL:DOWN |            |              | PL8C         |                |           |           |








    +| PL8D/5   |     unused, PULL:DOWN |            |              | PL8D         |                |           |           |








    +| PL9C/5   |     unused, PULL:DOWN |            |              | PL9C         |                |           |           |








    +| PL9D/5   |     unused, PULL:DOWN |            |              | PL9D         |                |           |           |








    +| PL10C/4  |     unused, PULL:DOWN |            |              | PL10C        |                |           |           |








    +| PL10D/4  |     unused, PULL:DOWN |            |              | PL10D        |                |           |           |








    +| PL11C/4  |     unused, PULL:DOWN |            |              | PL11C        |                |           |           |








    +| PL11D/4  |     unused, PULL:DOWN |            |              | PL11D        |                |           |           |








    +| PL12C/4  |     unused, PULL:DOWN |            |              | PL12C        |                |           |           |








    +| PL12D/4  |     unused, PULL:DOWN |            |              | PL12D        |                |           |           |








    +| PL15C/4  |     unused, PULL:DOWN |            |              | PL15C        |                |           |           |








    +| PL15D/4  |     unused, PULL:DOWN |            |              | PL15D        |                |           |           |








    +| PL16A/4  |     unused, PULL:DOWN |            |              | PL16A        |                |           |           |








    +| PL16B/4  |     unused, PULL:DOWN |            |              | PL16B        |                |           |           |








    +| PL16C/4  |     unused, PULL:DOWN |            |              | PL16C        |                |           |           |








    +| PL16D/4  |     unused, PULL:DOWN |            |              | PL16D        |                |           |           |








    +| PL17C/4  |     unused, PULL:DOWN |            |              | PL17C        |                |           |           |








    +| PL17D/4  |     unused, PULL:DOWN |            |              | PL17D        |                |           |           |








    +| PL18A/3  |     unused, PULL:DOWN |            |              | PL18A        |                |           |           |








    +| PL18B/3  |     unused, PULL:DOWN |            |              | PL18B        |                |           |           |








    +| PL18C/3  |     unused, PULL:DOWN |            |              | PL18C        |                |           |           |








    +| PL18D/3  |     unused, PULL:DOWN |            |              | PL18D        |                |           |           |








    +| PL19C/3  |     unused, PULL:DOWN |            |              | PL19C        |                |           |           |








    +| PL19D/3  |     unused, PULL:DOWN |            |              | PL19D        |                |           |           |








    +| PL21A/3  |     unused, PULL:DOWN |            |              | PL21A        |                |           |           |








    +| PL21B/3  |     unused, PULL:DOWN |            |              | PL21B        |                |           |           |








    +| PL21C/3  |     unused, PULL:DOWN |            |              | PL21C        |                |           |           |








    +| PL21D/3  |     unused, PULL:DOWN |            |              | PL21D        |                |           |           |








    +| PL22C/3  |     unused, PULL:DOWN |            |              | PL22C        |                |           |           |








    +| PL22D/3  |     unused, PULL:DOWN |            |              | PL22D        |                |           |           |








    +| PL23A/3  |     unused, PULL:DOWN |            |              | PL23A        |                |           |           |








    +| PL23B/3  |     unused, PULL:DOWN |            |              | PL23B        |                |           |           |








    +| PL23C/3  |     unused, PULL:DOWN |            |              | PL23C        |                |           |           |








    +| PL24C/3  |     unused, PULL:DOWN |            |              | PL24C        |                |           |           |








    +| PL24D/3  |     unused, PULL:DOWN |            |              | PL24D        |                |           |           |








    +| PL25C/3  |     unused, PULL:DOWN |            |              | PL25C        |                |           |           |








    +| PL25D/3  |     unused, PULL:DOWN |            |              | PL25D        |                |           |           |








    +| PR2C/1   |     unused, PULL:DOWN |            |              | PR2C         |                |           |           |








    +| PR2D/1   |     unused, PULL:DOWN |            |              | PR2D         |                |           |           |








    +| PR3C/1   |     unused, PULL:DOWN |            |              | PR3C         |                |           |           |








    +| PR3D/1   |     unused, PULL:DOWN |            |              | PR3D         |                |           |           |








    +| PR4A/1   |     unused, PULL:DOWN |            |              | PR4A         |                |           |           |








    +| PR4B/1   |     unused, PULL:DOWN |            |              | PR4B         |                |           |           |








    +| PR4D/1   |     unused, PULL:DOWN |            |              | PR4D         |                |           |           |








    +| PR5C/1   |     unused, PULL:DOWN |            |              | PR5C         |                |           |           |








    +| PR5D/1   |     unused, PULL:DOWN |            |              | PR5D         |                |           |           |








    +| PR6A/1   |     unused, PULL:DOWN |            |              | PR6A         |                |           |           |








    +| PR6B/1   |     unused, PULL:DOWN |            |              | PR6B         |                |           |           |








    +| PR6C/1   |     unused, PULL:DOWN |            |              | PR6C         |                |           |           |








    +| PR6D/1   |     unused, PULL:DOWN |            |              | PR6D         |                |           |           |








    +| PR7C/1   |     unused, PULL:DOWN |            |              | PR7C         |                |           |           |








    +| PR7D/1   |     unused, PULL:DOWN |            |              | PR7D         |                |           |           |








    +| PR8A/1   |     unused, PULL:DOWN |            |              | PR8A         |                |           |           |








    +| PR8B/1   |     unused, PULL:DOWN |            |              | PR8B         |                |           |           |








    +| PR8C/1   |     unused, PULL:DOWN |            |              | PR8C         |                |           |           |








    +| PR8D/1   |     unused, PULL:DOWN |            |              | PR8D         |                |           |           |








    +| PR9C/1   |     unused, PULL:DOWN |            |              | PR9C         |                |           |           |








    +| PR9D/1   |     unused, PULL:DOWN |            |              | PR9D         |                |           |           |








    +| PR10A/1  |     unused, PULL:DOWN |            |              | PR10A        |                |           |           |








    +| PR10B/1  |     unused, PULL:DOWN |            |              | PR10B        |                |           |           |








    +| PR10C/1  |     unused, PULL:DOWN |            |              | PR10C        |                |           |           |








    +| PR10D/1  |     unused, PULL:DOWN |            |              | PR10D        |                |           |           |








    +| PR11C/1  |     unused, PULL:DOWN |            |              | PR11C        |                |           |           |








    +| PR11D/1  |     unused, PULL:DOWN |            |              | PR11D        |                |           |           |








    +| PR12C/1  |     unused, PULL:DOWN |            |              | PR12C        |                |           |           |








    +| PR12D/1  |     unused, PULL:DOWN |            |              | PR12D        |                |           |           |








    +| PR15C/1  |     unused, PULL:DOWN |            |              | PR15C        |                |           |           |








    +| PR15D/1  |     unused, PULL:DOWN |            |              | PR15D        |                |           |           |








    +| PR16C/1  |     unused, PULL:DOWN |            |              | PR16C        |                |           |           |








    +| PR16D/1  |     unused, PULL:DOWN |            |              | PR16D        |                |           |           |








    +| PR17C/1  |     unused, PULL:DOWN |            |              | PR17C        |                |           |           |








    +| PR17D/1  |     unused, PULL:DOWN |            |              | PR17D        |                |           |           |








    +| PR18C/1  |     unused, PULL:DOWN |            |              | PR18C        |                |           |           |








    +| PR18D/1  |     unused, PULL:DOWN |            |              | PR18D        |                |           |           |








    +| PR19A/1  |     unused, PULL:DOWN |            |              | PR19A        |                |           |           |








    +| PR19B/1  |     unused, PULL:DOWN |            |              | PR19B        |                |           |           |








    +| PR19C/1  |     unused, PULL:DOWN |            |              | PR19C        | DQ1            |           |           |








    +| PR19D/1  |     unused, PULL:DOWN |            |              | PR19D        | DQ1            |           |           |








    +| PR21C/1  |     unused, PULL:DOWN |            |              | PR21C        |                |           |           |








    +| PR21D/1  |     unused, PULL:DOWN |            |              | PR21D        |                |           |           |








    +| PR22A/1  |     unused, PULL:DOWN |            |              | PR22A        |                |           |           |








    +| PR22B/1  |     unused, PULL:DOWN |            |              | PR22B        |                |           |           |








    +| PR22C/1  |     unused, PULL:DOWN |            |              | PR22C        |                |           |           |








    +| PR22D/1  |     unused, PULL:DOWN |            |              | PR22D        |                |           |           |








    +| PR23C/1  |     unused, PULL:DOWN |            |              | PR23C        |                |           |           |








    +| PR23D/1  |     unused, PULL:DOWN |            |              | PR23D        |                |           |           |








    +| PR24C/1  |     unused, PULL:DOWN |            |              | PR24C        |                |           |           |








    +| PR24D/1  |     unused, PULL:DOWN |            |              | PR24D        |                |           |           |








    +| PR25A/1  |     unused, PULL:DOWN |            |              | PR25A        |                |           |           |








    +| PR25B/1  |     unused, PULL:DOWN |            |              | PR25B        |                |           |           |








    +| PR25C/1  |     unused, PULL:DOWN |            |              | PR25C        |                |           |           |








    +| PR25D/1  |     unused, PULL:DOWN |            |              | PR25D        |                |           |           |








    +| PT9C/0   |     unused, PULL:DOWN |            |              | PT9C         |                |           |           |








    +| PT9D/0   |     unused, PULL:DOWN |            |              | PT9D         |                |           |           |








    +| PT10C/0  |     unused, PULL:DOWN |            |              | PT10C        |                |           |           |








    +| PT10D/0  |     unused, PULL:DOWN |            |              | PT10D        |                |           |           |








    +| PT11C/0  |     unused, PULL:DOWN |            |              | PT11C        |                |           |           |








    +| PT11D/0  |     unused, PULL:DOWN |            |              | PT11D        |                |           |           |








    +| PT12A/0  |     unused, PULL:DOWN |            |              | PT12A        |                |           |           |








    +| PT12B/0  |     unused, PULL:DOWN |            |              | PT12B        |                |           |           |








    +| PT12C/0  |     unused, PULL:DOWN |            |              | PT12C        |                |           |           |








    +| PT12D/0  |     unused, PULL:DOWN |            |              | PT12D        |                |           |           |








    +| PT13A/0  |     unused, PULL:DOWN |            |              | PT13A        |                |           |           |








    +| PT13B/0  |     unused, PULL:DOWN |            |              | PT13B        |                |           |           |








    +| PT13C/0  |     unused, PULL:DOWN |            |              | PT13C        |                |           |           |








    +| PT13D/0  |     unused, PULL:DOWN |            |              | PT13D        |                |           |           |








    +| PT14A/0  |     unused, PULL:DOWN |            |              | PT14A        |                |           |           |








    +| PT14B/0  |     unused, PULL:DOWN |            |              | PT14B        |                |           |           |








    +| PT15C/0  |     unused, PULL:DOWN |            |              | PT15C        |                |           |           |








    +| PT15D/0  |     unused, PULL:DOWN |            |              | PT15D        |                |           |           |








    +| PT16A/0  |     unused, PULL:DOWN |            |              | PT16A        |                |           |           |








    +| PT16B/0  |     unused, PULL:DOWN |            |              | PT16B        |                |           |           |








    +| PT16C/0  |     unused, PULL:DOWN |            |              | PT16C        |                |           |           |








    +| PT16D/0  |     unused, PULL:DOWN |            |              | PT16D        |                |           |           |








    +| PT17A/0  |     unused, PULL:DOWN |            |              | PT17A        |                |           |           |








    +| PT17B/0  |     unused, PULL:DOWN |            |              | PT17B        |                |           |           |








    +| PT18C/0  |     unused, PULL:DOWN |            |              | PT18C        |                |           |           |








    +| PT18D/0  |     unused, PULL:DOWN |            |              | PT18D        |                |           |           |








    +| PT21A/0  |     unused, PULL:DOWN |            |              | PT21A        |                |           |           |








    +| PT21B/0  |     unused, PULL:DOWN |            |              | PT21B        |                |           |           |








    +| PT21C/0  |     unused, PULL:DOWN |            |              | PT21C        |                |           |           |








    +| PT21D/0  |     unused, PULL:DOWN |            |              | PT21D        |                |           |           |








    +| PT22A/0  |     unused, PULL:DOWN |            |              | PT22A        |                |           |           |








    +| PT22B/0  |     unused, PULL:DOWN |            |              | PT22B        |                |           |           |








    +| PT25C/0  |     unused, PULL:DOWN |            |              | PT25C        |                |           |           |








    +| PT25D/0  |     unused, PULL:DOWN |            |              | PT25D        |                |           |           |








    +| PT26A/0  |     unused, PULL:DOWN |            |              | PT26A        |                |           |           |








    +| PT26B/0  |     unused, PULL:DOWN |            |              | PT26B        |                |           |           |








    +| PT26C/0  |     unused, PULL:DOWN |            |              | PT26C        |                |           |           |








    +| PT26D/0  |     unused, PULL:DOWN |            |              | PT26D        |                |           |           |








    +| PT27A/0  |     unused, PULL:DOWN |            |              | PT27A        |                |           |           |








    +| PT27B/0  |     unused, PULL:DOWN |            |              | PT27B        |                |           |           |








    +| PT28C/0  |     unused, PULL:DOWN |            |              | PT28C        |                |           |           |








    +| PT28D/0  |     unused, PULL:DOWN |            |              | PT28D        |                |           |           |








    +| PT32A/0  |     unused, PULL:DOWN |            |              | PT32A        |                |           |           |








    +| PT32B/0  |     unused, PULL:DOWN |            |              | PT32B        |                |           |           |








    +| PT32C/0  |     unused, PULL:DOWN |            |              | PT32C        |                |           |           |








    +| PT32D/0  |     unused, PULL:DOWN |            |              | PT32D        |                |           |           |








    +| PT33C/0  |     unused, PULL:DOWN |            |              | PT33C        |                |           |           |








    +| PT33D/0  |     unused, PULL:DOWN |            |              | PT33D        |                |           |           |








    +| PT34A/0  |     unused, PULL:DOWN |            |              | PT34A        |                |           |           |








    +| PT34B/0  |     unused, PULL:DOWN |            |              | PT34B        |                |           |           |








    +| PT34C/0  |     unused, PULL:DOWN |            |              | PT34C        |                |           |           |








    +| PT34D/0  |     unused, PULL:DOWN |            |              | PT34D        |                |           |           |








    +| PT35C/0  |     unused, PULL:DOWN |            |              | PT35C        |                |           |           |








    +| PT35D/0  |     unused, PULL:DOWN |            |              | PT35D        |                |           |           |








    +| PT36A/0  |     unused, PULL:DOWN |            |              | PT36A        |                |           |           |








    +| PT36B/0  |     unused, PULL:DOWN |            |              | PT36B        |                |           |           |








    ++----------+-----------------------+------------+--------------+--------------+----------------+-----------+-----------+








    +








    +sysCONFIG Pins:








    ++----------+--------------------+--------------------+----------+-------------+-------------------+








    +| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode  |








    ++----------+--------------------+--------------------+----------+-------------+-------------------+








    +| PT17D    | TMS                | JTAG_PORT=ENABLE   | 130/0    |             | PULLUP            |








    +| PT17C    | TCK/TEST_CLK       | JTAG_PORT=ENABLE   | 131/0    |             | NO pull up/down   |








    +| PT14D    | TDI/MD7            | JTAG_PORT=ENABLE   | 136/0    |             | PULLUP            |








    +| PT14C    | TDO                | JTAG_PORT=ENABLE   | 137/0    |             | PULLUP            |








    ++----------+--------------------+--------------------+----------+-------------+-------------------+








    +








    +








    +Locate Preferences for each Pin: 








    +








    +LOCATE  COMP  "addr_o[0]"  SITE  "38";








    +LOCATE  COMP  "addr_o[10]"  SITE  "48";








    +LOCATE  COMP  "addr_o[11]"  SITE  "50";








    +LOCATE  COMP  "addr_o[12]"  SITE  "52";








    +LOCATE  COMP  "addr_o[13]"  SITE  "55";








    +LOCATE  COMP  "addr_o[14]"  SITE  "54";








    +LOCATE  COMP  "addr_o[15]"  SITE  "56";








    +LOCATE  COMP  "addr_o[1]"  SITE  "40";








    +LOCATE  COMP  "addr_o[2]"  SITE  "39";








    +LOCATE  COMP  "addr_o[3]"  SITE  "41";








    +LOCATE  COMP  "addr_o[4]"  SITE  "42";








    +LOCATE  COMP  "addr_o[5]"  SITE  "44";








    +LOCATE  COMP  "addr_o[6]"  SITE  "43";








    +LOCATE  COMP  "addr_o[7]"  SITE  "45";








    +LOCATE  COMP  "addr_o[8]"  SITE  "47";








    +LOCATE  COMP  "addr_o[9]"  SITE  "49";








    +LOCATE  COMP  "blue_o"  SITE  "74";








    +LOCATE  COMP  "cen_o"  SITE  "57";








    +LOCATE  COMP  "clk40_i"  SITE  "27";








    +LOCATE  COMP  "cpuclk_o"  SITE  "60";








    +LOCATE  COMP  "data_io[0]"  SITE  "143";








    +LOCATE  COMP  "data_io[1]"  SITE  "142";








    +LOCATE  COMP  "data_io[2]"  SITE  "141";








    +LOCATE  COMP  "data_io[3]"  SITE  "140";








    +LOCATE  COMP  "data_io[4]"  SITE  "139";








    +LOCATE  COMP  "data_io[5]"  SITE  "138";








    +LOCATE  COMP  "data_io[6]"  SITE  "133";








    +LOCATE  COMP  "data_io[7]"  SITE  "132";








    +LOCATE  COMP  "green_o"  SITE  "76";








    +LOCATE  COMP  "hsync_o"  SITE  "73";








    +LOCATE  COMP  "leds_o[0]"  SITE  "97";








    +LOCATE  COMP  "leds_o[1]"  SITE  "98";








    +LOCATE  COMP  "leds_o[2]"  SITE  "99";








    +LOCATE  COMP  "leds_o[3]"  SITE  "100";








    +LOCATE  COMP  "leds_o[4]"  SITE  "104";








    +LOCATE  COMP  "leds_o[5]"  SITE  "105";








    +LOCATE  COMP  "leds_o[6]"  SITE  "106";








    +LOCATE  COMP  "leds_o[7]"  SITE  "107";








    +LOCATE  COMP  "oen_o"  SITE  "58";








    +LOCATE  COMP  "red_o"  SITE  "78";








    +LOCATE  COMP  "reset_o"  SITE  "125";








    +LOCATE  COMP  "state_o[0]"  SITE  "128";








    +LOCATE  COMP  "state_o[1]"  SITE  "127";








    +LOCATE  COMP  "state_o[2]"  SITE  "126";








    +LOCATE  COMP  "state_o[3]"  SITE  "61";








    +LOCATE  COMP  "state_o[4]"  SITE  "65";








    +LOCATE  COMP  "state_o[5]"  SITE  "62";








    +LOCATE  COMP  "vsync_o"  SITE  "75";








    +LOCATE  COMP  "wen_o"  SITE  "59";








    +








    +








    +








    +








    +








    +PAR: Place And Route Diamond (64-bit) 2.2.0.101.








    +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.








    +Copyright (c) 1995 AT&T Corp.   All rights reserved.








    +Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.








    +Copyright (c) 2001 Agere Systems   All rights reserved.








    +Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.








    +Wed Dec 25 17:50:45 2013








    +








    +








    +








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+ +
/syn/lattice/logs/bios2k_generate.log
0,0 → 1,47
Starting process: Module
 
Starting process:
 
SCUBA, Version Diamond_2.2_Production (99)
Sun Dec 22 20:20:07 2013
 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2013 Lattice Semiconductor Corporation, All rights reserved.
 
BEGIN SCUBA Module Synthesis
 
Issued command : /usr/local/diamond/2.2_x64/ispfpga/bin/lin64/scuba -w -n bios2k -lang verilog -synth synplify -bus_exp 7 -bb -arch xo2c00 -type ramdp -device LCMXO2-7000HE -aaddr_width 11 -widtha 8 -baddr_width 11 -widthb 8 -anum_words 2048 -bnum_words 2048 -cascade -1 -memfile /home/pacito/02_Elektronik/020_V6809/6809/test1.mem -memformat orca -writemodeA NORMAL -writemodeB NORMAL -e
Circuit name : bios2k
Module type : RAM_DP_TRUE
Module Version : 7.2
Ports :
Inputs : DataInA[7:0], DataInB[7:0], AddressA[10:0], AddressB[10:0], ClockA, ClockB, ClockEnA, ClockEnB, WrA, WrB, ResetA, ResetB
Outputs : QA[7:0], QB[7:0]
I/O buffer : not inserted
Memory file : /home/pacito/02_Elektronik/020_V6809/6809/test1.mem
EDIF output : suppressed
Verilog output : bios2k.v
Verilog template : bios2k_tmpl.v
Verilog testbench: tb_bios2k_tmpl.v
Verilog purpose : for synthesis and simulation
Bus notation : big endian
Report output : bios2k.srp
Estimated Resource Usage:
EBR : 2
 
END SCUBA Module Synthesis
 
File: bios2k.lpc created.
 
 
End process: completed successfully.
 
 
Total Warnings: 0
 
Total Errors: 0
 
 
/syn/lattice/logs/P6809_P6809_bgn.html
0,0 → 1,228
<HTML>
<HEAD><TITLE>Bitgen Report</TITLE>
<STYLE TYPE="text/css">
<!--
+} +--> + + +
BITGEN: Bitstream Generator Diamond (64-bit) 2.2.0.101








    +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.








    +Copyright (c) 1995 AT&T Corp.   All rights reserved.








    +Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.








    +Copyright (c) 2001 Agere Systems   All rights reserved.








    +Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.








    +








    +Command: bitgen -g RamCfg:Reset -path /home/pacito/02_Elektronik/020_V6809/6809/lattice -w -jedec P6809_P6809.ncd P6809_P6809.prf 








    +








    +Loading design for application Bitgen from file P6809_P6809.ncd.








    +Design name: CC3_top








    +NCD version: 3.2








    +Vendor:      LATTICE








    +Device:      LCMXO2-7000HE








    +Package:     TQFP144








    +Performance: 4








    +Loading device for application Bitgen from file 'xo2c7000.nph' in environment: /usr/local/diamond/2.2_x64/ispfpga.








    +Package Status:                     Final          Version 1.36








    +Performance Hardware Data Status:   Final)         Version 23.4








    +








    +Running DRC.








    +INFO: Design contains EBR with ASYNC Reset Mode that has a limitation: The use of the EBR block asynchronous reset requires that certain timing be met between the clock and the reset within the memory block. See the device specific datasheet for additional details.








    +INFO: Design contains pre-loadable EBR during configuration that has a requirement: Since the GSR is disabled for the EBR, make sure write enable and chip enable are inactive during wake-up, so that the pre-loaded initialization values will not be corrupted during wake-up state.








    +DRC detected 0 errors and 0 warnings.








    +Reading Preference File from P6809_P6809.prf...








    +








    +








    +Preference Summary:








    +








    ++---------------------------------+---------------------------------+








    +|  Preference                     |  Current Setting                |








    ++---------------------------------+---------------------------------+








    +|                         RamCfg  |                        Reset**  |








    ++---------------------------------+---------------------------------+








    +|                     MCCLK_FREQ  |                         2.08**  |








    ++---------------------------------+---------------------------------+








    +|                  CONFIG_SECURE  |                          OFF**  |








    ++---------------------------------+---------------------------------+








    +|                      JTAG_PORT  |                       ENABLE**  |








    ++---------------------------------+---------------------------------+








    +|                       SDM_PORT  |                      DISABLE**  |








    ++---------------------------------+---------------------------------+








    +|                 SLAVE_SPI_PORT  |                      DISABLE**  |








    ++---------------------------------+---------------------------------+








    +|                MASTER_SPI_PORT  |                      DISABLE**  |








    ++---------------------------------+---------------------------------+








    +|                       I2C_PORT  |                      DISABLE**  |








    ++---------------------------------+---------------------------------+








    +|        MUX_CONFIGURATION_PORTS  |                      DISABLE**  |








    ++---------------------------------+---------------------------------+








    +|                  CONFIGURATION  |                          CFG**  |








    ++---------------------------------+---------------------------------+








    +|                COMPRESS_CONFIG  |                           ON**  |








    ++---------------------------------+---------------------------------+








    +|                        MY_ASSP  |                          OFF**  |








    ++---------------------------------+---------------------------------+








    +|               ONE_TIME_PROGRAM  |                          OFF**  |








    ++---------------------------------+---------------------------------+








    +|                 ENABLE_TRANSFR  |                      DISABLE**  |








    ++---------------------------------+---------------------------------+








    +|                  SHAREDEBRINIT  |                      DISABLE**  |








    ++---------------------------------+---------------------------------+








    + *  Default setting.








    + ** The specified setting matches the default setting.








    +








    +








    +Creating bit map...








    + 








    +Bitstream Status:   Final           Version 1.83








    + 








    +Saving bit stream in "P6809_P6809.jed".








    + 








    +===========








    +UFM Summary








    +===========








    +UFM Size:        2046 Pages (128*2046 Bits)








    +UFM Utilization: General Purpose Flash Memory








    + 








    +Available General Purpose Flash Memory: 2046 Pages (Page 0 to Page 2045)








    +Initialized UFM Pages:                     0 Page








    + 








    +








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+ +
/syn/lattice/logs/P6809_P6809_synplify.html
0,0 → 1,712
<HTML>
<HEAD><TITLE>Synthesis Report</TITLE>
<STYLE TYPE="text/css">
<!--
+} +--> + + +
Synthesis Report








    +#Build: Synplify Pro G-2012.09L-SP1 , Build 029R, Mar 11 2013








    +#install: /usr/local/diamond/2.2_x64/synpbase








    +#OS: Linux 








    +#Hostname: node01.pacito.sys








    +








    +#Implementation: P6809








    +








    +$ Start of Compile








    +#Wed Dec 25 17:50:10 2013








    +








    +Synopsys Verilog Compiler, version comp201209rcp1, Build 271R, built Mar 11 2013








    +@N|Running in 64-bit mode








    +Copyright (C) 1994-2012 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.








    +








    +@I::"/usr/local/diamond/2.2_x64/synpbase/lib/lucent/machxo2.v"








    +@I::"/usr/local/diamond/2.2_x64/synpbase/lib/lucent/pmi_def.v"








    +@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/umr_capim.v"








    +@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/scemi_objects.v"








    +@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/scemi_pipes.svh"








    +@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/hypermods.v"








    +@I::"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v"








    +@I::"/home/pacito/02_Elektronik/020_V6809/6809/alu16.v"








    +@I:"/home/pacito/02_Elektronik/020_V6809/6809/alu16.v":"/home/pacito/02_Elektronik/020_V6809/6809/defs.v"








    +@I::"/home/pacito/02_Elektronik/020_V6809/6809/decoders.v"








    +@I::"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v"








    +@I::"/home/pacito/02_Elektronik/020_V6809/6809/regblock.v"








    +@I::"/home/pacito/02_Elektronik/020_V6809/6809/CC3_top.v"








    +@I::"/home/pacito/02_Elektronik/020_V6809/6809/lattice/bios2k.v"








    +Verilog syntax check successful!








    +File /home/pacito/02_Elektronik/020_V6809/6809/decoders.v changed - recompiling








    +File /home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v changed - recompiling








    +File /home/pacito/02_Elektronik/020_V6809/6809/CC3_top.v changed - recompiling








    +Selecting top level module CC3_top








    +@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/alu16.v":13:7:13:11|Synthesizing module alu16








    +








    +@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/alu16.v":493:0:493:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored








    +@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/regblock.v":7:7:7:14|Synthesizing module regblock








    +








    +@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/regblock.v":225:0:225:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored








    +@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/regblock.v":50:10:50:13|No assignment to regh[7]








    +@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/regblock.v":50:21:50:24|No assignment to regl[6]








    +@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/decoders.v":9:7:9:17|Synthesizing module decode_regs








    +








    +@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/decoders.v":108:7:108:15|Synthesizing module decode_op








    +








    +@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/decoders.v":236:7:236:15|Synthesizing module decode_ea








    +








    +@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/decoders.v":262:7:262:16|Synthesizing module decode_alu








    +








    +@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/decoders.v":334:7:334:20|Synthesizing module test_condition








    +








    +@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":25:7:25:16|Synthesizing module MC6809_cpu








    +








    +@N: CG793 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":405:6:405:13|Ignoring system task $display








    +@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":961:0:961:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored








    +@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal next_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.








    +@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal next_push_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.








    +@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal next_mem_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.








    +@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_write_post_incdec -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.








    +@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_write_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.








    +@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_set_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.








    +@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_pull_reg_write -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.








    +@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_pp_regs[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.








    +@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_pp_active_reg[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.








    +@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_postbyte0[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.








    +@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_p3_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.








    +@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_p2_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.








    +@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_opcode[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.








    +@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_ofslo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.








    +@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_ofshi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.








    +@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_new_pc[15:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.








    +@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_memlo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.








    +@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_memhi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.








    +@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_mem_dest[1:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.








    +@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_ind_ea[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.








    +@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_inc_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.








    +@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_inc_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.








    +@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_ealo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.








    +@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_eahi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.








    +@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_dec_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.








    +@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_cpu_we -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.








    +@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_cpu_oe -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.








    +@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_cpu_data_o[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.








    +@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_cpu_addr[15:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.








    +@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_clear_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.








    +@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Register bit k_mem_dest[0] is always 1, optimizing ...








    +@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Register bit k_mem_dest[1] is always 0, optimizing ...








    +@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Register bit next_mem_state[1] is always 0, optimizing ...








    +@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Register bit next_mem_state[2] is always 0, optimizing ...








    +@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Pruning register bits 2 to 1 of next_mem_state[5:0] 








    +








    +@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1120:7:1120:9|Synthesizing module VHI








    +








    +@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1291:7:1291:11|Synthesizing module DP8KC








    +








    +@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1124:7:1124:9|Synthesizing module VLO








    +








    +@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/lattice/bios2k.v":8:7:8:12|Synthesizing module bios2k








    +








    +@W: CL168 :"/home/pacito/02_Elektronik/020_V6809/6809/lattice/bios2k.v":28:8:28:21|Pruning instance scuba_vhi_inst -- not in use ...








    +








    +@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/CC3_top.v":7:7:7:13|Synthesizing module CC3_top








    +








    +@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/CC3_top.v":28:14:28:21|No assignment to clk_div2








    +@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/CC3_top.v":33:25:33:35|No assignment to wire cpu1_addr_o








    +








    +@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/CC3_top.v":34:40:34:51|No assignment to wire cpu1_data_in








    +








    +@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/CC3_top.v":34:54:34:66|No assignment to wire cpu1_data_out








    +








    +@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/CC3_top.v":35:23:35:29|No assignment to wire cpu1_we








    +








    +@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/CC3_top.v":35:32:35:38|No assignment to wire cpu1_oe








    +








    +@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/CC3_top.v":34:54:34:66|*Input cpu1_data_out[7:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.








    +@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/CC3_top.v":33:25:33:35|*Input cpu1_addr_o[10:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.








    +@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Pruning register bits 5 to 2 of next_push_state[5:0] 








    +








    +@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/decoders.v":338:18:338:20|Input port bits 7 to 4 of CCR[7:0] are unused








    +








    +@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/decoders.v":264:18:264:26|Input port bits 5 to 4 of postbyte0[7:0] are unused








    +








    +@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/decoders.v":237:18:237:27|Input port bits 6 to 5 of eapostbyte[7:0] are unused








    +








    +@END








    +Process took 0h:00m:01s realtime, 0h:00m:01s cputime








    +# Wed Dec 25 17:50:12 2013








    +








    +###########################################################]








    +Premap Report








    +








    +Synopsys Lattice Technology Pre-mapping, Version maplat, Build 618R, Built Mar 14 2013 09:13:46








    +Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.








    +Product Version G-2012.09L-SP1 








    +








    +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)








    +








    +@L: /home/pacito/02_Elektronik/020_V6809/6809/lattice/P6809/P6809_P6809_scck.rpt 








    +Printing clock  summary report in "/home/pacito/02_Elektronik/020_V6809/6809/lattice/P6809/P6809_P6809_scck.rpt" file 








    +@N: MF248 |Running in 64-bit mode.








    +@N: MF666 |Clock conversion enabled 








    +








    +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 94MB)








    +








    +








    +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 94MB)








    +








    +








    +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 109MB)








    +








    +








    +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 111MB)








    +








    +








    +








    +Clock Summary








    +**************








    +








    +Start                             Requested     Requested     Clock                              Clock              








    +Clock                             Frequency     Period        Type                               Group              








    +--------------------------------------------------------------------------------------------------------------------








    +CC3_top|clk40_i                   1.0 MHz       1000.000      inferred                           Inferred_clkgroup_0








    +CC3_top|cpu_clk_derived_clock     1.0 MHz       1000.000      derived (from CC3_top|clk40_i)     Inferred_clkgroup_0








    +====================================================================================================================








    +








    +@W: MT529 :"/home/pacito/02_Elektronik/020_V6809/6809/lattice/bios2k.v":74:10:74:21|Found inferred clock CC3_top|clk40_i which controls 1 sequential elements including bios.bios2k_0_0_1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 








    +








    +syn_allowed_resources : blockrams=26  set on top level netlist CC3_top








    +Finished Pre Mapping Phase.Pre-mapping successful!








    +








    +At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 136MB)








    +








    +Process took 0h:00m:01s realtime, 0h:00m:01s cputime








    +# Wed Dec 25 17:50:13 2013








    +








    +###########################################################]








    +Map & Optimize Report








    +








    +Synopsys Lattice Technology Mapper, Version maplat, Build 618R, Built Mar 14 2013 09:13:46








    +Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.








    +Product Version G-2012.09L-SP1 








    +








    +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)








    +








    +@N: MF248 |Running in 64-bit mode.








    +@N: MF666 |Clock conversion enabled 








    +








    +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)








    +








    +








    +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)








    +








    +








    +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 106MB)








    +








    +








    +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 108MB)








    +








    +








    +








    +Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)








    +








    +








    +Available hyper_sources - for debug and ip models








    +	None Found








    +








    +








    +Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)








    +








    +@N:"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Found counter in view:work.MC6809_cpu(verilog) inst k_cpu_addr[15:0]








    +@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Removing sequential instance k_reg_firq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs 








    +@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Removing sequential instance k_reg_irq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs 








    +@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Removing sequential instance k_reg_nmi[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs 








    +@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Removing sequential instance k_clear_e in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs 








    +@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Removing sequential instance k_set_e in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs 








    +@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Removing sequential instance k_reg_firq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs 








    +@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Removing sequential instance k_reg_irq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs 








    +@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Removing sequential instance k_reg_nmi[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs 








    +@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/regblock.v":172:0:172:5|Removing sequential instance regs.fflag in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs 








    +@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/regblock.v":172:0:172:5|Removing sequential instance regs.intff in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs 








    +@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/regblock.v":172:0:172:5|Removing sequential instance regs.eflag in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs 








    +








    +Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 154MB peak: 156MB)








    +








    +@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Removing sequential instance cpu0.k_reg_firq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs 








    +@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Removing sequential instance cpu0.k_reg_irq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs 








    +@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Removing sequential instance cpu0.k_reg_nmi[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs 








    +








    +Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 150MB peak: 157MB)








    +








    +








    +








    +Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 151MB peak: 167MB)








    +








    +@N: FA113 :"/home/pacito/02_Elektronik/020_V6809/6809/regblock.v":205:24:205:32|Pipelining module un63_regl[15:0]








    +@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Register k_inc_pc pushed in.








    +@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Register k_write_pc pushed in.








    +@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Register k_new_pc[15:0] pushed in.








    +@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/alu16.v":376:0:376:5|Register regq8[7:0] pushed in.








    +@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/alu16.v":376:0:376:5|Register regq16[15:0] pushed in.








    +@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/alu16.v":376:0:376:5|Register reg_z_in pushed in.








    +@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/alu16.v":376:0:376:5|Register reg_n_in pushed in.








    +@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/regblock.v":172:0:172:5|Register vff pushed in.








    +@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/regblock.v":172:0:172:5|Register zff pushed in.








    +@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/regblock.v":172:0:172:5|Register nff pushed in.








    +@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/regblock.v":172:0:172:5|Register hflag pushed in.








    +@N: FA113 :"/home/pacito/02_Elektronik/020_V6809/6809/alu16.v":180:19:180:32|Pipelining module daa_lnm9








    +@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/alu16.v":376:0:376:5|Register regq16[15:0] pushed in.








    +@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/alu16.v":376:0:376:5|Register regq8[7:0] pushed in.








    +@N: MF169 :|Register NoName pushed in.








    +@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/regblock.v":172:0:172:5|Register cff pushed in.








    +@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":289:2:289:3|Found addmux in view:work.CC3_top(verilog) inst cpu0.dec_regs.k_new_pc_17_2_i_m2[15:0] from cpu0.un1_regs_o_pc[15:0] 








    +@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/regblock.v":205:24:205:32|Found addmux in view:work.CC3_top(verilog) inst cpu0.regs.regl\[5\]_8[15:0] from cpu0.regs.un63_regl[15:0] 








    +








    +Starting Early Timing Optimization (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 154MB peak: 167MB)








    +








    +








    +Finished Early Timing Optimization (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 154MB peak: 167MB)








    +








    +








    +Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 153MB peak: 167MB)








    +








    +








    +Finished preparing to map (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 152MB peak: 167MB)








    +








    +








    +Finished technology mapping (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 206MB peak: 229MB)








    +








    +Pass		 CPU time		Worst Slack		Luts / Registers








    +------------------------------------------------------------








    +Pass		 CPU time		Worst Slack		Luts / Registers








    +------------------------------------------------------------








    +------------------------------------------------------------








    +








    +








    +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 167MB peak: 229MB)








    +








    +@N: FX164 |The option to pack flops in the IOB has not been specified 








    +








    +Finished restoring hierarchy (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 168MB peak: 229MB)








    +








    +








    +








    +#### START OF CLOCK OPTIMIZATION REPORT #####[








    +








    +1 non-gated/non-generated clock tree(s) driving 473 clock pin(s) of sequential element(s)








    +0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)








    +274 @K:conv_instances converted, 0 sequential instances remain driven by gated/generated clocks








    +








    +=========================== Non-Gated/Non-Generated Clocks ============================








    +Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance








    +---------------------------------------------------------------------------------------








    +@K:CKID0001       clk40_i             port                   473        cpu_clk        








    +=======================================================================================








    +===== Gated/Generated Clocks =====








    +************** None **************








    +----------------------------------








    +==================================








    +








    +








    +##### END OF CLOCK OPTIMIZATION REPORT ######]








    +








    +Writing Analyst data base /home/pacito/02_Elektronik/020_V6809/6809/lattice/P6809/P6809_P6809.srm








    +








    +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 170MB peak: 229MB)








    +








    +Writing EDIF Netlist and constraint files








    +G-2012.09L-SP1 








    +@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 








    +








    +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 174MB peak: 229MB)








    +








    +@W: MT420 |Found inferred clock CC3_top|clk40_i with period 1000.00ns. Please declare a user-defined clock on object "p:clk40_i"








    +








    +








    +








    +##### START OF TIMING REPORT #####[








    +# Timing Report written on Wed Dec 25 17:50:28 2013








    +#








    +








    +








    +Top view:               CC3_top








    +Requested Frequency:    1.0 MHz








    +Wire load mode:         top








    +Paths requested:        5








    +Constraint File(s):    








    +@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.








    +








    +@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.








    +








    +








    +








    +Performance Summary 








    +*******************








    +








    +








    +Worst slack in design: 975.177








    +








    +                    Requested     Estimated     Requested     Estimated                 Clock        Clock              








    +Starting Clock      Frequency     Frequency     Period        Period        Slack       Type         Group              








    +------------------------------------------------------------------------------------------------------------------------








    +CC3_top|clk40_i     1.0 MHz       40.3 MHz      1000.000      24.823        975.177     inferred     Inferred_clkgroup_0








    +========================================================================================================================








    +








    +








    +








    +








    +








    +Clock Relationships








    +*******************








    +








    +Clocks                            |    rise  to  rise     |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 








    +--------------------------------------------------------------------------------------------------------------------------








    +Starting         Ending           |  constraint  slack    |  constraint  slack  |  constraint  slack  |  constraint  slack








    +--------------------------------------------------------------------------------------------------------------------------








    +CC3_top|clk40_i  CC3_top|clk40_i  |  1000.000    975.177  |  No paths    -      |  No paths    -      |  No paths    -    








    +==========================================================================================================================








    + Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.








    +       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.








    +








    +








    +








    +Interface Information 








    +*********************








    +








    +No IO constraint found








    +








    +








    +








    +====================================








    +Detailed Report for Clock: CC3_top|clk40_i








    +====================================








    +








    +








    +








    +Starting Points with Worst Slack








    +********************************








    +








    +                            Starting                                                       Arrival            








    +Instance                    Reference           Type        Pin     Net                    Time        Slack  








    +                            Clock                                                                             








    +--------------------------------------------------------------------------------------------------------------








    +cpu0.k_opcode[1]            CC3_top|clk40_i     FD1P3AX     Q       k_opcode[1]            1.350       975.177








    +cpu0.k_opcode[7]            CC3_top|clk40_i     FD1P3AX     Q       k_opcode[7]            1.344       975.183








    +cpu0.k_opcode[4]            CC3_top|clk40_i     FD1P3AX     Q       k_opcode[4]            1.309       975.218








    +cpu0.k_opcode[5]            CC3_top|clk40_i     FD1P3AX     Q       k_opcode[5]            1.288       975.239








    +cpu0.k_pp_active_reg[0]     CC3_top|clk40_i     FD1P3AX     Q       k_pp_active_reg[0]     1.204       975.340








    +cpu0.k_pp_active_reg[1]     CC3_top|clk40_i     FD1P3AX     Q       k_pp_active_reg[1]     1.188       975.356








    +cpu0.k_pp_active_reg[3]     CC3_top|clk40_i     FD1P3AX     Q       k_pp_active_reg[3]     1.188       975.356








    +cpu0.k_pp_active_reg[2]     CC3_top|clk40_i     FD1P3AX     Q       k_pp_active_reg[2]     1.180       975.364








    +cpu0.k_pp_active_reg[4]     CC3_top|clk40_i     FD1P3AX     Q       k_pp_active_reg[4]     1.180       975.364








    +cpu0.k_pp_active_reg[5]     CC3_top|clk40_i     FD1P3AX     Q       k_pp_active_reg[5]     1.180       975.364








    +==============================================================================================================








    +








    +








    +Ending Points with Worst Slack








    +******************************








    +








    +                            Starting                                           Required            








    +Instance                    Reference           Type        Pin     Net        Time         Slack  








    +                            Clock                                                                  








    +---------------------------------------------------------------------------------------------------








    +cpu0.alu.regq16_pipe        CC3_top|clk40_i     FD1P3AX     D       N_712      1000.089     975.177








    +cpu0.alu.regq16_pipe_11     CC3_top|clk40_i     FD1P3AX     D       N_711      1000.089     975.319








    +cpu0.alu.regq16_pipe_22     CC3_top|clk40_i     FD1P3AX     D       N_710      1000.089     975.319








    +cpu0.alu.regq16_pipe_33     CC3_top|clk40_i     FD1P3AX     D       N_709      1000.089     975.462








    +cpu0.alu.regq16_pipe_44     CC3_top|clk40_i     FD1P3AX     D       N_708      1000.089     975.462








    +cpu0.alu.regq16_pipe_55     CC3_top|clk40_i     FD1P3AX     D       N_707      1000.089     975.605








    +cpu0.alu.regq16_pipe_66     CC3_top|clk40_i     FD1P3AX     D       N_706      1000.089     975.605








    +cpu0.alu.cff_pipe_5         CC3_top|clk40_i     FD1P3AX     D       N_1009     1000.089     975.676








    +cpu0.alu.regq16_pipe_88     CC3_top|clk40_i     FD1P3AX     D       N_704      1000.089     975.676








    +cpu0.alu.regq16_pipe_77     CC3_top|clk40_i     FD1P3AX     D       N_705      1000.089     975.748








    +===================================================================================================








    +








    +








    +








    +Worst Path Information








    +***********************








    +








    +








    +Path information for path number 1: 








    +      Requested Period:                      1000.000








    +    - Setup time:                            -0.089








    +    + Clock delay at ending point:           0.000 (ideal)








    +    = Required time:                         1000.089








    +








    +    - Propagation time:                      24.912








    +    - Clock delay at starting point:         0.000 (ideal)








    +    = Slack (critical) :                     975.177








    +








    +    Number of logic level(s):                26








    +    Starting point:                          cpu0.k_opcode[1] / Q








    +    Ending point:                            cpu0.alu.regq16_pipe / D








    +    The start point is clocked by            CC3_top|clk40_i [rising] on pin CK








    +    The end   point is clocked by            CC3_top|clk40_i [rising] on pin CK








    +








    +Instance / Net                                                             Pin      Pin                Arrival     No. of    








    +Name                                                          Type         Name     Dir     Delay      Time        Fan Out(s)








    +-----------------------------------------------------------------------------------------------------------------------------








    +cpu0.k_opcode[1]                                              FD1P3AX      Q        Out     1.350      1.350       -         








    +k_opcode[1]                                                   Net          -        -       -          -           48        








    +cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_a6_2_1                ORCALUT4     A        In      0.000      1.350       -         








    +cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_a6_2_1                ORCALUT4     Z        Out     1.017      2.367       -         








    +un1_dest_reg_2_sqmuxa_1_1_a6_2_1                              Net          -        -       -          -           1         








    +cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_a6_2                  ORCALUT4     B        In      0.000      2.367       -         








    +cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_a6_2                  ORCALUT4     Z        Out     1.017      3.384       -         








    +N_372                                                         Net          -        -       -          -           1         








    +cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_2                     ORCALUT4     A        In      0.000      3.384       -         








    +cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_2                     ORCALUT4     Z        Out     1.017      4.401       -         








    +un1_dest_reg_2_sqmuxa_1_1_2                                   Net          -        -       -          -           1         








    +cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1                       ORCALUT4     C        In      0.000      4.401       -         








    +cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1                       ORCALUT4     Z        Out     1.193      5.593       -         








    +un1_dest_reg_2_sqmuxa_1_0                                     Net          -        -       -          -           4         








    +cpu0.dec_regs.path_left_addr[0]                               ORCALUT4     D        In      0.000      5.593       -         








    +cpu0.dec_regs.path_left_addr[0]                               ORCALUT4     Z        Out     0.449      6.042       -         








    +dec_o_left_path_addr[0]                                       Net          -        -       -          -           3         








    +cpu0.regs.datamux_o_alu_in_left_path_addr_1_0[0]              ORCALUT4     C        In      0.000      6.042       -         








    +cpu0.regs.datamux_o_alu_in_left_path_addr_1_0[0]              ORCALUT4     Z        Out     1.225      7.267       -         








    +N_959                                                         Net          -        -       -          -           5         








    +cpu0.regs.datamux_o_alu_in_left_path_addr_1_0_RNIB1K51[0]     ORCALUT4     B        In      0.000      7.267       -         








    +cpu0.regs.datamux_o_alu_in_left_path_addr_1_0_RNIB1K51[0]     ORCALUT4     Z        Out     1.406      8.673       -         








    +datamux_o_alu_in_left_path_addr_1[0]                          Net          -        -       -          -           55        








    +cpu0.regs.path_left_data_7_am_1[0]                            ORCALUT4     A        In      0.000      8.673       -         








    +cpu0.regs.path_left_data_7_am_1[0]                            ORCALUT4     Z        Out     1.017      9.690       -         








    +path_left_data_7_am_1[0]                                      Net          -        -       -          -           1         








    +cpu0.regs.path_left_data_7_am[0]                              ORCALUT4     B        In      0.000      9.690       -         








    +cpu0.regs.path_left_data_7_am[0]                              ORCALUT4     Z        Out     1.017      10.707      -         








    +path_left_data_7_am[0]                                        Net          -        -       -          -           1         








    +cpu0.regs.path_left_data_7[0]                                 PFUMX        BLUT     In      0.000      10.707      -         








    +cpu0.regs.path_left_data_7[0]                                 PFUMX        Z        Out     -0.033     10.674      -         








    +N_401                                                         Net          -        -       -          -           1         








    +cpu0.regs.path_left_data[0]                                   L6MUX21      D0       In      0.000      10.674      -         








    +cpu0.regs.path_left_data[0]                                   L6MUX21      Z        Out     0.868      11.542      -         








    +regs_o_left_path_data[0]                                      Net          -        -       -          -           3         








    +cpu0.alu.datamux_o_alu_in_left_path_data[0]                   ORCALUT4     C        In      0.000      11.542      -         








    +cpu0.alu.datamux_o_alu_in_left_path_data[0]                   ORCALUT4     Z        Out     1.384      12.926      -         








    +datamux_o_alu_in_left_path_data[0]                            Net          -        -       -          -           41        








    +cpu0.alu.mul16_w_madd_0_cry_0_0                               CCU2D        C1       In      0.000      12.926      -         








    +cpu0.alu.mul16_w_madd_0_cry_0_0                               CCU2D        COUT     Out     1.544      14.470      -         








    +mul16_w_madd_0_cry_0                                          Net          -        -       -          -           1         








    +cpu0.alu.mul16_w_madd_0_cry_1_0                               CCU2D        CIN      In      0.000      14.470      -         








    +cpu0.alu.mul16_w_madd_0_cry_1_0                               CCU2D        S0       Out     1.621      16.091      -         








    +mul16_w_madd_4                                                Net          -        -       -          -           2         








    +cpu0.alu.mul16_w_madd_4_cry_0_0                               CCU2D        A1       In      0.000      16.091      -         








    +cpu0.alu.mul16_w_madd_4_cry_0_0                               CCU2D        COUT     Out     1.544      17.636      -         








    +mul16_w_madd_4_cry_0                                          Net          -        -       -          -           1         








    +cpu0.alu.mul16_w_madd_4_cry_1_0                               CCU2D        CIN      In      0.000      17.636      -         








    +cpu0.alu.mul16_w_madd_4_cry_1_0                               CCU2D        S1       Out     1.621      19.257      -         








    +mul16_w_madd                                                  Net          -        -       -          -           2         








    +cpu0.alu.mul16_w_madd_cry_0_0                                 CCU2D        A1       In      0.000      19.257      -         








    +cpu0.alu.mul16_w_madd_cry_0_0                                 CCU2D        COUT     Out     1.544      20.801      -         








    +mul16_w_madd_cry_0                                            Net          -        -       -          -           1         








    +cpu0.alu.mul16_w_madd_cry_1_0                                 CCU2D        CIN      In      0.000      20.801      -         








    +cpu0.alu.mul16_w_madd_cry_1_0                                 CCU2D        COUT     Out     0.143      20.944      -         








    +mul16_w_madd_cry_2                                            Net          -        -       -          -           1         








    +cpu0.alu.mul16_w_madd_cry_3_0                                 CCU2D        CIN      In      0.000      20.944      -         








    +cpu0.alu.mul16_w_madd_cry_3_0                                 CCU2D        COUT     Out     0.143      21.087      -         








    +mul16_w_madd_cry_4                                            Net          -        -       -          -           1         








    +cpu0.alu.mul16_w_madd_cry_5_0                                 CCU2D        CIN      In      0.000      21.087      -         








    +cpu0.alu.mul16_w_madd_cry_5_0                                 CCU2D        COUT     Out     0.143      21.230      -         








    +mul16_w_madd_cry_6                                            Net          -        -       -          -           1         








    +cpu0.alu.mul16_w_madd_cry_7_0                                 CCU2D        CIN      In      0.000      21.230      -         








    +cpu0.alu.mul16_w_madd_cry_7_0                                 CCU2D        COUT     Out     0.143      21.372      -         








    +mul16_w_madd_cry_8                                            Net          -        -       -          -           1         








    +cpu0.alu.mul16_w_madd_cry_9_0                                 CCU2D        CIN      In      0.000      21.372      -         








    +cpu0.alu.mul16_w_madd_cry_9_0                                 CCU2D        COUT     Out     0.143      21.515      -         








    +mul16_w_madd_cry_10                                           Net          -        -       -          -           1         








    +cpu0.alu.mul16_w_madd_s_11_0                                  CCU2D        CIN      In      0.000      21.515      -         








    +cpu0.alu.mul16_w_madd_s_11_0                                  CCU2D        S0       Out     1.549      23.064      -         








    +mul16_w[15]                                                   Net          -        -       -          -           1         








    +cpu0.alu.q16_11_bm[15]                                        ORCALUT4     A        In      0.000      23.064      -         








    +cpu0.alu.q16_11_bm[15]                                        ORCALUT4     Z        Out     1.017      24.081      -         








    +q16_11_bm[15]                                                 Net          -        -       -          -           1         








    +cpu0.alu.q16_11[15]                                           PFUMX        ALUT     In      0.000      24.081      -         








    +cpu0.alu.q16_11[15]                                           PFUMX        Z        Out     0.214      24.295      -         








    +N_696                                                         Net          -        -       -          -           1         








    +cpu0.alu.q16_12[15]                                           ORCALUT4     B        In      0.000      24.295      -         








    +cpu0.alu.q16_12[15]                                           ORCALUT4     Z        Out     0.617      24.912      -         








    +N_712                                                         Net          -        -       -          -           1         








    +cpu0.alu.regq16_pipe                                          FD1P3AX      D        In      0.000      24.912      -         








    +=============================================================================================================================








    +








    +








    +








    +##### END OF TIMING REPORT #####]








    +








    +---------------------------------------








    +Resource Usage Report








    +Part: lcmxo2_7000he-4








    +








    +Register bits: 469 of 6864 (7%)








    +PIC Latch:       0








    +I/O cells:       49








    +Block Rams : 2 of 26 (7%)








    +








    +








    +Details:








    +CCU2D:          205








    +DP8KC:          2








    +FD1P3AX:        449








    +FD1P3DX:        6








    +FD1P3IX:        1








    +FD1P3JX:        4








    +FD1S3AX:        1








    +GSR:            1








    +IB:             1








    +INV:            5








    +L6MUX21:        21








    +OB:             48








    +OFS1P3DX:       8








    +ORCALUT4:       1904








    +PFUMX:          224








    +PUR:            1








    +VHI:            4








    +VLO:            10








    +true:           6








    +Mapper successful!








    +








    +At Mapper Exit (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 44MB peak: 229MB)








    +








    +Process took 0h:00m:14s realtime, 0h:00m:14s cputime








    +# Wed Dec 25 17:50:28 2013








    +








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    +
P6809 project summary
Module Name:P6809Synthesis:SynplifyPro
Implementation Name:P6809Strategy Name:Strategy1
Last Process:Place & Route TraceState:Passed
Target Device:LCMXO2-7000HE-4TG144IDevice Family:MachXO2
Device Type:LCMXO2-7000HEPackage Type:TQFP144
Performance grade:4Operating conditions:IND
Logic preference file:P6809.lpf
Physical Preference file:P6809/P6809_P6809.prf
Product Version:2.2.0.101Patch Version:
Updated:2013/12/25 18:32:42
Implementation Location:/home/pacito/02_Elektronik/020_V6809/6809/lattice/P6809
Project File:/home/pacito/02_Elektronik/020_V6809/6809/lattice/P6809.ldf









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I/O Timing Report








    +Loading design for application iotiming from file P6809_P6809.ncd.








    +Design name: CC3_top








    +NCD version: 3.2








    +Vendor:      LATTICE








    +Device:      LCMXO2-7000HE








    +Package:     TQFP144








    +Performance: 5








    +Package Status:                     Final          Version 1.36








    +Performance Hardware Data Status:   Final)         Version 23.4








    +Loading design for application iotiming from file P6809_P6809.ncd.








    +Design name: CC3_top








    +NCD version: 3.2








    +Vendor:      LATTICE








    +Device:      LCMXO2-7000HE








    +Package:     TQFP144








    +Performance: 6








    +Package Status:                     Final          Version 1.36








    +Performance Hardware Data Status:   Final)         Version 23.4








    +Loading design for application iotiming from file P6809_P6809.ncd.








    +Design name: CC3_top








    +NCD version: 3.2








    +Vendor:      LATTICE








    +Device:      LCMXO2-7000HE








    +Package:     TQFP144








    +Performance: M








    +Package Status:                     Final          Version 1.36








    +Performance Hardware Data Status:   Final)         Version 23.4








    +// Design: CC3_top








    +// Package: TQFP144








    +// ncd File: P6809_P6809.ncd








    +// Version: Diamond (64-bit) 2.2.0.101








    +// Written on Sun Dec  1 11:45:54 2013








    +// M: Minimum Performance Grade








    +// iotiming P6809_P6809.ncd P6809_P6809.prf








    +








    +I/O Timing Report (All units are in ns)








    +








    +Worst Case Results across Performance Grades (M, 6, 5, 4):








    +








    +// Input Setup and Hold Times








    +








    +Port  Clock Edge  Setup Performance_Grade  Hold Performance_Grade








    +----------------------------------------------------------------------








    +(no input setup/hold data)








    +








    +








    +// Clock to Output Delay








    +








    +Port       Clock   Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade








    +------------------------------------------------------------------------








    +addr_o[0]  clk40_i R    41.611         4        3.619          M








    +addr_o[10] clk40_i R    46.573         4        3.378          M








    +addr_o[11] clk40_i R    47.114         4        3.507          M








    +addr_o[12] clk40_i R    48.171         4        3.484          M








    +addr_o[13] clk40_i R    49.848         4        3.284          M








    +addr_o[14] clk40_i R    48.609         4        3.430          M








    +addr_o[15] clk40_i R    47.119         4        3.094          M








    +addr_o[1]  clk40_i R    43.836         4        3.722          M








    +addr_o[2]  clk40_i R    46.227         4        3.619          M








    +addr_o[3]  clk40_i R    44.300         4        3.439          M








    +addr_o[4]  clk40_i R    44.674         4        3.602          M








    +addr_o[5]  clk40_i R    45.422         4        3.808          M








    +addr_o[6]  clk40_i R    47.504         4        3.708          M








    +addr_o[7]  clk40_i R    46.761         4        3.740          M








    +addr_o[8]  clk40_i R    46.239         4        3.520          M








    +addr_o[9]  clk40_i R    45.470         4        3.592          M








    +cen_o      clk40_i R    16.673         4        3.105          M








    +cpuclk_o   clk40_i R    11.045         4        3.067          M








    +data_io[0] clk40_i R    56.130         4        3.957          M








    +data_io[1] clk40_i R    58.070         4        3.982          M








    +data_io[2] clk40_i R    57.514         4        4.090          M








    +data_io[3] clk40_i R    58.051         4        3.990          M








    +data_io[4] clk40_i R    56.783         4        3.911          M








    +data_io[5] clk40_i R    59.973         4        4.014          M








    +data_io[6] clk40_i R    61.430         4        3.836          M








    +data_io[7] clk40_i R    60.991         4        3.727          M








    +leds_o[0]  clk40_i R     8.259         4        2.366          M








    +leds_o[1]  clk40_i R     8.259         4        2.366          M








    +leds_o[2]  clk40_i R     8.259         4        2.366          M








    +leds_o[3]  clk40_i R     8.259         4        2.366          M








    +leds_o[4]  clk40_i R     8.259         4        2.366          M








    +leds_o[5]  clk40_i R     8.259         4        2.366          M








    +leds_o[6]  clk40_i R     8.259         4        2.366          M








    +leds_o[7]  clk40_i R     8.259         4        2.366          M








    +oen_o      clk40_i R    17.030         4        3.258          M








    +reset_o    clk40_i R    12.741         4        3.065          M








    +state_o[0] clk40_i R    17.013         4        3.390          M








    +state_o[1] clk40_i R    17.517         4        3.140          M








    +state_o[2] clk40_i R    15.318         4        3.080          M








    +state_o[3] clk40_i R    19.807         4        3.491          M








    +state_o[4] clk40_i R    18.231         4        3.908          M








    +wen_o      clk40_i R    15.352         4        3.593          M








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/syn/lattice/CC3_top.v
0,0 → 1,111
/*
* Synthesis top Module for the MC6809/HD6309 compatible core.
* This top module has been tested in the MachXO2-7000HE breakout board
* (c) 2013 R.A. Paz Schmidt rapazschmidt@gmail.com
* Distributed under the terms of the Lesser GPL
*
* Implemented using diamond 2.1
*/
module CC3_top(
input wire clk40_i,
/* CPU Bus */
output wire cpuclk_o,
output wire reset_o,
output wire [15:0] addr_o,
output wire oen_o,
output wire wen_o,
output wire cen_o,
output wire [7:0] data_io,
output wire [5:0] state_o,
/* Debug */
output wire [7:0] leds_o,
/* VGA output */
output wire hsync_o,
output wire vsync_o,
output wire red_o,
output wire green_o,
output wire blue_o
);
+reg cpu_clk, clk_div2; +reg [3:0] reset_cnt; +reg [7:0] leds_r; + +/* CPU IO */ +wire [15:0] cpu0_addr_o, cpu1_addr_o; +wire [7:0] cpu0_data_in, cpu0_data_out, cpu1_data_in, cpu1_data_out; +wire cpu0_we, cpu0_oe, cpu1_we, cpu1_oe, cpu_reset; +wire [5:0] cpu0_state; +/* Module io */ + +assign addr_o = cpu0_addr_o; +assign data_io = cpu0_we ? cpu0_data_out:cpu0_data_in; + +assign hsync_o = 0; +assign vsync_o = 0; +assign red_o = 0; +assign green_o = 0; +assign blue_o = 0; +assign leds_o = leds_r; + +assign oen_o = !cpu0_oe; +assign wen_o = !cpu0_we; +assign cen_o = !(cpu0_oe | cpu0_we); +assign cpuclk_o = cpu_clk; +assign reset_o = cpu_reset; +assign state_o = cpu0_state; + +always @(posedge clk40_i) + cpu_clk <= !cpu_clk; + +assign cpu_reset = reset_cnt != 4'd14; +always @(posedge cpu_clk) + begin + if (reset_cnt != 4'd14) + reset_cnt <= reset_cnt + 4'h1; + if (cpu0_we) + leds_r <= cpu0_data_out; + end + + +MC6809_cpu cpu0( + .cpu_clk(cpu_clk), + .cpu_reset(cpu_reset), + .cpu_nmi_n(1'b0), + .cpu_irq_n(1'b0), + .cpu_firq_n(1'b0), + .cpu_state_o(cpu0_state), + .cpu_we_o(cpu0_we), + .cpu_oe_o(cpu0_oe), + .cpu_addr_o(cpu0_addr_o), + .cpu_data_i(cpu0_data_in), + .cpu_data_o(cpu0_data_out) + ); + +/* Memory */ + +bios2k bios( + .DataInA(cpu0_data_out[7:0]), + .DataInB(cpu1_data_out[7:0]), + .AddressA(cpu0_addr_o[10:0]), + .AddressB(cpu1_addr_o[10:0]), + .ClockA(clk40_i), + .ClockB(clk40_i), + .ClockEnA((cpu0_we | cpu0_oe)), + .ClockEnB(1'b0), + .WrA(cpu0_we), + .WrB(1'b0),//cpu1_we), + .ResetA(1'b0), + .ResetB(1'b0), + .QA(cpu0_data_in), + .QB() + ); + + + + + +endmodule
/syn/xilinx/logs/CC3_top_x.par
0,0 → 1,180
Release 10.1 par K.31 (lin)
Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
 
node01.pacito.sys:: Wed Dec 25 11:42:55 2013
 
par -w -intstyle ise -ol std -t 1 CC3_top_x_map.ncd CC3_top_x.ncd CC3_top_x.pcf
 
 
Constraints file: CC3_top_x.pcf.
Loading device for application Rf_Device from file 'v100.nph' in environment /home/pacito/Xilinx/10.1/ISE.
"CC3_top_x" is an NCD, version 3.2, device xc2s100, package pq208, speed -5
 
Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
Initializing voltage to 2.375 Volts. (default - Range: 2.375 to 2.625 Volts)
 
INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
-x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For
the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". For a
balance between the fastest runtime and best performance, set the effort level to "med".
 
Device speed data version: "PRODUCTION 1.27 2008-01-09".
 
 
Device Utilization Summary:
 
Number of BLOCKRAMs 1 out of 10 10%
Number of GCLKs 1 out of 4 25%
Number of External GCLKIOBs 1 out of 4 25%
Number of LOCed GCLKIOBs 0 out of 1 0%
 
Number of External IOBs 26 out of 140 18%
Number of LOCed IOBs 0 out of 26 0%
 
Number of SLICEs 1198 out of 1200 99%
 
 
Overall effort level (-ol): Standard
Placer effort level (-pl): High
Placer cost table entry (-t): 1
Router effort level (-rl): Standard
 
 
Starting Placer
 
Phase 1.1
Phase 1.1 (Checksum:98c581) REAL time: 0 secs
 
Phase 2.7
Phase 2.7 (Checksum:1312cfe) REAL time: 0 secs
 
Phase 3.31
Phase 3.31 (Checksum:1c9c37d) REAL time: 0 secs
 
Phase 4.23
Phase 4.23 (Checksum:26259fc) REAL time: 0 secs
 
Phase 5.3
...
Phase 5.3 (Checksum:2faf07b) REAL time: 0 secs
 
Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs
 
Phase 7.8
..........
.............................................................
....................
..............................................................................................................
..................................
....................................
Phase 7.8 (Checksum:e43d41) REAL time: 4 secs
 
Phase 8.5
Phase 8.5 (Checksum:4c4b3f8) REAL time: 4 secs
 
Phase 9.18
Phase 9.18 (Checksum:55d4a77) REAL time: 6 secs
 
Phase 10.5
Phase 10.5 (Checksum:5f5e0f6) REAL time: 6 secs
 
REAL time consumed by placer: 6 secs
CPU time consumed by placer: 6 secs
Writing design to file CC3_top_x.ncd
 
 
Total REAL time to Placer completion: 6 secs
Total CPU time to Placer completion: 6 secs
 
Starting Router
 
Phase 1: 8784 unrouted; REAL time: 6 secs
 
Phase 2: 8535 unrouted; REAL time: 7 secs
 
Phase 3: 2951 unrouted; REAL time: 7 secs
 
Phase 4: 2951 unrouted; (958) REAL time: 7 secs
 
Phase 5: 2960 unrouted; (0) REAL time: 7 secs
 
Phase 6: 0 unrouted; (0) REAL time: 8 secs
 
Phase 7: 0 unrouted; (0) REAL time: 9 secs
 
Phase 8: 0 unrouted; (0) REAL time: 9 secs
 
Phase 9: 0 unrouted; (0) REAL time: 9 secs
 
Total REAL time to Router completion: 9 secs
Total CPU time to Router completion: 9 secs
 
Partition Implementation Status
-------------------------------
 
No Partitions were found in this design.
 
-------------------------------
 
Generating "PAR" statistics.
 
**************************
Generating Clock Report
**************************
 
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| clk32_i_BUFGP | GCLKBUF1| No | 249 | 0.481 | 0.677 |
+---------------------+--------------+------+------+------------+-------------+
 
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
 
Timing Score: 0
 
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no
requested value.
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
 
------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net clk | SETUP | N/A| 66.168ns| N/A| 0
32_i_BUFGP | HOLD | 2.524ns| | 0| 0
------------------------------------------------------------------------------------------------------
 
 
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
constraint does not cover any paths or that it has no requested value.
 
 
Generating Pad Report.
 
All signals are completely routed.
 
Total REAL time to PAR completion: 10 secs
Total CPU time to PAR completion: 10 secs
 
Peak Memory Usage: 120 MB
 
Placement: Completed - No errors found.
Routing: Completed - No errors found.
 
Number of error messages: 0
Number of warning messages: 0
Number of info messages: 2
 
Writing design to file CC3_top_x.ncd
 
 
 
PAR done!
/syn/xilinx/logs/CC3_top_x.cmd_log
0,0 → 1,15
xst -ise "/home/pacito/02_Elektronik/020_V6809/6809/xilinx/P6809/P6809.ise" -intstyle ise -ifn "/home/pacito/02_Elektronik/020_V6809/6809/xilinx/P6809/CC3_top_x.xst" -ofn "/home/pacito/02_Elektronik/020_V6809/6809/xilinx/P6809/CC3_top_x.syr"
ngdbuild -ise "/home/pacito/02_Elektronik/020_V6809/6809/xilinx/P6809/P6809.ise" -intstyle ise -dd _ngo -nt timestamp -i -p xc2s100-pq208-5 "CC3_top_x.ngc" CC3_top_x.ngd
map -ise "/home/pacito/02_Elektronik/020_V6809/6809/xilinx/P6809/P6809.ise" -intstyle ise -p xc2s100-pq208-5 -cm area -pr off -k 4 -c 100 -tx off -o CC3_top_x_map.ncd CC3_top_x.ngd CC3_top_x.pcf
par -ise "/home/pacito/02_Elektronik/020_V6809/6809/xilinx/P6809/P6809.ise" -w -intstyle ise -ol std -t 1 CC3_top_x_map.ncd CC3_top_x.ncd CC3_top_x.pcf
trce -ise "/home/pacito/02_Elektronik/020_V6809/6809/xilinx/P6809/P6809.ise" -intstyle ise -e 3 -s 5 -xml CC3_top_x CC3_top_x.ncd -o CC3_top_x.twr CC3_top_x.pcf
xst -ise "/home/pacito/02_Elektronik/020_V6809/6809/xilinx/P6809/P6809.ise" -intstyle ise -ifn "/home/pacito/02_Elektronik/020_V6809/6809/xilinx/P6809/CC3_top_x.xst" -ofn "/home/pacito/02_Elektronik/020_V6809/6809/xilinx/P6809/CC3_top_x.syr"
ngdbuild -ise "/home/pacito/02_Elektronik/020_V6809/6809/xilinx/P6809/P6809.ise" -intstyle ise -dd _ngo -nt timestamp -i -p xc2s100-pq208-5 "CC3_top_x.ngc" CC3_top_x.ngd
map -ise "/home/pacito/02_Elektronik/020_V6809/6809/xilinx/P6809/P6809.ise" -intstyle ise -p xc2s100-pq208-5 -cm area -pr off -k 4 -c 100 -tx off -o CC3_top_x_map.ncd CC3_top_x.ngd CC3_top_x.pcf
par -ise "/home/pacito/02_Elektronik/020_V6809/6809/xilinx/P6809/P6809.ise" -w -intstyle ise -ol std -t 1 CC3_top_x_map.ncd CC3_top_x.ncd CC3_top_x.pcf
trce -ise "/home/pacito/02_Elektronik/020_V6809/6809/xilinx/P6809/P6809.ise" -intstyle ise -e 3 -s 5 -xml CC3_top_x CC3_top_x.ncd -o CC3_top_x.twr CC3_top_x.pcf
xst -ise "/home/pacito/02_Elektronik/020_V6809/6809/xilinx/P6809/P6809.ise" -intstyle ise -ifn "/home/pacito/02_Elektronik/020_V6809/6809/xilinx/P6809/CC3_top_x.xst" -ofn "/home/pacito/02_Elektronik/020_V6809/6809/xilinx/P6809/CC3_top_x.syr"
ngdbuild -ise "/home/pacito/02_Elektronik/020_V6809/6809/xilinx/P6809/P6809.ise" -intstyle ise -dd _ngo -nt timestamp -i -p xc2s100-pq208-5 "CC3_top_x.ngc" CC3_top_x.ngd
map -ise "/home/pacito/02_Elektronik/020_V6809/6809/xilinx/P6809/P6809.ise" -intstyle ise -p xc2s100-pq208-5 -cm area -pr off -k 4 -c 100 -tx off -o CC3_top_x_map.ncd CC3_top_x.ngd CC3_top_x.pcf
par -ise "/home/pacito/02_Elektronik/020_V6809/6809/xilinx/P6809/P6809.ise" -w -intstyle ise -ol std -t 1 CC3_top_x_map.ncd CC3_top_x.ncd CC3_top_x.pcf
trce -ise "/home/pacito/02_Elektronik/020_V6809/6809/xilinx/P6809/P6809.ise" -intstyle ise -e 3 -s 5 -xml CC3_top_x CC3_top_x.ncd -o CC3_top_x.twr CC3_top_x.pcf
/syn/xilinx/logs/CC3_top_x.pad
0,0 → 1,238
Release 10.1 - par K.31 (lin)
Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
 
Wed Dec 25 11:43:06 2013
 
 
# NOTE: This file is designed to be imported into a spreadsheet program
# such as Microsoft Excel for viewing, printing and sorting. The |
# character is used as the data field separator. This file is also designed
# to support parsing.
#
INPUT FILE: CC3_top_x_map.ncd
OUTPUT FILE: CC3_top_x.pad
PART TYPE: xc2s100
SPEED GRADE: -5
PACKAGE: pq208
 
Pinout by Pin Number:
 
-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
Pin Number|Signal Name|Pin Usage|Pin Name|Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage|Constraint|DCI Value|IO Register|Signal Integrity|
P1|||GND|||||||||||||
P2|||TMS|||||||||||||
P3||IOB|IO|UNUSED||7||||||||||
P4||IOB|IO|UNUSED||7||||||||||
P5||IOB|IO|UNUSED||7||||||||||
P6||IOB|IO_VREF_7|UNUSED||7||||||||||
P7||IOB|IO|UNUSED||7||||||||||
P8|mem_addr_o<15>|IOB|IO|OUTPUT|LVTTL*|7|12|SLOW|NONE**|||||NO|NONE|
P9||IOB|IO_VREF_7|UNUSED||7||||||||||
P10||IOB|IO|UNUSED||7||||||||||
P11|||GND|||||||||||||
P12|||VCCO|||0|||||3.30|||||
P13|||VCCINT||||||||2.5|||||
P14||IOB|IO|UNUSED||7||||||||||
P15|mem_addr_o<12>|IOB|IO|OUTPUT|LVTTL*|7|12|SLOW|NONE**|||||NO|NONE|
P16||IOB|IO|UNUSED||7||||||||||
P17|mem_addr_o<9>|IOB|IO|OUTPUT|LVTTL*|7|12|SLOW|NONE**|||||NO|NONE|
P18||IOB|IO|UNUSED||7||||||||||
P19|||GND|||||||||||||
P20|mem_addr_o<14>|IOB|IO_VREF_7|OUTPUT|LVTTL*|7|12|SLOW|NONE**|||||NO|NONE|
P21||IOB|IO|UNUSED||7||||||||||
P22||IOB|IO|UNUSED||7||||||||||
P23||IOB|IO|UNUSED||7||||||||||
P24||PCIIOB|IO_IRDY|UNUSED||7||||||||||
P25|||GND|||||||||||||
P26|||VCCO|||0|||||3.30|||||
P27|mem_addr_o<13>|IOB|IO_TRDY|OUTPUT|LVTTL*|6|12|SLOW|NONE**|||||NO|NONE|
P28|||VCCINT||||||||2.5|||||
P29|mem_addr_o<11>|IOB|IO|OUTPUT|LVTTL*|6|12|SLOW|NONE**|||||NO|NONE|
P30||IOB|IO|UNUSED||6||||||||||
P31|mem_addr_o<10>|IOB|IO_VREF_6|OUTPUT|LVTTL*|6|12|SLOW|NONE**|||||NO|NONE|
P32|||GND|||||||||||||
P33||IOB|IO|UNUSED||6||||||||||
P34|mem_addr_o<7>|IOB|IO|OUTPUT|LVTTL*|6|12|SLOW|NONE**|||||NO|NONE|
P35|mem_addr_o<8>|IOB|IO|OUTPUT|LVTTL*|6|12|SLOW|NONE**|||||NO|NONE|
P36||IOB|IO|UNUSED||6||||||||||
P37||IOB|IO|UNUSED||6||||||||||
P38|||VCCINT||||||||2.5|||||
P39|||VCCO|||0|||||3.30|||||
P40|||GND|||||||||||||
P41|mem_we_n|IOB|IO|OUTPUT|LVTTL*|6|12|SLOW|NONE**|||||NO|NONE|
P42|mem_oe_n|IOB|IO_VREF_6|OUTPUT|LVTTL*|6|12|SLOW|NONE**|||||NO|NONE|
P43|mem_addr_o<6>|IOB|IO|OUTPUT|LVTTL*|6|12|SLOW|NONE**|||||NO|NONE|
P44|mem_addr_o<5>|IOB|IO|OUTPUT|LVTTL*|6|12|SLOW|NONE**|||||NO|NONE|
P45|mem_addr_o<4>|IOB|IO_VREF_6|OUTPUT|LVTTL*|6|12|SLOW|NONE**|||||NO|NONE|
P46|mem_addr_o<3>|IOB|IO|OUTPUT|LVTTL*|6|12|SLOW|NONE**|||||NO|NONE|
P47|mem_addr_o<2>|IOB|IO|OUTPUT|LVTTL*|6|12|SLOW|NONE**|||||NO|NONE|
P48|mem_addr_o<1>|IOB|IO|OUTPUT|LVTTL*|6|12|SLOW|NONE**|||||NO|NONE|
P49|mem_addr_o<0>|IOB|IO|OUTPUT|LVTTL*|6|12|SLOW|NONE**|||||NO|NONE|
P50|||M1|||||||||||||
P51|||GND|||||||||||||
P52|||M0|||||||||||||
P53|||VCCO|||0|||||3.30|||||
P54|||M2|||||||||||||
P55|||NC|||||||||||||
P56|||NC|||||||||||||
P57||IOB|IO|UNUSED||5||||||||||
P58||IOB|IO|UNUSED||5||||||||||
P59||IOB|IO_VREF_5|UNUSED||5||||||||||
P60||IOB|IO|UNUSED||5||||||||||
P61||IOB|IO|UNUSED||5||||||||||
P62||IOB|IO_VREF_5|UNUSED||5||||||||||
P63||IOB|IO|UNUSED||5||||||||||
P64|||GND|||||||||||||
P65|||VCCO|||0|||||3.30|||||
P66|||VCCINT||||||||2.5|||||
P67||IOB|IO|UNUSED||5||||||||||
P68||IOB|IO|UNUSED||5||||||||||
P69||IOB|IO|UNUSED||5||||||||||
P70||IOB|IO|UNUSED||5||||||||||
P71||IOB|IO|UNUSED||5||||||||||
P72|||GND|||||||||||||
P73||IOB|IO_VREF_5|UNUSED||5||||||||||
P74||IOB|IO|UNUSED||5||||||||||
P75||IOB|IO|UNUSED||5||||||||||
P76|||VCCINT||||||||2.5|||||
P77|clk32_i|GCLKIOB|GCK1|INPUT|LVTTL*|5||||NONE||||NO|NONE|
P78|||VCCO|||0|||||3.30|||||
P79|||GND|||||||||||||
P80||GCLKIOB|GCK0|UNUSED||4||||||||||
P81||IOB|IO|UNUSED||4||||||||||
P82||IOB|IO|UNUSED||4||||||||||
P83||IOB|IO|UNUSED||4||||||||||
P84||IOB|IO_VREF_4|UNUSED||4||||||||||
P85|||GND|||||||||||||
P86||IOB|IO|UNUSED||4||||||||||
P87||IOB|IO|UNUSED||4||||||||||
P88||IOB|IO|UNUSED||4||||||||||
P89||IOB|IO|UNUSED||4||||||||||
P90||IOB|IO|UNUSED||4||||||||||
P91|||VCCINT||||||||2.5|||||
P92|||VCCO|||0|||||3.30|||||
P93|||GND|||||||||||||
P94||IOB|IO|UNUSED||4||||||||||
P95||IOB|IO_VREF_4|UNUSED||4||||||||||
P96||IOB|IO|UNUSED||4||||||||||
P97||IOB|IO|UNUSED||4||||||||||
P98||IOB|IO_VREF_4|UNUSED||4||||||||||
P99||IOB|IO|UNUSED||4||||||||||
P100||IOB|IO|UNUSED||4||||||||||
P101||IOB|IO|UNUSED||4||||||||||
P102||IOB|IO|UNUSED||4||||||||||
P103|||GND|||||||||||||
P104|||DONE|||||||||||||
P105|||VCCO|||0|||||3.30|||||
P106|||PROGRAM|||||||||||||
P107||IOB|IO_INIT|UNUSED||3||||||||||
P108||IOB|IO_D7|UNUSED||3||||||||||
P109||IOB|IO|UNUSED||3||||||||||
P110||IOB|IO|UNUSED||3||||||||||
P111||IOB|IO_VREF_3|UNUSED||3||||||||||
P112||IOB|IO|UNUSED||3||||||||||
P113||IOB|IO|UNUSED||3||||||||||
P114||IOB|IO_VREF_3|UNUSED||3||||||||||
P115||IOB|IO_D6|UNUSED||3||||||||||
P116|||GND|||||||||||||
P117|||VCCO|||0|||||3.30|||||
P118|||VCCINT||||||||2.5|||||
P119||IOB|IO_D5|UNUSED||3||||||||||
P120||IOB|IO|UNUSED||3||||||||||
P121||IOB|IO|UNUSED||3||||||||||
P122||IOB|IO|UNUSED||3||||||||||
P123||IOB|IO|UNUSED||3||||||||||
P124|||GND|||||||||||||
P125||IOB|IO_VREF_3|UNUSED||3||||||||||
P126||IOB|IO_D4|UNUSED||3||||||||||
P127||IOB|IO|UNUSED||3||||||||||
P128|||VCCINT||||||||2.5|||||
P129||PCIIOB|IO_TRDY|UNUSED||3||||||||||
P130|||VCCO|||0|||||3.30|||||
P131|||GND|||||||||||||
P132||PCIIOB|IO_IRDY|UNUSED||2||||||||||
P133||IOB|IO|UNUSED||2||||||||||
P134||IOB|IO|UNUSED||2||||||||||
P135||IOB|IO_D3|UNUSED||2||||||||||
P136||IOB|IO_VREF_2|UNUSED||2||||||||||
P137|||GND|||||||||||||
P138||IOB|IO|UNUSED||2||||||||||
P139||IOB|IO|UNUSED||2||||||||||
P140||IOB|IO|UNUSED||2||||||||||
P141||IOB|IO|UNUSED||2||||||||||
P142||IOB|IO_D2|UNUSED||2||||||||||
P143|||VCCINT||||||||2.5|||||
P144|||VCCO|||0|||||3.30|||||
P145|||GND|||||||||||||
P146||IOB|IO_D1|UNUSED||2||||||||||
P147||IOB|IO_VREF_2|UNUSED||2||||||||||
P148||IOB|IO|UNUSED||2||||||||||
P149||IOB|IO|UNUSED||2||||||||||
P150||IOB|IO_VREF_2|UNUSED||2||||||||||
P151||IOB|IO|UNUSED||2||||||||||
P152||IOB|IO|UNUSED||2||||||||||
P153||IOB|IO_DIN_D0|UNUSED||2||||||||||
P154||IOB|IO_DOUT_BUSY|UNUSED||2||||||||||
P155|||CCLK|||||||||||||
P156|||VCCO|||0|||||3.30|||||
P157|||TDO|||||||||||||
P158|||GND|||||||||||||
P159|||TDI|||||||||||||
P160||IOB|IO_CS|UNUSED||1||||||||||
P161||IOB|IO_WRITE|UNUSED||1||||||||||
P162||IOB|IO|UNUSED||1||||||||||
P163||IOB|IO|UNUSED||1||||||||||
P164||IOB|IO_VREF_1|UNUSED||1||||||||||
P165||IOB|IO|UNUSED||1||||||||||
P166||IOB|IO|UNUSED||1||||||||||
P167||IOB|IO_VREF_1|UNUSED||1||||||||||
P168|mem_data_io<7>|IOB|IO|OUTPUT|LVTTL*|1|12|SLOW|NONE**|||||NO|NONE|
P169|||GND|||||||||||||
P170|||VCCO|||0|||||3.30|||||
P171|||VCCINT||||||||2.5|||||
P172||IOB|IO|UNUSED||1||||||||||
P173||IOB|IO|UNUSED||1||||||||||
P174||IOB|IO|UNUSED||1||||||||||
P175|mem_data_io<6>|IOB|IO|OUTPUT|LVTTL*|1|12|SLOW|NONE**|||||NO|NONE|
P176|mem_data_io<2>|IOB|IO|OUTPUT|LVTTL*|1|12|SLOW|NONE**|||||NO|NONE|
P177|||GND|||||||||||||
P178|mem_data_io<3>|IOB|IO_VREF_1|OUTPUT|LVTTL*|1|12|SLOW|NONE**|||||NO|NONE|
P179||IOB|IO|UNUSED||1||||||||||
P180|mem_data_io<5>|IOB|IO|OUTPUT|LVTTL*|1|12|SLOW|NONE**|||||NO|NONE|
P181||IOB|IO|UNUSED||1||||||||||
P182||GCLKIOB|GCK2|UNUSED||1||||||||||
P183|||GND|||||||||||||
P184|||VCCO|||0|||||3.30|||||
P185||GCLKIOB|GCK3|UNUSED||0||||||||||
P186|||VCCINT||||||||2.5|||||
P187|mem_data_io<4>|IOB|IO|OUTPUT|LVTTL*|0|12|SLOW|NONE**|||||NO|NONE|
P188|mem_data_io<1>|IOB|IO|OUTPUT|LVTTL*|0|12|SLOW|NONE**|||||NO|NONE|
P189|mem_data_io<0>|IOB|IO_VREF_0|OUTPUT|LVTTL*|0|12|SLOW|NONE**|||||NO|NONE|
P190|||GND|||||||||||||
P191||IOB|IO|UNUSED||0||||||||||
P192||IOB|IO|UNUSED||0||||||||||
P193||IOB|IO|UNUSED||0||||||||||
P194||IOB|IO|UNUSED||0||||||||||
P195||IOB|IO|UNUSED||0||||||||||
P196|||VCCINT||||||||2.5|||||
P197|||VCCO|||0|||||3.30|||||
P198|||GND|||||||||||||
P199||IOB|IO|UNUSED||0||||||||||
P200||IOB|IO_VREF_0|UNUSED||0||||||||||
P201||IOB|IO|UNUSED||0||||||||||
P202||IOB|IO|UNUSED||0||||||||||
P203||IOB|IO_VREF_0|UNUSED||0||||||||||
P204||IOB|IO|UNUSED||0||||||||||
P205||IOB|IO|UNUSED||0||||||||||
P206||IOB|IO|UNUSED||0||||||||||
P207|||TCK|||||||||||||
P208|||VCCO|||0|||||3.30|||||
 
-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
 
* Default value.
** This default Pullup/Pulldown value can be overridden in Bitgen.
****** Special VCCO requirements may apply. Please consult the device
family datasheet for specific guideline on VCCO requirements.
 
 
/syn/xilinx/logs/CC3_top_x_map.map
0,0 → 1,66
Release 10.1 Map K.31 (lin)
Xilinx Map Application Log File for Design 'CC3_top_x'
 
Design Information
------------------
Command Line : map -ise
/home/pacito/02_Elektronik/020_V6809/6809/xilinx/P6809/P6809.ise -intstyle ise
-p xc2s100-pq208-5 -cm area -pr off -k 4 -c 100 -tx off -o CC3_top_x_map.ncd
CC3_top_x.ngd CC3_top_x.pcf
Target Device : xc2s100
Target Package : pq208
Target Speed : -5
Mapper Version : spartan2 -- $Revision: 1.46 $
Mapped Date : Wed Dec 25 11:42:53 2013
 
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...
 
Design Summary
--------------
 
Design Summary:
Number of errors: 0
Number of warnings: 6
Logic Utilization:
Number of Slice Flip Flops: 301 out of 2,400 12%
Number of 4 input LUTs: 2,239 out of 2,400 93%
Logic Distribution:
Number of occupied Slices: 1,198 out of 1,200 99%
Number of Slices containing only related logic: 1,198 out of 1,198 100%
Number of Slices containing unrelated logic: 0 out of 1,198 0%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs: 2,291 out of 2,400 95%
Number used as logic: 2,239
Number used as a route-thru: 52
Number of bonded IOBs: 26 out of 140 18%
Number of Block RAMs: 1 out of 10 10%
Number of GCLKs: 1 out of 4 25%
Number of GCLKIOBs: 1 out of 4 25%
 
Peak Memory Usage: 148 MB
Total REAL time to MAP completion: 2 secs
Total CPU time to MAP completion: 2 secs
 
NOTES:
 
Related logic is defined as being logic that shares connectivity - e.g. two
LUTs are "related" if they share common inputs. When assembling slices,
Map gives priority to combine logic that is related. Doing so results in
the best timing performance.
 
Unrelated logic shares no connectivity. Map will only begin packing
unrelated logic into a slice once 99% of the slices are occupied through
related logic packing.
 
Note that once logic distribution reaches the 99% level through related
logic packing, this does not mean the device is completely utilized.
Unrelated logic packing will then begin, continuing until all usable LUTs
and FFs are occupied. Depending on your timing budget, increased levels of
unrelated logic packing may adversely affect the overall timing performance
of your design.
 
Mapping completed.
See MAP report file "CC3_top_x_map.mrp" for details.
/syn/xilinx/logs/CC3_top_x_map.mrp
0,0 → 1,193
Release 10.1 Map K.31 (lin)
Xilinx Mapping Report File for Design 'CC3_top_x'
 
Design Information
------------------
Command Line : map -ise
/home/pacito/02_Elektronik/020_V6809/6809/xilinx/P6809/P6809.ise -intstyle ise
-p xc2s100-pq208-5 -cm area -pr off -k 4 -c 100 -tx off -o CC3_top_x_map.ncd
CC3_top_x.ngd CC3_top_x.pcf
Target Device : xc2s100
Target Package : pq208
Target Speed : -5
Mapper Version : spartan2 -- $Revision: 1.46 $
Mapped Date : Wed Dec 25 11:42:53 2013
 
Design Summary
--------------
Number of errors: 0
Number of warnings: 6
Logic Utilization:
Number of Slice Flip Flops: 301 out of 2,400 12%
Number of 4 input LUTs: 2,239 out of 2,400 93%
Logic Distribution:
Number of occupied Slices: 1,198 out of 1,200 99%
Number of Slices containing only related logic: 1,198 out of 1,198 100%
Number of Slices containing unrelated logic: 0 out of 1,198 0%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs: 2,291 out of 2,400 95%
Number used as logic: 2,239
Number used as a route-thru: 52
Number of bonded IOBs: 26 out of 140 18%
Number of Block RAMs: 1 out of 10 10%
Number of GCLKs: 1 out of 4 25%
Number of GCLKIOBs: 1 out of 4 25%
 
Peak Memory Usage: 148 MB
Total REAL time to MAP completion: 2 secs
Total CPU time to MAP completion: 2 secs
 
NOTES:
 
Related logic is defined as being logic that shares connectivity - e.g. two
LUTs are "related" if they share common inputs. When assembling slices,
Map gives priority to combine logic that is related. Doing so results in
the best timing performance.
 
Unrelated logic shares no connectivity. Map will only begin packing
unrelated logic into a slice once 99% of the slices are occupied through
related logic packing.
 
Note that once logic distribution reaches the 99% level through related
logic packing, this does not mean the device is completely utilized.
Unrelated logic packing will then begin, continuing until all usable LUTs
and FFs are occupied. Depending on your timing budget, increased levels of
unrelated logic packing may adversely affect the overall timing performance
of your design.
 
Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information
Section 13 - Control Set Information
Section 14 - Utilization by Hierarchy
 
Section 1 - Errors
------------------
 
Section 2 - Warnings
--------------------
WARNING:Pack:266 - The function generator cpu/k_pp_active_reg_mux0000<3>11
failed to merge with F5 multiplexer cpu/state_mux0000<1>1_f5. There is a
conflict for the FXMUX. The design will exhibit suboptimal timing.
WARNING:Pack:249 - The following adjacent carry multiplexers occupy different
slice components. The resulting carry chain will have suboptimal timing.
cpu/alu/Mmult_mul16_w_Madd1_cy<8>
cpu/alu/Mmult_mul16_w_Madd1_cy<9>
WARNING:Pack:249 - The following adjacent carry multiplexers occupy different
slice components. The resulting carry chain will have suboptimal timing.
cpu/alu/Mmult_mul16_w_Madd_cy<7>
cpu/alu/Mmult_mul16_w_Madd_cy<8>
WARNING:Pack:249 - The following adjacent carry multiplexers occupy different
slice components. The resulting carry chain will have suboptimal timing.
cpu/alu/Mmult_mul16_w_Madd3_cy<11>
cpu/alu/Mmult_mul16_w_Madd3_cy<12>
WARNING:Pack:249 - The following adjacent carry multiplexers occupy different
slice components. The resulting carry chain will have suboptimal timing.
cpu/alu/Mmult_mul16_w_Madd5_cy<5>
cpu/alu/Mmult_mul16_w_Madd5_cy<6>
WARNING:Pack:249 - The following adjacent carry multiplexers occupy different
slice components. The resulting carry chain will have suboptimal timing.
cpu/alu/Mmult_mul16_w_Madd2_cy<7>
cpu/alu/Mmult_mul16_w_Madd2_cy<8>
 
Section 3 - Informational
-------------------------
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
rate limited output drivers. The delay on speed critical single ended outputs
can be dramatically reduced by designating them as fast outputs.
 
Section 4 - Removed Logic Summary
---------------------------------
2 block(s) optimized away
 
Section 5 - Removed Logic
-------------------------
 
Optimized Block(s):
TYPE BLOCK
GND XST_GND
VCC XST_VCC
 
To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.
 
Section 6 - IOB Properties
--------------------------
 
+------------------------------------------------------------------------------------------------------------------------+
| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB |
| | | | | Strength | Rate | | | Delay |
+------------------------------------------------------------------------------------------------------------------------+
| clk32_i | GCLKIOB | INPUT | LVTTL | | | | | |
| mem_addr_o<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| mem_addr_o<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| mem_addr_o<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| mem_addr_o<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| mem_addr_o<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| mem_addr_o<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| mem_addr_o<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| mem_addr_o<7> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| mem_addr_o<8> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| mem_addr_o<9> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| mem_addr_o<10> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| mem_addr_o<11> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| mem_addr_o<12> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| mem_addr_o<13> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| mem_addr_o<14> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| mem_addr_o<15> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| mem_data_io<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| mem_data_io<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| mem_data_io<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| mem_data_io<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| mem_data_io<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| mem_data_io<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| mem_data_io<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| mem_data_io<7> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| mem_oe_n | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| mem_we_n | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
+------------------------------------------------------------------------------------------------------------------------+
 
Section 7 - RPMs
----------------
 
Section 8 - Guide Report
------------------------
Guide not run on this design.
 
Section 9 - Area Group and Partition Summary
--------------------------------------------
 
Area Group Information
----------------------
 
No area groups were found in this design.
 
----------------------
 
Section 10 - Modular Design Summary
-----------------------------------
Modular Design not used for this design.
 
Section 11 - Timing Report
--------------------------
No timing report for this architecture.
 
Section 12 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings
 
Section 13 - Control Set Information
------------------------------------
No control set information for this architecture.
/syn/xilinx/CC3_top_x.v
0,0 → 1,108
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: R.A. Paz Schmidt
//
// Create Date: 11:12:42 12/23/2013
// Design Name:
// Module Name: CC3_top_x
// Project Name: MC6809/HD6309 compatible core
// Target Devices:
// Tool versions: Xilinx WebPack v 10.1 (for Spartan II)
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments: Distributed under the terms of the Lesser GPL, see LICENSE.TXT
//
//////////////////////////////////////////////////////////////////////////////////
module CC3_top_x(
input clk32_i,
output mem_we_n,
output mem_oe_n,
output [15:0] mem_addr_o,
inout [7:0] mem_data_io
);
 
wire cpu_clk;
wire cpu_reset_n;
wire cpu_nmi_n;
wire cpu_irq_n;
wire cpu_firq_n;
wire cpu_state_o;
wire cpu_we_o;
wire cpu_oe_o;
wire [15:0] cpu_addr_o;
wire [7:0] cpu_data_i;
wire [7:0] cpu_data_o;
 
assign mem_we_n = cpu_we_o;
assign mem_oe_n = cpu_oe_o;
assign mem_addr_o = cpu_addr_o;
assign mem_data_io = cpu_we_o ? cpu_data_o:cpu_data_i;
 
wire cpu_reset;
reg [3:0] reset_cnt;
 
assign cpu_reset = reset_cnt == 4'd14;
+always @(posedge clk32_i) + begin + if (reset_cnt != 4'd14) + reset_cnt <= reset_cnt + 4'h1; + end + + +MC6809_cpu cpu( + .cpu_clk(clk32_i), + .cpu_reset_n(cpu_reset), + .cpu_nmi_n(0), + .cpu_irq_n(0), + .cpu_firq_n(0), + .cpu_state_o(), + .cpu_we_o(cpu_we_o), + .cpu_oe_o(cpu_oe_o), + .cpu_addr_o(cpu_addr_o), + .cpu_data_i(cpu_data_i), + .cpu_data_o(cpu_data_o) + ); + + +`ifdef SPARTAN3 +RAMB16_S9_S9 bios2k(.DOA(cpu_data_i), .DOPA(), .ADDRA(cpu_addr_o), .CLKA(clk32_i), + .DIA(cpu_data_o), .DIPA(), .ENA(cpu_oe_o | cpu_we_o), .SSRA(1), .WEA(cpu_we_o), + .DOPB(), .DOB(), .ADDRB(0), .CLKB(clk32_i), .DIB(0), .DIPB(), .ENB(0), + .SSRB(0), .WEB(0)); +`else +RAMB4_S8 #( + // The following INIT_xx declarations specify the initial contents of the RAM + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000001086), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h00FF000000000000000000000000000000000000000000000000000000000000) + ) RAMB4_S8_inst ( + .DO(cpu_data_i), // 8-bit data output + .ADDR(cpu_addr_o), // 9-bit address input + .CLK(clk32_i), // Clock input + .DI(cpu_data_o), // 8-bit data input + .EN(cpu_oe_o | cpu_we_o), // RAM enable input + .RST(1'b0), // Synchronous reset input + .WE(cpu_we_o) // RAM write enable input + ); +`endif +endmodule

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