OpenCores
URL https://opencores.org/ocsvn/adv_debug_sys/adv_debug_sys/trunk

Subversion Repositories adv_debug_sys

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /adv_debug_sys
    from Rev 49 to Rev 50
    ↔ Reverse comparison
  •

Rev 49 → Rev 50

/trunk/Software/adv_jtag_bridge/or32_selftest.c
26,6 → 26,7
 
#include <stdio.h>
#include <stdlib.h> // for exit()
#include <stdint.h>
 
#include "or32_selftest.h"
#include "dbg_api.h"
145,7 → 146,7
 
void init_mc(void)
{
unsigned long insn;
uint32_t insn;
 
printf("Initialize Memory Controller (SDRAM)\n");
CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_BAR_0, FLASH_BAR_VAL & 0xffff0000));
179,7 → 180,7
CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_CCR_4, 0xc0bf0005));
CHECK(dbg_wb_read32(MC_BASE_ADDR+MC_CCR_4, &insn));
printf("expected %x, read %lx\n", 0xc0bf0005, insn);
printf("expected %x, read %x\n", 0xc0bf0005, insn);
}
 
 
196,14 → 197,14
 
int test_sdram(void)
{
unsigned long insn;
uint32_t insn;
unsigned long i;
unsigned long data4_out[0x08];
unsigned long data4_in[0x08];
unsigned short data2_out[0x10];
unsigned short data2_in[0x10];
unsigned char data1_out[0x20];
unsigned char data1_in[0x20];
uint32_t data4_out[0x08];
uint32_t data4_in[0x08];
uint16_t data2_out[0x10];
uint16_t data2_in[0x10];
uint8_t data1_out[0x20];
uint8_t data1_in[0x20];
printf("Start SDRAM WR\n");
for (i=0x10; i<(SDRAM_SIZE+SDRAM_BASE); i=i<<1) {
236,7 → 237,7
for (i=0; i<(0x20/4); i++) {
//printf("0x%x: 0x%x\n", SDRAM_BASE+(i*4), data_out[i]);
if (data4_in[i] != data4_out[i]) {
printf("SDRAM data differs. Expected: 0x%0lx, read: 0x%0lx\n", data4_in[i], data4_out[i]);
printf("SDRAM data differs. Expected: 0x%0x, read: 0x%0x\n", data4_in[i], data4_out[i]);
return APP_ERR_TEST_FAIL;
}
}
285,17 → 286,17
 
int test_sdram_2(void)
{
unsigned long insn;
uint32_t insn;
 
printf("SDRAM test 2: \n");
CHECK(dbg_wb_write32(SDRAM_BASE+0x00, 0x12345678));
CHECK(dbg_wb_read32(SDRAM_BASE+0x00, &insn));
printf("expected %x, read %lx\n", 0x12345678, insn);
printf("expected %x, read %x\n", 0x12345678, insn);
if (insn != 0x12345678) return APP_ERR_TEST_FAIL;
CHECK(dbg_wb_write32(SDRAM_BASE+0x0000, 0x11112222));
CHECK(dbg_wb_read32(SDRAM_BASE+0x0000, &insn));
printf("expected %x, read %lx\n", 0x11112222, insn);
printf("expected %x, read %x\n", 0x11112222, insn);
if (insn != 0x11112222) return APP_ERR_TEST_FAIL;
 
CHECK(dbg_wb_write32(SDRAM_BASE+0x0004, 0x33334444));
308,23 → 309,23
CHECK(dbg_wb_write32(SDRAM_BASE+0x0020, 0xdeadbeef));
CHECK(dbg_wb_read32(SDRAM_BASE+0x0000, &insn));
printf("expected %x, read %lx\n", 0x11112222, insn);
printf("expected %x, read %x\n", 0x11112222, insn);
CHECK(dbg_wb_read32(SDRAM_BASE+0x0004, &insn));
printf("expected %x, read %lx\n", 0x33334444, insn);
printf("expected %x, read %x\n", 0x33334444, insn);
CHECK(dbg_wb_read32(SDRAM_BASE+0x0008, &insn));
printf("expected %x, read %lx\n", 0x55556666, insn);
printf("expected %x, read %x\n", 0x55556666, insn);
CHECK(dbg_wb_read32(SDRAM_BASE+0x000c, &insn));
printf("expected %x, read %lx\n", 0x77778888, insn);
printf("expected %x, read %x\n", 0x77778888, insn);
CHECK(dbg_wb_read32(SDRAM_BASE+0x0010, &insn));
printf("expected %x, read %lx\n", 0x9999aaaa, insn);
printf("expected %x, read %x\n", 0x9999aaaa, insn);
CHECK(dbg_wb_read32(SDRAM_BASE+0x0014, &insn));
printf("expected %x, read %lx\n", 0xbbbbcccc, insn);
printf("expected %x, read %x\n", 0xbbbbcccc, insn);
CHECK(dbg_wb_read32(SDRAM_BASE+0x0018, &insn));
printf("expected %x, read %lx\n", 0xddddeeee, insn);
printf("expected %x, read %x\n", 0xddddeeee, insn);
CHECK(dbg_wb_read32(SDRAM_BASE+0x001c, &insn));
printf("expected %x, read %lx\n", 0xffff0000, insn);
printf("expected %x, read %x\n", 0xffff0000, insn);
CHECK(dbg_wb_read32(SDRAM_BASE+0x0020, &insn));
printf("expected %x, read %lx\n", 0xdeadbeef, insn);
printf("expected %x, read %x\n", 0xdeadbeef, insn);
if (insn != 0xdeadbeef) {
printf("SDRAM test 2 FAILED\n");
340,8 → 341,8
int test_sram(void)
{
//unsigned long insn;
unsigned long ins;
unsigned long insn[9];
uint32_t ins;
uint32_t insn[9];
insn[0] = 0x11112222;
insn[1] = 0x33334444;
insn[2] = 0x55556666;
367,23 → 368,23
 
CHECK(dbg_wb_read32(SRAM_BASE+0x0000, &ins));
printf("expected %x, read %lx\n", 0x11112222, ins);
printf("expected %x, read %x\n", 0x11112222, ins);
CHECK(dbg_wb_read32(SRAM_BASE+0x0004, &ins));
printf("expected %x, read %lx\n", 0x33334444, ins);
printf("expected %x, read %x\n", 0x33334444, ins);
CHECK(dbg_wb_read32(SRAM_BASE+0x0008, &ins));
printf("expected %x, read %lx\n", 0x55556666, ins);
printf("expected %x, read %x\n", 0x55556666, ins);
CHECK(dbg_wb_read32(SRAM_BASE+0x000c, &ins));
printf("expected %x, read %lx\n", 0x77778888, ins);
printf("expected %x, read %x\n", 0x77778888, ins);
CHECK(dbg_wb_read32(SRAM_BASE+0x0010, &ins));
printf("expected %x, read %lx\n", 0x9999aaaa, ins);
printf("expected %x, read %x\n", 0x9999aaaa, ins);
CHECK(dbg_wb_read32(SRAM_BASE+0x0014, &ins));
printf("expected %x, read %lx\n", 0xbbbbcccc, ins);
printf("expected %x, read %x\n", 0xbbbbcccc, ins);
CHECK(dbg_wb_read32(SRAM_BASE+0x0018, &ins));
printf("expected %x, read %lx\n", 0xddddeeee, ins);
printf("expected %x, read %x\n", 0xddddeeee, ins);
CHECK(dbg_wb_read32(SRAM_BASE+0x001c, &ins));
printf("expected %x, read %lx\n", 0xffff0000, ins);
printf("expected %x, read %x\n", 0xffff0000, ins);
CHECK(dbg_wb_read32(SRAM_BASE+0x0020, &ins));
printf("expected %x, read %lx\n", 0xdedababa, ins);
printf("expected %x, read %x\n", 0xdedababa, ins);
if (ins != 0xdedababa) {
printf("SRAM test failed!!!\n");
399,9 → 400,9
 
int test_or1k_cpu0(void)
{
unsigned long npc, ppc, r1, insn;
unsigned char stalled;
unsigned long result;
uint32_t npc, ppc, r1, insn;
uint8_t stalled;
uint32_t result;
int i;
 
printf("Testing CPU0 (or1k) - writing instructions\n");
433,7 → 434,7
CHECK(dbg_cpu0_read((0 << 11) + 16, &npc)); /* Read NPC */
CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc)); /* Read PPC */
CHECK(dbg_cpu0_read(0x401, &r1)); /* Read R1 */
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
printf("Read npc = %.8x ppc = %.8x r1 = %.8x\n", npc, ppc, r1);
printf("Expected npc = %.8x ppc = %.8x r1 = %.8x\n", 0x00000010, 0x00000028, 5);
result = npc + ppc + r1;
446,7 → 447,7
CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc)); // Read PPC
CHECK(dbg_cpu0_read(0x401, &r1)); // Read R1
CHECK(dbg_wb_write32(SDRAM_BASE + 0x28, insn)); // Set back original insn
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
printf("Read npc = %.8x ppc = %.8x r1 = %.8x\n", npc, ppc, r1);
printf("Expected npc = %.8x ppc = %.8x r1 = %.8x\n", 0x00000010, 0x00000028, 8);
result = npc + ppc + r1 + result;
 
459,7 → 460,7
CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc)); // Read PPC
CHECK(dbg_cpu0_read(0x401, &r1)); // Read R1
CHECK(dbg_wb_write32(SDRAM_BASE + 0x24, insn)); // Set back original insn
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
printf("Read npc = %.8x ppc = %.8x r1 = %.8x\n", npc, ppc, r1);
printf("Expected npc = %.8x ppc = %.8x r1 = %.8x\n", 0x00000028, 0x00000024, 11);
result = npc + ppc + r1 + result;
472,7 → 473,7
CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc)); /* Read PPC */
CHECK(dbg_cpu0_read(0x401, &r1)); /* Read R1 */
CHECK(dbg_wb_write32(SDRAM_BASE + 0x20, insn)); /* Set back original insn */
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
printf("Read npc = %.8x ppc = %.8x r1 = %.8x\n", npc, ppc, r1);
printf("Expected npc = %.8x ppc = %.8x r1 = %.8x\n", 0x00000024, 0x00000020, 24);
result = npc + ppc + r1 + result;
 
485,7 → 486,7
CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc)); /* Read PPC */
CHECK(dbg_cpu0_read(0x401, &r1)); /* Read R1 */
CHECK(dbg_wb_write32(SDRAM_BASE + 0x1c, insn)); /* Set back original insn */
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
printf("Read npc = %.8x ppc = %.8x r1 = %.8x\n", npc, ppc, r1);
printf("Expected npc = %.8x ppc = %.8x r1 = %.8x\n", 0x00000020, 0x0000001c, 49);
result = npc + ppc + r1 + result;
 
498,7 → 499,7
CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc)); /* Read PPC */
CHECK(dbg_cpu0_read(0x401, &r1)); /* Read R1 */
CHECK(dbg_wb_write32(SDRAM_BASE + 0x20, insn)); /* Set back original insn */
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
printf("Read npc = %.8x ppc = %.8x r1 = %.8x\n", npc, ppc, r1);
printf("Expected npc = %.8x ppc = %.8x r1 = %.8x\n", 0x00000024, 0x00000020, 50);
result = npc + ppc + r1 + result;
 
511,7 → 512,7
CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc)); /* Read PPC */
CHECK(dbg_cpu0_read(0x401, &r1)); /* Read R1 */
CHECK(dbg_wb_write32(SDRAM_BASE + 0x10, insn)); /* Set back original insn */
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
printf("Read npc = %.8x ppc = %.8x r1 = %.8x\n", npc, ppc, r1);
printf("Expected npc = %.8x ppc = %.8x r1 = %.8x\n", 0x00000014, 0x00000010, 99);
result = npc + ppc + r1 + result;
 
525,7 → 526,7
CHECK(dbg_cpu0_read((0 << 11) + 16, &npc)); /* Read NPC */
CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc)); /* Read PPC */
CHECK(dbg_cpu0_read(0x401, &r1)); /* Read R1 */
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
printf("Read npc = %.8x ppc = %.8x r1 = %.8x\n", npc, ppc, r1);
printf("Expected npc = %.8x ppc = %.8x r1 = %.8x\n", 0x00000028, 0x00000024, 101);
result = npc + ppc + r1 + result;
 
539,10 → 540,10
CHECK(dbg_cpu0_read((0 << 11) + 16, &npc)); /* Read NPC */
CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc)); /* Read PPC */
CHECK(dbg_cpu0_read(0x401, &r1)); /* Read R1 */
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
printf("Read npc = %.8x ppc = %.8x r1 = %.8x\n", npc, ppc, r1);
printf("Expected npc = %.8x ppc = %.8x r1 = %.8x\n", 0x00000010, 0x00000028, 201);
result = npc + ppc + r1 + result;
printf("result = %.8lx\n", result ^ 0xdeaddae1);
printf("result = %.8x\n", result ^ 0xdeaddae1);
 
if((result ^ 0xdeaddae1) != 0xdeaddead)
return APP_ERR_TEST_FAIL;
/trunk/Software/adv_jtag_bridge/rsp-server.c
378,7 → 378,8
{
struct pollfd fds[2]; /* The FD to poll for */
char monitor_status;
unsigned long drrval;
uint32_t drrval;
uint32_t ppcval;
 
/* Give up if no RSP server port (this should not occur) */
if (-1 == rsp.server_fd)
496,7 → 497,6
if (rsp.client_waiting)
{
// Read the PPC
unsigned long ppcval;
dbg_cpu0_read(SPR_PPC, &ppcval);
if ((TARGET_SIGNAL_TRAP == rsp.sigval) &&
602,7 → 602,7
int fd; /* The client FD */
int flags; /* fcntl () flags */
int optval; /* Option value for setsockopt () */
unsigned long tmp;
uint32_t tmp;
 
/* Get the client FD */
len = sizeof (sock_addr);
1730,7 → 1730,7
static void
rsp_continue_generic (unsigned long int except)
{
unsigned long tmp;
uint32_t tmp;
 
/* Clear Debug Reason Register and watchpoint break generation in Debug Mode
Register 2 */
1771,8 → 1771,8
{
struct rsp_buf buf; /* Buffer for the reply */
int r; /* Register index */
unsigned long regbuf[MAX_GPRS];
unsigned int errcode = APP_ERR_NONE;
uint32_t regbuf[MAX_GPRS];
unsigned int errcode = APP_ERR_NONE;
 
// Read all the GPRs in a single burst, for efficiency
errcode = dbg_cpu0_read_block(SPR_GPR_BASE, regbuf, MAX_GPRS);
1801,22 → 1801,6
 
//fprintf(stderr, "Read SPRs: 0x%08X, 0x%08X, 0x%08X\n", regbuf[0], regbuf[1], regbuf[2]);
 
/*
dbg_cpu0_read(SPR_PPC, &tmp);
reg2hex(tmp, &(buf.data[PPC_REGNUM * 8]));
 
if(use_cached_npc == 1) { // Hackery to work around CPU hardware quirk
tmp = cached_npc;
}
else {
dbg_cpu0_read(SPR_NPC, &tmp);
}
reg2hex(tmp, &(buf.data[NPC_REGNUM * 8]));
 
dbg_cpu0_read(SPR_SR, &tmp);
reg2hex(tmp, &(buf.data[SR_REGNUM * 8]));
*/
 
if(errcode == APP_ERR_NONE) {
/* Finalize the packet and send it */
buf.data[NUM_REGS * 8] = 0;
1850,8 → 1834,8
rsp_write_all_regs (struct rsp_buf *buf)
{
int r; /* Register index */
unsigned long regbuf[MAX_GPRS];
unsigned int errcode;
uint32_t regbuf[MAX_GPRS];
unsigned int errcode;
 
/* The GPRs */
for (r = 0; r < MAX_GPRS; r++)
2051,7 → 2035,7
rsp_read_reg (struct rsp_buf *buf)
{
unsigned int regnum;
unsigned long tmp;
uint32_t tmp;
unsigned int errcode = APP_ERR_NONE;
 
/* Break out the fields from the data */
2283,8 → 2267,8
static void
rsp_command (struct rsp_buf *buf)
{
char cmd[GDB_BUF_MAX];
unsigned long tmp;
char cmd[GDB_BUF_MAX];
uint32_t tmp;
 
hex2ascii (cmd, &(buf->data[strlen ("qRcmd,")]));
 
2313,7 → 2297,7
 
/* Construct the reply */
dbg_cpu0_read(regno, &tmp); // TODO Check return value of all hardware accesses
sprintf (cmd, "%8lx", tmp);
sprintf (cmd, "%8x", tmp);
ascii2hex (buf->data, cmd);
buf->len = strlen (buf->data);
put_packet (buf);
2461,7 → 2445,7
static void
rsp_step_generic (unsigned long int except)
{
unsigned long tmp;
uint32_t tmp;
 
/* Clear Debug Reason Register and watchpoint break generation in Debug Mode
Register 2 */
2661,13 → 2645,13
rsp_remove_matchpoint (struct rsp_buf *buf)
{
enum mp_type type; /* What sort of matchpoint */
unsigned long int addr; /* Address specified */
uint32_t addr; /* Address specified */
int len; /* Matchpoint length (not used) */
struct mp_entry *mpe; /* Info about the replaced instr */
unsigned long instbuf[1];
uint32_t instbuf[1];
 
/* Break out the instruction */
if (3 != sscanf (buf->data, "z%1d,%lx,%1d", (int *)&type, &addr, &len))
if (3 != sscanf (buf->data, "z%1d,%x,%1d", (int *)&type, &addr, &len))
{
fprintf (stderr, "Warning: RSP matchpoint deletion request not "
"recognized: ignored\n");
2744,12 → 2728,12
rsp_insert_matchpoint (struct rsp_buf *buf)
{
enum mp_type type; /* What sort of matchpoint */
unsigned long int addr; /* Address specified */
uint32_t addr; /* Address specified */
int len; /* Matchpoint length (not used) */
unsigned long instbuf[1];
uint32_t instbuf[1];
 
/* Break out the instruction */
if (3 != sscanf (buf->data, "Z%1d,%lx,%1d", (int *)&type, &addr, &len))
if (3 != sscanf (buf->data, "Z%1d,%x,%1d", (int *)&type, &addr, &len))
{
fprintf (stderr, "Warning: RSP matchpoint insertion request not "
"recognized: ignored\n");
/trunk/Software/adv_jtag_bridge/dbg_api.c
48,7 → 48,7
pthread_mutex_t dbg_access_mutex = PTHREAD_MUTEX_INITIALIZER;
 
/* read a word from wishbone */
int dbg_wb_read32(unsigned long adr, unsigned long *data) {
int dbg_wb_read32(uint32_t adr, uint32_t *data) {
int err;
pthread_mutex_lock(&dbg_access_mutex);
 
75,7 → 75,7
}
 
/* write a word to wishbone */
int dbg_wb_write32(unsigned long adr, unsigned long data) {
int dbg_wb_write32(uint32_t adr, uint32_t data) {
int err;
pthread_mutex_lock(&dbg_access_mutex);
 
103,7 → 103,7
 
// write a word to wishbone
// Never actually called from the GDB interface
int dbg_wb_write16(unsigned long adr, uint16_t data) {
int dbg_wb_write16(uint32_t adr, uint16_t data) {
int err;
pthread_mutex_lock(&dbg_access_mutex);
 
131,7 → 131,7
 
// write a word to wishbone
// Never actually called from the GDB interface
int dbg_wb_write8(unsigned long adr, uint8_t data) {
int dbg_wb_write8(uint32_t adr, uint8_t data) {
int err;
pthread_mutex_lock(&dbg_access_mutex);
 
157,7 → 157,7
}
 
 
int dbg_wb_read_block32(unsigned long adr, unsigned long *data, int len) {
int dbg_wb_read_block32(uint32_t adr, uint32_t *data, int len) {
int err;
 
if(!len)
190,7 → 190,7
 
 
// Never actually called from the GDB interface
int dbg_wb_read_block16(unsigned long adr, uint16_t *data, int len) {
int dbg_wb_read_block16(uint32_t adr, uint16_t *data, int len) {
int err;
 
if(!len)
222,7 → 222,7
}
 
// Never actually called from the GDB interface
int dbg_wb_read_block8(unsigned long adr, uint8_t *data, int len) {
int dbg_wb_read_block8(uint32_t adr, uint8_t *data, int len) {
int err;
 
if(!len)
252,7 → 252,7
 
 
// write a block to wishbone
int dbg_wb_write_block32(unsigned long adr, unsigned long *data, int len) {
int dbg_wb_write_block32(uint32_t adr, uint32_t *data, int len) {
int err;
 
if(!len)
286,7 → 286,7
 
// write a block to wishbone
// Never actually called from the GDB interface
int dbg_wb_write_block16(unsigned long adr, uint16_t *data, int len) {
int dbg_wb_write_block16(uint32_t adr, uint16_t *data, int len) {
int err;
 
if(!len)
318,7 → 318,7
}
 
// write a block to wishbone
int dbg_wb_write_block8(unsigned long adr, uint8_t *data, int len) {
int dbg_wb_write_block8(uint32_t adr, uint8_t *data, int len) {
int err;
 
if(!len)
348,7 → 348,7
 
 
/* read a register from cpu0. This is assumed to be an OR32 CPU, with 32-bit regs. */
int dbg_cpu0_read(unsigned long adr, unsigned long *data) {
int dbg_cpu0_read(uint32_t adr, uint32_t *data) {
int err;
pthread_mutex_lock(&dbg_access_mutex);
 
376,7 → 376,7
}
 
/* read multiple registers from cpu0. This is assumed to be an OR32 CPU, with 32-bit regs. */
int dbg_cpu0_read_block(unsigned long adr, unsigned long *data, int count) {
int dbg_cpu0_read_block(uint32_t adr, uint32_t *data, int count) {
int err;
 
if(DEBUG_HARDWARE == DBG_HW_ADVANCED)
407,7 → 407,7
}
 
/* write a cpu register to cpu0. This is assumed to be an OR32 CPU, with 32-bit regs. */
int dbg_cpu0_write(unsigned long adr, unsigned long data) {
int dbg_cpu0_write(uint32_t adr, uint32_t data) {
int err;
pthread_mutex_lock(&dbg_access_mutex);
 
435,7 → 435,7
}
 
/* write multiple cpu registers to cpu0. This is assumed to be an OR32 CPU, with 32-bit regs. */
int dbg_cpu0_write_block(unsigned long adr, unsigned long *data, int count) {
int dbg_cpu0_write_block(uint32_t adr, uint32_t *data, int count) {
int err;
if(DEBUG_HARDWARE == DBG_HW_ADVANCED)
468,7 → 468,7
/* write a debug unit cpu module register
* Since OR32 debug module has only 1 register,
* adr is ignored (for now) */
int dbg_cpu0_write_ctrl(unsigned long adr, unsigned char data) {
int dbg_cpu0_write_ctrl(uint32_t adr, uint8_t data) {
int err = APP_ERR_NONE;
uint32_t dataword = data;
pthread_mutex_lock(&dbg_access_mutex);
503,7 → 503,7
/* read a register from cpu module of the debug unit.
* Currently, there is only 1 register, so we do not need to select it, adr is ignored
*/
int dbg_cpu0_read_ctrl(unsigned long adr, unsigned char *data) {
int dbg_cpu0_read_ctrl(uint32_t adr, uint8_t *data) {
int err = APP_ERR_NONE;
uint32_t dataword;
pthread_mutex_lock(&dbg_access_mutex);
541,7 → 541,7
// CPU1 Functions. Note that 2 CPUs are not currently supported by GDB, so these are never actually
// called from the GDB interface. They are included for completeness and future use.
// read a register from cpu1
int dbg_cpu1_read(unsigned long adr, unsigned long *data)
int dbg_cpu1_read(uint32_t adr, uint32_t *data)
{
int err;
pthread_mutex_lock(&dbg_access_mutex);
570,7 → 570,7
 
 
// write a cpu register
int dbg_cpu1_write(unsigned long adr, unsigned long data)
int dbg_cpu1_write(uint32_t adr, uint32_t data)
{
int err;
pthread_mutex_lock(&dbg_access_mutex);
599,7 → 599,7
 
 
// write a debug unit cpu module register
int dbg_cpu1_write_ctrl(unsigned long adr, unsigned char data) {
int dbg_cpu1_write_ctrl(uint32_t adr, uint8_t data) {
int err;
uint32_t dataword = data;
pthread_mutex_lock(&dbg_access_mutex);
631,7 → 631,7
 
 
// read a debug unit cpu module register
int dbg_cpu1_read_ctrl(unsigned long adr, unsigned char *data) {
int dbg_cpu1_read_ctrl(uint32_t adr, uint8_t *data) {
int err;
uint32_t dataword;
pthread_mutex_lock(&dbg_access_mutex);
666,7 → 666,7
return err;
}
 
int dbg_serial_sndrcv(unsigned int *bytes_to_send, const char *data_to_send, unsigned int *bytes_received, char *data_received) {
int dbg_serial_sndrcv(unsigned int *bytes_to_send, const uint8_t *data_to_send, unsigned int *bytes_received, uint8_t *data_received) {
int err;
 
pthread_mutex_lock(&dbg_access_mutex);
/trunk/Software/adv_jtag_bridge/dbg_api.h
7,26 → 7,26
 
 
// API for GDB
int dbg_wb_read32(unsigned long adr, unsigned long *data);
int dbg_wb_write32(unsigned long adr, unsigned long data);
int dbg_wb_write16(unsigned long adr, uint16_t data);
int dbg_wb_write8(unsigned long adr, uint8_t data);
int dbg_wb_read_block32(unsigned long adr, unsigned long *data, int len);
int dbg_wb_read_block16(unsigned long adr, uint16_t *data, int len);
int dbg_wb_read_block8(unsigned long adr, uint8_t *data, int len);
int dbg_wb_write_block32(unsigned long adr, unsigned long *data, int len);
int dbg_wb_write_block16(unsigned long adr, uint16_t *data, int len);
int dbg_wb_write_block8(unsigned long adr, uint8_t *data, int len);
int dbg_cpu0_read(unsigned long adr, unsigned long *data);
int dbg_cpu0_read_block(unsigned long adr, unsigned long *data, int count);
int dbg_cpu0_write(unsigned long adr, unsigned long data);
int dbg_cpu0_write_block(unsigned long adr, unsigned long *data, int count);
int dbg_cpu0_write_ctrl(unsigned long adr, unsigned char data);
int dbg_cpu0_read_ctrl(unsigned long adr, unsigned char *data);
//int dbg_cpu1_read(unsigned long adr, unsigned long *data);
//int dbg_cpu1_write(unsigned long adr, unsigned long data);
//int dbg_cpu1_write_reg(unsigned long adr, unsigned char data);
//int dbg_cpu1_read_ctrl(unsigned long adr, unsigned char *data);
int dbg_serial_sndrcv(unsigned int *bytes_to_send, const char *data_to_send, unsigned int *bytes_received, char *data_received);
int dbg_wb_read32(uint32_t adr, uint32_t *data);
int dbg_wb_write32(uint32_t adr, uint32_t data);
int dbg_wb_write16(uint32_t adr, uint16_t data);
int dbg_wb_write8(uint32_t adr, uint8_t data);
int dbg_wb_read_block32(uint32_t adr, uint32_t *data, int len);
int dbg_wb_read_block16(uint32_t adr, uint16_t *data, int len);
int dbg_wb_read_block8(uint32_t adr, uint8_t *data, int len);
int dbg_wb_write_block32(uint32_t adr, uint32_t *data, int len);
int dbg_wb_write_block16(uint32_t adr, uint16_t *data, int len);
int dbg_wb_write_block8(uint32_t adr, uint8_t *data, int len);
int dbg_cpu0_read(uint32_t adr, uint32_t *data);
int dbg_cpu0_read_block(uint32_t adr, uint32_t *data, int count);
int dbg_cpu0_write(uint32_t adr, uint32_t data);
int dbg_cpu0_write_block(uint32_t adr, uint32_t *data, int count);
int dbg_cpu0_write_ctrl(uint32_t adr, uint8_t data);
int dbg_cpu0_read_ctrl(uint32_t adr, uint8_t *data);
//int dbg_cpu1_read(uint32_t adr, uint32_t *data);
//int dbg_cpu1_write(uint32_t adr, uint32_t data);
//int dbg_cpu1_write_reg(uint32_t adr, uint8_t data);
//int dbg_cpu1_read_ctrl(uint32_t adr, uint8_t *data);
int dbg_serial_sndrcv(unsigned int *bytes_to_send, const uint8_t *data_to_send, unsigned int *bytes_received, uint8_t *data_received);
 
#endif

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