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/rtl/subsh.vhdl
0,0 → 1,103
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2001, 2002 Authors ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http:--www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
------------------------------------------------------
-- Project: AESFast
-- Author: Subhasis
-- Last Modified: 20/03/10
-- Email: subhasis256@gmail.com
------------------------------------------------------
--
-- Description: The Sbox and Shiftrows step
-- Ports:
-- clk: System Clock
-- blockin: Input state block
-- fc3: See keysched1 for explanation
-- c0: See keysched1 for explanation
-- c1: See keysched1 for explanation
-- c2: See keysched1 for explanation
-- c3: See keysched1 for explanation
-- nextkey: Roundkey for next round
-- blockout: output state block
------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
 
library work;
use work.aes_pkg.all;
 
entity sboxshr is
port(
clk: in std_logic;
blockin: in datablock;
fc3: in blockcol;
c0: in blockcol;
c1: in blockcol;
c2: in blockcol;
c3: in blockcol;
nextkey: out datablock;
blockout: out datablock
);
end sboxshr;
 
architecture rtl of sboxshr is
component sbox is
port(
clk: in std_logic;
bytein: in std_logic_vector(7 downto 0);
byteout: out std_logic_vector(7 downto 0)
);
end component;
begin
-- The sbox, the output going to the appropriate state byte after shiftrows
g0: for i in 3 downto 0 generate
g1: for j in 3 downto 0 generate
sub: sbox port map(
clk => clk,
bytein => blockin(i,j),
byteout => blockout(i,(j-i) mod 4)
);
end generate;
end generate;
process(clk)
begin
if(rising_edge(clk)) then
-- col0 of nextkey = fc3 xor col0
-- col1 of nextkey = fc3 xor col0 xor col1
-- col2 of nextkey = fc3 xor col0 xor col1 xor col2
-- col3 of nextkey = fc3 xor col0 xor col1 xor col2 xor col3
genkey: for j in 3 downto 0 loop
nextkey(j, 0) <= fc3(j) xor c0(j);
nextkey(j, 1) <= fc3(j) xor c1(j);
nextkey(j, 2) <= fc3(j) xor c2(j);
nextkey(j, 3) <= fc3(j) xor c3(j);
end loop;
end if;
end process;
end rtl;
/rtl/aes.vhdl
0,0 → 1,108
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2001, 2002 Authors ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http:--www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
------------------------------------------------------
-- Project: AESFast
-- Author: Subhasis
-- Last Modified: 20/03/10
-- Email: subhasis256@gmail.com
------------------------------------------------------
--
-- Description: The Overall Processor
-- Ports:
-- clk: System Clock
-- plaintext: Input Plaintext Blocks three at a time
-- keyblock: Input Key Blocks three at a time
-- ciphertext: Output Cipher Block
------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
 
library work;
use work.aes_pkg.all;
 
entity aes is
port(
clk: in std_logic;
start: in std_logic;
plaintext: in datablock;
keyblock: in datablock;
done: out std_logic;
ciphertext: out datablock
);
end aes;
 
architecture rtl of aes is
component aes_proc is
port(
clk: in std_logic;
plaintext: in datablock;
keyblock: in datablock;
rcon: in std_logic_vector(7 downto 0);
inmux: in std_logic;
final: in std_logic;
op_en: in std_logic;
ciphertext: out datablock
);
end component;
 
component aes_con is
port(
clk: in std_logic;
start: in std_logic;
done: out std_logic;
op_en: out std_logic;
inmux: out std_logic;
final: out std_logic;
rcon: out std_logic_vector(7 downto 0)
);
end component;
signal inmux, op_en, final: std_logic;
signal rcon: std_logic_vector(7 downto 0);
begin
proc0: aes_proc port map(
clk => clk,
plaintext => plaintext,
keyblock => keyblock,
rcon => rcon,
inmux => inmux,
final => final,
op_en => op_en,
ciphertext => ciphertext
);
con0: aes_con port map(
clk => clk,
start => start,
done => done,
op_en => op_en,
inmux => inmux,
final => final,
rcon => rcon
);
end rtl;
/rtl/aes_pkg.vhdl
0,0 → 1,50
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2001, 2002 Authors ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http:--www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
------------------------------------------------------
-- Project: AESFast
-- Author: Subhasis
-- Last Modified: 20/03/10
-- Email: subhasis256@gmail.com
------------------------------------------------------
-- Common library file containing common data path definitions
------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
 
package aes_pkg is
-- A column of 4 bytes
type blockcol is array(3 downto 0) of std_logic_vector(7 downto 0);
-- A datablock of 16 bytes
type datablock is array(3 downto 0, 3 downto 0) of std_logic_vector(7 downto 0);
-- Vector of columns
type colnet is array(natural range<>) of blockcol;
-- Vector of blocks
type datanet is array(natural range<>) of datablock;
-- the 10 rcon bytes
type rconarr is array(9 downto 0) of std_logic_vector(7 downto 0);
end package aes_pkg;
/rtl/aes_proc.vhdl
0,0 → 1,174
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2001, 2002 Authors ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http:--www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
------------------------------------------------------
-- Project: AESFast
-- Author: Subhasis
-- Last Modified: 20/03/10
-- Email: subhasis256@gmail.com
------------------------------------------------------
--
-- Description: The Datapath
-- Ports:
-- clk: System Clock
-- plaintext: Input Plaintext Blocks three at a time
-- keyblock: Input Key Blocks three at a time
-- ciphertext: Output Cipher Block
------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
 
library work;
use work.aes_pkg.all;
 
entity aes_proc is
port(
clk: in std_logic;
plaintext: in datablock;
keyblock: in datablock;
ciphertext: out datablock
);
end aes_proc;
 
architecture rtl of aes_proc is
constant rcon: rconarr := (X"36", X"1b", X"80", X"40", X"20", X"10", X"08", X"04", X"02", X"01");
signal fc3, c0, c1, c2, c3: colnet(9 downto 0);
signal textnet_a_s, textnet_s_m, textnet_m_a: datanet(9 downto 0);
signal key_m, key_s: datanet(9 downto 0);
signal textnet_s_a: datablock;
 
component sboxshr is
port(
clk: in std_logic;
blockin: in datablock;
fc3: in blockcol;
c0: in blockcol;
c1: in blockcol;
c2: in blockcol;
c3: in blockcol;
nextkey: out datablock;
blockout: out datablock
);
end component;
component colmix is
port(
clk: in std_logic;
datain: in datablock;
inrkey: in datablock;
outrkey: out datablock;
dataout: out datablock
);
end component;
component addkey is
port(
clk: in std_logic;
roundkey: in datablock;
datain: in datablock;
rcon: in std_logic_vector(7 downto 0);
dataout: out datablock;
fc3: out blockcol;
c0: out blockcol;
c1: out blockcol;
c2: out blockcol;
c3: out blockcol
);
end component;
begin
key_m(0) <= keyblock;
textnet_m_a(0) <= plaintext;
-------------------------------------------------------
-- Instead of the conventional order of
-- Addkey -> (Sbox -> Mixcol -> Addkey) ... 9 times
-- -> Sbox -> Addkey, we code the design as
-- (Addkey -> Sbox -> Mixcol) ... 9 times -> Addkey ->
-- Sbox -> Addkey
-------------------------------------------------------
proc: for i in 8 downto 0 generate
add: addkey port map(
clk => clk,
roundkey => key_m(i),
datain => textnet_m_a(i),
rcon => rcon(i),
dataout => textnet_a_s(i),
fc3 => fc3(i),
c0 => c0(i),
c1 => c1(i),
c2 => c2(i),
c3 => c3(i)
);
sbox: sboxshr port map(
clk => clk,
blockin => textnet_a_s(i),
fc3 => fc3(i),
c0 => c0(i),
c1 => c1(i),
c2 => c2(i),
c3 => c3(i),
nextkey => key_s(i),
blockout => textnet_s_m(i)
);
mix: colmix port map(
clk => clk,
datain => textnet_s_m(i),
inrkey => key_s(i),
outrkey => key_m(i+1),
dataout => textnet_m_a(i+1)
);
end generate;
add_f_1: addkey port map(
clk => clk,
roundkey => key_m(9),
datain => textnet_m_a(9),
rcon => rcon(9),
dataout => textnet_a_s(9),
fc3 => fc3(9),
c0 => c0(9),
c1 => c1(9),
c2 => c2(9),
c3 => c3(9)
);
sbox_f_1: sboxshr port map(
clk => clk,
blockin => textnet_a_s(9),
fc3 => fc3(9),
c0 => c0(9),
c1 => c1(9),
c2 => c2(9),
c3 => c3(9),
nextkey => key_s(9),
blockout => textnet_s_a
);
add_f: addkey port map(
clk => clk,
roundkey => key_s(9),
datain => textnet_s_a,
rcon => X"00",
dataout => ciphertext
);
end rtl;
/rtl/colmix.vhdl
0,0 → 1,98
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2001, 2002 Authors ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http:--www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
------------------------------------------------------
-- Project: AESFast
-- Author: Subhasis
-- Last Modified: 20/03/10
-- Email: subhasis256@gmail.com
------------------------------------------------------
--
-- Description: The MixColumns step
-- Ports:
-- clk: System Clock
-- datain: Input State block
-- inrkey: Input round key for passing on
-- to the next stage, i.e. Addkey
-- outrkey: Output round key to next stage
-- dataout: Output state block
------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
 
library work;
use work.aes_pkg.all;
 
entity colmix is
port(
clk: in std_logic;
datain: in datablock;
inrkey: in datablock;
outrkey: out datablock;
dataout: out datablock
);
end colmix;
 
architecture rtl of colmix is
component mixcol is
port(
clk: in std_logic;
in0: in std_logic_vector(7 downto 0);
in1: in std_logic_vector(7 downto 0);
in2: in std_logic_vector(7 downto 0);
in3: in std_logic_vector(7 downto 0);
out0: out std_logic_vector(7 downto 0);
out1: out std_logic_vector(7 downto 0);
out2: out std_logic_vector(7 downto 0);
out3: out std_logic_vector(7 downto 0)
);
end component;
 
begin
-- Do the mixcol operation on all the 4 columns
g0: for i in 3 downto 0 generate
mix: mixcol port map(
clk => clk,
in0 => datain(0, i),
in1 => datain(1, i),
in2 => datain(2, i),
in3 => datain(3, i),
out0 => dataout(0, i),
out1 => dataout(1, i),
out2 => dataout(2, i),
out3 => dataout(3, i)
);
end generate;
process(clk)
begin
if(rising_edge(clk)) then
outrkey <= inrkey;
end if;
end process;
end rtl;
/rtl/mixcol.vhdl
0,0 → 1,120
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2001, 2002 Authors ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http:--www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
------------------------------------------------------
-- Project: AESFast
-- Author: Subhasis
-- Last Modified: 20/03/10
-- Email: subhasis256@gmail.com
------------------------------------------------------
--
-- Description: The MixColumns operation
-- Ports:
-- clk: System Clock
-- in0: Byte 0 of a column
-- in1: Byte 1 of a column
-- in2: Byte 2 of a column
-- in3: Byte 3 of a column
-- out0: Byte 0 of output column
-- out1: Byte 1 of output column
-- out2: Byte 2 of output column
-- out3: Byte 3 of output column
-- keyblock: Input Key Blocks three at a time
-- ciphertext: Output Cipher Block
------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
 
library work;
use work.aes_pkg.all;
 
entity mixcol is
port(
clk: in std_logic;
in0: in std_logic_vector(7 downto 0);
in1: in std_logic_vector(7 downto 0);
in2: in std_logic_vector(7 downto 0);
in3: in std_logic_vector(7 downto 0);
out0: out std_logic_vector(7 downto 0);
out1: out std_logic_vector(7 downto 0);
out2: out std_logic_vector(7 downto 0);
out3: out std_logic_vector(7 downto 0)
);
end mixcol;
 
architecture rtl of mixcol is
signal d0, d1, d2, d3: std_logic_vector(7 downto 0);
signal t0, t1, t2, t3: std_logic_vector(7 downto 0);
signal sh0, sh1, sh2, sh3: std_logic_vector(7 downto 0);
signal xored: std_logic_vector(7 downto 0);
 
begin
sh0(0) <= '0';
sh1(0) <= '0';
sh2(0) <= '0';
sh3(0) <= '0';
-----------------------------------------------------
-- In GF(2^8) 2*x = (x << 1) xor 0x1b if x(7) = '1'
-- (x << 1) else
-- This just left shifts each byte by 1.
shift: for i in 7 downto 1 generate
sh0(i) <= in0(i-1);
sh1(i) <= in1(i-1);
sh2(i) <= in2(i-1);
sh3(i) <= in3(i-1);
end generate;
-- Conditional XOR'ing
d0 <= sh0 xor X"1b" when in0(7) = '1' else
sh0;
d1 <= sh1 xor X"1b" when in1(7) = '1' else
sh1;
d2 <= sh2 xor X"1b" when in2(7) = '1' else
sh2;
d3 <= sh3 xor X"1b" when in3(7) = '1' else
sh3;
----------------------------------------------------
-- 3*x = 2*x xor x
----------------------------------------------------
t0 <= d0 xor in0;
t1 <= d1 xor in1;
t2 <= d2 xor in2;
t3 <= d3 xor in3;
xored <= in0 xor in1 xor in2 xor in3;
process(clk)
begin
if(rising_edge(clk)) then
out0 <= xored xor t0 xor d1;
out1 <= xored xor t1 xor d2;
out2 <= xored xor t2 xor d3;
out3 <= xored xor t3 xor d0;
end if;
end process;
end rtl;
/rtl/sbox.vhdl
0,0 → 1,89
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2001, 2002 Authors ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http:--www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
------------------------------------------------------
-- Project: AESFast
-- Author: Subhasis
-- Last Modified: 20/03/10
-- Email: subhasis256@gmail.com
------------------------------------------------------
--
-- Description: The Datapath
-- Ports:
-- clk: System Clock
-- plaintext: Input Plaintext Blocks three at a time
-- keyblock: Input Key Blocks three at a time
-- rcon: The rcon byte corresponding to the current stage
-- inmux: Control Signal to determine whether take input
-- op_en: Control Signal to generate o/p
-- ciphertext: Output Cipher Block
------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
 
library work;
use work.aes_pkg.all;
 
entity sbox is
port(
clk: in std_logic;
bytein: in std_logic_vector(7 downto 0);
byteout: out std_logic_vector(7 downto 0)
);
end sbox;
 
architecture rtl of sbox is
type ram_type is array(natural range<>) of std_logic_vector(7 downto 0);
constant sbox_ram: ram_type(255 downto 0) :=
(
X"16", X"bb", X"54", X"b0", X"0f", X"2d", X"99", X"41", X"68", X"42", X"e6", X"bf", X"0d", X"89", X"a1", X"8c",
X"df", X"28", X"55", X"ce", X"e9", X"87", X"1e", X"9b", X"94", X"8e", X"d9", X"69", X"11", X"98", X"f8", X"e1",
X"9e", X"1d", X"c1", X"86", X"b9", X"57", X"35", X"61", X"0e", X"f6", X"03", X"48", X"66", X"b5", X"3e", X"70",
X"8a", X"8b", X"bd", X"4b", X"1f", X"74", X"dd", X"e8", X"c6", X"b4", X"a6", X"1c", X"2e", X"25", X"78", X"ba",
X"08", X"ae", X"7a", X"65", X"ea", X"f4", X"56", X"6c", X"a9", X"4e", X"d5", X"8d", X"6d", X"37", X"c8", X"e7",
X"79", X"e4", X"95", X"91", X"62", X"ac", X"d3", X"c2", X"5c", X"24", X"06", X"49", X"0a", X"3a", X"32", X"e0",
X"db", X"0b", X"5e", X"de", X"14", X"b8", X"ee", X"46", X"88", X"90", X"2a", X"22", X"dc", X"4f", X"81", X"60",
X"73", X"19", X"5d", X"64", X"3d", X"7e", X"a7", X"c4", X"17", X"44", X"97", X"5f", X"ec", X"13", X"0c", X"cd",
X"d2", X"f3", X"ff", X"10", X"21", X"da", X"b6", X"bc", X"f5", X"38", X"9d", X"92", X"8f", X"40", X"a3", X"51",
X"a8", X"9f", X"3c", X"50", X"7f", X"02", X"f9", X"45", X"85", X"33", X"4d", X"43", X"fb", X"aa", X"ef", X"d0",
X"cf", X"58", X"4c", X"4a", X"39", X"be", X"cb", X"6a", X"5b", X"b1", X"fc", X"20", X"ed", X"00", X"d1", X"53",
X"84", X"2f", X"e3", X"29", X"b3", X"d6", X"3b", X"52", X"a0", X"5a", X"6e", X"1b", X"1a", X"2c", X"83", X"09",
X"75", X"b2", X"27", X"eb", X"e2", X"80", X"12", X"07", X"9a", X"05", X"96", X"18", X"c3", X"23", X"c7", X"04",
X"15", X"31", X"d8", X"71", X"f1", X"e5", X"a5", X"34", X"cc", X"f7", X"3f", X"36", X"26", X"93", X"fd", X"b7",
X"c0", X"72", X"a4", X"9c", X"af", X"a2", X"d4", X"ad", X"f0", X"47", X"59", X"fa", X"7d", X"c9", X"82", X"ca",
X"76", X"ab", X"d7", X"fe", X"2b", X"67", X"01", X"30", X"c5", X"6f", X"6b", X"f2", X"7b", X"77", X"7c", X"63"
);
begin
process(clk)
begin
if(rising_edge(clk)) then
byteout <= sbox_ram(conv_integer(bytein));
end if;
end process;
end rtl;
/rtl/keysched1.vhdl
0,0 → 1,115
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2001, 2002 Authors ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http:--www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
------------------------------------------------------
-- Project: AESFast
-- Author: Subhasis
-- Last Modified: 20/03/10
-- Email: subhasis256@gmail.com
------------------------------------------------------
--
-- Description: First stage of key expansion
-- Ports:
-- clk: System Clock
-- roundkey: Current roundkey
-- rcon: Rcon byte for the next byte
-- fc3: Sbox(RotWord(column3 of rkey)) xor Rcon
-- c0: column0 of rkey
-- c1: column0 xor column1
-- c2: column0 xor column1 xor column2
-- c3: column0 xor column1 xor column2 xor column3
------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
 
library work;
use work.aes_pkg.all;
 
entity keysched1 is
port(
clk: in std_logic;
roundkey: in datablock;
rcon: in std_logic_vector(7 downto 0);
fc3: out blockcol;
c0: out blockcol;
c1: out blockcol;
c2: out blockcol;
c3: out blockcol
);
end keysched1;
 
architecture rtl of keysched1 is
signal subst: blockcol;
signal key0, key1, key2, key3: std_logic_vector(7 downto 0);
component sbox is
port(
clk: in std_logic;
bytein: in std_logic_vector(7 downto 0);
byteout: out std_logic_vector(7 downto 0)
);
end component;
signal rcon_d: std_logic_vector(7 downto 0);
begin
sub0: sbox port map(
clk => clk,
bytein => roundkey(0, 3),
byteout => subst(3)
);
sub1: sbox port map(
clk => clk,
bytein => roundkey(1, 3),
byteout => subst(0)
);
sub2: sbox port map(
clk => clk,
bytein => roundkey(2, 3),
byteout => subst(1)
);
sub3: sbox port map(
clk => clk,
bytein => roundkey(3, 3),
byteout => subst(2)
);
fc3(0) <= subst(0) xor rcon_d;
fc3(1) <= subst(1);
fc3(2) <= subst(2);
fc3(3) <= subst(3);
process(clk)
begin
if(rising_edge(clk)) then
rcon_d <= rcon;
for j in 3 downto 0 loop
c0(j) <= roundkey(j, 0);
c1(j) <= roundkey(j, 0) xor roundkey(j, 1);
c2(j) <= roundkey(j, 0) xor roundkey(j, 1) xor roundkey(j, 2);
c3(j) <= roundkey(j, 0) xor roundkey(j, 1) xor roundkey(j, 2) xor roundkey(j, 3);
end loop;
end if;
end process;
end rtl;
/rtl/addkey.vhdl
0,0 → 1,108
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2001, 2002 Authors ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http:--www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
------------------------------------------------------
-- Project: AESFast
-- Author: Subhasis
-- Last Modified: 20/03/10
-- Email: subhasis256@gmail.com
------------------------------------------------------
--
-- Description: The AddKey step
-- Ports:
-- clk: System Clock
-- roundkey: The RoundKey block for this round
-- datain: Input State block
-- rcon: The rcon byte corresponding to the current stage
-- dataout: datain xor roundkey
-- fc3: See keysched1 for explanation
-- c0: See keysched1 for explanation
-- c1: See keysched1 for explanation
-- c2: See keysched1 for explanation
-- c3: See keysched1 for explanation
------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
 
library work;
use work.aes_pkg.all;
 
entity addkey is
port(
clk: in std_logic;
roundkey: in datablock;
datain: in datablock;
rcon: in std_logic_vector(7 downto 0);
dataout: out datablock;
fc3: out blockcol;
c0: out blockcol;
c1: out blockcol;
c2: out blockcol;
c3: out blockcol
);
end addkey;
 
architecture rtl of addkey is
component keysched1 is
port(
clk: in std_logic;
roundkey: in datablock;
rcon: in std_logic_vector(7 downto 0);
fc3: out blockcol;
c0: out blockcol;
c1: out blockcol;
c2: out blockcol;
c3: out blockcol
);
end component;
signal added: datablock;
begin
step1: keysched1 port map(
clk => clk,
roundkey => roundkey,
rcon => rcon,
fc3 => fc3,
c0 => c0,
c1 => c1,
c2 => c2,
c3 => c3
);
g0: for i in 3 downto 0 generate
g1: for j in 3 downto 0 generate
added(i,j) <= datain(i,j) xor roundkey(i,j);
end generate;
end generate;
process(clk)
begin
if(rising_edge(clk)) then
dataout <= added;
end if;
end process;
end rtl;
/rtl_sim/tb_aes.vhdl
0,0 → 1,107
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2001, 2002 Authors ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http:--www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
------------------------------------------------------
-- Project: AESFast
-- Author: Subhasis
-- Last Modified: 20/03/10
-- Email: subhasis256@gmail.com
--
-- TODO: Test with NIST test vectors
------------------------------------------------------
--
-- Description: Testbench for AESFast
------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
 
library work;
use work.aes_pkg.all;
 
entity tb_aes is
end tb_aes;
 
architecture rtl of tb_aes is
signal clk: std_logic;
signal plaintext: datablock;
signal key: datablock;
signal cipher: datablock;
signal start: std_logic := '0';
signal done: std_logic;
 
component aes_proc is
port(
clk: in std_logic;
plaintext: in datablock;
keyblock: in datablock;
ciphertext: out datablock
);
end component;
 
begin
g0: for i in 3 downto 0 generate
g1: for j in 3 downto 1 generate
plaintext(i,j) <= X"00";
key(i,j) <= X"00";
end generate;
end generate;
plaintext(3,0) <= X"00";
plaintext(2,0) <= X"00";
plaintext(1,0) <= X"00";
key(3,0) <= X"00";
key(2,0) <= X"00";
key(1,0) <= X"00";
key(0,0) <= X"00";
proc0: aes_proc port map(
clk => clk,
plaintext => plaintext,
keyblock => key,
ciphertext => cipher
);
gen_clk: process
begin
wait for 10 ns;
clk <= '1';
wait for 10 ns;
clk <= '0';
end process;
gen_in: process
begin
wait for 25 ns;
plaintext(0,0) <= X"00";
wait for 20 ns;
plaintext(0,0) <= X"01";
wait for 20 ns;
plaintext(0,0) <= X"02";
wait for 40 ns;
plaintext(0,0) <= X"03";
wait;
end process;
end rtl;

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