URL
https://opencores.org/ocsvn/ahb_slave/ahb_slave/trunk
Subversion Repositories ahb_slave
Compare Revisions
- This comparison shows the changes necessary to convert path
/ahb_slave
- from Rev 2 to Rev 3
- ↔ Reverse comparison
Rev 2 → Rev 3
/trunk/src/base/ahb_slave_trace.v
4,11 → 4,8
INCLUDE def_ahb_slave.txt |
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module PREFIX_trace(PORTS); |
parameter SLAVE_NUM = 0; |
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parameter SLAVE_NUM = 0; |
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parameter FILE_NAME = "PREFIX.trc"; |
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input clk; |
input reset; |
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20,12 → 17,18
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wire [31:0] ADDR_WR_disp = ADDR_WR; |
wire [31:0] ADDR_RD_disp = ADDR_RD_d; |
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reg [64*8-1:0] filename; |
integer file_ptr; |
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initial |
file_ptr = $fopen(FILE_NAME, "w"); |
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begin |
//erase trace |
file_ptr = $fopen({"PREFIX.trc"}, "w"); |
$fwrite(file_ptr, "\n"); |
$fclose(file_ptr); |
end |
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always @(posedge clk or posedge reset) |
if (reset) |
41,12 → 44,19
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always @(posedge clk) |
if (WR) |
$fwrite(file_ptr, "%16d: %0s WR: Addr: 0x%8h, Data: 0x%8h, Bsel: 0x%2h\n", $time, FILE_NAME, ADDR_WR_disp, DIN, BSEL); |
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begin |
file_ptr = $fopen({"PREFIX.trc"}, "a"); |
$fwrite(file_ptr, "%16d: PREFIX%0d WR: Addr: 0x%EXPR(ADDR_BITS/4)h, Data: 0x%EXPR(DATA_BITS/4)h, Bsel: 0x%EXPR(DATA_BITS/32)h\n", $time, SLAVE_NUM, ADDR_WR_disp, DIN, BSEL); |
$fclose(file_ptr); |
end |
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always @(posedge clk) |
if (RD_d) |
$fwrite(file_ptr, "%16d: %0s RD: Addr: 0x%8h, Data: 0x%8h\n", $time, FILE_NAME, ADDR_RD_disp, DOUT); |
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begin |
file_ptr = $fopen({"PREFIX.trc"}, "a"); |
$fwrite(file_ptr, "%16d: PREFIX%0d RD: Addr: 0x%EXPR(ADDR_BITS/4)h, Data: 0x%EXPR(DATA_BITS/4)h\n", $time, SLAVE_NUM, ADDR_RD_disp, DOUT); |
$fclose(file_ptr); |
end |
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endmodule |
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/trunk/src/base/ahb_slave_ram.v
41,8 → 41,9
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reg [1:0] HSIZE_d; |
wire WR_pre; |
reg WR_pre_d; |
wire WR; |
wire [ADDR_BITS-1:0] ADDR_WR_pre; |
reg WR; |
reg [ADDR_BITS-1:0] ADDR_WR; |
reg data_phase; |
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133,6 → 134,7
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assign WR_pre = HWRITE & ((HTRANS == TRANS_NONSEQ) | (HTRANS == TRANS_SEQ)); |
assign WR = WR_pre_d & HREADY; |
assign RD = (~HWRITE) & ((HTRANS == TRANS_NONSEQ) | (HTRANS == TRANS_SEQ)) & HREADY; |
assign ADDR_WR_pre = {ADDR_BITS{WR_pre}} & HADDR; |
assign ADDR_RD = {ADDR_BITS{RD}} & HADDR; |
168,13 → 170,13
always @(posedge clk or posedge reset) |
if (reset) |
begin |
WR <= #FFD 1'b0; |
WR_pre_d <= #FFD 1'b0; |
ADDR_WR <= #FFD {ADDR_BITS{1'b0}}; |
HSIZE_d <= #FFD 2'b0; |
end |
else if (HREADY) |
begin |
WR <= #FFD WR_pre; |
WR_pre_d <= #FFD WR_pre; |
ADDR_WR <= #FFD ADDR_WR_pre; |
HSIZE_d <= #FFD HSIZE; |
end |