URL
https://opencores.org/ocsvn/amber/amber/trunk
Subversion Repositories amber
Compare Revisions
- This comparison shows the changes necessary to convert path
/amber/trunk/hw/vlog/amber25
- from Rev 16 to Rev 17
- ↔ Reverse comparison
Rev 16 → Rev 17
/a25_dcache.v
1,14 → 1,14
////////////////////////////////////////////////////////////////// |
// // |
// L1 Instruction Cache for Amber 25 Core // |
// L1 Data Cache for Amber 25 Core // |
// // |
// This file is part of the Amber project // |
// http://www.opencores.org/project,amber // |
// // |
// Description // |
// Synthesizable L1 Unified Data and Instruction Cache // |
// Cache is 4-way, 256 line and 16 bytes per line for // |
// a total of 16KB. The cache policy is write-through and // |
// Synthesizable L1 Data Cache // |
// Cache is 2, 3, 4 or 8 way, 256 line and 16 bytes per line. // |
// The cache policy is write-through and // |
// read allocate. For swap instructions (SWP and SWPB) the // |
// location is evicted from the cache and read from main // |
// memory. // |
/a25_icache.v
6,12 → 6,10
// http://www.opencores.org/project,amber // |
// // |
// Description // |
// Synthesizable L1 Unified Data and Instruction Cache // |
// Cache is 4-way, 256 line and 16 bytes per line for // |
// a total of 16KB. The cache policy is write-through and // |
// read allocate. For swap instructions (SWP and SWPB) the // |
// location is evicted from the cache and read from main // |
// memory. // |
// Synthesizable L1 Instruction Cache. // |
// Cache is 2,3,4 or 8 way, 256 line and 16 bytes per line. // |
// a total of 16KB. The cache is read only. Writes from // |
// the core to through the data cache. // |
// // |
// Author(s): // |
// - Conor Santifort, csantifort.amber@gmail.com // |
/a25_wishbone.v
7,11 → 7,11
// // |
// Description // |
// Turns memory access requests from the execute stage and // |
// cache into wishbone bus cycles. For 4-word read requests // |
// from the cache and swap accesses ( read followed by write // |
// to the same address) from the execute stage, // |
// a block transfer is done. All other requests result in // |
// single word transfers. // |
// instruction and data caches into wishbone bus cycles. // |
// For 4-word read requests from either cache and swap // |
// accesses ( read followed by write to the same address) // |
// from the execute stage, a block transfer is done. // |
// All other requests result in single word transfers. // |
// // |
// Write accesses can be done in a single clock cycle on // |
// the wishbone bus, is the destination allows it. The // |
/a25_decode.v
684,9 → 684,10
// interrupt is triggered if the execute condition is met in the execute stage |
assign interrupt = next_interrupt != 3'd0 && |
next_interrupt != 3'd7 && // SWI |
next_interrupt != 3'd6 ; // undefined interrupt |
next_interrupt != 3'd6 && // undefined interrupt |
!conflict ; // Wait for conflicts to resolve before |
// triggering int |
|
|
assign interrupt_mode = next_interrupt == 3'd2 ? FIRQ : |
next_interrupt == 3'd3 ? IRQ : |
next_interrupt == 3'd4 ? SVC : |
/a25_core.v
7,7 → 7,9
// // |
// Description // |
// Instantiates the core consisting of fetch, instruction // |
// decode, execute, and co-processor. // |
// decode, execute, memory access and write back. The // |
// Wishbone interface and Co-Processor modules are also // |
// instantiated here. // |
// // |
// Author(s): // |
// - Conor Santifort, csantifort.amber@gmail.com // |
73,7 → 75,6
wire [31:0] write_data; |
wire write_enable; |
wire [31:0] fetch_instruction; |
// wire priviledged; |
wire decode_exclusive; |
wire decode_iaccess; |
wire decode_daccess; |
118,7 → 119,6
wire [1:0] byte_enable_sel; |
wire [2:0] status_bits_sel; |
wire [2:0] reg_write_sel; |
// wire user_mode_regs_load; |
wire user_mode_regs_store_nxt; |
wire firq_not_user_mode; |
|
261,7 → 261,6
.o_byte_enable_sel ( byte_enable_sel ), |
.o_status_bits_sel ( status_bits_sel ), |
.o_reg_write_sel ( reg_write_sel ), |
// .o_user_mode_regs_load ( user_mode_regs_load ), |
.o_user_mode_regs_store_nxt ( user_mode_regs_store_nxt ), |
.o_firq_not_user_mode ( firq_not_user_mode ), |
.o_write_data_wen ( write_data_wen ), |
350,7 → 349,6
.i_byte_enable_sel ( byte_enable_sel ), |
.i_status_bits_sel ( status_bits_sel ), |
.i_reg_write_sel ( reg_write_sel ), |
// .i_user_mode_regs_load ( user_mode_regs_load ), |
.i_user_mode_regs_store_nxt ( user_mode_regs_store_nxt ), |
.i_firq_not_user_mode ( firq_not_user_mode ), |
.i_write_data_wen ( write_data_wen ), |
/a25_decompile.v
1,6 → 1,6
////////////////////////////////////////////////////////////////// |
// // |
// Decompiler for Amber 25 Core // |
// Decompiler for Amber 25 Core // |
// // |
// This file is part of the Amber project // |
// http://www.opencores.org/project,amber // |