URL
https://opencores.org/ocsvn/amber/amber/trunk
Subversion Repositories amber
Compare Revisions
- This comparison shows the changes necessary to convert path
/amber/trunk/hw/vlog/amber25
- from Rev 39 to Rev 53
- ↔ Reverse comparison
Rev 39 → Rev 53
/a25_write_back.v
59,7 → 59,6
reg [31:0] mem_read_data_r = 'd0; // Register read data from Data Cache |
reg mem_read_data_valid_r = 'd0; // Register read data from Data Cache |
reg [10:0] mem_load_rd_r = 'd0; // Register the Rd value for loads |
reg [31:0] daddress_r = 'd0; // Register read data from Data Cache |
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assign o_wb_read_data = mem_read_data_r; |
assign o_wb_read_data_valid = mem_read_data_valid_r; |
68,13 → 67,20
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always @( posedge i_clk ) |
if ( !i_mem_stall ) |
begin |
mem_read_data_r <= i_mem_read_data; |
mem_read_data_valid_r <= i_mem_read_data_valid; |
mem_load_rd_r <= i_mem_load_rd; |
daddress_r <= i_daddress; |
end |
|
begin |
mem_read_data_r <= i_mem_read_data; |
mem_read_data_valid_r <= i_mem_read_data_valid; |
mem_load_rd_r <= i_mem_load_rd; |
end |
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// Used by a25_decompile.v, so simulation only |
//synopsys translate_off |
reg [31:0] daddress_r = 'd0; // Register read data from Data Cache |
always @( posedge i_clk ) |
if ( !i_mem_stall ) |
daddress_r <= i_daddress; |
//synopsys translate_on |
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endmodule |
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/a25_multiply.v
80,8 → 80,6
reg [67:0] product = 'd0; |
reg [67:0] product_nxt; |
reg [1:0] flags_nxt; |
reg sum_acc1_carry = 'd0; |
reg sum_acc1_carry_nxt; |
wire [32:0] sum_acc1; // the MSB is the carry out for the upper 32 bit addition |
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154,7 → 152,6
begin |
// Defaults |
count_nxt = count; |
sum_acc1_carry_nxt = sum_acc1_carry; |
product_nxt = product; |
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// update Negative and Zero flags |
173,7 → 170,6
// Note that bit 0 is not part of the product. It is used during the booth |
// multiplication algorithm |
product_nxt = { product[64:33], sum_acc1[31:0], 1'd0}; // Accumulate |
sum_acc1_carry_nxt = sum_acc1[32]; |
end |
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// Multiplication state counter |
192,7 → 188,6
begin |
count <= i_execute ? count_nxt : count; |
product <= i_execute ? product_nxt : product; |
sum_acc1_carry <= i_execute ? sum_acc1_carry_nxt : sum_acc1_carry; |
o_done <= i_execute ? count == 6'd31 : o_done; |
end |
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/a25_register_bank.v
341,7 → 341,6
4'd12 : o_rs = r12_rds ; |
4'd13 : o_rs = r13_rds ; |
4'd14 : o_rs = r14_rds ; |
4'd15 : o_rs = r15_out_rn ; |
default: o_rs = r15_out_rn ; |
endcase |
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366,7 → 365,6
4'd12 : o_rd = r12_rds ; |
4'd13 : o_rd = r13_rds ; |
4'd14 : o_rd = r14_rds ; |
4'd15 : o_rd = r15_out_rm_nxt ; |
default: o_rd = r15_out_rm_nxt ; |
endcase |
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/a25_decode.v
298,8 → 298,6
wire und_request; |
wire dabt_request; |
reg [1:0] copro_operation_nxt; |
reg mtrans_r15 = 'd0; |
reg mtrans_r15_nxt; |
reg restore_base_address = 'd0; |
reg restore_base_address_nxt; |
|
728,7 → 726,6
// Save an instruction to use later |
saved_current_instruction_wen = 1'd0; |
pre_fetch_instruction_wen = 1'd0; |
mtrans_r15_nxt = mtrans_r15; |
restore_base_address_nxt = restore_base_address; |
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// default Mux Select values |
949,7 → 946,6
saved_current_instruction_wen = 1'd1; // Save the memory access instruction to refer back to later |
decode_daccess_nxt = 1'd1; // valid data access |
alu_out_sel_nxt = 4'd1; // Add |
mtrans_r15_nxt = instruction[15]; // load or save r15 ? |
base_address_wen_nxt = 1'd1; // Save the value of the register used for the base address, |
// in case of a data abort, and need to restore the value |
|
1618,7 → 1614,6
o_copro_num <= instruction[11:8]; |
o_copro_operation <= copro_operation_nxt; |
o_copro_write_data_wen <= copro_write_data_wen_nxt; |
mtrans_r15 <= mtrans_r15_nxt; |
restore_base_address <= restore_base_address_nxt; |
control_state <= control_state_nxt; |
end |
/a25_core.v
167,7 → 167,6
wire [15:0] dcache_wb_byte_enable; |
wire [31:0] dcache_wb_address; |
wire [127:0] dcache_wb_cached_rdata; |
wire [127:0] dcache_wb_uncached_rdata; |
wire [127:0] dcache_wb_write_data; |
wire dcache_wb_cached_ready; |
wire dcache_wb_uncached_ready; |
450,7 → 449,7
.i_port0_wdata ( dcache_wb_write_data ), |
.i_port0_be ( dcache_wb_byte_enable ), |
.i_port0_addr ( dcache_wb_address ), |
.o_port0_rdata ( dcache_wb_uncached_rdata ), |
.o_port0_rdata ( ), |
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// Port 1 - dcache cached |
.i_port1_req ( dcache_wb_cached_req ), |
/a25_execute.v
357,10 → 357,10
// mem_load_rd[6:5] -> Write into this Mode registers |
// mem_load_rd[4] -> zero_extend byte |
// mem_load_rd[3:0] -> Destination Register |
assign read_data_filtered1 = i_wb_load_rd[10:9] === 2'd0 ? i_wb_read_data : |
i_wb_load_rd[10:9] === 2'd1 ? {i_wb_read_data[7:0], i_wb_read_data[31:8]} : |
i_wb_load_rd[10:9] === 2'd2 ? {i_wb_read_data[15:0], i_wb_read_data[31:16]} : |
{i_wb_read_data[23:0], i_wb_read_data[31:24]} ; |
assign read_data_filtered1 = i_wb_load_rd[10:9] == 2'd0 ? i_wb_read_data : |
i_wb_load_rd[10:9] == 2'd1 ? {i_wb_read_data[7:0], i_wb_read_data[31:8]} : |
i_wb_load_rd[10:9] == 2'd2 ? {i_wb_read_data[15:0], i_wb_read_data[31:16]} : |
{i_wb_read_data[23:0], i_wb_read_data[31:24]} ; |
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assign read_data_filtered = i_wb_load_rd[4] ? {24'd0, read_data_filtered1[7:0]} : read_data_filtered1 ; |
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