URL
https://opencores.org/ocsvn/amber/amber/trunk
Subversion Repositories amber
Compare Revisions
- This comparison shows the changes necessary to convert path
/amber/trunk/hw/vlog/amber25
- from Rev 63 to Rev 82
- ↔ Reverse comparison
Rev 63 → Rev 82
/a25_config_defines.v
File deleted
/a25_localparams.v
File deleted
/a25_functions.v
File deleted
/a25_shifter.v
54,7 → 54,7
|
); |
|
`include "a25_localparams.v" |
`include "a25_localparams.vh" |
|
// MSB is carry out |
wire [32:0] lsl_out; |
/a25_localparams.vh
0,0 → 1,117
////////////////////////////////////////////////////////////////// |
// // |
// Parameters file for Amber 25 Core // |
// // |
// This file is part of the Amber project // |
// http://www.opencores.org/project,amber // |
// // |
// Description // |
// Holds general parameters that are used is several core // |
// modules // |
// // |
// Author(s): // |
// - Conor Santifort, csantifort.amber@gmail.com // |
// // |
////////////////////////////////////////////////////////////////// |
// // |
// Copyright (C) 2011 Authors and OPENCORES.ORG // |
// // |
// This source file may be used and distributed without // |
// restriction provided that this copyright statement is not // |
// removed from the file and that any derivative work contains // |
// the original copyright notice and the associated disclaimer. // |
// // |
// This source file is free software; you can redistribute it // |
// and/or modify it under the terms of the GNU Lesser General // |
// Public License as published by the Free Software Foundation; // |
// either version 2.1 of the License, or (at your option) any // |
// later version. // |
// // |
// This source is distributed in the hope that it will be // |
// useful, but WITHOUT ANY WARRANTY; without even the implied // |
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // |
// PURPOSE. See the GNU Lesser General Public License for more // |
// details. // |
// // |
// You should have received a copy of the GNU Lesser General // |
// Public License along with this source; if not, download it // |
// from http://www.opencores.org/lgpl.shtml // |
// // |
////////////////////////////////////////////////////////////////// |
|
|
// Instruction Types |
localparam [3:0] REGOP = 4'h0, // Data processing |
MULT = 4'h1, // Multiply |
SWAP = 4'h2, // Single Data Swap |
TRANS = 4'h3, // Single data transfer |
MTRANS = 4'h4, // Multi-word data transfer |
BRANCH = 4'h5, // Branch |
CODTRANS = 4'h6, // Co-processor data transfer |
COREGOP = 4'h7, // Co-processor data operation |
CORTRANS = 4'h8, // Co-processor register transfer |
SWI = 4'h9; // software interrupt |
|
|
// Opcodes |
localparam [3:0] AND = 4'h0, // Logical AND |
EOR = 4'h1, // Logical Exclusive OR |
SUB = 4'h2, // Subtract |
RSB = 4'h3, // Reverse Subtract |
ADD = 4'h4, // Add |
ADC = 4'h5, // Add with Carry |
SBC = 4'h6, // Subtract with Carry |
RSC = 4'h7, // Reverse Subtract with Carry |
TST = 4'h8, // Test (using AND operator) |
TEQ = 4'h9, // Test Equivalence (using EOR operator) |
CMP = 4'ha, // Compare (using Subtract operator) |
CMN = 4'hb, // Compare Negated |
ORR = 4'hc, // Logical OR |
MOV = 4'hd, // Move |
BIC = 4'he, // Bit Clear (using AND & NOT operators) |
MVN = 4'hf; // Move NOT |
|
// Condition Encoding |
localparam [3:0] EQ = 4'h0, // Equal / Z set |
NE = 4'h1, // Not equal / Z clear |
CS = 4'h2, // Carry set / C set |
CC = 4'h3, // Carry clear / C clear |
MI = 4'h4, // Minus / N set |
PL = 4'h5, // Plus / N clear |
VS = 4'h6, // Overflow / V set |
VC = 4'h7, // No overflow / V clear |
HI = 4'h8, // Unsigned higher / C set and Z clear |
LS = 4'h9, // Unsigned lower |
// or same / C clear or Z set |
GE = 4'ha, // Signed greater |
// than or equal / N == V |
LT = 4'hb, // Signed less than / N != V |
GT = 4'hc, // Signed greater |
// than / Z == 0, N == V |
LE = 4'hd, // Signed less than |
// or equal / Z == 1, N != V |
AL = 4'he, // Always |
NV = 4'hf; // Never |
|
// Any instruction with a condition field of 0b1111 is UNPREDICTABLE. |
|
// Shift Types |
localparam [1:0] LSL = 2'h0, |
LSR = 2'h1, |
ASR = 2'h2, |
RRX = 2'h3, |
ROR = 2'h3; |
|
// Modes |
localparam [1:0] SVC = 2'b11, // Supervisor |
IRQ = 2'b10, // Interrupt |
FIRQ = 2'b01, // Fast Interrupt |
USR = 2'b00; // User |
|
// One-Hot Mode encodings |
localparam [5:0] OH_USR = 0, |
OH_IRQ = 1, |
OH_FIRQ = 2, |
OH_SVC = 3; |
|
|
/a25_dcache.v
42,8 → 42,8
// from http://www.opencores.org/lgpl.shtml // |
// // |
////////////////////////////////////////////////////////////////// |
`include "global_defines.v" |
`include "a25_config_defines.v" |
`include "global_defines.vh" |
`include "a25_config_defines.vh" |
|
module a25_dcache |
#( |
105,8 → 105,8
input i_wb_cached_ready // wb_stb && !wb_ack |
); |
|
`include "a25_localparams.v" |
`include "a25_functions.v" |
`include "a25_localparams.vh" |
`include "a25_functions.vh" |
|
// One-hot encoded |
localparam C_INIT = 0, |
/makefile.inc
0,0 → 1,21
INCDIR += +$(IPVLOG)/amber25 |
SRC += $(IPVLOG)/amber25/a25_alu.v |
SRC += $(IPVLOG)/amber25/a25_barrel_shift.v |
SRC += $(IPVLOG)/amber25/a25_coprocessor.v |
SRC += $(IPVLOG)/amber25/a25_core.v |
SRC += $(IPVLOG)/amber25/a25_dcache.v |
SRC += $(IPVLOG)/amber25/a25_decode.v |
SRC += $(IPVLOG)/amber25/a25_decompile.v |
SRC += $(IPVLOG)/amber25/a25_execute.v |
SRC += $(IPVLOG)/amber25/a25_fetch.v |
SRC += $(IPVLOG)/amber25/a25_icache.v |
SRC += $(IPVLOG)/amber25/a25_mem.v |
SRC += $(IPVLOG)/amber25/a25_multiply.v |
SRC += $(IPVLOG)/amber25/a25_register_bank.v |
SRC += $(IPVLOG)/amber25/a25_shifter.v |
SRC += $(IPVLOG)/amber25/a25_wishbone_buf.v |
SRC += $(IPVLOG)/amber25/a25_wishbone.v |
SRC += $(IPVLOG)/amber25/a25_write_back.v |
DEP += $(IPVLOG)/amber25/a25_config_defines.vh |
DEP += $(IPVLOG)/amber25/a25_functions.vh |
DEP += $(IPVLOG)/amber25/a25_localparams.vh |
/a25_config_defines.vh
0,0 → 1,84
////////////////////////////////////////////////////////////////// |
// // |
// Amber Configuration and Debug for the Amber 25 Core // |
// // |
// This file is part of the Amber project // |
// http://www.opencores.org/project,amber // |
// // |
// Description // |
// Contains a set of defines used to configure and debug // |
// the Amber core // |
// // |
// Author(s): // |
// - Conor Santifort, csantifort.amber@gmail.com // |
// // |
////////////////////////////////////////////////////////////////// |
// // |
// Copyright (C) 2011 Authors and OPENCORES.ORG // |
// // |
// This source file may be used and distributed without // |
// restriction provided that this copyright statement is not // |
// removed from the file and that any derivative work contains // |
// the original copyright notice and the associated disclaimer. // |
// // |
// This source file is free software; you can redistribute it // |
// and/or modify it under the terms of the GNU Lesser General // |
// Public License as published by the Free Software Foundation; // |
// either version 2.1 of the License, or (at your option) any // |
// later version. // |
// // |
// This source is distributed in the hope that it will be // |
// useful, but WITHOUT ANY WARRANTY; without even the implied // |
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // |
// PURPOSE. See the GNU Lesser General Public License for more // |
// details. // |
// // |
// You should have received a copy of the GNU Lesser General // |
// Public License along with this source; if not, download it // |
// from http://www.opencores.org/lgpl.shtml // |
// // |
////////////////////////////////////////////////////////////////// |
|
`ifndef _A25_CONFIG_DEFINES |
`define _A25_CONFIG_DEFINES |
|
// Cache Ways |
// Changing this parameter is the recommended |
// way to change the Amber cache size; 2, 3, 4 and 8 ways are supported. |
// |
// 2 ways -> 8KB cache |
// 3 ways -> 12KB cache |
// 4 ways -> 16KB cache |
// 8 ways -> 32KB cache |
// |
// e.g. if both caches have 8 ways, the total is 32KB icache + 32KB dcache = 64KB |
|
`define A25_ICACHE_WAYS 4 |
`define A25_DCACHE_WAYS 4 |
|
|
// -------------------------------------------------------------------- |
// Debug switches |
// -------------------------------------------------------------------- |
|
// Enable the decompiler. The default output file is amber.dis |
`define A25_DECOMPILE |
|
// Co-processor 15 debug. Registers in here control the cache |
//`define A25_COPRO15_DEBUG |
|
// Cache debug |
//`define A25_CACHE_DEBUG |
|
// -------------------------------------------------------------------- |
|
|
// -------------------------------------------------------------------- |
// File Names |
// -------------------------------------------------------------------- |
`ifndef A25_DECOMPILE_FILE |
`define A25_DECOMPILE_FILE "amber.dis" |
`endif |
|
`endif |
|
/a25_icache.v
40,8 → 40,8
// from http://www.opencores.org/lgpl.shtml // |
// // |
////////////////////////////////////////////////////////////////// |
`include "global_defines.v" |
`include "a25_config_defines.v" |
`include "global_defines.vh" |
`include "a25_config_defines.vh" |
|
module a25_icache |
#( |
98,8 → 98,8
input i_wb_ready |
); |
|
`include "a25_localparams.v" |
`include "a25_functions.v" |
`include "a25_localparams.vh" |
`include "a25_functions.vh" |
|
// One-hot encoded |
localparam C_INIT = 0, |
/a25_mem.v
78,7 → 78,7
input i_wb_uncached_ready // wishbone access complete and read data valid |
); |
|
`include "memory_configuration.v" |
`include "memory_configuration.vh" |
|
wire [31:0] cache_read_data; |
wire address_cachable; |
/a25_register_bank.v
81,8 → 81,8
|
); |
|
`include "a25_localparams.v" |
`include "a25_functions.v" |
`include "a25_localparams.vh" |
`include "a25_functions.vh" |
|
|
// User Mode Registers |
/a25_functions.vh
0,0 → 1,208
////////////////////////////////////////////////////////////////// |
// // |
// Functions for Amber 25 Core // |
// // |
// This file is part of the Amber project // |
// http://www.opencores.org/project,amber // |
// // |
// Description // |
// Functions used in more than one module // |
// // |
// Author(s): // |
// - Conor Santifort, csantifort.amber@gmail.com // |
// // |
////////////////////////////////////////////////////////////////// |
// // |
// Copyright (C) 2011 Authors and OPENCORES.ORG // |
// // |
// This source file may be used and distributed without // |
// restriction provided that this copyright statement is not // |
// removed from the file and that any derivative work contains // |
// the original copyright notice and the associated disclaimer. // |
// // |
// This source file is free software; you can redistribute it // |
// and/or modify it under the terms of the GNU Lesser General // |
// Public License as published by the Free Software Foundation; // |
// either version 2.1 of the License, or (at your option) any // |
// later version. // |
// // |
// This source is distributed in the hope that it will be // |
// useful, but WITHOUT ANY WARRANTY; without even the implied // |
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // |
// PURPOSE. See the GNU Lesser General Public License for more // |
// details. // |
// // |
// You should have received a copy of the GNU Lesser General // |
// Public License along with this source; if not, download it // |
// from http://www.opencores.org/lgpl.shtml // |
// // |
////////////////////////////////////////////////////////////////// |
|
|
// ======================================================== |
// Instruction type decode |
// ======================================================== |
function [3:0] instruction_type; |
input [31:0] instruction; |
begin |
// Instruction Decode - Order is important! |
casez ({instruction[27:20], instruction[7:4]}) |
12'b00010?001001 : instruction_type = SWAP; |
12'b000000??1001 : instruction_type = MULT; |
12'b00?????????? : instruction_type = REGOP; |
12'b01?????????? : instruction_type = TRANS; |
12'b100????????? : instruction_type = MTRANS; |
12'b101????????? : instruction_type = BRANCH; |
12'b110????????? : instruction_type = CODTRANS; |
12'b1110???????0 : instruction_type = COREGOP; |
12'b1110???????1 : instruction_type = CORTRANS; |
default: instruction_type = SWI; |
endcase |
end |
endfunction |
|
|
// ======================================================== |
// Select 32 bits from a 128 bit bus based on a 2-bit address |
// ======================================================== |
function [31:0] sel32_128; |
input [1:0] select; |
input [127:0] bus; |
begin |
sel32_128 = select==2'd0 ? bus[31:0] : select==2'd1 ? bus[63:32] : select==2'd2 ? bus[95:64] : bus[127:96]; |
end |
endfunction |
|
|
// ======================================================== |
// PC Filter - Remove the status bits |
// ======================================================== |
function [31:0] pcf; |
input [31:0] pc_reg; |
begin |
pcf = {6'd0, pc_reg[25:2], 2'd0}; |
end |
endfunction |
|
|
// ======================================================== |
// 4-bit to 16-bit 1-hot decode |
// ======================================================== |
function [14:0] decode; |
input [3:0] reg_sel; |
begin |
case ( reg_sel ) |
4'h0: decode = 15'h0001; |
4'h1: decode = 15'h0002; |
4'h2: decode = 15'h0004; |
4'h3: decode = 15'h0008; |
4'h4: decode = 15'h0010; |
4'h5: decode = 15'h0020; |
4'h6: decode = 15'h0040; |
4'h7: decode = 15'h0080; |
4'h8: decode = 15'h0100; |
4'h9: decode = 15'h0200; |
4'ha: decode = 15'h0400; |
4'hb: decode = 15'h0800; |
4'hc: decode = 15'h1000; |
4'hd: decode = 15'h2000; |
4'he: decode = 15'h4000; |
default: decode = 15'h0000; |
endcase |
end |
endfunction |
|
|
// ======================================================== |
// Convert Stats Bits Mode to one-hot encoded version |
// ======================================================== |
function [3:0] oh_status_bits_mode; |
input [1:0] fn_status_bits_mode; |
begin |
oh_status_bits_mode = |
fn_status_bits_mode == SVC ? 1'd1 << OH_SVC : |
fn_status_bits_mode == IRQ ? 1'd1 << OH_IRQ : |
fn_status_bits_mode == FIRQ ? 1'd1 << OH_FIRQ : |
1'd1 << OH_USR ; |
end |
endfunction |
|
// ======================================================== |
// Convert mode into ascii name |
// ======================================================== |
function [(14*8)-1:0] mode_name; |
input [4:0] mode; |
begin |
|
mode_name = mode == USR ? "User " : |
mode == SVC ? "Supervisor " : |
mode == IRQ ? "Interrupt " : |
mode == FIRQ ? "Fast Interrupt" : |
"UNKNOWN " ; |
end |
endfunction |
|
|
// ======================================================== |
// Conditional Execution Function |
// ======================================================== |
// EQ Z set |
// NE Z clear |
// CS C set |
// CC C clear |
// MI N set |
// PL N clear |
// VS V set |
// VC V clear |
// HI C set and Z clear |
// LS C clear or Z set |
// GE N == V |
// LT N != V |
// GT Z == 0,N == V |
// LE Z == 1 or N != V |
// AL Always (unconditional) |
// NV Never |
|
function conditional_execute; |
input [3:0] condition; |
input [3:0] flags; |
begin |
conditional_execute |
= ( condition == AL ) || |
( condition == EQ && flags[2] ) || |
( condition == NE && !flags[2] ) || |
( condition == CS && flags[1] ) || |
( condition == CC && !flags[1] ) || |
( condition == MI && flags[3] ) || |
( condition == PL && !flags[3] ) || |
( condition == VS && flags[0] ) || |
( condition == VC && !flags[0] ) || |
|
( condition == HI && flags[1] && !flags[2] ) || |
( condition == LS && (!flags[1] || flags[2]) ) || |
|
( condition == GE && flags[3] == flags[0] ) || |
( condition == LT && flags[3] != flags[0] ) || |
|
( condition == GT && !flags[2] && flags[3] == flags[0] ) || |
( condition == LE && (flags[2] || flags[3] != flags[0])) ; |
|
end |
endfunction |
|
|
// ======================================================== |
// Log 2 |
// ======================================================== |
|
function [31:0] log2; |
input [31:0] num; |
integer i; |
|
begin |
log2 = 32'd0; |
for (i=0; i<30; i=i+1) |
if ((2**i > num) && (log2 == 0)) |
log2 = i-1; |
end |
endfunction |
/a25_decode.v
39,7 → 39,7
// from http://www.opencores.org/lgpl.shtml // |
// // |
////////////////////////////////////////////////////////////////// |
`include "global_defines.v" |
`include "global_defines.vh" |
|
module a25_decode |
( |
131,8 → 131,8
|
); |
|
`include "a25_localparams.v" |
`include "a25_functions.v" |
`include "a25_localparams.vh" |
`include "a25_functions.vh" |
|
localparam [4:0] RST_WAIT1 = 5'd0, |
RST_WAIT2 = 5'd1, |
439,7 → 439,7
instruction[15:12] ; |
|
// Load from memory into registers |
assign ldm_user_mode = type == MTRANS && {instruction[22:20],instruction[15]} == 4'b1010; |
assign ldm_user_mode = type == MTRANS && {instruction[22],instruction[20],instruction[15]} == 3'b110; |
assign ldm_flags = type == MTRANS && rs_sel_nxt == 4'd15 && instruction[20] && instruction[22]; |
assign ldm_status_bits = type == MTRANS && rs_sel_nxt == 4'd15 && instruction[20] && instruction[22] && i_execute_status_bits[1:0] != USR; |
assign load_rd_byte = (type == TRANS || type == SWAP) && instruction[22]; |
803,6 → 803,11
|
if ( !immediate_shift_op && !instruction[4] ) |
barrel_shift_amount_sel_nxt = 2'd2; // Shift immediate amount |
|
// regops that do not change the overflow flag |
if ( opcode == AND || opcode == EOR || opcode == TST || opcode == TEQ || |
opcode == ORR || opcode == MOV || opcode == BIC || opcode == MVN ) |
status_bits_sel_nxt = 3'd5; |
|
if ( opcode == ADD || opcode == CMN ) // CMN is just like an ADD |
begin |
1000,7 → 1005,7
write_data_wen_nxt = 1'd1; |
|
// stm: store the user mode registers, when in priviledged mode |
if ( {instruction[22:20]} == 3'b100 ) |
if ( {instruction[22],instruction[20]} == 2'b10 ) |
o_user_mode_regs_store_nxt = 1'd1; |
|
// update the base register ? |
1205,7 → 1210,7
write_data_wen_nxt = 1'd1; |
|
// stm: store the user mode registers, when in priviledged mode |
if ( {instruction[22:20]} == 3'b100 ) |
if ( {instruction[22],instruction[20]} == 2'b10 ) |
o_user_mode_regs_store_nxt = 1'd1; |
|
// write to the pc ? |
1241,7 → 1246,7
write_data_wen_nxt = 1'd1; |
|
// stm: store the user mode registers, when in priviledged mode |
if ( {instruction[22:20]} == 3'b100 ) |
if ( {instruction[22],instruction[20]} == 2'b10 ) |
o_user_mode_regs_store_nxt = 1'd1; |
|
// write to the pc ? |
1414,7 → 1419,6
|
// Speed up the long path from u_decode/fetch_instruction_r to u_register_bank/r8_firq |
// This pre-encodes the firq_s3 signal thats used in u_register_bank |
// assign firq_not_user_mode_nxt = !user_mode_regs_load_nxt && status_bits_mode_nxt == FIRQ; |
assign firq_not_user_mode_nxt = status_bits_mode_nxt == FIRQ; |
|
|
1708,7 → 1712,7
// ======================================================== |
//synopsys translate_off |
|
`include "debug_functions.v" |
`include "debug_functions.vh" |
|
a25_decompile u_decompile ( |
.i_clk ( i_clk ), |
/a25_fetch.v
68,7 → 68,7
|
); |
|
`include "memory_configuration.v" |
`include "memory_configuration.vh" |
|
wire core_stall; |
wire cache_stall; |
/a25_decompile.v
39,8 → 39,9
// from http://www.opencores.org/lgpl.shtml // |
// // |
////////////////////////////////////////////////////////////////// |
`include "global_defines.v" |
`include "a25_config_defines.v" |
`include "global_timescale.vh" |
`include "global_defines.vh" |
`include "a25_config_defines.vh" |
|
module a25_decompile |
( |
58,7 → 59,7
|
); |
|
`include "a25_localparams.v" |
`include "a25_localparams.vh" |
|
`ifdef A25_DECOMPILE |
|
/a25_execute.v
127,8 → 127,8
input i_rd_use_read |
); |
|
`include "a25_localparams.v" |
`include "a25_functions.v" |
`include "a25_localparams.vh" |
`include "a25_functions.vh" |
|
// ======================================================== |
// Internal signals |
240,10 → 240,14
i_status_bits_sel == 3'd1 ? alu_out [31:28] : |
i_status_bits_sel == 3'd3 ? i_copro_read_data[31:28] : |
// 4 = update flags after a multiply operation |
{ multiply_flags, status_bits_flags[1:0] } ; |
i_status_bits_sel == 3'd4 ? { multiply_flags, status_bits_flags[1:0] } : |
// regops that do not change the overflow flag |
i_status_bits_sel == 3'd5 ? { alu_flags[3:1], status_bits_flags[0] } : |
4'b1111 ; |
|
assign status_bits_mode_nxt = ldm_status_bits ? read_data_filtered [1:0] : |
i_status_bits_sel == 3'd0 ? i_status_bits_mode : |
i_status_bits_sel == 3'd5 ? i_status_bits_mode : |
i_status_bits_sel == 3'd1 ? alu_out [1:0] : |
i_copro_read_data [1:0] ; |
|
262,11 → 266,13
|
assign status_bits_irq_mask_nxt = ldm_status_bits ? read_data_filtered [27] : |
i_status_bits_sel == 3'd0 ? i_status_bits_irq_mask : |
i_status_bits_sel == 3'd5 ? i_status_bits_irq_mask : |
i_status_bits_sel == 3'd1 ? alu_out [27] : |
i_copro_read_data [27] ; |
|
assign status_bits_firq_mask_nxt = ldm_status_bits ? read_data_filtered [26] : |
i_status_bits_sel == 3'd0 ? i_status_bits_firq_mask : |
i_status_bits_sel == 3'd5 ? i_status_bits_firq_mask : |
i_status_bits_sel == 3'd1 ? alu_out [26] : |
i_copro_read_data [26] ; |
|