OpenCores
URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/lib/perl
    from Rev 55 to Rev 56
    ↔ Reverse comparison
  •

Rev 55 → Rev 56

/Consts.pm
1,4 → 1,4
#This file is created by /home/alireza/work/git/hca_git/ProNoC/mpsoc/intsall.sh
#This file is created by /home/alireza/work/git/pronoc/mpsoc/intsall.sh
package Consts;
 
use constant VERSION => '2.1.0';
/compile.pl
358,7 → 358,7
}
 
 
my $cpu_num;
sub select_parallel_process_num {
my ($self,$name,$top,$target_dir)=@_;
my $table = def_table(2, 2, FALSE);
367,20 → 367,22
#get total number of processor in the system
my $cmd = "nproc\n";
my $cpu_num=4;
my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($cmd);
if(length $stderr>1){
#nproc command has failed. set default 4 paralel processor
}else {
my ($number ) = $stdout =~ /(\d+)/;
if (defined $number ){
$cpu_num =$number if ($number > 0 );
}
if(!defined $cpu_num){
my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($cmd);
if(length $stderr>1){
#nproc command has failed. set default 4 paralel processor
}else {
my ($number ) = $stdout =~ /(\d+)/;
if (defined $number ){
$cpu_num =$number if ($number > 0 );
}
}
}
($row,$col)= add_param_widget ($self,"Paralle run:" , "cpu_num", 1, 'Spin-button', "1,$cpu_num,1","specify the number of processors the Verilator can use at once to run parallel compilations/simulations", $table,$row,$col,1, 'compile', undef,undef,'vertical');
return $table;
}
 
sub select_parallel_thread_num {
my ($self,$name,$top,$target_dir)=@_;
my $table = def_table(2, 2, FALSE);
389,16 → 391,17
#get total number of processor in the system
my $cmd = "nproc\n";
my $cpu_num=4;
my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($cmd);
if(length $stderr>1){
#nproc command has failed. set default 4 paralel processor
}else {
my ($number ) = $stdout =~ /(\d+)/;
if (defined $number ){
$cpu_num =$number if ($number > 0 );
}
if(!defined $cpu_num){
my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($cmd);
if(length $stderr>1){
#nproc command has failed. set default 4 paralel processor
}else {
my ($number ) = $stdout =~ /(\d+)/;
if (defined $number ){
$cpu_num =$number if ($number > 0 );
}
}
}
($row,$col)= add_param_widget ($self,"Thread run:" , "thread_num", 1, 'Spin-button', "1,$cpu_num,1","specify the number of threads the Verilator can use at once in one simulation", $table,$row,$col,1, 'compile', undef,undef,'vertical');
return $table;
/emulator.pl
976,7 → 976,8
noc_emulator #(
.STATISTIC_VJTAG_INDEX(STATISTIC_VJTAG_INDEX),
.PATTERN_VJTAG_INDEX(PATTERN_VJTAG_INDEX)
.PATTERN_VJTAG_INDEX(PATTERN_VJTAG_INDEX),
.NOC_ID(0)
)
noc_emulate_top
(
/mpsoc_verilog_gen.pl
46,12 → 46,11
#functions
my $functions=get_functions();
$param_as_in_v = (defined $param_as_in_v)? "$param_as_in_v,\nparameter NOC_ID=0\n" : "parameter NOC_ID=0\n";
my $global_localparam=get_golal_param_v();
my $mpsoc_v = (defined $param_as_in_v )? "`timescale 1ns/1ps\nmodule $mpsoc_name\n\t import pronoc_pkg::*;\n\t #(\n $param_as_in_v\n)(\n$io_short\n);\n": "`timescale 1ns/1ps\nmodule $mpsoc_name\n \t import pronoc_pkg::*;\n\t(\n$io_short\n);\n";
my $pdef = "`include \"pronoc_def.v\"";
my $mpsoc_v = (defined $param_as_in_v )? " $pdef\nmodule $mpsoc_name\n\t #(\n $param_as_in_v)(\n$io_short\n);\n\t`NOC_CONF": "$pdef\nmodule $mpsoc_name\n \t (\n$io_short\n);\n\t`NOC_CONF";
$mpsoc_v=$mpsoc_v. "
$functions
$global_localparam
$socs_param
$io_full
61,7 → 60,7
";
my $top_v = (defined $param_as_in_v )? "`timescale 1ns/1ps\nmodule ${mpsoc_name}_top #(\n $param_as_in_v\n)(\n$top_io_short\n);\n": "`timescale 1ns/1ps\nmodule ${mpsoc_name}_top (\n $top_io_short\n);\n";
my $top_v = (defined $param_as_in_v )? "$pdef\nmodule ${mpsoc_name}_top #(\n $param_as_in_v\n)(\n$top_io_short\n);\n": "$pdef\nmodule ${mpsoc_name}_top (\n $top_io_short\n);\n";
 
$top_v=$top_v."
$global_localparam
461,18 → 460,16
wire noc_clk_in,noc_reset_in;
//NoC
noc_top the_noc
(
noc_top # (
.NOC_ID(NOC_ID)
) the_noc (
.reset(noc_reset_in),
.clk(noc_clk_in),
.chan_in_all(ni_chan_out),
.chan_out_all(ni_chan_in),
.router_event( )
);
);
clk_source src (
.clk_in($noc_clk),
.clk_out(noc_clk_in),
/network_maker.pl
1573,7 → 1573,7
my %L_num;
my @all_endpoints=get_list_of_all_endpoints($self);
foreach my $r (@all_endpoints ){
$R_num{$r} =0;
#$R_num{$r} =0;
}
my @nodes=get_list_of_all_routers($self);
foreach my $p (@nodes){
1582,9 → 1582,11
foreach my $src (@all_endpoints ){
foreach my $dst (@all_endpoints ){
my $path = $self->object_get_attribute('Route',"${src}::$dst");
if (defined $path){
if (defined $path){
#router counting
my @p=@{$path};
shift @p; #remove source node from the path
pop @p; #remove the destination node from the path
foreach my $r (@p){
$R_num{$r} ++;
}
2578,9 → 2580,9
}
my @acyclic_turns = @{$pp};
my %rusage = get_router_usage ($self,\@acyclic_turns);
#step 1: calculate all minimal paths between all source and destination pairs
add_info($info,"Calculate all paths between all source and destination pairs\n");
my @all_endpoints=get_list_of_all_endpoints($self);
2613,7 → 2615,12
my ($paths_to_dst,$ports_to_dst) = get_all_paths_between_two_endps_using_accyclic_turn($self,$src, $dst,\@acyclic_turns);
#my @cyle_free_paths=remove_cycle_paths($self,$info,$paths_to_dst, \@forbiden_turn);
my @cyle_free_paths= @{$paths_to_dst} if (defined $paths_to_dst);
my @sort_paths=sort_paths_based_on_link_usage($self,\@cyle_free_paths);
my @sort_paths=sort_paths_based_on_router_usage($self,\@cyle_free_paths,\%rusage);
# my @sort_paths=sort_paths_based_on_link_usage($self,\@cyle_free_paths);
 
my $path;
my $n=0;
foreach my $p (@sort_paths ){
2701,6 → 2708,51
return %copy;
}
 
 
sub sort_paths_based_on_router_usage{
my ($self,$paths_to_dst,$usage)=@_;
my %scored;
my %usage_r= %{$usage};
#get list of 30% high congested ruters
my @A = sort { $usage_r{$b} <=> $usage_r{$a} } keys %usage_r;
#my $t = (scalar @A)*.3; # %30
my %congested;
foreach my $a ( @A){
$congested{$a}=$usage_r{$a};# if(scalar(keys %congested)<$t);
}
my $i=0;
foreach my $path (@{$paths_to_dst}) {
my $val = 0;
my $num=0;
for my $r (@{$path}){
if(defined $congested{$r}){
$val+=$congested{$r}**1.5;# pow of 3/2 to give higher weight to more congested routers
$num++;
}
}
$scored{$i}=($num==0)? 0 : $val/$num; #average weight of congested routers
$i++;
}
my @order = sort { $scored{$a} <=> $scored{$b} } keys %scored;
my @sorted;
$i=0;
foreach my $a ( @order){
$sorted[$i]=${$paths_to_dst}[$a];
$i++;
#print "\$max{$a}=$max{$a},"
}
#print "\n";
return @sorted;
}
 
 
sub sort_paths_based_on_link_usage{
my ($self,$paths_to_dst)=@_;
2714,6 → 2766,7
if (defined $path){
#path counting
my @p= get_adjacent_router_in_a_path($path);
foreach my $r (@p){
$L_num{$r} ++;
}
2754,6 → 2807,34
}
 
 
sub get_router_usage{
my ($self,$acycle_turn_ref)=@_;
my @all_endpoints=get_list_of_all_endpoints($self);
my %router_cnt;
#get router counts
foreach my $src (@all_endpoints ){
foreach my $dst (@all_endpoints ){
#get list of all path between a source and destination nodes
my ($paths_to_dst,$ports_to_dst)= get_all_paths_between_two_endps_using_accyclic_turn($self,$src, $dst,$acycle_turn_ref);
my @paths = @{$paths_to_dst};
foreach my $path (@paths){
shift @{$path}; #remove source node from the path
pop @{$path}; #remove the destination node from the path
foreach my $q ( @{$path}){
$router_cnt{"$q"} = ( defined $router_cnt{"$q"})? $router_cnt{"$q"}+1 : 1;
}
}
}
}
return %router_cnt;
}
 
 
sub check_cyclick_loop{
my ($self,$paths_to_dst)=@_;
/simulator.pl
1893,7 → 1893,7
$chart = gen_multiple_charts ($simulate,\@pages,\@charts,0.4);
$ctrl = noc_sim_ctrl ($simulate,$info);
$main_table->attach ($ctrl,0, 12, 24,25,'fill','fill',2,2);
$v1 -> pack1($conf_box, TRUE, TRUE);
$v1 -> pack1($conf_box, TRUE, TRUE);
$v1 -> pack2($image, TRUE, TRUE);
$v2 -> pack2($chart, TRUE, TRUE);
/soc_gen.pl
756,7 → 756,7
close(FILE) || die "Error closing file: $!";
# Write verilog file
my $h=autogen_warning().get_license_header("${name}.sv")."\n`timescale 1ns / 1ps\n";
my $h=autogen_warning().get_license_header("${name}.sv")."\n";
open(FILE, ">lib/verilog/$name.sv") || die "Can not open: $!";
print FILE $h.$file_v;
close(FILE) || die "Error closing file: $!";
/topology.pl
130,7 → 130,7
for (my $i = 0; $i <$l; $i=$i+1 ) {
$tmp=int($pos/$pow);
$tmp=$tmp % $k;
$tmp=$tmp<<($i)*$kw;
$tmp=$tmp << ($i)*$kw;
$addrencode=$addrencode | $tmp;
$pow=$pow * $k;
}
143,7 → 143,7
my $mask=0;
my $pow; my $tmp;
my $pos=0;
while((0x1<<$kw) < $k){
while((0x1 << $kw) < $k){
$kw++;
$mask<<=1;
$mask|=0x1;
237,7 → 237,7
my $NXw=log2($T1);
my $NYw=log2($T2);
my $addrencode=0;
$addrencode = ($p<<($NXw+$NYw)| ($y << $NXw) | $x);
$addrencode = ($p << ($NXw+$NYw)| ($y << $NXw) | $x);
return $addrencode;
}
 
299,8 → 299,10
my $T3=$self->object_get_attribute('noc_param','T3');
if($topology eq '"FATTREE"' || $topology eq '"TREE"') {
return fattree_addrencode($id, $T1, $T2);
}elsif ($topology eq '"RING"' || $topology eq '"LINE"' || $topology eq '"MESH"' || $topology eq '"TORUS"'){
}elsif ($topology eq '"MESH"' || $topology eq '"TORUS"'){
return mesh_tori_addrencode($id,$T1, $T2,$T3);
}elsif ($topology eq '"RING"' || $topology eq '"LINE"'){
return ring_line_addrencode($id,$T1, $T3);
}elsif ($topology eq '"FMESH"' ){
return fmesh_addrencode($id,$T1, $T2,$T3);
}else{#CUSTOM & STAR
332,7 → 334,7
my $k=shift;
my $kw=0;
my $mask=0;
while((0x1<<$kw) < $k){
while((0x1 << $kw) < $k){
$kw++;
$mask<<=1;
$mask|=0x1;
360,6 → 362,12
return mesh_tori_addr_join($x,$y,$l,$T1, $T2,$T3);
}
 
sub ring_line_addrencode {
my ($id,$T1, $T3)=@_;
my ($x,$y,$l)=mesh_tori_addrencod_sep($id,$T1,0,$T3);
return ring_line_addr_join($x,$y,$l,$T1, $T3);
}
 
sub mesh_tori_addrencod_sep{
my ($id,$T1,$T2,$T3)=@_;
my ($x,$y,$l);
375,11 → 383,20
my $NXw=log2($T1);
my $NYw=log2($T2);
my $addrencode=0;
$addrencode =($T3==1)? ($y << $NXw | $x) : ($l<<($NXw+$NYw)| ($y << $NXw) | $x);
$addrencode =($T3==1)? ($y << $NXw | $x) : ($l << ($NXw+$NYw)| ($y << $NXw) | $x);
return $addrencode;
}
 
sub ring_line_addr_join {
my ($x, $y, $l,$T1, $T3)=@_;
my $NXw=log2($T1);
my $addrencode=0;
$addrencode =($T3==1)? $x : ($l << $NXw) | $x;
return $addrencode;
}
 
 
 
sub mcast_partial_width {
my ($p,$NE)=@_;
my $m=0;
424,8 → 441,6
my $DAw = ($CAST_TYPE eq '"UNICAST"') ? $EAw: $MCASTw + $DAw_OFFSETw;
print "$DAw=$DAw\n";
 
my $custom_include="";
if($topology eq '"FATTREE"') {
my $K = $T1;
623,7 → 638,8
update_router_st(
NR${i}_PNUM,
router${i}[i]->current_r_id,
router${i}[i]->router_event
router${i}[i]->router_event,
sizeof(router${i}[i]->router_event[0])
);
return;
}
679,16 → 695,13
}
 
#define SMART_NUM ((SMART_MAX==0)? 1 : SMART_MAX)
#if SMART_NUM > 8
typedef unsigned int EVENT;
#else
typedef unsigned char EVENT;
#endif
 
 
extern void update_router_st (
unsigned int,
unsigned int,
EVENT *
void * ,
size_t
);
void single_router_st_update(int i){
/topology_verilog_gen.pl
134,28 → 134,15
print $fd "
module ${name}_noc
import pronoc_pkg::*;
(
$ports
#(
parameter NOC_ID=0
)
(
$ports
);
function integer log2;
input integer number; begin
log2=(number <=1) ? 1: 0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
 
localparam
NE = $NE,
NR = $NR,
RAw=log2(NR);
 
`NOC_CONF
input reset,clk;
$wires
209,6 → 196,7
* $instance
*******************/
router_top #(
.NOC_ID(NOC_ID),
.P($Pnum)
)
$instance
467,6 → 455,7
assign current_r_addr [RID] = RID[RAw-1: 0];
 
router_top #(
.NOC_ID(NOC_ID),
.P($i)
)
router_${i}_port
511,9 → 500,10
print $fd "
module ${name}_noc_genvar
import pronoc_pkg::*;
(
module ${name}_noc_genvar
#(
parameter NOC_ID=0
)(
 
reset,
clk,
522,21 → 512,7
router_event
);
 
function integer log2;
input integer number; begin
log2=(number <=1) ? 1: 0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
 
localparam
NE = $NE,
NR = $NR,
RAw=log2(NR),
MAX_P=$MAX_P;
`NOC_CONF
$ports_def
 
628,6 → 604,7
my $router_v="
router_top #(
.NOC_ID(NOC_ID),
.P($Pnum)
)
router_${Pnum}_port
1446,45 → 1423,21
print $fd "
module ${name}_connection
import pronoc_pkg::*;
(
#(
parameter NOC_ID=0
)(
$ports
);
 
function integer log2;
input integer number; begin
log2=(number <=1) ? 1: 0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
`NOC_CONF
 
localparam
NE = $NE,
NR = $NR,
RAw=log2(NR),
MAX_P=$MAX_P;
localparam
P= MAX_P,
PV = V * P,
PFw = P * Fw,
CONG_ALw = CONGw * P,
PRAw = P * RAw;
 
PRAw = P * RAw;
$ports_def
 
1564,7 → 1517,7
if(TOPOLOGY == \"$name\" && ROUTE_NAME== \"$rname\" ) begin : $Vname
${Vname}_conventional_routing #(
.RAw(RAw),
.RAw(RAw),
.EAw(EAw),
.DSTPw(DSTPw)
)
1679,8 → 1632,9
//do not modify this line ===${name}===
if(TOPOLOGY == \"$name\" ) begin : T$name
${name}_connection connection
(
${name}_connection #(
.NOC_ID(NOC_ID)
) connection (
$ports
);
1725,16 → 1679,15
$ports="\t\t.reset(reset),
\t\t.clk(clk)";
$str="
//do not modify this line ===${name}===
if(TOPOLOGY == \"$name\" ) begin : T$name
${name}_noc_genvar the_noc
(
${name}_noc_genvar #(
.NOC_ID(NOC_ID)
) the_noc (
.reset(reset),
.clk(clk),
.chan_in_all(chan_in_all),
/verilog_gen.pl
89,10 → 89,11
$sockets_assign_v_all="" if(!defined $sockets_assign_v_all);
 
my $has_ni =check_for_ni($soc);
my $import = ($has_ni)? "\n\timport pronoc_pkg::*;\n" : "";
my $import = ($has_ni)? "\n\t`NOC_CONF\n" : "";
my $tscale = ($has_ni)? "`include \"pronoc_def.v\"\n" : "`timescale 1ns / 1ps\n";
 
my $global_localparam=get_golal_param_v();
my $soc_v = (defined $param_as_in_v_all )? "module $soc_name $import #(\n $param_as_in_v_all\n)(\n$io_sim_v_all\n);\n": "module $soc_name (\n$io_sim_v_all\n);\n";
my $soc_v = (defined $param_as_in_v_all )? "$tscale module $soc_name #(\n $param_as_in_v_all\n)(\n$io_sim_v_all\n);\n$import\n": "$tscale module $soc_name (\n$io_sim_v_all\n);\n $import\n";
$soc_v = $soc_v."
$functions_all
$system_v_all
125,7 → 126,7
my @chains = (sort { $b <=> $a } keys %jtag_info);
$soc->object_add_attribute('JTAG','M_CHAIN',$chains[0]);
my $top_v = (defined $param_as_in_v_all )? "module ${soc_name}_top $import #(\n $param_as_in_v_all\n)(\n$top_io_short_all\n);\n": "module ${soc_name}_top (\n $top_io_short_all\n);\n";
my $top_v = (defined $param_as_in_v_all )? "module ${soc_name}_top #(\n $param_as_in_v_all\n)(\n$top_io_short_all\n);\n": "module ${soc_name}_top (\n $top_io_short_all\n);\n $import ";
#my $ins= gen_soc_instance_v($soc,$soc_name,$param_pass_v,$txview);
1294,7 → 1295,7
# $top_io_pass_all=$top_io_pass_all.",\n$clk_assigned_port";
my $has_ni =check_for_ni($soc);
my $import = ($has_ni)? "\n\timport pronoc_pkg::*;\n" : "";
my $import = ($has_ni)? "\n\t`NOC_CONF\n" : "";
my $verilator_v = "
/*********************
1301,7 → 1302,7
${name}
*********************/
module ${name} $import (\n $top_io_short_all\n);\n";
module ${name} (\n $top_io_short_all\n);\n $import \n";
my $ins= gen_soc_instance_v_no_modfy($soc,$soc_name,$param_pass_v_all);
$verilator_v.="
$functions_all
/widget3.pl
2204,21 → 2204,11
my $cmd=shift;
my $exit;
my ($stdout, $stderr);
#open(OLDERR, ">&STDERR");
#open(STDERR, ">>/tmp/tmp.spderr") or die "Can't dup stdout";
#select(STDOUT); $| = 1; # make unbuffered
#print OLDERR ""; #this fixed an error about OLDERR not being used
 
## do my stuff here.
STDOUT->flush();
STDERR->flush();
capture { $exit=run_cmd_in_back_ground($cmd) } \$stdout, \$stderr;
#close(STDERR);
#open(STDERR, ">&OLDERR");
return ($stdout,$exit,$stderr);
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.