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/filelist.f
2,5 → 2,7
#./testbench_noc.sv
./traffic_pattern.sv
./pck_injector_test.sv
./noc_sim_statistic.sv
 
 
 
/multicast_injector.sv
0,0 → 1,660
`timescale 1ns/1ps
/****************************
* This module can inject and eject packets from the NoC.
* It can be used in simulation for injecting real application traces to the NoC
* *************************/
 
 
module multicast_injector
import pronoc_pkg::*;
(
//general
current_e_addr,
reset,
clk,
//noc port
chan_in,
chan_out,
//control interafce
pck_injct_in,
pck_injct_out
);
//general
input reset,clk;
input [EAw-1 :0 ] current_e_addr;
// the destination endpoint address
//NoC interface
input smartflit_chanel_t chan_in;
output smartflit_chanel_t chan_out;
//control interafce
input pck_injct_t pck_injct_in;
output pck_injct_t pck_injct_out;
wire [RAw-1 :0 ] current_r_addr;
wire [DSTPw-1 : 0 ] destport;
reg flit_wr;
assign current_r_addr = chan_in.ctrl_chanel.neighbors_r_addr;
/*
conventional_routing #(
.TOPOLOGY(TOPOLOGY),
.ROUTE_NAME(ROUTE_NAME),
.ROUTE_TYPE(ROUTE_TYPE),
.T1(T1),
.T2(T2),
.T3(T3),
.RAw(RAw),
.EAw(EAw),
.DSTPw(DSTPw),
.LOCATED_IN_NI(1)
)
routing_module
(
.reset(reset),
.clk(clk),
.current_r_addr(current_r_addr),
.dest_e_addr(pck_injct_in.endp_addr),
.src_e_addr(current_e_addr),
.destport(destport)
);
*/
 
assign destport = 7;
 
 
localparam
HDR_BYTE_NUM = HDR_MAX_DATw / 8, // = HDR_MAX_DATw / (8 - HDR_MAX_DATw %8)
HDR_DATA_w_tmp = HDR_BYTE_NUM * 8,
HDR_DATA_w = (PCK_INJ_Dw < HDR_DATA_w_tmp)? PCK_INJ_Dw : HDR_DATA_w_tmp;
 
wire [HDR_DATA_w-1 : 0] hdr_data_in = pck_injct_in.data [HDR_DATA_w-1 : 0];
wire [Fw-1 : 0] hdr_flit_out;
header_flit_generator #(
.DATA_w(HDR_DATA_w)
)
the_header_flit_generator
(
.flit_out (hdr_flit_out),
.vc_num_in (pck_injct_in.vc),
.class_in (pck_injct_in.class_num),
.dest_e_addr_in (pck_injct_in.endp_addr),
.src_e_addr_in (current_e_addr),
.weight_in (pck_injct_in.init_weight),
.destport_in (destport),
.data_in (hdr_data_in),
.be_in({BEw{1'b1}} )// Be is not used in simulation as we dont sent real data
);
localparam
REMAIN_DATw = PCK_INJ_Dw - HDR_DATA_w,
REMAIN_DAT_FLIT_I = (REMAIN_DATw / Fpay),
REMAIN_DAT_FLIT_F = (REMAIN_DATw % Fpay == 0)? 0 : 1,
REMAIN_DAT_FLIT = REMAIN_DAT_FLIT_I + REMAIN_DAT_FLIT_F,
CNTw = log2(REMAIN_DAT_FLIT),
MIN_PCK_SIZ = REMAIN_DAT_FLIT +1;
reg [PCK_SIZw-1 : 0] counter, counter_next;
reg [CNTw-1 : 0] counter2,counter2_next;
reg tail,head;
wire [Fpay -1 : 0] remain_dat [REMAIN_DAT_FLIT -1 : 0];
wire [Fpay-1 : 0] dataIn = remain_dat[counter2];
enum {HEADER, BODY,TAIL} flit_type,flit_type_next;
wire [V-1 : 0] wr_vc_send = (flit_wr)? pck_injct_in.vc : {V{1'b0}};
wire [V-1 : 0] vc_fifo_full;
wire noc_ready;
localparam
LAST_TMP =PCK_INJ_Dw - (Fpay*REMAIN_DAT_FLIT_I)-HDR_DATA_w,
LASTw=(LAST_TMP==0)? Fpay : LAST_TMP;
genvar i;
generate
for(i=0; i<REMAIN_DAT_FLIT_I; i++) begin
assign remain_dat [i] = pck_injct_in.data [Fpay*(i+1)+HDR_DATA_w-1 : (Fpay*i)+HDR_DATA_w];
end
if(REMAIN_DAT_FLIT_F ) begin
 
assign remain_dat [REMAIN_DAT_FLIT_I][LASTw-1 : 0] = pck_injct_in.data [PCK_INJ_Dw-1 : (Fpay*REMAIN_DAT_FLIT_I)+HDR_DATA_w];
end
endgenerate
one_hot_mux #(
.IN_WIDTH (V ),
.SEL_WIDTH (V ),
.OUT_WIDTH (1 )
) one_hot_mux1 (
.mux_in (~ vc_fifo_full ),
.mux_out (noc_ready ),
.sel (pck_injct_in.vc ));
always @ (*) begin
counter_next = counter;
counter2_next =counter2;
flit_type_next =flit_type;
tail=1'b0;
head=1'b0;
flit_wr=0;
if(noc_ready)begin
case(flit_type)
HEADER:begin
if(pck_injct_in.pck_wr)begin
flit_wr=1;
counter_next = pck_injct_in.size-1;
counter2_next=0;
head=1'b1;
if(pck_injct_in.size == 1)begin
tail=1'b1;
end else if (pck_injct_in.size == 2) begin
flit_type_next = TAIL;
end else begin
flit_type_next = BODY;
end
end
end
BODY: begin
flit_wr=1;
counter_next = counter -1'b1;
counter2_next =counter2 +1'b1;
if(counter == 2) begin
flit_type_next = TAIL;
end
end
TAIL: begin
flit_type_next = HEADER;
flit_wr=1;
tail=1'b1;
end
endcase
end
end
reg [V-1 : 0] credit_o;
always @ (posedge clk) begin
if(reset) begin
flit_type<=HEADER;
counter<=0;
counter2<=0;
credit_o<={V{1'b0}};
end else begin
flit_type<=flit_type_next;
counter<=counter_next;
counter2<=counter2_next;
if (chan_in.flit_chanel.flit_wr) credit_o<= chan_in.flit_chanel.flit.vc;
else credit_o<={V{1'b0}};
end
end
injector_ovc_status #(
.V(V),
.B(LB),
.CRDTw(CRDTw)
)
the_ovc_status
(
.credit_init_val_in ( chan_in.ctrl_chanel.credit_init_val),
.wr_in(wr_vc_send),
.credit_in(chan_in.flit_chanel.credit),
.full_vc(vc_fifo_full),
.nearly_full_vc( ),
.empty_vc( ),
.clk(clk),
.reset(reset)
);
wire [HDR_DATA_w-1 : 0] hdr_data_o;
hdr_flit_t hdr_flit_i;
header_flit_info
#(
.DATA_w (HDR_DATA_w )
) extractor (
.flit(chan_in.flit_chanel.flit),
.hdr_flit(hdr_flit_i),
.data_o(hdr_data_o)
);
wire [PCK_INJ_Dw-1 : 0] pck_data_o [V-1 : 0];
reg [Fpay-1 : 0] pck_data_o_gen [V-1 : 0][REMAIN_DAT_FLIT : 0];
genvar k;
reg [PCK_SIZw-1 : 0] rsv_counter [V-1 : 0];
reg [EAw-1 : 0] sender_endp_addr_reg [V-1 : 0];
logic [15:0] h2t_counter [V-1 : 0];
logic [15:0] h2t_counter_next [V-1 : 0];
//synthesis translate_off
wire [NEw-1 : 0] current_id;
wire [NEw-1 : 0] sendor_id;
endp_addr_decoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw), .NE(NE)) encode1 ( .id(current_id), .code(current_e_addr));
endp_addr_decoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw), .NE(NE)) encode2 ( .id(sendor_id), .code(pck_injct_out.endp_addr[EAw-1 : 0]));
//synthesis translate_on
generate
for(i=0; i<V; i++) begin: V_
always@(*) begin
h2t_counter_next[i]=h2t_counter[i]+1'b1;
if(chan_in.flit_chanel.flit.vc[i] & chan_in.flit_chanel.flit_wr & chan_in.flit_chanel.flit.hdr_flag)begin
h2t_counter_next[i]= 16'd0; // reset once header flit is received
end//hdr flit wr
end//always
always_ff @(posedge clk or posedge reset) begin
if (reset) begin
rsv_counter[i]<= {PCK_SIZw{1'b0}};
h2t_counter[i]<= 16'd0;
sender_endp_addr_reg [i]<= {EAw{1'b0}};
end else begin
h2t_counter[i]<=h2t_counter_next[i];
if(chan_in.flit_chanel.flit.vc[i] & chan_in.flit_chanel.flit_wr ) begin
if(chan_in.flit_chanel.flit.hdr_flag)begin
rsv_counter[i]<= {{(PCK_SIZw-1){1'b0}}, 1'b1};
sender_endp_addr_reg [i]<= hdr_flit_i.src_e_addr;
//synthesis translate_off
if(hdr_flit_i.dest_e_addr != current_e_addr) begin
$display("%t: ERROR: packet destination address %d does not match reciver endp address %d. %m",$time,hdr_flit_i.dest_e_addr , current_e_addr );
$finish;
end//if hdr_flit_i
//synthesis translate_on
end //if hdr_flag
else rsv_counter[i]<= rsv_counter[i]+1'b1;
end//flit wr
end//reset
end//always
 
for (k=0;k< REMAIN_DAT_FLIT+1;k++)begin : K_
always_ff @(posedge clk or posedge reset) begin
if (reset) begin
pck_data_o_gen [i][k] <= {Fpay{1'b0}};
end else begin
if(chan_in.flit_chanel.flit.vc[i] & chan_in.flit_chanel.flit_wr ) begin
if (chan_in.flit_chanel.flit.hdr_flag )begin
if ( k ==0 ) pck_data_o_gen [i][k][HDR_DATA_w-1 : 0] <= hdr_data_o;
end
else begin
if (rsv_counter[i] == k ) pck_data_o_gen [i][k] <= chan_in.flit_chanel.flit.payload;
end // else
end //if
end //else
end// always
if (k == 0 ) assign pck_data_o [i][HDR_DATA_w-1 : 0] = pck_data_o_gen [i][0][HDR_DATA_w-1 : 0];
else if (k == REMAIN_DAT_FLIT) assign pck_data_o [i][PCK_INJ_Dw-1 : (k-1)*Fpay+ HDR_DATA_w] = pck_data_o_gen [i][k][LASTw-1: 0];
else assign pck_data_o [i][(k)*Fpay+HDR_DATA_w -1 : (k-1)*Fpay+ HDR_DATA_w] = pck_data_o_gen [i][k];
end //for k
//synthesis translate_off
always @(posedge clk) begin
if((pck_injct_out.ready[i] == 1'b0 ) & pck_injct_in.vc[i] & pck_injct_in.pck_wr )begin
$display("%t: ERROR: a packet injection request is recived in core(%d), vc (%d) while packet injectore was not ready. %m",$time,current_id,i);
$finish;
end
end
//synthesis translate_on
end//for i
endgenerate
wire [V-1 : 0] vc_reg;
wire tail_flag_reg, hdr_flag_reg;
pronoc_register #(.W(V)) register1 (.in(chan_in.flit_chanel.flit.vc), .reset (reset ), .clk (clk),.out(vc_reg));
pronoc_register #(.W(1)) register2 (.in(chan_in.flit_chanel.flit.hdr_flag), .reset (reset ), .clk (clk),.out(hdr_flag_reg));
pronoc_register #(.W(1)) register3 (.in(chan_in.flit_chanel.flit.tail_flag & chan_in.flit_chanel.flit_wr ),.reset (reset ), .clk (clk),.out(tail_flag_reg));
wire [Vw-1 : 0] vc_bin;
one_hot_to_bin #(
.ONE_HOT_WIDTH (V),
.BIN_WIDTH (Vw )
) one_hot_to_bin (
.one_hot_code (vc_reg ),
.bin_code (vc_bin )
);
 
assign pck_injct_out.data = pck_data_o[vc_bin];
assign pck_injct_out.size = rsv_counter[vc_bin];
assign pck_injct_out.h2t_delay = h2t_counter[vc_bin];
assign pck_injct_out.ready = (flit_type == HEADER)? ~vc_fifo_full : {V{1'b0}};
assign pck_injct_out.endp_addr = sender_endp_addr_reg[vc_bin];
assign pck_injct_out.vc = vc_reg;
assign pck_injct_out.pck_wr = tail_flag_reg;
assign chan_out.flit_chanel.flit.hdr_flag =head;
assign chan_out.flit_chanel.flit.tail_flag=tail;
assign chan_out.flit_chanel.flit.vc=pck_injct_in.vc;
assign chan_out.flit_chanel.flit_wr=flit_wr;
 
assign chan_out.flit_chanel.flit.payload = (flit_type== HEADER)? hdr_flit_out[Fpay-1 : 0] : dataIn;
assign chan_out.smart_chanel = {SMART_CHANEL_w{1'b0}};
assign chan_out.flit_chanel.congestion = {CONGw{1'b0}};
assign chan_out.flit_chanel.credit= credit_o;
assign chan_out.ctrl_chanel.credit_init_val= LB;
assign chan_out.ctrl_chanel.endp_port =1'b1;
distance_gen #(
.TOPOLOGY(TOPOLOGY),
.T1(T1),
.T2(T2),
.T3(T3),
.EAw(EAw),
.DISTw(DISTw)
)
the_distance_gen
(
.src_e_addr(sender_endp_addr_reg[vc_bin]),
.dest_e_addr(current_e_addr),
.distance(pck_injct_out.distance)
);
//synthesis translate_off
//`define MONITOR_RSV_DAT
 
always @(posedge clk) begin
if((pck_injct_in.vc == {V{1'b0}} ) & pck_injct_in.pck_wr )begin
$display("%t: ERROR: a packet injection request is recived while vc is not set. %m",$time);
$finish;
end
if(pck_injct_in.pck_wr && (pck_injct_in.size<MIN_PCK_SIZ[PCK_SIZw-1 : 0])) begin
$display("%t: ERROR: requested %d flit packet size is smaller than minimum %d flits to send %d bits of data. %m",$time,pck_injct_in.size,MIN_PCK_SIZ, PCK_INJ_Dw );
$finish;
end
`ifdef MONITOR_RSV_DAT
if(pck_injct_in.pck_wr) begin
$display ("pck_inj(%d) send a packet: size=%d, data=%h, v=%h",current_id,
pck_injct_in.size, pck_injct_in.data,pck_injct_in.vc);
end
if(pck_injct_out.pck_wr) begin
$display ("pck_inj(%d) got a packet: source=%d, size=%d, data=%h",current_id,
sendor_id,pck_injct_out.size,pck_injct_out.data);
end
`endif
end
//synthesis translate_on
endmodule
 
 
 
 
/******************
* ovc_status
*******************/
module injector_ovc_status #(
parameter V = 4,
parameter B = 16,
parameter CRDTw =4
)
(
input [V-1 : 0] [CRDTw-1 : 0 ] credit_init_val_in,
input [V-1 :0] wr_in,
input [V-1 :0] credit_in,
output [V-1 :0] full_vc,
output [V-1 :0] nearly_full_vc,
output [V-1 :0] empty_vc,
input clk,
input reset
);
 
function integer log2;
input integer number; begin
log2=(number <=1) ? 1: 0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
localparam DEPTH_WIDTH = log2(B+1);
reg [DEPTH_WIDTH-1 : 0] credit [V-1 : 0];
wire [V-1 : 0] cand_vc_next;
genvar i;
generate
for(i=0;i<V;i=i+1) begin : vc_loop
`ifdef SYNC_RESET_MODE
always @ (posedge clk )begin
`else
always @ (posedge clk or posedge reset)begin
`endif
if(reset)begin
credit[i]<= credit_init_val_in[i][DEPTH_WIDTH-1:0];
end else begin
if( wr_in[i] && ~credit_in[i]) credit[i] <= credit[i]-1'b1;
if( ~wr_in[i] && credit_in[i]) credit[i] <= credit[i]+1'b1;
end //reset
end//always
 
assign full_vc[i] = (credit[i] == {DEPTH_WIDTH{1'b0}});
assign nearly_full_vc[i]= (credit[i] == 1) | full_vc[i];
assign empty_vc[i] = (credit[i] == credit_init_val_in[i][DEPTH_WIDTH-1:0]);
end//for
endgenerate
endmodule
 
 
 
 
/**************************************
*
*
* ***********************************/
 
 
 
module packet_injector_verilator
import pronoc_pkg::*;
(
//general
current_e_addr,
reset,
clk,
//noc port
chan_in,
chan_out,
//control interafce
pck_injct_in_data,
pck_injct_in_size,
pck_injct_in_endp_addr,
pck_injct_in_class_num,
pck_injct_in_init_weight,
pck_injct_in_vc,
pck_injct_in_pck_wr,
pck_injct_in_ready,
pck_injct_out_data,
pck_injct_out_size,
pck_injct_out_endp_addr,
pck_injct_out_class_num,
pck_injct_out_init_weight,
pck_injct_out_vc,
pck_injct_out_pck_wr,
pck_injct_out_ready,
pck_injct_out_distance,
pck_injct_out_h2t_delay,
min_pck_size
);
 
 
//general
input reset,clk;
input [EAw-1 :0 ] current_e_addr;
// the destination endpoint address
//NoC interface
input smartflit_chanel_t chan_in;
output smartflit_chanel_t chan_out;
//control interafce
input [PCK_INJ_Dw-1 : 0] pck_injct_in_data;
input [PCK_SIZw-1 : 0] pck_injct_in_size;
input [EAw-1 : 0] pck_injct_in_endp_addr;
input [Cw-1 : 0] pck_injct_in_class_num;
input [WEIGHTw-1 : 0] pck_injct_in_init_weight;
input [V-1 : 0] pck_injct_in_vc;
input pck_injct_in_pck_wr;
input [V-1 : 0] pck_injct_in_ready;
 
output [PCK_INJ_Dw-1 : 0] pck_injct_out_data;
output [PCK_SIZw-1 : 0] pck_injct_out_size;
output [EAw-1 : 0] pck_injct_out_endp_addr;
output [Cw-1 : 0] pck_injct_out_class_num;
output [WEIGHTw-1 : 0] pck_injct_out_init_weight;
output [V-1 : 0] pck_injct_out_vc;
output pck_injct_out_pck_wr;
output [V-1 : 0] pck_injct_out_ready;
output [DISTw-1 : 0] pck_injct_out_distance;
output [15 : 0] pck_injct_out_h2t_delay;
output [4 : 0] min_pck_size;
pck_injct_t pck_injct_in;
pck_injct_t pck_injct_out;
 
assign pck_injct_in.data = pck_injct_in_data;
assign pck_injct_in.size = pck_injct_in_size;
assign pck_injct_in.endp_addr = pck_injct_in_endp_addr;
assign pck_injct_in.class_num = pck_injct_in_class_num;
assign pck_injct_in.init_weight = pck_injct_in_init_weight;
assign pck_injct_in.vc = pck_injct_in_vc;
assign pck_injct_in.pck_wr = pck_injct_in_pck_wr;
assign pck_injct_in.ready = pck_injct_in_ready;
assign pck_injct_out_data = pck_injct_out.data;
assign pck_injct_out_size = pck_injct_out.size;
assign pck_injct_out_endp_addr = pck_injct_out.endp_addr;
assign pck_injct_out_class_num = pck_injct_out.class_num;
assign pck_injct_out_init_weight = pck_injct_out.init_weight;
assign pck_injct_out_vc = pck_injct_out.vc;
assign pck_injct_out_pck_wr = pck_injct_out.pck_wr;
assign pck_injct_out_ready = pck_injct_out.ready;
assign pck_injct_out_distance = pck_injct_out.distance;
assign pck_injct_out_h2t_delay = pck_injct_out.h2t_delay;
packet_injector injector (
.current_e_addr (current_e_addr ),
.reset (reset ),
.clk (clk ),
.chan_in (chan_in ),
.chan_out (chan_out ),
.pck_injct_in (pck_injct_in ),
.pck_injct_out (pck_injct_out ));
localparam
HDR_BYTE_NUM = HDR_MAX_DATw / 8, // = HDR_MAX_DATw / (8 - HDR_MAX_DATw %8)
HDR_DATA_w_tmp = HDR_BYTE_NUM * 8,
HDR_DATA_w = (PCK_INJ_Dw < HDR_DATA_w_tmp)? PCK_INJ_Dw : HDR_DATA_w_tmp,
REMAIN_DATw = PCK_INJ_Dw - HDR_DATA_w,
REMAIN_DAT_FLIT_I = (REMAIN_DATw / Fpay),
REMAIN_DAT_FLIT_F = (REMAIN_DATw % Fpay == 0)? 0 : 1,
REMAIN_DAT_FLIT = REMAIN_DAT_FLIT_I + REMAIN_DAT_FLIT_F,
CNTw = log2(REMAIN_DAT_FLIT),
MIN_PCK_SIZ = REMAIN_DAT_FLIT +1;
assign min_pck_size = MIN_PCK_SIZ[4:0];
 
 
// `ifdef VERILATOR
// logic endp_is_active /*verilator public_flat_rd*/ ;
//
// always @ (*) begin
// endp_is_active = 1'b0;
// if (chan_out.flit_chanel.flit_wr) endp_is_active=1'b1;
// if (chan_out.flit_chanel.credit > {V{1'b0}} ) endp_is_active=1'b1;
// if (chan_out.smart_chanel.requests > {SMART_NUM{1'b0}} ) endp_is_active=1'b1;
// end
// `endif
endmodule
/multicast_test.sv
0,0 → 1,126
// synthesis translate_off
`timescale 1ns/1ns
 
 
module multicast_test;
import pronoc_pkg::*;
reg reset ,clk;
initial begin
clk = 1'b0;
forever clk = #10 ~clk;
end
smartflit_chanel_t chan_in_all [NE-1 : 0];
smartflit_chanel_t chan_out_all [NE-1 : 0];
pck_injct_t pck_injct_in [NE-1 : 0];
pck_injct_t pck_injct_out[NE-1 : 0];
noc_top the_noc
(
.reset(reset),
.clk(clk),
.chan_in_all(chan_in_all),
.chan_out_all(chan_out_all),
.router_event( )
);
reg [NEw-1 : 0] dest_id [NE-1 : 0];
wire [NEw-1: 0] current_e_addr [NE-1 : 0];
genvar i;
generate
for(i=0; i< NE; i=i+1) begin : endpoints
endp_addr_encoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw), .NE(NE)) encode1 ( .id(i[NEw-1 :0]), .code(current_e_addr[i]));
multicast_injector pck_inj(
//general
.current_e_addr(current_e_addr[i]),
.reset(reset),
.clk(clk),
//noc port
.chan_in(chan_out_all[i]),
.chan_out(chan_in_all[i]),
//control interafce
.pck_injct_in(pck_injct_in[i]),
.pck_injct_out(pck_injct_out[i])
);
 
endp_addr_encoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw), .NE(NE)) encode2 ( .id(dest_id[i]), .code(pck_injct_in[i].endp_addr[EAw-1 : 0]));
reg [31:0]k;
 
initial begin
reset = 1'b1;
k=0;
pck_injct_in[i].data =0;
#10
pck_injct_in[i].class_num=0;
pck_injct_in[i].init_weight=1;
pck_injct_in[i].vc=1;
pck_injct_in[i].pck_wr=1'b0;
#100
@(posedge clk) #1;
reset=1'b0;
#100
@(posedge clk) #1;
//if(i==1) begin
// repeat(10) begin
while (pck_injct_out[i].ready[0] == 1'b0) @(posedge clk) #1;
pck_injct_in[i].data='h123456789ABCDEFEDCBA987654321+k;
pck_injct_in[i].size=3+(k%18);
dest_id[i]=0;
pck_injct_in[i].pck_wr=1'b1;
@(posedge clk) #1 k++;
pck_injct_in[i].pck_wr=1'b0;
@(posedge clk) #1 k++;
 
// end
 
#10000
@(posedge clk) $stop;
 
//end
end
always @(posedge clk) begin
if(pck_injct_out[i].pck_wr) begin
$display ("%t:pck_inj(%d) got a packet: source=%d, size=%d, data=%h",$time,i,
pck_injct_out[i].endp_addr,pck_injct_out[i].size,pck_injct_out[i].data);
end
end
end//for
endgenerate
 
 
 
 
 
endmodule
// synthesis translate_on
 
multicast_test.sv Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: noc_sim_statistic.sv =================================================================== --- noc_sim_statistic.sv (nonexistent) +++ noc_sim_statistic.sv (revision 54) @@ -0,0 +1,128 @@ +// synthesis translate_off +`timescale 1ns/1ns +`include "pronoc_def.v" +module routers_statistic_collector + import pronoc_pkg::*; + ( + reset, + clk, + router_event, + print + ); + + + input clk,reset; + input router_event_t router_event [NR-1 : 0][MAX_P-1 : 0]; + input print; + + typedef struct { + integer pck_num_in; + integer flit_num_in; + integer pck_num_out; + integer flit_num_out; + integer flit_num_in_bypassed; + integer flit_num_in_buffered; + integer bypass_counter [SMART_NUM : 0]; + } router_stat_t; + + + + task reset_router_stat; + output router_stat_t stat_in; + integer k; + begin + stat_in.pck_num_in=0; + stat_in.flit_num_in=0; + stat_in.pck_num_out=0; + stat_in.flit_num_out=0; + stat_in.flit_num_in_bypassed=0; + stat_in.flit_num_in_buffered=0; + for (k=0;k0) for (k=0;k0) for (k=0;k
noc_sim_statistic.sv Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: pck_injector_test.sv =================================================================== --- pck_injector_test.sv (revision 48) +++ pck_injector_test.sv (revision 54) @@ -26,7 +26,8 @@ .reset(reset), .clk(clk), .chan_in_all(chan_in_all), - .chan_out_all(chan_out_all) + .chan_out_all(chan_out_all), + .router_event( ) ); reg [NEw-1 : 0] dest_id [NE-1 : 0];
/testbench_noc.sv
150,17 → 150,17
 
 
reg print_router_st;
smartflit_chanel_t chan_in_all [NE-1 : 0];
smartflit_chanel_t chan_out_all [NE-1 : 0];
router_event_t router_event [NR-1 : 0] [MAX_P-1 : 0];
wire [NE-1 : 0] hdr_flit_sent;
wire [EAw-1 : 0] dest_e_addr [NE-1 :0];
wire [DAw-1 : 0] dest_e_addr [NE-1 :0];
wire [EAw-1 : 0] src_e_addr [NE-1 :0];
wire [Cw-1 : 0] pck_class_in [NE-1 :0];
wire [Cw-1 : 0] flit_out_class [NE-1 :0];
168,8 → 168,8
wire [PCK_SIZw-1: 0] pck_size_in [NE-1 :0];
wire [PCK_SIZw-1: 0] pck_size_o [NE-1 :0];
wire [NEw-1 : 0] mcast_dst_num [NE-1 :0];
// wire [NE-1 :0] report;
reg [CLK_CNTw-1 :0] clk_counter;
210,7 → 210,8
.reset(reset),
.clk(clk),
.chan_in_all(chan_in_all),
.chan_out_all(chan_out_all)
.chan_out_all(chan_out_all),
.router_event(router_event)
);
267,7 → 268,8
traffic_gen_top #(
.MAX_RATIO(100)
.MAX_RATIO(100),
.ENDP_ID(i)
)
the_traffic_gen
(
297,7 → 299,8
.start_delay(start_delay[i]),
.flit_out_class(flit_out_class[i]),
.flit_out_wr(),
.flit_in_wr()
.flit_in_wr(),
.mcast_dst_num_o(mcast_dst_num[i])
);
338,7 → 341,15
.NE(NE),
.MAX_PCK_NUM(MAX_PCK_NUM),
.TRAFFIC(TRAFFIC),
.HOTSPOT_NODE_NUM(HOTSPOT_NODE_NUM)
.HOTSPOT_NODE_NUM(HOTSPOT_NODE_NUM),
.MCAST_TRAFFIC_RATIO(MCAST_TRAFFIC_RATIO),
.MCAST_PCK_SIZ_MIN(MCAST_PCK_SIZ_MIN),
.MCAST_PCK_SIZ_MAX(MCAST_PCK_SIZ_MAX),
.PCK_SIZw(PCK_SIZw),
.MIN_PACKET_SIZE(MIN_PACKET_SIZE),
.MAX_PACKET_SIZE(MAX_PACKET_SIZE),
.PCK_SIZ_SEL(PCK_SIZ_SEL),
.DISCRETE_PCK_SIZ_NUM(DISCRETE_PCK_SIZ_NUM)
)
the_pck_dst_gen
(
351,25 → 362,13
.dest_e_addr(dest_e_addr[i]),
.valid_dst(valid_dst[i]),
.hotspot_info(hotspot_info),
.pck_size_o( pck_size_in[i]) ,
.rnd_discrete(rnd_discrete),
.custom_traffic_t(custom_traffic_t[i]), // defined in sim_param.sv
.custom_traffic_en(custom_traffic_en[i]) // defined in sim_param.sv
);
pck_size_gen #(
.PCK_SIZw(PCK_SIZw),
.MIN(MIN_PACKET_SIZE),
.MAX(MAX_PACKET_SIZE),
.PCK_SIZ_SEL(PCK_SIZ_SEL),
.DISCRETE_PCK_SIZ_NUM(DISCRETE_PCK_SIZ_NUM)
)
the_pck_siz_gen
(
.reset(reset),
.clk(clk),
.en(hdr_flit_sent[i]),
.pck_size( pck_size_in[i]) ,
.rnd_discrete(rnd_discrete)
);
end
endgenerate
394,7 → 393,7
integer sent_core_worst_delay [NE-1 : 0];
integer total_active_endp;
integer total_rsv_pck_num,total_rsv_flit_number;
integer total_sent_pck_num,total_sent_flit_number;
integer total_sent_pck_num,total_sent_flit_number,total_expect_rsv_flit_num;
integer core_num,k;
always @(posedge clk or posedge reset)begin
407,6 → 406,7
sum_clk_per_hop=0;
total_sent_flit_number=0;
total_rsv_flit_number=0;
total_expect_rsv_flit_num=0;
for (k=0;k<C;k=k+1) begin
sum_clk_pow2_per_class[k]=0;
total_rsv_pck_num_per_class[k]=0;
427,6 → 427,10
for (core_num=0; core_num<NE; core_num=core_num+1)begin
if(chan_in_all[core_num].flit_chanel.flit_wr)begin
total_sent_flit_number+=1;
if (CAST_TYPE != "UNICAST") total_expect_rsv_flit_num+=mcast_dst_num[core_num];
else total_expect_rsv_flit_num++;
if (C>1) sent_stat [core_num][flit_out_class[core_num]].flit_num++;
else sent_stat [core_num][0].flit_num++;
if(chan_in_all[core_num].flit_chanel.flit[Fw-1])begin
476,11 → 480,11
sum_clk_pow2+=time_stamp_h2h[core_num] * time_stamp_h2h[core_num];
sum_clk_pow2_per_class[pck_class_out[core_num]]+=time_stamp_h2h[core_num] * time_stamp_h2h[core_num];
`endif
sum_clk_per_hop+= $itor(time_stamp_h2h[core_num])/$itor(distance[core_num]);
if(distance[core_num] > 0) sum_clk_per_hop+= $itor(time_stamp_h2h[core_num])/$itor(distance[core_num]);
total_rsv_pck_num_per_class[pck_class_out[core_num]]+=1;
sum_clk_h2h_per_class[pck_class_out[core_num]]+=time_stamp_h2h[core_num] ;
sum_clk_h2t_per_class[pck_class_out[core_num]]+=time_stamp_h2t[core_num] ;
sum_clk_per_hop_per_class[pck_class_out[core_num]]+= $itor(time_stamp_h2h[core_num])/$itor(distance[core_num]);
if(distance[core_num]>0) sum_clk_per_hop_per_class[pck_class_out[core_num]]+= $itor(time_stamp_h2h[core_num])/$itor(distance[core_num]);
rsvd_core_total_rsv_pck_num[core_num]+=1;
if (rsvd_core_worst_delay[core_num] < time_stamp_h2t[core_num]) rsvd_core_worst_delay[core_num] = ( AVG_LATENCY_METRIC == "HEAD_2_TAIL")? time_stamp_h2t[core_num] : time_stamp_h2h[core_num];
if (sent_core_worst_delay[src_id[core_num]] < time_stamp_h2t[core_num]) sent_core_worst_delay[src_id[core_num]] = (AVG_LATENCY_METRIC == "HEAD_2_TAIL")? time_stamp_h2t[core_num] : time_stamp_h2h[core_num];
528,11 → 532,12
if(all_done_in) begin //All injectors stopped injecting packets
if(total_rsv_flit_number_old==total_rsv_flit_number) rsv_ideal_cnt<=rsv_ideal_cnt+1;//count the number of cycle when no flit is received by any injector
else rsv_ideal_cnt=0;
if(total_sent_flit_number == total_rsv_flit_number) begin // All injected packets are consumed
if(total_expect_rsv_flit_num == total_rsv_flit_number) begin // All injected packets are consumed
done<=1'b1;
end
if(rsv_ideal_cnt >= 100) begin // Injectors stopped sending packets, number of received and sent flits are not equal yet and for 100 cycles no flit is consumed.
$display ("ERROR: The number of sent (%d) & received flits (%d) were not equal at the end of simulation",total_sent_flit_number ,total_rsv_flit_number);
done<=1'b1;
#100 $display ("ERROR: The number of expected (%d) & received flits (%d) were not equal at the end of simulation",total_expect_rsv_flit_num ,total_rsv_flit_number);
$stop;
end
551,11 → 556,12
end
 
initial print_router_st=1'b0;
//report
always @( posedge done) begin
for (core_num=0; core_num<NE; core_num=core_num+1) begin
if(pck_counter[core_num]>0) total_active_endp = total_active_endp +1;
end
566,6 → 572,10
avg_latency_per_hop = sum_clk_per_hop/$itor(total_rsv_pck_num);
$display("simulation results-------------------");
$display("\tSimulation clock cycles:%0d",clk_counter);
print_router_st=1'b1;
#1
/*
$display(" total sent/received packets:%d/%d",total_sent_pck_num,total_rsv_pck_num);
$display(" total sent/received flits:%d/%d",total_sent_flit_number,total_rsv_flit_number);
579,12 → 589,12
$display(" average packet latency = %f \n average flit latency = %f ",avg_latency_pck, avg_latency_flit);
*/
$display("\n\tTotal injected packet in different size:");
for (m=0;m<=(MAX_PACKET_SIZE - MIN_PACKET_SIZE);m++) begin
$write("\tflit_size,");
$write("\tflit_size,");
for (m=0;m<=(MAX_PACKET_SIZE - MIN_PACKET_SIZE);m++) begin
if(rsv_size_array[m]>0)$write("%0d,",m+ MIN_PACKET_SIZE);
end
for (m=0;m<=(MAX_PACKET_SIZE - MIN_PACKET_SIZE);m++) begin
$write("\n\t#pck,");
$write("\n\t#pck,");
for (m=0;m<=(MAX_PACKET_SIZE - MIN_PACKET_SIZE);m++) begin
if(rsv_size_array[m]>0)$write("%0d,",rsv_size_array[m]);
end
593,16 → 603,12
//std_dev= standard_dev( sum_clk_pow2,total_rsv_pck_num, avg_latency_flit);
//$display(" standard_dev = %f",std_dev);
//`endif
 
$write("\n\n\t#node,sent_stat.pck_num,rsvd_stat.pck_num,sent_stat.flit_num,rsvd_stat.flit_num,sent_stat.worst_latency,rsvd_stat.worst_latency,sent_stat.min_latency,rsvd_stat.min_latency,avg_latency_per_hop,avg_latency_flit,avg_latency_pck,avg_throughput(%%),avg_pck_size,");
$display("\n\n\tEndpoints' statistics");
$write("\t#node,sent_stat.pck_num,rsvd_stat.pck_num,sent_stat.flit_num,rsvd_stat.flit_num,sent_stat.worst_latency,rsvd_stat.worst_latency,sent_stat.min_latency,rsvd_stat.min_latency,avg_latency_per_hop,avg_latency_flit,avg_latency_pck,avg_throughput(%%),avg_pck_size,");
`ifdef STND_DEV_EN
$write("avg.std_dev");
`endif
$write("\n");
 
 
 
$write("\n");
for (m=0; m<NE;m++)begin
for (c=0; c<STAT_NUM;c++)begin
701,41 → 707,7
 
initial begin
 
//print_parameter
$display ("NoC parameters:----------------");
$display ("\tTopology: %s",TOPOLOGY);
$display ("\tRouting algorithm: %s",ROUTE_NAME);
$display ("\tVC_per port: %0d", V);
$display ("\tNon-local port buffer_width per VC: %0d", B);
$display ("\tLocal port buffer_width per VC: %0d", LB);
if(TOPOLOGY=="MESH" || TOPOLOGY=="TORUS")begin
$display ("\tRouter num in row: %0d",T1);
$display ("\tRouter num in column: %0d",T2);
$display ("\tEndpoint num per router: %0d",T3);
end else if (TOPOLOGY=="RING" || TOPOLOGY == "LINE") begin
$display ("\tTotal Router num: %0d",T1);
$display ("\tEndpoint num per router: %0d",T3);
end else if (TOPOLOGY == "TREE" || TOPOLOGY == "FATTREE")begin
$display ("\tK: %0d",T1);
$display ("\tL: %0d",T2);
end else begin //CUSTOM
$display ("\tTotal Endpoints number: %0d",T1);
$display ("\tTotal Routers number: %0d",T2);
end
$display ("\tNumber of Class: %0d", C);
$display ("\tFlit data width: %0d", Fpay);
$display ("\tVC reallocation mechanism: %s", VC_REALLOCATION_TYPE);
$display ("\tVC/sw combination mechanism: %s", COMBINATION_TYPE);
$display ("\tAVC_ATOMIC_EN:%0d", AVC_ATOMIC_EN);
$display ("\tCongestion Index:%0d",CONGESTION_INDEX);
$display ("\tADD_PIPREG_AFTER_CROSSBAR:%0d",ADD_PIPREG_AFTER_CROSSBAR);
$display ("\tSSA_EN enabled:%s",SSA_EN);
$display ("\tSwitch allocator arbitration type:%s",SWA_ARBITER_TYPE);
$display ("\tMinimum supported packet size:%0d flit(s)",MIN_PCK_SIZE);
$display ("\tLoop back is enabled:%s",SELF_LOOP_EN);
$display ("\tNumber of multihop bypass (SMART max):%0d",SMART_MAX);
$display ("NoC parameters:----------------");
display_noc_parameters();
$display ("Simulation parameters-------------");
if(DEBUG_EN)
$display ("\tDebuging is enabled");
753,6 → 725,12
//$display ("\tHot spot percentage: %u\n", HOTSPOT_PERCENTAGE);
$display ("\tNumber of hot spot cores: %0d", HOTSPOT_NODE_NUM);
end
if (CAST_TYPE != "UNICAST")begin
$display ("\tMULTICAST traffic ratio: %d(%%), min: %d, max: %d\n", MCAST_TRAFFIC_RATIO,MCAST_PCK_SIZ_MIN,MCAST_PCK_SIZ_MAX);
end
 
//$display ("\tTotal packets sent by one router: %u\n", TOTAL_PKT_PER_ROUTER);
$display ("\tSimulation timeout =%0d", STOP_SIM_CLK);
$display ("\tSimulation ends on total packet num of =%0d", STOP_PCK_NUM);
799,7 → 777,7
rsvd_stat[core_num][0].pck_num ++;
rsvd_stat[core_num][0].sum_clk_h2h +=clk_num_h2h;
rsvd_stat[core_num][0].sum_clk_h2t +=clk_num_h2t;
rsvd_stat[core_num][0].sum_clk_per_hop+= (clk_num_h2h/$itor(distance));
if(distance>0) rsvd_stat[core_num][0].sum_clk_per_hop+= (clk_num_h2h/$itor(distance));
if (rsvd_stat[core_num][0].worst_latency < latency ) rsvd_stat[core_num][0].worst_latency=latency;
if (rsvd_stat[core_num][0].min_latency==0 ) rsvd_stat[core_num][0].min_latency =latency;
if (rsvd_stat[core_num][0].min_latency > latency ) rsvd_stat[core_num][0].min_latency =latency;
946,6 → 924,14
.start_o(start_o)
);
*/
routers_statistic_collector router_stat(
.reset(reset),
.clk(clk),
.router_event(router_event),
.print(print_router_st)
);
 
endmodule
// synthesis translate_on
/traffic_pattern.sv
73,9 → 73,245
pck_dst_gen
 
*********************************/
module pck_dst_gen
import pronoc_pkg::*;
#(
parameter NE=4,
parameter TRAFFIC = "RANDOM",
parameter MAX_PCK_NUM = 10000,
parameter HOTSPOT_NODE_NUM = 4,
parameter MCAST_TRAFFIC_RATIO =50,
parameter MCAST_PCK_SIZ_MIN = 2,
parameter MCAST_PCK_SIZ_MAX = 4,
parameter PCK_SIZw=5,
parameter MIN_PACKET_SIZE=5,
parameter MAX_PACKET_SIZE=5,
parameter PCK_SIZ_SEL="random-discrete",
parameter DISCRETE_PCK_SIZ_NUM=1
)(
en,
current_e_addr,
core_num,
pck_number,
dest_e_addr,
clk,
reset,
valid_dst,
hotspot_info,
custom_traffic_t,
custom_traffic_en,
pck_size_o,
rnd_discrete
);
module pck_dst_gen
localparam ADDR_DIMENSION = (TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") ? 2 : 1; // "RING" and FULLY_CONNECT
localparam NEw= log2(NE),
PCK_CNTw = log2(MAX_PCK_NUM+1),
HOTSPOT_NUM= (TRAFFIC=="HOTSPOT")? HOTSPOT_NODE_NUM : 1;
input reset,clk,en;
input [NEw-1 : 0] core_num;
input [PCK_CNTw-1 : 0] pck_number;
input [EAw-1 : 0] current_e_addr;
output [DAw-1 : 0] dest_e_addr;
output valid_dst;
input [NEw-1 : 0] custom_traffic_t;
input custom_traffic_en;
output [PCK_SIZw-1:0] pck_size_o;
input rnd_discrete_t rnd_discrete [DISCRETE_PCK_SIZ_NUM-1: 0];
input hotspot_t hotspot_info [HOTSPOT_NUM-1 : 0];
 
 
wire [EAw-1 : 0] unicast_dest_e_addr;
wire [PCK_SIZw-1 : 0] pck_size_uni;
 
pck_dst_gen_unicast #(
.NE(NE),
.TRAFFIC(TRAFFIC),
.MAX_PCK_NUM(MAX_PCK_NUM),
.HOTSPOT_NODE_NUM(HOTSPOT_NODE_NUM)
)
unicast
(
.en (en ),
.current_e_addr (current_e_addr ),
.core_num (core_num ),
.pck_number (pck_number ),
.dest_e_addr (unicast_dest_e_addr),
.clk (clk ),
.reset (reset ),
.valid_dst (valid_dst ),
.hotspot_info (hotspot_info ),
.custom_traffic_t (custom_traffic_t),
.custom_traffic_en(custom_traffic_en)
);
pck_size_gen #(
.PCK_SIZw(PCK_SIZw),
.MIN(MIN_PACKET_SIZE),
.MAX(MAX_PACKET_SIZE),
.PCK_SIZ_SEL(PCK_SIZ_SEL),
.DISCRETE_PCK_SIZ_NUM(DISCRETE_PCK_SIZ_NUM)
)
unicast_pck_size
(
.reset(reset),
.clk(clk),
.en(en),
.pck_size(pck_size_uni) ,
.rnd_discrete(rnd_discrete)
);
 
generate
if(CAST_TYPE == "UNICAST") begin :uni
assign dest_e_addr = unicast_dest_e_addr;
assign pck_size_o = pck_size_uni;
end else begin :multi
reg [DAw-1 : 0] multicast_dest_e_addr,temp;
reg [6: 0] rnd_reg;
wire [PCK_SIZw-1 : 0] pck_size_mcast;
reg [PCK_SIZw-1 : 0] pck_siz_tmp;
wire [NEw-1 : 0] unicast_id_num;
endp_addr_decoder #(
.T1(T1),
.T2(T2),
.T3(T3),
.NE(NE),
.EAw(EAw),
.TOPOLOGY(TOPOLOGY)
)enc
(
.code(unicast_dest_e_addr),
.id(unicast_id_num)
);
pck_size_gen #(
.PCK_SIZw(PCK_SIZw),
.MIN(MCAST_PCK_SIZ_MIN),
.MAX(MCAST_PCK_SIZ_MAX),
.PCK_SIZ_SEL("random-range"),
.DISCRETE_PCK_SIZ_NUM(DISCRETE_PCK_SIZ_NUM)
)
mcast_pck_size
(
.reset(reset),
.clk(clk),
.en(en),
.pck_size(pck_size_mcast) ,
.rnd_discrete(rnd_discrete)
);
always @(posedge clk ) begin
if(en | reset) begin
rnd_reg <= $urandom_range(99,0);
end
end
if(CAST_TYPE == "MULTICAST_FULL") begin :mful
always @( * ) begin
multicast_dest_e_addr = {DAw{1'b0}};
temp={DAw{1'b0}};
temp[unicast_id_num]=1'b1;
pck_siz_tmp= pck_size_uni;
if(rnd_reg >= MCAST_TRAFFIC_RATIO) begin
multicast_dest_e_addr[unicast_id_num]=1'b1;
end
else begin
multicast_dest_e_addr = $urandom();
pck_siz_tmp=pck_size_mcast;
end
if(SELF_LOOP_EN == "NO") multicast_dest_e_addr[core_num]=1'b0;
end
assign dest_e_addr = (multicast_dest_e_addr=={DAw{1'b0}} )? temp : multicast_dest_e_addr ;
assign pck_size_o = pck_siz_tmp;
end else if(CAST_TYPE == "MULTICAST_PARTIAL") begin :mpar
always @( * ) begin
multicast_dest_e_addr = {DAw{1'b0}};
temp={unicast_dest_e_addr,1'b1};
pck_siz_tmp= pck_size_uni;
if(rnd_reg >= MCAST_TRAFFIC_RATIO) begin
multicast_dest_e_addr = {unicast_dest_e_addr,1'b1};
end
else begin
multicast_dest_e_addr = $urandom();
multicast_dest_e_addr[0] =1'b0;
pck_siz_tmp=pck_size_mcast;
if(SELF_LOOP_EN == "NO") begin
if(MCAST_ENDP_LIST[core_num]==1'b1) multicast_dest_e_addr[endp_id_to_mcast_id(core_num)+1]=1'b0;
end
end
end
assign dest_e_addr = (multicast_dest_e_addr=={DAw{1'b0}} )? temp : multicast_dest_e_addr ;
assign pck_size_o = pck_siz_tmp;
end else begin //Broadcast
always @( * ) begin
multicast_dest_e_addr = {DAw{1'b0}};
pck_siz_tmp = pck_size_uni;
if(rnd_reg >= MCAST_TRAFFIC_RATIO) begin
multicast_dest_e_addr = {unicast_dest_e_addr,1'b1};
end
else begin
pck_siz_tmp=pck_size_mcast;
end
end
assign dest_e_addr = multicast_dest_e_addr ;
assign pck_size_o = pck_siz_tmp;
end
 
end endgenerate
 
endmodule
 
 
 
 
 
 
 
 
 
 
 
 
 
module pck_dst_gen_unicast
import pronoc_pkg::*;
#(
parameter NE=4,

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