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URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

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    /an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/rtl/src_noc
    from Rev 55 to Rev 56
    ↔ Reverse comparison
  •

Rev 55 → Rev 56

/comb_nonspec.sv
29,12 → 29,10
***********************************************************************/
 
module comb_nonspec_allocator
import pronoc_pkg::*;
#(
module comb_nonspec_allocator # (
parameter NOC_ID = 0,
parameter P = 5 //port number
)
(
)(
//VC allocator
//input
dest_port_all, // from input port
65,6 → 63,8
reset
 
);
 
`NOC_CONF
localparam
P_1 = (SELF_LOOP_EN == "NO")? P-1 : P,
92,28 → 92,25
output [P-1 : 0] any_ivc_sw_request_granted_all;
output [P-1 : 0] any_ovc_granted_in_outport_all;
output [PV-1 : 0] nonspec_first_arbiter_granted_ivc_all;
// input [PVP_1-1 : 0] lk_destination_all;
 
input clk,reset;
input [PV-1 : 0] vc_weight_is_consumed_all;
input [P-1 : 0] iport_weight_is_consumed_all;
output [P-1 : 0] granted_dst_is_from_a_single_flit_pck;
output [P-1 : 0] granted_dst_is_from_a_single_flit_pck;
 
 
//internal wires switch allocator
wire [PV-1 : 0] first_arbiter_granted_ivc_all;
wire [PV-1 : 0] ivc_request_masked_all;
wire [P-1 : 0] any_cand_ovc_exsit;
wire [PV-1 : 0] first_arbiter_granted_ivc_all;
wire [PV-1 : 0] ivc_request_masked_all;
wire [P-1 : 0] any_cand_ovc_exsit;
wire [PV-1 : 0] ivc_request_all;
wire [PV-1 : 0] ovc_is_assigned_all;
wire [PV-1 : 0] assigned_ovc_not_full_all;
wire [PV-1 : 0] assigned_ovc_not_full_all;
assign nonspec_first_arbiter_granted_ivc_all = first_arbiter_granted_ivc_all;
//nonspeculative switch allocator
nonspec_sw_alloc #(
.V(V),
138,12 → 135,9
.vc_weight_is_consumed_all(vc_weight_is_consumed_all),
.iport_weight_is_consumed_all(iport_weight_is_consumed_all),
.clk (clk),
.reset (reset)
.reset (reset)
);
wire [PVV-1 : 0] masked_ovc_request_all;
wire [V-1 : 0] masked_non_assigned_request [PV-1 : 0] ;
wire [PV-1 : 0] masked_assigned_request;
160,16 → 154,12
wire [V : 0] summ_in [PV-1 : 0];
wire [V-1 : 0] vc_pririty [PV-1 : 0] ;
assign assigned_ovc_request_all = ivc_request_all & ovc_is_assigned_all;
assign assigned_ovc_request_all = ivc_request_all & ovc_is_assigned_all;
genvar i,j;
genvar i,j;
generate
// IVC loop
for(i=0;i< PV;i=i+1) begin :total_vc_loop
for(i=0;i< PV;i=i+1) begin :total_vc_loop
// mask unavailable ovc from requests
assign masked_non_assigned_request [i] = masked_ovc_request_all [(i+1)*V-1 : i*V ];
177,11 → 167,10
// summing assigned and non-assigned VC requests
assign summ_in[i] ={masked_non_assigned_request [i],masked_assigned_request [i]};
assign ivc_request_masked_all[i] = | summ_in[i];
assign ivc_request_masked_all[i] = | summ_in[i];
//first level arbiter to candidate only one OVC
// if(VC_ARBITER_TYPE=="RRA")begin :round_robin
//if(VC_ARBITER_TYPE=="RRA")begin :round_robin
arbiter #(
.ARBITER_WIDTH(V)
/combined_vc_sw_alloc.sv
26,12 → 26,10
*************************************/
 
 
module combined_vc_sw_alloc
import pronoc_pkg::*;
#(
module combined_vc_sw_alloc #(
parameter NOC_ID=0,
parameter P = 5 //port number
)
(
)(
ivc_info,
dest_port_all,
masked_ovc_request_all,
54,21 → 52,19
reset
 
);
`NOC_CONF
 
 
localparam
PV = V * P,
PVV = PV * V,
P_1 = (SELF_LOOP_EN == "NO")? P-1 : P,
PP_1 = P_1 * P,
PVP_1 = PV * P_1;
PVP_1 = PV * P_1;
input ivc_info_t ivc_info [P-1 : 0][V-1 : 0];
input [PVP_1-1 : 0] dest_port_all;
input [PVV-1 : 0] masked_ovc_request_all;
input [PVV-1 : 0] masked_ovc_request_all;
output [PV-1 : 0] ovc_allocated_all;
output [PVV-1 : 0] granted_ovc_num_all;
82,7 → 78,7
output [PP_1-1 : 0] nonspec_granted_dest_port_all;
output [PP_1-1 : 0] spec_granted_dest_port_all;
output [PVV-1 : 0] spec_ovc_num_all;
// input [PVP_1-1 : 0] lk_destination_all;
input [PV-1 : 0] vc_weight_is_consumed_all;
input [P-1 : 0] iport_weight_is_consumed_all;
259,7 → 255,8
end else begin :cmb_v1
comb_nonspec_allocator #(
.P(P)
.NOC_ID(NOC_ID),
.P(P)
)
nonspec_comb
(
/crossbar.v
26,6 → 26,7
**************************************************************/
 
module crossbar #(
parameter NOC_ID=0,
parameter TOPOLOGY = "MESH",
parameter V = 4, // vc_num_per_port
parameter P = 5, // router port num
108,6 → 109,7
if (SSA_EN =="YES")begin :predict //If no output is granted replace the output port with SS port
/* verilator lint_on WIDTH */
add_ss_port #(
.NOC_ID(NOC_ID),
.SW_LOC(i),
.P(P)
)
/debug.v
141,9 → 141,9
NX = T1,
NY = T2,
RXw = log2(NX), // number of node in x axis
RYw = log2(NY),
RYw = (TOPOLOGY=="RING" || TOPOLOGY == "LINE") ? 1 : log2(NY),
EXw = log2(NX), // number of node in x axis
EYw = log2(NY); // number of node in y axis
EYw = (TOPOLOGY=="RING" || TOPOLOGY == "LINE") ? 1 : log2(NY); // number of node in y axis
wire [RXw-1 : 0] current_x;
368,6 → 368,7
* *****************/
module check_destination_addr #(
parameter NOC_ID=0,
parameter TOPOLOGY = "MESH",
parameter T1=2,
parameter T2=2,
398,7 → 399,9
wire [NE-1 : 0] dest_mcast_all_endp;
mcast_dest_list_decode decode (
mcast_dest_list_decode #(
.NOC_ID(NOC_ID)
) decode (
.dest_e_addr(dest_e_addr),
.dest_o(dest_mcast_all_endp),
.row_has_any_dest( ),
560,6 → 563,7
end else if (TOPOLOGY == "MESH" || TOPOLOGY == "TORUS" || TOPOLOGY == "RING" || TOPOLOGY == "LINE") begin :tori
/* verilator lint_on WIDTH */
mesh_tori_addr_coder #(
.TOPOLOGY(TOPOLOGY),
.NX (T1 ),
.NY (T2 ),
.NL (T3 ),
594,6 → 598,7
 
module check_pck_size #(
parameter NOC_ID=0,
parameter V=2,
parameter MIN_PCK_SIZE=2,
parameter Fw=36,
625,17 → 630,12
wire [V-1 : 0] vc_hdr_wr_en;
wire [V-1 : 0] onehot;
 
localparam MIN_B = (B<LB)? B : LB;
localparam MIN_B = (B<LB)? B : LB;
genvar i;
generate
for (i=0;i<V;i=i+1) begin
genvar i;
generate
for (i=0;i<V;i=i+1) begin
always @(*) begin
pck_size_counter_next [i] = pck_size_counter [i];
if (vc_num_in == i)begin
678,7 → 678,9
);
mcast_dest_list_decode decode (
mcast_dest_list_decode #(
.NOC_ID(NOC_ID)
) decode (
.dest_e_addr(dest_e_addr[i]),
.dest_o(dest_mcast_all_endp[i]),
.row_has_any_dest(),
/fattree_noc_top.sv
18,16 → 18,17
***************************************/
 
 
module fattree_noc_top
import pronoc_pkg::*;
(
reset,
clk,
chan_in_all,
chan_out_all,
router_event
);
module fattree_noc_top #(
parameter NOC_ID=0
) (
reset,
clk,
chan_in_all,
chan_out_all,
router_event
);
`NOC_CONF
input clk,reset;
//Endpoints ports
46,8 → 47,6
PV = V * MAX_P,
PFw = MAX_P * Fw,
NRL= NE/K, //number of router in each layer
NEFw = NE * Fw,
NEV = NE * V,
CONG_ALw = CONGw * MAX_P,
PLKw = MAX_P * LKw,
PLw = MAX_P * Lw,
81,18 → 80,17
generate
for( pos=0; pos<NRL; pos=pos+1) begin : root
localparam RID = pos;
router_top # (
.P(K)
)
the_router
(
.current_r_id (RID),
router_top # (
.NOC_ID(NOC_ID),
.P(K)
) the_router (
.current_r_id (RID),
.current_r_addr (current_r_addr [RID]),
.chan_in (router_chan_in [RID][K-1 : 0]),
.chan_out (router_chan_out[RID][K-1 : 0]),
.router_event (router_event[RID][K-1 : 0]),
.clk (clk ),
.reset (reset )
.clk (clk),
.reset (reset )
);
end
 
103,11 → 101,10
localparam RID = NRL*level+pos;
router_top # (
.P(2*K)
)
the_router
(
.current_r_id (RID),
.NOC_ID(NOC_ID),
.P(2*K)
) the_router (
.current_r_id (RID),
.current_r_addr (current_r_addr [RID]),
.chan_in (router_chan_in [RID]),
.chan_out (router_chan_out[RID]),
/flit_buffer.sv
28,10 → 28,14
 
 
module flit_buffer
import pronoc_pkg::*;
#(
parameter B =4,
parameter SSA_EN="YES" // "YES" , "NO"
parameter SSA_EN="YES", // "YES" , "NO"
parameter Fw=32,
parameter PCK_TYPE ="MULTI_FLIT",
parameter CAST_TYPE = "UNICAST",
parameter DEBUG_EN = 1,
parameter V=1
)
(
din, // Data in
51,8 → 55,15
flit_is_tail
);
 
function integer log2;
input integer number; begin
log2=(number <=1) ? 1: 0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
localparam
Bw = (B==1)? 1 : log2(B),
718,7 → 729,7
for(i=0;i<DATA_WIDTH; i=i+1) begin : lp
always @(posedge clk ) begin
//if (reset) begin
//if (`pronoc_reset) begin
// shiftreg[i] <= {MAX_DEPTH{1'b0}};
//end else begin
if(wr_en) shiftreg[i] <= {shiftreg[i][MAX_DEPTH-3 : 0] ,din[i]};
920,7 → 931,7
for(i=0;i<DATA_WIDTH; i=i+1) begin : lp
always @(posedge clk ) begin
//if (reset) begin
//if (`pronoc_reset) begin
// shiftreg[i] <= {MAX_DEPTH{1'b0}};
//end else begin
if(wr_en) shiftreg[i] <= {shiftreg[i][MAX_DEPTH-3 : 0] ,din[i]};
1011,7 → 1022,7
always @(posedge clk)
 
begin
if(~reset)begin
if(`pronoc_reset==0)begin
if (wr_en && ~rd_en && full) begin
$display("%t: ERROR: Attempt to write to full FIFO:FIFO size is %d. %m",$time,MAX_DEPTH);
$finish;
1034,13 → 1045,10
endmodule
 
 
/***************
fwft_fifo_bram
****************/
 
 
 
 
 
 
 
module fwft_fifo_bram #(
parameter DATA_WIDTH = 2,
parameter MAX_DEPTH = 2,
1082,6 → 1090,9
wire [DATA_WIDTH-1 : 0] bram_dout;
wire [DATA_WIDTH-1 : 0] out_reg;
reg [DATA_WIDTH-1 : 0] out_reg_next;
wire [DEPTH_DATA_WIDTH-1 : 0] depth;
reg [DEPTH_DATA_WIDTH-1 : 0] depth_next;
assign dout = (bram_out_is_valid)? bram_dout : out_reg;
 
1100,8 → 1111,9
always @(*) begin
valid_next = valid;
if(out_reg_wr_en) valid_next =1'b1;
else if( bram_empty & rd_en) valid_next =1'b0;
if(depth_next == {DEPTH_DATA_WIDTH{1'b0}}) valid_next =1'b0;
else if(out_reg_wr_en) valid_next =1'b1;
else if(bram_empty & rd_en) valid_next =1'b0;
end
1120,8 → 1132,7
.clk(clk)
);
wire [DEPTH_DATA_WIDTH-1 : 0] depth;
reg [DEPTH_DATA_WIDTH-1 : 0] depth_next;
pronoc_register #(.W(DATA_WIDTH) ) reg1 (.in(out_reg_next ), .out(out_reg), .reset(reset), .clk(clk));
1137,7 → 1148,7
if (wr_en & ~rd_en) depth_next = depth + 1'h1;
else if (~wr_en & rd_en) depth_next = depth - 1'h1;
if(pass_din_to_out_reg) out_reg_next = din;
if(bram_out_is_valid) out_reg_next = bram_dout;
else if(bram_out_is_valid) out_reg_next = bram_dout;
end
1256,7 → 1267,7
 
always @(posedge clk)
begin
if (reset) begin
if (`pronoc_reset) begin
rd_ptr <= {Bw{1'b0}};
wr_ptr <= {Bw{1'b0}};
depth <= {DEPTHw{1'b0}};
1281,7 → 1292,7
//synopsys translate_off
always @(posedge clk)
begin
if(~reset)begin
if(`pronoc_reset==1'b0)begin
if (wr_en && depth == B[DEPTHw-1 : 0] && !rd_en) begin
$display(" %t: ERROR: Attempt to write to full FIFO: %m",$time);
$finish;
/flit_buffer_reg_bas.v
8,6 → 8,7
`timescale 1ns / 1ps
 
module flit_buffer_reg_base #(
parameter NOC_ID = 0,
parameter V = 4,
parameter B = 4, // buffer space :flit per VC
parameter Fpay = 32,
15,7 → 16,9
parameter DEBUG_EN = 1,
parameter C=1,
parameter DSTPw=4,
parameter SSA_EN="YES" // "YES" , "NO"
parameter SSA_EN="YES", // "YES" , "NO"
parameter CAST_TYPE="UNI_CAST"
)(
din,
vc_num_wr,
133,8 → 136,13
 
flit_buffer #(
.V(V),
.B(B),
.SSA_EN("NO")// should be "NO" even if SSA is enabled
.SSA_EN("NO"),// should be "NO" even if SSA is enabled
.Fw(Fw),
.PCK_TYPE(PCK_TYPE),
.CAST_TYPE(CAST_TYPE),
.DEBUG_EN(DEBUG_EN)
)
flit_buffer
(
176,10 → 184,9
extract_header_flit_info #(
.NOC_ID(NOC_ID),
.DATA_w(0)
)
header_extractor
(
) header_extractor (
.flit_in({flit_reg_mux_out[REGFw-1:REGFw-2],flit_reg_wr_en,flit_reg_mux_out[Fpay-1 : 0]}),
.flit_in_wr(),
.class_o(class_i),
/header_flit.sv
29,13 → 29,10
* header_flit_generator
***************/
 
module header_flit_generator
import pronoc_pkg::*;
#(
parameter DATA_w = 9 // header flit can carry Optional data. The data will be placed after control data. Fpay >= DATA_w + CTRL_BITS_w
)(
module header_flit_generator #(
parameter NOC_ID=0,
parameter DATA_w=9 // header flit can carry Optional data. The data will be placed after control data. Fpay >= DATA_w + CTRL_BITS_w
)(
flit_out,
src_e_addr_in,
dest_e_addr_in,
45,36 → 42,16
vc_num_in,
be_in,
data_in
);
 
);
function integer log2;
input integer number; begin
log2=(number <=1) ? 1: 0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
/* verilator lint_off WIDTH */
localparam
Cw = (C>1)? log2(C): 1,
HDR_FLAG = 2'b10,
BEw = (BYTE_EN)? log2(Fpay/8) : 1;
/* verilator lint_on WIDTH */
 
 
`NOC_CONF
localparam HDR_FLAG = 2'b10;
 
 
localparam
Dw = (DATA_w==0)? 1 : DATA_w,
DATA_LSB= MSB_BE+1, DATA_MSB= (DATA_LSB + DATA_w)<FPAYw ? DATA_LSB + Dw-1 : FPAYw-1;
output [Fw-1 : 0] flit_out;
input [Cw-1 : 0] class_in;
input [DAw-1 : 0] dest_e_addr_in;
129,18 → 106,15
end
end
//synopsys translate_on
//synthesis translate_on
//synthesis translate_on
 
endmodule
 
 
 
module extract_header_flit_info
import pronoc_pkg::*;
#(
module extract_header_flit_info # (
parameter NOC_ID=0,
parameter DATA_w = 0
)(
) (
//inputs
flit_in,
flit_in_wr,
155,38 → 129,18
hdr_flg_o,
vc_num_o,
hdr_flit_wr_o,
be_o
be_o
);
);
 
function integer log2;
input integer number; begin
log2=(number <=1) ? 1: 0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
`NOC_CONF
localparam
Cw = (C>1)? log2(C): 1,
W = WEIGHTw,
BEw = (BYTE_EN)? log2(Fpay/8) : 1;
Dw = (DATA_w==0)? 1 : DATA_w,
DATA_LSB= MSB_BE+1, DATA_MSB= (DATA_LSB + DATA_w)<FPAYw ? DATA_LSB + Dw-1 : FPAYw-1,
OFFSETw = DATA_MSB - DATA_LSB +1;
localparam
Dw = (DATA_w==0)? 1 : DATA_w;
localparam
DATA_LSB= MSB_BE+1, DATA_MSB= (DATA_LSB + DATA_w)<FPAYw ? DATA_LSB + Dw-1 : FPAYw-1;
localparam OFFSETw = DATA_MSB - DATA_LSB +1;
input [Fw-1 : 0] flit_in;
input flit_in_wr;
267,11 → 221,11
* update the header flit look ahead routing and output VC
**********************************/
 
module header_flit_update_lk_route_ovc
import pronoc_pkg::*;
#(
parameter P = 5
)(
module header_flit_update_lk_route_ovc #(
parameter NOC_ID=0,
parameter P = 5
)
(
flit_in ,
flit_out,
vc_num_in,
284,13 → 238,11
clk
);
 
 
`NOC_CONF
localparam
VDSTPw = V * DSTPw,
VV = V * V;
VV = V * V;
 
input [Fw-1 : 0] flit_in;
output reg [Fw-1 : 0] flit_out;
308,10 → 260,7
wire [DSTPw-1 : 0] lk_dest,dest_coded;
wire [DSTPw-1 : 0] lk_mux_out;
 
pronoc_register #(.W(V)) reg1 (.in(vc_num_in), .out(vc_num_delayed), .reset(reset), .clk(clk));
pronoc_register #(.W(V)) reg1 (.in(vc_num_in), .out(vc_num_delayed), .reset(reset), .clk(clk));
 
/* verilator lint_off WIDTH */
assign hdr_flag = ( PCK_TYPE == "MULTI_FLIT")? flit_in[Fw-1]: 1'b1;
412,37 → 361,21
* hdr_flit_weight_update
* ****************/
 
module hdr_flit_weight_update
import pronoc_pkg::*;
(
module hdr_flit_weight_update #(
parameter NOC_ID = 0
) (
new_weight,
flit_in,
flit_out
);
 
function integer log2;
input integer number; begin
log2=(number <=1) ? 1: 0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
 
 
localparam
Cw = (C>1)? log2(C): 1;
 
`NOC_CONF
input [WEIGHTw-1 : 0] new_weight;
input [Fw-1 : 0] flit_in;
output [Fw-1 : 0] flit_out;
 
assign flit_out = {flit_in[Fw-1 : WEIGHT_LSB+WEIGHTw ] ,new_weight, flit_in[WEIGHT_LSB-1 : 0] };
 
assign flit_out = {flit_in[Fw-1 : WEIGHT_LSB+WEIGHTw ] ,new_weight, flit_in[WEIGHT_LSB-1 : 0] };
 
 
endmodule
 
/inout_ports.sv
25,12 → 25,10
**
**************************************************************/
 
module inout_ports
import pronoc_pkg::*;
#(
parameter P = 5
)
(
module inout_ports #(
parameter NOC_ID=0,
parameter P=5
) (
current_r_addr,
neighbors_r_addr,
clk,
87,7 → 85,8
vsa_ctrl_in,
smart_ctrl_in
);
 
`NOC_CONF
localparam
PV = V * P,
161,10 → 160,7
input smart_ctrl_t smart_ctrl_in [P-1 : 0];
input vsa_ctrl_t vsa_ctrl_in [P-1 : 0];
input [CRDTw-1 : 0 ] credit_init_val_in [P-1 : 0][V-1 : 0];
output [CRDTw-1 : 0 ] credit_init_val_out [P-1 : 0][V-1 : 0];
output [CRDTw-1 : 0 ] credit_init_val_out [P-1 : 0][V-1 : 0];
 
wire [PPSw-1 : 0] port_pre_sel;
176,16 → 172,13
wire [DSTPw-1 : 0] destport_clear [P-1 : 0][V-1 : 0]; // clear non preferable ports in adaptive routing
wire [PV-1 : 0] ivc_num_getting_sw_grant;
ssa_ctrl_t ssa_ctrl [P-1 : 0];
ssa_ctrl_t ssa_ctrl [P-1 : 0];
 
input_ports
#(
.P(P)
)
the_input_port
(
input_ports #(
.NOC_ID(NOC_ID),
.P(P)
) the_input_port (
.current_r_addr (current_r_addr),
.neighbors_r_addr(neighbors_r_addr),
.ivc_num_getting_sw_grant (ivc_num_getting_sw_grant ),
223,11 → 216,9
output_ports #(
.NOC_ID(NOC_ID),
.P (P)
)
output_ports
(
) output_ports (
.vsa_ovc_allocated_all (vsa_ovc_allocated_all),
.flit_is_tail_all (flit_is_tail_all),
.dest_port_all (dest_port_all),
259,10 → 250,9
 
 
vc_alloc_request_gen #(
.P(P)
)
vc_alloc_req_gen
(
.NOC_ID(NOC_ID),
.P(P)
) vc_alloc_req_gen (
.ivc_info(ivc_info),
.ovc_avalable_all(ovc_avalable_all),
.dest_port_decoded_all(dest_port_all),
311,7 → 301,8
if( SSA_EN =="YES" ) begin : ssa
/* verilator lint_on WIDTH */
ss_allocator #(
.P(P)
.NOC_ID(NOC_ID),
.P(P)
)
the_ssa
(
483,13 → 474,10
************************/
 
 
module vc_alloc_request_gen
import pronoc_pkg::*;
#(
parameter P = 5
)(
module vc_alloc_request_gen #(
parameter NOC_ID=0,
parameter P=5
) (
ivc_info,
ovc_avalable_all,
dest_port_decoded_all,
504,6 → 492,8
smart_ctrl_in,
ssa_ctrl_in
);
`NOC_CONF
 
localparam P_1 = (SELF_LOOP_EN == "NO")? P-1 : P,
PV = V * P,
/input_ports.sv
28,51 → 28,47
**
**************************************************************/
 
 
 
 
module input_ports
import pronoc_pkg::*;
#(
parameter P=5
)(
current_r_addr,
neighbors_r_addr,
ivc_num_getting_sw_grant,// for non spec ivc_num_getting_first_sw_grant,
any_ivc_sw_request_granted_all,
flit_in_all,
flit_in_wr_all,
reset_ivc_all,
flit_is_tail_all,
ivc_request_all,
dest_port_all,
flit_out_all,
assigned_ovc_not_full_all,
ovc_is_assigned_all,
sel,
port_pre_sel,
swap_port_presel,
nonspec_first_arbiter_granted_ivc_all,
credit_out_all,
destport_clear,
vc_weight_is_consumed_all,
iport_weight_is_consumed_all,
iport_weight_all,
oports_weight_all,
granted_dest_port_all,
refresh_w_counter,
ivc_info,
vsa_ctrl_in,
ssa_ctrl_in,
smart_ctrl_in,
credit_init_val_out,
reset,
clk
);
module input_ports #(
parameter NOC_ID=0,
parameter P=5
) (
current_r_addr,
neighbors_r_addr,
ivc_num_getting_sw_grant,// for non spec ivc_num_getting_first_sw_grant,
any_ivc_sw_request_granted_all,
flit_in_all,
flit_in_wr_all,
reset_ivc_all,
flit_is_tail_all,
ivc_request_all,
dest_port_all,
flit_out_all,
assigned_ovc_not_full_all,
ovc_is_assigned_all,
sel,
port_pre_sel,
swap_port_presel,
nonspec_first_arbiter_granted_ivc_all,
credit_out_all,
destport_clear,
vc_weight_is_consumed_all,
iport_weight_is_consumed_all,
iport_weight_all,
oports_weight_all,
granted_dest_port_all,
refresh_w_counter,
ivc_info,
vsa_ctrl_in,
ssa_ctrl_in,
smart_ctrl_in,
credit_init_val_out,
reset,
clk
);
`NOC_CONF
localparam
PV = V * P,
87,8 → 83,7
WP= W * P,
WPP = WP * P,
PVDSTPw= PV * DSTPw,
PRAw= P * RAw;
PRAw= P * RAw;
input reset,clk;
111,16 → 106,13
input [PV-1 : 0] sel;
input [PPSw-1 : 0] port_pre_sel;
input [PV-1 : 0] swap_port_presel;
input [PV-1 : 0] nonspec_first_arbiter_granted_ivc_all;
input [PV-1 : 0] nonspec_first_arbiter_granted_ivc_all;
output [WP-1 : 0] iport_weight_all;
output [PV-1 : 0] vc_weight_is_consumed_all;
output [P-1 : 0] iport_weight_is_consumed_all;
input [PP_1-1 : 0] granted_dest_port_all;
output [WPP-1 : 0] oports_weight_all;
output [WPP-1 : 0] oports_weight_all;
 
output ivc_info_t ivc_info [P-1 : 0][V-1 : 0];
input vsa_ctrl_t vsa_ctrl_in [P-1: 0];
134,54 → 126,49
 
genvar i;
generate
for(i=0;i<P;i=i+1)begin : Port_
for(i=0;i<P;i=i+1)begin : Port_
input_queue_per_port
// iport_reg_base
#(
.SW_LOC(i),
.P(P)
)
the_input_queue_per_port
(
.credit_out(credit_out_all [(i+1)*V-1 : i*V]),
.current_r_addr(current_r_addr),
.neighbors_r_addr(neighbors_r_addr),
.ivc_num_getting_sw_grant(ivc_num_getting_sw_grant [(i+1)*V-1 : i*V]),// for non spec ivc_num_getting_first_sw_grant,
.any_ivc_sw_request_granted(any_ivc_sw_request_granted_all [i]),
.flit_in(flit_in_all[(i+1)*Fw-1 : i*Fw]),
.flit_in_wr(flit_in_wr_all[i]),
.reset_ivc(reset_ivc_all [(i+1)*V-1 : i*V]),
.flit_is_tail(flit_is_tail_all [(i+1)*V-1 : i*V]),
.ivc_request(ivc_request_all [(i+1)*V-1 : i*V]),
.dest_port(dest_port_all [(i+1)*P_1*V-1 : i*P_1*V]),
.flit_out(flit_out_all [(i+1)*Fw-1 : i*Fw]),
.assigned_ovc_not_full(assigned_ovc_not_full_all [(i+1)*V-1 : i*V]),
.ovc_is_assigned(ovc_is_assigned_all [(i+1)*V-1 : i*V]),
.sel(sel [(i+1)*V-1 : i*V]),
.port_pre_sel(port_pre_sel),
.swap_port_presel(swap_port_presel[(i+1)*V-1 : i*V]),
.nonspec_first_arbiter_granted_ivc(nonspec_first_arbiter_granted_ivc_all[(i+1)*V-1 : i*V]),
.reset(reset),
.clk(clk),
.destport_clear(destport_clear [i]),
.iport_weight(iport_weight_all[(i+1)*W-1 : i*W]),
.oports_weight(oports_weight_all[(i+1)*WP-1 : i*WP]),
.vc_weight_is_consumed(vc_weight_is_consumed_all [(i+1)*V-1 : i*V]),
.iport_weight_is_consumed(iport_weight_is_consumed_all[i]),
.refresh_w_counter(refresh_w_counter),
.granted_dest_port(granted_dest_port_all[(i+1)*P_1-1 : i*P_1]),
.ivc_info(ivc_info[i]),
.vsa_ctrl_in(vsa_ctrl_in [i]),
.smart_ctrl_in(smart_ctrl_in [i]),
.ssa_ctrl_in(ssa_ctrl_in [i]),
.credit_init_val_out(credit_init_val_out[i])
);
#(
.NOC_ID(NOC_ID),
.SW_LOC(i),
.P(P)
) the_input_queue_per_port (
.credit_out(credit_out_all [(i+1)*V-1 : i*V]),
.current_r_addr(current_r_addr),
.neighbors_r_addr(neighbors_r_addr),
.ivc_num_getting_sw_grant(ivc_num_getting_sw_grant [(i+1)*V-1 : i*V]),// for non spec ivc_num_getting_first_sw_grant,
.any_ivc_sw_request_granted(any_ivc_sw_request_granted_all [i]),
.flit_in(flit_in_all[(i+1)*Fw-1 : i*Fw]),
.flit_in_wr(flit_in_wr_all[i]),
.reset_ivc(reset_ivc_all [(i+1)*V-1 : i*V]),
.flit_is_tail(flit_is_tail_all [(i+1)*V-1 : i*V]),
.ivc_request(ivc_request_all [(i+1)*V-1 : i*V]),
.dest_port(dest_port_all [(i+1)*P_1*V-1 : i*P_1*V]),
.flit_out(flit_out_all [(i+1)*Fw-1 : i*Fw]),
.assigned_ovc_not_full(assigned_ovc_not_full_all [(i+1)*V-1 : i*V]),
.ovc_is_assigned(ovc_is_assigned_all [(i+1)*V-1 : i*V]),
.sel(sel [(i+1)*V-1 : i*V]),
.port_pre_sel(port_pre_sel),
.swap_port_presel(swap_port_presel[(i+1)*V-1 : i*V]),
.nonspec_first_arbiter_granted_ivc(nonspec_first_arbiter_granted_ivc_all[(i+1)*V-1 : i*V]),
.reset(reset),
.clk(clk),
.destport_clear(destport_clear [i]),
.iport_weight(iport_weight_all[(i+1)*W-1 : i*W]),
.oports_weight(oports_weight_all[(i+1)*WP-1 : i*WP]),
.vc_weight_is_consumed(vc_weight_is_consumed_all [(i+1)*V-1 : i*V]),
.iport_weight_is_consumed(iport_weight_is_consumed_all[i]),
.refresh_w_counter(refresh_w_counter),
.granted_dest_port(granted_dest_port_all[(i+1)*P_1-1 : i*P_1]),
.ivc_info(ivc_info[i]),
.vsa_ctrl_in(vsa_ctrl_in [i]),
.smart_ctrl_in(smart_ctrl_in [i]),
.ssa_ctrl_in(ssa_ctrl_in [i]),
.credit_init_val_out(credit_init_val_out[i])
);
end//for
endgenerate
195,57 → 182,52
 
**************************/
 
module input_queue_per_port
import pronoc_pkg::*;
#(
parameter P = 5, // router port num
parameter SW_LOC = 0
)(
current_r_addr,
credit_out,
neighbors_r_addr,
ivc_num_getting_sw_grant,// for non spec ivc_num_getting_first_sw_grant,
any_ivc_sw_request_granted,
flit_in,
flit_in_wr,
reset_ivc,
flit_is_tail,
ivc_request,
dest_port,
flit_out,
assigned_ovc_not_full,
ovc_is_assigned,
sel,
port_pre_sel,
swap_port_presel,
reset,
clk,
nonspec_first_arbiter_granted_ivc,
destport_clear,
iport_weight,
oports_weight,
vc_weight_is_consumed,
iport_weight_is_consumed,
refresh_w_counter,
granted_dest_port,
ivc_info,
smart_ctrl_in,
vsa_ctrl_in,
ssa_ctrl_in,
credit_init_val_out
);
 
module input_queue_per_port #(
parameter NOC_ID=0,
parameter P = 5, // router port num
parameter SW_LOC = 0
) (
current_r_addr,
credit_out,
neighbors_r_addr,
ivc_num_getting_sw_grant,// for non spec ivc_num_getting_first_sw_grant,
any_ivc_sw_request_granted,
flit_in,
flit_in_wr,
reset_ivc,
flit_is_tail,
ivc_request,
dest_port,
flit_out,
assigned_ovc_not_full,
ovc_is_assigned,
sel,
port_pre_sel,
swap_port_presel,
reset,
clk,
nonspec_first_arbiter_granted_ivc,
destport_clear,
iport_weight,
oports_weight,
vc_weight_is_consumed,
iport_weight_is_consumed,
refresh_w_counter,
granted_dest_port,
ivc_info,
smart_ctrl_in,
vsa_ctrl_in,
ssa_ctrl_in,
credit_init_val_out
);
`NOC_CONF
localparam
PORT_B = port_buffer_size(SW_LOC),
PORT_Bw= log2(PORT_B);
localparam
VV = V * V,
VDSTPw = V * DSTPw,
408,24 → 390,23
//extract header flit info
extract_header_flit_info #(
.DATA_w(0)
)
header_extractor
(
.flit_in(flit_in),
.flit_in_wr(flit_in_wr),
.class_o(class_in),
.destport_o(destport_in),
.dest_e_addr_o(dest_e_addr_in),
.src_e_addr_o(src_e_addr_in),
.vc_num_o(vc_num_in),
.hdr_flit_wr_o(hdr_flit_wr),
.hdr_flg_o(hdr_flg_in),
.tail_flg_o(tail_flg_in),
.weight_o(weight_in),
.be_o( ),
.data_o( )
);
.NOC_ID(NOC_ID),
.DATA_w(0)
) header_extractor (
.flit_in(flit_in),
.flit_in_wr(flit_in_wr),
.class_o(class_in),
.destport_o(destport_in),
.dest_e_addr_o(dest_e_addr_in),
.src_e_addr_o(src_e_addr_in),
.vc_num_o(vc_num_in),
.hdr_flit_wr_o(hdr_flit_wr),
.hdr_flg_o(hdr_flg_in),
.tail_flg_o(tail_flg_in),
.weight_o(weight_in),
.be_o( ),
.data_o( )
);
438,7 → 419,7
mesh_tori_endp_addr_decode #(
.TOPOLOGY("MESH"),
.TOPOLOGY(TOPOLOGY),
.T1(T1),
.T2(T2),
.T3(T3),
719,7 → 700,9
assign clear_dspt_mulicast [i] = (reset_ivc[i] & multiple_dest[i]) ? dest_port_encoded[i] : {DSTPw{1'b0}};
// a fix priority arbiter.
multicast_dst_sel sel(
multicast_dst_sel #(
.NOC_ID(NOC_ID)
) sel_arb(
.destport_in(dest_port_multi[i]),
.destport_out(dest_port_encoded[i])
);
974,8 → 957,13
flit_buffer #(
.V(V),
.B(PORT_B), // buffer space :flit per VC
.SSA_EN(SSA_EN)
.SSA_EN(SSA_EN),
.Fw(Fw),
.PCK_TYPE(PCK_TYPE),
.CAST_TYPE(CAST_TYPE),
.DEBUG_EN(DEBUG_EN)
)
the_flit_buffer
(
999,8 → 987,13
 
flit_buffer #(
.V(V),
.B(PORT_B), // buffer space :flit per VC
.SSA_EN(SSA_EN)
.SSA_EN(SSA_EN),
.Fw(Fw),
.PCK_TYPE(PCK_TYPE),
.CAST_TYPE(CAST_TYPE),
.DEBUG_EN(DEBUG_EN)
)
the_flit_buffer
(
1027,6 → 1020,7
if(CAST_TYPE== "UNICAST") begin : unicast
/* verilator lint_on WIDTH */
look_ahead_routing #(
.NOC_ID(NOC_ID),
.T1(T1),
.T2(T2),
.T3(T3),
1052,19 → 1046,16
.reset(reset),
.clk(clk)
);
end // unicast
end // unicast
endgenerate
 
 
header_flit_update_lk_route_ovc #(
.NOC_ID(NOC_ID),
.P(P)
)
the_flit_update
(
) the_flit_update (
.flit_in (buffer_out),
.flit_out (flit_out),
.vc_num_in(ivc_num_getting_sw_grant),
1076,16 → 1067,13
.reset (reset),
.clk (clk)
);
//synthesis translate_off
//synopsys translate_off
generate
if(DEBUG_EN) begin :debg
if(DEBUG_EN) begin :debg
always @ (posedge clk) begin
if((|vsa_ctrl_in.ivc_num_getting_sw_grant) & (|ssa_ctrl_in.ivc_num_getting_sw_grant))begin
$display("%t: ERROR: VSA/SSA conflict: an input port cannot get both sva and ssa grant at the same time %m",$time);
1159,7 → 1147,7
generate
for (j=0;j<V;j=j+1)begin : lp
always @(posedge clk) begin
if(reset)begin
if(`pronoc_reset)begin
t1[j]<=1'b0;
end else begin
if(flit_in_wr >0 && vc_num_in[j] && t1[j]==0)begin
/iport_reg_base.sv
36,6 → 36,7
**************************/
 
module iport_reg_base #(
parameter NOC_ID=0,
parameter PCK_TYPE = "MULTI_FLIT",
parameter V = 4, // vc_num_per_port
parameter P = 5, // router port num
66,7 → 67,8
parameter WRRA_CONFIG_INDEX=0,
parameter PPSw=4,
parameter MIN_PCK_SIZE=2, //minimum packet size in flits. The minimum value is 1.
parameter BYTE_EN=0
parameter BYTE_EN=0,
parameter CAST_TYPE= "UNICAST"
 
)(
current_r_addr,
183,30 → 185,27
wire [ELw-1 : 0] endp_l_in;
logic [WEIGHTw-1 : 0] iport_weight_next;
 
//extract header flit info
//extract header flit info
extract_header_flit_info #(
.NOC_ID(NOC_ID),
.DATA_w(0)
)
header_extractor
(
.flit_in(flit_in),
.flit_in_wr(flit_in_wr),
.class_o(class_in),
.destport_o(destport_in),
.dest_e_addr_o(dest_e_addr_in),
.src_e_addr_o(src_e_addr_in),
.vc_num_o(vc_num_in),
.hdr_flit_wr_o(hdr_flit_wr),
.hdr_flg_o(hdr_flg_in),
.tail_flg_o(tail_flg_in),
.weight_o(weight_in),
.be_o( ),
.data_o( )
);
) header_extractor (
.flit_in(flit_in),
.flit_in_wr(flit_in_wr),
.class_o(class_in),
.destport_o(destport_in),
.dest_e_addr_o(dest_e_addr_in),
.src_e_addr_o(src_e_addr_in),
.vc_num_o(vc_num_in),
.hdr_flit_wr_o(hdr_flit_wr),
.hdr_flg_o(hdr_flg_in),
.tail_flg_o(tail_flg_in),
.weight_o(weight_in),
.be_o( ),
.data_o( )
);
// synopsys translate_off
// synthesis translate_off
`ifdef MONITORE_PATH
547,8 → 546,14
/* verilator lint_on WIDTH */
flit_buffer #(
.V(V),
.B(B), // buffer space :flit per VC
.SSA_EN(SSA_EN)
.SSA_EN(SSA_EN),
.Fw(Fw),
.PCK_TYPE(PCK_TYPE),
.CAST_TYPE(CAST_TYPE),
.DEBUG_EN(DEBUG_EN)
)
the_flit_buffer
(
576,15 → 581,16
flit_buffer_reg_base #(
.PCK_TYPE(PCK_TYPE),
flit_buffer_reg_base #(
.NOC_ID(NOC_ID),
.V(V),
.B(B),
.SSA_EN(SSA_EN),
.Fpay(Fpay),
.DEBUG_EN(DEBUG_EN),
.DSTPw(DSTPw)
.DEBUG_EN(DEBUG_EN),
.DSTPw(DSTPw),
.PCK_TYPE(PCK_TYPE),
.CAST_TYPE(CAST_TYPE)
)
nn
(
631,8 → 637,13
 
flit_buffer #(
.V(V),
.B(B), // buffer space :flit per VC
.SSA_EN(SSA_EN)
.SSA_EN(SSA_EN),
.Fw(Fw),
.PCK_TYPE(PCK_TYPE),
.CAST_TYPE(CAST_TYPE),
.DEBUG_EN(DEBUG_EN)
)
the_flit_buffer
(
668,9 → 679,7
.TOPOLOGY(TOPOLOGY),
.ROUTE_NAME(ROUTE_NAME),
.ROUTE_TYPE(ROUTE_TYPE)
)
lk_routing
(
) lk_routing (
.current_r_addr(current_r_addr),
.neighbors_r_addr(neighbors_r_addr),
.dest_e_addr(dest_e_addr_in),
682,18 → 691,9
);
 
header_flit_update_lk_route_ovc #(
.V(V),
.P(P),
.TOPOLOGY(TOPOLOGY),
.EAw(EAw),
.DSTPw(DSTPw),
.SSA_EN(SSA_EN),
.ROUTE_TYPE(ROUTE_TYPE)
)
the_flit_update
(
.NOC_ID(NOC_ID),
.P(P)
) the_flit_update (
.flit_in (buffer_out),
.flit_out (flit_out),
.vc_num_in(ivc_num_getting_sw_grant),
/mesh_torus.sv
1184,7 → 1184,7
NX = T1,
NY = T2,
RXw = log2(NX), // number of node in x axis
RYw = log2(NY); // number of node in y axis
RYw = (TOPOLOGY=="RING" || TOPOLOGY == "LINE") ? 1 : log2(NY); // number of node in y axis
/* verilator lint_off WIDTH */
localparam [RXw-1 : 0] MAXX = (NX-1);
1241,7 → 1241,7
NY = T2,
NL = T3,
EXw = log2(NX), // number of node in x axis
EYw = log2(NY),
EYw = (TOPOLOGY=="RING" || TOPOLOGY == "LINE")? 1 : log2(NY),
ELw = log2(NL); // number of node in y axis
/* verilator lint_off WIDTH */
1334,7 → 1334,7
localparam
NXw= log2(NX),
NYw= log2(NY),
NYw= (TOPOLOGY=="RING" || TOPOLOGY=="LINE")? 0 : log2(NY),
NEw = log2(NE);
 
 
1358,6 → 1358,7
 
 
module mesh_tori_addr_coder #(
parameter TOPOLOGY = "MESH",
parameter NX=2,
parameter NY=2,
parameter NL=2,
1393,7 → 1394,7
localparam
NXw= log2(NX),
NYw= log2(NY),
NYw= (TOPOLOGY=="RING" || TOPOLOGY=="LINE")? 0 : log2(NY),
NEw = log2(NE);
 
 
/mesh_torus_noc_top.sv
33,10 → 33,9
 
 
 
module mesh_torus_noc_top
import pronoc_pkg::*;
(
 
module mesh_torus_noc_top #(
parameter NOC_ID=0
) (
reset,
clk,
chan_in_all,
44,7 → 43,7
router_event
);
 
 
`NOC_CONF
input clk,reset;
//Endpoints ports
58,20 → 57,8
smartflit_chanel_t router_chan_in [NR-1 :0][MAX_P-1 : 0];
smartflit_chanel_t router_chan_out [NR-1 :0][MAX_P-1 : 0];
 
wire [RAw-1 : 0] current_r_addr [NR-1 : 0];
wire [RAw-1 : 0] current_r_addr [NR-1 : 0];
 
// mesh torus
localparam
EAST = 3'd1,
NORTH = 3'd2,
WEST = 3'd3,
SOUTH = 3'd4;
//ring line
localparam
FORWARD = 2'd1,
BACKWARD= 2'd2;
 
 
genvar x,y,l;
generate
/* verilator lint_off WIDTH */
83,6 → 70,7
assign current_r_addr [x] = x[RAw-1: 0];
router_top #(
.NOC_ID(NOC_ID),
.P (MAX_P )
) the_router (
.current_r_id (x),
135,6 → 123,7
assign current_r_addr [RID] = R_ADDR[RAw-1 :0];
router_top #(
.NOC_ID(NOC_ID),
.P (MAX_P )
) the_router (
.current_r_id (RID),
/mesh_torus_routting.v
40,7 → 40,7
localparam P_1 = P-1,
Xw = log2(NX), // number of node in x axis
Yw = log2(NY); // number of node in y axis
Yw = (TOPOLOGY=="RING" || TOPOLOGY == "LINE") ? 1 : log2(NY); // number of node in y axis
input [Xw-1 : 0] current_x;
input [Yw-1 : 0] current_y;
148,7 → 148,7
localparam P_1 = P-1,
Xw = log2(NX), // number of node in x axis
Yw = log2(NY); // number of node in y axis
Yw = (TOPOLOGY=="RING" || TOPOLOGY == "LINE") ? 1 : log2(NY); // number of node in y axis
input [Xw-1 : 0] current_x;
418,7 → 418,7
endfunction // log2
localparam Xw = log2(NX),
Yw = log2(NY);
Yw = (TOPOLOGY=="RING" || TOPOLOGY == "LINE")? 1 : log2(NY);
// mesh torus
localparam EAST = 3'd1,
NORTH = 3'd2,
770,7 → 770,7
/* verilator lint_on WIDTH */
P_1 = P-1,
Xw = log2(NX),
Yw = log2(NY);
Yw = (TOPOLOGY=="RING" || TOPOLOGY=="LINE" )? 1 : log2(NY);
localparam DSTw = P_1;
/multicast.sv
20,18 → 20,18
 
*************************************/
module multicast_routing
import pronoc_pkg::*;
#(
parameter P = 5,
parameter SW_LOC = 0
)
(
current_r_addr, //current router address
dest_e_addr, // destination endpoint address
destport
);
module multicast_routing # (
parameter NOC_ID=0,
parameter SW_LOC=0,
parameter P=5
)(
current_r_addr, //current router address
dest_e_addr, // destination endpoint address
destport
);
 
`NOC_CONF
input [RAw-1 : 0] current_r_addr;
input [DAw-1 : 0] dest_e_addr;
output [DSTPw-1 : 0] destport;
40,13 → 40,11
/* verilator lint_off WIDTH */
if(TOPOLOGY=="MESH") begin: mesh
/* verilator lint_on WIDTH */
multicast_routing_mesh
#(
.P(P) ,
multicast_routing_mesh #(
.NOC_ID(NOC_ID),
.P(P) ,
.SW_LOC(SW_LOC)
)
routing
(
) routing (
.current_r_addr(current_r_addr), //current router address
.dest_e_addr(dest_e_addr), // destination endpoint address
.destport(destport)
54,13 → 52,11
/* verilator lint_off WIDTH */
end else if (TOPOLOGY == "FMESH") begin : fmesh
/* verilator lint_on WIDTH */
multicast_routing_fmesh
#(
.P(P) ,
multicast_routing_fmesh #(
.NOC_ID(NOC_ID),
.P(P) ,
.SW_LOC(SW_LOC)
)
routing
(
) routing (
.current_r_addr(current_r_addr), //current router address
.dest_e_addr(dest_e_addr), // destination endpoint address
.destport(destport)
78,19 → 74,17
endmodule
 
module multicast_routing_mesh
import pronoc_pkg::*;
#(
parameter P = 5,
parameter SW_LOC = 0
)
(
current_r_addr, //current router address
dest_e_addr, // destination endpoint address
destport
);
module multicast_routing_mesh #(
parameter NOC_ID=0,
parameter SW_LOC=0,
parameter P=5
) (
current_r_addr, //current router address
dest_e_addr, // destination endpoint address
destport
);
`NOC_CONF
input [RAw-1 : 0] current_r_addr;
input [DAw-1 : 0] dest_e_addr;
98,8 → 92,6
 
localparam
NX = T1,
NY = T2,
RXw = log2(NX),
RYw = log2(NY),
EXw = RXw,
136,7 → 128,9
wire [NX-1 : 0] row_has_any_dest;
wire [NE-1 : 0] dest_mcast_all_endp;
mcast_dest_list_decode decode (
mcast_dest_list_decode #(
.NOC_ID(NOC_ID)
) decode (
.dest_e_addr(dest_e_addr),
.dest_o(dest_mcast_all_endp),
.row_has_any_dest(row_has_any_dest),
228,21 → 222,18
 
 
 
 
 
 
module multicast_routing_fmesh
import pronoc_pkg::*;
#(
parameter P = 5,
parameter SW_LOC = 0
)
(
module multicast_routing_fmesh #(
parameter NOC_ID=0,
parameter SW_LOC=0,
parameter P=5
) (
current_r_addr, //current router address
dest_e_addr, // destination endpoint address
destport
);
);
 
`NOC_CONF
input [RAw-1 : 0] current_r_addr;
input [DAw-1 : 0] dest_e_addr;
output [DSTPw-1 : 0] destport;
249,9 → 240,7
 
localparam Pw = log2(MAX_P_FMESH);
localparam
NX = T1,
NY = T2,
localparam
RXw = log2(NX),
RYw = log2(NY),
EXw = RXw,
287,12 → 276,14
wire [NX-1 : 0] row_has_any_dest;
wire [NE-1 : 0] dest_mcast_all_endp;
mcast_dest_list_decode decode (
.dest_e_addr(dest_e_addr),
.dest_o(dest_mcast_all_endp),
.row_has_any_dest(row_has_any_dest),
.is_unicast()
);
mcast_dest_list_decode # (
.NOC_ID(NOC_ID)
) decode (
.dest_e_addr(dest_e_addr),
.dest_o(dest_mcast_all_endp),
.row_has_any_dest(row_has_any_dest),
.is_unicast()
);
genvar i,j;
312,8 → 303,7
ADR = fmesh_addrencode(i),
XX = ADR [NXw -1 : 0],
YY = ADR [NXw+NYw-1 : NXw],
PP = ADR [NXw+NYw+Pw-1 : NXw+NYw];
PP = ADR [NXw+NYw+Pw-1 : NXw+NYw];
/* verilator lint_off CMPCONST */
assign y_plus[i] = (current_rx == XX) && (current_ry > YY);
326,9 → 316,6
for(j=0;j<MAX_P_FMESH;j++)begin : lp
assign local_p[j][i] = (current_rx == XX) && (current_ry == YY) && (PP == j);
end
end//for ne
wire [MAX_P_FMESH-1 : 0] goto_local;
343,49 → 330,45
wire goto_west = (|(x_plus & row_has_any_dest)) | goto_local[WEST];
reg [4 : 0] destport_tmp;
reg [4 : 0] destport_tmp;
always @(*) begin
destport_tmp = {DSTPw{1'b0}};
destport_tmp[LOCAL]=goto_local[LOCAL];
if (SW_LOC == SOUTH)begin
destport_tmp [NORTH] = goto_north ;
destport_tmp [EAST] = goto_east;
destport_tmp [WEST] = goto_west;
end
else if(SW_LOC == NORTH) begin
destport_tmp [SOUTH] = goto_south ;
destport_tmp [EAST] = goto_east;
destport_tmp [WEST] = goto_west;
end
else if(SW_LOC == WEST)begin
destport_tmp [NORTH] = goto_north ;
destport_tmp [SOUTH] = goto_south;
destport_tmp [EAST ] = goto_east;
end
else if(SW_LOC == EAST) begin
destport_tmp [NORTH] = goto_north;
destport_tmp [SOUTH] = goto_south;
destport_tmp [WEST ] = goto_west;
end
else if(SW_LOC == LOCAL || SW_LOC > SOUTH) begin
destport_tmp [NORTH] = goto_north;
destport_tmp [SOUTH] = goto_south;
destport_tmp [EAST] = goto_east;
destport_tmp [WEST] = goto_west;
end
always @(*) begin
destport_tmp = {DSTPw{1'b0}};
destport_tmp[LOCAL]=goto_local[LOCAL];
if (SW_LOC == SOUTH)begin
destport_tmp [NORTH] = goto_north ;
destport_tmp [EAST] = goto_east;
destport_tmp [WEST] = goto_west;
end
else if(SW_LOC == NORTH) begin
destport_tmp [SOUTH] = goto_south ;
destport_tmp [EAST] = goto_east;
destport_tmp [WEST] = goto_west;
end
else if(SW_LOC == WEST)begin
destport_tmp [NORTH] = goto_north ;
destport_tmp [SOUTH] = goto_south;
destport_tmp [EAST ] = goto_east;
end
else if(SW_LOC == EAST) begin
destport_tmp [NORTH] = goto_north;
destport_tmp [SOUTH] = goto_south;
destport_tmp [WEST ] = goto_west;
end
else if(SW_LOC == LOCAL || SW_LOC > SOUTH) begin
destport_tmp [NORTH] = goto_north;
destport_tmp [SOUTH] = goto_south;
destport_tmp [EAST] = goto_east;
destport_tmp [WEST] = goto_west;
end
end
localparam MSB_DSTP = (DSTPw-1 < SOUTH)? DSTPw-1: SOUTH;
localparam MSB_DSTP = (DSTPw-1 < SOUTH)? DSTPw-1: SOUTH;
assign destport [MSB_DSTP : 0] =destport_tmp;
for(i=1;i<NL;i++) begin :other_local
assign destport[MSB_DSTP+i]=goto_local[i];
end
assign destport [MSB_DSTP : 0] =destport_tmp;
for(i=1;i<NL;i++) begin :other_local
assign destport[MSB_DSTP+i]=goto_local[i];
end
endgenerate
393,15 → 376,16
endmodule
 
 
module mcast_dest_list_decode
import pronoc_pkg::*;
(
dest_e_addr,
dest_o,
row_has_any_dest,
is_unicast
);
module mcast_dest_list_decode #(
parameter NOC_ID=0
) (
dest_e_addr,
dest_o,
row_has_any_dest,
is_unicast
);
`NOC_CONF
input [DAw-1 :0] dest_e_addr;
output [NE-1 : 0] dest_o;
527,26 → 511,24
endgenerate
endmodule
 
 
 
 
module multicast_chan_in_process
import pronoc_pkg::*;
#(
parameter P = 5,
parameter SW_LOC = 0
)
(
endp_port,
current_r_addr,
chan_in,
chan_out,
clk
);
module multicast_chan_in_process #(
parameter NOC_ID=0,
parameter SW_LOC=0,
parameter P=5
) (
endp_port,
current_r_addr,
chan_in,
chan_out,
clk
);
 
`NOC_CONF
input endp_port;
input [RAw-1 : 0] current_r_addr;
558,19 → 540,21
wire [MCASTw-1 : 0] mcast_dst_coded;
wire [NE-1 : 0] dest_mcast_all_endp;
wire [NX-1 : 0] row_has_any_dest,row_has_any_dest_in;
wire [DSTPw-1 : 0] destport,destport_o;
wire [DSTPw-1 : 0] destport,destport_o;
hdr_flit_t hdr_flit;
header_flit_info #(
.NOC_ID (NOC_ID)
) extract (
.flit(chan_in.flit),
.hdr_flit(hdr_flit),
.data_o()
);
hdr_flit_t hdr_flit;
header_flit_info extract(
.flit(chan_in.flit),
.hdr_flit(hdr_flit),
.data_o()
);
mcast_dest_list_decode decoder
(
mcast_dest_list_decode #(
.NOC_ID(NOC_ID)
) decoder (
.dest_e_addr(hdr_flit.dest_e_addr),
.dest_o(dest_mcast_all_endp),
.row_has_any_dest(row_has_any_dest_in),
579,9 → 563,8
localparam MCASTw_= (MCASTw < DAw ) ? MCASTw : DAw;
assign mcast_dst_coded = hdr_flit.dest_e_addr[MCASTw_-1:0];
assign mcast_dst_coded = hdr_flit.dest_e_addr[MCASTw_-1:0];
genvar i;
generate
if(TOPOLOGY == "MESH") begin : mesh_
677,6 → 660,7
multicast_routing
#(
.NOC_ID(NOC_ID),
.P(P) ,
.SW_LOC(SW_LOC)
)
697,12 → 681,9
chan_out.flit [DST_P_MSB : DST_P_LSB] = destport_o;
end
end
//synthesis translate_off
if(DEBUG_EN) begin :debg
always @(posedge clk) begin
733,16 → 714,15
 
 
 
module multicast_dst_sel # (
parameter NOC_ID=0
)(
destport_in,
destport_out
);
 
 
module multicast_dst_sel
import pronoc_pkg::*;
(
 
destport_in,
destport_out
);
 
`NOC_CONF
input [DSTPw-1 : 0] destport_in;
output [DSTPw-1 : 0] destport_out;
 
/noc_localparam.v
1,80 → 1,80
 
/**************************************************************************
** WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT ARE LIKELY TO BE
** OVERWRITTEN AND LOST. Rename this file if you wish to do any modification.
** WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT ARE LIKELY TO BE
** OVERWRITTEN AND LOST. Rename this file if you wish to do any modification.
****************************************************************************/
 
 
/**********************************************************************
** File: noc_localparam.v
** File: noc_localparam.v
**
** Copyright (C) 2014-2021 Alireza Monemi
** Copyright (C) 2014-2021 Alireza Monemi
**
** This file is part of ProNoC 2.0.0
** This file is part of ProNoC 2.1.0
**
** ProNoC ( stands for Prototype Network-on-chip) is free software:
** you can redistribute it and/or modify it under the terms of the GNU
** Lesser General Public License as published by the Free Software Foundation,
** either version 2 of the License, or (at your option) any later version.
** ProNoC ( stands for Prototype Network-on-chip) is free software:
** you can redistribute it and/or modify it under the terms of the GNU
** Lesser General Public License as published by the Free Software Foundation,
** either version 2 of the License, or (at your option) any later version.
**
** ProNoC is distributed in the hope that it will be useful, but WITHOUT
** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
** Public License for more details.
** ProNoC is distributed in the hope that it will be useful, but WITHOUT
** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
** Public License for more details.
**
** You should have received a copy of the GNU Lesser General Public
** License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
** You should have received a copy of the GNU Lesser General Public
** License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
******************************************************************************/
 
`ifdef NOC_LOCAL_PARAM
`ifdef NOC_LOCAL_PARAM
 
//NoC parameters
localparam TOPOLOGY="MESH";
localparam T1=3;
localparam T2=3;
localparam T3=1;
localparam V=2;
localparam B=4;
localparam LB=4;
localparam Fpay=64;
localparam ROUTE_NAME="XY";
localparam PCK_TYPE="MULTI_FLIT";
localparam MIN_PCK_SIZE=2;
localparam BYTE_EN=0;
localparam CAST_TYPE="MULTICAST_PARTIAL";
localparam MCAST_ENDP_LIST=9'hf;
localparam SSA_EN="NO";
localparam SMART_MAX=0;
localparam CONGESTION_INDEX=3;
localparam ESCAP_VC_MASK=2'b01;
localparam VC_REALLOCATION_TYPE="NONATOMIC";
localparam COMBINATION_TYPE="COMB_NONSPEC";
localparam MUX_TYPE="BINARY";
localparam C=0;
localparam DEBUG_EN=1;
localparam ADD_PIPREG_AFTER_CROSSBAR=1'b0;
localparam FIRST_ARBITER_EXT_P_EN=1;
localparam SWA_ARBITER_TYPE="RRA";
localparam WEIGHTw=4;
localparam SELF_LOOP_EN="NO";
localparam AVC_ATOMIC_EN=0;
localparam CLASS_SETTING={V{1'b1}};
localparam CVw=(C==0)? V : C * V;
//NoC localparams
localparam TOPOLOGY="MESH";
localparam T1=4;
localparam T2=4;
localparam T3=2;
localparam V=2;
localparam B=4;
localparam LB=7;
localparam Fpay=32;
localparam ROUTE_NAME="XY";
localparam PCK_TYPE="MULTI_FLIT";
localparam MIN_PCK_SIZE=2;
localparam BYTE_EN=0;
localparam CAST_TYPE="UNICAST";
localparam MCAST_ENDP_LIST=32'hf;
localparam SSA_EN="NO";
localparam SMART_MAX=0;
localparam CONGESTION_INDEX=3;
localparam ESCAP_VC_MASK=2'b01;
localparam VC_REALLOCATION_TYPE="NONATOMIC";
localparam COMBINATION_TYPE="COMB_NONSPEC";
localparam MUX_TYPE="BINARY";
localparam C=0;
localparam DEBUG_EN=0;
localparam ADD_PIPREG_AFTER_CROSSBAR=1'b0;
localparam FIRST_ARBITER_EXT_P_EN=1;
localparam SWA_ARBITER_TYPE="RRA";
localparam WEIGHTw=4;
localparam SELF_LOOP_EN="NO";
localparam AVC_ATOMIC_EN=0;
localparam CLASS_SETTING={V{1'b1}};
localparam CVw=(C==0)? V : C * V;
//simulation parameter
//localparam MAX_RATIO = 1000;
localparam MAX_PCK_NUM = 1000000000;
localparam MAX_PCK_SIZ = 16383;
localparam MAX_SIM_CLKs= 1000000000;
localparam TIMSTMP_FIFO_NUM = 16;
//simulation localparam
//localparam MAX_RATIO = 1000;
localparam MAX_PCK_NUM = 1000000000;
localparam MAX_PCK_SIZ = 16383;
localparam MAX_SIM_CLKs= 1000000000;
localparam TIMSTMP_FIFO_NUM = 16;
 
`endif
/noc_top.sv
27,9 → 27,9
 
 
 
module noc_top
import pronoc_pkg::*;
(
module noc_top #(
parameter NOC_ID=0
) (
reset,
clk,
chan_in_all,
37,6 → 37,7
router_event
);
`NOC_CONF
input clk,reset;
//Endpoints ports
52,28 → 53,33
/* verilator lint_off WIDTH */
if (TOPOLOGY == "MESH" || TOPOLOGY == "FMESH" || TOPOLOGY == "TORUS" || TOPOLOGY == "RING" || TOPOLOGY == "LINE") begin : tori_noc
/* verilator lint_on WIDTH */
mesh_torus_noc_top noc_top (
mesh_torus_noc_top #(
.NOC_ID(NOC_ID)
) noc_top (
.reset (reset ),
.clk (clk ),
.chan_in_all (chan_in_all ),
.chan_out_all (chan_out_all ),
.router_event (router_event )
);
);
end else if (TOPOLOGY == "FATTREE") begin : fat_
fattree_noc_top noc_top (
.reset (reset ),
.clk (clk ),
.chan_in_all (chan_in_all ),
.chan_out_all (chan_out_all ),
.router_event (router_event )
fattree_noc_top #(
.NOC_ID(NOC_ID)
) noc_top (
.reset (reset ),
.clk (clk ),
.chan_in_all (chan_in_all ),
.chan_out_all (chan_out_all ),
.router_event (router_event )
);
end else if (TOPOLOGY == "TREE") begin : tree_
tree_noc_top noc_top (
tree_noc_top #(
.NOC_ID(NOC_ID)
) noc_top (
.reset (reset ),
.clk (clk ),
.chan_in_all (chan_in_all ),
81,17 → 87,21
.router_event (router_event )
);
end else if (TOPOLOGY == "STAR") begin : star_
star_noc_top noc_top (
star_noc_top #(
.NOC_ID(NOC_ID)
) noc_top (
.reset (reset ),
.clk (clk ),
.chan_in_all (chan_in_all ),
.chan_out_all (chan_out_all ),
.router_event (router_event )
);
);
end else begin :custom_
 
custom_noc_top noc_top (
custom_noc_top #(
.NOC_ID(NOC_ID)
) noc_top (
.reset (reset ),
.clk (clk ),
.chan_in_all (chan_in_all ),
113,9 → 123,9
 
***********************************/
 
module noc_top_v
import pronoc_pkg::*;
(
module noc_top_v #(
parameter NOC_ID=0
)(
flit_out_all,
flit_out_wr_all,
credit_in_all,
126,6 → 136,7
clk
);
 
`NOC_CONF
input clk,reset;
output [NEFw-1 : 0] flit_out_all;
140,7 → 151,9
smartflit_chanel_t chan_in_all [NE-1 : 0];
smartflit_chanel_t chan_out_all [NE-1 : 0];
 
noc_top the_top(
noc_top #(
.NOC_ID(NOC_ID)
) the_top(
.reset(reset),
.clk(clk),
.chan_in_all(chan_in_all),
148,9 → 161,7
.router_event ( )
);
 
genvar i;
generate
for (i=0; i<NE; i=i+1) begin : lp1
/output_ports.sv
26,11 → 26,10
**************************************************************/
 
 
module output_ports
import pronoc_pkg::*;
#(
parameter P = 5 // router port num
)(
module output_ports #(
parameter NOC_ID=0,
parameter P=5
) (
vsa_ovc_allocated_all,
flit_is_tail_all,
61,28 → 60,17
);
 
 
function integer log2;
input integer number; begin
log2=(number <=1) ? 1: 0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
`NOC_CONF
localparam PV = V * P,
VV = V * V,
PVV = PV * V,
P_1 = ( SELF_LOOP_EN=="NO")? P-1 : P,
VP_1 = V * P_1,
PP_1 = P_1 * P,
PVP_1 = PV * P_1;
 
localparam NORTH = 2,
SOUTH = 4;
localparam
PV = V * P,
VV = V * V,
PVV = PV * V,
P_1 = ( SELF_LOOP_EN=="NO")? P-1 : P,
VP_1 = V * P_1,
PP_1 = P_1 * P,
PVP_1 = PV * P_1;
localparam [V-1 : 0] ADAPTIVE_VC_MASK = ~ ESCAP_VC_MASK;
localparam CONG_ALw= CONGw * P; // congestion width per router;
295,23 → 283,20
assign assigned_ovc_num_all[(i+1)*V-1 : i*V] = ivc_info[i/V][i%V].assigned_ovc_num;
assign ovc_is_assigned_all[i]=ivc_info[i/V][i%V].ovc_is_assigned;
credit_monitor_per_ovc #(
.SW_LOC(i/V)
)
credit_monitor
(
.credit_init_val_i(credit_init_val_in[i/V][i%V]),
.credit_counter_o (credit_counter[i]),
.credit_increased (credit_increased_all[i]),
.credit_decreased(credit_decreased_all[i]),
.empty_all_next(empty_all_next[i]),
.full_all_next(full_all_next[i]),
.nearly_full_all_next(nearly_full_all_next[i]),
.reset(reset),
.clk(clk)
);
.NOC_ID(NOC_ID),
.SW_LOC(i/V)
) credit_monitor (
.credit_init_val_i(credit_init_val_in[i/V][i%V]),
.credit_counter_o (credit_counter[i]),
.credit_increased (credit_increased_all[i]),
.credit_decreased(credit_decreased_all[i]),
.empty_all_next(empty_all_next[i]),
.full_all_next(full_all_next[i]),
.nearly_full_all_next(nearly_full_all_next[i]),
.reset(reset),
.clk(clk)
);
489,26 → 474,26
* credit_monitor_per_ovc
********************/
module credit_monitor_per_ovc
import pronoc_pkg::*;
#(
parameter SW_LOC=0
)(
credit_init_val_i,
credit_increased,
credit_decreased,
credit_counter_o,
empty_all_next,
full_all_next,
nearly_full_all_next,
reset,
clk
);
 
module credit_monitor_per_ovc #(
parameter NOC_ID=0,
parameter SW_LOC=0
) (
credit_init_val_i,
credit_increased,
credit_decreased,
credit_counter_o,
empty_all_next,
full_all_next,
nearly_full_all_next,
reset,
clk
);
`NOC_CONF
localparam
PORT_B = port_buffer_size(SW_LOC),
DEPTHw = log2(PORT_B+1);
PORT_B = port_buffer_size(SW_LOC),
DEPTHw = log2(PORT_B+1);
localparam [DEPTHw-1 : 0] Bint = PORT_B [DEPTHw-1 : 0];
/packet_injector.sv
6,21 → 6,23
* *************************/
 
 
module packet_injector
import pronoc_pkg::*;
(
//general
current_e_addr,
reset,
clk,
//noc port
chan_in,
chan_out,
//control interafce
pck_injct_in,
pck_injct_out
);
module packet_injector #(
parameter NOC_ID=0
) (
//general
current_e_addr,
reset,
clk,
//noc port
chan_in,
chan_out,
//control interafce
pck_injct_in,
pck_injct_out
);
`NOC_CONF
//general
input reset,clk;
input [EAw-1 :0 ] current_e_addr;
51,6 → 53,7
generate if(CAST_TYPE == "UNICAST") begin : uni
conventional_routing #(
.NOC_ID(NOC_ID),
.TOPOLOGY(TOPOLOGY),
.ROUTE_NAME(ROUTE_NAME),
.ROUTE_TYPE(ROUTE_TYPE),
85,20 → 88,19
wire [Fw-1 : 0] hdr_flit_out;
header_flit_generator #(
.DATA_w(HDR_DATA_w)
)
the_header_flit_generator
(
.flit_out (hdr_flit_out),
.vc_num_in (pck_injct_in.vc),
.class_in (pck_injct_in.class_num),
.dest_e_addr_in (pck_injct_in.endp_addr),
.src_e_addr_in (current_e_addr),
.weight_in (pck_injct_in.init_weight),
.destport_in (destport),
.data_in (hdr_data_in),
.be_in({BEw{1'b1}} )// Be is not used in simulation as we dont sent real data
);
.NOC_ID(NOC_ID),
.DATA_w(HDR_DATA_w)
) the_header_flit_generator (
.flit_out (hdr_flit_out),
.vc_num_in (pck_injct_in.vc),
.class_in (pck_injct_in.class_num),
.dest_e_addr_in (pck_injct_in.endp_addr),
.src_e_addr_in (current_e_addr),
.weight_in (pck_injct_in.init_weight),
.destport_in (destport),
.data_in (hdr_data_in),
.be_in({BEw{1'b1}} )// Be is not used in simulation as we dont sent real data
);
localparam
237,25 → 239,19
.empty_vc( ),
.clk(clk),
.reset(reset)
);
);
wire [HDR_DATA_w-1 : 0] hdr_data_o;
hdr_flit_t hdr_flit_i;
header_flit_info
#(
.DATA_w (HDR_DATA_w )
) extractor (
.flit(chan_in.flit_chanel.flit),
.hdr_flit(hdr_flit_i),
.data_o(hdr_data_o)
);
header_flit_info #(
.NOC_ID (NOC_ID),
.DATA_w (HDR_DATA_w)
) extractor (
.flit(chan_in.flit_chanel.flit),
.hdr_flit(hdr_flit_i),
.data_o(hdr_data_o)
);
wire [PCK_INJ_Dw-1 : 0] pck_data_o [V-1 : 0];
reg [Fpay-1 : 0] pck_data_o_gen [V-1 : 0][REMAIN_DAT_FLIT : 0];
265,10 → 261,8
reg [PCK_SIZw-1 : 0] rsv_counter [V-1 : 0];
reg [EAw-1 : 0] sender_endp_addr_reg [V-1 : 0];
logic [15:0] h2t_counter [V-1 : 0];
logic [15:0] h2t_counter_next [V-1 : 0];
logic [15:0] h2t_counter_next [V-1 : 0];
//synthesis translate_off
wire [NEw-1 : 0] current_id;
wire [NEw-1 : 0] sendor_id;
283,12 → 277,14
generate
if(CAST_TYPE != "UNICAST") begin
mcast_dest_list_decode decode (
.dest_e_addr(hdr_flit_i.dest_e_addr),
.dest_o(dest_mcast_all_endp),
.row_has_any_dest(),
.is_unicast()
);
mcast_dest_list_decode #(
.NOC_ID(NOC_ID)
) decode (
.dest_e_addr(hdr_flit_i.dest_e_addr),
.dest_o(dest_mcast_all_endp),
.row_has_any_dest(),
.is_unicast()
);
end
for(i=0; i<V; i++) begin: V_
316,12 → 312,12
//synthesis translate_off
if(CAST_TYPE == "UNICAST") begin
if(hdr_flit_i.dest_e_addr[EAw-1:0] != current_e_addr) begin
$display("%t: ERROR: packet destination address %d does not match reciver endp address %d. %m",$time,hdr_flit_i.dest_e_addr , current_e_addr );
$display("%t: ERROR: packet destination address %d does not match receiver endp address %d. %m",$time,hdr_flit_i.dest_e_addr , current_e_addr );
$finish;
end//if hdr_flit_i
end else begin
if(dest_mcast_all_endp[current_id] !=1'b1 ) begin
$display("%t: ERROR: packet destination address %b does not match reciver endp address %d. %m",$time,hdr_flit_i.dest_e_addr , current_e_addr ,current_id );
$display("%t: ERROR: packet destination address %b does not match receiver endp address %d. %m",$time,hdr_flit_i.dest_e_addr , current_e_addr ,current_id );
$finish;
end
end//if hdr_flit_i
561,42 → 557,42
 
 
 
module packet_injector_verilator
import pronoc_pkg::*;
(
//general
current_e_addr,
reset,
clk,
//noc port
chan_in,
chan_out,
//control interafce
pck_injct_in_data,
pck_injct_in_size,
pck_injct_in_endp_addr,
pck_injct_in_class_num,
pck_injct_in_init_weight,
pck_injct_in_vc,
pck_injct_in_pck_wr,
pck_injct_in_ready,
pck_injct_out_data,
pck_injct_out_size,
pck_injct_out_endp_addr,
pck_injct_out_class_num,
pck_injct_out_init_weight,
pck_injct_out_vc,
pck_injct_out_pck_wr,
pck_injct_out_ready,
pck_injct_out_distance,
pck_injct_out_h2t_delay,
min_pck_size
module packet_injector_verilator #(
parameter NOC_ID=0
) (
//general
current_e_addr,
reset,
clk,
//noc port
chan_in,
chan_out,
//control interafce
pck_injct_in_data,
pck_injct_in_size,
pck_injct_in_endp_addr,
pck_injct_in_class_num,
pck_injct_in_init_weight,
pck_injct_in_vc,
pck_injct_in_pck_wr,
pck_injct_in_ready,
pck_injct_out_data,
pck_injct_out_size,
pck_injct_out_endp_addr,
pck_injct_out_class_num,
pck_injct_out_init_weight,
pck_injct_out_vc,
pck_injct_out_pck_wr,
pck_injct_out_ready,
pck_injct_out_distance,
pck_injct_out_h2t_delay,
min_pck_size
);
 
`NOC_CONF
);
 
 
//general
input reset,clk;
input [EAw-1 :0 ] current_e_addr;
652,14 → 648,17
assign pck_injct_out_distance = pck_injct_out.distance;
assign pck_injct_out_h2t_delay = pck_injct_out.h2t_delay;
packet_injector injector (
.current_e_addr (current_e_addr ),
.reset (reset ),
.clk (clk ),
.chan_in (chan_in ),
.chan_out (chan_out ),
.pck_injct_in (pck_injct_in ),
.pck_injct_out (pck_injct_out ));
packet_injector #(
.NOC_ID(NOC_ID)
) injector (
.current_e_addr (current_e_addr ),
.reset (reset ),
.clk (clk ),
.chan_in (chan_in ),
.chan_out (chan_out ),
.pck_injct_in (pck_injct_in ),
.pck_injct_out (pck_injct_out )
);
localparam
/pronoc_pkg.sv
1,13 → 1,17
 
`include "pronoc_def.v"
/****************************************************************************
* pronoc_pkg.sv
****************************************************************************/
 
`ifdef PRONOC_PKG
 
`ifdef IMPORT_PRONOC_PCK
package pronoc_pkg;
`endif
`define NOC_LOCAL_PARAM
`include "noc_localparam.v"
260,7 → 264,7
bit endp_port; // if it is one, it means the corresponding port is connected o an endpoint
logic [RAw-1: 0] neighbors_r_addr;
logic [V-1 :0] [CRDTw-1: 0] credit_init_val; // the connected port initial credit value. It is taken at reset time
logic [V-1 :0] credit_release_en;
logic [V-1 :0] credit_release_en;
} ctrl_chanel_t;
localparam CTRL_CHANEL_w = $bits(ctrl_chanel_t);
280,7 → 284,7
* simulation
* **********/
localparam DELAYw = EAw+2; //Injector start delay counter width
localparam DELAYw = 9; //Injector start delay counter width. 10 to 500 clk cycles delay randomly selected
typedef struct packed {
integer ip_num;
295,7 → 299,7
//packet injector interface
localparam PCK_INJ_Dw =64;//TODO to be defined by user
localparam PCK_SIZw= log2(MAX_PCK_SIZ);
localparam PCK_SIZw= log2(MAX_PCK_SIZ+1);
 
319,11 → 323,14
bit pck_wr_i;
bit flit_wr_o;
bit pck_wr_o;
bit flit_in_bypassed;
bit flit_in_bypassed;
bit active_high_reset; // if asserted means ProNoC is configured with active high reset
} router_event_t;
localparam ROUTER_EVENT_w = $bits(router_event_t);
 
`ifdef IMPORT_PRONOC_PCK
endpackage : pronoc_pkg
`endif
 
 
`endif
/router_bypass.sv
86,12 → 86,12
 
onehot_mux_2D #(
.W (W ),
.N (N )
.W (W),
.N (N)
) onehot_mux_2D (
.in (in_array ),
.sel (sel ),
.out (out ));
.in (in_array),
.sel (sel),
.out (out));
endmodule
121,12 → 121,12
 
onehot_mux_2D #(
.W (N ),
.N (W )
.W (N),
.N (W)
) onehot_mux_2D (
.in (in_array2 ),
.sel (sel ),
.out (out ));
.in (in_array2),
.sel (sel),
.out (out));
endmodule
133,18 → 133,17
 
 
 
 
 
 
module header_flit_info
import pronoc_pkg::*;
#(
parameter DATA_w = 0
module header_flit_info #(
parameter NOC_ID = 0,
parameter DATA_w = 0
)(
flit,
hdr_flit,
data_o
);
);
`NOC_CONF
localparam
Dw = (DATA_w==0)? 1 : DATA_w;
179,7 → 178,7
assign hdr_flit.weight = {WEIGHTw{1'bX}};
end
if( BYTE_EN ) begin : be_1
if( BYTE_EN) begin : be_1
assign hdr_flit.be = flit.payload [BE_MSB : BE_LSB];
end else begin : be_0
assign hdr_flit.be = {BEw{1'bX}};
204,15 → 203,17
//synthesis translate_off
//synopsys translate_off
 
module smart_chanel_check
import pronoc_pkg::*;
(
flit_chanel,
smart_chanel,
reset,
clk
);
module smart_chanel_check #(
parameter NOC_ID=0
) (
flit_chanel,
smart_chanel,
reset,
clk
);
 
`NOC_CONF
 
input flit_chanel_t flit_chanel;
input smart_chanel_t smart_chanel;
input reset,clk;
221,20 → 222,22
always @(posedge clk) smart_chanel_delay<=smart_chanel;
hdr_flit_t hdr_flit;
header_flit_info extract(
.flit(flit_chanel.flit),
.hdr_flit(hdr_flit),
.data_o()
);
header_flit_info #(
.NOC_ID (NOC_ID)
) extract (
.flit(flit_chanel.flit),
.hdr_flit(hdr_flit),
.data_o()
);
 
always @(posedge clk) begin
if(flit_chanel.flit_wr) begin
if(smart_chanel_delay.ovc!=flit_chanel.flit.vc) begin
$display("%t: ERROR: smart ovc %d is not equal with flit ovc %d. %m",$time,smart_chanel_delay.ovc,flit_chanel.flit.vc );
$display("%t: ERROR: smart ovc %d is not equal with flit ovc %d. %m",$time,smart_chanel_delay.ovc,flit_chanel.flit.vc);
$finish;
end
if(flit_chanel.flit.hdr_flag==1'b1 && hdr_flit.dest_e_addr != smart_chanel_delay.dest_e_addr) begin
$display("%t: ERROR: smart dest_e_addr %d is not equal with flit dest_e_addr %d. %m",$time,smart_chanel_delay.dest_e_addr,hdr_flit.dest_e_addr );
$display("%t: ERROR: smart dest_e_addr %d is not equal with flit dest_e_addr %d. %m",$time,smart_chanel_delay.dest_e_addr,hdr_flit.dest_e_addr);
$finish;
end
if(flit_chanel.flit.hdr_flag!=smart_chanel_delay.hdr_flit) begin
251,24 → 254,20
//synthesis translate_on
 
 
 
 
 
module smart_forward_ivc_info
import pronoc_pkg::*;
#(
module smart_forward_ivc_info #(
parameter NOC_ID=0,
parameter P=5
)(
ivc_info,
iport_info,
oport_info,
smart_chanel,
ovc_locally_requested,
reset,clk
) (
ivc_info,
iport_info,
oport_info,
smart_chanel,
ovc_locally_requested,
reset,clk
);
`NOC_CONF
//ivc info
input reset,clk;
input ivc_info_t ivc_info [P-1 : 0][V-1 : 0];
314,7 → 313,7
assign ovc_locally_requested_next[i][j]=|mask_gen[i][j];
end//V
pronoc_register #(.W(V)) reg1 (.in(ovc_locally_requested_next[i] ), .reset(reset), .clk(clk), .out(ovc_locally_requested[i]));
pronoc_register #(.W(V)) reg1 (.in(ovc_locally_requested_next[i]), .reset(reset), .clk(clk), .out(ovc_locally_requested[i]));
328,11 → 327,11
//assign smart_vc_info_o[i] = smart_ivc_info_all_port[i].or; not synthesizable
// assign smart_vc_info_o[i] = smart_ivc_info_all_port[i].[0] | smart_ivc_info_all_port[i].[1] | smart_ivc_info_all_port[i].[2] ... | smart_ivc_info_all_port[i].[p-1];
reduction_or #(
.W (SMART_IVC_w ),
.N (P )
.W (SMART_IVC_w),
.N (P)
) _or (
.in (smart_ivc_info_all_port[i] ),
.out (smart_vc_info_o[i] )
.in (smart_ivc_info_all_port[i]),
.out (smart_vc_info_o[i])
);
/*
always_comb begin
345,10 → 344,10
bin_to_one_hot #(
.BIN_WIDTH (Vw),
.ONE_HOT_WIDTH (V )
.ONE_HOT_WIDTH (V)
) conv (
.bin_code (smart_vc_info_o[i].assigned_ovc_bin ),
.one_hot_code (assigned_ovc[i] )
.bin_code (smart_vc_info_o[i].assigned_ovc_bin),
.one_hot_code (assigned_ovc[i])
);
360,14 → 359,14
assign smart_chanel_next[i].bypassed_num = {BYPASSw{1'b0}} ;
if( ADD_PIPREG_AFTER_CROSSBAR == 1 ) begin :link_reg
if( ADD_PIPREG_AFTER_CROSSBAR == 1) begin :link_reg
pronoc_register #(
.W ( SMART_CHANEL_w )
.W ( SMART_CHANEL_w)
) register (
.in (smart_chanel_next[i] ),
.reset (reset ),
.clk (clk ),
.out (smart_chanel[i] ));
.in (smart_chanel_next[i]),
.reset (reset),
.clk (clk),
.out (smart_chanel[i]));
end else begin :no_link_reg
assign smart_chanel[i] = smart_chanel_next[i];
374,7 → 373,7
end
/*
always @ (`pronoc_clk_reset_edge )begin
always @ (`pronoc_clk_reset_edge)begin
if(`pronoc_reset) begin
smart_chanel[i].dest_e_addr<= {EAw{1'b0}};
smart_chanel[i].ovc<= {V{1'b0}};
406,11 → 405,10
module smart_bypass_chanels
import pronoc_pkg::*;
#(
parameter P=5
)(
module smart_bypass_chanels #(
parameter NOC_ID=0,
parameter P=5
) (
ivc_info,
iport_info,
oport_info,
419,9 → 417,10
smart_chanel_out,
smart_req,
reset,
clk
clk
);
`NOC_CONF
 
input reset,clk;
input smart_chanel_t smart_chanel_new [P-1 : 0];
449,7 → 448,7
/* verilator lint_on WIDTH */
if( ADD_PIPREG_AFTER_CROSSBAR == 1 ) begin :link_reg
if( ADD_PIPREG_AFTER_CROSSBAR == 1) begin :link_reg
always @( posedge clk)begin
outport_is_granted[i] <= oport_info[i].any_ovc_granted;
end
506,7 → 505,7
generate
/* verilator lint_off WIDTH */
if(TOPOLOGY == "MESH" || TOPOLOGY == "TORUS" || TOPOLOGY =="FMESH" ) begin :twoD
if(TOPOLOGY == "MESH" || TOPOLOGY == "TORUS" || TOPOLOGY =="FMESH") begin :twoD
/* verilator lint_on WIDTH */
if (SS_PORT_LOC == 0 || SS_PORT_LOC > 4) begin : local_ports
assign goes_straight_o = 1'b0; // There is not a next router in this case at all
523,7 → 522,7
end//else
end//mesh_tori
/* verilator lint_off WIDTH */
else if(TOPOLOGY == "RING" || TOPOLOGY == "LINE" ) begin :oneD
else if(TOPOLOGY == "RING" || TOPOLOGY == "LINE") begin :oneD
/* verilator lint_on WIDTH */
if (SS_PORT_LOC == 0 || SS_PORT_LOC > 2) begin : local_ports
assign goes_straight_o = 1'b0; // There is not a next router in this case at all
551,73 → 550,76
 
module smart_validity_check_per_ivc
import pronoc_pkg::*;
#(
module smart_validity_check_per_ivc #(
parameter NOC_ID=0,
parameter IVC_NUM = 0
)(
reset ,
clk ,
) (
reset,
clk,
//smart channel
goes_straight ,
smart_requests_i ,
smart_ivc_i ,
smart_hdr_flit ,
goes_straight ,
smart_requests_i,
smart_ivc_i,
smart_hdr_flit,
//flit
flit_hdr_flag_i ,
flit_tail_flag_i ,
flit_wr_i ,
flit_hdr_flag_i,
flit_tail_flag_i,
flit_wr_i,
//router ivc status
ovc_locally_requested ,
assigned_to_ss_ovc ,
assigned_ovc_not_full ,
ovc_is_assigned ,
ivc_request ,
ovc_locally_requested,
assigned_to_ss_ovc,
assigned_ovc_not_full,
ovc_is_assigned,
ivc_request,
//ss port status
ss_ovc_avalable_in_ss_port ,
ss_port_link_reg_flit_wr ,
ss_ovc_crossbar_wr ,
ss_ovc_avalable_in_ss_port,
ss_port_link_reg_flit_wr,
ss_ovc_crossbar_wr,
//output
smart_single_flit_pck_o ,
smart_ivc_smart_en_o ,
smart_credit_o ,
smart_buff_space_decreased_o ,
smart_ss_ovc_is_allocated_o ,
smart_ss_ovc_is_released_o ,
smart_mask_available_ss_ovc_o ,
smart_single_flit_pck_o,
smart_ivc_smart_en_o,
smart_credit_o,
smart_buff_space_decreased_o,
smart_ss_ovc_is_allocated_o,
smart_ss_ovc_is_released_o,
smart_mask_available_ss_ovc_o,
smart_ivc_num_getting_ovc_grant_o,
smart_ivc_reset_o,
smart_ivc_granted_ovc_num_o
);
input reset, clk;
//smart channel
input goes_straight ,
smart_requests_i ,
smart_ivc_i ,
smart_hdr_flit ,
`NOC_CONF
 
input reset, clk;
//smart channel
input goes_straight,
smart_requests_i,
smart_ivc_i,
smart_hdr_flit,
//flit
flit_hdr_flag_i ,
flit_tail_flag_i ,
flit_wr_i ,
flit_hdr_flag_i ,
flit_tail_flag_i,
flit_wr_i,
//router ivc status
ovc_locally_requested ,
assigned_to_ss_ovc ,
assigned_ovc_not_full ,
ovc_is_assigned ,
ivc_request ,
ovc_locally_requested,
assigned_to_ss_ovc,
assigned_ovc_not_full,
ovc_is_assigned,
ivc_request,
//ss port status
ss_ovc_avalable_in_ss_port ,
ss_ovc_avalable_in_ss_port,
ss_ovc_crossbar_wr,
ss_port_link_reg_flit_wr ;
ss_port_link_reg_flit_wr;
//output
output
smart_single_flit_pck_o ,
smart_ivc_smart_en_o ,
smart_credit_o ,
smart_buff_space_decreased_o ,
smart_ss_ovc_is_allocated_o ,
smart_ss_ovc_is_released_o ,
smart_single_flit_pck_o ,
smart_ivc_smart_en_o,
smart_credit_o,
smart_buff_space_decreased_o,
smart_ss_ovc_is_allocated_o,
smart_ss_ovc_is_released_o,
smart_ivc_num_getting_ovc_grant_o,
smart_ivc_reset_o,
smart_mask_available_ss_ovc_o;
658,7 → 660,7
/* verilator lint_on WIDTH */
 
if( ADD_PIPREG_AFTER_CROSSBAR == 1 ) begin :link_reg
if( ADD_PIPREG_AFTER_CROSSBAR == 1) begin :link_reg
assign condition2= ~(non_empty_ivc_condition | ss_port_link_reg_flit_wr| ss_ovc_crossbar_wr);
end else begin : no_link_reg
assign condition2= ~(non_empty_ivc_condition | ss_port_link_reg_flit_wr); // ss_port_link_reg_flit_wr are identical with ss_ovc_crossbar_wr when there is no link reg
695,13 → 697,12
module smart_allocator_per_iport
import pronoc_pkg::*;
#(
module smart_allocator_per_iport # (
parameter NOC_ID=0,
parameter P=5,
parameter SW_LOC=0,
parameter SS_PORT_LOC=1
)(
) (
//general
clk,
reset,
732,6 → 733,9
smart_ivc_single_flit_pck_o,
smart_ovc_single_flit_pck_o
);
`NOC_CONF
 
//general
input clk, reset;
input [RAw-1 :0] current_r_addr_i;
776,22 → 780,23
// does the route computation for the current router
conventional_routing #(
.TOPOLOGY (TOPOLOGY ),
.ROUTE_NAME (ROUTE_NAME ),
.ROUTE_TYPE (ROUTE_TYPE ),
.T1 (T1 ),
.T2 (T2 ),
.T3 (T3 ),
.RAw (RAw ),
.EAw (EAw ),
.DSTPw (DSTPw ),
.LOCATED_IN_NI (LOCATED_IN_NI )
.NOC_ID (NOC_ID),
.TOPOLOGY (TOPOLOGY),
.ROUTE_NAME (ROUTE_NAME),
.ROUTE_TYPE (ROUTE_TYPE),
.T1 (T1),
.T2 (T2),
.T3 (T3),
.RAw (RAw),
.EAw (EAw),
.DSTPw (DSTPw),
.LOCATED_IN_NI (LOCATED_IN_NI)
) routing (
.reset (reset ),
.clk (clk ),
.current_r_addr (current_r_addr_i ),
.src_e_addr ( ),// needed only for custom routing
.dest_e_addr (smart_chanel_i.dest_e_addr ),
.reset (reset),
.clk (clk),
.current_r_addr (current_r_addr_i),
.src_e_addr ( ),// needed only for custom routing
.dest_e_addr (smart_chanel_i.dest_e_addr),
.destport (destport)
);
798,10 → 803,10
pronoc_register #(.W(DSTPw)) reg1 (.in(destport), .reset(reset), .clk(clk), .out(smart_destport_o));
check_straight_oport #(
.TOPOLOGY ( TOPOLOGY ),
.ROUTE_NAME ( ROUTE_NAME ),
.ROUTE_TYPE ( ROUTE_TYPE ),
.DSTPw ( DSTPw ),
.TOPOLOGY ( TOPOLOGY),
.ROUTE_NAME ( ROUTE_NAME),
.ROUTE_TYPE ( ROUTE_TYPE),
.DSTPw ( DSTPw),
.SS_PORT_LOC ( SS_PORT_LOC)
) check_straight (
.destport_coded_i (destport),
810,22 → 815,23
//look ahead routing. take straight next router address as input
conventional_routing #(
.TOPOLOGY (TOPOLOGY ),
.ROUTE_NAME (ROUTE_NAME ),
.ROUTE_TYPE (ROUTE_TYPE ),
.T1 (T1 ),
.T2 (T2 ),
.T3 (T3 ),
.RAw (RAw ),
.EAw (EAw ),
.DSTPw (DSTPw ),
.LOCATED_IN_NI (LOCATED_IN_NI )
.NOC_ID(NOC_ID),
.TOPOLOGY (TOPOLOGY),
.ROUTE_NAME (ROUTE_NAME),
.ROUTE_TYPE (ROUTE_TYPE),
.T1 (T1),
.T2 (T2),
.T3 (T3),
.RAw (RAw),
.EAw (EAw),
.DSTPw (DSTPw),
.LOCATED_IN_NI (LOCATED_IN_NI)
) lkrouting (
.reset (reset ),
.clk (clk ),
.current_r_addr (neighbors_r_addr_i[SS_PORT_LOC] ),
.src_e_addr ( ),// needed only for custom routing
.dest_e_addr (smart_chanel_i.dest_e_addr ),
.reset (reset),
.clk (clk),
.current_r_addr (neighbors_r_addr_i[SS_PORT_LOC]),
.src_e_addr ( ),// needed only for custom routing
.dest_e_addr (smart_chanel_i.dest_e_addr),
.destport (lkdestport)
);
832,7 → 838,7
pronoc_register #(.W(DSTPw)) reg2 (.in(lkdestport), .reset(reset), .clk(clk), .out(smart_lk_destport_o));
wire [V-1 : 0] ss_ovc_crossbar_wr;//If asserted, a flit will be injected to ovc at next clk cycle
assign ss_ovc_crossbar_wr = (ss_smart_chanel_new.requests[0] ) ? ss_smart_chanel_new.ovc : {V{1'b0}};
assign ss_ovc_crossbar_wr = (ss_smart_chanel_new.requests[0]) ? ss_smart_chanel_new.ovc : {V{1'b0}};
843,18 → 849,19
generate
for (i=0;i<V; i=i+1) begin : vc
smart_validity_check_per_ivc #(
.IVC_NUM(i)
) validity_check (
.reset (reset ),
.clk (clk ),
.NOC_ID(NOC_ID),
.IVC_NUM(i)
) validity_check (
.reset (reset),
.clk (clk),
.goes_straight (goes_straight),
.smart_requests_i (smart_chanel_i.requests[0] ),
.smart_ivc_i (smart_chanel_i.ovc [i] ),
.smart_hdr_flit (smart_chanel_i.hdr_flit ),
.smart_hdr_flit (smart_chanel_i.hdr_flit),
.flit_hdr_flag_i (flit_chanel_i.flit.hdr_flag ),
.flit_tail_flag_i (flit_chanel_i.flit.tail_flag ),
.flit_wr_i (flit_chanel_i.flit_wr ),
.flit_hdr_flag_i (flit_chanel_i.flit.hdr_flag),
.flit_tail_flag_i (flit_chanel_i.flit.tail_flag),
.flit_wr_i (flit_chanel_i.flit_wr),
.ovc_locally_requested (ovc_locally_requested[i] ),
864,16 → 871,16
.ivc_request (ivc_info[i].ivc_req ),
.ss_ovc_avalable_in_ss_port (ss_ovc_info[i].avalable),
.ss_port_link_reg_flit_wr (ss_port_link_reg_flit_wr ),
.ss_port_link_reg_flit_wr (ss_port_link_reg_flit_wr),
.ss_ovc_crossbar_wr (ss_ovc_crossbar_wr[i]),
.smart_single_flit_pck_o (smart_ivc_single_flit_pck_o[i] ),
.smart_single_flit_pck_o (smart_ivc_single_flit_pck_o[i]),
.smart_ivc_smart_en_o (smart_ivc_smart_en_o[i] ),
.smart_credit_o (smart_credit_o[i] ),
.smart_credit_o (smart_credit_o[i]),
.smart_buff_space_decreased_o (smart_buff_space_decreased_o[i]),
.smart_ss_ovc_is_allocated_o (smart_ss_ovc_is_allocated_o[i] ),
.smart_ss_ovc_is_released_o (smart_ss_ovc_is_released_o[i] ),
.smart_mask_available_ss_ovc_o (smart_mask_available_ss_ovc_o[i] ),
.smart_ss_ovc_is_allocated_o (smart_ss_ovc_is_allocated_o[i]),
.smart_ss_ovc_is_released_o (smart_ss_ovc_is_released_o[i]),
.smart_mask_available_ss_ovc_o (smart_mask_available_ss_ovc_o[i]),
.smart_ivc_num_getting_ovc_grant_o(smart_ivc_num_getting_ovc_grant_o[i]),
.smart_ivc_reset_o (smart_ivc_reset_o[i]),
.smart_ivc_granted_ovc_num_o (smart_ivc_granted_ovc_num_o[(i+1)*V-1 : i*V])
940,8 → 947,8
always @(*) begin
counter_next=counter;
if(credit_in & smart_credit_in ) counter_next = counter +1'b1;
else if(credit_in | smart_credit_in ) counter_next=counter;
if(credit_in & smart_credit_in) counter_next = counter +1'b1;
else if(credit_in | smart_credit_in) counter_next=counter;
else if(counter > 0) counter_next = counter -1'b1;
end
 
/router_top.sv
10,24 → 10,23
*
* add optional bypass links to two stage router.
*/
module router_top
import pronoc_pkg::*;
module router_top #(
parameter NOC_ID=0,
parameter P=5
)(
current_r_id,
current_r_addr,
chan_in,
chan_out,
# (
parameter P = 5 // router port num
)(
current_r_id,
current_r_addr,
router_event,
chan_in,
chan_out,
router_event,
clk,
reset
);
clk,
reset
);
 
`NOC_CONF
localparam DISABLED =P;
52,19 → 51,19
//synopsys translate_off
/* verilator lint_off WIDTH */
initial begin
if((SSA_EN=="YES") && (SMART_EN==1'b1) )begin
if((SSA_EN=="YES") &&(SMART_EN==1'b1))begin
$display("ERROR: Only one of the SMART or SAA can be enabled at the same time");
$finish;
end
if((SMART_EN==1'b1) && COMBINATION_TYPE!="COMB_NONSPEC" )begin
if((SMART_EN==1'b1) && COMBINATION_TYPE!="COMB_NONSPEC")begin
$display("ERROR: SMART only works with non-speculative VSA");
$finish;
end
if((MIN_PCK_SIZE > 1) && (PCK_TYPE == "SINGLE_FLIT")) begin
if((MIN_PCK_SIZE > 1) &&(PCK_TYPE == "SINGLE_FLIT")) begin
$display("ERROR: The minimum packet size must be set as one for single-flit packet type NoC");
$finish;
end
if(((SSA_EN=="YES") || (SMART_EN==1'b1) ) && CAST_TYPE!="UNICAST") begin
if(((SSA_EN=="YES") ||(SMART_EN==1'b1)) && CAST_TYPE!="UNICAST") begin
$display("ERROR: SMART or SAA do not support muticast/braodcast packets");
$finish;
end
79,9 → 78,9
logic report_active_ivcs = 0;
generate
for (i=0; i<P; i=i+1) begin :P1_
for (j=0; j<V; j=j+1) begin :V_
always @ (posedge report_active_ivcs) begin
for(i=0; i<P; i=i+1) begin :P1_
for(j=0; j<V; j=j+1) begin :V_
always @(posedge report_active_ivcs) begin
if(ivc_info[i][j].ivc_req) $display("%t : The IVC in router[%h] port[%d] VC [%d] is not empty",$time,current_r_addr,i,j);
end
end
94,7 → 93,7
generate
for (i=0; i<P; i=i+1) begin :P2_
for(i=0; i<P; i=i+1) begin :P2_
assign router_event[i].flit_wr_i = chan_in[i].flit_chanel.flit_wr;
assign router_event[i].bypassed_num = chan_in[i].smart_chanel.bypassed_num;
assign router_event[i].pck_wr_i = chan_in[i].flit_chanel.flit_wr & chan_in[i].flit_chanel.flit.hdr_flag;
101,15 → 100,15
assign router_event[i].flit_wr_o = chan_out[i].flit_chanel.flit_wr;
assign router_event[i].pck_wr_o = chan_out[i].flit_chanel.flit_wr & chan_out[i].flit_chanel.flit.hdr_flag;
assign router_event[i].flit_in_bypassed = chan_out[i].smart_chanel.flit_in_bypassed;
`ifdef ACTIVE_LOW_RESET_MODE
assign router_event[i].active_high_reset = 1'b0;
`else
assign router_event[i].active_high_reset = 1'b1;
`endif
end
endgenerate
flit_chanel_t r2_chan_in [P-1 : 0];
flit_chanel_t r2_chan_out [P-1 : 0];
127,7 → 126,7
ctrl_chanel_t ctrl_out [P-1 : 0];
generate
for (i=0; i<P; i=i+1) begin :Pt_
for(i=0; i<P; i=i+1) begin :Pt_
assign ctrl_in [i] = chan_in[i].ctrl_chanel;
assign chan_out[i].ctrl_chanel= ctrl_out [i];
141,21 → 140,23
hdr_flit_t hdr_flit_o [P-1 : 0]; // the sent packet header flit info
generate
for (i=0; i<P; i=i+1) begin :Port_
for(i=0; i<P; i=i+1) begin :Port_
header_flit_info #(
.NOC_ID(NOC_ID)
) in_extract(
.flit(chan_in[i].flit_chanel.flit),
.hdr_flit( hdr_flit_i[i]),
.data_o()
);
header_flit_info in_extract(
.flit(chan_in[i].flit_chanel.flit),
.hdr_flit( hdr_flit_i[i]),
.data_o()
);
header_flit_info out_extract(
.flit(chan_out[i].flit_chanel.flit),
.hdr_flit( hdr_flit_o[i]),
.data_o()
);
header_flit_info #(
.NOC_ID(NOC_ID)
) out_extract(
.flit(chan_out[i].flit_chanel.flit),
.hdr_flit( hdr_flit_o[i]),
.data_o()
);
if(DEBUG_EN) begin :dbg
check_flit_chanel_type_is_in_order #(
162,9 → 163,7
.V(V),
.PCK_TYPE(PCK_TYPE),
.MIN_PCK_SIZE(MIN_PCK_SIZE)
)
IVC_flit_type_check
(
) IVC_flit_type_check(
.clk(clk),
.reset(reset),
.hdr_flg_in(chan_in[i].flit_chanel.flit.hdr_flag),
174,30 → 173,27
);
check_pck_size #(
.V(V),
.MIN_PCK_SIZE(MIN_PCK_SIZE),
.Fw(Fw),
.DAw(DAw),
.CAST_TYPE(CAST_TYPE),
.NE(NE),
.B(B),
.LB(LB)
)
check_pck_siz
(
.clk(clk),
.reset(reset),
.hdr_flg_in(chan_in[i].flit_chanel.flit.hdr_flag),
.tail_flg_in(chan_in[i].flit_chanel.flit.tail_flag),
.flit_in_wr(chan_in[i].flit_chanel.flit_wr),
.vc_num_in(chan_in[i].flit_chanel.flit.vc),
.dest_e_addr_in(chan_in[i].flit_chanel.flit.payload[E_DST_MSB : E_DST_LSB])
);
.NOC_ID(NOC_ID),
.V(V),
.MIN_PCK_SIZE(MIN_PCK_SIZE),
.Fw(Fw),
.DAw(DAw),
.CAST_TYPE(CAST_TYPE),
.NE(NE),
.B(B),
.LB(LB)
) check_pck_siz(
.clk(clk),
.reset(reset),
.hdr_flg_in(chan_in[i].flit_chanel.flit.hdr_flag),
.tail_flg_in(chan_in[i].flit_chanel.flit.tail_flag),
.flit_in_wr(chan_in[i].flit_chanel.flit_wr),
.vc_num_in(chan_in[i].flit_chanel.flit.vc),
.dest_e_addr_in(chan_in[i].flit_chanel.flit.payload[E_DST_MSB : E_DST_LSB])
);
end
end
end
endgenerate
// synthesis translate_on
210,21 → 206,22
flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit bypass link goes to straight port
 
router_two_stage #(//r2
.P (P)
)router_ref (
.ivc_info (ivc_info),
.ovc_info (ovc_info),
.iport_info (iport_info),
.oport_info (oport_info),
.smart_ctrl_in (smart_ctrl),
.NOC_ID(NOC_ID),
.P(P)
)router_ref(
.ivc_info(ivc_info),
.ovc_info(ovc_info),
.iport_info(iport_info),
.oport_info(oport_info),
.smart_ctrl_in(smart_ctrl),
.current_r_addr(current_r_addr),
.current_r_id(current_r_id),
.chan_in (r2_chan_in),
.chan_out (r2_chan_out),
.ctrl_in (ctrl_in),
.ctrl_out (ctrl_out),
.clk (clk),
.reset (reset)
.chan_in(r2_chan_in),
.chan_out(r2_chan_out),
.ctrl_in(ctrl_in),
.ctrl_out(ctrl_out),
.clk(clk),
.reset(reset)
);
 
generate
232,39 → 229,39
if(SMART_EN) begin :smart
smart_forward_ivc_info
#(
.P(P)
)forward_ivc(
.ivc_info(ivc_info),
.iport_info(iport_info),
.oport_info(oport_info),
.smart_chanel(smart_chanel_new),
.ovc_locally_requested(ovc_locally_requested),
.reset(reset),
.clk(clk)
);
smart_forward_ivc_info #(
.NOC_ID(NOC_ID),
.P(P)
) forward_ivc(
.ivc_info(ivc_info),
.iport_info(iport_info),
.oport_info(oport_info),
.smart_chanel(smart_chanel_new),
.ovc_locally_requested(ovc_locally_requested),
.reset(reset),
.clk(clk)
);
smart_bypass_chanels
#(
.P(P)
)smart_bypass(
.ivc_info(ivc_info),
.iport_info(iport_info),
.oport_info(oport_info),
.smart_chanel_new(smart_chanel_new),
.smart_chanel_in(smart_chanel_in),
.smart_chanel_out(smart_chanel_out),
.smart_req( ),
.reset(reset),
.clk(clk)
);
smart_bypass_chanels #(
.NOC_ID(NOC_ID),
.P(P)
) smart_bypass(
.ivc_info(ivc_info),
.iport_info(iport_info),
.oport_info(oport_info),
.smart_chanel_new(smart_chanel_new),
.smart_chanel_in(smart_chanel_in),
.smart_chanel_out(smart_chanel_out),
.smart_req(),
.reset(reset),
.clk(clk)
);
wire [RAw-1: 0] neighbors_r_addr [P-1: 0];
wire [V-1 : 0] credit_out [P-1 : 0];
wire [V-1 : 0] ivc_smart_en [P-1 : 0];
for (i=0;i<P;i=i+1)begin : Port_
localparam SS_PORT = strieght_port (P,i);
for(i=0;i<P;i=i+1)begin : Port_
localparam SS_PORT = strieght_port(P,i);
if(SS_PORT == DISABLED) begin: smart_dis
assign r2_chan_in[i] = chan_in[i].flit_chanel;
assign chan_out[i].flit_chanel = r2_chan_out[i];
274,38 → 271,39
assign neighbors_r_addr [i] = chan_in[i].ctrl_chanel.neighbors_r_addr;
//smart allocator
smart_allocator_per_iport #(
.P (P ),
.SW_LOC (i ),
.SS_PORT_LOC (SS_PORT )
) smart_allocator(
.clk (clk ),
.reset (reset ),
.current_r_addr_i (current_r_addr ),
.neighbors_r_addr_i (neighbors_r_addr ),
.smart_chanel_i (chan_in[i].smart_chanel ),
.flit_chanel_i (chan_in[i].flit_chanel ),
.ivc_info (ivc_info[i] ),
.ss_ovc_info (ovc_info[SS_PORT] ),
.ovc_locally_requested (ovc_locally_requested[SS_PORT] ),
.ss_smart_chanel_new (smart_chanel_new[SS_PORT]),
.ss_port_link_reg_flit_wr (r2_chan_out[SS_PORT].flit_wr),
.NOC_ID(NOC_ID),
.P(P),
.SW_LOC(i),
.SS_PORT_LOC(SS_PORT)
) smart_allocator (
.clk(clk),
.reset(reset),
.current_r_addr_i(current_r_addr),
.neighbors_r_addr_i(neighbors_r_addr),
.smart_chanel_i(chan_in[i].smart_chanel),
.flit_chanel_i(chan_in[i].flit_chanel),
.ivc_info (ivc_info[i]),
.ss_ovc_info(ovc_info[SS_PORT]),
.ovc_locally_requested(ovc_locally_requested[SS_PORT]),
.ss_smart_chanel_new (smart_chanel_new[SS_PORT]),
.ss_port_link_reg_flit_wr(r2_chan_out[SS_PORT].flit_wr),
.smart_ivc_single_flit_pck_o (smart_ctrl[i].ivc_single_flit_pck),
.smart_destport_o (smart_ctrl[i].destport ),
.smart_lk_destport_o (smart_ctrl[i].lk_destport ),
.smart_hdr_flit_req_o (smart_ctrl[i].hdr_flit_req ),
.smart_ivc_smart_en_o (ivc_smart_en[i] ),
.smart_credit_o (smart_ctrl[i].credit_out ),
.smart_buff_space_decreased_o (smart_ctrl[SS_PORT].buff_space_decreased),
.smart_ivc_num_getting_ovc_grant_o(smart_ctrl[i].ivc_num_getting_ovc_grant),
.smart_ivc_reset_o (smart_ctrl[i].ivc_reset),
.smart_ivc_granted_ovc_num_o (smart_ctrl[i].ivc_granted_ovc_num),
.smart_ovc_single_flit_pck_o (smart_ctrl[SS_PORT].ovc_single_flit_pck),
.smart_ss_ovc_is_allocated_o (smart_ctrl[SS_PORT].ovc_is_allocated),
.smart_ss_ovc_is_released_o (smart_ctrl[SS_PORT].ovc_is_released),
.smart_mask_available_ss_ovc_o (smart_ctrl[SS_PORT].mask_available_ovc)
.smart_ivc_single_flit_pck_o(smart_ctrl[i].ivc_single_flit_pck),
.smart_destport_o(smart_ctrl[i].destport),
.smart_lk_destport_o(smart_ctrl[i].lk_destport),
.smart_hdr_flit_req_o(smart_ctrl[i].hdr_flit_req),
.smart_ivc_smart_en_o(ivc_smart_en[i]),
.smart_credit_o(smart_ctrl[i].credit_out),
.smart_buff_space_decreased_o(smart_ctrl[SS_PORT].buff_space_decreased),
.smart_ivc_num_getting_ovc_grant_o(smart_ctrl[i].ivc_num_getting_ovc_grant),
.smart_ivc_reset_o(smart_ctrl[i].ivc_reset),
.smart_ivc_granted_ovc_num_o(smart_ctrl[i].ivc_granted_ovc_num),
.smart_ovc_single_flit_pck_o(smart_ctrl[SS_PORT].ovc_single_flit_pck),
.smart_ss_ovc_is_allocated_o(smart_ctrl[SS_PORT].ovc_is_allocated),
.smart_ss_ovc_is_released_o (smart_ctrl[SS_PORT].ovc_is_released),
.smart_mask_available_ss_ovc_o(smart_ctrl[SS_PORT].mask_available_ovc)
);
);
assign smart_ctrl[i].ivc_smart_en = ivc_smart_en[i];
assign smart_ctrl[i].smart_en = |ivc_smart_en[i];
314,13 → 312,15
// synthesis translate_off
//assign chan_out[i].smart_chanel = (smart_chanel[i].requests[0]) ? smart_chanel_new[i] : take ss shifted smart;
smart_chanel_check check (
.flit_chanel(chan_out[i].flit_chanel),
.smart_chanel(chan_out[i].smart_chanel),
.reset(reset),
.clk(clk)
);
//assign chan_out[i].smart_chanel =(smart_chanel[i].requests[0]) ? smart_chanel_new[i] : take ss shifted smart;
smart_chanel_check #(
.NOC_ID(NOC_ID)
) check(
.flit_chanel(chan_out[i].flit_chanel),
.smart_chanel(chan_out[i].smart_chanel),
.reset(reset),
.clk(clk)
);
// synthesis translate_on
assign smart_chanel_in[i] = chan_in[i].smart_chanel;
336,7 → 336,7
//mask only flit_wr if smart_en is asserted
r2_chan_in[i] = chan_in[i].flit_chanel;
//can replace destport here and remove lk rout from internal router
if (smart_ctrl[i].smart_en) r2_chan_in[i].flit_wr = 1'b0;
if(smart_ctrl[i].smart_en) r2_chan_in[i].flit_wr = 1'b0;
//send flit_in to straight out port. Replace lk destport in header flit
356,14 → 356,14
end
smart_credit_manage #(
.V (V ),
.B (B )
) smart_credit_manage (
.credit_in (r2_chan_out[i].credit ),
.smart_credit_in (smart_ctrl[i].credit_out ),
.credit_out ( credit_out[i] ),
.reset (reset ),
.clk (clk ));
.V(V),
.B(B)
) smart_credit_manage(
.credit_in(r2_chan_out[i].credit),
.smart_credit_in(smart_ctrl[i].credit_out),
.credit_out( credit_out[i]),
.reset(reset),
.clk(clk));
373,7 → 373,7
end else begin :no_smart
for (i=0;i<P;i=i+1)begin : Port_
for(i=0;i<P;i=i+1)begin : Port_
assign r2_chan_in[i] = chan_in[i].flit_chanel;
assign chan_out[i].flit_chanel = r2_chan_out[i];
assign smart_ctrl[i]={SMART_CTRL_w{1'b0}};
387,16 → 387,16
// logic router_is_ideal /*verilator public_flat_rd*/ ;
// logic not_ideal_next,not_ideal;
// integer ii,jj;
// always @ (*) begin
// always @(*) begin
// router_is_ideal = 1'b1;
// not_ideal_next = 1'b0;
// for (ii=0; ii<P; ii=ii+1) begin
// for(ii=0; ii<P; ii=ii+1) begin
// nb_router_active[ii]= 1'b0;
// if (chan_out[ii].flit_chanel.flit_wr) nb_router_active[ii]=1'b1;
// if (chan_out[ii].flit_chanel.credit > {V{1'b0}} ) nb_router_active[ii]=1'b1;
// if (chan_out[ii].smart_chanel.requests > {SMART_NUM{1'b0}} ) nb_router_active[ii]=1'b1;
// if(chan_out[ii].flit_chanel.flit_wr) nb_router_active[ii]=1'b1;
// if(chan_out[ii].flit_chanel.credit > {V{1'b0}}) nb_router_active[ii]=1'b1;
// if(chan_out[ii].smart_chanel.requests > {SMART_NUM{1'b0}}) nb_router_active[ii]=1'b1;
//
// for (jj=0; jj<V; jj=jj+1) begin
// for(jj=0; jj<V; jj=jj+1) begin
// //no active request is in any input queues
// if(ivc_info[ii][jj].ivc_req)begin
// router_is_ideal=1'b0;
404,11 → 404,11
// end
// end
// //no output flit wr
// if (r2_chan_out[ii].flit_wr) router_is_ideal=1'b0;
// if(r2_chan_out[ii].flit_wr) router_is_ideal=1'b0;
// end
// if (not_ideal) router_is_ideal =1'b0; // delay one clock cycle if the input req exist in last clock cycle bot not on the current one
// if(not_ideal) router_is_ideal =1'b0; // delay one clock cycle if the input req exist in last clock cycle bot not on the current one
// end
// pronoc_register #( .W(1)) no_ideal_register (.in(not_ideal_next), .reset (reset), .clk(clk), .out (not_ideal));
// pronoc_register #( .W(1)) no_ideal_register(.in(not_ideal_next), .reset(reset), .clk(clk), .out(not_ideal));
//`endif
418,25 → 418,24
 
 
module router_top_v //to be used as top module in veralator
import pronoc_pkg::*;
#(
parameter NOC_ID=0,
parameter P=5
)(
current_r_addr,
current_r_id,
# (
parameter P = 5 // router port num
)(
current_r_addr,
current_r_id,
chan_in,
chan_out,
chan_in,
chan_out,
router_event,
router_event,
clk,
reset
 
);
clk,
reset
);
`NOC_CONF
 
input [RAw-1 : 0] current_r_addr;
input [31:0] current_r_id;
448,19 → 447,18
output router_event_t router_event [P-1 : 0];
router_top # (
.P(P)
)
router
(
.current_r_id(current_r_id),
.current_r_addr(current_r_addr),
.chan_in (chan_in),
.chan_out(chan_out),
.router_event(router_event),
.clk(clk),
.reset(reset)
);
router_top #(
.NOC_ID(NOC_ID),
.P(P)
) router (
.current_r_id(current_r_id),
.current_r_addr(current_r_addr),
.chan_in(chan_in),
.chan_out(chan_out),
.router_event(router_event),
.clk(clk),
.reset(reset)
);
endmodule
/router_two_stage.sv
30,12 → 30,10
**************************************************************/
 
 
module router_two_stage
import pronoc_pkg::*;
# (
parameter P = 6 // router port num
)(
module router_two_stage #(
parameter NOC_ID=0,
parameter P=5
) (
current_r_id,
current_r_addr,// connected to constant parameter
56,8 → 54,9
clk,
reset
 
);
);
`NOC_CONF
 
// The current/neighbor routers addresses/port. These values are fixed in each router and they are supposed to be given as parameter.
181,6 → 180,7
assign chan_in_tmp[i] = chan_in[i];
end else begin : multi
multicast_chan_in_process #(
.NOC_ID(NOC_ID),
.P(P),
.SW_LOC (i)
) multicast_process (
240,6 → 240,7
//credit_release. Only activated for local ports as credit_release_en never be asserted in router to router connection.
credit_release_gen #(
.NOC_ID(NOC_ID),
.CREDIT_NUM (LB)
) credit_release_gen (
.clk (clk ),
266,94 → 267,91
inout_ports
#(
.P(P)
)
the_inout_ports
(
.current_r_addr(current_r_addr),
.neighbors_r_addr(neighbors_r_addr),
.flit_in_all(flit_in_all),
.flit_in_wr_all(flit_in_wr_all),
.credit_out_all(credit_out_all),
.credit_in_all(credit_in_all),
.masked_ovc_request_all(masked_ovc_request_all),
.granted_dst_is_from_a_single_flit_pck(granted_dst_is_from_a_single_flit_pck),
.vsa_ovc_allocated_all(ovc_allocated_all),
.granted_ovc_num_all(granted_ovc_num_all),
.ivc_num_getting_ovc_grant(ivc_num_getting_ovc_grant),
.spec_ovc_num_all(spec_ovc_num_all),
.nonspec_first_arbiter_granted_ivc_all(nonspec_first_arbiter_granted_ivc_all),
.spec_first_arbiter_granted_ivc_all(spec_first_arbiter_granted_ivc_all),
.nonspec_granted_dest_port_all(nonspec_granted_dest_port_all),
.spec_granted_dest_port_all(spec_granted_dest_port_all),
.granted_dest_port_all(granted_dest_port_all),
.any_ivc_sw_request_granted_all(any_ivc_sw_request_granted_all),
.any_ovc_granted_in_outport_all(any_ovc_granted_in_outport_all),
.dest_port_all(dest_port_all),
.ovc_is_assigned_all(ovc_is_assigned_all),
.ivc_request_all(ivc_request_all),
.assigned_ovc_not_full_all(assigned_ovc_not_full_all),
.flit_out_all(iport_flit_out_all),
.congestion_in_all(congestion_in_all),
.congestion_out_all(congestion_out_all),
// .lk_destination_all(lk_destination_all),
.ssa_flit_wr_all(ssa_flit_wr_all),
.iport_weight_all(iport_weight_all),
.oports_weight_all(oports_weight_all),
.vc_weight_is_consumed_all(vc_weight_is_consumed_all),
.iport_weight_is_consumed_all(iport_weight_is_consumed_all),
.refresh_w_counter(refresh_w_counter),
.clk(clk),
.reset(reset),
.ivc_info(ivc_info),
.ovc_info(ovc_info),
.oport_info(oport_info),
.smart_ctrl_in(smart_ctrl_in),
.vsa_ctrl_in(vsa_ctrl),
.credit_init_val_in (credit_init_val_in),
.credit_init_val_out (credit_init_val_out),
.flit_is_tail_all(flit_is_tail_all),
.crossbar_flit_out_wr_all(crossbar_flit_out_wr_all),
.vsa_ovc_released_all(vsa_ovc_released_all),
.vsa_credit_decreased_all(vsa_credit_decreased_all)
);
inout_ports #(
.NOC_ID(NOC_ID),
.P(P)
) the_inout_ports (
.current_r_addr(current_r_addr),
.neighbors_r_addr(neighbors_r_addr),
.flit_in_all(flit_in_all),
.flit_in_wr_all(flit_in_wr_all),
.credit_out_all(credit_out_all),
.credit_in_all(credit_in_all),
.masked_ovc_request_all(masked_ovc_request_all),
.granted_dst_is_from_a_single_flit_pck(granted_dst_is_from_a_single_flit_pck),
.vsa_ovc_allocated_all(ovc_allocated_all),
.granted_ovc_num_all(granted_ovc_num_all),
.ivc_num_getting_ovc_grant(ivc_num_getting_ovc_grant),
.spec_ovc_num_all(spec_ovc_num_all),
.nonspec_first_arbiter_granted_ivc_all(nonspec_first_arbiter_granted_ivc_all),
.spec_first_arbiter_granted_ivc_all(spec_first_arbiter_granted_ivc_all),
.nonspec_granted_dest_port_all(nonspec_granted_dest_port_all),
.spec_granted_dest_port_all(spec_granted_dest_port_all),
.granted_dest_port_all(granted_dest_port_all),
.any_ivc_sw_request_granted_all(any_ivc_sw_request_granted_all),
.any_ovc_granted_in_outport_all(any_ovc_granted_in_outport_all),
.dest_port_all(dest_port_all),
.ovc_is_assigned_all(ovc_is_assigned_all),
.ivc_request_all(ivc_request_all),
.assigned_ovc_not_full_all(assigned_ovc_not_full_all),
.flit_out_all(iport_flit_out_all),
.congestion_in_all(congestion_in_all),
.congestion_out_all(congestion_out_all),
// .lk_destination_all(lk_destination_all),
.ssa_flit_wr_all(ssa_flit_wr_all),
.iport_weight_all(iport_weight_all),
.oports_weight_all(oports_weight_all),
.vc_weight_is_consumed_all(vc_weight_is_consumed_all),
.iport_weight_is_consumed_all(iport_weight_is_consumed_all),
.refresh_w_counter(refresh_w_counter),
.clk(clk),
.reset(reset),
.ivc_info(ivc_info),
.ovc_info(ovc_info),
.oport_info(oport_info),
.smart_ctrl_in(smart_ctrl_in),
.vsa_ctrl_in(vsa_ctrl),
.credit_init_val_in (credit_init_val_in),
.credit_init_val_out (credit_init_val_out),
.flit_is_tail_all(flit_is_tail_all),
.crossbar_flit_out_wr_all(crossbar_flit_out_wr_all),
.vsa_ovc_released_all(vsa_ovc_released_all),
.vsa_credit_decreased_all(vsa_credit_decreased_all)
);
 
 
combined_vc_sw_alloc #(
.P(P)
)
vsa
(
.dest_port_all(dest_port_all),
.masked_ovc_request_all(masked_ovc_request_all),
.granted_dst_is_from_a_single_flit_pck(granted_dst_is_from_a_single_flit_pck),
.ovc_allocated_all(ovc_allocated_all),
.granted_ovc_num_all(granted_ovc_num_all),
.ivc_num_getting_ovc_grant(ivc_num_getting_ovc_grant),
.ivc_num_getting_sw_grant(ivc_num_getting_sw_grant),
.spec_first_arbiter_granted_ivc_all(spec_first_arbiter_granted_ivc_all),
.nonspec_first_arbiter_granted_ivc_all(nonspec_first_arbiter_granted_ivc_all),
.nonspec_granted_dest_port_all(nonspec_granted_dest_port_all),
.spec_granted_dest_port_all(spec_granted_dest_port_all),
.granted_dest_port_all(granted_dest_port_all),
.any_ivc_sw_request_granted_all(any_ivc_sw_request_granted_all),
.any_ovc_granted_in_outport_all(any_ovc_granted_in_outport_all),
.spec_ovc_num_all(spec_ovc_num_all),
// .lk_destination_all(lk_destination_all),
.vc_weight_is_consumed_all(vc_weight_is_consumed_all),
.iport_weight_is_consumed_all(iport_weight_is_consumed_all),
.ivc_info(ivc_info),
.clk(clk),
.reset(reset)
);
.NOC_ID(NOC_ID),
.P(P)
) vsa (
.dest_port_all(dest_port_all),
.masked_ovc_request_all(masked_ovc_request_all),
.granted_dst_is_from_a_single_flit_pck(granted_dst_is_from_a_single_flit_pck),
.ovc_allocated_all(ovc_allocated_all),
.granted_ovc_num_all(granted_ovc_num_all),
.ivc_num_getting_ovc_grant(ivc_num_getting_ovc_grant),
.ivc_num_getting_sw_grant(ivc_num_getting_sw_grant),
.spec_first_arbiter_granted_ivc_all(spec_first_arbiter_granted_ivc_all),
.nonspec_first_arbiter_granted_ivc_all(nonspec_first_arbiter_granted_ivc_all),
.nonspec_granted_dest_port_all(nonspec_granted_dest_port_all),
.spec_granted_dest_port_all(spec_granted_dest_port_all),
.granted_dest_port_all(granted_dest_port_all),
.any_ivc_sw_request_granted_all(any_ivc_sw_request_granted_all),
.any_ovc_granted_in_outport_all(any_ovc_granted_in_outport_all),
.spec_ovc_num_all(spec_ovc_num_all),
// .lk_destination_all(lk_destination_all),
.vc_weight_is_consumed_all(vc_weight_is_consumed_all),
.iport_weight_is_consumed_all(iport_weight_is_consumed_all),
.ivc_info(ivc_info),
.clk(clk),
.reset(reset)
);
pronoc_register #(.W(PP_1)) reg2 (.in(granted_dest_port_all ), .out(granted_dest_port_all_delayed), .reset(reset), .clk(clk));
crossbar #(
crossbar #(
.NOC_ID(NOC_ID),
.TOPOLOGY(TOPOLOGY),
.V (V), // vc_num_per_port
.P (P), // router port num
360,8 → 358,7
.Fw (Fw),
.MUX_TYPE (MUX_TYPE),
.SSA_EN (SSA_EN),
.SELF_LOOP_EN(SELF_LOOP_EN)
.SELF_LOOP_EN(SELF_LOOP_EN)
)
the_crossbar
(
369,8 → 366,7
.flit_in_all (iport_flit_out_all),
.ssa_flit_wr_all (ssa_flit_wr_all),
.flit_out_all (crossbar_flit_out_all),
.flit_out_wr_all (crossbar_flit_out_wr_all)
.flit_out_wr_all (crossbar_flit_out_wr_all)
);
//link reg
425,6 → 421,7
);
weights_update #(
.NOC_ID(NOC_ID),
.ARBITER_TYPE(SWA_ARBITER_TYPE),
.V(V),
.P(P),
502,7 → 499,7
always @(posedge clk) begin
if(reset)begin
if(`pronoc_reset)begin
t1[i]<=1'b0;
t2[i]<=1'b0;
end else begin
556,6 → 553,7
`ifdef TRACE_DUMP_PER_NoC
pronoc_trace_dump #(
.NOC_ID(NOC_ID),
.P(P),
.TRACE_DUMP_PER("NOC"), //NOC, ROUTER, PORT
.CYCLE_REPORT(0) // 1 : enable, 0 : disable
570,6 → 568,7
`endif
`ifdef TRACE_DUMP_PER_ROUTER
pronoc_trace_dump #(
.NOC_ID(NOC_ID),
.P(P),
.TRACE_DUMP_PER("ROUTER"), //NOC, ROUTER, PORT
.CYCLE_REPORT(0) // 1 : enable, 0 : disable
584,6 → 583,7
`endif
`ifdef TRACE_DUMP_PER_PORT
pronoc_trace_dump #(
.NOC_ID(NOC_ID),
.P(P),
.TRACE_DUMP_PER("PORT"), //NOC, ROUTER, PORT
.CYCLE_REPORT(0) // 1 : enable, 0 : disable
610,16 → 610,19
 
 
 
module credit_release_gen
import pronoc_pkg::*;
#(
module credit_release_gen #(
parameter NOC_ID=0,
parameter CREDIT_NUM=4
)(
)
(
clk,
reset,
en,
credit_out
);
`NOC_CONF
input clk, reset;
input en;
output reg credit_out;
649,26 → 652,28
end
endmodule
endmodule
 
 
 
 
//synthesis translate_off
module pronoc_trace_dump
import pronoc_pkg::*;
#(
module pronoc_trace_dump #(
parameter NOC_ID=0,
parameter P = 6,
parameter TRACE_DUMP_PER= "ROUTER", //NOC, ROUTER, PORT
parameter CYCLE_REPORT=0 // 1 : enable, 0 : disable
)(
)
(
current_r_id,
chan_in,
chan_out,
clk
);
 
`NOC_CONF
 
input [31:0] current_r_id;
input flit_chanel_t chan_in [P-1 : 0];
input flit_chanel_t chan_out [P-1 : 0];
675,6 → 680,7
input clk;
 
pronoc_trace_dump_sub #(
.NOC_ID(NOC_ID),
.P(P),
.TRACE_DUMP_PER(TRACE_DUMP_PER), //NOC, ROUTER, PORT
.DIRECTION("in"), // in,out
688,6 → 694,7
);
 
pronoc_trace_dump_sub #(
.NOC_ID(NOC_ID),
.P(P),
.TRACE_DUMP_PER(TRACE_DUMP_PER), //NOC, ROUTER, PORT
.DIRECTION("out"), // in,out
701,35 → 708,39
);
endmodule
 
module pronoc_trace_dump_sub
import pronoc_pkg::*;
#(
module pronoc_trace_dump_sub #(
parameter NOC_ID=0,
parameter P = 6,
parameter TRACE_DUMP_PER= "ROUTER", //NOC, ROUTER, PORT
parameter DIRECTION="in", // in,out
parameter CYCLE_REPORT=0 // 1 : enable, 0 : disable
)(
) (
current_r_id,
chan_in,
clk
);
 
input [31:0] current_r_id;
input flit_chanel_t chan_in [P-1 : 0];
input clk;
`NOC_CONF
 
integer out;
string fname [P-1 : 0];
 
genvar p;
generate
for (p=0;p<P;p++)begin
 
input [31:0] current_r_id;
input flit_chanel_t chan_in [P-1 : 0];
input clk;
 
integer out;
string fname [P-1 : 0];
 
genvar p;
generate
for (p=0;p<P;p++)begin
initial begin
/* verilator lint_off WIDTH */
if(TRACE_DUMP_PER == "PORT" ) fname[p] = $sformatf("trace_dump_R%0d_P%0d.out",current_r_id,p);
if(TRACE_DUMP_PER == "ROUTER") fname[p] = $sformatf("trace_dump_R%0d.out",current_r_id);
if(TRACE_DUMP_PER == "NOC" ) fname[p] = $sformatf("trace_dump.out",current_r_id,p);
if(TRACE_DUMP_PER == "NOC" ) fname[p] = $sformatf("trace_dump.out");
/* verilator lint_on WIDTH */
out = $fopen(fname[p],"w");
$fclose(out);
751,8 → 762,8
end
end
 
end
endgenerate
end
endgenerate
endmodule
//synthesis translate_on
 
/routing.v
1,12 → 1,12
`timescale 1ns/1ps
/**********************************************************************
** File: routing.v
**
**
** Copyright (C) 2014-2017 Alireza Monemi
**
** This file is part of ProNoC
**
** ProNoC ( stands for Prototype Network-on-chip) is free software:
** This file is part of ProNoC
**
** ProNoC ( stands for Prototype Network-on-chip) is free software:
** you can redistribute it and/or modify it under the terms of the GNU
** Lesser General Public License as published by the Free Software Foundation,
** either version 2 of the License, or (at your option) any later version.
20,7 → 20,7
** License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
**
**
** Description:
** Description:
** look-ahead and conventional routing algorithms for Mesh and Torus NoC
**
**
28,18 → 28,19
 
 
module conventional_routing #(
parameter TOPOLOGY = "MESH",
parameter NOC_ID = 0,
parameter TOPOLOGY = "MESH",
parameter ROUTE_NAME = "XY",
parameter ROUTE_TYPE = "DETERMINISTIC",
parameter ROUTE_TYPE = "DETERMINISTIC",
parameter T1 = 4,
parameter T2 = 4,
parameter T3 = 4,
parameter RAw = 3,
parameter EAw = 3,
parameter RAw = 3,
parameter EAw = 3,
parameter DSTPw = 4,
parameter LOCATED_IN_NI = 1 // only needed for mesh and odd-even routing
)
(
(
reset,
clk,
current_r_addr,
46,42 → 47,42
src_e_addr,
dest_e_addr,
destport
);
);
 
function integer log2;
input integer number; begin
log2=(number <=1) ? 1: 0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
input reset,clk;
input integer number; begin
log2=(number <=1) ? 1: 0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
 
input reset,clk;
input [RAw-1 :0] current_r_addr;
input [EAw-1 :0] src_e_addr;
input [EAw-1 :0] dest_e_addr;
output [DSTPw-1 :0] destport;
generate
/* verilator lint_off WIDTH */
 
generate
/* verilator lint_off WIDTH */
if(TOPOLOGY == "MESH" || TOPOLOGY == "FMESH" || TOPOLOGY == "TORUS" || TOPOLOGY == "RING" || TOPOLOGY == "LINE") begin :mesh_torus
/* verilator lint_on WIDTH */
/* verilator lint_on WIDTH */
 
localparam
NX = T1,
NY = T2,
RXw = log2(NX),
RYw = log2(NY),
RXw = log2(NX),
RYw = (TOPOLOGY=="RING" || TOPOLOGY == "LINE") ? 1 :log2(NY),
EXw = RXw,
EYw = RYw;
EYw = (TOPOLOGY=="RING" || TOPOLOGY == "LINE") ? 1 : RYw;
 
wire [RXw-1 : 0] current_rx;
wire [RYw-1 : 0] current_ry;
wire [RYw-1 : 0] current_ry;
wire [EXw-1 : 0] dest_ex;
wire [EYw-1 : 0] dest_ey;
 
 
mesh_tori_router_addr_decode #(
.TOPOLOGY(TOPOLOGY),
.T1(T1),
96,10 → 97,10
.ry(current_ry),
.valid( )
);
/* verilator lint_off WIDTH */
 
/* verilator lint_off WIDTH */
if(TOPOLOGY == "FMESH") begin :fmesh
/* verilator lint_on WIDTH */
/* verilator lint_on WIDTH */
fmesh_endp_addr_decode #(
.T1(T1),
.T2(T2),
113,10 → 114,10
.ey(dest_ey),
.ep( ),
.valid()
);
);
 
 
 
end else begin : mesh
mesh_tori_endp_addr_decode #(
.TOPOLOGY(TOPOLOGY),
132,9 → 133,9
.ey(dest_ey),
.el( ),
.valid()
);
);
end//mesh
 
mesh_torus_conventional_routing #(
.TOPOLOGY(TOPOLOGY),
.ROUTE_NAME(ROUTE_NAME),
151,11 → 152,11
.dest_y(dest_ey),
.destport(destport)
);
/* verilator lint_off WIDTH */
 
/* verilator lint_off WIDTH */
end else if(TOPOLOGY == "FATTREE" || TOPOLOGY == "TREE" ) begin :tree_based
/* verilator lint_on WIDTH */
/* verilator lint_on WIDTH */
 
localparam
K=T1,
L=T2,
162,10 → 163,10
Kw = log2(K),
LKw= L*Kw,
Lw = log2(L);
 
wire [LKw-1 :0] current_rx;
wire [Lw-1 :0] current_rl;
wire [Lw-1 :0] current_rl;
 
fattree_router_addr_decode #(
.K(T1),
.L(T2)
175,12 → 176,12
.r_addr(current_r_addr),
.rx(current_rx),
.rl(current_rl)
);
/* verilator lint_off WIDTH */
if(TOPOLOGY == "FATTREE" )begin : fattree
/* verilator lint_on WIDTH */
);
 
/* verilator lint_off WIDTH */
if(TOPOLOGY == "FATTREE" )begin : fattree
/* verilator lint_on WIDTH */
 
fattree_conventional_routing #(
.ROUTE_NAME(ROUTE_NAME),
.K(T1),
194,10 → 195,10
.current_level(current_rl),
.dest_addr_encoded(dest_e_addr),
.destport_encoded(destport)
);
/* verilator lint_off WIDTH */
end else if(TOPOLOGY == "TREE" )begin : tree
/* verilator lint_on WIDTH */
);
/* verilator lint_off WIDTH */
end else if(TOPOLOGY == "TREE" )begin : tree
/* verilator lint_on WIDTH */
tree_conventional_routing #(
.ROUTE_NAME(ROUTE_NAME),
.K(T1),
205,46 → 206,46
)
the_conventional_routing
(
 
.current_addr_encoded(current_rx),
.current_level(current_rl),
.dest_addr_encoded(dest_e_addr),
.destport_encoded(destport)
);
end // tree
/* verilator lint_off WIDTH */
end else if (TOPOLOGY == "STAR") begin : star
/* verilator lint_on WIDTH */
);
end // tree
 
/* verilator lint_off WIDTH */
end else if (TOPOLOGY == "STAR") begin : star
/* verilator lint_on WIDTH */
star_conventional_routing #(
.NE(T1)
.NE(T1)
)
the_conventional_routing
(
(
.dest_e_addr(dest_e_addr),
.destport(destport)
);
);
 
 
 
 
end else begin :custom
 
custom_ni_routing #(
.TOPOLOGY(TOPOLOGY),
.ROUTE_NAME(ROUTE_NAME),
.ROUTE_TYPE(ROUTE_TYPE),
.RAw(RAw),
.EAw(EAw),
.DSTPw(DSTPw)
.RAw(RAw),
.EAw(EAw),
.DSTPw(DSTPw)
)
the_conventional_routing
(
.dest_e_addr(dest_e_addr),
.src_e_addr(src_e_addr),
.destport(destport)
);
.destport(destport)
);
 
end //custom
endgenerate
 
266,41 → 267,42
*************************************/
 
module look_ahead_routing #(
parameter NOC_ID=0,
parameter P = 5,
parameter T1= 8,
parameter T2= 8,
parameter T3= 8,
parameter T4= 8,
parameter RAw = 3,
parameter EAw = 3,
parameter RAw = 3,
parameter EAw = 3,
parameter DAw = 3,
parameter DSTPw=P-1,
parameter SW_LOC =0,
parameter TOPOLOGY ="MESH",//"MESH","TORUS"
parameter ROUTE_NAME="XY",//
parameter ROUTE_NAME="XY",//
parameter ROUTE_TYPE="DETERMINISTIC"// "DETERMINISTIC", "FULL_ADAPTIVE", "PAR_ADAPTIVE"
)
(
current_r_addr, //current router address
neighbors_r_addr,
dest_e_addr, // destination endpoint address
src_e_addr, // source endpoint address. Only needed for custom topology
destport_encoded, // current router destination port number
dest_e_addr, // destination endpoint address
src_e_addr, // source endpoint address. Only needed for custom topology
destport_encoded, // current router destination port number
lkdestport_encoded, // look ahead destination port number
reset,
clk
);
 
function integer log2;
input integer number; begin
log2=(number <=1) ? 1: 0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
localparam
input integer number; begin
log2=(number <=1) ? 1: 0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
 
localparam
PRAw= P * RAw;
localparam
//K= T1,
310,7 → 312,7
LKw= T2 * Kw,
PLw = P * Lw,
PLKw = P * LKw;
 
input [PRAw-1: 0] neighbors_r_addr;
input [RAw-1 : 0] current_r_addr;
input [DAw-1 : 0] dest_e_addr;
318,28 → 320,28
input [DSTPw-1 : 0] destport_encoded;
output [DSTPw-1 : 0] lkdestport_encoded;
input reset,clk;
 
genvar i;
generate
/* verilator lint_off WIDTH */
generate
/* verilator lint_off WIDTH */
if(TOPOLOGY == "MESH" || TOPOLOGY == "FMESH" || TOPOLOGY == "TORUS" || TOPOLOGY == "RING" || TOPOLOGY == "LINE")begin :mesh_torus
/* verilator lint_on WIDTH */
/* verilator lint_on WIDTH */
 
localparam
NX = T1,
NY = T2,
RXw = log2(NX),
RYw = log2(NY),
RXw = log2(NX),
RYw = (TOPOLOGY=="RING" || TOPOLOGY == "LINE")? 1 : log2(NY),
EXw = RXw,
EYw = RYw;
 
wire [RXw-1 : 0] current_rx;
wire [RYw-1 : 0] current_ry;
wire [RYw-1 : 0] current_ry;
wire [EXw-1 : 0] dest_ex;
wire [EYw-1 : 0] dest_ey;
localparam SL_SW_LOC = ( SW_LOC > P-T3) ? 0 : SW_LOC; //single_local
 
localparam SL_SW_LOC = ( SW_LOC > P-T3) ? 0 : SW_LOC; //single_local
 
mesh_tori_router_addr_decode #(
.TOPOLOGY(TOPOLOGY),
.T1(T1),
354,10 → 356,10
.ry(current_ry),
.valid( )
);
/* verilator lint_off WIDTH */
/* verilator lint_off WIDTH */
if(TOPOLOGY == "FMESH") begin :fmesh
/* verilator lint_on WIDTH */
fmesh_endp_addr_decode #(
/* verilator lint_on WIDTH */
fmesh_endp_addr_decode #(
.T1(T1),
.T2(T2),
.T3(T3),
371,7 → 373,7
.ep( ),
.valid()
);
end else begin :mesh
end else begin :mesh
mesh_tori_endp_addr_decode #(
.TOPOLOGY(TOPOLOGY),
.T1(T1),
387,10 → 389,10
.el( ),
.valid()
);
 
 
end
 
mesh_torus_look_ahead_routing #(
.NX(T1),
.NY(T2),
410,18 → 412,18
.reset(reset),
.clk(clk)
);
/* verilator lint_off WIDTH */
/* verilator lint_off WIDTH */
end else if (TOPOLOGY == "FATTREE") begin: fat
/* verilator lint_on WIDTH */
/* verilator lint_on WIDTH */
 
wire [PLKw-1 : 0] neighbors_rx;
wire [PLw-1 : 0] neighbors_ry;
 
for (i=0; i<P; i=i+1) begin : port
assign neighbors_rx[(i+1)*LKw-1: i*LKw] = neighbors_r_addr[(i*RAw)+LKw-1 : i*RAw];
assign neighbors_rx[(i+1)*LKw-1: i*LKw] = neighbors_r_addr[(i*RAw)+LKw-1 : i*RAw];
assign neighbors_ry[(i+1)*Lw-1 : i*Lw] = neighbors_r_addr[(i+1)*RAw-1: (i*RAw)+LKw];
end//port
end//port
 
fattree_look_ahead_routing #(
.ROUTE_NAME(ROUTE_NAME),
.P(P),
438,20 → 440,20
.reset(reset),
.clk(clk)
);
/* verilator lint_off WIDTH */
 
/* verilator lint_off WIDTH */
end else if (TOPOLOGY == "TREE") begin: tree
/* verilator lint_on WIDTH */
/* verilator lint_on WIDTH */
 
wire [PLKw-1 : 0] neighbors_rx_tree;
wire [PLw-1 : 0] neighbors_ry_tree;
 
for (i=0; i<P; i=i+1) begin : port
assign neighbors_rx_tree[(i+1)*LKw-1: i*LKw] = neighbors_r_addr[(i*RAw)+LKw-1 : i*RAw];
assign neighbors_rx_tree[(i+1)*LKw-1: i*LKw] = neighbors_r_addr[(i*RAw)+LKw-1 : i*RAw];
assign neighbors_ry_tree[(i+1)*Lw-1 : i*Lw] = neighbors_r_addr[(i+1)*RAw-1: (i*RAw)+LKw];
end//port
end//port
 
 
tree_look_ahead_routing #(
.ROUTE_NAME(ROUTE_NAME),
.P(P),
468,22 → 470,22
.reset(reset),
.clk(clk)
);
/* verilator lint_off WIDTH */
end else if (TOPOLOGY == "STAR") begin : star
/* verilator lint_on WIDTH */
 
/* verilator lint_off WIDTH */
end else if (TOPOLOGY == "STAR") begin : star
/* verilator lint_on WIDTH */
//look-ahead routing is not needed in star topology as there is only one router
assign lkdestport_encoded={DSTPw{1'b0}};
 
end else begin : custom
 
custom_lkh_routing #(
.TOPOLOGY(TOPOLOGY),
.ROUTE_NAME(ROUTE_NAME),
.ROUTE_TYPE(ROUTE_TYPE),
.RAw(RAw),
.EAw(EAw),
.DSTPw(DSTPw)
.RAw(RAw),
.EAw(EAw),
.DSTPw(DSTPw)
)
look_ahead_routing
(
494,17 → 496,17
.reset(reset),
.clk(clk)
);
 
end
endgenerate
endmodule
 
/********************************************************
 
next_router_addr_selector
Determine the next router address based on the packet destination port
 
Determine the next router address based on the packet destination port
 
********************************************************/
 
 
518,22 → 520,22
neighbors_rx,
neighbors_ry,
next_rx,
next_ry
next_ry
);
 
localparam
PRXw = P * RXw,
PRYw = P * RYw;
PRYw = P * RYw;
 
input [P-1 : 0] destport_onehot;
input [PRXw-1: 0] neighbors_rx;
input [PRYw-1: 0] neighbors_ry;
output[RXw-1 : 0] next_rx;
output[RYw-1 : 0] next_ry;
output[RYw-1 : 0] next_ry;
 
onehot_mux_1D #(
.W(RXw),
.N(P)
.N(P)
)
next_x_mux
(
541,10 → 543,10
.out(next_rx),
.sel(destport_onehot)
);
 
onehot_mux_1D #(
.W(RYw),
.N(P)
.N(P)
)
next_y_mux
(
552,13 → 554,13
.out(next_ry),
.sel(destport_onehot)
);
endmodule
 
endmodule
 
 
 
 
 
module next_router_addr_selector_bin #(
parameter P = 5,
parameter RXw = 3, // The router's x dimension adress width in bits
569,30 → 571,30
neighbors_rx,
neighbors_ry,
next_rx,
next_ry
next_ry
 
);
 
function integer log2;
input integer number; begin
log2=(number <=1) ? 1: 0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
input integer number; begin
log2=(number <=1) ? 1: 0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
 
localparam
Pw = log2(P),
PRXw = P * RXw,
PRYw = P * RYw;
PRYw = P * RYw;
 
input [Pw-1 : 0] destport_bin;
input [PRXw-1: 0] neighbors_rx;
input [PRYw-1: 0] neighbors_ry;
output[RXw-1 : 0] next_rx;
output[RYw-1 : 0] next_ry;
output[RYw-1 : 0] next_ry;
 
binary_mux #(
.IN_WIDTH(PRXw),
.OUT_WIDTH(RXw)
603,7 → 605,7
.mux_out(next_rx),
.sel(destport_bin)
);
 
binary_mux #(
.IN_WIDTH(PRYw),
.OUT_WIDTH(RYw)
614,9 → 616,9
.mux_out(next_ry),
.sel(destport_bin)
);
endmodule
 
endmodule
 
 
 
 
/ss_allocator.sv
34,12 → 34,10
***************************************/
 
 
module ss_allocator
import pronoc_pkg::*;
#(
parameter P = 5
)
(
module ss_allocator #(
parameter NOC_ID=0,
parameter P=5
)(
clk,
reset,
flit_in_wr_all,
51,12 → 49,14
// dest_port_encoded_all,
// assigned_ovc_num_all,
// ovc_is_assigned_all,
ivc_info,
ivc_info,
ovc_info,
ssa_ctrl_o
);
 
 
`NOC_CONF
localparam PV = V * P,
VV = V * V,
PVV = PV * V,
64,21 → 64,7
PFw = P * Fw;
localparam DISABLED = P;
//MESH, TORUS Topology p=5
localparam EAST = 1,
NORTH = 2,
WEST = 3,
SOUTH = 4;
//LINE RING Topology p=3
localparam FORWARD = 1,
BACKWARD= 2;
 
input [PFw-1 : 0] flit_in_all;
input [P-1 : 0] flit_in_wr_all;
117,7 → 103,7
wire [PVV-1 : 0] assigned_ovc_num_all;
wire [PV-1 : 0] ovc_is_assigned_all;
wire [MAX_P-1 : 0] destport_one_hot [PV-1 : 0];
 
genvar i;
// there is no ssa for local port in 5 and 3 port routers
generate
167,6 → 153,7
ssa_per_vc #(
.NOC_ID(NOC_ID),
.SS_PORT(SS_PORT),
.V_GLOBAL(i),
.P(P)
247,13 → 234,12
* ssa_per_vc
* ***********/
 
module ssa_per_vc
import pronoc_pkg::*;
#(
module ssa_per_vc #(
parameter NOC_ID=0,
parameter P=5,
parameter SS_PORT = "WEST",
parameter V_GLOBAL = 1,
parameter P=5
)
parameter V_GLOBAL = 1
)
(
flit_in_wr,
flit_in,
281,7 → 267,10
//synthesis translate_on
);
);
`NOC_CONF
//header packet filds width
289,7 → 278,7
V_LOCAL =V_GLOBAL%V;
 
/* verilator lint_off WIDTH */
localparam SSA_EN = ((TOPOLOGY== "MESH" || TOPOLOGY == "TORUS") && (ROUTE_TYPE == "FULL_ADAPTIVE") && (SS_PORT==2 || SS_PORT == 4) && ((1<<V_LOCAL & ~ESCAP_VC_MASK ) != {V{1'b0}})) ? 1'b0 :1'b1;
localparam SSA_EN_IN_PORT = ((TOPOLOGY== "MESH" || TOPOLOGY == "TORUS") && (ROUTE_TYPE == "FULL_ADAPTIVE") && (SS_PORT==2 || SS_PORT == 4) && ((1<<V_LOCAL & ~ESCAP_VC_MASK ) != {V{1'b0}})) ? 1'b0 :1'b1;
/* verilator lint_on WIDTH */
347,14 → 336,13
/* verilator lint_on WIDTH */
wire condition_1_2_valid;
wire condition_1_2_valid;
wire [DAw-1 : 0] dest_e_addr_in;
extract_header_flit_info #(
.NOC_ID(NOC_ID),
.DATA_w(0)
)
extractor
(
) extractor (
.flit_in(flit_in),
.flit_in_wr(flit_in_wr),
.class_o(),
368,7 → 356,7
.weight_o( ),
.be_o( ),
.data_o( )
);
);
 
380,8 → 368,9
wire ss_port_hdr_flit, ss_port_nonhdr_flit;
 
ssa_check_destport #(
.NOC_ID(NOC_ID),
.SW_LOC(SW_LOC),
.P(P),
.P(P),
.SS_PORT(SS_PORT)
)
check_destport
417,7 → 406,7
 
 
generate
if (SSA_EN) begin : enable
if (SSA_EN_IN_PORT) begin : enable
assign ssa_permited_by_iport = ss_ovc_ready & (~ivc_request) & condition_1_2_valid;
end else begin : disabled
assign ssa_permited_by_iport = 1'b0;
455,13 → 444,13
 
 
 
module ssa_check_destport
import pronoc_pkg::*;
#(
module ssa_check_destport #(
parameter NOC_ID=0,
parameter SW_LOC = 0,
parameter P=5,
parameter P=5,
parameter SS_PORT=0
)(
)
(
destport_encoded, //non header flit dest port
destport_in_encoded, // header flit packet dest port
ss_port_hdr_flit, // asserted if the header incomming flit goes to ss port
477,7 → 466,13
//synopsys translate_on
//synthesis translate_on
);
 
`NOC_CONF
 
 
 
 
//synthesis translate_off
//synopsys translate_off
input clk, ivc_num_getting_sw_grant, hdr_flg;
531,7 → 526,7
//synopsys translate_on
//synthesis translate_on
 
);
);
/* verilator lint_off WIDTH */
end else if (TOPOLOGY == "FMESH") begin :fmesh
/* verilator lint_on WIDTH */
587,7 → 582,7
assign ss_port_nonhdr_flit = destport_one_hot [SS_PORT];
assign ss_port_hdr_flit = destport_one_hot_in [SS_PORT];
end else begin : line
end else begin : line
line_ring_ssa_check_destport #(
.ROUTE_TYPE(ROUTE_TYPE),
.SW_LOC(SW_LOC),
617,16 → 612,19
**************************/
 
module add_ss_port
import pronoc_pkg::*;
#(
parameter SW_LOC=1,
parameter P=5
module add_ss_port #(
parameter NOC_ID=0,
parameter SW_LOC=0,
parameter P=5
)(
destport_in,
destport_out
);
 
 
`NOC_CONF
 
 
localparam SS_PORT = strieght_port(P,SW_LOC);
localparam DISABLED = P;
localparam P_1 = ( SELF_LOOP_EN=="NO")? P-1 : P;
/star_noc.sv
13,9 → 13,9
***************************************/
 
module star_noc_top
import pronoc_pkg::*;
(
module star_noc_top #(
parameter NOC_ID=0
) (
reset,
clk,
chan_in_all,
23,6 → 23,7
router_event
);
`NOC_CONF
input clk,reset;
//Endpoints ports
34,6 → 35,7
router_top # (
.NOC_ID(NOC_ID),
.P(NE)
)
the_router
/traffic_gen_top.sv
1,11 → 1,10
`include "pronoc_def.v"
 
module traffic_gen_top
import pronoc_pkg::*;
#(
parameter MAX_RATIO = 1000,
parameter ENDP_ID = 100000
)
module traffic_gen_top #(
parameter NOC_ID=0,
parameter MAX_RATIO = 1000,
parameter ENDP_ID = 100000
)
(
//noc port
45,6 → 44,11
clk
);
`NOC_CONF
localparam
RATIOw= $clog2(MAX_RATIO);
59,11 → 63,9
localparam
PCK_CNTw = log2(MAX_PCK_NUM+1),
CLK_CNTw = log2(MAX_SIM_CLKs+1),
PCK_SIZw = log2(MAX_PCK_SIZ+1),
CLK_CNTw = log2(MAX_SIM_CLKs+1),
AVG_PCK_SIZw = log2(10*MAX_PCK_SIZ+1),
/* verilator lint_off WIDTH */
DISTw = (TOPOLOGY=="FATTREE" || TOPOLOGY=="TREE" ) ? log2(2*L+1): log2(NR+1),
/* verilator lint_off WIDTH */
W=WEIGHTw,
PORT_B = (TOPOLOGY!="FMESH")? LB :
(ENDP_ID < NE_MESH_TORI)? LB :B; // in FMESH, the buffer size of endpoints connected to edge routers non-local ports are B not LB
142,6 → 144,10
reg inject_en,cand_wr_vc_en,pck_rd;
reg [PCK_SIZw-1 :0] pck_size;
logic [DAw-1 :0] dest_e_addr_reg,dest_e_addr_o;
 
 
 
 
// synopsys translate_off
// synthesis translate_off
151,7 → 157,7
reg tt;
always @(posedge clk) begin
if(reset)begin
if(`pronoc_reset)begin
tt<=1'b0;
end else begin
if(flit_out_wr && tt==1'b0 )begin
164,12 → 170,8
// synthesis translate_on
// synopsys translate_on
localparam
HDR_DATA_w = (MIN_PCK_SIZE==1)? CLK_CNTw : 0,
HDR_Dw = (MIN_PCK_SIZE==1)? CLK_CNTw : 1;
180,261 → 182,212
wire [DSTPw-1 : 0] destport;
wire [V-1 : 0] ovc_wr_in;
wire [V-1 : 0] full_vc,empty_vc,nearly_full_vc;
reg [V-1 : 0] wr_vc,wr_vc_next;
wire [V-1 : 0] cand_vc;
wire [DSTPw-1 : 0] destport;
wire [V-1 : 0] ovc_wr_in;
wire [V-1 : 0] full_vc,empty_vc,nearly_full_vc;
reg [V-1 : 0] wr_vc,wr_vc_next;
wire [V-1 : 0] cand_vc;
wire [CLK_CNTw-1 : 0] wr_timestamp,pck_timestamp;
wire hdr_flit,tail_flit;
reg [PCK_SIZw-1 : 0] flit_counter;
reg flit_cnt_rst,flit_cnt_inc;
wire rd_hdr_flg,rd_tail_flg;
wire [Cw-1 : 0] rd_class_hdr;
// wire [P_1-1 : 0] rd_destport_hdr;
wire [DAw-1 : 0] rd_des_e_addr;
wire [EAw-1 : 0] rd_src_e_addr;
wire [CLK_CNTw-1 : 0] wr_timestamp,pck_timestamp;
wire hdr_flit,tail_flit;
reg [PCK_SIZw-1 : 0] flit_counter;
reg flit_cnt_rst,flit_cnt_inc;
wire rd_hdr_flg,rd_tail_flg;
wire [Cw-1 : 0] rd_class_hdr;
// wire [P_1-1 : 0] rd_destport_hdr;
wire [DAw-1 : 0] rd_des_e_addr;
wire [EAw-1 : 0] rd_src_e_addr;
reg [CLK_CNTw-1 : 0] rsv_counter;
reg [CLK_CNTw-1 : 0] clk_counter;
wire [Vw-1 : 0] rd_vc_bin;//,wr_vc_bin;
reg [CLK_CNTw-1 : 0] rsv_time_stamp[V-1:0];
reg [PCK_SIZw-1 : 0] rsv_pck_size [V-1:0];
wire [V-1 : 0] rd_vc;
wire wr_vc_is_full,wr_vc_avb,wr_vc_is_empty;
reg [V-1 : 0] credit_out_next;
reg [EAw-1 : 0] rsv_pck_src_e_addr [V-1:0];
reg [Cw-1 : 0] rsv_pck_class_in [V-1:0];
reg [CLK_CNTw-1 : 0] rsv_counter;
reg [CLK_CNTw-1 : 0] clk_counter;
wire [Vw-1 : 0] rd_vc_bin;//,wr_vc_bin;
reg [CLK_CNTw-1 : 0] rsv_time_stamp[V-1:0];
reg [PCK_SIZw-1 : 0] rsv_pck_size [V-1:0];
wire [V-1 : 0] rd_vc;
wire wr_vc_is_full,wr_vc_avb,wr_vc_is_empty;
reg [V-1 : 0] credit_out_next;
reg [EAw-1 : 0] rsv_pck_src_e_addr [V-1:0];
reg [Cw-1 : 0] rsv_pck_class_in [V-1:0];
wire [CLK_CNTw-1 : 0] hdr_flit_timestamp;
wire pck_wr,buffer_full,pck_ready,valid_dst;
wire [CLK_CNTw-1 : 0] rd_timestamp;
wire [CLK_CNTw-1 : 0] hdr_flit_timestamp;
wire pck_wr,buffer_full,pck_ready,valid_dst;
wire [CLK_CNTw-1 : 0] rd_timestamp;
logic [DELAYw-1 : 0] start_delay_counter,start_delay_counter_next;
logic start_en_next , start_en;
logic [DELAYw-1 : 0] start_delay_counter,start_delay_counter_next;
logic start_en_next , start_en;
 
pronoc_register #(.W(1)) streg1 (.reset(reset),.clk(clk), .in(start_en_next), .out(start_en) );
pronoc_register #(.W(DELAYw)) streg2 (.reset(reset),.clk(clk), .in(start_delay_counter_next), .out(start_delay_counter) );
pronoc_register #(.W(1)) streg1 (.reset(reset),.clk(clk), .in(start_en_next), .out(start_en) );
pronoc_register #(.W(DELAYw)) streg2 (.reset(reset),.clk(clk), .in(start_delay_counter_next), .out(start_delay_counter) );
always @(*) begin
start_en_next =start_en;
start_delay_counter_next= start_delay_counter;
if(start) begin
start_en_next=1'b1;
start_delay_counter_next={DELAYw{1'b0}};
end else if(start_en && ~inject_en) begin
start_delay_counter_next= start_delay_counter + 1'b1;
end
if(stop) begin
start_en_next=1'b0;
end
end//always
always @(*) begin
start_en_next =start_en;
start_delay_counter_next= start_delay_counter;
if(start) begin
start_en_next=1'b1;
start_delay_counter_next={DELAYw{1'b0}};
end else if(start_en && ~inject_en) begin
start_delay_counter_next= start_delay_counter + 1'b1;
end
if(stop) begin
start_en_next=1'b0;
end
end//always
wire start_injection = (start_delay_counter == start_delay);
wire start_injection = (start_delay_counter == start_delay);
check_destination_addr #(
.TOPOLOGY(TOPOLOGY),
.T1(T1),
.T2(T2),
.T3(T3),
.EAw(EAw),
.SELF_LOOP_EN(SELF_LOOP_EN),
.DAw(DAw),
.CAST_TYPE(CAST_TYPE),
.NE(NE)
)
check_destination_addr(
.dest_e_addr(dest_e_addr),
.current_e_addr(current_e_addr),
.dest_is_valid(valid_dst)
);
//assign hdr_flit_sent=pck_rd;
injection_ratio_ctrl #
(
.MAX_PCK_SIZ(MAX_PCK_SIZ),
.MAX_RATIO(MAX_RATIO)
)
pck_inject_ratio_ctrl
(
.en(inject_en),
.pck_size_in(pck_size_tmp),
.clk(clk),
.reset(reset),
.freez(buffer_full),
.inject(pck_wr),
.ratio(ratio)
);
check_destination_addr #(
.NOC_ID(NOC_ID),
.TOPOLOGY(TOPOLOGY),
.T1(T1),
.T2(T2),
.T3(T3),
.EAw(EAw),
.SELF_LOOP_EN(SELF_LOOP_EN),
.DAw(DAw),
.CAST_TYPE(CAST_TYPE),
.NE(NE)
) check_destination_addr (
.dest_e_addr(dest_e_addr),
.current_e_addr(current_e_addr),
.dest_is_valid(valid_dst)
);
//assign hdr_flit_sent=pck_rd;
injection_ratio_ctrl # (
.MAX_PCK_SIZ(MAX_PCK_SIZ),
.MAX_RATIO(MAX_RATIO)
) pck_inject_ratio_ctrl (
.en(inject_en),
.pck_size_in(pck_size_tmp),
.clk(clk),
.reset(reset),
.freez(buffer_full),
.inject(pck_wr),
.ratio(ratio)
);
output_vc_status #(
.CRDTw(CRDTw),
.V (V),
.B (PORT_B)
)
nic_ovc_status
(
.credit_init_val_in ( chan_in.ctrl_chanel.credit_init_val),
.wr_in (ovc_wr_in),
.credit_in (credit_in),
.nearly_full_vc (nearly_full_vc),
.full_vc (full_vc),
.empty_vc (empty_vc),
.cand_vc (cand_vc),
.cand_wr_vc_en (cand_wr_vc_en),
.clk (clk),
.reset (reset)
);
output_vc_status #(
.CRDTw(CRDTw),
.V (V),
.B (PORT_B)
) nic_ovc_status (
.credit_init_val_in ( chan_in.ctrl_chanel.credit_init_val),
.wr_in (ovc_wr_in),
.credit_in (credit_in),
.nearly_full_vc (nearly_full_vc),
.full_vc (full_vc),
.empty_vc (empty_vc),
.cand_vc (cand_vc),
.cand_wr_vc_en (cand_wr_vc_en),
.clk (clk),
.reset (reset)
);
packet_gen #(
.P(MAX_P),
.PCK_TYPE(PCK_TYPE),
.ROUTE_TYPE(ROUTE_TYPE),
.MAX_PCK_NUM(MAX_PCK_NUM),
.MAX_SIM_CLKs(MAX_SIM_CLKs),
.TIMSTMP_FIFO_NUM(TIMSTMP_FIFO_NUM),
.MIN_PCK_SIZE(MIN_PCK_SIZE),
.MAX_PCK_SIZ(MAX_PCK_SIZ)
)
packet_buffer
(
.reset(reset),
.clk(clk),
.pck_wr(pck_wr),
.pck_rd(pck_rd),
.current_r_addr(current_r_addr),
.current_e_addr(current_e_addr),
.clk_counter(clk_counter+1'b1),//in case of zero load latency, the flit will be injected in the next clock cycle
.pck_number(pck_number),
.dest_e_addr_in(dest_e_addr),
.dest_e_addr_o(dest_e_addr_o),
.pck_timestamp(pck_timestamp),
.buffer_full(buffer_full),
.pck_ready(pck_ready),
.valid_dst(valid_dst),
.destport(destport),
.pck_size_in(pck_size_tmp),
.pck_size_o(pck_size)
);
packet_gen #(
.NOC_ID(NOC_ID),
.P(MAX_P)
) packet_buffer (
.reset(reset),
.clk(clk),
.pck_wr(pck_wr),
.pck_rd(pck_rd),
.current_r_addr(current_r_addr),
.current_e_addr(current_e_addr),
.clk_counter(clk_counter+1'b1),//in case of zero load latency, the flit will be injected in the next clock cycle
.pck_number(pck_number),
.dest_e_addr_in(dest_e_addr),
.dest_e_addr_o(dest_e_addr_o),
.pck_timestamp(pck_timestamp),
.buffer_full(buffer_full),
.pck_ready(pck_ready),
.valid_dst(valid_dst),
.destport(destport),
.pck_size_in(pck_size_tmp),
.pck_size_o(pck_size)
);
assign wr_timestamp =pck_timestamp;
assign update = flit_in_wr & flit_in[Fw-2];
assign hdr_flit = (flit_counter == 0);
assign tail_flit = (flit_counter == pck_size-1'b1);
assign time_stamp_h2h = hdr_flit_timestamp - rd_timestamp;
assign time_stamp_h2t = clk_counter - rd_timestamp;
 
wire [FPAYw-1 : 0] flit_out_pyload;
wire [1 : 0] flit_out_hdr;
wire [FPAYw-1 : 0] flit_out_header_pyload;
wire [Fw-1 : 0] hdr_flit_out;
assign hdr_data_in = (MIN_PCK_SIZE==1)? wr_timestamp[HDR_Dw-1 : 0] : {HDR_Dw{1'b0}};
assign wr_timestamp =pck_timestamp;
header_flit_generator #(
.NOC_ID(NOC_ID),
.DATA_w(HDR_DATA_w)
) the_header_flit_generator (
.flit_out(hdr_flit_out),
.vc_num_in(wr_vc),
.class_in(pck_class_in),
.dest_e_addr_in(dest_e_addr_o),
.src_e_addr_in(current_e_addr),
.weight_in(init_weight),
.destport_in(destport),
.data_in(hdr_data_in),
.be_in({BEw{1'b1}} )// Be is not used in simulation as we dont sent real data
);
assign update = flit_in_wr & flit_in[Fw-2];
assign hdr_flit = (flit_counter == 0);
assign tail_flit = (flit_counter == pck_size-1'b1);
assign flit_out_class = pck_class_in;
assign flit_out_hdr = {hdr_flit,tail_flit};
assign time_stamp_h2h = hdr_flit_timestamp - rd_timestamp;
assign time_stamp_h2t = clk_counter - rd_timestamp;
 
wire [FPAYw-1 : 0] flit_out_pyload;
wire [1 : 0] flit_out_hdr;
 
wire [FPAYw-1 : 0] flit_out_header_pyload;
wire [Fw-1 : 0] hdr_flit_out;
assign hdr_data_in = (MIN_PCK_SIZE==1)? wr_timestamp[HDR_Dw-1 : 0] : {HDR_Dw{1'b0}};
header_flit_generator #(
.DATA_w(HDR_DATA_w)
)
the_header_flit_generator
(
.flit_out(hdr_flit_out),
.vc_num_in(wr_vc),
.class_in(pck_class_in),
.dest_e_addr_in(dest_e_addr_o),
.src_e_addr_in(current_e_addr),
.weight_in(init_weight),
.destport_in(destport),
.data_in(hdr_data_in),
.be_in({BEw{1'b1}} )// Be is not used in simulation as we dont sent real data
);
assign flit_out_class = pck_class_in;
assign flit_out_hdr = {hdr_flit,tail_flit};
assign flit_out_header_pyload = hdr_flit_out[FPAYw-1 : 0];
assign flit_out_header_pyload = hdr_flit_out[FPAYw-1 : 0];
/* verilator lint_off WIDTH */
assign flit_out_pyload = (hdr_flit) ? flit_out_header_pyload :
(tail_flit) ? wr_timestamp:
{pck_number,flit_counter};
/* verilator lint_off WIDTH */
assign flit_out_pyload = (hdr_flit) ? flit_out_header_pyload :
(tail_flit) ? wr_timestamp:
{pck_number,flit_counter};
/* verilator lint_on WIDTH */
assign flit_out = {flit_out_hdr, wr_vc, flit_out_pyload };
assign flit_out = {flit_out_hdr, wr_vc, flit_out_pyload };
 
 
//extract header flit info
//extract header flit info
extract_header_flit_info #(
.NOC_ID(NOC_ID),
.DATA_w(HDR_DATA_w)
) header_extractor (
.flit_in(flit_in),
.flit_in_wr(flit_in_wr),
.class_o(rd_class_hdr),
.destport_o(),
.dest_e_addr_o(rd_des_e_addr),
.src_e_addr_o(rd_src_e_addr),
.vc_num_o(rd_vc),
.hdr_flit_wr_o( ),
.hdr_flg_o(rd_hdr_flg),
.tail_flg_o(rd_tail_flg),
.weight_o( ),
.be_o( ),
.data_o(rd_hdr_data_out)
);
 
extract_header_flit_info #(
.DATA_w(HDR_DATA_w)
)
header_extractor
(
.flit_in(flit_in),
.flit_in_wr(flit_in_wr),
.class_o(rd_class_hdr),
.destport_o(),
.dest_e_addr_o(rd_des_e_addr),
.src_e_addr_o(rd_src_e_addr),
.vc_num_o(rd_vc),
.hdr_flit_wr_o( ),
.hdr_flg_o(rd_hdr_flg),
.tail_flg_o(rd_tail_flg),
.weight_o( ),
.be_o( ),
.data_o(rd_hdr_data_out)
);
distance_gen #(
.TOPOLOGY(TOPOLOGY),
.T1(T1),
.T2(T2),
.T3(T3),
.EAw(EAw),
.DISTw(DISTw)
)
the_distance_gen
(
.src_e_addr(src_e_addr),
.dest_e_addr(current_e_addr),
.distance(distance)
);
distance_gen #(
.TOPOLOGY(TOPOLOGY),
.T1(T1),
.T2(T2),
.T3(T3),
.EAw(EAw),
.DISTw(DISTw)
) the_distance_gen (
.src_e_addr(src_e_addr),
.dest_e_addr(current_e_addr),
.distance(distance)
);
generate
453,7 → 406,7
end
 
 
if(V==1) begin : v1
if(V==1) begin : v1
assign rd_vc_bin=1'b0;
// assign wr_vc_bin=1'b0;
end else begin :vother
477,7 → 430,8
assign ovc_wr_in = (flit_out_wr ) ? wr_vc : {V{1'b0}};
/* verilator lint_off WIDTH */
assign wr_vc_is_full = (SSA_EN=="NO")? | ( full_vc & wr_vc) : | (nearly_full_vc & wr_vc);
//assign wr_vc_is_full = (SSA_EN=="NO")? | ( full_vc & wr_vc) : | (nearly_full_vc & wr_vc);
assign wr_vc_is_full = | ( full_vc & wr_vc);
/* verilator lint_on WIDTH */
648,12 → 602,14
wire [NEw-1 : 0] sum_temp;
wire is_unicast;
mcast_dest_list_decode decode1 (
.dest_e_addr(dest_e_addr_o),
.dest_o(dest_mcast_all_endp1),
.row_has_any_dest(),
.is_unicast(is_unicast)
);
mcast_dest_list_decode #(
.NOC_ID(NOC_ID)
) decode1 (
.dest_e_addr(dest_e_addr_o),
.dest_o(dest_mcast_all_endp1),
.row_has_any_dest(),
.is_unicast(is_unicast)
);
/* verilator lint_off WIDTH */
if (CAST_TYPE == "BROADCAST_FULL") begin :bcastf
712,13 → 668,16
wire [NE-1 :0] dest_mcast_all_endp2;
generate
if(CAST_TYPE != "UNICAST") begin :no_unicast
mcast_dest_list_decode decode2 (
.dest_e_addr(rd_des_e_addr),
.dest_o(dest_mcast_all_endp2),
.row_has_any_dest(),
.is_unicast()
);
end endgenerate
mcast_dest_list_decode #(
.NOC_ID(NOC_ID)
) decode2 (
.dest_e_addr(rd_des_e_addr),
.dest_o(dest_mcast_all_endp2),
.row_has_any_dest(),
.is_unicast()
);
end
endgenerate
846,14 → 805,10
// if (chan_out.smart_chanel.requests > {SMART_NUM{1'b0}} ) endp_is_active=1'b1;
// end
// `endif
 
endmodule
 
 
 
 
 
/*****************************
injection_ratio_ctrl
984,16 → 939,9
 
module packet_gen
import pronoc_pkg::*;
#(
parameter P = 5,
parameter PCK_TYPE = "SINGLE_FLIT",
parameter ROUTE_TYPE = "DETERMINISTIC",
parameter MAX_PCK_NUM = 10000,
parameter MAX_SIM_CLKs = 100000,
parameter TIMSTMP_FIFO_NUM=16,
parameter MIN_PCK_SIZE=2,
parameter MAX_PCK_SIZ=100
#(
parameter NOC_ID=0,
parameter P = 5
)(
clk_counter,
pck_wr,
1013,21 → 961,14
clk,
reset
);
 
function integer log2;
input integer number; begin
log2=(number <=1) ? 1: 0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
`NOC_CONF
localparam
PCK_CNTw = log2(MAX_PCK_NUM+1),
CLK_CNTw = log2(MAX_SIM_CLKs+1),
PCK_SIZw = log2(MAX_PCK_SIZ);
CLK_CNTw = log2(MAX_SIM_CLKs+1);
 
input reset,clk, pck_wr, pck_rd;
input [RAw-1 :0] current_r_addr;
1051,6 → 992,7
generate if(CAST_TYPE == "UNICAST") begin : uni
conventional_routing #(
.NOC_ID(NOC_ID),
.TOPOLOGY(TOPOLOGY),
.ROUTE_NAME(ROUTE_NAME),
.ROUTE_TYPE(ROUTE_TYPE),
/tree_noc_top.sv
13,17 → 13,18
***************************************/
 
module tree_noc_top
import pronoc_pkg::*;
(
reset,
clk,
chan_in_all,
chan_out_all,
router_event
);
module tree_noc_top #(
parameter NOC_ID=0
) (
reset,
clk,
chan_in_all,
chan_out_all,
router_event
);
`NOC_CONF
input clk,reset;
//Endpoints ports
input smartflit_chanel_t chan_in_all [NE-1 : 0];
56,8 → 57,6
localparam
PV = V * MAX_P,
PFw = MAX_P * Fw,
NEFw = NE * Fw,
NEV = NE * V,
CONG_ALw = CONGw * MAX_P,
PLKw = MAX_P * LKw,
PLw = MAX_P * Lw,
86,6 → 85,7
 
router_top # (
.NOC_ID(NOC_ID),
.P(K)
)
root_router
111,7 → 111,8
for( pos=0; pos<NPOS1; pos=pos+1) begin : pos_lp
localparam RID = NRATTOP1+pos;
router_top # (
.P(K+1)// leaves have K+1 port number
.NOC_ID(NOC_ID),
.P(K+1)// leaves have K+1 port number
)
the_router
(
/wrra.v
737,6 → 737,7
***************/
 
module weights_update # (
parameter NOC_ID=0,
parameter ARBITER_TYPE="WRRA",
parameter V=4,
parameter P=5,
799,6 → 800,7
for (i=1; i<P; i=i+1) begin : non_local_port
weight_update_per_port #(
.NOC_ID(NOC_ID),
.V(V),
.C(C),
.P(P),
967,6 → 969,7
 
 
module weight_update_per_port # (
parameter NOC_ID=0,
parameter V=4,
parameter C=2,
parameter P=5,
985,16 → 988,11
flit_out_wr,
clk,
reset
);
);
 
 
localparam
W=WEIGHTw;
localparam WEIGHT_LATCHED = 0; //(WRRA_CONFIG_INDEX==0 || WRRA_CONFIG_INDEX==1 || WRRA_CONFIG_INDEX==2 || WRRA_CONFIG_INDEX==3 ); //1: no latched 0: latched
W=WEIGHTw,
WEIGHT_LATCHED = 0; //(WRRA_CONFIG_INDEX==0 || WRRA_CONFIG_INDEX==1 || WRRA_CONFIG_INDEX==2 || WRRA_CONFIG_INDEX==3 ); //1: no latched 0: latched
input [W-1 : 0] contention_in;
1047,8 → 1045,9
wire [Fw-1 : 0] hdr_flit_new;
hdr_flit_weight_update updater
(
hdr_flit_weight_update #(
.NOC_ID(NOC_ID)
) updater (
.new_weight(contention),
.flit_in(flit_in),
.flit_out(hdr_flit_new)

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