OpenCores
URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

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Rev 45 → Rev 48

/model.tcl
1,126 → 1,36
#!/usr/bin/tclsh
###################################################################
## Author : Alireza Monemi
## Email :
## Description : Compile all verilog files inside the design folder
## : using modelsim
###################################################################
set text "###################################################################"
set text "## Start Compilation Script "
set text "###################################################################"
 
###################################################################
##---- Specify variables
set text "###################################################################"
set text "##---- Specify variables"
#Get tcl shell path relative to current script
set tcl_path [file dirname [info script]]
if { [info exists $::env(LM_WORK_PLACE)] } {
puts "You need to define the work dir as LM_WORK_PLACE linux envirement variable \n"
exit(1)
}
 
##-- Project path variables
set path [pwd]/..
set src_noc_path $path/src_noc
set src_modelsim_path $path/src_modelsim
set comp_path $path/../mpsoc_work/modelsim
set work_path $comp_path/work
set file_list [glob -directory $src_noc_path *.v]
set modelsim_file_list [glob -directory $src_modelsim_path *.v]
 
 
##-- change directory
file mkdir $comp_path
 
cd $comp_path
exec rm -Rf *
proc r {} {uplevel #0 source compile.tcl}
proc rr {} {global last_compile_time
set last_compile_time 0
r }
proc q {} {quit -force }
 
proc sleep {N} {
after [expr {int($N * 1000)}]
if { [info exists $::env(LM_FILE_LIST)] } {
puts "You need to define the file list path as LM_FILE_LIST linux envirement variable \n"
exit(1)
}
 
 
#Does this installation support Tk?
set tk_ok 1
if [catch {package require Tk}] {set tk_ok 0}
 
###################################################################
##---- 1. Creating working library
set text "###################################################################"
set text "##---- 1. Creating working library"
 
##-- Create work lib
vlib $work_path
set rtl_work $::env(LM_WORK_PLACE)/rtl_work
 
##-- Mapping work lib
vmap work $work_path
 
 
 
###################################################################
##---- 3. Compile the Design
set text "###################################################################"
set text "##---- 3. Compile the Design"
 
 
# Compile out of date files
set time_now [clock seconds]
 
if {[file isfile start_time.txt] != 0} {
set fp [open start_time.txt r]
set line [gets $fp]
close $fp
regexp {\d+} $line last_compile_time
puts "last compiled time is $last_compile_time"
} else {
set last_compile_time 0
transcript on
if {[file exists $rtl_work]} {
vdel -lib $rtl_work -all
}
vlib $rtl_work
vmap work $rtl_work
 
set last_compile_time 0
 
foreach f $file_list {
if { $last_compile_time < [file mtime $f] } {
vlog -work $work_path +incdir+$src_noc_path $f
set last_compile_time 0
} else {
puts "$f is uptodate"
}
}
vlog +acc=rn -F $::env(LM_FILE_LIST)
 
foreach f $modelsim_file_list {
if { $last_compile_time < [file mtime $f] } {
vlog -work $work_path +incdir+$src_modelsim_path $f
set last_compile_time 0
} else {
puts "$f is uptodate"
}
}
vsim -t 1ps -L $rtl_work -L work -voptargs="+acc" pck_injector_test
 
set last_compile_time $time_now
 
 
 
set text "###################################################################"
set text "## END OF COMPILATION"
set text "###################################################################"
 
 
#vsim -t ps work.testbench_router
vsim -t ps work.testbench_modelsim
 
run 100 ms
 
#save last compile time
 
set fp [open start_time.txt w]
puts $fp "Start time was [clock seconds]"
close $fp
 
#q
 
 
#####################################################################################
 
add wave *
view structure
view signals
run -all
/modelsim.ini
0,0 → 1,2126
; vsim modelsim.ini file
[Version]
INIVersion = "10.7c"
 
; Copyright 1991-2018 Mentor Graphics Corporation
;
; All Rights Reserved.
;
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
;
 
[Library]
others = $MODEL_TECH/../modelsim.ini
;
; VITAL concerns:
;
; The library ieee contains (among other packages) the packages of the
; VITAL 2000 standard. When a design uses VITAL 2000 exclusively, it should use
; the physical library ieee (recommended), or use the physical library
; vital2000, but not both. The design can use logical library ieee and/or
; vital2000 as long as each of these maps to the same physical library, either
; ieee or vital2000.
;
; A design using the 1995 version of the VITAL packages, whether or not
; it also uses the 2000 version of the VITAL packages, must have logical library
; name ieee mapped to physical library vital1995. (A design cannot use library
; vital1995 directly because some packages in this library use logical name ieee
; when referring to the other packages in the library.) The design source
; should use logical name ieee when referring to any packages there except the
; VITAL 2000 packages. Any VITAL 2000 present in the design must use logical
; name vital2000 (mapped to physical library vital2000) to refer to those
; packages.
; ieee = $MODEL_TECH/../vital1995
;
; For compatiblity with previous releases, logical library name vital2000 maps
; to library vital2000 (a different library than library ieee, containing the
; same packages).
; A design should not reference VITAL from both the ieee library and the
; vital2000 library because the vital packages are effectively different.
; A design that references both the ieee and vital2000 libraries must have
; both logical names ieee and vital2000 mapped to the same library, either of
; these:
; $MODEL_TECH/../ieee
; $MODEL_TECH/../vital2000
;
 
; added mapping for ADMS
 
;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release
;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release
;mvc_lib = $MODEL_TECH/../mvc_lib
 
; Automatically perform logical->physical mapping for physical libraries that
; appear in -L/-Lf options with filesystem path delimiters (e.g. '.' or '/').
; The tail of the filesystem path name is chosen as the logical library name.
; For example, in the command "vopt -L ./path/to/lib1 -o opttop top",
; vopt automatically performs the mapping "lib1 -> ./path/to/lib1".
; See the User Manual for more details.
;
; AutoLibMapping = 0
 
work = /home/alireza/work/git/hca_git/mpsoc_work/simulation/rtl_work
[DefineOptionset]
; Define optionset entries for the various compilers, vmake, and vsim.
; These option sets can be used with the "-optionset <optionsetname>" syntax.
; i.e.
; vlog -optionset COMPILEDEBUG top.sv
; vsim -optionset UVMDEBUG my_top
;
; Following are some useful examples.
 
; define a vsim optionset for uvm debugging
UVMDEBUG = -uvmcontrol=all -msgmode both -displaymsgmode both -classdebug -onfinish stop
 
; define a vopt optionset for debugging
VOPTDEBUG = +acc -debugdb
 
[encryption]
; For vencrypt and vhencrypt.
 
; Controls whether to encrypt whole files by ignoring all protect directives
; (except "viewport" and "interface_viewport") that are present in the input.
; The default is 0, use embedded protect directives to control the encryption.
; Set this to 1 to encrypt whole files by ignoring embedded protect directives.
; wholefile = 0
 
; Sets the data_method to use for the symmetric session key.
; The session key is a symmetric key that is randomly generated for each
; protected region (envelope) and is the heart of all encryption. This is used
; to set the length of the session key to generate and use when encrypting the
; HDL text. Supported values are aes128, aes192, and aes256.
; data_method = aes128
 
; The following 2 are for specifying an IEEE Std. 1735 Version 2 (V2) encryption
; "recipe" comprising an optional common block, at least one tool block (which
; contains the key public key), and the text to be encrypted. The common block
; and any of the tool blocks may contain rights in the form of the "control"
; directive. The text to be encrypted is specified either by setting
; "wholefile" to 1 or by embedding protect "begin" and "end" directives in
; the input HDL files.
 
; Common recipe specification file. This file is optional. Its presence will
; require at least one "toolblock" to be specified.
; Directives such as "author" "author_info" and "data_method",
; as well as the common block license specification, go in this file.
; common = <file name>
 
; Tool block specification recipe(s). Public key file with optional tool block
; file name. May be multiply-defined; at least one tool block is required if
; a recipe is being specified.
; Key file is a file name with no extension (.deprecated or .active will be
; supplied by the encryption tool).
; Rights file name is optional.
; toolblock = <key file name>[,<rights file name>]{:<key file name>[,<rights file name>]}
 
; Location of directory containing recipe files.
; The default location is in the product installation directory.
; keyring = $MODEL_TECH/../keyring
 
; Enable encryption statistics. Specify one or more arguments:
; [all,none,time,cmd,msg,perf,verbose,list]
; Add '-' to disable specific statistics. Default is [cmd,msg].
Stats = cmd,msg
 
[vcom]
; VHDL93 variable selects language version as the default.
; Default is VHDL-2002.
; Value of 0 or 1987 for VHDL-1987.
; Value of 1 or 1993 for VHDL-1993.
; Default or value of 2 or 2002 for VHDL-2002.
; Value of 3 or 2008 for VHDL-2008
; Value of 4 or ams99 for VHDL-AMS-1999
; Value of 5 or ams07 for VHDL-AMS-2007
VHDL93 = 2002
 
; Ignore VHDL-2008 declaration of REAL_VECTOR in package STANDARD. Default is off.
; ignoreStandardRealVector = 1
 
; Show source line containing error. Default is off.
; Show_source = 1
 
; Turn off unbound-component warnings. Default is on.
; Show_Warning1 = 0
 
; Turn off process-without-a-wait-statement warnings. Default is on.
; Show_Warning2 = 0
 
; Turn off null-range warnings. Default is on.
; Show_Warning3 = 0
 
; Turn off no-space-in-time-literal warnings. Default is on.
; Show_Warning4 = 0
 
; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
; Show_Warning5 = 0
 
; Turn off optimization for IEEE std_logic_1164 package. Default is on.
; Optimize_1164 = 0
 
; Enable compiler statistics. Specify one or more arguments:
; [all,none,time,cmd,msg,perf,verbose,list]
; Add '-' to disable specific statistics. Default is [time,cmd,msg].
; Stats = time,cmd,msg
 
; Turn on resolving of ambiguous function overloading in favor of the
; "explicit" function declaration (not the one automatically created by
; the compiler for each type declaration). Default is off.
; The .ini file has Explicit enabled so that std_logic_signed/unsigned
; will match the behavior of synthesis tools.
Explicit = 1
 
; Turn off acceleration of the VITAL packages. Default is to accelerate.
; NoVital = 1
 
; Turn off VITAL compliance checking. Default is checking on.
; NoVitalCheck = 1
 
; Ignore VITAL compliance checking errors. Default is to not ignore.
; IgnoreVitalErrors = 1
 
; Turn off VITAL compliance checking warnings. Default is to show warnings.
; Show_VitalChecksWarnings = 0
 
; Turn off PSL assertion warning messages. Default is to show warnings.
; Show_PslChecksWarnings = 0
 
; Enable parsing of embedded PSL assertions. Default is enabled.
; EmbeddedPsl = 0
 
; Keep silent about case statement static warnings.
; Default is to give a warning.
; NoCaseStaticError = 1
 
; Keep silent about warnings caused by aggregates that are not locally static.
; Default is to give a warning.
; NoOthersStaticError = 1
 
; Treat as errors:
; case statement static warnings
; warnings caused by aggregates that are not locally static
; Overrides NoCaseStaticError, NoOthersStaticError settings.
; PedanticErrors = 1
 
; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1
 
; Turn off "Loading..." messages. Default is messages on.
; Quiet = 1
 
; Turn on some limited synthesis rule compliance checking. Checks only:
; -- signals used (read) by a process must be in the sensitivity list
; CheckSynthesis = 1
 
; Activate optimizations on expressions that do not involve signals,
; waits, or function/procedure/task invocations. Default is off.
; ScalarOpts = 1
 
; Turns on lint-style checking.
; Show_Lint = 1
 
; Require the user to specify a configuration for all bindings,
; and do not generate a compile time default binding for the
; component. This will result in an elaboration error of
; 'component not bound' if the user fails to do so. Avoids the rare
; issue of a false dependency upon the unused default binding.
; RequireConfigForAllDefaultBinding = 1
 
; Perform default binding at compile time.
; Default is to do default binding at load time.
; BindAtCompile = 1;
 
; Inhibit range checking on subscripts of arrays. Range checking on
; scalars defined with subtypes is inhibited by default.
; NoIndexCheck = 1
 
; Inhibit range checks on all (implicit and explicit) assignments to
; scalar objects defined with subtypes.
; NoRangeCheck = 1
 
; Set the prefix to be honored for synthesis/coverage pragma recognition.
; Default is "".
; AddPragmaPrefix = ""
 
; Ignore synthesis and coverage pragmas with this prefix.
; Default is "".
; IgnorePragmaPrefix = ""
 
; Turn on code coverage in VHDL design units. Default is off.
; Coverage = sbceft
 
; Turn off code coverage in VHDL subprograms. Default is on.
; CoverSub = 0
 
; Automatically exclude VHDL case statement OTHERS choice branches.
; This includes OTHERS choices in selected signal assigment statements.
; Default is to not exclude.
; CoverExcludeDefault = 1
 
; Control compiler and VOPT optimizations that are allowed when
; code coverage is on. Refer to the comment for this in the [vlog] area.
; CoverOpt = 3
 
; Turn on or off clkOpt optimization for code coverage. Default is on.
; CoverClkOpt = 1
 
; Turn on or off clkOpt optimization builtins for code coverage. Default is on.
; CoverClkOptBuiltins = 0
 
; Inform code coverage optimizations to respect VHDL 'H' and 'L'
; values on signals in conditions and expressions, and to not automatically
; convert them to '1' and '0'. Default is to not convert.
; CoverRespectHandL = 0
 
; Increase or decrease the maximum number of rows allowed in a UDP table
; implementing a VHDL condition coverage or expression coverage expression.
; More rows leads to a longer compile time, but more expressions covered.
; CoverMaxUDPRows = 192
 
; Increase or decrease the maximum number of input patterns that are present
; in FEC table. This leads to a longer compile time with more expressions
; covered with FEC metric.
; CoverMaxFECRows = 192
 
; Increase or decrease the limit on the size of expressions and conditions
; considered for expression and condition coverages. Higher FecUdpEffort leads
; to higher compile, optimize and simulation time, but more expressions and
; conditions are considered for coverage in the design. FecUdpEffort can
; be set to a number ranging from 1 (low) to 3 (high), defined as:
; 1 - (low) Only small expressions and conditions considered for coverage.
; 2 - (medium) Bigger expressions and conditions considered for coverage.
; 3 - (high) Very large expressions and conditions considered for coverage.
; The default setting is 1 (low).
; FecUdpEffort = 1
 
; Enable or disable Focused Expression Coverage analysis for conditions and
; expressions. Focused Expression Coverage data is provided by default when
; expression and/or condition coverage is active.
; CoverFEC = 0
 
; Enable or disable UDP Coverage analysis for conditions and expressions.
; UDP Coverage data is disabled by default when expression and/or condition
; coverage is active.
; CoverUDP = 1
 
; Enable or disable Rapid Expression Coverage mode for conditions and expressions.
; Disabling this would convert non-masking conditions in FEC tables to matching
; input patterns.
; CoverREC = 1
 
; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions
; for expression/condition coverage.
; NOTE: Enabling this may have a negative impact on simulation performance.
; CoverExpandReductionPrefix = 0
 
; Enable or disable short circuit evaluation of conditions and expressions when
; condition or expression coverage is active. Short circuit evaluation is enabled
; by default.
; CoverShortCircuit = 0
 
; Enable code coverage reporting of code that has been optimized away.
; The default is not to report.
; CoverReportCancelled = 1
 
; Enable deglitching of code coverage in combinatorial, non-clocked, processes.
; Default is no deglitching.
; CoverDeglitchOn = 1
 
; Control the code coverage deglitching period. A period of 0, eliminates delta
; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a
; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps".
; CoverDeglitchPeriod = 0
 
; Use this directory for compiler temporary files instead of "work/_temp"
; CompilerTempDir = /tmp
 
; Set this to cause the compilers to force data to be committed to disk
; when the files are closed.
; SyncCompilerFiles = 1
 
; Add VHDL-AMS declarations to package STANDARD
; Default is not to add
; AmsStandard = 1
 
; Range and length checking will be performed on array indices and discrete
; ranges, and when violations are found within subprograms, errors will be
; reported. Default is to issue warnings for violations, because subprograms
; may not be invoked.
; NoDeferSubpgmCheck = 0
 
; Turn ON detection of FSMs having single bit current state variable.
; FsmSingle = 1
 
; Turn off reset state transitions in FSM.
; FsmResetTrans = 0
 
; Turn ON detection of FSM Implicit Transitions.
; FsmImplicitTrans = 1
 
; Controls whether or not to show immediate assertions with constant expressions
; in GUI/report/UCDB etc. By default, immediate assertions with constant
; expressions are shown in GUI/report/UCDB etc. This does not affect
; evaluation of immediate assertions.
; ShowConstantImmediateAsserts = 0
 
; Controls how VHDL basic identifiers are stored with the design unit.
; Does not make the language case-sensitive, affects only how declarations
; declared with basic identifiers have their names stored and printed
; (in the GUI, examine, etc.).
; Default is to preserve the case as originally depicted in the VHDL source.
; Value of 0 indicates to change all basic identifiers to lower case.
; PreserveCase = 0
 
; For Configuration Declarations, controls the effect that USE clauses have
; on visibility inside the configuration items being configured. If 1
; (the default), then use pre-10.0 behavior. If 0, then for stricter LRM-compliance,
; extend the visibility of objects made visible through USE clauses into nested
; component configurations.
; OldVHDLConfigurationVisibility = 0
 
; Allows VHDL configuration declarations to be in a different library from
; the corresponding configured entity. Default is to not allow this for
; stricter LRM-compliance.
; SeparateConfigLibrary = 1;
 
; Determine how mode OUT subprogram parameters of type array and record are treated.
; If 0 (the default), then only VHDL 2008 will do this initialization.
; If 1, always initialize the mode OUT parameter to its default value.
; If 2, do not initialize the mode OUT out parameter.
; Note that prior to release 10.1, all language versions did not initialize mode
; OUT array and record type parameters, unless overridden here via this mechanism.
; In release 10.1 and later, only files compiled with VHDL 2008 will cause this
; initialization, unless overridden here.
; InitOutCompositeParam = 0
 
; Generate symbols debugging database in only some special cases to save on
; the number of files in the library. For other design-units, this database is
; generated on-demand in vsim.
; Default is to to generate debugging database for all design-units.
; SmartDbgSym = 1
 
; Enable or disable automatic creation of missing libraries.
; Default is 1 (enabled)
; CreateLib = 1
 
[vlog]
; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1
 
; Turn on `protect compiler directive processing.
; Default is to ignore `protect directives.
; Protect = 1
 
; Turn off "Loading..." messages. Default is messages on.
; Quiet = 1
 
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
; Default is off.
; Hazard = 1
 
; Turn on converting regular Verilog identifiers to uppercase. Allows case
; insensitivity for module names. Default is no conversion.
; UpCase = 1
 
; Activate optimizations on expressions that do not involve signals,
; waits, or function/procedure/task invocations. Default is off.
; ScalarOpts = 1
 
; Turns on lint-style checking.
; Show_Lint = 1
 
; Show source line containing error. Default is off.
; Show_source = 1
 
; Turn on bad option warning. Default is off.
; Show_BadOptionWarning = 1
 
; Revert back to IEEE 1364-1995 syntax, default is 0 (off).
; vlog95compat = 1
 
; Turn off PSL warning messages. Default is to show warnings.
; Show_PslChecksWarnings = 0
 
; Enable parsing of embedded PSL assertions. Default is enabled.
; EmbeddedPsl = 0
 
; Enable compiler statistics. Specify one or more arguments:
; [all,none,time,cmd,msg,perf,verbose,list,kb]
; Add '-' to disable specific statistics. Default is [time,cmd,msg].
; Stats = time,cmd,msg
 
; Set the threshold for automatically identifying sparse Verilog memories.
; A memory with total size in bytes equal to or more than the sparse memory
; threshold gets marked as sparse automatically, unless specified otherwise
; in source code or by the +nosparse commandline option of vlog or vopt.
; The default is 1M. (i.e. memories with total size equal
; to or greater than 1Mb are marked as sparse)
; SparseMemThreshold = 1048576
 
; Set the prefix to be honored for synthesis and coverage pragma recognition.
; Default is "".
; AddPragmaPrefix = ""
 
; Ignore synthesis and coverage pragmas with this prefix.
; Default is "".
; IgnorePragmaPrefix = ""
 
; Set the option to treat all files specified in a vlog invocation as a
; single compilation unit. The default value is set to 0 which will treat
; each file as a separate compilation unit as specified in the P1800 draft standard.
; MultiFileCompilationUnit = 1
 
; Turn on code coverage in Verilog design units. Default is off.
; Coverage = sbceft
 
; Automatically exclude Verilog case statement default branches.
; Default is to not automatically exclude defaults.
; CoverExcludeDefault = 1
 
; Increase or decrease the maximum number of rows allowed in a UDP table
; implementing a VHDL condition coverage or expression coverage expression.
; More rows leads to a longer compile time, but more expressions covered.
; CoverMaxUDPRows = 192
 
; Increase or decrease the maximum number of input patterns that are present
; in FEC table. This leads to a longer compile time with more expressions
; covered with FEC metric.
; CoverMaxFECRows = 192
 
; Increase or decrease the limit on the size of expressions and conditions
; considered for expression and condition coverages. Higher FecUdpEffort leads
; to higher compile, optimize and simulation time, but more expressions and
; conditions are considered for coverage in the design. FecUdpEffort can
; be set to a number ranging from 1 (low) to 3 (high), defined as:
; 1 - (low) Only small expressions and conditions considered for coverage.
; 2 - (medium) Bigger expressions and conditions considered for coverage.
; 3 - (high) Very large expressions and conditions considered for coverage.
; The default setting is 1 (low).
; FecUdpEffort = 1
 
; Enable or disable Focused Expression Coverage analysis for conditions and
; expressions. Focused Expression Coverage data is provided by default when
; expression and/or condition coverage is active.
; CoverFEC = 0
 
; Enable or disable UDP Coverage analysis for conditions and expressions.
; UDP Coverage data is disabled by default when expression and/or condition
; coverage is active.
; CoverUDP = 1
 
; Enable or disable Rapid Expression Coverage mode for conditions and expressions.
; Disabling this would convert non-masking conditions in FEC tables to matching
; input patterns.
; CoverREC = 1
 
; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions
; for expression/condition coverage.
; NOTE: Enabling this may have a negative impact on simulation performance.
; CoverExpandReductionPrefix = 0
 
; Enable or disable short circuit evaluation of conditions and expressions when
; condition or expression coverage is active. Short circuit evaluation is enabled
; by default.
; CoverShortCircuit = 0
 
; Enable deglitching of code coverage in combinatorial, non-clocked, processes.
; Default is no deglitching.
; CoverDeglitchOn = 1
 
; Control the code coverage deglitching period. A period of 0, eliminates delta
; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a
; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps".
; CoverDeglitchPeriod = 0
 
; Turn on code coverage in VLOG `celldefine modules, modules containing
; specify blocks, and modules included using vlog -v and -y. Default is off.
; CoverCells = 1
 
; Enable code coverage reporting of code that has been optimized away.
; The default is not to report.
; CoverReportCancelled = 1
 
; Control compiler and VOPT optimizations that are allowed when
; code coverage is on. This is a number from 0 to 5, with the following
; meanings (the default is 3):
; 5 -- All allowable optimizations are on.
; 4 -- Turn off removing unreferenced code.
; 3 -- Turn off process, always block and if statement merging.
; 2 -- Turn off expression optimization, converting primitives
; to continuous assignments, VHDL subprogram inlining.
; and VHDL clkOpt (converting FF's to builtins).
; 1 -- Turn off continuous assignment optimizations and clock suppression.
; 0 -- Turn off Verilog module inlining and VHDL arch inlining.
; HOWEVER, if fsm coverage is turned on, optimizations will be forced to
; level 3, with also turning off converting primitives to continuous assigns.
; CoverOpt = 3
 
; Specify the override for the default value of "cross_num_print_missing"
; option for the Cross in Covergroups. If not specified then LRM default
; value of 0 (zero) is used. This is a compile time option.
; SVCrossNumPrintMissingDefault = 0
 
; Setting following to 1 would cause creation of variables which
; would represent the value of Coverpoint expressions. This is used
; in conjunction with "SVCoverpointExprVariablePrefix" option
; in the modelsim.ini
; EnableSVCoverpointExprVariable = 0
 
; Specify the override for the prefix used in forming the variable names
; which represent the Coverpoint expressions. This is used in conjunction with
; "EnableSVCoverpointExprVariable" option of the modelsim.ini
; The default prefix is "expr".
; The variable name is
; variable name => <prefix>_<coverpoint name>
; SVCoverpointExprVariablePrefix = expr
 
; Override for the default value of the SystemVerilog covergroup,
; coverpoint, and cross option.goal (defined to be 100 in the LRM).
; NOTE: It does not override specific assignments in SystemVerilog
; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal"
; in the [vsim] section can override this value.
; SVCovergroupGoalDefault = 100
 
; Override for the default value of the SystemVerilog covergroup,
; coverpoint, and cross type_option.goal (defined to be 100 in the LRM)
; NOTE: It does not override specific assignments in SystemVerilog
; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal"
; in the [vsim] section can override this value.
; SVCovergroupTypeGoalDefault = 100
 
; Specify the override for the default value of "strobe" option for the
; Covergroup Type. This is a compile time option which forces "strobe" to
; a user specified default value and supersedes SystemVerilog specified
; default value of '0'(zero). NOTE: This can be overriden by a runtime
; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section.
; SVCovergroupStrobeDefault = 0
 
; Specify the override for the default value of "per_instance" option for the
; Covergroup variables. This is a compile time option which forces "per_instance"
; to a user specified default value and supersedes SystemVerilog specified
; default value of '0'(zero).
; SVCovergroupPerInstanceDefault = 0
 
; Specify the override for the default value of "get_inst_coverage" option for the
; Covergroup variables. This is a compile time option which forces
; "get_inst_coverage" to a user specified default value and supersedes
; SystemVerilog specified default value of '0'(zero).
; SVCovergroupGetInstCoverageDefault = 0
 
;
; A space separated list of resource libraries that contain precompiled
; packages. The behavior is identical to using the "-L" switch.
;
; LibrarySearchPath = <path/lib> [<path/lib> ...]
LibrarySearchPath = mtiAvm mtiRnm mtiOvm mtiUvm mtiUPF infact
 
; The behavior is identical to the "-mixedansiports" switch. Default is off.
; MixedAnsiPorts = 1
 
; Enable SystemVerilog 3.1a $typeof() function. Default is off.
; EnableTypeOf = 1
 
; Only allow lower case pragmas. Default is disabled.
; AcceptLowerCasePragmaOnly = 1
 
; Set the maximum depth permitted for a recursive include file nesting.
; IncludeRecursionDepthMax = 5
 
; Turn ON detection of FSMs having single bit current state variable.
; FsmSingle = 1
 
; Turn off reset state transitions in FSM.
; FsmResetTrans = 0
 
; Turn off detections of FSMs having x-assignment.
; FsmXAssign = 0
 
; Turn ON detection of FSM Implicit Transitions.
; FsmImplicitTrans = 1
 
; List of file suffixes which will be read as SystemVerilog. White space
; in extensions can be specified with a back-slash: "\ ". Back-slashes
; can be specified with two consecutive back-slashes: "\\";
; SvFileSuffixes = sv svp svh
 
; This setting is the same as the vlog -sv command line switch.
; Enables SystemVerilog features and keywords when true (1).
; When false (0), the rules of IEEE Std 1364-2001 are followed and
; SystemVerilog keywords are ignored.
; Svlog = 0
 
; Prints attribute placed upon SV packages during package import
; when true (1). The attribute will be ignored when this
; entry is false (0). The attribute name is "package_load_message".
; The value of this attribute is a string literal.
; Default is true (1).
; PrintSVPackageLoadingAttribute = 1
 
; Do not show immediate assertions with constant expressions in
; GUI/reports/UCDB etc. By default immediate assertions with constant
; expressions are shown in GUI/reports/UCDB etc. This does not affect
; evaluation of immediate assertions.
; ShowConstantImmediateAsserts = 0
 
; Controls if untyped parameters that are initialized with values greater
; than 2147483647 are mapped to generics of type INTEGER or ignored.
; If mapped to VHDL Integers, values greater than 2147483647
; are mapped to negative values.
; Default is to map these parameter to generic of type INTEGER
; ForceUnsignedToVHDLInteger = 1
 
; Enable AMS wreal (wired real) extensions. Default is 0.
; WrealType = 1
 
; Controls SystemVerilog Language Extensions. These options enable
; some non-LRM compliant behavior.
; SvExtensions = [+|-]<extension>[,[+|-]<extension>*]
 
; Generate symbols debugging database in only some special cases to save on
; the number of files in the library. For other design-units, this database is
; generated on-demand in vsim.
; Default is to to generate debugging database for all design-units.
; SmartDbgSym = 1
 
; Controls how $unit library entries are named. Valid options are:
; "file" (generate name based on the first file on the command line)
; "du" (generate name based on first design unit following an item
; found in $unit scope)
; CUAutoName = file
 
; Enable or disable automatic creation of missing libraries.
; Default is 1 (enabled)
; CreateLib = 1
 
[sccom]
; Enable use of SCV include files and library. Default is off.
; UseScv = 1
 
; Add C++ compiler options to the sccom command line by using this variable.
; CppOptions = -g
 
; Use custom C++ compiler located at this path rather than the default path.
; The path should point directly at a compiler executable.
; CppPath = /usr/bin/g++
 
; Specify the compiler version from the list of support GNU compilers.
; examples 4.3.3, 4.5.0
; CppInstall = 4.5.0
 
; Enable verbose messages from sccom. Default is off.
; SccomVerbose = 1
 
; sccom logfile. Default is no logfile.
; SccomLogfile = sccom.log
 
; Enable use of SC_MS include files and library. Default is off.
; UseScMs = 1
 
; Use SystemC-2.2 instead of the default SystemC-2.3. Default is off.
; Sc22Mode = 1
 
; Enable compiler statistics. Specify one or more arguments:
; [all,none,time,cmd,msg,perf,verbose,list,kb]
; Add '-' to disable specific statistics. Default is [time,cmd,msg].
; Stats = time,cmd,msg
 
; Enable or disable automatic creation of missing libraries.
; Default is 1 (enabled)
; CreateLib = 1
 
; Enable use of UVMC library. Default is off.
; UseUvmc = 1
 
[vopt]
; Turn on code coverage in vopt. Default is off.
; Coverage = sbceft
 
; Control compiler optimizations that are allowed when
; code coverage is on. Refer to the comment for this in the [vlog] area.
; CoverOpt = 3
 
; Controls set of CoverConstructs that are being considered for Coverage
; Collection.
; Some of Valid options are: default,set1,set2
; Covermode = default
 
; Controls set of HDL cover constructs that would be considered(or not considered)
; for Coverage Collection. (Default corresponds to covermode default).
; Some of Valid options are: "ca", "citf", "cifl", "tcint", "fsmqs".
; Coverconstruct = noca,nocitf,nofsmtf,nofsmds,noctes,nocicl,nocprc,nocfl,nofsmup,nocifl,nocpm,notcint,nocpkg,nocsva
 
; Increase or decrease the maximum number of rows allowed in a UDP table
; implementing a VHDL condition coverage or expression coverage expression.
; More rows leads to a longer compile time, but more expressions covered.
; CoverMaxUDPRows = 192
 
; Increase or decrease the maximum number of input patterns that are present
; in FEC table. This leads to a longer compile time with more expressions
; covered with FEC metric.
; CoverMaxFECRows = 192
 
; Increase or decrease the limit on the size of expressions and conditions
; considered for expression and condition coverages. Higher FecUdpEffort leads
; to higher compile, optimize and simulation time, but more expressions and
; conditions are considered for coverage in the design. FecUdpEffort can
; be set to a number ranging from 1 (low) to 3 (high), defined as:
; 1 - (low) Only small expressions and conditions considered for coverage.
; 2 - (medium) Bigger expressions and conditions considered for coverage.
; 3 - (high) Very large expressions and conditions considered for coverage.
; The default setting is 1 (low).
; FecUdpEffort = 1
 
; Enable code coverage reporting of code that has been optimized away.
; The default is not to report.
; CoverReportCancelled = 1
 
; Enable deglitching of code coverage in combinatorial, non-clocked, processes.
; Default is no deglitching.
; CoverDeglitchOn = 1
 
; Enable compiler statistics. Specify one or more arguments:
; [all,none,time,cmd,msg,perf,verbose,list,kb]
; Add '-' to disable specific statistics. Default is [time,cmd,msg].
; Stats = time,cmd,msg
 
; Control the code coverage deglitching period. A period of 0, eliminates delta
; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a
; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps".
; CoverDeglitchPeriod = 0
 
; Do not show immediate assertions with constant expressions in
; GUI/reports/UCDB etc. By default immediate assertions with constant
; expressions are shown in GUI/reports/UCDB etc. This does not affect
; evaluation of immediate assertions.
; ShowConstantImmediateAsserts = 0
 
; Set the maximum number of iterations permitted for a generate loop.
; Restricting this permits the implementation to recognize infinite
; generate loops.
; GenerateLoopIterationMax = 100000
 
; Set the maximum depth permitted for a recursive generate instantiation.
; Restricting this permits the implementation to recognize infinite
; recursions.
; GenerateRecursionDepthMax = 200
 
; Set the number of processes created during the code generation phase.
; By default a heuristic is used to set this value. This may be set to 0
; to disable this feature completely.
; ParallelJobs = 0
 
; Controls SystemVerilog Language Extensions. These options enable
; some non-LRM compliant behavior.
; SvExtensions = [+|-]<extension>[,[+|-]<extension>*]
 
; Load the specified shared objects with the RTLD_GLOBAL flag.
; This gives global visibility to all symbols in the shared objects,
; meaning that subsequently loaded shared objects can bind to symbols
; in the global shared objects. The list of shared objects should
; be whitespace delimited. This option is not supported on the
; Windows or AIX platforms.
; GlobalSharedObjectList = example1.so example2.so example3.so
 
; Disable SystemVerilog elaboration system task messages
; IgnoreSVAInfo = 1
; IgnoreSVAWarning = 1
; IgnoreSVAError = 1
; IgnoreSVAFatal = 1
 
; Enable or disable automatic creation of missing libraries.
; Default is 1 (enabled)
; CreateLib = 1
 
[vsim]
; vopt flow
; Set to turn on automatic optimization of a design.
; Default is on
VoptFlow = 1
 
; Simulator resolution
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
Resolution = ns
 
; Disable certain code coverage exclusions automatically.
; Assertions and FSM are exluded from the code coverage by default
; Set AutoExclusionsDisable = fsm to enable code coverage for fsm
; Set AutoExclusionsDisable = assertions to enable code coverage for assertions
; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions
; Or specify comma or space separated list
;AutoExclusionsDisable = fsm,assertions
 
; User time unit for run commands
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
; unit specified for Resolution. For example, if Resolution is 100ps,
; then UserTimeUnit defaults to ps.
; Should generally be set to default.
UserTimeUnit = default
 
; Default run length
RunLength = 100
 
; Maximum iterations that can be run without advancing simulation time
IterationLimit = 10000000
 
; Specify libraries to be searched for precompiled modules
; LibrarySearchPath = <path/lib> [<path/lib> ...]
 
; Set XPROP assertion fail limit. Default is 5.
; Any positive integer, -1 for infinity.
; XpropAssertionLimit = 5
 
; Control PSL and Verilog Assume directives during simulation
; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts
; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts
; SimulateAssumeDirectives = 1
 
; Control the simulation of PSL and SVA
; These switches can be overridden by the vsim command line switches:
; -psl, -nopsl, -sva, -nosva.
; Set SimulatePSL = 0 to disable PSL simulation
; Set SimulatePSL = 1 to enable PSL simulation (default)
; SimulatePSL = 1
; Set SimulateSVA = 0 to disable SVA simulation
; Set SimulateSVA = 1 to enable concurrent SVA simulation (default)
; SimulateSVA = 1
 
; Control SVA and VHDL immediate assertion directives during simulation
; Set SimulateImmedAsserts = 0 to disable simulation of immediate asserts
; Set SimulateImmedAsserts = 1 to enable simulation of immediate asserts
; SimulateImmedAsserts = 1
 
; License feature mappings for Verilog and VHDL
; qhsimvh Single language VHDL license
; qhsimvl Single language Verilog license
; msimhdlsim Language neutral license for either Verilog or VHDL
; msimhdlmix Second language only, language neutral license for either
; Verilog or VHDL
;
; Directives to license manager can be set either as single value or as
; space separated multi-values:
; vhdl Immediately checkout and hold a VHDL license (i.e., one of
; qhsimvh, msimhdlsim, or msimhdlmix)
; vlog Immediately checkout and hold a Verilog license (i.e., one of
; qhsimvl, msimhdlsim, or msimhdlmix)
; plus Immediately checkout and hold a VHDL license and a Verilog license
; noqueue Do not wait in the license queue when a license is not available
; viewsim Try for viewer license but accept simulator license(s) instead
; of queuing for viewer license (PE ONLY)
; noviewer Disable checkout of msimviewer license feature (PE ONLY)
; noslvhdl Disable checkout of qhsimvh license feature
; noslvlog Disable checkout of qhsimvl license feature
; nomix Disable checkout of msimhdlmix license feature
; nolnl Disable checkout of msimhdlsim license feature
; mixedonly Disable checkout of qhsimvh and qhsimvl license features
; lnlonly Disable checkout of qhsimvh,qhsimvl, and msimhdlmix license features
;
; Examples (remove ";" comment character to activate licensing directives):
; Single directive:
; License = plus
; Multi-directive (Note: space delimited directives):
; License = noqueue plus
 
; Severity level of a VHDL assertion message or of a SystemVerilog severity system task
; which will cause a running simulation to stop.
; VHDL assertions and SystemVerilog severity system task that occur with the
; given severity or higher will cause a running simulation to stop.
; This value is ignored during elaboration.
; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
BreakOnAssertion = 3
 
; Severity level of a tool message which will cause a running simulation to
; stop. This value is ignored during elaboration. Default is to not break.
; 0 = Note 1 = Warning 2 = Error 3 = Fatal
;BreakOnMessage = 2
 
; The class debug feature enables more visibility and tracking of class instances
; during simulation. By default this feature is disabled (0). To enable this
; feature set ClassDebug to 1.
; ClassDebug = 1
 
; Message Format conversion specifications:
; %S - Severity Level of message/assertion
; %R - Text of message
; %T - Time of message
; %D - Delta value (iteration number) of Time
; %K - Kind of path: Instance/Region/Signal/Process/Foreign Process/Unknown/Protected
; %i - Instance/Region/Signal pathname with Process name (if available)
; %I - shorthand for one of these:
; " %K: %i"
; " %K: %i File: %F" (when path is not Process or Signal)
; except that the %i in this case does not report the Process name
; %O - Process name
; %P - Instance/Region path without leaf process
; %F - File name
; %L - Line number; if assertion message, then line number of assertion or, if
; assertion is in a subprogram, line from which the call is made
; %u - Design unit name in form library.primary
; %U - Design unit name in form library.primary(secondary)
; %% - The '%' character itself
;
; If specific format for Severity Level is defined, use that format.
; Else, for a message that occurs during elaboration:
; -- Failure/Fatal message in VHDL region that is not a Process, and in
; certain non-VHDL regions, uses MessageFormatBreakLine;
; -- Failure/Fatal message otherwise uses MessageFormatBreak;
; -- Note/Warning/Error message uses MessageFormat.
; Else, for a message that occurs during runtime and triggers a breakpoint because
; of the BreakOnAssertion setting:
; -- if in a VHDL region that is not a Process, uses MessageFormatBreakLine;
; -- otherwise uses MessageFormatBreak.
; Else (a runtime message that does not trigger a breakpoint) uses MessageFormat.
;
; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n"
; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n"
; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n"
; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
 
; Error File - alternate file for storing error messages
; ErrorFile = error.log
 
; Simulation Breakpoint messages
; This flag controls the display of function names when reporting the location
; where the simulator stops because of a breakpoint or fatal error.
; Example with function name: # Break in Process ctr at counter.vhd line 44
; Example without function name: # Break at counter.vhd line 44
; Default value is 1.
ShowFunctions = 1
 
; Default radix for all windows and commands.
; Radix may be one of: symbolic, ascii, binary, octal, decimal, hex, unsigned
; Flags may be one of: enumnumeric, showbase, wreal
DefaultRadix = hexadecimal
DefaultRadixFlags = showbase
; Set to 1 for make the signal_force VHDL and Verilog functions use the
; default radix when processing the force value. Prior to 10.2 signal_force
; used the default radix, now it always uses symbolic unless value explicitly indicates base
;SignalForceFunctionUseDefaultRadix = 0
 
; VSIM Startup command
; Startup = do startup.do
 
; VSIM Shutdown file
; Filename to save u/i formats and configurations.
; ShutdownFile = restart.do
; To explicitly disable auto save:
; ShutdownFile = --disable-auto-save
 
; Run simulator in batch mode as if -batch were specified on the command line if none of -c, -gui, or -i specified.
; Simulator runs in interactive mode as if -i were specified if this option is 0. Default is 0.
; BatchMode = 1
 
; File for saving command transcript when -batch option used
; This option is ignored when -c, -gui, or -i options are used or if BatchMode above is zero
; default is unset so command transcript only goes to stdout for better performance
; BatchTranscriptFile = transcript
 
; File for saving command transcript, this option is ignored when -batch option is used
TranscriptFile = transcript
 
; Transcript file long line wrapping mode(s)
; mode == 0 :: no wrapping, line recorded as is
; mode == 1 :: wrap at first whitespace after WSColumn
; or at Column.
; mode == 2 :: wrap as above, but add continuation
; character ('\') at end of each wrapped line
;
; WrapMode = 0
; WrapColumn = 30000
; WrapWSColumn = 27000
 
; File for saving command history
; CommandHistory = cmdhist.log
 
; Specify whether paths in simulator commands should be described
; in VHDL or Verilog format.
; For VHDL, PathSeparator = /
; For Verilog, PathSeparator = .
; Must not be the same character as DatasetSeparator.
PathSeparator = /
 
; Specify the dataset separator for fully rooted contexts.
; The default is ':'. For example: sim:/top
; Must not be the same character as PathSeparator.
DatasetSeparator = :
 
; Specify a unique path separator for the Signal Spy set of functions.
; The default will be to use the PathSeparator variable.
; Must not be the same character as DatasetSeparator.
; SignalSpyPathSeparator = /
 
; Used to control parsing of HDL identifiers input to the tool.
; This includes CLI commands, vsim/vopt/vlog/vcom options,
; string arguments to FLI/VPI/DPI calls, etc.
; If set to 1, accept either Verilog escaped Id syntax or
; VHDL extended id syntax, regardless of source language.
; If set to 0, the syntax of the source language must be used.
; Each identifier in a hierarchical name may need different syntax,
; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or
; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom"
; GenerousIdentifierParsing = 1
 
; Disable VHDL assertion messages
; IgnoreNote = 1
; IgnoreWarning = 1
; IgnoreError = 1
; IgnoreFailure = 1
 
; Disable SystemVerilog assertion messages
; IgnoreSVAInfo = 1
; IgnoreSVAWarning = 1
; IgnoreSVAError = 1
; IgnoreSVAFatal = 1
 
; Do not print any additional information from Severity System tasks.
; Only the message provided by the user is printed along with severity
; information.
; SVAPrintOnlyUserMessage = 1;
 
; Default force kind. May be freeze, drive, deposit, or default
; or in other terms, fixed, wired, or charged.
; A value of "default" will use the signal kind to determine the
; force kind, drive for resolved signals, freeze for unresolved signals
; DefaultForceKind = freeze
 
; Control the iteration of events when a VHDL signal is forced to a value
; This flag can be set to honour the signal update event in next iteration,
; the default is to update and propagate in the same iteration.
; ForceSigNextIter = 1
 
; Enable simulation statistics. Specify one or more arguments:
; [all,none,time,cmd,msg,perf,verbose,list,kb,eor]
; Add '-' to disable specific statistics. Default is [time,cmd,msg].
; Stats = time,cmd,msg
 
; If zero, open files when elaborated; otherwise, open files on
; first read or write. Default is 0.
; DelayFileOpen = 1
 
; Control VHDL files opened for write.
; 0 = Buffered, 1 = Unbuffered
UnbufferedOutput = 0
 
; Control the number of VHDL files open concurrently.
; This number should always be less than the current ulimit
; setting for max file descriptors.
; 0 = unlimited
ConcurrentFileLimit = 40
 
; If nonzero, close files as soon as there is either an explicit call to
; file_close, or when the file variable's scope is closed. When zero, a
; file opened in append mode is not closed in case it is immediately
; reopened in append mode; otherwise, the file will be closed at the
; point it is reopened.
; AppendClose = 1
 
; Control the number of hierarchical regions displayed as
; part of a signal name shown in the Wave window.
; A value of zero tells VSIM to display the full name.
; The default is 0.
; WaveSignalNameWidth = 0
 
; Turn off warnings when changing VHDL constants and generics
; Default is 1 to generate warning messages
; WarnConstantChange = 0
 
; Turn off warnings from accelerated versions of the std_logic_arith,
; std_logic_unsigned, and std_logic_signed packages.
; StdArithNoWarnings = 1
 
; Turn off warnings from accelerated versions of the IEEE numeric_std
; and numeric_bit packages.
; NumericStdNoWarnings = 1
 
; Use old-style (pre-6.6) VHDL FOR GENERATE statement iteration names
; in the design hierarchy.
; This style is controlled by the value of the GenerateFormat
; value described next. Default is to use new-style names, which
; comprise the generate statement label, '(', the value of the generate
; parameter, and a closing ')'.
; Set this to 1 to use old-style names.
; OldVhdlForGenNames = 1
 
; Control the format of the old-style VHDL FOR generate statement region
; name for each iteration. Do not quote the value.
; The format string here must contain the conversion codes %s and %d,
; in that order, and no other conversion codes. The %s represents
; the generate statement label; the %d represents the generate parameter value
; at a particular iteration (this is the position number if the generate parameter
; is of an enumeration type). Embedded whitespace is allowed (but discouraged);
; leading and trailing whitespace is ignored.
; Application of the format must result in a unique region name over all
; loop iterations for a particular immediately enclosing scope so that name
; lookup can function properly. The default is %s__%d.
; GenerateFormat = %s__%d
 
; Enable more efficient logging of VHDL Variables.
; Logging VHDL variables without this enabled, while possible, is very
; inefficient. Enabling this will provide a more efficient logging methodology
; at the expense of more memory usage. By default this feature is disabled (0).
; To enabled this feature, set this variable to 1.
; VhdlVariableLogging = 1
 
; Enable logging of VHDL access type variables and their designated objects.
; This setting will allow both variables of an access type ("access variables")
; and their designated objects ("access objects") to be logged. Logging a
; variable of an access type will automatically also cause the designated
; object(s) of that variable to be logged as the simulation progresses.
; Further, enabling this allows access objects to be logged by name. By default
; this feature is disabled (0). To enable this feature, set this variable to 1.
; Enabling this will automatically enable the VhdlVariableLogging feature also.
; AccessObjDebug = 1
 
; Make each VHDL package in a PDU has its own separate copy of the package instead
; of sharing the package between PDUs. The default is to share packages.
; To ensure that each PDU has its own set of packages, set this variable to 1.
; VhdlSeparatePduPackage = 1
 
; Specify whether checkpoint files should be compressed.
; The default is 1 (compressed).
; CheckpointCompressMode = 0
 
; Specify gcc compiler used in the compilation of automatically generated DPI exportwrapper.
; Use custom gcc compiler located at this path rather than the default path.
; The path should point directly at a compiler executable.
; DpiCppPath = <your-gcc-installation>/bin/gcc
;
; Specify the compiler version from the list of support GNU compilers.
; examples 4.5.0, 4.7.4
; DpiCppInstall = 4.7.4
 
; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls.
; The term "out-of-the-blue" refers to SystemVerilog export function calls
; made from C functions that don't have the proper context setup
; (as is the case when running under "DPI-C" import functions).
; When this is enabled, one can call a DPI export function
; (but not task) from any C code.
; the setting of this variable can be one of the following values:
; 0 : dpioutoftheblue call is disabled (default)
; 1 : dpioutoftheblue call is enabled, but export call debug support is not available.
; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available.
; DpiOutOfTheBlue = 1
 
; Specify whether continuous assignments are run before other normal priority
; processes scheduled in the same iteration. This event ordering minimizes race
; differences between optimized and non-optimized designs, and is the default
; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set
; ImmediateContinuousAssign to 0.
; The default is 1 (enabled).
; ImmediateContinuousAssign = 0
 
; List of dynamically loaded objects for Verilog PLI applications
; Veriuser = veriuser.sl
 
; Which default VPI object model should the tool conform to?
; The 1364 modes are Verilog-only, for backwards compatibility with older
; libraries, and SystemVerilog objects are not available in these modes.
;
; In the absence of a user-specified default, the tool default is the
; latest available LRM behavior.
; Options for PliCompatDefault are:
; VPI_COMPATIBILITY_VERSION_1364v1995
; VPI_COMPATIBILITY_VERSION_1364v2001
; VPI_COMPATIBILITY_VERSION_1364v2005
; VPI_COMPATIBILITY_VERSION_1800v2005
; VPI_COMPATIBILITY_VERSION_1800v2008
;
; Synonyms for each string are also recognized:
; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995)
; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001)
; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005)
; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005)
; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008)
 
 
; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005
 
; Specify whether the Verilog system task $fopen or vpi_mcd_open()
; will create directories that do not exist when opening the file
; in "a" or "w" mode.
; The default is 0 (do not create non-existent directories)
; CreateDirForFileAccess = 1
 
; Specify default options for the restart command. Options can be one
; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions
; DefaultRestartOptions = -force
 
 
; Specify default UVM-aware debug options if the vsim -uvmcontrol switch is not used.
; Valid options include: all, none, verbose, disable, struct, reseed, msglog, trlog, certe.
; Options can be enabled by just adding the name, or disabled by prefixing the option with a "-".
; The list of options must be delimited by commas, without spaces or tabs.
;
; Some examples
; To turn on all available UVM-aware debug features:
; UVMControl = all
; To turn on the struct window, mesage logging, and transaction logging:
; UVMControl = struct,msglog,trlog
; To turn on all options except certe:
; UVMControl = all,-certe
; To completely disable all UVM-aware debug functionality:
; UVMControl = disable
 
; Specify the WildcardFilter setting.
; A space separated list of object types to be excluded when performing
; wildcard matches with log, wave, etc commands. The default value for this variable is:
; "Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile"
; See "Using the WildcardFilter Preference Variable" in the documentation for
; details on how to use this variable and for descriptions of the filter types.
WildcardFilter = Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile
 
; Specify the WildcardSizeThreshold setting.
; This integer setting specifies the size at which objects will be excluded when
; performing wildcard matches with log, wave, etc commands. Objects of size equal
; to or greater than the WildcardSizeThreshold will be filtered out from the wildcard
; matches. The size is a simple calculation of number of bits or items in the object.
; The default value is 8k (8192). Setting this value to 0 will disable the checking
; of object size against this threshold and allow all objects of any size to be logged.
WildcardSizeThreshold = 8192
 
; Specify whether warning messages are output when objects are filtered out due to the
; WildcardSizeThreshold. The default is 0 (no messages generated).
WildcardSizeThresholdVerbose = 0
 
; Turn on (1) or off (0) WLF file compression.
; The default is 1 (compress WLF file).
; WLFCompress = 0
 
; Specify whether to save all design hierarchy (1) in the WLF file
; or only regions containing logged signals (0).
; The default is 0 (save only regions with logged signals).
; WLFSaveAllRegions = 1
 
; WLF file time limit. Limit WLF file by time, as closely as possible,
; to the specified amount of simulation time. When the limit is exceeded
; the earliest times get truncated from the file.
; If both time and size limits are specified the most restrictive is used.
; UserTimeUnits are used if time units are not specified.
; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
; WLFTimeLimit = 0
 
; WLF file size limit. Limit WLF file size, as closely as possible,
; to the specified number of megabytes. If both time and size limits
; are specified then the most restrictive is used.
; The default is 0 (no limit).
; WLFSizeLimit = 1000
 
; Specify whether or not a WLF file should be deleted when the
; simulation ends. A value of 1 will cause the WLF file to be deleted.
; The default is 0 (do not delete WLF file when simulation ends).
; WLFDeleteOnQuit = 1
 
; Specify whether or not a WLF file should be optimized during
; simulation. If set to 0, the WLF file will not be optimized.
; The default is 1, optimize the WLF file.
; WLFOptimize = 0
 
; Specify the name of the WLF file.
; The default is vsim.wlf
; WLFFilename = vsim.wlf
 
; Specify whether to lock the WLF file.
; Locking the file prevents other invocations of ModelSim/Questa tools from
; inadvertently overwriting the WLF file.
; The default is 1, lock the WLF file.
; WLFFileLock = 0
 
; Specify the update interval for the WLF file in live simulation.
; The interval is given in seconds.
; The value is the smallest interval between WLF file updates. The WLF file
; will be flushed (updated) after (at least) the interval has elapsed, ensuring
; that the data is correct when viewed from a separate viewer.
; A value of 0 means that no updating will occur.
; The default value is 10 seconds.
; WLFUpdateInterval = 10
 
; Specify the WLF cache size limit for WLF files.
; The value is given in megabytes. A value of 0 turns off the cache.
; On non-Windows platforms the default WLFCacheSize setting is 2000 (megabytes).
; On Windows, the default value is 1000 (megabytes) to help to avoid filling
; process memory.
; WLFSimCacheSize allows a different cache size to be set for a live simulation
; WLF file, independent of post-simulation WLF file viewing. If WLFSimCacheSize
; is not set, it defaults to the WLFCacheSize value.
; WLFCacheSize = 2000
; WLFSimCacheSize = 500
 
; Specify the WLF file event collapse mode.
; 0 = Preserve all events and event order. (same as -wlfnocollapse)
; 1 = Only record values of logged objects at the end of a simulator iteration.
; (same as -wlfcollapsedelta)
; 2 = Only record values of logged objects at the end of a simulator time step.
; (same as -wlfcollapsetime)
; The default is 1.
; WLFCollapseMode = 0
 
; Specify whether WLF file logging can use threads on multi-processor machines.
; If 0, no threads will be used; if 1, threads will be used if the system has
; more than one processor.
; WLFUseThreads = 1
 
; Specify the size of objects that will trigger "large object" messages
; at log/wave/list time. The size calculation of the object is the same as that
; used by the WildcardSizeThreshold. The default LargeObjectSize size is 500,000.
; Setting LargeObjectSize to 0 will disable these messages.
; LargeObjectSize = 500000
 
; Specify the depth of stack frames returned by $stacktrace([level]).
; This depth will be picked up when the optional 'level' argument
; is not specified or its value is not a positive integer.
; StackTraceDepth = 100
 
; Turn on/off undebuggable SystemC type warnings. Default is on.
; ShowUndebuggableScTypeWarning = 0
 
; Turn on/off unassociated SystemC name warnings. Default is off.
; ShowUnassociatedScNameWarning = 1
 
; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off.
; ScShowIeeeDeprecationWarnings = 1
 
; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off.
; ScEnableScSignalWriteCheck = 1
 
; Set SystemC default time unit.
; Set to fs, ps, ns, us, ms, or sec with optional
; prefix of 1, 10, or 100. The default is 1 ns.
; The ScTimeUnit value is honored if it is coarser than Resolution.
; If ScTimeUnit is finer than Resolution, it is set to the value
; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns,
; then the default time unit will be 1 ns. However if Resolution
; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns.
ScTimeUnit = ns
 
; Set SystemC sc_main stack size. The stack size is set as an integer
; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or
; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends
; on the amount of data on the sc_main() stack and the memory required
; to succesfully execute the longest function call chain of sc_main().
ScMainStackSize = 10 Mb
 
; Set SystemC thread stack size. The stack size is set as an integer
; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or
; Gb(Giga-byte). The stack size for sc_thread depends
; on the amount of data on the sc_thread stack and the memory required
; to succesfully execute the thread.
; ScStackSize = 1 Mb
 
; Turn on/off execution of remainder of sc_main upon quitting the current
; simulation session. If the cumulative length of sc_main() in terms of
; simulation time units is less than the length of the current simulation
; run upon quit or restart, sc_main() will be in the middle of execution.
; This switch gives the option to execute the remainder of sc_main upon
; quitting simulation. The drawback of not running sc_main till the end
; is memory leaks for objects created by sc_main. If on, the remainder of
; sc_main will be executed ignoring all delays. This may cause the simulator
; to crash if the code in sc_main is dependent on some simulation state.
; Default is on.
ScMainFinishOnQuit = 1
 
; Enable calling of the DPI export taks/functions from the
; SystemC start_of_simulation() callback.
; The default is off.
; EnableDpiSosCb = 1
 
 
; Set the SCV relationship name that will be used to identify phase
; relations. If the name given to a transactor relation matches this
; name, the transactions involved will be treated as phase transactions
ScvPhaseRelationName = mti_phase
 
; Customize the vsim kernel shutdown behavior at the end of the simulation.
; Some common causes of the end of simulation are $finish (implicit or explicit),
; sc_stop(), tf_dofinish(), and assertion failures.
; This should be set to "ask", "exit", or "stop". The default is "ask".
; "ask" -- In batch mode, the vsim kernel will abruptly exit.
; In GUI mode, a dialog box will pop up and ask for user confirmation
; whether or not to quit the simulation.
; "stop" -- Cause the simulation to stay loaded in memory. This can make some
; post-simulation tasks easier.
; "exit" -- The simulation will abruptly exit without asking for any confirmation.
; "final" -- Run SystemVerilog final blocks then behave as "stop".
; Note: This variable can be overridden with the vsim "-onfinish" command line switch.
OnFinish = ask
 
; Print pending deferred assertion messages.
; Deferred assertion messages may be scheduled after the $finish in the same
; time step. Deferred assertions scheduled to print after the $finish are
; printed before exiting with severity level NOTE since it's not known whether
; the assertion is still valid due to being printed in the active region
; instead of the reactive region where they are normally printed.
; OnFinishPendingAssert = 1;
 
; Print "simstats" result. Default is 0.
; 0 == do not print simstats
; 1 == print at end of simulation
; 2 == print at end of each run command and end of simulation
; PrintSimStats = 1
 
; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages
; AssertFile = assert.log
 
; Enable assertion counts. Default is off.
; AssertionCounts = 1
 
; Run simulator in assertion debug mode. Default is off.
; AssertionDebug = 1
 
; Turn on/off PSL/SVA/VHDL assertion enable. Default is on.
; AssertionEnable = 0
 
; Set PSL/SVA/VHDL concurrent assertion fail limit. Default is -1.
; Any positive integer, -1 for infinity.
; AssertionLimit = 1
 
; Turn on/off concurrent assertion pass log. Default is off.
; Assertion pass logging is only enabled when assertion is browseable
; and assertion debug is enabled.
; AssertionPassLog = 1
 
; Turn on/off PSL concurrent assertion fail log. Default is on.
; The flag does not affect SVA
; AssertionFailLog = 0
 
; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on.
; AssertionFailLocalVarLog = 0
 
; Set action type for PSL/SVA concurrent assertion fail action. Default is continue.
; 0 = Continue 1 = Break 2 = Exit
; AssertionFailAction = 1
 
; Enable the active thread monitor in the waveform display when assertion debug is enabled.
; AssertionActiveThreadMonitor = 1
 
; Control how many waveform rows will be used for displaying the active threads. Default is 5.
; AssertionActiveThreadMonitorLimit = 5
 
; Assertion thread limit after which assertion would be killed/switched off.
; The default is -1 (unlimited). If the number of threads for an assertion go
; beyond this limit, the assertion would be either switched off or killed. This
; limit applies to only assert directives.
;AssertionThreadLimit = -1
 
; Action to be taken once the assertion thread limit is reached. Default
; is kill. It can have a value of off or kill. In case of kill, all the existing
; threads are terminated and no new attempts are started. In case of off, the
; existing attempts keep on evaluating but no new attempts are started. This
; variable applies to only assert directives.
;AssertionThreadLimitAction = kill
 
; Cover thread limit after which cover would be killed/switched off.
; The default is -1 (unlimited). If the number of threads for a cover go
; beyond this limit, the cover would be either switched off or killed. This
; limit applies to only cover directives.
;CoverThreadLimit = -1
 
; Action to be taken once the cover thread limit is reached. Default
; is kill. It can have a value of off or kill. In case of kill, all the existing
; threads are terminated and no new attempts are started. In case of off, the
; existing attempts keep on evaluating but no new attempts are started. This
; variable applies to only cover directives.
;CoverThreadLimitAction = kill
 
 
; By default immediate assertions do not participate in Assertion Coverage calculations
; unless they are executed. This switch causes all immediate assertions in the design
; to participate in Assertion Coverage calculations, whether attempted or not.
; UnattemptedImmediateAssertions = 0
 
; By default immediate covers participate in Coverage calculations
; whether they are attempted or not. This switch causes all unattempted
; immediate covers in the design to stop participating in Coverage
; calculations.
; UnattemptedImmediateCovers = 0
 
; By default pass action block is not executed for assertions on vacuous
; success. The following variable is provided to enable execution of
; pass action block on vacuous success. The following variable is only effective
; if the user does not disable pass action block execution by using either
; system tasks or CLI. Also there is a performance penalty for enabling
; the following variable.
;AssertionEnableVacuousPassActionBlock = 1
 
; As per strict 1850-2005 PSL LRM, an always property can either pass
; or fail. However, by default, Questa reports multiple passes and
; multiple fails on top always/never property (always/never operator
; is the top operator under Verification Directive). The reason
; being that Questa reports passes and fails on per attempt of the
; top always/never property. Use the following flag to instruct
; Questa to strictly follow LRM. With this flag, all assert/never
; directives will start an attempt once at start of simulation.
; The attempt can either fail, match or match vacuously.
; For e.g. if always is the top operator under assert, the always will
; keep on checking the property at every clock. If the property under
; always fails, the directive will be considered failed and no more
; checking will be done for that directive. A top always property,
; if it does not fail, will show a pass at end of simulation.
; The default value is '0' (i.e. zero is off). For example:
; PslOneAttempt = 1
 
; Specify the number of clock ticks to represent infinite clock ticks.
; This affects eventually!, until! and until_!. If at End of Simulation
; (EOS) an active strong-property has not clocked this number of
; clock ticks then neither pass or fail (vacuous match) is returned
; else respective fail/pass is returned. The default value is '0' (zero)
; which effectively does not check for clock tick condition. For example:
; PslInfinityThreshold = 5000
 
; Control how many thread start times will be preserved for ATV viewing for a given assertion
; instance. Default is -1 (ALL).
; ATVStartTimeKeepCount = -1
 
; Turn on/off code coverage
; CodeCoverage = 0
 
; This option applies to condition and expression coverage UDP tables. It
; has no effect unless UDP is enabled for coverage with vcom/vlog/vopt -coverudp.
; If this option is used and a match occurs in more than one row in the UDP table,
; none of the counts for all matching rows is incremented. By default, counts are
; incremented for all matching rows.
; CoverCountAll = 1
 
; Turn off automatic inclusion of VHDL integers in toggle coverage. Default
; is to include them.
; ToggleNoIntegers = 1
 
; Set the maximum number of values that are collected for toggle coverage of
; VHDL integers. Default is 100;
; ToggleMaxIntValues = 100
 
; Set the maximum number of values that are collected for toggle coverage of
; Verilog real. Default is 100;
; ToggleMaxRealValues = 100
 
; Turn on automatic inclusion of Verilog integers in toggle coverage, except
; for enumeration types. Default is to include them.
; ToggleVlogIntegers = 0
 
; Turn on automatic inclusion of Verilog real type in toggle coverage, except
; for shortreal types. Default is to not include them.
; ToggleVlogReal = 1
 
; Turn on automatic inclusion of Verilog fixed-size unpacked arrays, VHDL multi-d arrays
; and VHDL arrays-of-arrays in toggle coverage.
; Default is to not include them.
; ToggleFixedSizeArray = 1
 
; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays,
; VHDL multi-d arrays and VHDL arrays-of-arrays that are included for toggle coverage.
; This leads to a longer simulation time with bigger arrays covered with toggle coverage.
; Default is 1024.
; ToggleMaxFixedSizeArray = 1024
 
; Treat Verilog multi-dimensional packed vectors and packed structures as equivalently sized
; one-dimensional packed vectors for toggle coverage. Default is 0.
; TogglePackedAsVec = 0
 
; Treat Verilog enumerated types as equivalently sized one-dimensional packed vectors for
; toggle coverage. Default is 0.
; ToggleVlogEnumBits = 0
 
; Turn off automatic inclusion of VHDL records in toggle coverage.
; Default is to include them.
; ToggleVHDLRecords = 0
 
; Limit the widths of registers automatically tracked for toggle coverage. Default is 128.
; For unlimited width, set to 0.
; ToggleWidthLimit = 128
 
; Limit the counts that are tracked for toggle coverage. When all edges for a bit have
; reached this count, further activity on the bit is ignored. Default is 1.
; For unlimited counts, set to 0.
; ToggleCountLimit = 1
 
; Change the mode of extended toggle coverage. Default is 3. Valid modes are 1, 2 and 3.
; Following is the toggle coverage calculation criteria based on extended toggle mode:
; Mode 1: 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z').
; Mode 2: 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'.
; Mode 3: 0L->1H & 1H->0L & all 'Z' transitions.
; ExtendedToggleMode = 3
 
; Enable toggle statistics collection only for ports. Default is 0.
; TogglePortsOnly = 1
 
; Limit the counts that are tracked for Focussed Expression Coverage. When a bin has
; reached this count, further tracking of the input patterns linked to it is ignored.
; Default is 1. For unlimited counts, set to 0.
; NOTE: Changing this value from its default value may affect simulation performance.
; FecCountLimit = 1
 
; Limit the counts that are tracked for UDP Coverage. When a bin has
; reached this count, further tracking of the input patterns linked to it is ignored.
; Default is 1. For unlimited counts, set to 0.
; NOTE: Changing this value from its default value may affect simulation performance.
; UdpCountLimit = 1
 
; Control toggle coverage deglitching period. A period of 0, eliminates delta
; cycle glitches. This is the default. The value of ToggleDeglitchPeriod needs to be either
; 0 or a time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps".
; ToggleDeglitchPeriod = 10.0ps
 
; Turn on/off all PSL/SVA cover directive enables. Default is on.
; CoverEnable = 0
 
; Turn on/off PSL/SVA cover log. Default is off "0".
; CoverLog = 1
 
; Set "at_least" value for all PSL/SVA cover directives. Default is 1.
; CoverAtLeast = 2
 
; Set "limit" value for all PSL/SVA cover directives. Default is -1.
; Any positive integer, -1 for infinity.
; CoverLimit = 1
 
; Specify the coverage database filename.
; Default is "" (i.e. database is NOT automatically saved on close).
; UCDBFilename = vsim.ucdb
 
; Specify the maximum limit for the number of Cross (bin) products reported
; in XML and UCDB report against a Cross. A warning is issued if the limit
; is crossed. Default is zero. vsim switch -cvgmaxrptrhscross can override this
; setting.
; MaxReportRhsSVCrossProducts = 1000
 
; Specify the override for the "auto_bin_max" option for the Covergroups.
; If not specified then value from Covergroup "option" is used.
; SVCoverpointAutoBinMax = 64
 
; Specify the override for the value of "cross_num_print_missing"
; option for the Cross in Covergroups. If not specified then value
; specified in the "option.cross_num_print_missing" is used. This
; is a runtime option. NOTE: This overrides any "cross_num_print_missing"
; value specified by user in source file and any SVCrossNumPrintMissingDefault
; specified in modelsim.ini.
; SVCrossNumPrintMissing = 0
 
; Specify whether to use the value of "cross_num_print_missing"
; option in report and GUI for the Cross in Covergroups. If not specified then
; cross_num_print_missing is ignored for creating reports and displaying
; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing".
; UseSVCrossNumPrintMissing = 0
 
; Specify the threshold of Coverpoint wildcard bin value range size, above which
; a warning will be triggered. The default is 4K -- 12 wildcard bits.
; SVCoverpointWildCardBinValueSizeWarn = 4096
 
; Specify the override for the value of "strobe" option for the
; Covergroup Type. If not specified then value in "type_option.strobe"
; will be used. This is runtime option which forces "strobe" to
; user specified value and supersedes user specified values in the
; SystemVerilog Code. NOTE: This also overrides the compile time
; default value override specified using "SVCovergroupStrobeDefault"
; SVCovergroupStrobe = 0
 
; Override for explicit assignments in source code to "option.goal" of
; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
; default value of "option.goal" (defined to be 100 in the SystemVerilog
; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault".
; SVCovergroupGoal = 100
 
; Override for explicit assignments in source code to "type_option.goal" of
; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
; default value of "type_option.goal" (defined to be 100 in the SystemVerilog
; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault".
; SVCovergroupTypeGoal = 100
 
; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage()
; builtin functions, and report. This setting changes the default values of
; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3
; behavior if explicit assignments are not made on option.get_inst_coverage and
; type_option.merge_instances by the user. There are two vsim command line
; options, -cvg63 and -nocvg63 to override this setting from vsim command line.
; The default value of this variable from release 6.6 onwards is 0. This default
; drives compliance with the clarified behavior in the IEEE 1800-2009 standard.
; SVCovergroup63Compatibility = 0
 
; Enforce the default behavior of covergroup get_coverage() builtin function, GUI
; and report. This variable sets the default value of type_option.merge_instances.
; There are two vsim command line options, -cvgmergeinstances and
; -nocvgmergeinstances to override this setting from vsim command line.
; The default value of this variable, -1 (don't care), allows the tool to determine
; the effective value, based on factors related to capacity and optimization.
; The type_option.merge_instances appears in the GUI and coverage reports as either
; auto(1) or auto(0), depending on whether the effective value was determined to
; be a 1 or a 0.
; SVCovergroupMergeInstancesDefault = -1
 
; Enable or disable generation of more detailed information about the sampling
; of covergroup, cross, and coverpoints. It provides the details of the number
; of times the covergroup instance and type were sampled, as well as details
; about why covergroup, cross and coverpoint were not covered. A non-zero value
; is to enable this feature. 0 is to disable this feature. Default is 0
; SVCovergroupSampleInfo = 0
 
; Specify the maximum number of Coverpoint bins in whole design for
; all Covergroups.
; MaxSVCoverpointBinsDesign = 2147483648
 
; Specify maximum number of Coverpoint bins in any instance of a Covergroup, default is 2^10 bins
; MaxSVCoverpointBinsInst = 1048576
 
; Specify the maximum number of Cross bins in whole design for
; all Covergroups.
; MaxSVCrossBinsDesign = 2147483648
 
; Specify maximum number of Cross bins in any instance of a Covergroup, default is 2^16 bins
; MaxSVCrossBinsInst = 67108864
 
; Specify whether vsim will collect the coverage data of zero-weight coverage items or not.
; By default, this variable is set 0, in which case option.no_collect setting will take effect.
; If this variable is set to 1, all zero-weight coverage items will not be saved.
; Note that the usage of vsim switch -cvgzwnocollect, if present, will override the setting
; of this variable.
; CvgZWNoCollect = 1
 
; Specify a space delimited list of double quoted TCL style
; regular expressions which will be matched against the text of all messages.
; If any regular expression is found to be contained within any message, the
; status for that message will not be propagated to the UCDB TESTSTATUS.
; If no match is detected, then the status will be propagated to the
; UCDB TESTSTATUS. More than one such regular expression text is allowed,
; and each message text is compared for each regular expression in the list.
; UCDBTestStatusMessageFilter = "Done with Test Bench" "Ignore .* message"
 
; Set weight for all PSL/SVA cover directives. Default is 1.
; CoverWeight = 2
 
; Check vsim plusargs. Default is 0 (off).
; 0 = Don't check plusargs
; 1 = Warning on unrecognized plusarg
; 2 = Error and exit on unrecognized plusarg
; CheckPlusargs = 1
 
; Load the specified shared objects with the RTLD_GLOBAL flag.
; This gives global visibility to all symbols in the shared objects,
; meaning that subsequently loaded shared objects can bind to symbols
; in the global shared objects. The list of shared objects should
; be whitespace delimited. This option is not supported on the
; Windows or AIX platforms.
; GlobalSharedObjectList = example1.so example2.so example3.so
 
; Generate the stub definitions for the undefined symbols in the shared libraries being
; loaded in the simulation. When this flow is turned on, the undefined symbols will not
; prevent vsim from loading. Calling undefined symbols at runtime will cause fatal error.
; The valid arguments are: on, off, verbose.
; on : turn on the automatic generation of stub definitions.
; off: turn off the flow. The undefined symbols will trigger an immediate load failure.
; verbose: Turn on the flow and report the undefined symbols for each shared library.
; NOTE: This variable can be overriden with vsim switch "-undefsyms".
; The default is on.
;
; UndefSyms = off
 
; Enable the support for checkpointing foreign C++ libraries.
; The valid arguments are: 1 and 0.
; 1 : turn on the support
; 0 : turn off the support (default)
; This option is not supported on the Windows platforms.
;
; AllowCheckpointCpp = 1
 
; Initial seed for the random number generator of the root thread (SystemVerilog).
; NOTE: This variable can be overridden with the vsim "-sv_seed" command line switch.
; The default value is 0.
; Sv_Seed = 0
 
; Specify the solver "engine" that vsim will select for constrained random
; generation.
; Valid values are:
; "auto" - automatically select the best engine for the current
; constraint scenario
; "bdd" - evaluate all constraint scenarios using the BDD solver engine
; "act" - evaluate all constraint scenarios using the ACT solver engine
; While the BDD solver engine is generally efficient with constraint scenarios
; involving bitwise logical relationships, the ACT solver engine can exhibit
; superior performance with constraint scenarios involving large numbers of
; random variables related via arithmetic operators (+, *, etc).
; NOTE: This variable can be overridden with the vsim "-solveengine" command
; line switch.
; The default value is "auto".
; SolveEngine = auto
 
; Specifies the maximum size that a dynamic array may be resized to by the
; solver. If the solver attempts to resize a dynamic array to a size greater
; than the specified limit, the solver will abort with an error.
; The default value is 10000. A value of 0 indicates no limit.
; SolveArrayResizeMax = 10000
 
; Error message severity when normal randomize() and randomize(null) failures are detected.
; Integer value up to two digits are allowed with each digit having the following legal values:
; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal
;
; 1) When a value with two digits is used, the digit at tenth place (leftmost digit) represents
; the severtity setting for normal randomize() calls. The digit at ones place (rightmost digit)
; represents the setting for randomize(null) calls.
;
; 2) When a single digit value is used, the setting is applied to both normal randomize() call
; and randomize(null) call.
;
; Example: -solvefailseverity=40 means:
; fatal error for failed normal randomize() calls and NO error for failed randomize(null) calls.
;
; The default is 0 (no error).
; SolveFailSeverity = 0
 
; Error message severity for suppressible errors that are detected in a
; solve/before constraint.
; NOTE: This variable can be overridden with the vsim "-solvebeforeerrorseverity"
; command line switch.
; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal
; The default is 3 (failure).
; SolveBeforeErrorSeverity = 3
 
; Error message severity for suppressible errors that are related to
; solve engine capacity limits
; NOTE: This variable can be overridden with the vsim "-solveengineerrorseverity"
; command line switch.
; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal
; The default is 3 (failure).
; SolveEngineErrorSeverity = 3
 
; Enable/disable debug information for randomize() failures.
; NOTE: This variable can be overridden with the vsim "-solvefaildebug" command
; line switch.
; The default is 0 (disabled). Set to 1 to enable basic debug (with no
; performance penalty). Set to 2 for enhanced debug (will result in slower
; runtime performance).
; SolveFailDebug = 0
 
; Upon encountering a randomize() failure, generate a simplified testcase that
; will reproduce the failure. Optionally output the testcase to a file.
; Testcases for 'no-solution' failures will only be produced if SolveFailDebug
; is enabled (see above).
; NOTE: This variable can be overridden with the vsim "-solvefailtestcase"
; command line switch.
; The default is OFF (do not generate a testcase). To enable testcase
; generation, uncomment this variable. To redirect testcase generation to a
; file, specify the name of the output file.
; SolveFailTestcase =
 
; Specify solver timeout threshold (in seconds). randomize() will fail if the
; CPU time required to evaluate any randset exceeds the specified timeout.
; The default value is 500. A value of 0 will disable timeout failures.
; SolveTimeout = 500
 
; Specify the maximum size of the solution graph generated by the BDD solver.
; This value can be used to force the BDD solver to abort the evaluation of a
; complex constraint scenario that cannot be evaluated with finite memory.
; This value is specified in 1000s of nodes.
; The default value is 10000. A value of 0 indicates no limit.
; SolveGraphMaxSize = 10000
 
; Specify the maximum number of evaluations that may be performed on the
; solution graph by the BDD solver. This value can be used to force the BDD
; solver to abort the evaluation of a complex constraint scenario that cannot
; be evaluated in finite time. This value is specified in 10000s of evaluations.
; The default value is 10000. A value of 0 indicates no limit.
; SolveGraphMaxEval = 10000
 
; Specify random sequence compatiblity with a prior letter release. This
; option is used to get the same random sequences during simulation as
; as a prior letter release. Only prior letter releases (of the current
; number release) are allowed.
; NOTE: Only those random sequence changes due to solver optimizations are
; reverted by this variable. Random sequence changes due to solver bugfixes
; cannot be un-done.
; NOTE: This variable can be overridden with the vsim "-solverev" command
; line switch.
; Default value set to "" (no compatibility).
; SolveRev =
 
; Environment variable expansion of command line arguments has been depricated
; in favor shell level expansion. Universal environment variable expansion
; inside -f files is support and continued support for MGC Location Maps provide
; alternative methods for handling flexible pathnames.
; The following line may be uncommented and the value set to 1 to re-enable this
; deprecated behavior. The default value is 0.
; DeprecatedEnvironmentVariableExpansion = 0
 
; Specify the memory threshold for the System Verilog garbage collector.
; The value is the number of megabytes of class objects that must accumulate
; before the garbage collector is run.
; The GCThreshold setting is used when class debug mode is disabled to allow
; less frequent garbage collection and better simulation performance.
; The GCThresholdClassDebug setting is used when class debug mode is enabled
; to allow for more frequent garbage collection.
; GCThreshold = 100
; GCThresholdClassDebug = 5
 
; Turn on/off collapsing of bus ports in VCD dumpports output
DumpportsCollapse = 1
 
; Location of Multi-Level Verification Component (MVC) installation.
; The default location is the product installation directory.
MvcHome = $MODEL_TECH/..
 
; Location of InFact installation. The default is $MODEL_TECH/../../infact
;
; InFactHome = $MODEL_TECH/../../infact
 
; Initialize SystemVerilog enums using the base type's default value
; instead of the leftmost value.
; EnumBaseInit = 1
 
; Suppress file type registration.
; SuppressFileTypeReg = 1
 
; Enable/disable non-LRM compliant SystemVerilog language extensions.
; Valid extensions are:
; altdpiheader - Alternative style function signature generated in DPI header",
; cfce - generate an error if $cast fails as a function
; cfmt - C like formatting for specifiers with '#' prefix ('%#x', '%#h')
; dfsp - sets default format specifier as %p, if no format specifier is given for unpacked array in $display and related systasks
; expdfmt - enable format string extensions for $display/$sformatf
; extscan - support values greater than 32 bit for string builtin methods (atohex, atobin, atooct, atoi)
; fmtcap - prints capital hex digits with %X/%H in display calls
; iddp - ignore DPI disable protocol check
; lfmt - zero-pad data if '0' prefixes width in format specifier (e.g. "%04h")
; noexptc - ignore DPI export type name overloading check
; realrand - support randomize() with real variables and constraints (Default)
; thrdrngshfl - use the thread RNG for array.shuffle
; SvExtensions = [+|-]<extension>[,[+|-]<extension>*]
 
; Enable/disable non-LRM compliant SystemVerilog constrained-random language extensions.
; Valid extensions are:
; arraymode - consider rand_mode of unpacked array field independently from its elements
; deepcheck - allow randomize(null) to recursively consider constraints from member rand class handles
; funcback - enable function backtracking (ACT only)
; nodist - interpret 'dist' constraint as 'inside' (ACT only)
; noorder - ignore solve/before ordering constraints (ACT only)
; promotedist - promote priority of 'dist' constraint if LHS has no solve/before
; randindex - allow random index in constraint (Default)
; randstruct - consider all fields of unpacked structs as 'rand'
; skew - skew randomize results (ACT only)
; strictstab - strict random stability
; SvRandExtensions = [+|-]<extension>[,[+|-]<extension>*]
 
; Controls the formatting of '%p' and '%P' conversion specification, used in $display
; and similar system tasks.
; 1. SVPrettyPrintFlags=I<n><S|T> use <n> spaces(S) or tabs(T) per indentation level.
; The 'I' flag when present causes relevant data types to be expanded and indented into
; a more readable format.
; (e.g. SVPrettyPrintFlags=I4S will cause 4 spaces to be used per indentation level).
; 2. SVPrettyPrintFlags=L<numLines> limits the output to <numLines> lines.
; (e.g. SVPrettyPrintFlags=L20 will limit the output to 20 lines).
; 3. SVPrettyPrintFlags=C<numChars> limits the output to <numChars> characters.
; (e.g. SVPrettyPrintFlags=C256 will limit the output to 256 characters).
; 4. SVPrettyPrintFlags=F<numFields> limits the output to <numFields> of relevant datatypes
; (e.g. SVPrettyPrintFlags=F4 will limit the output to 4 fields of a structure).
; 5. SVPrettyPrintFlags=E<numElements> limits the output to <numElements> of relevant datatypes
; (e.g. SVPrettyPrintFlags=E50 will limit the output to 50 elements of an array).
; 6. SVPrettyPrintFlags=D<depth> suppresses the output of sub-elements below <depth>.
; (e.g. SVPrettyPrintFlags=D5 will suppresses the output of sub elements below a depth of 5).
; 7. SVPrettyPrintFlags=R<specifier> shows the output of specifier %p as per the specifed radix.
; It changes the output in $display and similar systasks. It does not affect formatted output functions ($displayh etc)).
; (e.g. SVPrettyPrintFlags=Rb will show the output of %p specifier in binary format.
; 8. Items 1-7 above can be combined as a comma separated list.
; (e.g. SVPrettyPrintFlags=I4S,L20,C256,F4,E50,D5,Rb)
; SVPrettyPrintFlags=I4S
 
[lmc]
; The simulator's interface to Logic Modeling's SmartModel SWIFT software
libsm = $MODEL_TECH/libsm.sl
; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
; libsm = $MODEL_TECH/libsm.dll
; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
; Logic Modeling's SmartModel SWIFT software (Windows NT)
; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux)
; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so
; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux)
; libswift = $LMC_HOME/lib/linux.lib/libswift.so
 
; The simulator's interface to Logic Modeling's hardware modeler SFI software
libhm = $MODEL_TECH/libhm.sl
; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
; libhm = $MODEL_TECH/libhm.dll
; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
; libsfi = <sfi_dir>/lib/hp700/libsfi.sl
; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
; libsfi = <sfi_dir>/lib/rs6000/libsfi.a
; Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
; libsfi = <sfi_dir>/lib/sun4.solaris/libsfi.so
; Logic Modeling's hardware modeler SFI software (Windows NT)
; libsfi = <sfi_dir>/lib/pcnt/lm_sfi.dll
; Logic Modeling's hardware modeler SFI software (Linux)
; libsfi = <sfi_dir>/lib/linux/libsfi.so
 
[msg_system]
; Change a message severity or suppress a message.
; The format is: <msg directive> = <msg number>[,<msg number>...]
; suppress can be used to achieve +nowarn<CODE> functionality
; The format is: suppress = <CODE>,<msg number>,[<CODE>,<msg number>,...]
; Examples:
suppress = 8780 ;an explanation can be had by running: verror 8780
; note = 3009
; warning = 3033
; error = 3010,3016
; fatal = 3016,3033
; suppress = 3009,3016,3601
; suppress = 3009,CNNODP,3601,TFMPC
; suppress = 8683,8684
; The command verror <msg number> can be used to get the complete
; description of a message.
 
; Control transcripting of Verilog display system task messages and
; PLI/FLI print function call messages. The system tasks include
; $display[bho], $strobe[bho], $monitor[bho], and $write[bho]. They
; also include the analogous file I/O tasks that write to STDOUT
; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf,
; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default
; is to have messages appear only in the transcript. The other
; settings are to send messages to the wlf file only (messages that
; are recorded in the wlf file can be viewed in the MsgViewer) or
; to both the transcript and the wlf file. The valid values are
; tran {transcript only (default)}
; wlf {wlf file only}
; both {transcript and wlf file}
; displaymsgmode = tran
 
; Control transcripting of elaboration/runtime messages not
; addressed by the displaymsgmode setting. The default is to
; have messages appear only in the transcript. The other settings
; are to send messages to the wlf file only (messages that are
; recorded in the wlf file can be viewed in the MsgViewer) or to both
; the transcript and the wlf file. The valid values are
; tran {transcript only (default)}
; wlf {wlf file only}
; both {transcript and wlf file}
; msgmode = tran
 
; Controls number of displays of a particluar message
; default value is 5
; MsgLimitCount = 5
 
[utils]
; Default Library Type (while creating a library with "vlib")
; 0 - legacy library using subdirectories for design units
; 2 - flat library
; DefaultLibType = 2
 
; Flat Library Page Size (while creating a library with "vlib")
; Set the size in bytes for flat library file pages. Libraries containing
; very large files may benefit from a larger value.
; FlatLibPageSize = 8192
 
; Flat Library Page Cleanup Percentage (while creating a library with "vlib")
; Set the percentage of total pages deleted before library cleanup can occur.
; This setting is applied together with FlatLibPageDeleteThreshold.
; FlatLibPageDeletePercentage = 50
 
; Flat Library Page Cleanup Threshold (while creating a library with "vlib")
; Set the number of pages deleted before library cleanup can occur.
; This setting is applied together with FlatLibPageDeletePercentage.
; FlatLibPageDeleteThreshold = 1000
 
/modelsim_filelist.f
0,0 → 1,3
+incdir+./../rtl/src_noc/
-F ../rtl/src_noc/noc_filelist.f
-F ../rtl/src_modelsim/filelist.f
/noc_files.f
0,0 → 1,34
${workspace_loc}/mpsoc/rtl/arbiter.v
${workspace_loc}/mpsoc/rtl/src_noc/fattree.v
${workspace_loc}/mpsoc/rtl/src_noc/route_mesh.v
${workspace_loc}/mpsoc/rtl/src_noc/baseline.v
${workspace_loc}/mpsoc/rtl/src_noc/flit_buffer_reg_bas.v
${workspace_loc}/mpsoc/rtl/src_noc/router_bypass.sv
${workspace_loc}/mpsoc/rtl/src_noc/canonical_credit_count.v
${workspace_loc}/mpsoc/rtl/src_noc/flit_buffer.v
${workspace_loc}/mpsoc/rtl/src_noc/router.v
${workspace_loc}/mpsoc/rtl/src_noc/class_table.v
${workspace_loc}/mpsoc/rtl/src_noc/header_flit.v
${workspace_loc}/mpsoc/rtl/src_noc/route_torus.v
${workspace_loc}/mpsoc/rtl/src_noc/combined_vc_sw_alloc.v
${workspace_loc}/mpsoc/rtl/src_noc/inout_ports.v
${workspace_loc}/mpsoc/rtl/src_noc/routing.v
${workspace_loc}/mpsoc/rtl/src_noc/comb_nonspec.v
${workspace_loc}/mpsoc/rtl/src_noc/input_ports.v
${workspace_loc}/mpsoc/rtl/src_noc/ss_allocator.v
${workspace_loc}/mpsoc/rtl/src_noc/comb-spec1.v
${workspace_loc}/mpsoc/rtl/src_noc/iport_reg_base.v
${workspace_loc}/mpsoc/rtl/src_noc/test_topology_genvar.v
${workspace_loc}/mpsoc/rtl/src_noc/comb_spec2.v
${workspace_loc}/mpsoc/rtl/main_comp.v
${workspace_loc}/mpsoc/rtl/src_noc/congestion_analyzer.v
${workspace_loc}/mpsoc/rtl/src_noc/mesh_torus_noc.v
${workspace_loc}/mpsoc/rtl/src_noc/traffic_gen.v
${workspace_loc}/mpsoc/rtl/src_noc/credit_count.v
${workspace_loc}/mpsoc/rtl/src_noc/mesh_torus_routting.v
${workspace_loc}/mpsoc/rtl/src_noc/tree.v
${workspace_loc}/mpsoc/rtl/src_noc/crossbar.v
${workspace_loc}/mpsoc/rtl/src_noc/mesh_torus.v
${workspace_loc}/mpsoc/rtl/src_noc/wrra.v
${workspace_loc}/mpsoc/rtl/src_noc/debug.v
${workspace_loc}/mpsoc/rtl/src_noc/noc.v
/replace.sh
0,0 → 1,2
grep -rl 'flit_in_we' ./ | xargs sed -i 's/flit_in_we/flit_in_wr/g'
grep -rl 'flit_out_we' ./ | xargs sed -i 's/flit_out_we/flit_out_wr/g'
replace.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: run_modelsim =================================================================== --- run_modelsim (revision 45) +++ run_modelsim (revision 48) @@ -1,5 +1,23 @@ #!/bin/bash -/home/alireza/intelFPGA_lite/17.1/modelsim_ase/bin/vsim -do model.tcl +#/home/alireza/intelFPGA_lite/17.1/modelsim_ase/bin/vsim -do model.tcl #/home/alireza/altera/13.0sp1/modelsim_ase/bin/vsim -do model.tcl #/home/alireza/altera/modeltech/bin/vsim -do model.tcl +SCRPT_FULL_PATH=$(realpath ${BASH_SOURCE[0]}) +SCRPT_DIR_PATH=$(dirname $SCRPT_FULL_PATH) + +#questasim +LM_LICENSE="1717@epi03.bsc.es" +VSIM_BIN="/home/alireza/intelFPGA_lite/questa/questasim/bin/vsim" + +export LM_LICENSE_FILE=${LM_LICENSE} +export LM_WORK_PLACE=${PRONOC_WORK}/simulation +export LM_FILE_LIST="$SCRPT_DIR_PATH/modelsim_filelist.f" + +#"$SCRPT_DIR_PATH/../rtl/src_noc/noc_filelist.f $SCRPT_DIR_PATH/../rtl/src_modelsim/filelist.f" + + +echo "Start simulation" >&3 +$VSIM_BIN -quiet -64 -do model.tcl +wait +echo "End of Simulation" >&3
/sbp_lint.sh
0,0 → 1,10
#!/bin/bash
 
 
 
#top="packet_injector"
#top="noc_top_v"
top="router_top_v"
 
echo "filelist: $1";
verilator --lint-only --cc --top-module $top --profile-cfuncs --prefix "Vnoc" -O3 -CFLAGS -O3 -f $1/noc_filelist.f -y $1
sbp_lint.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: server/Integration_test/config =================================================================== --- server/Integration_test/config (nonexistent) +++ server/Integration_test/config (revision 48) @@ -0,0 +1,36 @@ + + + +#install perl locally on the server +#select a srever which has following file +ls /opt/rh/devtoolset-7/root/usr/bin/make + + +#1-go to https://www.cpan.org/src/ + + wget https://www.cpan.org/src/5.0/perl-5.34.0.tar.gz + tar -xzf perl-5.34.0.tar.gz + cd perl-5.34.0 + ./Configure -des -Dprefix=$HOME/localperl + make + make test + make install + + +#2- + perl -MCPAN -e shell + o conf makepl_arg INSTALL_BASE=~/localperl + o conf commit + + install String::Similarity + install CPAN::DistnameInfo + install Test::utf8 + install Try::Tiny + install Test::Fatal + install Test::MockRandom + install File::Copy::Recursive File::Find::Rule constant::boolean Class::Accessor::Fast Proc::Background List::MoreUtils + install IPC::Run + + + + Index: server/Integration_test/report =================================================================== --- server/Integration_test/report (nonexistent) +++ server/Integration_test/report (revision 48) @@ -0,0 +1,91 @@ +Verification Results: +****************************bintree_k3_L3_st : Compile *******************************: + model is generated successfully. +****************************custom1_topology : Compile *******************************: + model is generated successfully. +****************************Fattree_k3_L3_st : Compile *******************************: + model is generated successfully. +****************************fmesh_1x1_openpiton : Compile *******************************: + model is generated successfully. +****************************fmesh_2x2_openpiton : Compile *******************************: + model is generated successfully. +****************************fmesh_8x8_2cycle_xy : Compile *******************************: + model is generated successfully. +****************************mesh_2x2_openpiton : Compile *******************************: + model is generated successfully. +****************************mesh_4x4x3_2cycle_xy : Compile *******************************: + model is generated successfully. +****************************mesh_8x8_2cycle_adaptive : Compile *******************************: + model is generated successfully. +****************************mesh_8x8_2cycle_west_first : Compile *******************************: + model is generated successfully. +****************************mesh_8x8_2cycle_xy : Compile *******************************: + model is generated successfully. +****************************mesh_8x8_b2 : Compile *******************************: + model is generated successfully. +****************************mesh_8x8_sbp6_xy : Compile *******************************: + model is generated successfully. +****************************mesh_8x8_ssa_xy : Compile *******************************: + model is generated successfully. +****************************torus_8x8_2cycle_xy : Compile *******************************: + model is generated successfully. +****************************bintree_k3_L3_st : random traffic *******************************: + Passed: zero load (2,14.7281) saturation (14,379.752) +****************************custom1_topology : random traffic *******************************: + Passed: zero load (2,13.1179) saturation (46,86.3685) +****************************Fattree_k3_L3_st : random traffic *******************************: + Passed: zero load (2,13.6576) saturation (62,71.6165) +****************************fmesh_1x1_openpiton : random traffic *******************************: + Passed: zero load (6,7.28354) saturation (70,60.8977) +****************************fmesh_2x2_openpiton : random traffic *******************************: + Passed: zero load (2,8.44643) saturation (50,50.8248) +****************************fmesh_8x8_2cycle_xy : random traffic *******************************: + Passed: zero load (2,19.5545) saturation (18,139.838) +****************************mesh_2x2_openpiton : random traffic *******************************: + Passed: zero load (6,9.3401) saturation (66,96.9067) +****************************mesh_4x4x3_2cycle_xy : random traffic *******************************: + Passed: zero load (2,12.746) saturation (26,176.019) +****************************mesh_8x8_2cycle_adaptive : random traffic *******************************: + Passed: zero load (2,17.8393) saturation (34,152.975) +****************************mesh_8x8_2cycle_west_first : random traffic *******************************: + Passed: zero load (2,17.8471) saturation (34,145.493) +****************************mesh_8x8_2cycle_xy : random traffic *******************************: + Passed: zero load (2,17.8508) saturation (38,164.783) +****************************mesh_8x8_b2 : random traffic *******************************: + Passed: zero load (2,22.3767) saturation (30,188.136) +****************************mesh_8x8_sbp6_xy : random traffic *******************************: + Passed: zero load (2,10.9141) saturation (34,82.2115) +****************************mesh_8x8_ssa_xy : random traffic *******************************: + Passed: zero load (2,14.461) saturation (34,98.62) +****************************torus_8x8_2cycle_xy : random traffic *******************************: + Passed: zero load (2,16.5606) saturation (38,95.6085) +****************************bintree_k3_L3_st : transposed 1 traffic *******************************: + Passed: zero load (2,14.7752) saturation (14,437.991) +****************************custom1_topology : transposed 1 traffic *******************************: + Passed: zero load (2,12.8065) saturation (34,72.4262) +****************************Fattree_k3_L3_st : transposed 1 traffic *******************************: + Passed: zero load (6,13.4357) saturation (100,-) +****************************fmesh_1x1_openpiton : transposed 1 traffic *******************************: + Passed: zero load (50,6.98981) saturation (100,-) +****************************fmesh_2x2_openpiton : transposed 1 traffic *******************************: + Passed: zero load (2,9.55789) saturation (46,80.2851) +****************************fmesh_8x8_2cycle_xy : transposed 1 traffic *******************************: + Passed: zero load (2,21.6498) saturation (14,150.105) +****************************mesh_2x2_openpiton : transposed 1 traffic *******************************: + Passed: zero load (2,8.59722) saturation (100,-) +****************************mesh_4x4x3_2cycle_xy : transposed 1 traffic *******************************: + Passed: zero load (2,12.8887) saturation (14,134.467) +****************************mesh_8x8_2cycle_adaptive : transposed 1 traffic *******************************: + Passed: zero load (2,19.5769) saturation (26,108.948) +****************************mesh_8x8_2cycle_west_first : transposed 1 traffic *******************************: + Passed: zero load (2,19.5526) saturation (22,103.205) +****************************mesh_8x8_2cycle_xy : transposed 1 traffic *******************************: + Passed: zero load (2,19.5652) saturation (18,126.475) +****************************mesh_8x8_b2 : transposed 1 traffic *******************************: + Passed: zero load (2,23.8014) saturation (18,119.631) +****************************mesh_8x8_sbp6_xy : transposed 1 traffic *******************************: + Passed: zero load (2,11.4453) saturation (18,121.72) +****************************mesh_8x8_ssa_xy : transposed 1 traffic *******************************: + Passed: zero load (2,15.635) saturation (18,121.085) +****************************torus_8x8_2cycle_xy : transposed 1 traffic *******************************: + Passed: zero load (2,18.0481) saturation (18,131.333) Index: server/Integration_test/report_old =================================================================== --- server/Integration_test/report_old (nonexistent) +++ server/Integration_test/report_old (revision 48) @@ -0,0 +1,91 @@ +Verification Results: +****************************bintree_k3_L3_st : Compile *******************************: + model is generated successfully. +****************************custom1_topology : Compile *******************************: + model is generated successfully. +****************************Fattree_k3_L3_st : Compile *******************************: + model is generated successfully. +****************************fmesh_1x1_openpiton : Compile *******************************: + model is generated successfully. +****************************fmesh_2x2_openpiton : Compile *******************************: + model is generated successfully. +****************************fmesh_8x8_2cycle_xy : Compile *******************************: + model is generated successfully. +****************************mesh_2x2_openpiton : Compile *******************************: + model is generated successfully. +****************************mesh_4x4x3_2cycle_xy : Compile *******************************: + model is generated successfully. +****************************mesh_8x8_2cycle_adaptive : Compile *******************************: + model is generated successfully. +****************************mesh_8x8_2cycle_west_first : Compile *******************************: + model is generated successfully. +****************************mesh_8x8_2cycle_xy : Compile *******************************: + model is generated successfully. +****************************mesh_8x8_b2 : Compile *******************************: + model is generated successfully. +****************************mesh_8x8_sbp6_xy : Compile *******************************: + model is generated successfully. +****************************mesh_8x8_ssa_xy : Compile *******************************: + model is generated successfully. +****************************torus_8x8_2cycle_xy : Compile *******************************: + model is generated successfully. +****************************bintree_k3_L3_st : random traffic *******************************: + Passed: zero load (2,14.7281) saturation (14,590.075) +****************************custom1_topology : random traffic *******************************: + Passed: zero load (2,13.1179) saturation (42,87.1052) +****************************Fattree_k3_L3_st : random traffic *******************************: + Passed: zero load (2,13.6576) saturation (62,121.906) +****************************fmesh_1x1_openpiton : random traffic *******************************: + Passed: zero load (6,7.28354) saturation (62,47.9529) +****************************fmesh_2x2_openpiton : random traffic *******************************: + Passed: zero load (2,8.44643) saturation (46,78.8617) +****************************fmesh_8x8_2cycle_xy : random traffic *******************************: + Passed: zero load (2,19.5545) saturation (18,155.581) +****************************mesh_2x2_openpiton : random traffic *******************************: + Passed: zero load (6,9.3401) saturation (62,118.704) +****************************mesh_4x4x3_2cycle_xy : random traffic *******************************: + Passed: zero load (2,12.746) saturation (22,66.6152) +****************************mesh_8x8_2cycle_adaptive : random traffic *******************************: + Passed: zero load (2,17.8393) saturation (34,251.245) +****************************mesh_8x8_2cycle_west_first : random traffic *******************************: + Passed: zero load (2,17.8471) saturation (34,187.293) +****************************mesh_8x8_2cycle_xy : random traffic *******************************: + Passed: zero load (2,17.8508) saturation (34,182.91) +****************************mesh_8x8_b2 : random traffic *******************************: + Passed: zero load (2,22.3767) saturation (26,162.042) +****************************mesh_8x8_sbp6_xy : random traffic *******************************: + Passed: zero load (2,10.9141) saturation (34,154.839) +****************************mesh_8x8_ssa_xy : random traffic *******************************: + Passed: zero load (2,14.461) saturation (34,160.416) +****************************torus_8x8_2cycle_xy : random traffic *******************************: + Passed: zero load (2,16.5606) saturation (38,167.525) +****************************bintree_k3_L3_st : transposed 1 traffic *******************************: + Passed: zero load (2,14.7752) saturation (14,501.411) +****************************custom1_topology : transposed 1 traffic *******************************: + Passed: zero load (2,12.8065) saturation (30,74.697) +****************************Fattree_k3_L3_st : transposed 1 traffic *******************************: + Passed: zero load (6,13.4357) saturation (100,-) +****************************fmesh_1x1_openpiton : transposed 1 traffic *******************************: + Passed: zero load (50,6.98981) saturation (100,-) +****************************fmesh_2x2_openpiton : transposed 1 traffic *******************************: + Passed: zero load (2,9.55789) saturation (42,56.4886) +****************************fmesh_8x8_2cycle_xy : transposed 1 traffic *******************************: + Passed: zero load (2,21.6498) saturation (14,162.412) +****************************mesh_2x2_openpiton : transposed 1 traffic *******************************: + Passed: zero load (2,8.59722) saturation (100,-) +****************************mesh_4x4x3_2cycle_xy : transposed 1 traffic *******************************: + Passed: zero load (2,12.8887) saturation (14,182.267) +****************************mesh_8x8_2cycle_adaptive : transposed 1 traffic *******************************: + Passed: zero load (2,19.5769) saturation (26,139.04) +****************************mesh_8x8_2cycle_west_first : transposed 1 traffic *******************************: + Passed: zero load (2,19.5526) saturation (22,108.232) +****************************mesh_8x8_2cycle_xy : transposed 1 traffic *******************************: + Passed: zero load (2,19.5652) saturation (18,136.997) +****************************mesh_8x8_b2 : transposed 1 traffic *******************************: + Passed: zero load (2,23.8014) saturation (18,145.991) +****************************mesh_8x8_sbp6_xy : transposed 1 traffic *******************************: + Passed: zero load (2,11.4453) saturation (18,130.27) +****************************mesh_8x8_ssa_xy : transposed 1 traffic *******************************: + Passed: zero load (2,15.635) saturation (18,129.592) +****************************torus_8x8_2cycle_xy : transposed 1 traffic *******************************: + Passed: zero load (2,18.0481) saturation (18,175.375) Index: server/Integration_test/run.sh =================================================================== --- server/Integration_test/run.sh (nonexistent) +++ server/Integration_test/run.sh (revision 48) @@ -0,0 +1,99 @@ +#!/bin/bash + +#the max server load that is permited for runing the parallel test +max_allowed_server_load=35 +source "my_password.sh" # define servers and passwords + +SCRPT_FULL_PATH=$(realpath ${BASH_SOURCE[0]}) +SCRPT_DIR_PATH=$(dirname $SCRPT_FULL_PATH) + + + + + +#servers=( $server1 $server2 $server3 ) # an array which define the list of servers +my_server="to be selected" +SERVER_ROOT_DIR="~/pronoc_verify" + +ProNoC="../../.." + +my_srcs=( "rtl" + "Integration_test" + "src_verilator" + "src_c/netrace-1.0" + "script" + "/perl_gui/lib/perl" ) + + +rm "$SCRPT_DIR_PATH/report" + + + + +#copy_sources +#login_in_server + +#step one login in tje server and read the load +function get_server_avg_load { + out=$(sshpass -p $my_passwd ssh -t -o "StrictHostKeyChecking no" $1 "uptime") + load_avg=$(grep -oP '(?<=load average: )[0-9]+' <<< $out) +} + + +function select_a_server { + min_load="100" + + for i in "${servers[@]}"; do + echo "get load average on $i server" + get_server_avg_load $i + echo $load_avg + if [ $min_load -gt $load_avg ] + then + min_load=$load_avg + my_server=$i + fi + done + if [ $min_load -gt $max_allowed_server_load ] + then + echo "All servers are busy. Cannot continue" + exit + fi + echo "server $my_server is selected for running the test" +} + + +function copy_sources { + sshpass -p $my_passwd ssh -o "StrictHostKeyChecking no" $my_server rm -rf ${SERVER_ROOT_DIR} + sshpass -p $my_passwd ssh -o "StrictHostKeyChecking no" $my_server mkdir -p "${SERVER_ROOT_DIR}/mpsoc/perl_gui/lib/" + sshpass -p $my_passwd ssh -o "StrictHostKeyChecking no" $my_server mkdir -p "${SERVER_ROOT_DIR}/mpsoc/src_c/" + sshpass -p $my_passwd ssh -o "StrictHostKeyChecking no" $my_server mkdir -p "${SERVER_ROOT_DIR}/mpsoc_work" + for i in "${my_srcs[@]}"; do + echo "Copy $i on the server" + sshpass -p $my_passwd scp -o "StrictHostKeyChecking no" -r "$ProNoC/$i" "$my_server:${SERVER_ROOT_DIR}/mpsoc/$i" + done + sshpass -p $my_passwd scp -o "StrictHostKeyChecking no" -r "$SCRPT_DIR_PATH/server_run.sh" "$my_server:${SERVER_ROOT_DIR}/mpsoc/Integration_test/server_run.sh" +} + + +function run_test { + cmd="export PRONOC_WORK=${SERVER_ROOT_DIR}/mpsoc_work;" + sshpass -p $my_passwd ssh -t -o "StrictHostKeyChecking no" $my_server $cmd + +} + +#setps to run the verrification + +#1 +select_a_server +#2 +copy_sources +#3 run the test + +sshpass -p $my_passwd ssh -o "StrictHostKeyChecking no" $my_server "cd ${SERVER_ROOT_DIR}/mpsoc/Integration_test; source \"/etc/profile\"; bash server_run.sh;" + +#collect the report +rm "$SCRPT_DIR_PATH/report" +sshpass -p $my_passwd scp -o "StrictHostKeyChecking no" -r "$my_server:${SERVER_ROOT_DIR}/mpsoc/Integration_test/report" "$SCRPT_DIR_PATH/report" +wait +gedit "$SCRPT_DIR_PATH/report" +
server/Integration_test/run.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: server/Integration_test/server_bashrc =================================================================== --- server/Integration_test/server_bashrc (nonexistent) +++ server/Integration_test/server_bashrc (revision 48) @@ -0,0 +1,8 @@ +export PATH=$HOME/localperl:$PATH +export PERL_LOCAL_LIB_ROOT="$HOME/localperl" +export PERL_MB_OPT="--install_base $HOME/localperl" +export PERL_MM_OPT="INSTALL_BASE=$HOME/localperl" +export PERL5LIB=$HOME/localperl/lib/5.34.0:$HOME/localperl/lib/perl5:$PERL5LIB +export localperl=/$HOME/localperl/bin/perl + + Index: server/Integration_test/server_run.sh =================================================================== --- server/Integration_test/server_run.sh (nonexistent) +++ server/Integration_test/server_run.sh (revision 48) @@ -0,0 +1,23 @@ +#!/bin/bash + +source "/etc/profile" + + SCRPT_FULL_PATH=$(realpath ${BASH_SOURCE[0]}) + SCRPT_DIR_PATH=$(dirname $SCRPT_FULL_PATH) + +echo "\$SCRPT_DIR_PATH is $SCRPT_DIR_PATH" + +export PRONOC_WORK=$SCRPT_DIR_PATH/../../mpsoc_work +export PATH=$PATH:/opt/verilator/bin +source "/eda/env.sh" + + + + +home=$(eval echo ~$USER) +source "$home/.bash_profile" + +$localperl ./verify.perl "20" "2" "80" "4" + + +
server/Integration_test/server_run.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: server/kc07/hardware =================================================================== --- server/kc07/hardware (nonexistent) +++ server/kc07/hardware (revision 48) @@ -0,0 +1,668 @@ +Report Instance Areas: ++------+-------------------------------------------------------------+--------------------------------------------------+------+ +| |Instance |Module |Cells | ++------+-------------------------------------------------------------+--------------------------------------------------+------+ +|1 |top | | 37643| +|2 | uut |kc07_mesh_top | 37632| +|3 | jwb_3 |xilinx_jtag_wb__parameterized0 | 194| +|4 | \block[0].ack_latch |wb_to_jtag_latch_535 | 4| +|5 | \block[1].ack_latch |wb_to_jtag_latch_536 | 4| +|6 | \block[2].ack_latch |wb_to_jtag_latch_537 | 4| +|7 | \block[3].ack_latch |wb_to_jtag_latch_538 | 4| +|8 | mem_ctrl |xilinx_jtag_mem_ctrl__parameterized0 | 177| +|9 | vjtag_ctrl_inst |xilinx_jtag_ctrl__parameterized0 | 157| +|10 | vjtag_inst |xilinx_jtag_bscan__parameterized0 | 47| +|11 | jwb_4 |xilinx_jtag_wb | 319| +|12 | \block[0].ack_latch |wb_to_jtag_latch | 4| +|13 | \block[1].ack_latch |wb_to_jtag_latch_532 | 4| +|14 | \block[2].ack_latch |wb_to_jtag_latch_533 | 4| +|15 | \block[3].ack_latch |wb_to_jtag_latch_534 | 4| +|16 | mem_ctrl |xilinx_jtag_mem_ctrl | 297| +|17 | vjtag_ctrl_inst |xilinx_jtag_ctrl | 247| +|18 | vjtag_inst |xilinx_jtag_bscan | 52| +|19 | pll |xilinx_pll2_base | 1| +|20 | the_kc07_mesh |kc07_mesh | 37117| +|21 | the_mor1k_tile_0 |mor1k_tile | 8166| +|22 | bus |wishbone_bus_471 | 471| +|23 | arbiter |bus_arbiter__parameterized0_529 | 471| +|24 | the_combinational_arbiter |arbiter__parameterized0_530 | 2| +|25 | \w4.one_hot_arb |my_one_hot_arbiter__parameterized0_531 | 2| +|26 | cpu |mor1k_472 | 6060| +|27 | mor1kx0 |mor1kx_495 | 5890| +|28 | mor1kx_cpu |mor1kx_cpu_496 | 5890| +|29 | \cappuccino.mor1kx_cpu |mor1kx_cpu_cappuccino_497 | 5888| +|30 | mor1kx_branch_prediction |mor1kx_branch_prediction_498 | 2| +|31 | mor1kx_ctrl_cappuccino |mor1kx_ctrl_cappuccino_499 | 827| +|32 | \pic.mor1kx_pic |mor1kx_pic_527 | 144| +|33 | \tt.mor1kx_ticktimer |mor1kx_ticktimer_528 | 118| +|34 | mor1kx_decode_execute_cappuccino |mor1kx_decode_execute_cappuccino_500 | 638| +|35 | mor1kx_execute_alu |mor1kx_execute_alu_501 | 297| +|36 | mor1kx_execute_ctrl_cappuccino |mor1kx_execute_ctrl_cappuccino_502 | 984| +|37 | mor1kx_fetch_cappuccino |mor1kx_fetch_cappuccino_503 | 908| +|38 | \icache_gen.mor1kx_icache |mor1kx_icache_520 | 294| +|39 | tag_ram |mor1kx_simple_dpram_sclk__parameterized0_524 | 130| +|40 | \way_memories[0].way_data_ram |mor1kx_simple_dpram_sclk_525 | 15| +|41 | \way_memories[1].way_data_ram |mor1kx_simple_dpram_sclk_526 | 42| +|42 | \immu_gen.mor1kx_immu |mor1kx_immu_521 | 236| +|43 | itlb_match_regs |mor1kx_true_dpram_sclk_522 | 166| +|44 | itlb_translate_regs |mor1kx_true_dpram_sclk_523 | 25| +|45 | mor1kx_lsu_cappuccino |mor1kx_lsu_cappuccino_504 | 1387| +|46 | \dcache_gen.mor1kx_dcache |mor1kx_dcache_510 | 800| +|47 | snoop_tag_ram |mor1kx_simple_dpram_sclk__parameterized3_516 | 375| +|48 | tag_ram |mor1kx_simple_dpram_sclk__parameterized4_517 | 191| +|49 | \way_memories[0].way_data_ram |mor1kx_simple_dpram_sclk__parameterized2_518 | 72| +|50 | \way_memories[1].way_data_ram |mor1kx_simple_dpram_sclk__parameterized2_519 | 23| +|51 | \dmmu_gen.mor1kx_dmmu |mor1kx_dmmu_511 | 240| +|52 | dtlb_match_regs |mor1kx_true_dpram_sclk_514 | 60| +|53 | dtlb_translate_regs |mor1kx_true_dpram_sclk_515 | 175| +|54 | \store_buffer_gen.mor1kx_store_buffer |mor1kx_store_buffer_512 | 162| +|55 | fifo_ram |mor1kx_simple_dpram_sclk__parameterized1_513 | 121| +|56 | mor1kx_rf_cappuccino |mor1kx_rf_cappuccino_505 | 734| +|57 | rfa |mor1kx_simple_dpram_sclk__parameterized5_507 | 33| +|58 | rfb |mor1kx_simple_dpram_sclk__parameterized5_508 | 33| +|59 | \rfspr_gen.rfspr |mor1kx_simple_dpram_sclk__parameterized5_509 | 1| +|60 | mor1kx_wb_mux_cappuccino |mor1kx_wb_mux_cappuccino_506 | 111| +|61 | led |gpo_473 | 2| +|62 | ni |ni_master_474 | 1019| +|63 | \multi_channel.receive_arbiter |bus_arbiter_480 | 11| +|64 | the_combinational_arbiter |arbiter_493 | 2| +|65 | \w4.one_hot_arb |my_one_hot_arbiter_494 | 2| +|66 | \multi_channel.send_arbiter |bus_arbiter_481 | 10| +|67 | the_combinational_arbiter |arbiter_491 | 2| +|68 | \w4.one_hot_arb |my_one_hot_arbiter_492 | 2| +|69 | \precap.vc__[0].precap_data_fifo |fwft_fifo__parameterized1_482 | 11| +|70 | \precap.vc__[1].precap_data_fifo |fwft_fifo__parameterized1_483 | 14| +|71 | the_ififo |flit_buffer_484 | 81| +|72 | \pow2.the_queue |fifo_ram_490 | 49| +|73 | the_ovc_status |ovc_status_485 | 15| +|74 | \vc_[0].vc_dma |ni_vc_dma_486 | 215| +|75 | \vc_[0].wb_slave_registers |ni_vc_wb_slave_regs_487 | 191| +|76 | \vc_[1].vc_dma |ni_vc_dma_488 | 213| +|77 | \vc_[1].wb_slave_registers |ni_vc_wb_slave_regs_489 | 224| +|78 | ram |wb_single_port_ram | 296| +|79 | ctrl |wb_bram_ctrl_478 | 226| +|80 | \burst_wb.bram_ctrl |wb_burst_bram_ctrl_479 | 226| +|81 | ram_top |single_port_ram_top | 70| +|82 | \xilinx_fpga.xilinx_dual.xpm_memory_tdpram_inst |xpm_memory_tdpram | 64| +|83 | xpm_memory_base_inst |xpm_memory_base | 64| +|84 | timer |timer_475 | 187| +|85 | uart |pronoc_jtag_uart | 131| +|86 | uart_hw |pronoc_jtag_uart_hw | 131| +|87 | jtag_to_wb_fifo |uart_fifo_476 | 57| +|88 | wb_to_jtag_fifo |uart_fifo_477 | 66| +|89 | the_mor1k_tile_1 |mor1k_tile__parameterized0 | 8154| +|90 | bus |wishbone_bus_410 | 465| +|91 | arbiter |bus_arbiter__parameterized0_468 | 465| +|92 | the_combinational_arbiter |arbiter__parameterized0_469 | 2| +|93 | \w4.one_hot_arb |my_one_hot_arbiter__parameterized0_470 | 2| +|94 | cpu |mor1k_411 | 6061| +|95 | mor1kx0 |mor1kx_434 | 5891| +|96 | mor1kx_cpu |mor1kx_cpu_435 | 5891| +|97 | \cappuccino.mor1kx_cpu |mor1kx_cpu_cappuccino_436 | 5889| +|98 | mor1kx_branch_prediction |mor1kx_branch_prediction_437 | 2| +|99 | mor1kx_ctrl_cappuccino |mor1kx_ctrl_cappuccino_438 | 847| +|100 | \pic.mor1kx_pic |mor1kx_pic_466 | 145| +|101 | \tt.mor1kx_ticktimer |mor1kx_ticktimer_467 | 118| +|102 | mor1kx_decode_execute_cappuccino |mor1kx_decode_execute_cappuccino_439 | 638| +|103 | mor1kx_execute_alu |mor1kx_execute_alu_440 | 297| +|104 | mor1kx_execute_ctrl_cappuccino |mor1kx_execute_ctrl_cappuccino_441 | 984| +|105 | mor1kx_fetch_cappuccino |mor1kx_fetch_cappuccino_442 | 889| +|106 | \icache_gen.mor1kx_icache |mor1kx_icache_459 | 294| +|107 | tag_ram |mor1kx_simple_dpram_sclk__parameterized0_463 | 130| +|108 | \way_memories[0].way_data_ram |mor1kx_simple_dpram_sclk_464 | 15| +|109 | \way_memories[1].way_data_ram |mor1kx_simple_dpram_sclk_465 | 42| +|110 | \immu_gen.mor1kx_immu |mor1kx_immu_460 | 217| +|111 | itlb_match_regs |mor1kx_true_dpram_sclk_461 | 148| +|112 | itlb_translate_regs |mor1kx_true_dpram_sclk_462 | 25| +|113 | mor1kx_lsu_cappuccino |mor1kx_lsu_cappuccino_443 | 1387| +|114 | \dcache_gen.mor1kx_dcache |mor1kx_dcache_449 | 800| +|115 | snoop_tag_ram |mor1kx_simple_dpram_sclk__parameterized3_455 | 375| +|116 | tag_ram |mor1kx_simple_dpram_sclk__parameterized4_456 | 191| +|117 | \way_memories[0].way_data_ram |mor1kx_simple_dpram_sclk__parameterized2_457 | 72| +|118 | \way_memories[1].way_data_ram |mor1kx_simple_dpram_sclk__parameterized2_458 | 23| +|119 | \dmmu_gen.mor1kx_dmmu |mor1kx_dmmu_450 | 240| +|120 | dtlb_match_regs |mor1kx_true_dpram_sclk_453 | 60| +|121 | dtlb_translate_regs |mor1kx_true_dpram_sclk_454 | 175| +|122 | \store_buffer_gen.mor1kx_store_buffer |mor1kx_store_buffer_451 | 162| +|123 | fifo_ram |mor1kx_simple_dpram_sclk__parameterized1_452 | 121| +|124 | mor1kx_rf_cappuccino |mor1kx_rf_cappuccino_444 | 734| +|125 | rfa |mor1kx_simple_dpram_sclk__parameterized5_446 | 33| +|126 | rfb |mor1kx_simple_dpram_sclk__parameterized5_447 | 33| +|127 | \rfspr_gen.rfspr |mor1kx_simple_dpram_sclk__parameterized5_448 | 1| +|128 | mor1kx_wb_mux_cappuccino |mor1kx_wb_mux_cappuccino_445 | 111| +|129 | led |gpo_412 | 2| +|130 | ni |ni_master_413 | 1017| +|131 | \multi_channel.receive_arbiter |bus_arbiter_419 | 11| +|132 | the_combinational_arbiter |arbiter_432 | 2| +|133 | \w4.one_hot_arb |my_one_hot_arbiter_433 | 2| +|134 | \multi_channel.send_arbiter |bus_arbiter_420 | 10| +|135 | the_combinational_arbiter |arbiter_430 | 2| +|136 | \w4.one_hot_arb |my_one_hot_arbiter_431 | 2| +|137 | \precap.vc__[0].precap_data_fifo |fwft_fifo__parameterized1_421 | 11| +|138 | \precap.vc__[1].precap_data_fifo |fwft_fifo__parameterized1_422 | 13| +|139 | the_ififo |flit_buffer_423 | 81| +|140 | \pow2.the_queue |fifo_ram_429 | 49| +|141 | the_ovc_status |ovc_status_424 | 15| +|142 | \vc_[0].vc_dma |ni_vc_dma_425 | 215| +|143 | \vc_[0].wb_slave_registers |ni_vc_wb_slave_regs_426 | 192| +|144 | \vc_[1].vc_dma |ni_vc_dma_427 | 213| +|145 | \vc_[1].wb_slave_registers |ni_vc_wb_slave_regs_428 | 222| +|146 | ram |wb_single_port_ram__parameterized0 | 291| +|147 | ctrl |wb_bram_ctrl_417 | 226| +|148 | \burst_wb.bram_ctrl |wb_burst_bram_ctrl_418 | 226| +|149 | ram_top |single_port_ram_top__parameterized0 | 65| +|150 | \xilinx_fpga.xilinx_dual.xpm_memory_tdpram_inst |xpm_memory_tdpram__parameterized0 | 64| +|151 | xpm_memory_base_inst |xpm_memory_base__parameterized0 | 64| +|152 | timer |timer_414 | 187| +|153 | uart |pronoc_jtag_uart__parameterized0 | 131| +|154 | uart_hw |pronoc_jtag_uart_hw__parameterized0 | 131| +|155 | jtag_to_wb_fifo |uart_fifo_415 | 57| +|156 | wb_to_jtag_fifo |uart_fifo_416 | 66| +|157 | the_mor1k_tile_2 |mor1k_tile__parameterized1 | 8205| +|158 | bus |wishbone_bus_349 | 561| +|159 | arbiter |bus_arbiter__parameterized0_407 | 561| +|160 | the_combinational_arbiter |arbiter__parameterized0_408 | 12| +|161 | \w4.one_hot_arb |my_one_hot_arbiter__parameterized0_409 | 12| +|162 | cpu |mor1k_350 | 6037| +|163 | mor1kx0 |mor1kx_373 | 5867| +|164 | mor1kx_cpu |mor1kx_cpu_374 | 5867| +|165 | \cappuccino.mor1kx_cpu |mor1kx_cpu_cappuccino_375 | 5865| +|166 | mor1kx_branch_prediction |mor1kx_branch_prediction_376 | 2| +|167 | mor1kx_ctrl_cappuccino |mor1kx_ctrl_cappuccino_377 | 827| +|168 | \pic.mor1kx_pic |mor1kx_pic_405 | 144| +|169 | \tt.mor1kx_ticktimer |mor1kx_ticktimer_406 | 118| +|170 | mor1kx_decode_execute_cappuccino |mor1kx_decode_execute_cappuccino_378 | 638| +|171 | mor1kx_execute_alu |mor1kx_execute_alu_379 | 297| +|172 | mor1kx_execute_ctrl_cappuccino |mor1kx_execute_ctrl_cappuccino_380 | 984| +|173 | mor1kx_fetch_cappuccino |mor1kx_fetch_cappuccino_381 | 910| +|174 | \icache_gen.mor1kx_icache |mor1kx_icache_398 | 296| +|175 | tag_ram |mor1kx_simple_dpram_sclk__parameterized0_402 | 130| +|176 | \way_memories[0].way_data_ram |mor1kx_simple_dpram_sclk_403 | 15| +|177 | \way_memories[1].way_data_ram |mor1kx_simple_dpram_sclk_404 | 42| +|178 | \immu_gen.mor1kx_immu |mor1kx_immu_399 | 236| +|179 | itlb_match_regs |mor1kx_true_dpram_sclk_400 | 166| +|180 | itlb_translate_regs |mor1kx_true_dpram_sclk_401 | 25| +|181 | mor1kx_lsu_cappuccino |mor1kx_lsu_cappuccino_382 | 1362| +|182 | \dcache_gen.mor1kx_dcache |mor1kx_dcache_388 | 802| +|183 | snoop_tag_ram |mor1kx_simple_dpram_sclk__parameterized3_394 | 375| +|184 | tag_ram |mor1kx_simple_dpram_sclk__parameterized4_395 | 191| +|185 | \way_memories[0].way_data_ram |mor1kx_simple_dpram_sclk__parameterized2_396 | 72| +|186 | \way_memories[1].way_data_ram |mor1kx_simple_dpram_sclk__parameterized2_397 | 23| +|187 | \dmmu_gen.mor1kx_dmmu |mor1kx_dmmu_389 | 241| +|188 | dtlb_match_regs |mor1kx_true_dpram_sclk_392 | 60| +|189 | dtlb_translate_regs |mor1kx_true_dpram_sclk_393 | 176| +|190 | \store_buffer_gen.mor1kx_store_buffer |mor1kx_store_buffer_390 | 162| +|191 | fifo_ram |mor1kx_simple_dpram_sclk__parameterized1_391 | 121| +|192 | mor1kx_rf_cappuccino |mor1kx_rf_cappuccino_383 | 734| +|193 | rfa |mor1kx_simple_dpram_sclk__parameterized5_385 | 33| +|194 | rfb |mor1kx_simple_dpram_sclk__parameterized5_386 | 33| +|195 | \rfspr_gen.rfspr |mor1kx_simple_dpram_sclk__parameterized5_387 | 1| +|196 | mor1kx_wb_mux_cappuccino |mor1kx_wb_mux_cappuccino_384 | 111| +|197 | led |gpo_351 | 2| +|198 | ni |ni_master_352 | 1023| +|199 | \multi_channel.receive_arbiter |bus_arbiter_358 | 11| +|200 | the_combinational_arbiter |arbiter_371 | 2| +|201 | \w4.one_hot_arb |my_one_hot_arbiter_372 | 2| +|202 | \multi_channel.send_arbiter |bus_arbiter_359 | 39| +|203 | the_combinational_arbiter |arbiter_369 | 2| +|204 | \w4.one_hot_arb |my_one_hot_arbiter_370 | 2| +|205 | \precap.vc__[0].precap_data_fifo |fwft_fifo__parameterized1_360 | 13| +|206 | \precap.vc__[1].precap_data_fifo |fwft_fifo__parameterized1_361 | 15| +|207 | the_ififo |flit_buffer_362 | 72| +|208 | \pow2.the_queue |fifo_ram_368 | 42| +|209 | the_ovc_status |ovc_status_363 | 16| +|210 | \vc_[0].vc_dma |ni_vc_dma_364 | 224| +|211 | \vc_[0].wb_slave_registers |ni_vc_wb_slave_regs_365 | 193| +|212 | \vc_[1].vc_dma |ni_vc_dma_366 | 217| +|213 | \vc_[1].wb_slave_registers |ni_vc_wb_slave_regs_367 | 191| +|214 | ram |wb_single_port_ram__parameterized1 | 291| +|215 | ctrl |wb_bram_ctrl_356 | 226| +|216 | \burst_wb.bram_ctrl |wb_burst_bram_ctrl_357 | 226| +|217 | ram_top |single_port_ram_top__parameterized1 | 65| +|218 | \xilinx_fpga.xilinx_dual.xpm_memory_tdpram_inst |xpm_memory_tdpram__parameterized1 | 64| +|219 | xpm_memory_base_inst |xpm_memory_base__parameterized1 | 64| +|220 | timer |timer_353 | 153| +|221 | uart |pronoc_jtag_uart__parameterized1 | 138| +|222 | uart_hw |pronoc_jtag_uart_hw__parameterized1 | 138| +|223 | jtag_to_wb_fifo |uart_fifo_354 | 70| +|224 | wb_to_jtag_fifo |uart_fifo_355 | 57| +|225 | the_mor1k_tile_3 |mor1k_tile__parameterized2 | 8183| +|226 | bus |wishbone_bus | 474| +|227 | arbiter |bus_arbiter__parameterized0 | 474| +|228 | the_combinational_arbiter |arbiter__parameterized0_347 | 2| +|229 | \w4.one_hot_arb |my_one_hot_arbiter__parameterized0_348 | 2| +|230 | cpu |mor1k | 6061| +|231 | mor1kx0 |mor1kx | 5889| +|232 | mor1kx_cpu |mor1kx_cpu | 5889| +|233 | \cappuccino.mor1kx_cpu |mor1kx_cpu_cappuccino | 5887| +|234 | mor1kx_branch_prediction |mor1kx_branch_prediction | 2| +|235 | mor1kx_ctrl_cappuccino |mor1kx_ctrl_cappuccino | 827| +|236 | \pic.mor1kx_pic |mor1kx_pic | 144| +|237 | \tt.mor1kx_ticktimer |mor1kx_ticktimer | 118| +|238 | mor1kx_decode_execute_cappuccino |mor1kx_decode_execute_cappuccino | 638| +|239 | mor1kx_execute_alu |mor1kx_execute_alu | 297| +|240 | mor1kx_execute_ctrl_cappuccino |mor1kx_execute_ctrl_cappuccino | 984| +|241 | mor1kx_fetch_cappuccino |mor1kx_fetch_cappuccino | 908| +|242 | \icache_gen.mor1kx_icache |mor1kx_icache | 294| +|243 | tag_ram |mor1kx_simple_dpram_sclk__parameterized0 | 130| +|244 | \way_memories[0].way_data_ram |mor1kx_simple_dpram_sclk | 15| +|245 | \way_memories[1].way_data_ram |mor1kx_simple_dpram_sclk_346 | 42| +|246 | \immu_gen.mor1kx_immu |mor1kx_immu | 236| +|247 | itlb_match_regs |mor1kx_true_dpram_sclk_344 | 166| +|248 | itlb_translate_regs |mor1kx_true_dpram_sclk_345 | 25| +|249 | mor1kx_lsu_cappuccino |mor1kx_lsu_cappuccino | 1386| +|250 | \dcache_gen.mor1kx_dcache |mor1kx_dcache | 800| +|251 | snoop_tag_ram |mor1kx_simple_dpram_sclk__parameterized3 | 375| +|252 | tag_ram |mor1kx_simple_dpram_sclk__parameterized4 | 191| +|253 | \way_memories[0].way_data_ram |mor1kx_simple_dpram_sclk__parameterized2 | 72| +|254 | \way_memories[1].way_data_ram |mor1kx_simple_dpram_sclk__parameterized2_343 | 23| +|255 | \dmmu_gen.mor1kx_dmmu |mor1kx_dmmu | 239| +|256 | dtlb_match_regs |mor1kx_true_dpram_sclk | 61| +|257 | dtlb_translate_regs |mor1kx_true_dpram_sclk_342 | 173| +|258 | \store_buffer_gen.mor1kx_store_buffer |mor1kx_store_buffer | 162| +|259 | fifo_ram |mor1kx_simple_dpram_sclk__parameterized1 | 121| +|260 | mor1kx_rf_cappuccino |mor1kx_rf_cappuccino | 734| +|261 | rfa |mor1kx_simple_dpram_sclk__parameterized5 | 33| +|262 | rfb |mor1kx_simple_dpram_sclk__parameterized5_340 | 33| +|263 | \rfspr_gen.rfspr |mor1kx_simple_dpram_sclk__parameterized5_341 | 1| +|264 | mor1kx_wb_mux_cappuccino |mor1kx_wb_mux_cappuccino | 111| +|265 | led |gpo | 2| +|266 | ni |ni_master | 1028| +|267 | \multi_channel.receive_arbiter |bus_arbiter | 10| +|268 | the_combinational_arbiter |arbiter_338 | 2| +|269 | \w4.one_hot_arb |my_one_hot_arbiter_339 | 2| +|270 | \multi_channel.send_arbiter |bus_arbiter_330 | 8| +|271 | the_combinational_arbiter |arbiter_336 | 2| +|272 | \w4.one_hot_arb |my_one_hot_arbiter_337 | 2| +|273 | \precap.vc__[0].precap_data_fifo |fwft_fifo__parameterized1 | 11| +|274 | \precap.vc__[1].precap_data_fifo |fwft_fifo__parameterized1_331 | 13| +|275 | the_ififo |flit_buffer_332 | 81| +|276 | \pow2.the_queue |fifo_ram_335 | 49| +|277 | the_ovc_status |ovc_status | 15| +|278 | \vc_[0].vc_dma |ni_vc_dma | 226| +|279 | \vc_[0].wb_slave_registers |ni_vc_wb_slave_regs | 192| +|280 | \vc_[1].vc_dma |ni_vc_dma_333 | 214| +|281 | \vc_[1].wb_slave_registers |ni_vc_wb_slave_regs_334 | 224| +|282 | ram |wb_single_port_ram__parameterized2 | 291| +|283 | ctrl |wb_bram_ctrl | 226| +|284 | \burst_wb.bram_ctrl |wb_burst_bram_ctrl | 226| +|285 | ram_top |single_port_ram_top__parameterized2 | 65| +|286 | \xilinx_fpga.xilinx_dual.xpm_memory_tdpram_inst |xpm_memory_tdpram__parameterized2 | 64| +|287 | xpm_memory_base_inst |xpm_memory_base__parameterized2 | 64| +|288 | ss |clk_source | 17| +|289 | sync |altera_reset_synchronizer | 17| +|290 | timer |timer | 185| +|291 | uart |pronoc_jtag_uart__parameterized2 | 125| +|292 | uart_hw |pronoc_jtag_uart_hw__parameterized2 | 125| +|293 | jtag_to_wb_fifo |uart_fifo | 55| +|294 | wb_to_jtag_fifo |uart_fifo_329 | 61| +|295 | the_noc |noc | 4409| +|296 | \tori_noc.mesh_torus_noc |mesh_torus_noc | 4409| +|297 | \mesh_torus.y_loop[0].x_loop[0].the_router |router | 1108| +|298 | the_combined_vc_sw_alloc |combined_vc_sw_alloc_239 | 20| +|299 | \nonspec.cmb_v1.nonspec_comb |comb_nonspec_allocator_294 | 20| +|300 | nonspeculative_sw_allocator |nonspec_sw_alloc_295 | 14| +|301 | \port_loop[0].input_arbiter |swa_input_port_arbiter_308 | 1| +|302 | \rra_m.arbiter_ext_en.arb |arbiter_priority_en_327 | 1| +|303 | \w4.one_hot_arb |my_one_hot_arbiter_priority_en_328 | 1| +|304 | \port_loop[0].output_arbiter |swa_output_port_arbiter_309 | 2| +|305 | \rra_m.arb |arbiter__parameterized0_325 | 2| +|306 | \w4.one_hot_arb |my_one_hot_arbiter__parameterized0_326 | 2| +|307 | \port_loop[1].input_arbiter |swa_input_port_arbiter_310 | 1| +|308 | \rra_m.arbiter_ext_en.arb |arbiter_priority_en_323 | 1| +|309 | \w4.one_hot_arb |my_one_hot_arbiter_priority_en_324 | 1| +|310 | \port_loop[2].output_arbiter |swa_output_port_arbiter_311 | 5| +|311 | \rra_m.arb |arbiter__parameterized0_321 | 5| +|312 | \w4.one_hot_arb |my_one_hot_arbiter__parameterized0_322 | 5| +|313 | \port_loop[3].output_arbiter |swa_output_port_arbiter_312 | 2| +|314 | \rra_m.arb |arbiter__parameterized0_319 | 2| +|315 | \w4.one_hot_arb |my_one_hot_arbiter__parameterized0_320 | 2| +|316 | \port_loop[4].input_arbiter |swa_input_port_arbiter_313 | 1| +|317 | \rra_m.arbiter_ext_en.arb |arbiter_priority_en_317 | 1| +|318 | \w4.one_hot_arb |my_one_hot_arbiter_priority_en_318 | 1| +|319 | \port_loop[4].output_arbiter |swa_output_port_arbiter_314 | 2| +|320 | \rra_m.arb |arbiter__parameterized0_315 | 2| +|321 | \w4.one_hot_arb |my_one_hot_arbiter__parameterized0_316 | 2| +|322 | \total_vc_loop[0].ovc_arbiter |arbiter_296 | 1| +|323 | \w4.one_hot_arb |my_one_hot_arbiter_307 | 1| +|324 | \total_vc_loop[1].ovc_arbiter |arbiter_297 | 1| +|325 | \w4.one_hot_arb |my_one_hot_arbiter_306 | 1| +|326 | \total_vc_loop[2].ovc_arbiter |arbiter_298 | 1| +|327 | \w4.one_hot_arb |my_one_hot_arbiter_305 | 1| +|328 | \total_vc_loop[3].ovc_arbiter |arbiter_299 | 1| +|329 | \w4.one_hot_arb |my_one_hot_arbiter_304 | 1| +|330 | \total_vc_loop[8].ovc_arbiter |arbiter_300 | 1| +|331 | \w4.one_hot_arb |my_one_hot_arbiter_303 | 1| +|332 | \total_vc_loop[9].ovc_arbiter |arbiter_301 | 1| +|333 | \w4.one_hot_arb |my_one_hot_arbiter_302 | 1| +|334 | the_inout_ports |inout_ports_240 | 1082| +|335 | \noncanonical.the_credit_counter |credit_counter_241 | 204| +|336 | \PV_loop2[0].sw_mask |sw_mask_gen_288 | 2| +|337 | \PV_loop2[1].sw_mask |sw_mask_gen_289 | 2| +|338 | \PV_loop2[2].sw_mask |sw_mask_gen_290 | 2| +|339 | \PV_loop2[3].sw_mask |sw_mask_gen_291 | 2| +|340 | \PV_loop2[8].sw_mask |sw_mask_gen_292 | 9| +|341 | \PV_loop2[9].sw_mask |sw_mask_gen_293 | 26| +|342 | the_input_port |input_ports_242 | 858| +|343 | \port_loop[0].the_input_queue_per_port |input_queue_per_port_243 | 263| +|344 | \V_loop[0].dtrmn_dest.dest_fifo |fwft_fifo_278 | 54| +|345 | \V_loop[0].lk_dest_fifo |fwft_fifo_279 | 17| +|346 | \V_loop[0].tail_fifo |fwft_fifo__parameterized0_280 | 22| +|347 | \V_loop[1].dtrmn_dest.dest_fifo |fwft_fifo_281 | 48| +|348 | \V_loop[1].lk_dest_fifo |fwft_fifo_282 | 17| +|349 | \V_loop[1].tail_fifo |fwft_fifo__parameterized0_283 | 15| +|350 | lk_routing |look_ahead_routing_284 | 10| +|351 | \mesh_torus.look_ahead_route |mesh_torus_look_ahead_routing_287 | 10| +|352 | \nonspec.the_flit_buffer |flit_buffer_285 | 76| +|353 | \pow2.the_queue |fifo_ram_286 | 48| +|354 | \port_loop[1].the_input_queue_per_port |input_queue_per_port__parameterized0_244 | 308| +|355 | \V_loop[0].dtrmn_dest.dest_fifo |fwft_fifo_267 | 55| +|356 | \V_loop[0].lk_dest_fifo |fwft_fifo_268 | 16| +|357 | \V_loop[0].tail_fifo |fwft_fifo__parameterized0_269 | 19| +|358 | \V_loop[1].dtrmn_dest.dest_fifo |fwft_fifo_270 | 46| +|359 | \V_loop[1].lk_dest_fifo |fwft_fifo_271 | 16| +|360 | \V_loop[1].tail_fifo |fwft_fifo__parameterized0_272 | 17| +|361 | lk_routing |look_ahead_routing__parameterized0_273 | 11| +|362 | \mesh_torus.look_ahead_route |mesh_torus_look_ahead_routing__parameterized0_277 | 11| +|363 | \nonspec.the_flit_buffer |flit_buffer_274 | 114| +|364 | \pow2.the_queue |fifo_ram_276 | 84| +|365 | the_flit_update |header_flit_update_lk_route_ovc_275 | 10| +|366 | \port_loop[2].the_input_queue_per_port |input_queue_per_port__parameterized1_245 | 14| +|367 | \V_loop[0].dtrmn_dest.dest_fifo |fwft_fifo_262 | 3| +|368 | \V_loop[0].tail_fifo |fwft_fifo__parameterized0_263 | 1| +|369 | \V_loop[1].dtrmn_dest.dest_fifo |fwft_fifo_264 | 3| +|370 | \V_loop[1].tail_fifo |fwft_fifo__parameterized0_265 | 3| +|371 | \nonspec.the_flit_buffer |flit_buffer_266 | 4| +|372 | \port_loop[3].the_input_queue_per_port |input_queue_per_port__parameterized2_246 | 11| +|373 | \V_loop[0].tail_fifo |fwft_fifo__parameterized0_259 | 2| +|374 | \V_loop[1].tail_fifo |fwft_fifo__parameterized0_260 | 2| +|375 | \nonspec.the_flit_buffer |flit_buffer_261 | 7| +|376 | \port_loop[4].the_input_queue_per_port |input_queue_per_port__parameterized3_247 | 262| +|377 | \V_loop[0].dtrmn_dest.dest_fifo |fwft_fifo_248 | 18| +|378 | \V_loop[0].lk_dest_fifo |fwft_fifo_249 | 16| +|379 | \V_loop[0].tail_fifo |fwft_fifo__parameterized0_250 | 16| +|380 | \V_loop[1].dtrmn_dest.dest_fifo |fwft_fifo_251 | 37| +|381 | \V_loop[1].lk_dest_fifo |fwft_fifo_252 | 16| +|382 | \V_loop[1].tail_fifo |fwft_fifo__parameterized0_253 | 14| +|383 | lk_routing |look_ahead_routing__parameterized3_254 | 11| +|384 | \mesh_torus.look_ahead_route |mesh_torus_look_ahead_routing__parameterized3_258 | 11| +|385 | \nonspec.the_flit_buffer |flit_buffer_255 | 118| +|386 | \pow2.the_queue |fifo_ram_257 | 90| +|387 | the_flit_update |header_flit_update_lk_route_ovc_256 | 12| +|388 | \mesh_torus.y_loop[0].x_loop[1].the_router |router_0 | 1111| +|389 | the_combined_vc_sw_alloc |combined_vc_sw_alloc_151 | 22| +|390 | \nonspec.cmb_v1.nonspec_comb |comb_nonspec_allocator_204 | 22| +|391 | nonspeculative_sw_allocator |nonspec_sw_alloc_205 | 16| +|392 | \port_loop[0].input_arbiter |swa_input_port_arbiter_218 | 1| +|393 | \rra_m.arbiter_ext_en.arb |arbiter_priority_en_237 | 1| +|394 | \w4.one_hot_arb |my_one_hot_arbiter_priority_en_238 | 1| +|395 | \port_loop[0].output_arbiter |swa_output_port_arbiter_219 | 5| +|396 | \rra_m.arb |arbiter__parameterized0_235 | 5| +|397 | \w4.one_hot_arb |my_one_hot_arbiter__parameterized0_236 | 5| +|398 | \port_loop[1].output_arbiter |swa_output_port_arbiter_220 | 2| +|399 | \rra_m.arb |arbiter__parameterized0_233 | 2| +|400 | \w4.one_hot_arb |my_one_hot_arbiter__parameterized0_234 | 2| +|401 | \port_loop[2].output_arbiter |swa_output_port_arbiter_221 | 4| +|402 | \rra_m.arb |arbiter__parameterized0_231 | 4| +|403 | \w4.one_hot_arb |my_one_hot_arbiter__parameterized0_232 | 4| +|404 | \port_loop[3].input_arbiter |swa_input_port_arbiter_222 | 1| +|405 | \rra_m.arbiter_ext_en.arb |arbiter_priority_en_229 | 1| +|406 | \w4.one_hot_arb |my_one_hot_arbiter_priority_en_230 | 1| +|407 | \port_loop[4].input_arbiter |swa_input_port_arbiter_223 | 1| +|408 | \rra_m.arbiter_ext_en.arb |arbiter_priority_en_227 | 1| +|409 | \w4.one_hot_arb |my_one_hot_arbiter_priority_en_228 | 1| +|410 | \port_loop[4].output_arbiter |swa_output_port_arbiter_224 | 2| +|411 | \rra_m.arb |arbiter__parameterized0_225 | 2| +|412 | \w4.one_hot_arb |my_one_hot_arbiter__parameterized0_226 | 2| +|413 | \total_vc_loop[0].ovc_arbiter |arbiter_206 | 1| +|414 | \w4.one_hot_arb |my_one_hot_arbiter_217 | 1| +|415 | \total_vc_loop[1].ovc_arbiter |arbiter_207 | 1| +|416 | \w4.one_hot_arb |my_one_hot_arbiter_216 | 1| +|417 | \total_vc_loop[6].ovc_arbiter |arbiter_208 | 1| +|418 | \w4.one_hot_arb |my_one_hot_arbiter_215 | 1| +|419 | \total_vc_loop[7].ovc_arbiter |arbiter_209 | 1| +|420 | \w4.one_hot_arb |my_one_hot_arbiter_214 | 1| +|421 | \total_vc_loop[8].ovc_arbiter |arbiter_210 | 1| +|422 | \w4.one_hot_arb |my_one_hot_arbiter_213 | 1| +|423 | \total_vc_loop[9].ovc_arbiter |arbiter_211 | 1| +|424 | \w4.one_hot_arb |my_one_hot_arbiter_212 | 1| +|425 | the_inout_ports |inout_ports_152 | 1083| +|426 | \noncanonical.the_credit_counter |credit_counter_153 | 209| +|427 | \PV_loop2[0].sw_mask |sw_mask_gen_198 | 2| +|428 | \PV_loop2[1].sw_mask |sw_mask_gen_199 | 2| +|429 | \PV_loop2[6].sw_mask |sw_mask_gen_200 | 2| +|430 | \PV_loop2[7].sw_mask |sw_mask_gen_201 | 2| +|431 | \PV_loop2[8].sw_mask |sw_mask_gen_202 | 7| +|432 | \PV_loop2[9].sw_mask |sw_mask_gen_203 | 32| +|433 | the_input_port |input_ports_154 | 854| +|434 | \port_loop[0].the_input_queue_per_port |input_queue_per_port_155 | 262| +|435 | \V_loop[0].dtrmn_dest.dest_fifo |fwft_fifo_188 | 54| +|436 | \V_loop[0].lk_dest_fifo |fwft_fifo_189 | 17| +|437 | \V_loop[0].tail_fifo |fwft_fifo__parameterized0_190 | 21| +|438 | \V_loop[1].dtrmn_dest.dest_fifo |fwft_fifo_191 | 48| +|439 | \V_loop[1].lk_dest_fifo |fwft_fifo_192 | 17| +|440 | \V_loop[1].tail_fifo |fwft_fifo__parameterized0_193 | 15| +|441 | lk_routing |look_ahead_routing_194 | 10| +|442 | \mesh_torus.look_ahead_route |mesh_torus_look_ahead_routing_197 | 10| +|443 | \nonspec.the_flit_buffer |flit_buffer_195 | 76| +|444 | \pow2.the_queue |fifo_ram_196 | 48| +|445 | \port_loop[1].the_input_queue_per_port |input_queue_per_port__parameterized0_156 | 11| +|446 | \V_loop[0].tail_fifo |fwft_fifo__parameterized0_185 | 2| +|447 | \V_loop[1].tail_fifo |fwft_fifo__parameterized0_186 | 2| +|448 | \nonspec.the_flit_buffer |flit_buffer_187 | 7| +|449 | \port_loop[2].the_input_queue_per_port |input_queue_per_port__parameterized1_157 | 14| +|450 | \V_loop[0].dtrmn_dest.dest_fifo |fwft_fifo_180 | 3| +|451 | \V_loop[0].tail_fifo |fwft_fifo__parameterized0_181 | 1| +|452 | \V_loop[1].dtrmn_dest.dest_fifo |fwft_fifo_182 | 3| +|453 | \V_loop[1].tail_fifo |fwft_fifo__parameterized0_183 | 3| +|454 | \nonspec.the_flit_buffer |flit_buffer_184 | 4| +|455 | \port_loop[3].the_input_queue_per_port |input_queue_per_port__parameterized2_158 | 357| +|456 | \V_loop[0].dtrmn_dest.dest_fifo |fwft_fifo_169 | 52| +|457 | \V_loop[0].lk_dest_fifo |fwft_fifo_170 | 16| +|458 | \V_loop[0].tail_fifo |fwft_fifo__parameterized0_171 | 19| +|459 | \V_loop[1].dtrmn_dest.dest_fifo |fwft_fifo_172 | 52| +|460 | \V_loop[1].lk_dest_fifo |fwft_fifo_173 | 16| +|461 | \V_loop[1].tail_fifo |fwft_fifo__parameterized0_174 | 17| +|462 | lk_routing |look_ahead_routing__parameterized2_175 | 11| +|463 | \mesh_torus.look_ahead_route |mesh_torus_look_ahead_routing__parameterized2_179 | 11| +|464 | \nonspec.the_flit_buffer |flit_buffer_176 | 160| +|465 | \pow2.the_queue |fifo_ram_178 | 130| +|466 | the_flit_update |header_flit_update_lk_route_ovc_177 | 10| +|467 | \port_loop[4].the_input_queue_per_port |input_queue_per_port__parameterized3_159 | 210| +|468 | \V_loop[0].dtrmn_dest.dest_fifo |fwft_fifo_160 | 19| +|469 | \V_loop[0].lk_dest_fifo |fwft_fifo_161 | 16| +|470 | \V_loop[0].tail_fifo |fwft_fifo__parameterized0_162 | 17| +|471 | \V_loop[1].dtrmn_dest.dest_fifo |fwft_fifo_163 | 27| +|472 | \V_loop[1].lk_dest_fifo |fwft_fifo_164 | 16| +|473 | \V_loop[1].tail_fifo |fwft_fifo__parameterized0_165 | 15| +|474 | lk_routing |look_ahead_routing__parameterized3 | 11| +|475 | \mesh_torus.look_ahead_route |mesh_torus_look_ahead_routing__parameterized3 | 11| +|476 | \nonspec.the_flit_buffer |flit_buffer_166 | 73| +|477 | \pow2.the_queue |fifo_ram_168 | 44| +|478 | the_flit_update |header_flit_update_lk_route_ovc_167 | 12| +|479 | \mesh_torus.y_loop[1].x_loop[0].the_router |router_1 | 1099| +|480 | the_combined_vc_sw_alloc |combined_vc_sw_alloc_63 | 20| +|481 | \nonspec.cmb_v1.nonspec_comb |comb_nonspec_allocator_116 | 20| +|482 | nonspeculative_sw_allocator |nonspec_sw_alloc_117 | 14| +|483 | \port_loop[0].input_arbiter |swa_input_port_arbiter_130 | 1| +|484 | \rra_m.arbiter_ext_en.arb |arbiter_priority_en_149 | 1| +|485 | \w4.one_hot_arb |my_one_hot_arbiter_priority_en_150 | 1| +|486 | \port_loop[0].output_arbiter |swa_output_port_arbiter_131 | 2| +|487 | \rra_m.arb |arbiter__parameterized0_147 | 2| +|488 | \w4.one_hot_arb |my_one_hot_arbiter__parameterized0_148 | 2| +|489 | \port_loop[1].input_arbiter |swa_input_port_arbiter_132 | 1| +|490 | \rra_m.arbiter_ext_en.arb |arbiter_priority_en_145 | 1| +|491 | \w4.one_hot_arb |my_one_hot_arbiter_priority_en_146 | 1| +|492 | \port_loop[2].input_arbiter |swa_input_port_arbiter_133 | 1| +|493 | \rra_m.arbiter_ext_en.arb |arbiter_priority_en_143 | 1| +|494 | \w4.one_hot_arb |my_one_hot_arbiter_priority_en_144 | 1| +|495 | \port_loop[2].output_arbiter |swa_output_port_arbiter_134 | 2| +|496 | \rra_m.arb |arbiter__parameterized0_141 | 2| +|497 | \w4.one_hot_arb |my_one_hot_arbiter__parameterized0_142 | 2| +|498 | \port_loop[3].output_arbiter |swa_output_port_arbiter_135 | 2| +|499 | \rra_m.arb |arbiter__parameterized0_139 | 2| +|500 | \w4.one_hot_arb |my_one_hot_arbiter__parameterized0_140 | 2| +|501 | \port_loop[4].output_arbiter |swa_output_port_arbiter_136 | 5| +|502 | \rra_m.arb |arbiter__parameterized0_137 | 5| +|503 | \w4.one_hot_arb |my_one_hot_arbiter__parameterized0_138 | 5| +|504 | \total_vc_loop[0].ovc_arbiter |arbiter_118 | 1| +|505 | \w4.one_hot_arb |my_one_hot_arbiter_129 | 1| +|506 | \total_vc_loop[1].ovc_arbiter |arbiter_119 | 1| +|507 | \w4.one_hot_arb |my_one_hot_arbiter_128 | 1| +|508 | \total_vc_loop[2].ovc_arbiter |arbiter_120 | 1| +|509 | \w4.one_hot_arb |my_one_hot_arbiter_127 | 1| +|510 | \total_vc_loop[3].ovc_arbiter |arbiter_121 | 1| +|511 | \w4.one_hot_arb |my_one_hot_arbiter_126 | 1| +|512 | \total_vc_loop[4].ovc_arbiter |arbiter_122 | 1| +|513 | \w4.one_hot_arb |my_one_hot_arbiter_125 | 1| +|514 | \total_vc_loop[5].ovc_arbiter |arbiter_123 | 1| +|515 | \w4.one_hot_arb |my_one_hot_arbiter_124 | 1| +|516 | the_inout_ports |inout_ports_64 | 1073| +|517 | \noncanonical.the_credit_counter |credit_counter_65 | 215| +|518 | \PV_loop2[0].sw_mask |sw_mask_gen_110 | 2| +|519 | \PV_loop2[1].sw_mask |sw_mask_gen_111 | 2| +|520 | \PV_loop2[2].sw_mask |sw_mask_gen_112 | 2| +|521 | \PV_loop2[3].sw_mask |sw_mask_gen_113 | 2| +|522 | \PV_loop2[4].sw_mask |sw_mask_gen_114 | 26| +|523 | \PV_loop2[5].sw_mask |sw_mask_gen_115 | 8| +|524 | the_input_port |input_ports_66 | 838| +|525 | \port_loop[0].the_input_queue_per_port |input_queue_per_port_67 | 225| +|526 | \V_loop[0].dtrmn_dest.dest_fifo |fwft_fifo_100 | 38| +|527 | \V_loop[0].lk_dest_fifo |fwft_fifo_101 | 17| +|528 | \V_loop[0].tail_fifo |fwft_fifo__parameterized0_102 | 16| +|529 | \V_loop[1].dtrmn_dest.dest_fifo |fwft_fifo_103 | 26| +|530 | \V_loop[1].lk_dest_fifo |fwft_fifo_104 | 17| +|531 | \V_loop[1].tail_fifo |fwft_fifo__parameterized0_105 | 17| +|532 | lk_routing |look_ahead_routing_106 | 12| +|533 | \mesh_torus.look_ahead_route |mesh_torus_look_ahead_routing_109 | 12| +|534 | \nonspec.the_flit_buffer |flit_buffer_107 | 78| +|535 | \pow2.the_queue |fifo_ram_108 | 48| +|536 | \port_loop[1].the_input_queue_per_port |input_queue_per_port__parameterized0_68 | 345| +|537 | \V_loop[0].dtrmn_dest.dest_fifo |fwft_fifo_91 | 68| +|538 | \V_loop[0].lk_dest_fifo |fwft_fifo_92 | 17| +|539 | \V_loop[0].tail_fifo |fwft_fifo__parameterized0_93 | 16| +|540 | \V_loop[1].dtrmn_dest.dest_fifo |fwft_fifo_94 | 67| +|541 | \V_loop[1].lk_dest_fifo |fwft_fifo_95 | 17| +|542 | \V_loop[1].tail_fifo |fwft_fifo__parameterized0_96 | 18| +|543 | lk_routing |look_ahead_routing__parameterized0 | 9| +|544 | \mesh_torus.look_ahead_route |mesh_torus_look_ahead_routing__parameterized0 | 9| +|545 | \nonspec.the_flit_buffer |flit_buffer_97 | 108| +|546 | \pow2.the_queue |fifo_ram_99 | 78| +|547 | the_flit_update |header_flit_update_lk_route_ovc_98 | 21| +|548 | \port_loop[2].the_input_queue_per_port |input_queue_per_port__parameterized1_69 | 246| +|549 | \V_loop[0].dtrmn_dest.dest_fifo |fwft_fifo_80 | 20| +|550 | \V_loop[0].lk_dest_fifo |fwft_fifo_81 | 16| +|551 | \V_loop[0].tail_fifo |fwft_fifo__parameterized0_82 | 15| +|552 | \V_loop[1].dtrmn_dest.dest_fifo |fwft_fifo_83 | 19| +|553 | \V_loop[1].lk_dest_fifo |fwft_fifo_84 | 16| +|554 | \V_loop[1].tail_fifo |fwft_fifo__parameterized0_85 | 14| +|555 | lk_routing |look_ahead_routing__parameterized1_86 | 11| +|556 | \mesh_torus.look_ahead_route |mesh_torus_look_ahead_routing__parameterized1_90 | 11| +|557 | \nonspec.the_flit_buffer |flit_buffer_87 | 115| +|558 | \pow2.the_queue |fifo_ram_89 | 82| +|559 | the_flit_update |header_flit_update_lk_route_ovc_88 | 16| +|560 | \port_loop[3].the_input_queue_per_port |input_queue_per_port__parameterized2_70 | 10| +|561 | \V_loop[0].tail_fifo |fwft_fifo__parameterized0_77 | 2| +|562 | \V_loop[1].tail_fifo |fwft_fifo__parameterized0_78 | 2| +|563 | \nonspec.the_flit_buffer |flit_buffer_79 | 6| +|564 | \port_loop[4].the_input_queue_per_port |input_queue_per_port__parameterized3_71 | 12| +|565 | \V_loop[0].dtrmn_dest.dest_fifo |fwft_fifo_72 | 2| +|566 | \V_loop[0].tail_fifo |fwft_fifo__parameterized0_73 | 1| +|567 | \V_loop[1].dtrmn_dest.dest_fifo |fwft_fifo_74 | 2| +|568 | \V_loop[1].tail_fifo |fwft_fifo__parameterized0_75 | 3| +|569 | \nonspec.the_flit_buffer |flit_buffer_76 | 4| +|570 | \mesh_torus.y_loop[1].x_loop[1].the_router |router_2 | 1091| +|571 | the_combined_vc_sw_alloc |combined_vc_sw_alloc | 22| +|572 | \nonspec.cmb_v1.nonspec_comb |comb_nonspec_allocator | 22| +|573 | nonspeculative_sw_allocator |nonspec_sw_alloc | 16| +|574 | \port_loop[0].input_arbiter |swa_input_port_arbiter | 1| +|575 | \rra_m.arbiter_ext_en.arb |arbiter_priority_en_61 | 1| +|576 | \w4.one_hot_arb |my_one_hot_arbiter_priority_en_62 | 1| +|577 | \port_loop[0].output_arbiter |swa_output_port_arbiter | 5| +|578 | \rra_m.arb |arbiter__parameterized0_59 | 5| +|579 | \w4.one_hot_arb |my_one_hot_arbiter__parameterized0_60 | 5| +|580 | \port_loop[1].output_arbiter |swa_output_port_arbiter_48 | 2| +|581 | \rra_m.arb |arbiter__parameterized0_57 | 2| +|582 | \w4.one_hot_arb |my_one_hot_arbiter__parameterized0_58 | 2| +|583 | \port_loop[2].input_arbiter |swa_input_port_arbiter_49 | 1| +|584 | \rra_m.arbiter_ext_en.arb |arbiter_priority_en_55 | 1| +|585 | \w4.one_hot_arb |my_one_hot_arbiter_priority_en_56 | 1| +|586 | \port_loop[2].output_arbiter |swa_output_port_arbiter_50 | 2| +|587 | \rra_m.arb |arbiter__parameterized0_53 | 2| +|588 | \w4.one_hot_arb |my_one_hot_arbiter__parameterized0_54 | 2| +|589 | \port_loop[3].input_arbiter |swa_input_port_arbiter_51 | 1| +|590 | \rra_m.arbiter_ext_en.arb |arbiter_priority_en | 1| +|591 | \w4.one_hot_arb |my_one_hot_arbiter_priority_en | 1| +|592 | \port_loop[4].output_arbiter |swa_output_port_arbiter_52 | 4| +|593 | \rra_m.arb |arbiter__parameterized0 | 4| +|594 | \w4.one_hot_arb |my_one_hot_arbiter__parameterized0 | 4| +|595 | \total_vc_loop[0].ovc_arbiter |arbiter | 1| +|596 | \w4.one_hot_arb |my_one_hot_arbiter_47 | 1| +|597 | \total_vc_loop[1].ovc_arbiter |arbiter_38 | 1| +|598 | \w4.one_hot_arb |my_one_hot_arbiter_46 | 1| +|599 | \total_vc_loop[4].ovc_arbiter |arbiter_39 | 1| +|600 | \w4.one_hot_arb |my_one_hot_arbiter_45 | 1| +|601 | \total_vc_loop[5].ovc_arbiter |arbiter_40 | 1| +|602 | \w4.one_hot_arb |my_one_hot_arbiter_44 | 1| +|603 | \total_vc_loop[6].ovc_arbiter |arbiter_41 | 1| +|604 | \w4.one_hot_arb |my_one_hot_arbiter_43 | 1| +|605 | \total_vc_loop[7].ovc_arbiter |arbiter_42 | 1| +|606 | \w4.one_hot_arb |my_one_hot_arbiter | 1| +|607 | the_inout_ports |inout_ports | 1062| +|608 | \noncanonical.the_credit_counter |credit_counter | 217| +|609 | \PV_loop2[0].sw_mask |sw_mask_gen | 6| +|610 | \PV_loop2[1].sw_mask |sw_mask_gen_33 | 4| +|611 | \PV_loop2[4].sw_mask |sw_mask_gen_34 | 25| +|612 | \PV_loop2[5].sw_mask |sw_mask_gen_35 | 8| +|613 | \PV_loop2[6].sw_mask |sw_mask_gen_36 | 2| +|614 | \PV_loop2[7].sw_mask |sw_mask_gen_37 | 2| +|615 | the_input_port |input_ports | 825| +|616 | \port_loop[0].the_input_queue_per_port |input_queue_per_port | 204| +|617 | \V_loop[0].dtrmn_dest.dest_fifo |fwft_fifo_25 | 18| +|618 | \V_loop[0].lk_dest_fifo |fwft_fifo_26 | 17| +|619 | \V_loop[0].tail_fifo |fwft_fifo__parameterized0_27 | 14| +|620 | \V_loop[1].dtrmn_dest.dest_fifo |fwft_fifo_28 | 31| +|621 | \V_loop[1].lk_dest_fifo |fwft_fifo_29 | 17| +|622 | \V_loop[1].tail_fifo |fwft_fifo__parameterized0_30 | 16| +|623 | lk_routing |look_ahead_routing | 10| +|624 | \mesh_torus.look_ahead_route |mesh_torus_look_ahead_routing | 10| +|625 | \nonspec.the_flit_buffer |flit_buffer_31 | 77| +|626 | \pow2.the_queue |fifo_ram_32 | 48| +|627 | \port_loop[1].the_input_queue_per_port |input_queue_per_port__parameterized0 | 11| +|628 | \V_loop[0].tail_fifo |fwft_fifo__parameterized0_21 | 2| +|629 | \V_loop[1].dtrmn_dest.dest_fifo |fwft_fifo_22 | 1| +|630 | \V_loop[1].tail_fifo |fwft_fifo__parameterized0_23 | 2| +|631 | \nonspec.the_flit_buffer |flit_buffer_24 | 6| +|632 | \port_loop[2].the_input_queue_per_port |input_queue_per_port__parameterized1 | 251| +|633 | \V_loop[0].dtrmn_dest.dest_fifo |fwft_fifo_12 | 17| +|634 | \V_loop[0].lk_dest_fifo |fwft_fifo_13 | 16| +|635 | \V_loop[0].tail_fifo |fwft_fifo__parameterized0_14 | 15| +|636 | \V_loop[1].dtrmn_dest.dest_fifo |fwft_fifo_15 | 28| +|637 | \V_loop[1].lk_dest_fifo |fwft_fifo_16 | 16| +|638 | \V_loop[1].tail_fifo |fwft_fifo__parameterized0_17 | 15| +|639 | lk_routing |look_ahead_routing__parameterized1 | 11| +|640 | \mesh_torus.look_ahead_route |mesh_torus_look_ahead_routing__parameterized1 | 11| +|641 | \nonspec.the_flit_buffer |flit_buffer_18 | 117| +|642 | \pow2.the_queue |fifo_ram_20 | 84| +|643 | the_flit_update |header_flit_update_lk_route_ovc_19 | 12| +|644 | \port_loop[3].the_input_queue_per_port |input_queue_per_port__parameterized2 | 347| +|645 | \V_loop[0].dtrmn_dest.dest_fifo |fwft_fifo_5 | 63| +|646 | \V_loop[0].lk_dest_fifo |fwft_fifo_6 | 16| +|647 | \V_loop[0].tail_fifo |fwft_fifo__parameterized0_7 | 16| +|648 | \V_loop[1].dtrmn_dest.dest_fifo |fwft_fifo_8 | 68| +|649 | \V_loop[1].lk_dest_fifo |fwft_fifo_9 | 16| +|650 | \V_loop[1].tail_fifo |fwft_fifo__parameterized0_10 | 18| +|651 | lk_routing |look_ahead_routing__parameterized2 | 11| +|652 | \mesh_torus.look_ahead_route |mesh_torus_look_ahead_routing__parameterized2 | 11| +|653 | \nonspec.the_flit_buffer |flit_buffer_11 | 108| +|654 | \pow2.the_queue |fifo_ram | 78| +|655 | the_flit_update |header_flit_update_lk_route_ovc | 27| +|656 | \port_loop[4].the_input_queue_per_port |input_queue_per_port__parameterized3 | 12| +|657 | \V_loop[0].dtrmn_dest.dest_fifo |fwft_fifo | 2| +|658 | \V_loop[0].tail_fifo |fwft_fifo__parameterized0 | 1| +|659 | \V_loop[1].dtrmn_dest.dest_fifo |fwft_fifo_3 | 2| +|660 | \V_loop[1].tail_fifo |fwft_fifo__parameterized0_4 | 3| +|661 | \nonspec.the_flit_buffer |flit_buffer | 4| ++------+-------------------------------------------------------------+--------------------------------------------------+------+ +--------------------------------------------------------------------------------- + Index: server/kc07/run.sh =================================================================== --- server/kc07/run.sh (nonexistent) +++ server/kc07/run.sh (revision 48) @@ -0,0 +1,112 @@ +#!/bin/bash + +#remove address from make_project.tcl & program_board.tcl +#fix jtag_intfc.sh ~/mpsoc/jtag_xilinx_xsct/jtag_xilinx_xsct + +source "my_password.sh" + +remote_folder="kc07_mesh6" +source_path="$PRONOC_WORK/MPSOC/kc07_mesh6" +ProNoC_HOME="../../.." + +echo "$PRONOC_WORK" + + +function check_fpga_exist_on_server { + xsct + connect + jtag targets +} + + + +my_array=("$source_path/src_verilog " + "$source_path/sw " + "$source_path/xilinx_compile " + "$source_path/xilinx_mem " + "$source_path/*.tcl " + "$source_path/*.xdc ") + + + + + +function copy_sources_all { + sshpass -p $my_passwd ssh $my_server mkdir -p "~/mpsoc/$remote_folder" + echo "copy $source_all on server" + #sshpass -p $my_passwd scp -r $source_all "$my_server:mpsoc/" + for i in "${my_array[@]}"; do + echo "copy $i on server" + sshpass -p $my_passwd scp -r $i "$my_server:mpsoc/$remote_folder/" + done + copy_uart_terminal +} + + +function copy_sources_sw { + echo "copy $source_path/sw on server" + sshpass -p $my_passwd scp -r "$source_path/sw" "$my_server:mpsoc/$remote_folder/" +} + +function copy_uart_terminal { + echo "copy uart_terminal on server" + sshpass -p $my_passwd scp -r "${ProNoC_HOME}/src_c/jtag/uart_xsct_terminal" "$my_server:mpsoc/" + sshpass -p $my_passwd scp -r "${ProNoC_HOME}/src_c/jtag/jtag_xilinx_xsct" "$my_server:mpsoc/" + +} + + +function copy_board_files { + echo "copy board files" + sshpass -p $my_passwd scp -r "$PRONOC_WORK/toolchain/board_files" "$my_server:mpsoc/" + # update board_part_repo_paths manulay in $my_server:mpsoc/$remote_folder/board_property.tcl file with new addr: " /mnt/SSD-2TB/alireza/mpsoc/board_files " +} + + +function update_jtag_xilinx_xsct { + # should be run inside the server + cd ~/mpsoc/jtag_xilinx_xsct/; make + cp ~/mpsoc/jtag_xilinx_xsct/jtag_xilinx_xsct ~/toolchain/bin/ + cd ~/mpsoc/uart_xsct_terminal/; make + cp ~/mpsoc/uart_xsct_terminal/uart ~/toolchain/bin/ +} + +#should be run in server folder +function compile_vivado { + vivado -mode tcl -source make_project.tcl +} + +function program_fpga { + cd ~/mpsoc/kc07_mesh6/ + vivado -mode tcl -source program_board.tcl +} + + +function run_uart { + cd ~/toolchain/bin + ./uart -a 2 -b 36 -t 3 -n 126,125,124,123,122,121,120,119,118,117,116,115 + +} + +function program_cpus { + cd ~/mpsoc/kc07_mesh12/sw + +} + + +function copy_back_from_server { + echo "copy back xilinx_compile to $source_path" + sshpass -p $my_passwd scp -r "$my_server:mpsoc/$remote_folder/xilinx_compile/*" "$source_path/xilinx_compile/" +} + +copy_sources_all + + +# copy_board_files + +#copy_back_from_server + +#copy_uart_terminal + +#copy_sources_sw +
server/kc07/run.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: server/smart-netrace/config =================================================================== --- server/smart-netrace/config (nonexistent) +++ server/smart-netrace/config (revision 48) @@ -0,0 +1,36 @@ + + + +#install perl locally on the server +#select a srever which has following file +ls /opt/rh/devtoolset-7/root/usr/bin/make + + +#1-go to https://www.cpan.org/src/ + + wget https://www.cpan.org/src/5.0/perl-5.34.0.tar.gz + tar -xzf perl-5.34.0.tar.gz + cd perl-5.34.0 + ./Configure -des -Dprefix=$HOME/localperl + make + make test + make install + + +#2- + perl -MCPAN -e shell + o conf makepl_arg INSTALL_BASE=~/localperl + o conf commit + + install String::Similarity + install CPAN::DistnameInfo + install Test::utf8 + install Try::Tiny + install Test::Fatal + install Test::MockRandom + install File::Copy::Recursive File::Find::Rule constant::boolean Class::Accessor::Fast Proc::Background List::MoreUtils + install IPC::Run + + + + Index: server/smart-netrace/report_old =================================================================== --- server/smart-netrace/report_old (nonexistent) +++ server/smart-netrace/report_old (revision 48) @@ -0,0 +1,87 @@ +Verification Results: +****************************custom1_topology : Compile *******************************: + model generation is FAILED. + make: *** [/opt/verilator/share/verilator/include/verilated.mk:235: testbench.o] Error 1 + +****************************Fattree_k3_L3_st : Compile *******************************: + model is generated successfully. +****************************fmesh_1x1_openpiton : Compile *******************************: + model is generated successfully. +****************************fmesh_2x2_openpiton : Compile *******************************: + model is generated successfully. +****************************fmesh_8x8_2cycle_xy : Compile *******************************: + model is generated successfully. +****************************mesh_2x2_openpiton : Compile *******************************: + model is generated successfully. +****************************mesh_4x4x3_2cycle_xy : Compile *******************************: + model is generated successfully. +****************************mesh_8x8_2cycle_adaptive : Compile *******************************: + model is generated successfully. +****************************mesh_8x8_2cycle_west_first : Compile *******************************: + model is generated successfully. +****************************mesh_8x8_2cycle_xy : Compile *******************************: + model is generated successfully. +****************************mesh_8x8_b2 : Compile *******************************: + model is generated successfully. +****************************mesh_8x8_sbp6_xy : Compile *******************************: + model is generated successfully. +****************************mesh_8x8_ssa_xy : Compile *******************************: + model is generated successfully. +****************************torus_8x8_2cycle_xy : Compile *******************************: + model is generated successfully. +****************************custom1_topology : random traffic *******************************: + failed. Simulation model is not avaialable +****************************Fattree_k3_L3_st : random traffic *******************************: + Passed: zero load (2,13.657638) saturation (62,121.906154) +****************************fmesh_1x1_openpiton : random traffic *******************************: + Passed: zero load (6,7.283544) saturation (62,47.952866) +****************************fmesh_2x2_openpiton : random traffic *******************************: + Passed: zero load (2,8.446429) saturation (46,78.861712) +****************************fmesh_8x8_2cycle_xy : random traffic *******************************: + Passed: zero load (2,19.554508) saturation (18,155.581334) +****************************mesh_2x2_openpiton : random traffic *******************************: + Passed: zero load (6,9.340102) saturation (62,118.703556) +****************************mesh_4x4x3_2cycle_xy : random traffic *******************************: + Passed: zero load (2,12.745953) saturation (22,66.615217) +****************************mesh_8x8_2cycle_adaptive : random traffic *******************************: + Passed: zero load (2,17.839302) saturation (34,251.244891) +****************************mesh_8x8_2cycle_west_first : random traffic *******************************: + Passed: zero load (2,17.847107) saturation (34,187.292574) +****************************mesh_8x8_2cycle_xy : random traffic *******************************: + Passed: zero load (2,17.850781) saturation (34,182.910213) +****************************mesh_8x8_b2 : random traffic *******************************: + Passed: zero load (2,22.376696) saturation (26,162.042382) +****************************mesh_8x8_sbp6_xy : random traffic *******************************: + Passed: zero load (2,10.914141) saturation (34,154.838619) +****************************mesh_8x8_ssa_xy : random traffic *******************************: + Passed: zero load (2,14.460973) saturation (34,160.415994) +****************************torus_8x8_2cycle_xy : random traffic *******************************: + Passed: zero load (2,16.560606) saturation (38,167.524583) +****************************custom1_topology : transposed 1 traffic *******************************: + failed. Simulation model is not avaialable +****************************Fattree_k3_L3_st : transposed 1 traffic *******************************: + Passed: zero load (6,13.435701) saturation (100,-) +****************************fmesh_1x1_openpiton : transposed 1 traffic *******************************: + Passed: zero load (50,6.989811) saturation (100,-) +****************************fmesh_2x2_openpiton : transposed 1 traffic *******************************: + Passed: zero load (2,9.557895) saturation (42,56.488636) +****************************fmesh_8x8_2cycle_xy : transposed 1 traffic *******************************: + Passed: zero load (2,21.649798) saturation (14,162.411596) +****************************mesh_2x2_openpiton : transposed 1 traffic *******************************: + Passed: zero load (2,8.597222) saturation (100,-) +****************************mesh_4x4x3_2cycle_xy : transposed 1 traffic *******************************: + Passed: zero load (2,12.888742) saturation (14,182.267303) +****************************mesh_8x8_2cycle_adaptive : transposed 1 traffic *******************************: + Passed: zero load (2,19.576862) saturation (26,139.040209) +****************************mesh_8x8_2cycle_west_first : transposed 1 traffic *******************************: + Passed: zero load (2,19.552562) saturation (22,108.231955) +****************************mesh_8x8_2cycle_xy : transposed 1 traffic *******************************: + Passed: zero load (2,19.565240) saturation (18,136.996558) +****************************mesh_8x8_b2 : transposed 1 traffic *******************************: + Passed: zero load (2,23.801373) saturation (18,145.991281) +****************************mesh_8x8_sbp6_xy : transposed 1 traffic *******************************: + Passed: zero load (2,11.445325) saturation (18,130.270034) +****************************mesh_8x8_ssa_xy : transposed 1 traffic *******************************: + Passed: zero load (2,15.634971) saturation (18,129.591605) +****************************torus_8x8_2cycle_xy : transposed 1 traffic *******************************: + Passed: zero load (2,18.048072) saturation (18,175.375388) Index: server/smart-netrace/run.sh =================================================================== --- server/smart-netrace/run.sh (nonexistent) +++ server/smart-netrace/run.sh (revision 48) @@ -0,0 +1,99 @@ +#!/bin/bash + +#the max server load that is permited for runing the parallel test +max_allowed_server_load=35 +source "my_password.sh" # define servers and passwords + +SCRPT_FULL_PATH=$(realpath ${BASH_SOURCE[0]}) +SCRPT_DIR_PATH=$(dirname $SCRPT_FULL_PATH) + + + + + +#servers=( $server1 $server2 $server3 ) # an array which define the list of servers +my_server="to be selected" +SERVER_ROOT_DIR="~/pronoc_verify" + +ProNoC="../../.." + +my_srcs=( "rtl" + "smart-netrace" + "src_verilator" + "src_c/netrace-1.0" + "script" + "/perl_gui/lib/perl" ) + + +rm "$SCRPT_DIR_PATH/report" + + + + +#copy_sources +#login_in_server + +#step one login in tje server and read the load +function get_server_avg_load { + out=$(sshpass -p $my_passwd ssh -t -o "StrictHostKeyChecking no" $1 "uptime") + load_avg=$(grep -oP '(?<=load average: )[0-9]+' <<< $out) +} + + +function select_a_server { + min_load="100" + + for i in "${servers[@]}"; do + echo "get load average on $i server" + get_server_avg_load $i + echo $load_avg + if [ $min_load -gt $load_avg ] + then + min_load=$load_avg + my_server=$i + fi + done + if [ $min_load -gt $max_allowed_server_load ] + then + echo "All servers are busy. Cannot continue" + exit + fi + echo "server $my_server is selected for running the test" +} + + +function copy_sources { + sshpass -p $my_passwd ssh -o "StrictHostKeyChecking no" $my_server rm -rf ${SERVER_ROOT_DIR} + sshpass -p $my_passwd ssh -o "StrictHostKeyChecking no" $my_server mkdir -p "${SERVER_ROOT_DIR}/mpsoc/perl_gui/lib/" + sshpass -p $my_passwd ssh -o "StrictHostKeyChecking no" $my_server mkdir -p "${SERVER_ROOT_DIR}/mpsoc/src_c/" + sshpass -p $my_passwd ssh -o "StrictHostKeyChecking no" $my_server mkdir -p "${SERVER_ROOT_DIR}/mpsoc_work" + for i in "${my_srcs[@]}"; do + echo "Copy $i on the server" + sshpass -p $my_passwd scp -o "StrictHostKeyChecking no" -r "$ProNoC/$i" "$my_server:${SERVER_ROOT_DIR}/mpsoc/$i" + done + sshpass -p $my_passwd scp -o "StrictHostKeyChecking no" -r "$SCRPT_DIR_PATH/server_run.sh" "$my_server:${SERVER_ROOT_DIR}/mpsoc/smart-netrace/server_run.sh" +} + + +function run_test { + cmd="export PRONOC_WORK=${SERVER_ROOT_DIR}/mpsoc_work;" + sshpass -p $my_passwd ssh -t -o "StrictHostKeyChecking no" $my_server $cmd + +} + +#setps to run the verrification + +#1 +select_a_server +#2 +copy_sources +#3 run the test + +sshpass -p $my_passwd ssh -o "StrictHostKeyChecking no" $my_server "cd ${SERVER_ROOT_DIR}/mpsoc/smart-netrace; source \"/etc/profile\"; bash server_run.sh;" + +#collect the report +rm "$SCRPT_DIR_PATH/report" +sshpass -p $my_passwd scp -o "StrictHostKeyChecking no" -r "$my_server:${SERVER_ROOT_DIR}/mpsoc/smart-netrace/report" "$SCRPT_DIR_PATH/report" +wait +gedit "$SCRPT_DIR_PATH/report" +
server/smart-netrace/run.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: server/smart-netrace/server_bashrc =================================================================== --- server/smart-netrace/server_bashrc (nonexistent) +++ server/smart-netrace/server_bashrc (revision 48) @@ -0,0 +1,8 @@ +export PATH=$HOME/localperl:$PATH +export PERL_LOCAL_LIB_ROOT="$HOME/localperl" +export PERL_MB_OPT="--install_base $HOME/localperl" +export PERL_MM_OPT="INSTALL_BASE=$HOME/localperl" +export PERL5LIB=$HOME/localperl/lib/5.34.0:$HOME/localperl/lib/perl5:$PERL5LIB +export localperl=/$HOME/localperl/bin/perl + + Index: server/smart-netrace/server_run.sh =================================================================== --- server/smart-netrace/server_run.sh (nonexistent) +++ server/smart-netrace/server_run.sh (revision 48) @@ -0,0 +1,23 @@ +#!/bin/bash + +source "/etc/profile" + + SCRPT_FULL_PATH=$(realpath ${BASH_SOURCE[0]}) + SCRPT_DIR_PATH=$(dirname $SCRPT_FULL_PATH) + +echo "\$SCRPT_DIR_PATH is $SCRPT_DIR_PATH" + +export PRONOC_WORK=$SCRPT_DIR_PATH/../../mpsoc_work +export PATH=$PATH:/opt/verilator/bin +source "/eda/env.sh" + + + + +home=$(eval echo ~$USER) +source "$home/.bash_profile" + +$localperl ./verify.perl "20" "2" "80" "4" + + +
server/smart-netrace/server_run.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: server/smart-netrace/server_run2.sh =================================================================== --- server/smart-netrace/server_run2.sh (nonexistent) +++ server/smart-netrace/server_run2.sh (revision 48) @@ -0,0 +1,55 @@ +#!/bin/bash +SCRPT_FULL_PATH=$(realpath ${BASH_SOURCE[0]}) +SCRPT_DIR_PATH=$(dirname $SCRPT_FULL_PATH) + +models_dir="$HOME/pronoc_verify/mpsoc_work/verify/work" + + + +#get the list of models and traces +models=() +traces=() +for model in $models_dir/*/; do + name="$(basename "$model")" + models+=("$name") +done + +for trace in $SCRPT_DIR_PATH/trace/*; do + traces+=("$trace") +echo $trace +done + + + + + +echo "step 1 copy bin files from $models_dir" +for model in ${models[@]} +do + cp "$models_dir/$model/obj_dir/testbench" "$SCRPT_DIR_PATH/models/$model" +done + + + +cd "$SCRPT_DIR_PATH/models" + +echo "step 2 run each trace for all models in parallel $models_dir" +for trace in ${traces[@]} +do + name="$(basename "$trace")" + mkdir -p $SCRPT_DIR_PATH/results/$name + + + echo "run simulation on $trace" + for model in ${models[@]} + do + cmd="./$model -v 0 -F $trace -T 4 -n 2000000 -r 2" + result=$SCRPT_DIR_PATH/results/$name/$model + echo $cmd + stdbuf -o0 $cmd 2>&1 | tee $result & + + done + + wait; + exit +done Index: verilator_compile_hw.sh =================================================================== --- verilator_compile_hw.sh (revision 45) +++ verilator_compile_hw.sh (revision 48) @@ -1,8 +1,8 @@ #!/bin/bash script_path=$(pwd) path=$script_path/.. -src_noc_path=$path/src_noc -src_modelsim_path=$path/src_modelsim +src_noc_path=$path/rtl/src_noc +src_modelsim_path=$path/rtl/src_modelsim src_verilator_path=$path/src_verilator comp_path=$path/../mpsoc_work/verilator work_path=$comp_path/work Index: verilator_compile_simulator.sh =================================================================== --- verilator_compile_simulator.sh (revision 45) +++ verilator_compile_simulator.sh (revision 48) @@ -5,8 +5,8 @@ script_path=$(pwd) path=$script_path/.. -src_noc_path=$path/src_noc -src_modelsim_path=$path/src_modelsim +src_noc_path=$path/rtl/src_noc +src_modelsim_path=$path/rtl/src_modelsim src_verilator_path=$path/src_verilator comp_path=$path/../mpsoc_work/verilator work_path=$comp_path/work
/verilator_compile_sw.sh
5,8 → 5,8
 
script_path=$(pwd)
path=$script_path/..
src_noc_path=$path/src_noc
src_modelsim_path=$path/src_modelsim
src_noc_path=$path/rtl/src_noc
src_modelsim_path=$path/rtl/src_modelsim
src_verilator_path=$path/src_verilator
comp_path=$path/../mpsoc_work/verilator
work_path=$comp_path/work
/verilator_lint.sh
0,0 → 1,4
#!/bin/bash
echo "filelist: $1";
export workspace_loc="$1/../.."
verilator --lint-only --cc --top-module "noc" --profile-cfuncs --prefix "Vnoc" -O3 -CFLAGS -O3 -f $1/noc_files.f -y ${workspace_loc}/mpsoc/rtl/src_noc/
verilator_lint.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: verilator_run_simulation.sh =================================================================== --- verilator_run_simulation.sh (revision 45) +++ verilator_run_simulation.sh (revision 48) @@ -5,8 +5,8 @@ script_path=$(pwd) path=$script_path/.. -src_noc_path=$path/src_noc -src_modelsim_path=$path/src_modelsim +src_noc_path=$path/rtl/src_noc +src_modelsim_path=$path/rtl/src_modelsim src_verilator_path=$path/src_verilator comp_path=$path/../mpsoc_work/verilator work_path=$comp_path/work

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