OpenCores
URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk
    from Rev 27 to Rev 28
    ↔ Reverse comparison
  •

Rev 27 → Rev 28

/mpsoc/change.log
1,5 → 1,13
All notable changes to this project will be documented in this file.
 
 
##[1.5.1] - 3-2-2017
## changed
- src_c/jtag_main.c: variable length memory support is added.
- NoC emulator: Jtag tabs are reduced to total of 3. A 64 core 2-VC NoC emulation is sucessfully tested on DE4 FPGA board.
-ssa: Now can work with fully adaptive routing.
 
 
##[1.5.0] - 13-10-2016
### Added
- static straight allocator (SSA) which accelerates packets traversing to the same direction to the NoC router.
/mpsoc/perl_gui/ProNoC.pl
37,9 → 37,19
 
# check if envirement variables are defined
if ( !defined $ENV{PRONOC_WORK} || !defined $ENV{QUARTUS_BIN}) {
my $message;
$message= "Warning: QUARTUS_BIN environment variable has not been set. It is required only for working with NoC emulator." if(!defined $ENV{QUARTUS_BIN});
$message= $message."\n\nWarning: PRONOC_WORK envirement varibale has not been set." if(!defined $ENV{PRONOC_WORK});
my $message;
if ( !defined $ENV{PRONOC_WORK}) {
my $dir = Cwd::getcwd();
my $project_dir = abs_path("$dir/../../mpsoc_work");
$ENV{'PRONOC_WORK'}= $project_dir;
$message= "\n\nWarning: PRONOC_WORK envirement varibale has not been set. The PRONOC_WORK is autumatically set to $ENV{'PRONOC_WORK'}.\n";
}
 
 
$message= $message."Warning: QUARTUS_BIN environment variable has not been set. It is required only for working with NoC emulator." if(!defined $ENV{QUARTUS_BIN});
$message= $message."\n\nPlease add aformentioned variables to ~\.bashrc file e.g: export PRONOC_WORK=[path_to]/mpsoc_work.";
message_dialog("$message");
/mpsoc/perl_gui/doc/ProNoC_system_installation.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/mpsoc/perl_gui/lib/ip/RAM/dual_port_ram.IP
24,32 → 24,32
'deafult' => 'Dw/8',
'global_param' => 'Localparam',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
'type' => 'Fixed',
'redefine_param' => 1
},
'PORT_B_BURST_MODE' => {
'info' => 'wisbone bus burst mode ebable/disable on port B',
'deafult' => '"DISABLED"',
'global_param' => 'Don\'t include',
'content' => '"DISABLED","ENABLED" ',
'redefine_param' => 1,
'type' => 'Fixed'
},
'Dw' => {
'info' => 'Ram data width in Bits',
'deafult' => '32',
'global_param' => 'Localparam',
'content' => '4,1024,1',
'type' => 'Spin-button',
'redefine_param' => 1
'redefine_param' => 1,
'type' => 'Spin-button'
},
'PORT_B_BURST_MODE' => {
'info' => 'wisbone bus burst mode ebable/disable on port B',
'deafult' => '"DISABLED"',
'global_param' => 'Don\'t include',
'content' => '"DISABLED","ENABLED" ',
'type' => 'Combo-box',
'redefine_param' => 1
},
'BTEw' => {
'info' => 'Parameter',
'deafult' => '2',
'global_param' => 'Localparam',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
'type' => 'Fixed',
'redefine_param' => 1
},
'WB_Aw' => {
'info' => 'Wishbone bus address width in byte',
56,8 → 56,8
'deafult' => 'Aw+2',
'global_param' => 'Don\'t include',
'content' => '',
'type' => 'Fixed',
'redefine_param' => 0
'redefine_param' => 0,
'type' => 'Fixed'
},
'RAM_INDEX' => {
'info' => 'RAM_INDEX is a unique number which will be used for initialing the memory content only.
66,8 → 66,8
'deafult' => 'CORE_ID',
'global_param' => 'Localparam',
'content' => '',
'type' => 'Entry',
'redefine_param' => 1
'redefine_param' => 1,
'type' => 'Entry'
},
'Aw' => {
'info' => 'Ram address width',
74,8 → 74,8
'deafult' => '12',
'global_param' => 'Localparam',
'content' => '2,31,1',
'type' => 'Spin-button',
'redefine_param' => 1
'redefine_param' => 1,
'type' => 'Spin-button'
},
'TAGw' => {
'info' => 'Parameter',
82,32 → 82,32
'deafult' => '3',
'global_param' => 'Localparam',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
'type' => 'Fixed',
'redefine_param' => 1
},
'PORT_A_BURST_MODE' => {
'info' => ' wisbone bus burst mode enable/disable on port A',
'deafult' => '"DISABLED"',
'global_param' => 'Localparam',
'content' => '"DISABLED","ENABLED"',
'redefine_param' => 1,
'type' => 'Combo-box'
},
'BYTE_WR_EN' => {
'info' => 'Parameter',
'deafult' => '"YES"',
'global_param' => 'Localparam',
'content' => '"YES","NO"',
'type' => 'Combo-box',
'redefine_param' => 1
'redefine_param' => 1,
'type' => 'Combo-box'
},
'PORT_A_BURST_MODE' => {
'info' => ' wisbone bus burst mode enable/disable on port A',
'deafult' => '"DISABLED"',
'global_param' => 'Localparam',
'content' => '"DISABLED","ENABLED"',
'type' => 'Combo-box',
'redefine_param' => 1
},
'CTIw' => {
'info' => 'Parameter',
'deafult' => '3',
'global_param' => 'Localparam',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
'type' => 'Fixed',
'redefine_param' => 1
},
'FPGA_VENDOR' => {
'info' => 'Parameter',
114,31 → 114,31
'deafult' => '"ALTERA"',
'global_param' => 'Localparam',
'content' => '"ALTERA","GENERIC"',
'type' => 'Combo-box',
'redefine_param' => 1
'redefine_param' => 1,
'type' => 'Combo-box'
}
},
'gui_status' => {
'timeout' => 0,
'status' => 'ideal'
'status' => 'ideal',
'timeout' => 0
},
'plugs' => {
'clk' => {
'clk' => {},
'value' => 1,
'0' => {
'name' => 'clk'
},
'type' => 'num'
},
'reset' => {
'reset' => {},
'value' => 1,
'0' => {
'name' => 'reset'
},
'value' => 1,
'type' => 'num'
},
'clk' => {
'clk' => {},
'0' => {
'name' => 'clk'
},
'value' => 1,
'type' => 'num'
},
'wb_slave' => {
'1' => {
'width' => 'WB_Aw',
145,12 → 145,12
'name' => 'wb_b',
'addr' => '0x0000_0000 0x3fff_ffff RAM'
},
'value' => 2,
'0' => {
'width' => 'WB_Aw',
'name' => 'wb_a',
'addr' => '0x0000_0000 0x3fff_ffff RAM'
},
'value' => 2,
'type' => 'num',
'wb_slave' => {}
}
159,171 → 159,171
'wb_dual_port_ram' => {}
},
'ports' => {
'sb_addr_i' => {
'intfc_port' => 'adr_i',
'intfc_name' => 'plug:wb_slave[1]',
'range' => 'Aw-1 : 0',
'type' => 'input'
},
'sa_tag_i' => {
'intfc_port' => 'tag_i',
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'tag_i',
'range' => 'TAGw-1 : 0',
'type' => 'input'
},
'sb_addr_i' => {
'intfc_name' => 'plug:wb_slave[1]',
'intfc_port' => 'adr_i',
'range' => 'Aw-1 : 0',
'type' => 'input'
},
'sa_rty_o' => {
'intfc_port' => 'rty_o',
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'rty_o',
'range' => '',
'type' => 'output'
},
'sa_cti_i' => {
'sa_sel_i' => {
'intfc_port' => 'sel_i',
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'cti_i',
'range' => 'CTIw-1 : 0',
'range' => 'SELw-1 : 0',
'type' => 'input'
},
'sa_sel_i' => {
'sa_cti_i' => {
'intfc_port' => 'cti_i',
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'sel_i',
'range' => 'SELw-1 : 0',
'range' => 'CTIw-1 : 0',
'type' => 'input'
},
'sa_bte_i' => {
'intfc_port' => 'bte_i',
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'bte_i',
'range' => 'BTEw-1 : 0',
'type' => 'input'
},
'sa_err_o' => {
'intfc_port' => 'err_o',
'intfc_name' => 'plug:wb_slave[0]',
'range' => '',
'type' => 'output'
},
'sa_cyc_i' => {
'intfc_port' => 'cyc_i',
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'cyc_i',
'range' => '',
'type' => 'input'
},
'sb_err_o' => {
'intfc_port' => 'err_o',
'intfc_name' => 'plug:wb_slave[1]',
'intfc_port' => 'err_o',
'range' => '',
'type' => 'output'
},
'sa_err_o' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'err_o',
'range' => '',
'sb_dat_o' => {
'intfc_port' => 'dat_o',
'intfc_name' => 'plug:wb_slave[1]',
'range' => 'Dw-1 : 0',
'type' => 'output'
},
'sa_ack_o' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'ack_o',
'range' => '',
'type' => 'output'
},
'reset' => {
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
'intfc_port' => 'reset_i',
'range' => '',
'type' => 'input'
},
'sb_dat_o' => {
'intfc_name' => 'plug:wb_slave[1]',
'intfc_port' => 'dat_o',
'range' => 'Dw-1 : 0',
'sa_ack_o' => {
'intfc_port' => 'ack_o',
'intfc_name' => 'plug:wb_slave[0]',
'range' => '',
'type' => 'output'
},
'sb_cti_i' => {
'intfc_port' => 'cti_i',
'intfc_name' => 'plug:wb_slave[1]',
'intfc_port' => 'cti_i',
'range' => 'CTIw-1 : 0',
'type' => 'input'
},
'sb_bte_i' => {
'intfc_port' => 'bte_i',
'intfc_name' => 'plug:wb_slave[1]',
'intfc_port' => 'bte_i',
'range' => 'BTEw-1 : 0',
'type' => 'input'
},
'sa_addr_i' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'adr_i',
'range' => 'Aw-1 : 0',
'type' => 'input'
},
'sb_ack_o' => {
'sb_cyc_i' => {
'intfc_port' => 'cyc_i',
'intfc_name' => 'plug:wb_slave[1]',
'intfc_port' => 'ack_o',
'range' => '',
'type' => 'output'
'type' => 'input'
},
'sb_cyc_i' => {
'sb_ack_o' => {
'intfc_port' => 'ack_o',
'intfc_name' => 'plug:wb_slave[1]',
'intfc_port' => 'cyc_i',
'range' => '',
'type' => 'input'
'type' => 'output'
},
'sa_addr_i' => {
'intfc_port' => 'adr_i',
'intfc_name' => 'plug:wb_slave[0]',
'range' => 'Aw-1 : 0',
'type' => 'input'
},
'sb_rty_o' => {
'intfc_port' => 'rty_o',
'intfc_name' => 'plug:wb_slave[1]',
'intfc_port' => 'rty_o',
'range' => '',
'type' => 'output'
},
'sb_dat_i' => {
'intfc_port' => 'dat_i',
'intfc_name' => 'plug:wb_slave[1]',
'intfc_port' => 'dat_i',
'range' => 'Dw-1 : 0',
'type' => 'input'
},
'sa_dat_o' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'dat_o',
'range' => 'Dw-1 : 0',
'type' => 'output'
},
'sb_we_i' => {
'intfc_port' => 'we_i',
'intfc_name' => 'plug:wb_slave[1]',
'intfc_port' => 'we_i',
'range' => '',
'type' => 'input'
},
'sa_dat_i' => {
'sa_dat_o' => {
'intfc_port' => 'dat_o',
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'dat_i',
'range' => 'Dw-1 : 0',
'type' => 'input'
'type' => 'output'
},
'sb_sel_i' => {
'intfc_port' => 'sel_i',
'intfc_name' => 'plug:wb_slave[1]',
'intfc_port' => 'sel_i',
'range' => 'SELw-1 : 0',
'type' => 'input'
},
'sa_dat_i' => {
'intfc_port' => 'dat_i',
'intfc_name' => 'plug:wb_slave[0]',
'range' => 'Dw-1 : 0',
'type' => 'input'
},
'sa_we_i' => {
'intfc_port' => 'we_i',
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'we_i',
'range' => '',
'type' => 'input'
},
'clk' => {
'intfc_port' => 'clk_i',
'intfc_name' => 'plug:clk[0]',
'intfc_port' => 'clk_i',
'range' => '',
'type' => 'input'
},
'sb_stb_i' => {
'sb_tag_i' => {
'intfc_port' => 'tag_i',
'intfc_name' => 'plug:wb_slave[1]',
'intfc_port' => 'stb_i',
'range' => '',
'range' => 'TAGw-1 : 0',
'type' => 'input'
},
'sb_tag_i' => {
'sb_stb_i' => {
'intfc_port' => 'stb_i',
'intfc_name' => 'plug:wb_slave[1]',
'intfc_port' => 'tag_i',
'range' => 'TAGw-1 : 0',
'range' => '',
'type' => 'input'
},
'sa_stb_i' => {
'intfc_port' => 'stb_i',
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'stb_i',
'range' => '',
'type' => 'input'
}
/mpsoc/perl_gui/lib/ip/RAM/single_port_ram.IP
126,7 → 126,7
},
'JTAG_CONNECT' => {
'info' => 'JTAG_CONNECT:
if it is not disabled then the actual memory implements as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb ',
if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. ',
'deafult' => '"DISABLED"',
'global_param' => 'Localparam',
'content' => '"DISABLED", "JTAG_WB" , "ALTERA_IMCE"',
141,6 → 141,14
'redefine_param' => 1,
'type' => 'Combo-box'
},
'INIT_FILE_NAME' => {
'info' => 'The name of RAM content memory file (without extention). The file will be used by the JTAG programer to programe the memory at run time.',
'deafult' => '"ram0"',
'global_param' => 'Don\'t include',
'content' => '',
'redefine_param' => 1,
'type' => 'Entry'
},
'CTIw' => {
'info' => 'Parameter',
'deafult' => '3',
170,7 → 178,8
'CTIw',
'BTEw',
'WB_Aw',
'BURST_MODE'
'BURST_MODE',
'INIT_FILE_NAME'
],
'ports' => {
'sa_tag_i' => {
/mpsoc/perl_gui/lib/mpsoc/mpsoc.MPSOC File deleted
/mpsoc/perl_gui/lib/mpsoc/lm32_noc.MPSOC
0,0 → 1,2607
#######################################################################
## File: lm32_noc.MPSOC
##
## Copyright (C) 2014-2016 Alireza Monemi
##
## This file is part of ProNoC 1.5.0
##
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
## MAY CAUSE UNEXPECTED BEHAIVOR.
################################################################################
 
$lm32_noc = bless( {
'socs' => {
'test' => {
'top' => bless( {
'ports' => {
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'intfc_name' => 'socket:ni[0]',
'range' => '',
'instance_name' => 'ni0',
'type' => 'output'
},
'ni_s_cti_i' => {
'intfc_port' => 'cti_i',
'intfc_name' => 'plug:wb_slave[0]',
'instance_name' => 'ni0',
'range' => 'ni_TAGw-1 : 0',
'type' => 'input'
},
'ni_s_cyc_i' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'cyc_i',
'instance_name' => 'ni0',
'range' => '',
'type' => 'input'
},
'ni_s_stb_i' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'stb_i',
'range' => '',
'instance_name' => 'ni0',
'type' => 'input'
},
'ni_s_sel_i' => {
'intfc_port' => 'sel_i',
'intfc_name' => 'plug:wb_slave[0]',
'instance_name' => 'ni0',
'range' => 'ni_SELw-1 : 0',
'type' => 'input'
},
'ni_current_y' => {
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'current_y',
'instance_name' => 'ni0',
'range' => 'ni_Yw-1 : 0',
'type' => 'input'
},
'ni_flit_in_wr' => {
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_in_wr',
'instance_name' => 'ni0',
'range' => '',
'type' => 'input'
},
'ni_credit_in' => {
'intfc_port' => 'credit_in',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni_V-1 : 0',
'type' => 'input'
},
'ni_s_ack_o' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'ack_o',
'instance_name' => 'ni0',
'range' => '',
'type' => 'output'
},
'ni_flit_in' => {
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_in',
'instance_name' => 'ni0',
'range' => 'ni_Fw-1 : 0',
'type' => 'input'
},
'ni_s_addr_i' => {
'intfc_port' => 'adr_i',
'intfc_name' => 'plug:wb_slave[0]',
'range' => 'ni_S_Aw-1 : 0',
'instance_name' => 'ni0',
'type' => 'input'
},
'ni_s_we_i' => {
'intfc_port' => 'we_i',
'intfc_name' => 'plug:wb_slave[0]',
'instance_name' => 'ni0',
'range' => '',
'type' => 'input'
},
'ni_current_x' => {
'intfc_port' => 'current_x',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni_Xw-1 : 0',
'type' => 'input'
},
'ni_s_rty_o' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'rty_o',
'range' => '',
'instance_name' => 'ni0',
'type' => 'output'
},
'ni_s_dat_o' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'dat_o',
'range' => 'ni_Dw-1 : 0',
'instance_name' => 'ni0',
'type' => 'output'
},
'ni_s_dat_i' => {
'intfc_port' => 'dat_i',
'intfc_name' => 'plug:wb_slave[0]',
'instance_name' => 'ni0',
'range' => 'ni_Dw-1 : 0',
'type' => 'input'
},
'ni_flit_out' => {
'intfc_port' => 'flit_out',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni_Fw-1 : 0',
'type' => 'output'
},
'ni_s_err_o' => {
'intfc_port' => 'err_o',
'intfc_name' => 'plug:wb_slave[0]',
'instance_name' => 'ni0',
'range' => '',
'type' => 'output'
},
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1: 0',
'instance_name' => 'ni0',
'type' => 'output'
}
},
'interface' => {
'socket:ni[0]' => {
'ports' => {
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'range' => '',
'instance_name' => 'ni0',
'type' => 'output'
},
'ni_current_x' => {
'intfc_port' => 'current_x',
'range' => 'ni_Xw-1 : 0',
'instance_name' => 'ni0',
'type' => 'input'
},
'ni_flit_out' => {
'intfc_port' => 'flit_out',
'range' => 'ni_Fw-1 : 0',
'instance_name' => 'ni0',
'type' => 'output'
},
'ni_current_y' => {
'intfc_port' => 'current_y',
'instance_name' => 'ni0',
'range' => 'ni_Yw-1 : 0',
'type' => 'input'
},
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'instance_name' => 'ni0',
'range' => 'ni_V-1: 0',
'type' => 'output'
},
'ni_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'range' => '',
'instance_name' => 'ni0',
'type' => 'input'
},
'ni_credit_in' => {
'intfc_port' => 'credit_in',
'instance_name' => 'ni0',
'range' => 'ni_V-1 : 0',
'type' => 'input'
},
'ni_flit_in' => {
'intfc_port' => 'flit_in',
'instance_name' => 'ni0',
'range' => 'ni_Fw-1 : 0',
'type' => 'input'
}
}
},
'plug:wb_slave[0]' => {
'ports' => {
'ni_s_rty_o' => {
'intfc_port' => 'rty_o',
'range' => '',
'instance_name' => 'ni0',
'type' => 'output'
},
'ni_s_cti_i' => {
'intfc_port' => 'cti_i',
'instance_name' => 'ni0',
'range' => 'ni_TAGw-1 : 0',
'type' => 'input'
},
'ni_s_cyc_i' => {
'intfc_port' => 'cyc_i',
'instance_name' => 'ni0',
'range' => '',
'type' => 'input'
},
'ni_s_dat_o' => {
'intfc_port' => 'dat_o',
'range' => 'ni_Dw-1 : 0',
'instance_name' => 'ni0',
'type' => 'output'
},
'ni_s_dat_i' => {
'intfc_port' => 'dat_i',
'range' => 'ni_Dw-1 : 0',
'instance_name' => 'ni0',
'type' => 'input'
},
'ni_s_stb_i' => {
'intfc_port' => 'stb_i',
'instance_name' => 'ni0',
'range' => '',
'type' => 'input'
},
'ni_s_err_o' => {
'intfc_port' => 'err_o',
'instance_name' => 'ni0',
'range' => '',
'type' => 'output'
},
'ni_s_sel_i' => {
'intfc_port' => 'sel_i',
'range' => 'ni_SELw-1 : 0',
'instance_name' => 'ni0',
'type' => 'input'
},
'ni_s_ack_o' => {
'intfc_port' => 'ack_o',
'range' => '',
'instance_name' => 'ni0',
'type' => 'output'
},
'ni_s_addr_i' => {
'intfc_port' => 'adr_i',
'instance_name' => 'ni0',
'range' => 'ni_S_Aw-1 : 0',
'type' => 'input'
},
'ni_s_we_i' => {
'intfc_port' => 'we_i',
'range' => '',
'instance_name' => 'ni0',
'type' => 'input'
}
}
}
},
'instance_ids' => {
'gpi0' => {
'module_name' => 'gpi',
'category' => 'GPI',
'instance' => 'gpi0',
'module' => 'gpi'
},
'clk_source0' => {
'module_name' => 'clk_source',
'category' => 'source',
'instance' => 'ss',
'module' => 'clk_source'
},
'ext_int0' => {
'module_name' => 'ext_int',
'category' => 'interrupt',
'instance' => 'ext_int',
'module' => 'ext_int'
},
'ni0' => {
'parameters' => {
'ni_SSA_EN' => {
'info' => undef,
'deafult' => '"NO"',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_NX' => {
'info' => undef,
'deafult' => ' 2',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_Fpay' => {
'info' => undef,
'deafult' => ' 32',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_TOPOLOGY' => {
'info' => undef,
'deafult' => '"MESH"',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_B' => {
'info' => '',
'deafult' => ' 4',
'global_param' => 'Parameter',
'content' => '',
'type' => 'Fixed',
'redefine_param' => 1
},
'ni_NY' => {
'info' => undef,
'deafult' => ' 2',
'global_param' => 'Parameter',
'content' => '',
'type' => 'Fixed',
'redefine_param' => 1
},
'ni_V' => {
'info' => '',
'deafult' => ' 4',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_CONGESTION_INDEX' => {
'info' => undef,
'deafult' => '3',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_DEBUG_EN' => {
'info' => undef,
'deafult' => '0',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_ROUTE_NAME' => {
'info' => undef,
'deafult' => '"XY"',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
}
},
'ports' => {
'ni_flit_out_wr' => {
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_out_wr',
'range' => '',
'type' => 'output'
},
'ni_s_cti_i' => {
'intfc_port' => 'cti_i',
'intfc_name' => 'plug:wb_slave[0]',
'range' => 'ni_TAGw-1 : 0',
'type' => 'input'
},
'ni_s_cyc_i' => {
'intfc_port' => 'cyc_i',
'intfc_name' => 'plug:wb_slave[0]',
'range' => '',
'type' => 'input'
},
'ni_s_stb_i' => {
'intfc_port' => 'stb_i',
'intfc_name' => 'plug:wb_slave[0]',
'range' => '',
'type' => 'input'
},
'ni_s_sel_i' => {
'intfc_port' => 'sel_i',
'intfc_name' => 'plug:wb_slave[0]',
'range' => 'ni_SELw-1 : 0',
'type' => 'input'
},
'ni_current_y' => {
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'current_y',
'range' => 'ni_Yw-1 : 0',
'type' => 'input'
},
'ni_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'intfc_name' => 'socket:ni[0]',
'range' => '',
'type' => 'input'
},
'ni_credit_in' => {
'intfc_port' => 'credit_in',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0',
'type' => 'input'
},
'ni_s_ack_o' => {
'intfc_port' => 'ack_o',
'intfc_name' => 'plug:wb_slave[0]',
'range' => '',
'type' => 'output'
},
'ni_flit_in' => {
'intfc_port' => 'flit_in',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'type' => 'input'
},
'ni_s_addr_i' => {
'intfc_port' => 'adr_i',
'intfc_name' => 'plug:wb_slave[0]',
'range' => 'ni_S_Aw-1 : 0',
'type' => 'input'
},
'ni_s_we_i' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'we_i',
'range' => '',
'type' => 'input'
},
'ni_current_x' => {
'intfc_port' => 'current_x',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Xw-1 : 0',
'type' => 'input'
},
'ni_s_rty_o' => {
'intfc_port' => 'rty_o',
'intfc_name' => 'plug:wb_slave[0]',
'range' => '',
'type' => 'output'
},
'ni_s_dat_o' => {
'intfc_port' => 'dat_o',
'intfc_name' => 'plug:wb_slave[0]',
'range' => 'ni_Dw-1 : 0',
'type' => 'output'
},
'ni_s_dat_i' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'dat_i',
'range' => 'ni_Dw-1 : 0',
'type' => 'input'
},
'ni_s_err_o' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'err_o',
'range' => '',
'type' => 'output'
},
'ni_flit_out' => {
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_out',
'range' => 'ni_Fw-1 : 0',
'type' => 'output'
},
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1: 0',
'type' => 'output'
}
},
'module_name' => 'ni',
'category' => 'NoC',
'instance' => 'ni',
'module' => 'ni'
},
'wishbone_bus0' => {
'module_name' => 'wishbone_bus',
'category' => 'bus',
'instance' => 'bus',
'module' => 'wishbone_bus'
},
'Altera_single_port_ram0' => {
'module_name' => 'Altera_single_port_ram',
'category' => 'RAM',
'instance' => 'Altera_single_port_ram0',
'module' => 'Altera_single_port_ram'
}
}
}, 'ip_gen' )
},
'lm32_tile' => {
'top' => bless( {
'parameters' => {
'gpo_PORT_WIDTH' => ' 1',
'ram_Dw' => '32',
'ram_Aw' => '12'
},
'ports' => {
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => '',
'type' => 'output'
},
'ni_current_x' => {
'intfc_port' => 'current_x',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni_Xw-1 : 0',
'type' => 'input'
},
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'intfc_name' => 'plug:clk[0]',
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input'
},
'cpu_en_i' => {
'intfc_port' => 'enable_i',
'intfc_name' => 'plug:enable[0]',
'instance_name' => 'lm320',
'range' => '',
'type' => 'input'
},
'ni_flit_out' => {
'intfc_port' => 'flit_out',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni_Fw-1 : 0',
'type' => 'output'
},
'ni_current_y' => {
'intfc_port' => 'current_y',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni_Yw-1 : 0',
'type' => 'input'
},
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni_V-1: 0',
'type' => 'output'
},
'ni_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => '',
'type' => 'input'
},
'gpo_port_o' => {
'intfc_port' => 'IO',
'intfc_name' => 'IO',
'instance_name' => 'gpo0',
'range' => 'gpo_PORT_WIDTH-1 : 0',
'type' => 'output'
},
'ni_credit_in' => {
'intfc_port' => 'credit_in',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni_V-1 : 0',
'type' => 'input'
},
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input'
},
'ni_flit_in' => {
'intfc_port' => 'flit_in',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni_Fw-1 : 0',
'type' => 'input'
}
},
'interface' => {
'plug:enable[0]' => {
'ports' => {
'cpu_en_i' => {
'intfc_port' => 'enable_i',
'instance_name' => 'lm320',
'range' => '',
'type' => 'input'
}
}
},
'socket:ni[0]' => {
'ports' => {
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'instance_name' => 'ni0',
'range' => '',
'type' => 'output'
},
'ni_current_x' => {
'intfc_port' => 'current_x',
'instance_name' => 'ni0',
'range' => 'ni_Xw-1 : 0',
'type' => 'input'
},
'ni_current_y' => {
'intfc_port' => 'current_y',
'instance_name' => 'ni0',
'range' => 'ni_Yw-1 : 0',
'type' => 'input'
},
'ni_flit_out' => {
'intfc_port' => 'flit_out',
'instance_name' => 'ni0',
'range' => 'ni_Fw-1 : 0',
'type' => 'output'
},
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'instance_name' => 'ni0',
'range' => 'ni_V-1: 0',
'type' => 'output'
},
'ni_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'instance_name' => 'ni0',
'range' => '',
'type' => 'input'
},
'ni_credit_in' => {
'intfc_port' => 'credit_in',
'instance_name' => 'ni0',
'range' => 'ni_V-1 : 0',
'type' => 'input'
},
'ni_flit_in' => {
'intfc_port' => 'flit_in',
'instance_name' => 'ni0',
'range' => 'ni_Fw-1 : 0',
'type' => 'input'
}
}
},
'IO' => {
'ports' => {
'gpo_port_o' => {
'intfc_port' => 'IO',
'instance_name' => 'gpo0',
'range' => 'gpo_PORT_WIDTH-1 : 0',
'type' => 'output'
}
}
},
'plug:clk[0]' => {
'ports' => {
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input'
}
}
},
'plug:reset[0]' => {
'ports' => {
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input'
}
}
}
},
'tiles' => {
'0' => {
'parameters' => {
'gpo_PORT_WIDTH' => 3,
'ram_Dw' => '32',
'ram_Aw' => '12'
}
}
},
'instance_ids' => {
'single_port_ram0' => {
'parameters' => {
'ram_Dw' => {
'info' => 'Memory data width in Bits.',
'deafult' => '32',
'global_param' => 'Parameter',
'content' => '8,1024,1',
'redefine_param' => 1,
'type' => 'Spin-button'
},
'ram_Aw' => {
'info' => 'Memory address width',
'deafult' => '12',
'global_param' => 'Parameter',
'content' => '4,31,1',
'redefine_param' => 1,
'type' => 'Spin-button'
}
},
'module_name' => 'wb_single_port_ram',
'category' => 'RAM',
'instance' => 'ram',
'module' => 'single_port_ram'
},
'lm320' => {
'ports' => {
'cpu_en_i' => {
'intfc_port' => 'enable_i',
'intfc_name' => 'plug:enable[0]',
'range' => '',
'type' => 'input'
}
},
'module_name' => 'lm32',
'category' => 'Processor',
'instance' => 'cpu',
'module' => 'lm32'
},
'clk_source0' => {
'ports' => {
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
'range' => '',
'type' => 'input'
},
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'intfc_name' => 'plug:clk[0]',
'range' => '',
'type' => 'input'
}
},
'module_name' => 'clk_source',
'category' => 'Source',
'instance' => 'ss',
'module' => 'clk_source'
},
'gpo0' => {
'parameters' => {
'gpo_PORT_WIDTH' => {
'info' => 'output port width',
'deafult' => ' 1',
'global_param' => 'Parameter',
'content' => '1,32,1',
'redefine_param' => 1,
'type' => 'Spin-button'
}
},
'ports' => {
'gpo_port_o' => {
'intfc_port' => 'IO',
'intfc_name' => 'IO',
'range' => 'gpo_PORT_WIDTH-1 : 0',
'type' => 'output'
}
},
'module_name' => 'gpo',
'category' => 'GPIO',
'instance' => 'gpo',
'module' => 'gpo'
},
'wishbone_bus0' => {
'module_name' => 'wishbone_bus',
'category' => 'Bus',
'instance' => 'bus',
'module' => 'wishbone_bus'
},
'ni0' => {
'parameters' => {
'ni_TOPOLOGY' => {
'info' => undef,
'deafult' => '"MESH"',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_Fpay' => {
'info' => undef,
'deafult' => ' 32',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_NX' => {
'info' => undef,
'deafult' => ' 2',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_NY' => {
'info' => undef,
'deafult' => ' 2',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_B' => {
'info' => '',
'deafult' => ' 4',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_V' => {
'info' => '',
'deafult' => ' 4',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_DEBUG_EN' => {
'info' => undef,
'deafult' => '0',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_ROUTE_NAME' => {
'info' => undef,
'deafult' => '"XY"',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
}
},
'ports' => {
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'intfc_name' => 'socket:ni[0]',
'range' => '',
'type' => 'output'
},
'ni_current_x' => {
'intfc_port' => 'current_x',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Xw-1 : 0',
'type' => 'input'
},
'ni_current_y' => {
'intfc_port' => 'current_y',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Yw-1 : 0',
'type' => 'input'
},
'ni_flit_out' => {
'intfc_port' => 'flit_out',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'type' => 'output'
},
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1: 0',
'type' => 'output'
},
'ni_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'intfc_name' => 'socket:ni[0]',
'range' => '',
'type' => 'input'
},
'ni_credit_in' => {
'intfc_port' => 'credit_in',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0',
'type' => 'input'
},
'ni_flit_in' => {
'intfc_port' => 'flit_in',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'type' => 'input'
}
},
'module_name' => 'ni',
'category' => 'NoC',
'instance' => 'ni',
'module' => 'ni'
}
}
}, 'ip_gen' ),
'tile_nums' => [
0,
1,
2,
3
]
},
'int_ni' => {
'top' => bless( {
'ports' => {
'ni0_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => '',
'type' => 'input'
},
'aeMB0_sys_ena_i' => {
'intfc_port' => 'enable_i',
'intfc_name' => 'plug:enable[0]',
'instance_name' => 'aeMB0',
'range' => '',
'type' => 'input'
},
'ni0_credit_out' => {
'intfc_port' => 'credit_out',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni0_V-1: 0',
'type' => 'output'
},
'ni0_current_x' => {
'intfc_port' => 'current_x',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni0_Xw-1 : 0',
'type' => 'input'
},
'ni0_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => '',
'type' => 'output'
},
'ni0_current_y' => {
'intfc_port' => 'current_y',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni0_Yw-1 : 0',
'type' => 'input'
},
'ni0_flit_in' => {
'intfc_port' => 'flit_in',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni0_Fw-1 : 0',
'type' => 'input'
},
'ni0_credit_in' => {
'intfc_port' => 'credit_in',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni0_V-1 : 0',
'type' => 'input'
},
'ni0_flit_out' => {
'intfc_port' => 'flit_out',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni0_Fw-1 : 0',
'type' => 'output'
}
},
'interface' => {
'plug:enable[0]' => {
'ports' => {
'aeMB0_sys_ena_i' => {
'intfc_port' => 'enable_i',
'instance_name' => 'aeMB0',
'range' => '',
'type' => 'input'
}
}
},
'socket:ni[0]' => {
'ports' => {
'ni0_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'instance_name' => 'ni0',
'range' => '',
'type' => 'input'
},
'ni0_credit_out' => {
'intfc_port' => 'credit_out',
'instance_name' => 'ni0',
'range' => 'ni0_V-1: 0',
'type' => 'output'
},
'ni0_current_x' => {
'intfc_port' => 'current_x',
'instance_name' => 'ni0',
'range' => 'ni0_Xw-1 : 0',
'type' => 'input'
},
'ni0_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'instance_name' => 'ni0',
'range' => '',
'type' => 'output'
},
'ni0_current_y' => {
'intfc_port' => 'current_y',
'instance_name' => 'ni0',
'range' => 'ni0_Yw-1 : 0',
'type' => 'input'
},
'ni0_flit_in' => {
'intfc_port' => 'flit_in',
'instance_name' => 'ni0',
'range' => 'ni0_Fw-1 : 0',
'type' => 'input'
},
'ni0_credit_in' => {
'intfc_port' => 'credit_in',
'instance_name' => 'ni0',
'range' => 'ni0_V-1 : 0',
'type' => 'input'
},
'ni0_flit_out' => {
'intfc_port' => 'flit_out',
'instance_name' => 'ni0',
'range' => 'ni0_Fw-1 : 0',
'type' => 'output'
}
}
}
},
'instance_ids' => {
'aeMB0' => {
'ports' => {
'aeMB0_sys_ena_i' => {
'intfc_port' => 'enable_i',
'intfc_name' => 'plug:enable[0]',
'range' => '',
'type' => 'input'
}
},
'module_name' => 'aeMB_top',
'category' => 'Processor',
'instance' => 'aeMB0',
'module' => 'aeMB'
},
'ext_int0' => {
'module_name' => 'ext_int',
'category' => 'interrupt',
'instance' => 'ext_int0',
'module' => 'ext_int'
},
'clk_source0' => {
'module_name' => 'clk_source',
'category' => 'source',
'instance' => 'clk_source0',
'module' => 'clk_source'
},
'wishbone_bus0' => {
'module_name' => 'wishbone_bus',
'category' => 'bus',
'instance' => 'bus',
'module' => 'wishbone_bus'
},
'ni0' => {
'parameters' => {
'ni0_TOPOLOGY' => {
'info' => undef,
'deafult' => '"MESH"',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni0_DEBUG_EN' => {
'info' => undef,
'deafult' => '0',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni0_Fpay' => {
'info' => undef,
'deafult' => ' 32',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni0_CONGESTION_INDEX' => {
'info' => undef,
'deafult' => '3',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni0_SSA_EN' => {
'info' => undef,
'deafult' => '"NO"',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni0_B' => {
'info' => '',
'deafult' => ' 4',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni0_V' => {
'info' => '',
'deafult' => ' 4',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni0_NY' => {
'info' => undef,
'deafult' => ' 2',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni0_NX' => {
'info' => undef,
'deafult' => ' 2',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni0_ROUTE_NAME' => {
'info' => undef,
'deafult' => '"XY"',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
}
},
'ports' => {
'ni0_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'intfc_name' => 'socket:ni[0]',
'range' => '',
'type' => 'input'
},
'ni0_credit_out' => {
'intfc_port' => 'credit_out',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni0_V-1: 0',
'type' => 'output'
},
'ni0_current_x' => {
'intfc_port' => 'current_x',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni0_Xw-1 : 0',
'type' => 'input'
},
'ni0_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'intfc_name' => 'socket:ni[0]',
'range' => '',
'type' => 'output'
},
'ni0_current_y' => {
'intfc_port' => 'current_y',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni0_Yw-1 : 0',
'type' => 'input'
},
'ni0_flit_in' => {
'intfc_port' => 'flit_in',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni0_Fw-1 : 0',
'type' => 'input'
},
'ni0_credit_in' => {
'intfc_port' => 'credit_in',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni0_V-1 : 0',
'type' => 'input'
},
'ni0_flit_out' => {
'intfc_port' => 'flit_out',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni0_Fw-1 : 0',
'type' => 'output'
}
},
'module_name' => 'ni',
'category' => 'NoC',
'instance' => 'ni0',
'module' => 'ni'
},
'int_ctrl0' => {
'module_name' => 'int_ctrl',
'category' => 'interrupt',
'instance' => 'int_ctrl0',
'module' => 'int_ctrl'
},
'Altera_single_port_ram0' => {
'module_name' => 'Altera_single_port_ram',
'category' => 'RAM',
'instance' => 'Altera_single_port_ram0',
'module' => 'Altera_single_port_ram'
}
}
}, 'ip_gen' )
},
'ni_test' => {
'top' => bless( {
'parameters' => {
'ram_Dw' => '32',
'ram_Aw' => 12,
'led_PORT_WIDTH' => ' 1'
},
'ports' => {
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => '',
'type' => 'output'
},
'ni_current_x' => {
'intfc_port' => 'current_x',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni_Xw-1 : 0',
'type' => 'input'
},
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'intfc_name' => 'plug:clk[0]',
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input'
},
'aeMB_sys_ena_i' => {
'intfc_port' => 'enable_i',
'intfc_name' => 'plug:enable[0]',
'instance_name' => 'aeMB0',
'range' => '',
'type' => 'input'
},
'led_port_o' => {
'intfc_port' => 'IO',
'intfc_name' => 'IO',
'instance_name' => 'gpo0',
'range' => 'led_PORT_WIDTH-1 : 0',
'type' => 'output'
},
'ni_flit_out' => {
'intfc_port' => 'flit_out',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni_Fw-1 : 0',
'type' => 'output'
},
'ni_current_y' => {
'intfc_port' => 'current_y',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni_Yw-1 : 0',
'type' => 'input'
},
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni_V-1: 0',
'type' => 'output'
},
'ni_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => '',
'type' => 'input'
},
'ni_credit_in' => {
'intfc_port' => 'credit_in',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni_V-1 : 0',
'type' => 'input'
},
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input'
},
'ni_flit_in' => {
'intfc_port' => 'flit_in',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni_Fw-1 : 0',
'type' => 'input'
}
},
'interface' => {
'plug:enable[0]' => {
'ports' => {
'aeMB_sys_ena_i' => {
'intfc_port' => 'enable_i',
'instance_name' => 'aeMB0',
'range' => '',
'type' => 'input'
}
}
},
'socket:ni[0]' => {
'ports' => {
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'instance_name' => 'ni0',
'range' => '',
'type' => 'output'
},
'ni_current_x' => {
'intfc_port' => 'current_x',
'instance_name' => 'ni0',
'range' => 'ni_Xw-1 : 0',
'type' => 'input'
},
'ni_current_y' => {
'intfc_port' => 'current_y',
'instance_name' => 'ni0',
'range' => 'ni_Yw-1 : 0',
'type' => 'input'
},
'ni_flit_out' => {
'intfc_port' => 'flit_out',
'instance_name' => 'ni0',
'range' => 'ni_Fw-1 : 0',
'type' => 'output'
},
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'instance_name' => 'ni0',
'range' => 'ni_V-1: 0',
'type' => 'output'
},
'ni_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'instance_name' => 'ni0',
'range' => '',
'type' => 'input'
},
'ni_credit_in' => {
'intfc_port' => 'credit_in',
'instance_name' => 'ni0',
'range' => 'ni_V-1 : 0',
'type' => 'input'
},
'ni_flit_in' => {
'intfc_port' => 'flit_in',
'instance_name' => 'ni0',
'range' => 'ni_Fw-1 : 0',
'type' => 'input'
}
}
},
'IO' => {
'ports' => {
'led_port_o' => {
'intfc_port' => 'IO',
'instance_name' => 'gpo0',
'range' => 'led_PORT_WIDTH-1 : 0',
'type' => 'output'
}
}
},
'plug:clk[0]' => {
'ports' => {
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input'
}
}
},
'plug:reset[0]' => {
'ports' => {
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input'
}
}
}
},
'instance_ids' => {
'aeMB0' => {
'ports' => {
'aeMB_sys_ena_i' => {
'intfc_port' => 'enable_i',
'intfc_name' => 'plug:enable[0]',
'range' => '',
'type' => 'input'
}
},
'module_name' => 'aeMB_top',
'category' => 'Processor',
'instance' => 'aeMB',
'module' => 'aeMB'
},
'gpo0' => {
'parameters' => {
'led_PORT_WIDTH' => {
'info' => 'output port width',
'deafult' => ' 1',
'global_param' => 1,
'content' => '1,32,1',
'redefine_param' => 1,
'type' => 'Spin-button'
}
},
'ports' => {
'led_port_o' => {
'intfc_port' => 'IO',
'intfc_name' => 'IO',
'range' => 'led_PORT_WIDTH-1 : 0',
'type' => 'output'
}
},
'module_name' => 'gpo',
'category' => 'GPI',
'instance' => 'led',
'module' => 'gpo'
},
'wishbone_bus0' => {
'module_name' => 'wishbone_bus',
'category' => 'bus',
'instance' => 'bus',
'module' => 'wishbone_bus'
},
'int_ctrl0' => {
'module_name' => 'int_ctrl',
'category' => 'interrupt',
'instance' => 'int_ctrl',
'module' => 'int_ctrl'
},
'Altera_single_port_ram0' => {
'parameters' => {
'ram_Dw' => {
'info' => undef,
'deafult' => '32',
'global_param' => 1,
'content' => '8,1024,1',
'redefine_param' => 1,
'type' => 'Spin-button'
},
'ram_Aw' => {
'info' => undef,
'deafult' => 12,
'global_param' => 1,
'content' => '4,31,1',
'redefine_param' => 1,
'type' => 'Spin-button'
}
},
'module_name' => 'Altera_single_port_ram',
'category' => 'RAM',
'instance' => 'ram',
'module' => 'Altera_single_port_ram'
},
'clk_source0' => {
'ports' => {
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
'range' => '',
'type' => 'input'
},
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'intfc_name' => 'plug:clk[0]',
'range' => '',
'type' => 'input'
}
},
'module_name' => 'clk_source',
'category' => 'source',
'instance' => 'ss',
'module' => 'clk_source'
},
'ni0' => {
'parameters' => {
'ni_TOPOLOGY' => {
'info' => undef,
'deafult' => '"MESH"',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_Fpay' => {
'info' => undef,
'deafult' => ' 32',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_NX' => {
'info' => undef,
'deafult' => ' 2',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_NY' => {
'info' => undef,
'deafult' => ' 2',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_B' => {
'info' => '',
'deafult' => ' 4',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_V' => {
'info' => '',
'deafult' => ' 4',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_DEBUG_EN' => {
'info' => undef,
'deafult' => '0',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_ROUTE_NAME' => {
'info' => undef,
'deafult' => '"XY"',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
}
},
'ports' => {
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'intfc_name' => 'socket:ni[0]',
'range' => '',
'type' => 'output'
},
'ni_current_x' => {
'intfc_port' => 'current_x',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Xw-1 : 0',
'type' => 'input'
},
'ni_current_y' => {
'intfc_port' => 'current_y',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Yw-1 : 0',
'type' => 'input'
},
'ni_flit_out' => {
'intfc_port' => 'flit_out',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'type' => 'output'
},
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1: 0',
'type' => 'output'
},
'ni_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'intfc_name' => 'socket:ni[0]',
'range' => '',
'type' => 'input'
},
'ni_credit_in' => {
'intfc_port' => 'credit_in',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0',
'type' => 'input'
},
'ni_flit_in' => {
'intfc_port' => 'flit_in',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'type' => 'input'
}
},
'module_name' => 'ni',
'category' => 'NoC',
'instance' => 'ni',
'module' => 'ni'
},
'timer0' => {
'module_name' => 'timer',
'category' => 'TIM',
'instance' => 'timer',
'module' => 'timer'
}
}
}, 'ip_gen' )
},
'tang' => {
'top' => bless( {
'parameters' => {
'ram_Dw' => '32',
'ram_Aw' => 13,
'led_PORT_WIDTH' => ' 1'
},
'ports' => {
'uart_readyfordata' => {
'intfc_port' => 'IO',
'intfc_name' => 'IO',
'instance_name' => 'altera_jtag_uart0',
'range' => '',
'type' => 'output'
},
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => '',
'type' => 'output'
},
'ni_current_x' => {
'intfc_port' => 'current_x',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni_Xw-1 : 0',
'type' => 'input'
},
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'intfc_name' => 'plug:clk[0]',
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input'
},
'aeMB_sys_ena_i' => {
'intfc_port' => 'enable_i',
'intfc_name' => 'plug:enable[0]',
'instance_name' => 'aeMB0',
'range' => '',
'type' => 'input'
},
'led_port_o' => {
'intfc_port' => 'IO',
'intfc_name' => 'IO',
'instance_name' => 'gpo0',
'range' => 'led_PORT_WIDTH-1 : 0',
'type' => 'output'
},
'ni_flit_out' => {
'intfc_port' => 'flit_out',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni_Fw-1 : 0',
'type' => 'output'
},
'ni_current_y' => {
'intfc_port' => 'current_y',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni_Yw-1 : 0',
'type' => 'input'
},
'uart_dataavailable' => {
'intfc_port' => 'IO',
'intfc_name' => 'IO',
'instance_name' => 'altera_jtag_uart0',
'range' => '',
'type' => 'output'
},
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni_V-1: 0',
'type' => 'output'
},
'ni_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => '',
'type' => 'input'
},
'ni_credit_in' => {
'intfc_port' => 'credit_in',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni_V-1 : 0',
'type' => 'input'
},
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input'
},
'ni_flit_in' => {
'intfc_port' => 'flit_in',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni_Fw-1 : 0',
'type' => 'input'
}
},
'interface' => {
'plug:enable[0]' => {
'ports' => {
'aeMB_sys_ena_i' => {
'intfc_port' => 'enable_i',
'instance_name' => 'aeMB0',
'range' => '',
'type' => 'input'
}
}
},
'socket:ni[0]' => {
'ports' => {
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'instance_name' => 'ni0',
'range' => '',
'type' => 'output'
},
'ni_current_x' => {
'intfc_port' => 'current_x',
'instance_name' => 'ni0',
'range' => 'ni_Xw-1 : 0',
'type' => 'input'
},
'ni_current_y' => {
'intfc_port' => 'current_y',
'instance_name' => 'ni0',
'range' => 'ni_Yw-1 : 0',
'type' => 'input'
},
'ni_flit_out' => {
'intfc_port' => 'flit_out',
'instance_name' => 'ni0',
'range' => 'ni_Fw-1 : 0',
'type' => 'output'
},
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'instance_name' => 'ni0',
'range' => 'ni_V-1: 0',
'type' => 'output'
},
'ni_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'instance_name' => 'ni0',
'range' => '',
'type' => 'input'
},
'ni_credit_in' => {
'intfc_port' => 'credit_in',
'instance_name' => 'ni0',
'range' => 'ni_V-1 : 0',
'type' => 'input'
},
'ni_flit_in' => {
'intfc_port' => 'flit_in',
'instance_name' => 'ni0',
'range' => 'ni_Fw-1 : 0',
'type' => 'input'
}
}
},
'IO' => {
'ports' => {
'led_port_o' => {
'intfc_port' => 'IO',
'instance_name' => 'gpo0',
'range' => 'led_PORT_WIDTH-1 : 0',
'type' => 'output'
},
'uart_readyfordata' => {
'intfc_port' => 'IO',
'instance_name' => 'altera_jtag_uart0',
'range' => '',
'type' => 'output'
},
'uart_dataavailable' => {
'intfc_port' => 'IO',
'instance_name' => 'altera_jtag_uart0',
'range' => '',
'type' => 'output'
}
}
},
'plug:clk[0]' => {
'ports' => {
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input'
}
}
},
'plug:reset[0]' => {
'ports' => {
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input'
}
}
}
},
'instance_ids' => {
'aeMB0' => {
'ports' => {
'aeMB_sys_ena_i' => {
'intfc_port' => 'enable_i',
'intfc_name' => 'plug:enable[0]',
'range' => '',
'type' => 'input'
}
},
'module_name' => 'aeMB_top',
'category' => 'Processor',
'instance' => 'aeMB',
'module' => 'aeMB'
},
'gpo0' => {
'parameters' => {
'led_PORT_WIDTH' => {
'info' => 'output port width',
'deafult' => ' 1',
'global_param' => 1,
'content' => '1,32,1',
'redefine_param' => 1,
'type' => 'Spin-button'
}
},
'ports' => {
'led_port_o' => {
'intfc_port' => 'IO',
'intfc_name' => 'IO',
'range' => 'led_PORT_WIDTH-1 : 0',
'type' => 'output'
}
},
'module_name' => 'gpo',
'category' => 'GPI',
'instance' => 'led',
'module' => 'gpo'
},
'wishbone_bus0' => {
'module_name' => 'wishbone_bus',
'category' => 'bus',
'instance' => 'bus',
'module' => 'wishbone_bus'
},
'int_ctrl0' => {
'module_name' => 'int_ctrl',
'category' => 'interrupt',
'instance' => 'int_ctrl',
'module' => 'int_ctrl'
},
'altera_jtag_uart0' => {
'ports' => {
'uart_readyfordata' => {
'intfc_port' => 'IO',
'intfc_name' => 'IO',
'range' => '',
'type' => 'output'
},
'uart_dataavailable' => {
'intfc_port' => 'IO',
'intfc_name' => 'IO',
'range' => '',
'type' => 'output'
}
},
'module_name' => 'altera_jtag_uart_wb',
'category' => 'Jtag',
'instance' => 'uart',
'module' => 'altera_jtag_uart'
},
'Altera_single_port_ram0' => {
'parameters' => {
'ram_Dw' => {
'info' => undef,
'deafult' => '32',
'global_param' => 1,
'content' => '8,1024,1',
'redefine_param' => 1,
'type' => 'Spin-button'
},
'ram_Aw' => {
'info' => undef,
'deafult' => 13,
'global_param' => 1,
'content' => '4,31,1',
'redefine_param' => 1,
'type' => 'Spin-button'
}
},
'module_name' => 'Altera_single_port_ram',
'category' => 'RAM',
'instance' => 'ram',
'module' => 'Altera_single_port_ram'
},
'clk_source0' => {
'ports' => {
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
'range' => '',
'type' => 'input'
},
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'intfc_name' => 'plug:clk[0]',
'range' => '',
'type' => 'input'
}
},
'module_name' => 'clk_source',
'category' => 'source',
'instance' => 'ss',
'module' => 'clk_source'
},
'ni0' => {
'parameters' => {
'ni_TOPOLOGY' => {
'info' => undef,
'deafult' => '"MESH"',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_Fpay' => {
'info' => undef,
'deafult' => ' 32',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_NX' => {
'info' => undef,
'deafult' => ' 2',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_NY' => {
'info' => undef,
'deafult' => ' 2',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_B' => {
'info' => '',
'deafult' => ' 4',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_V' => {
'info' => '',
'deafult' => ' 4',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_DEBUG_EN' => {
'info' => undef,
'deafult' => '0',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_ROUTE_NAME' => {
'info' => undef,
'deafult' => '"XY"',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
}
},
'ports' => {
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'intfc_name' => 'socket:ni[0]',
'range' => '',
'type' => 'output'
},
'ni_current_x' => {
'intfc_port' => 'current_x',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Xw-1 : 0',
'type' => 'input'
},
'ni_current_y' => {
'intfc_port' => 'current_y',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Yw-1 : 0',
'type' => 'input'
},
'ni_flit_out' => {
'intfc_port' => 'flit_out',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'type' => 'output'
},
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1: 0',
'type' => 'output'
},
'ni_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'intfc_name' => 'socket:ni[0]',
'range' => '',
'type' => 'input'
},
'ni_credit_in' => {
'intfc_port' => 'credit_in',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0',
'type' => 'input'
},
'ni_flit_in' => {
'intfc_port' => 'flit_in',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'type' => 'input'
}
},
'module_name' => 'ni',
'category' => 'NoC',
'instance' => 'ni',
'module' => 'ni'
},
'timer0' => {
'module_name' => 'timer',
'category' => 'TIM',
'instance' => 'timer',
'module' => 'timer'
}
}
}, 'ip_gen' )
},
'test_ni_p' => {
'top' => bless( {
'parameters' => {
'ram_Dw' => '32',
'ram_Aw' => '10'
},
'ports' => {
'ni0_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => '',
'type' => 'input'
},
'aeMB_sys_int_i' => {
'intfc_port' => 'int_i',
'intfc_name' => 'plug:interrupt_cpu[0]',
'instance_name' => 'aeMB0',
'range' => '',
'type' => 'input'
},
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'intfc_name' => 'plug:clk[0]',
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input'
},
'ni0_irq' => {
'intfc_port' => 'int_o',
'intfc_name' => 'plug:interrupt_peripheral[0]',
'instance_name' => 'ni0',
'range' => '',
'type' => 'output'
},
'ni0_credit_out' => {
'intfc_port' => 'credit_out',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni0_V-1: 0',
'type' => 'output'
},
'aeMB_sys_ena_i' => {
'intfc_port' => 'enable_i',
'intfc_name' => 'plug:enable[0]',
'instance_name' => 'aeMB0',
'range' => '',
'type' => 'input'
},
'ni0_current_x' => {
'intfc_port' => 'current_x',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni0_Xw-1 : 0',
'type' => 'input'
},
'ni0_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => '',
'type' => 'output'
},
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input'
},
'ni0_flit_in' => {
'intfc_port' => 'flit_in',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni0_Fw-1 : 0',
'type' => 'input'
},
'ni0_current_y' => {
'intfc_port' => 'current_y',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni0_Yw-1 : 0',
'type' => 'input'
},
'ni0_flit_out' => {
'intfc_port' => 'flit_out',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni0_Fw-1 : 0',
'type' => 'output'
},
'ni0_credit_in' => {
'intfc_port' => 'credit_in',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni0_V-1 : 0',
'type' => 'input'
}
},
'interface' => {
'plug:enable[0]' => {
'ports' => {
'aeMB_sys_ena_i' => {
'intfc_port' => 'enable_i',
'instance_name' => 'aeMB0',
'range' => '',
'type' => 'input'
}
}
},
'socket:ni[0]' => {
'ports' => {
'ni0_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'instance_name' => 'ni0',
'range' => '',
'type' => 'input'
},
'ni0_credit_out' => {
'intfc_port' => 'credit_out',
'instance_name' => 'ni0',
'range' => 'ni0_V-1: 0',
'type' => 'output'
},
'ni0_current_x' => {
'intfc_port' => 'current_x',
'instance_name' => 'ni0',
'range' => 'ni0_Xw-1 : 0',
'type' => 'input'
},
'ni0_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'instance_name' => 'ni0',
'range' => '',
'type' => 'output'
},
'ni0_current_y' => {
'intfc_port' => 'current_y',
'instance_name' => 'ni0',
'range' => 'ni0_Yw-1 : 0',
'type' => 'input'
},
'ni0_flit_in' => {
'intfc_port' => 'flit_in',
'instance_name' => 'ni0',
'range' => 'ni0_Fw-1 : 0',
'type' => 'input'
},
'ni0_credit_in' => {
'intfc_port' => 'credit_in',
'instance_name' => 'ni0',
'range' => 'ni0_V-1 : 0',
'type' => 'input'
},
'ni0_flit_out' => {
'intfc_port' => 'flit_out',
'instance_name' => 'ni0',
'range' => 'ni0_Fw-1 : 0',
'type' => 'output'
}
}
},
'plug:clk[0]' => {
'ports' => {
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input'
}
}
},
'plug:interrupt_cpu[0]' => {
'ports' => {
'aeMB_sys_int_i' => {
'intfc_port' => 'int_i',
'instance_name' => 'aeMB0',
'range' => '',
'type' => 'input'
}
}
},
'plug:interrupt_peripheral[0]' => {
'ports' => {
'ni0_irq' => {
'intfc_port' => 'int_o',
'instance_name' => 'ni0',
'range' => '',
'type' => 'output'
}
}
},
'plug:reset[0]' => {
'ports' => {
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input'
}
}
}
},
'instance_ids' => {
'aeMB0' => {
'ports' => {
'aeMB_sys_int_i' => {
'intfc_port' => 'int_i',
'intfc_name' => 'plug:interrupt_cpu[0]',
'range' => '',
'type' => 'input'
},
'aeMB_sys_ena_i' => {
'intfc_port' => 'enable_i',
'intfc_name' => 'plug:enable[0]',
'range' => '',
'type' => 'input'
}
},
'module_name' => 'aeMB_top',
'category' => 'Processor',
'instance' => 'aeMB',
'module' => 'aeMB'
},
'clk_source0' => {
'ports' => {
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
'range' => '',
'type' => 'input'
},
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'intfc_name' => 'plug:clk[0]',
'range' => '',
'type' => 'input'
}
},
'module_name' => 'clk_source',
'category' => 'source',
'instance' => 'ss',
'module' => 'clk_source'
},
'wishbone_bus0' => {
'module_name' => 'wishbone_bus',
'category' => 'bus',
'instance' => 'bus',
'module' => 'wishbone_bus'
},
'ni0' => {
'parameters' => {
'ni0_TOPOLOGY' => {
'info' => undef,
'deafult' => '"MESH"',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni0_DEBUG_EN' => {
'info' => undef,
'deafult' => '0',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni0_Fpay' => {
'info' => undef,
'deafult' => ' 32',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni0_CONGESTION_INDEX' => {
'info' => undef,
'deafult' => '3',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni0_SSA_EN' => {
'info' => undef,
'deafult' => '"NO"',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni0_B' => {
'info' => '',
'deafult' => ' 4',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni0_V' => {
'info' => '',
'deafult' => ' 4',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni0_NY' => {
'info' => undef,
'deafult' => ' 2',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni0_NX' => {
'info' => undef,
'deafult' => ' 2',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni0_ROUTE_NAME' => {
'info' => undef,
'deafult' => '"XY"',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
}
},
'ports' => {
'ni0_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'intfc_name' => 'socket:ni[0]',
'range' => '',
'type' => 'input'
},
'ni0_irq' => {
'intfc_port' => 'int_o',
'intfc_name' => 'plug:interrupt_peripheral[0]',
'range' => '',
'type' => 'output'
},
'ni0_credit_out' => {
'intfc_port' => 'credit_out',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni0_V-1: 0',
'type' => 'output'
},
'ni0_current_x' => {
'intfc_port' => 'current_x',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni0_Xw-1 : 0',
'type' => 'input'
},
'ni0_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'intfc_name' => 'socket:ni[0]',
'range' => '',
'type' => 'output'
},
'ni0_current_y' => {
'intfc_port' => 'current_y',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni0_Yw-1 : 0',
'type' => 'input'
},
'ni0_flit_in' => {
'intfc_port' => 'flit_in',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni0_Fw-1 : 0',
'type' => 'input'
},
'ni0_credit_in' => {
'intfc_port' => 'credit_in',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni0_V-1 : 0',
'type' => 'input'
},
'ni0_flit_out' => {
'intfc_port' => 'flit_out',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni0_Fw-1 : 0',
'type' => 'output'
}
},
'module_name' => 'ni',
'category' => 'NoC',
'instance' => 'ni0',
'module' => 'ni'
},
'Altera_single_port_ram0' => {
'parameters' => {
'ram_Dw' => {
'info' => undef,
'deafult' => '32',
'global_param' => 1,
'content' => '8,1024,1',
'redefine_param' => 1,
'type' => 'Spin-button'
},
'ram_Aw' => {
'info' => undef,
'deafult' => '10',
'global_param' => 1,
'content' => '4,31,1',
'redefine_param' => 1,
'type' => 'Spin-button'
}
},
'module_name' => 'Altera_single_port_ram',
'category' => 'RAM',
'instance' => 'ram',
'module' => 'Altera_single_port_ram'
}
}
}, 'ip_gen' )
}
},
'setting' => {
'show_adv_setting' => 0,
'soc_path' => 'lib/soc',
'show_noc_setting' => 1,
'show_tile_setting' => 1
},
'tile' => {
'1' => {},
'0' => {
'param_setting' => 'Custom'
},
'3' => {},
'2' => {}
},
'mpsoc_name' => 'lm32_noc',
'gui_status' => {
'status' => 'ideal',
'timeout' => 0
},
'parameters_order' => {
'noc_param' => [
'NX',
'NY',
'V',
'B',
'Fpay',
'TOPOLOGY',
'ROUTE_NAME',
'SSA_EN',
'VC_REALLOCATION_TYPE',
'COMBINATION_TYPE',
'MUX_TYPE',
'C',
'DEBUG_EN',
'ADD_PIPREG_AFTER_CROSSBAR',
'FIRST_ARBITER_EXT_P_EN',
'AVC_ATOMIC_EN',
'ROUTE_SUBFUNC'
],
'noc_type' => [
'ROUTER_TYPE'
]
},
'file_name' => undef,
'noc_param' => {
'COMBINATION_TYPE' => '"COMB_NONSPEC"',
'NY' => ' 2',
'DEBUG_EN' => '0',
'NX' => ' 2',
'VC_REALLOCATION_TYPE' => '"NONATOMIC"',
'V' => '2',
'ROUTE_SUBFUNC' => '"XY"',
'ADD_PIPREG_AFTER_CROSSBAR' => '1\'b0',
'C' => 0,
'ROUTE_NAME' => '"XY"',
'Fpay' => '32',
'MUX_TYPE' => '"BINARY"',
'B' => '4',
'TOPOLOGY' => '"MESH"',
'AVC_ATOMIC_EN' => 0,
'SSA_EN' => '"NO"',
'FIRST_ARBITER_EXT_P_EN' => 0
},
'noc_type' => {
'ROUTER_TYPE' => '"VC_BASED"'
},
'noc_indept_param' => {}
}, 'mpsoc' );
/mpsoc/perl_gui/lib/perl/emulate_ram_gen.pl
2,13 → 2,19
use strict;
use warnings;
use List::Util 'shuffle';
require "widget.pl";
require "widget.pl";
 
 
use constant RESET_CMD => " $ENV{'PRONOC_WORK'}/toolchain/bin/jtag_main -n 127 -d \"I:1,D:1:1,I:0\" ";
use constant UNRESET_CMD => " $ENV{'PRONOC_WORK'}/toolchain/bin/jtag_main -n 127 -d \"I:1,D:1:0,I:0\" ";
use constant READ_DONE_CMD => " $ENV{'PRONOC_WORK'}/toolchain/bin/jtag_main -n 127 -d \"I:2,R:1:0,I:0\" ";
use constant UPDATE_WB_ADDR => 0x7;
use constant SIM_RAM_GEN => 1;
 
use constant JTAG_RAM_INDEX => 128;
use constant JTAG_DONE_RESET_INDEX => 127;
use constant RESET_NOC => " $ENV{'PRONOC_WORK'}/toolchain/bin/jtag_main -n ".JTAG_DONE_RESET_INDEX." -d \"I:1,D:2:1,I:0\" ";
use constant UNRESET_NOC => " $ENV{'PRONOC_WORK'}/toolchain/bin/jtag_main -n ".JTAG_DONE_RESET_INDEX." -d \"I:1,D:2:0,I:0\" ";
 
use constant READ_DONE_CMD => " $ENV{'PRONOC_WORK'}/toolchain/bin/jtag_main -n ".JTAG_DONE_RESET_INDEX." -d \"I:2,R:2:0,I:0\" ";
 
use constant UPDATE_WB_ADDR => 0x7;
use constant UPDATE_WB_WR_DATA => 0x6;
use constant UPDATE_WB_RD_DATA => 0x5;
use constant RD_WR_STATUS => 0x4;
15,87 → 21,87
use constant PROBE_ST => 0x2;
use constant SOURCE_ST => 0x1;
use constant BYPAS_ST => 0x0;
use constant RAM_BIN_FILE => "$ENV{'PRONOC_WORK'}/emulate/emulate_ram.bin";
use constant RAM_SIM_FILE => "$ENV{'PRONOC_WORK'}/emulate/ram";
 
sub get_data{
my ( $x, $y, $ref, $traffic, $ratio_in,$num, $line_num, $dest)=@_;
my %noc_info= %$ref;
my $C=$noc_info{C};
my $xn=$noc_info{NX};
my $yn=$noc_info{NY};
my $MAX_PCK_NUM = $noc_info{MAX_PCK_NUM};
my $MAX_SIM_CLKs = $noc_info{MAX_SIM_CLKs};
my $MAX_PCK_SIZ = $noc_info{MAX_PCK_SIZ};
 
 
my $Xw = log2($xn); # number of node in x axis
my $Yw = log2($yn); # number of node in y axis
my $Cw = ($C > 1)? log2($C): 1;
#$Fw = 2+V+Fpay,
my $RATIOw = log2(100),
my $PCK_CNTw = log2($MAX_PCK_NUM+1),
my $CLK_CNTw = log2($MAX_SIM_CLKs+1),
my $PCK_SIZw = log2($MAX_PCK_SIZ+1);
 
my $Dw=$PCK_CNTw+ $RATIOw + $PCK_SIZw + $Xw + $Yw + $Cw +1;
my $val=0;
my $q=0;
my $i=0;
my $last_adr=($traffic eq 'random' && $line_num<($xn* $yn)-2 )? 0 : 1;
#print "my $last_adr=($traffic eq 'random' && $line_num<($xn* $yn)-2 )? 0 : 1; \n";
my @fileds=get_ram_line($C, $x, $y, $xn, $yn, $traffic,$ratio_in,$line_num,$dest,$last_adr);
my ($pck_num_to_send_,$ratio_in_,$pck_size_,$dest_x_,$dest_y_,$pck_class_in_,$last_adr_)=@fileds;
my @sizes= ($PCK_CNTw, $RATIOw , $PCK_SIZw , $Xw , $Yw , $Cw ,1);
foreach my $p (@fileds){
$val= $val << $q;
$val= $val + $p;
$i++;
$q=$sizes[$i] if(defined $sizes[$i]);
}
my $sum = 0;
foreach my $num (@sizes){
$sum = $sum + $num;
}
my $result = sprintf("%010x", $val);
#print"$result\n";
return ($result,$last_adr,$Dw);
sub reset_cmd {
my ($ctrl_reset, $noc_reset)=@_;
my $reset_vector= (($ctrl_reset & 0x1) << 1) + ($noc_reset & 0x1);
my $cmd = " $ENV{'PRONOC_WORK'}/toolchain/bin/jtag_main -n ".JTAG_DONE_RESET_INDEX." -d \"I:1,D:2:$reset_vector,I:0\" ";
#print "$cmd\n";
return $cmd;
 
#ram_do= {pck_num_to_send_,ratio_in_,pck_size_,dest_x_,dest_y_,pck_class_in_,last_adr_};
}
 
 
}
 
sub get_ram_line{
my ($C, $x, $y, $xn, $yn, $traffic,$ratio_in,$line_num,$dest,$last_adr_)=@_;
my $pck_num_to_send_=2000000;
my $pck_size_=4;
my $pck_class_in_=0;
 
my $xw=log2($xn);
my $yw=log2($yn);
sub help {
print
" usage: ./ram_gen X Y TRAFFIC
X: number of node in X direction 2<x<=16
Y: number of node in Y direction 2<y<=16
TRAFFIC : select one of the following traffic patterns :
tornado,
transposed 1,
transposed 2,
random,
";
#print "$traffic\n";
my $dest_x_;
my $dest_y_;
}
 
 
 
 
 
 
sub random_dest_gen {
my $n=shift;
my @c=(0..$n-1);
my @o;
for (my $i=0; $i<$n; $i++){
my @l= shuffle @c;
@l=remove_scolar_from_array(\@l,$i);
$o[$i]=\@l;
}
return \@o;
 
}
 
sub run_cmd_update_info {
my ($cmd,$info)=@_;
my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($cmd);
if($exit){
add_info($info, "$stdout\n") if(defined $stdout);
add_info($info, "$stderr\n") if(defined $stderr);
}
#print "\n$cmd \n $stdout";
return $exit;
}
 
 
sub synthetic_destination{
my($traffic,$x,$y,$xn,$yn,$line_num,$rnd)=@_;
my $dest_x;
my $dest_y;
my $xw = log2($xn);
my $yw = log2($yn);
 
if( $traffic eq "transposed 1"){
$dest_x_= $xn-$y-1;
$dest_y_= $yn-$x-1;
$dest_x= $xn-$y-1;
$dest_y= $yn-$x-1;
} elsif( $traffic eq "transposed 2"){
$dest_x_ = $y;
$dest_y_ = $x;
$dest_x = $y;
$dest_y = $x;
} elsif( $traffic eq "bit reverse"){
my $joint_addr= ($x << log2($xn))+$y;
my $reverse_addr=0;
105,40 → 111,39
$reverse_addr|= (($joint_addr >> $pos) & 0x01) << $i;
# reverse_addr[i] = joint_addr [((Xw+Yw)-1)-i];
}
$dest_x_ = $reverse_addr>>$yw;
$dest_y_ = $reverse_addr&(0xFF>> (8-$yw));
 
$dest_x = $reverse_addr>>$yw;
$dest_y = $reverse_addr&(0xFF>> (8-$yw));
} elsif( $traffic eq "bit complement") {
 
$dest_x_ = (~$x) &(0xFF>> (8-$xw));
$dest_y_ = (~$y) &(0xFF>> (8-$yw));
$dest_x = (~$x) &(0xFF>> (8-$xw));
$dest_y = (~$y) &(0xFF>> (8-$yw));
 
 
} elsif( $traffic eq "tornado") {
}elsif( $traffic eq "tornado") {
#[(x+(k/2-1)) mod k, (y+(k/2-1)) mod k],
$dest_x_ = (($x + (($xn/2)-1))%$xn);
$dest_y_ = (($y + (($yn/2)-1))%$yn);
 
} elsif( $traffic eq "random") {
$dest_x = (($x + (($xn/2)-1))%$xn);
$dest_y = (($y + (($yn/2)-1))%$yn);
}elsif( $traffic eq "random") {
#my $num=($y * $xn) + $x;
$pck_num_to_send_=2;
$dest_x_ = $dest % $xn;
$dest_y_ = $dest / $xn;
my $xc=$xn * $yn;
my @randoms=@{$rnd};
my $num=($y * $xn) + $x;
my $dest = @{$randoms[$num]}[$line_num-1];
#print "$num:$dest, "; # \@{ \$randoms\[$num\]\}\[$line_num\]";
$dest_x = $dest % $xn;
$dest_y = $dest / $xn;
}else{#off
} else{#off
print "***********************************$traffic is not defined*******************************************\n";
$dest_x_= $x;
$dest_y_= $y;
$dest_x= $x;
$dest_y= $y;
}
 
#print" ($pck_num_to_send_,$ratio_in,$pck_size_,$dest_x_,$dest_y_,$pck_class_in_,$last_adr_);\n";
return ($pck_num_to_send_,$ratio_in,$pck_size_,$dest_x_,$dest_y_,$pck_class_in_,$last_adr_);
return ($dest_x,$dest_y);
 
 
}
 
 
145,155 → 150,165
 
 
 
sub help {
print
" usage: ./ram_gen X Y TRAFFIC
X: number of node in X direction 2<x<=16
Y: number of node in Y direction 2<y<=16
TRAFFIC : select one of the following traffic patterns :
tornado,
transposed 1,
transposed 2,
random,
";
 
sub gen_synthetic_traffic_ram_line{
my ($emulate, $x, $y, $sample_num,$ratio ,$line_num,$rnd)=@_;
 
}
my $ref=$emulate->object_get_attribute("sample$sample_num","noc_info");
my %noc_info= %$ref;
my $xn=$noc_info{NX};
my $yn=$noc_info{NY};
my $traffic=$emulate->object_get_attribute("sample$sample_num","traffic");
 
my $pck_num_to_send=$emulate->object_get_attribute("sample$sample_num","PCK_NUM_LIMIT");
my $pck_size=$emulate->object_get_attribute("sample$sample_num","PCK_SIZE");
my $pck_class_in=0;
if($line_num==0){ #first ram line shows how many times the ram content must be read
#In random traffic each node sends 2 packets to other NC-1 nodes for (pck_num_to_send/2) times
my $ram_cnt= ($traffic eq 'random')? ($pck_num_to_send/(2*(($xn * $yn)-1)))+1:0 ;
return (0,$ram_cnt);
}
return (0,0) if($line_num>1 && $traffic ne 'random');
return (0,0) if( $line_num>= $xn * $yn);
 
 
#assign {pck_num_to_send_in,ratio_in, pck_size_in,dest_x_in, dest_y_in,pck_class_in, last_adr_in}= q_a;
my $last_adr = ( $traffic ne 'random') ? 1 :
($line_num ==($xn * $yn)-1)? 1 :0;
 
my ($dest_x, $dest_y)=synthetic_destination($traffic,$x,$y,$xn,$yn,$line_num,$rnd);
 
my $vs= ( $traffic eq 'random')? 2 : $pck_num_to_send;
$vs=($vs << 2 )+ ($ratio >>5) ;
 
sub gen_ram{
my ($data,$mem_width)=get_data(@_);
my $result = sprintf("%8x", $data);
 
my $vl= ($ratio %32);
$vl=($vl << PCK_SIZw )+$pck_size;
$vl=($vl << MAXXw )+$dest_x;
$vl=($vl << MAXYw )+$dest_y;
$vl=($vl << MAXCw )+$pck_class_in;
$vl=($vl << 1 )+$last_adr;
return ($vs,$vl);
return $result;
 
}
 
sub random_dest_gen {
my $n=shift;
my @c=(0..$n-1);
my @o;
for (my $i=0; $i<$n; $i++){
my @l= shuffle @c;
@l=remove_scolar_from_array(\@l,$i);
$o[$i]=\@l;
}
return \@o;
 
}
 
sub run_cmd_update_info {
my ($cmd,$info)=@_;
my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($cmd);
if($exit){
add_info($info, "$stdout\n") if(defined $stdout);
add_info($info, "$stderr\n") if(defined $stderr);
 
 
 
 
sub generate_synthetic_traffic_ram{
my ($emulate,$x,$y,$sample_num,$ratio , $file,$rnd,$num)=@_;
my $RAM_size=MAX_PATTERN+4;
 
 
my $line_num;
my $line_value;
my $ram;
if(SIM_RAM_GEN){
my $ext= sprintf("%02u.txt",$num);
open( $ram, '>', RAM_SIM_FILE.$ext) || die "Can not create: \">lib/emulate/emulate_ram.bin\" $!";
}
for ($line_num= 0; $line_num<MAX_PATTERN+4; $line_num++ ) {
my ($value_s,$value_l)=gen_synthetic_traffic_ram_line ($emulate, $x, $y, $sample_num, $ratio ,$line_num,$rnd);
#printf ("\n%08x\t",$value_s);
#printf ("%08x\t",$value_l);
if(SIM_RAM_GEN){
my $s=sprintf("%08X%08x",$value_s,$value_l);
print $ram "$s\n";
}
return $exit;
}
print_32_bit( $file, $value_s); # most significent 32 bit
print_32_bit( $file, $value_l); # list significent 32 bit
 
}
 
if(SIM_RAM_GEN){
close($ram);
}
#print "\n";
 
#last ram three rows reserved for reading data from emulator
 
}
 
 
sub print_32_bit {
my ($file,$v)=@_;
for (my $i= 24; $i >=0 ; $i-=8) {
my $byte= ($v >> $i ) & 0xFF;
print $file pack('C*',$byte);
#printf ("%02x\t",$byte);
}
}
 
 
sub programe_pck_gens{
my ($ref, $traffic,$ratio_in,$info)= @_;
 
sub generate_emulator_ram {
my ($emulate, $sample_num,$ratio_in,$info)=@_;
my $ref=$emulate->object_get_attribute("sample$sample_num","noc_info");
my %noc_info= %$ref;
my $C=$noc_info{C};
my $xn=$noc_info{NX};
my $yn=$noc_info{NY};
#print( "@_\n" );
my $xc=$xn*$yn;
my $rnd=random_dest_gen($xc); # generate a matrix of sudo random number
my $traffic=$emulate->object_get_attribute("sample$sample_num","traffic");
my @traffics=("tornado", "transposed 1", "transposed 2", "bit reverse", "bit complement","random", "hot spot" );
my $xc=$xn * $yn;
my @randoms=@{random_dest_gen($xc)};
 
if ( !defined $xn || $xn!~ /\s*\d+\b/ ){ add_info($info,"programe_pck_gens:invalid X value\n"); help(); return 0;}
if ( !defined $yn || $yn!~ /\s*\d+\b/ ){ add_info($info,"programe_pck_gens:invalid Y value\n"); help(); return 0;}
if ( !grep( /^$traffic$/, @traffics ) ){add_info($info,"programe_pck_gens:$traffic is an invalid Traffic name\n"); help(); return 0;}
if ( $xn <2 || $xn >16 ){ add_info($info,"programe_pck_gens:invalid X value: ($xn). should be between 2 and 16 \n"); help(); return 0;}
if ( $yn <2 || $yn >16 ){ add_info($info,"programe_pck_gens:invalid Y value:($yn). should be between 2 and 16 \n"); help(); return 0;}
 
#reset the FPGA board
#run_cmd_in_back_ground("quartus_stp -t ./lib/tcl/mem.tcl reset");
return if(run_cmd_update_info(RESET_CMD,$info));
#open file pointer
#open(my $file, RAM_BIN_FILE) || die "Can not create: \">lib/emulate/emulate_ram.bin\" $!";
open(my $file, '>', RAM_BIN_FILE) || die "Can not create: \">lib/emulate/emulate_ram.bin\" $!";
 
my $argument='';
my $argument2='';
 
for (my $x=0; $x<$xn; $x=$x+1){
#generate each node ram data
for (my $y=0; $y<$yn; $y=$y+1){
my $num=($y * $xn) + $x;
$num= ($num<=9)? "0$num" : $num;
#add_info($info, "programe M$num\n");
my $line=0;
my ($ram_val,$end,$Dw);
my $repeat=($traffic eq 'random')? "0x2710" : "0x0"; # 10000 : 0;
$argument=undef;
do{
($ram_val,$end,$Dw)=get_data($x, $y, $ref, $traffic,$ratio_in,$num,$line,@{$randoms[$num]}[$line]);
if(!defined $argument ) { #first row
$argument="-n $num -d \"I:".UPDATE_WB_ADDR.",D:$Dw:0,I:".UPDATE_WB_WR_DATA.",D:$Dw:0x$ram_val";
}
#$argument="$argument M$num $line $ram_val";
else {
$argument=$argument.",D:$Dw:0x$ram_val";
for (my $x=0; $x<$xn; $x=$x+1){
my $num=($y * $xn) + $x;
generate_synthetic_traffic_ram($emulate,$x,$y,$sample_num,$ratio_in, $file,$rnd,$num);
 
}
#$argument="$argument M$num $line $ram_val";
$line++;
#print "\$line=$line\n";
} while($end == 0);
$argument=$argument.",I:0\"";
#program the memory
#print "$cmd\n";
my $cmd="$ENV{'PRONOC_WORK'}/toolchain/bin/jtag_main $argument";
return if(run_cmd_update_info ($cmd,$info));
my $source_index=$num+128;
$cmd= "$ENV{'PRONOC_WORK'}/toolchain/bin/jtag_main -n $source_index -d \"I:".SOURCE_ST.",D:100:$repeat,I:0\"";
return if(run_cmd_update_info ($cmd,$info));
#$argument2="$argument2 P$num $repeat";
}
}
close($file);
return 1;
 
}
 
 
#my $file="./RAM/M$num.mif\n";
#unless(open FILE, '>'.$file) { die "\nUnable to create $file\n";}
 
# Write data to the file.
#my $ram_content= gen_ram(0, $x, $y, $xn, $yn, $traffic,"M$num");
#print FILE $ram_content;
# close the file.
#close FILE;
sub programe_pck_gens{
my ($emulate, $sample_num,$ratio_in,$info)= @_;
}
}
#print "quartus_stp -t ./lib/tcl/mem.tcl $argument\n";
# ($result,$exit)=run_cmd_in_back_ground_get_stdout("quartus_stp -t ./lib/tcl/mem.tcl $argument");
#add_info($info,"update packet generators\n");
#print "($result,$exit)\n";
#return 0 if ($exit);
#print "quartus_stp -t ./lib/tcl/source.tcl $argument2\n";
#($result,$exit)=run_cmd_in_back_ground_get_stdout("quartus_stp -t ./lib/tcl/source.tcl $argument2");
#print "($result,$exit)\n";
#return 0 if ($exit);
return 0 if(!generate_emulator_ram($emulate, $sample_num,$ratio_in,$info));
 
# deassert the reset
#reset the FPGA board
#run_cmd_in_back_ground("quartus_stp -t ./lib/tcl/mem.tcl reset");
return 0 if(run_cmd_update_info(reset_cmd(1,1),$info)); #reset both noc and jtag
return 0 if(run_cmd_update_info(reset_cmd(0,1),$info)); #enable jtag keep noc in reset
#programe packet generators rams
my $cmd= "$ENV{'PRONOC_WORK'}/toolchain/bin/jtag_main -n ".JTAG_RAM_INDEX." -w 8 -i ".RAM_BIN_FILE." -c";
#my ($result,$exit) = run_cmd_in_back_ground_get_stdout($cmd);
return if(run_cmd_update_info (UNRESET_CMD,$info));
return 0 if(run_cmd_update_info ($cmd,$info));
#print $result;
return 0 if(run_cmd_update_info(reset_cmd(1,1),$info)); #reset both
return 0 if(run_cmd_update_info(reset_cmd(0,0),$info)); #enable both
#run_cmd_in_back_ground("quartus_stp -t ./lib/tcl/mem.tcl unreset");
#add_info($info,"$r\n");
 
302,9 → 317,26
}
 
 
sub read_jtag_memory{
my $addr=shift;
my $cmd= "$ENV{'PRONOC_WORK'}/toolchain/bin/jtag_main -n ".JTAG_RAM_INDEX." -w 8 -d \"I:".UPDATE_WB_ADDR.",D:64:$addr,I:5,R:64:$addr,I:0\"";
#print "$cmd\n";
my ($result,$exit) = run_cmd_in_back_ground_get_stdout($cmd);
my @q =split (/###read data#/,$result);
my $d=$q[1];
my $s= substr $d,2;
#print "$s\n";
return hex($s);
}
 
 
 
 
 
 
sub read_pack_gen{
my ($ref,$info)= @_;
my ($emulate,$sample_num,$info)= @_;
my $ref=$emulate->object_get_attribute("sample$sample_num","noc_info");
my %noc_info= %$ref;
my $xn=$noc_info{NX};
my $yn=$noc_info{NY};
313,9 → 345,13
my $done=0;
my $counter=0;
while ($done ==0){
usleep(300000);
#my ($result,$exit) = run_cmd_in_back_ground_get_stdout("quartus_stp -t ./lib/tcl/read.tcl done");
my ($result,$exit) = run_cmd_in_back_ground_get_stdout(READ_DONE_CMD);
if($exit != 0 ){
add_info($info,$result);
return undef;
}
my @q =split (/###read data#/,$result);
#print "\$result=$result\n";
322,14 → 358,14
$done=($q[1] eq "0x0")? 0 : 1;
#print "\$q[1]=$q[1] done=$done\n";
usleep(9000);
$counter++;
if($counter == 15){ #
add_info($info,"Done is not asserted. I reset the board and try again\n");
return if(run_cmd_update_info (RESET_CMD,$info));
return if(run_cmd_update_info (reset_cmd(1,1),$info));
#run_cmd_in_back_ground("quartus_stp -t ./lib/tcl/mem.tcl reset");
usleep(300000);
return if(run_cmd_update_info (UNRESET_CMD,$info));
return if(run_cmd_update_info (reset_cmd(0,0),$info));
#run_cmd_in_back_ground("quartus_stp -t ./lib/tcl/mem.tcl unreset");
}
if($counter>30){
340,35 → 376,27
}
add_info($info,"Done is asserted\n");
#print" Done is asserted\n";
#my $i=0;
my %results;
my $sum_of_latency=0;
my $sum_of_pck=0;
for (my $x=0; $x<$xn; $x=$x+1){
for (my $y=0; $y<$yn; $y=$y+1){
for (my $y=0; $y<$yn; $y=$y+1){
for (my $x=0; $x<$xn; $x=$x+1){
my $num=($y * $xn) + $x;
my $source_index=$num+128;
my $cmd= "$ENV{'PRONOC_WORK'}/toolchain/bin/jtag_main -n $source_index -d \"I:".PROBE_ST.",R:100:0,I:0\"";
my ($result,$exit) = run_cmd_in_back_ground_get_stdout($cmd);
my @q =split (/###read data#/,$result);
my $read_addr=($num * RAM_SIZE) + MAX_PATTERN +1;
 
my $sent_pck_addr= sprintf ("%X",$read_addr);
my $got_pck_addr = sprintf ("%X",$read_addr+1);
my $latency_addr = sprintf ("%X",$read_addr+2);
 
$results{$num}{sent_pck}=read_jtag_memory($sent_pck_addr);
$results{$num}{got_pck}=read_jtag_memory($got_pck_addr);
$results{$num}{latency}=read_jtag_memory($latency_addr);
print "read pckgen $num\n";
my $d=$q[1];
#print "num=$num: ddddd=$d\n";
my $s= substr $d,2;
#print "dddddddd=$s\n";
my $latency =substr $s, 0,9;
my $got_pck= substr $s, -16, 8;
my $sent_pck= substr $s, -8;
#print "$latency, $got_pck, $sent_pck\n";
$results{$num}{latency}=hex($latency);
$results{$num}{got_pck}=hex($got_pck);
$results{$num}{sent_pck}=hex($sent_pck);
$sum_of_latency+=hex($latency);
$sum_of_pck+=hex($got_pck);
$sum_of_latency+=$results{$num}{latency};
$sum_of_pck+=$results{$num}{got_pck};
#$i=$i+2;
}}
381,6 → 409,7
 
}
my $avg= ($sum_of_pck>0)? $sum_of_latency/$sum_of_pck : 0;
return sprintf("%.1f", $avg);
}
 
/mpsoc/perl_gui/lib/perl/emulator.pl
13,6 → 13,8
 
use File::Basename;
use File::Path qw/make_path/;
use File::Copy;
use File::Find::Rule;
 
require "widget.pl";
require "emulate_ram_gen.pl";
23,9 → 25,28
use List::MoreUtils qw(uniq);
 
 
# hardware parameters taken from noc_emulator.v
use constant PCK_CNTw =>30; # packet counter width in bits (results in maximum of 2^30 = 1 G packets)
use constant PCK_SIZw =>14; # packet size width in bits (results in maximum packet size of 2^14 = 16 K flit)
use constant MAXXw =>4; # maximum nodes in x dimention is 2^MAXXw equal to 16 nodes in x dimention
use constant MAXYw =>4; # 16 nodes in y dimention : hence max emulator size is 16X16
use constant MAXCw =>4; # 16 message classes
use constant RATIOw =>7; # log2(100)
use constant MAX_PATTERN => 124;
use constant RAM_SIZE => (MAX_PATTERN+4);
 
#use constant MAX_PCK_NUM => (2**PCK_CNTw)-1;
use constant MAX_PCK_NUM => (2**PCK_CNTw)-1;
use constant MAX_PCK_SIZ => (2**PCK_SIZw)-1;
use constant MAX_SIM_CLKs=> 100000000; # simulation end at if clock counter reach this number
 
use constant EMULATION_RTLS => "/mpsoc/src_emulate/rtl/noc_emulator.v , /mpsoc/src_peripheral/jtag/jtag_wb/ , /mpsoc/src_peripheral/ram/generic_ram.v, /mpsoc/src_noc/";
 
 
 
 
 
sub gen_chart {
my $emulate=shift;
my($width,$hight)=max_win_size();
53,6 → 74,10
 
);
 
 
 
 
 
if(defined $sample_num){
my @color;
my $min_y=200;
70,7 → 95,7
}#for
my @x1;
@x1 = uniq(sort {$a<=>$b} @x) if (scalar @x);
 
#print "\@x1=@x1\n";
if (scalar @x1){
$results[0]=\@x1;
for (my $i=1;$i<=$sample_num; $i++) {
77,6 → 102,7
my $j=0;
my $ref=$emulate->object_get_attribute ("sample$i","result");
if(defined $ref){
#print "$i\n";
my %line=%$ref;
foreach my $k (@x1){
$results[$i][$j]=$line{$k};
83,7 → 109,11
$min_y= $line{$k} if (defined $line{$k} && $line{$k}!=0 && $min_y > $line{$k});
$j++;
}#$k
}#if
}#if
else {
$results[$i][$j]=undef;
 
}
}#$i
}#if
98,7 → 128,7
$graphs_info->{$d->{param_name}}= $d->{default_val} if(!defined $graphs_info->{$d->{param_name}});
}
#print "gggggggggggggggg=".$graphs_info->{X_Title};
 
$graph->set (
x_label => $graphs_info->{X_Title},
485,51 → 515,72
 
 
sub get_noc_configuration{
my ($emulate,$n) =@_;
my($width,$hight)=max_win_size();
my $win=def_popwin_size($width/2.5,$hight*.8,"NoC configuration setting");
my $table=def_table(10,2,FALSE);
my $entry=gen_entry();
my $row=0;
my @l;
my @u;
my ($emulate,$n) =@_;
my($width,$hight)=max_win_size();
my $win=def_popwin_size($width/2.5,$hight*.8,"NoC configuration setting");
my $table=def_table(10,2,FALSE);
my $row=0;
my $traffics="tornado,transposed 1,transposed 2,bit reverse,bit complement,random"; #TODO hot spot
$l[$row]=gen_label_help("Select the SRAM Object File (sof) for this NoC configration.","SoF file:");
my $dir = Cwd::getcwd();
my $traffics="tornado,transposed 1,transposed 2,bit reverse,bit complement,random"; #TODO hot spot
my $dir = Cwd::getcwd();
my $open_in = abs_path("$ENV{PRONOC_WORK}/emulate/sof");
attach_widget_to_table ($table,$row,gen_label_in_left("SoF file:"),gen_button_message ("Select the SRAM Object File (sof) for this NoC configration.","icons/help.png"), get_file_name_object ($emulate,"sample$n","sof_file",'sof',$open_in)); $row++;
 
 
 
my @siminfo = (
{ label=>'Configuration name:', param_name=>'line_name', type=>'Entry', default_val=>"NoC$n", content=>undef, info=>"NoC configration name. This name will be shown in load-latency graph for this configuration", param_parent=>"sample$n", ref_delay=> undef},
 
{ label=>"Traffic name", param_name=>'traffic', type=>'Combo-box', default_val=>'random', content=>$traffics, info=>"Select traffic pattern", param_parent=>"sample$n", ref_delay=>undef},
 
{ label=>"Packet size in flit:", param_name=>'PCK_SIZE', type=>'Spin-button', default_val=>4, content=>"2,".MAX_PCK_SIZ.",1", info=>undef, param_parent=>"sample$n", ref_delay=>undef},
 
{ label=>"Packet number limit:", param_name=>'PCK_NUM_LIMIT', type=>'Spin-button', default_val=>1000000, content=>"2,".MAX_PCK_NUM.",1", info=>"Each node stops sending packets when it reaches packet number limit or simulation clock number limit", param_parent=>"sample$n", ref_delay=>undef},
 
{ label=>"Emulation clocks limit:", param_name=>'SIM_CLOCK_LIMIT', type=>'Spin-button', default_val=>MAX_SIM_CLKs, content=>"2,".MAX_SIM_CLKs.",1", info=>"Each node stops sending packets when it reaches packet number limit or simulation clock number limit", param_parent=>"sample$n", ref_delay=>undef},
 
);
foreach my $d ( @siminfo) {
$row=noc_param_widget ($emulate, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,1, $d->{param_parent}, $d->{ref_delay});
}
 
 
 
 
my $l= "Define injection ratios. You can define individual ratios seprating by comma (\',\') or define a range of injection ratios with \$min:\$max:\$step format.
As an example defining 2,3,4:10:2 will result in (2,3,4,6,8,10) injection ratios." ;
my $u=get_injection_ratios ($emulate,"sample$n","ratios");
my $open_in = abs_path("$ENV{PRONOC_WORK}/emulate/sof");
$u[$row]= get_file_name_object ($emulate,"sample$n","sof_file",'sof',$open_in);
$row++;
$l[$row]=gen_label_help("NoC configration name. This name will be shown in load-latency graph for this configuration","Configuration name:");
$u[$row]=gen_entry_object ($emulate,"sample$n","line_name","NoC$n");
$row++;
$l[$row]=gen_label_help("Traffic name","Traffic name:");
$u[$row]=gen_combobox_object ($emulate,"sample$n","traffic",$traffics,"random");
$row++;
$l[$row]=gen_label_help("Define injection ratios. You can define individual ratios seprating by comma (\',\') or define a range of injection ratios with \$min:\$max:\$step format.
As an example definnig 2,3,4:10:2 will results in (2,3,4,6,8,10) injection ratios.","Injection ratios:");
$u[$row]=get_injection_ratios ($emulate,"sample$n","ratios");
$row++;
my $i=0;
for ( $i=0; $i<12; $i++){
if($i<$row){
$table->attach ($l[$i] , 0, 1, $i, $i+1,'fill','shrink',2,2);
$table->attach ($u[$i] , 1, 2, $i, $i+1,'fill','shrink',2,2);
}else{
my $l=gen_label_in_left(" ");
$table->attach_defaults ($l , 0, 1, $i, $i+1);
}
}
attach_widget_to_table ($table,$row,gen_label_in_left("Injection ratios:"),gen_button_message ($l,"icons/help.png") , $u); $row++;
my $scrolled_win = new Gtk2::ScrolledWindow (undef, undef);
$scrolled_win->set_policy( "automatic", "automatic" );
$scrolled_win->add_with_viewport($table);
my $ok = def_image_button('icons/select.png','OK');
my $mtable = def_table(10, 1, TRUE);
 
$mtable->attach_defaults($scrolled_win,0,1,0,9);
$mtable-> attach ($ok , 0, 1, 9, 10,'expand','shrink',2,2);
$win->add ($mtable);
$win->show_all();
 
 
 
 
 
$table->attach ($ok , 1, 2, $i, $i+1,'expand','shrink',2,2);
$ok->signal_connect("clicked"=> sub{
#check if sof file has been selected
my $s=$emulate->object_get_attribute("sample$n","sof_file");
547,9 → 598,14
}
}
});
$win->add($table);
$win->show_all;
 
 
 
}
710,7 → 766,14
$emulate->object_add_attribute ("sample$i","status","failed");
$status=0;
}else { #add info
my $p= do $sof_info ;
my $pp= do $sof_info ;
 
my $p=$pp->{'noc_param'};
 
 
 
 
$status=0 if $@;
message_dialog("Error reading: $@") if $@;
if ($status==1){
878,6 → 941,7
add_info($info, "jtagconfig could not find any USB blaster cable: $stdout \n");
$emulate->object_add_attribute('status',undef,'programer_failed');
set_gui_status($emulate,"ref",2);
#/***/
return;
}else{
add_info($info, "find $usb_blaster\n");
896,7 → 960,12
 
my $cmd = "$Quartus_bin/quartus_pgm -c \"$usb_blaster\" -m jtag -o \"p;$sof\"";
#my $output = `$cmd 2>&1 1>/dev/null`; # either with backticks
 
 
 
#/***/
my ($stdout,$exit)=run_cmd_in_back_ground_get_stdout("$cmd");
if($exit){#programming FPGA board has failed
$emulate->object_add_attribute('status',undef,'programer_failed');
904,27 → 973,29
$emulate->object_add_attribute ("sample$i","status","failed");
set_gui_status($emulate,"ref",2);
next;
}
}
#print "$stdout\n";
# read noc configuration
my $traffic = $emulate->object_get_attribute("sample$i","traffic");
my $ref=$emulate->object_get_attribute("sample$i","noc_info");
foreach my $ratio_in (@ratios){
foreach my $ratio_in (@ratios){
add_info($info, "Configure packet generators for injection ratio of $ratio_in \% \n");
next if(!programe_pck_gens($ref,$traffic,$ratio_in,$info));
my $avg=read_pack_gen($ref,$info);
my $ref=$emulate->object_get_attribute ("sample$i","result");
my %results;
%results= %{$ref} if(defined $ref);
#push(@results,$avg);
$results{$ratio_in}=$avg;
$emulate->object_add_attribute ("sample$i","result",\%results);
set_gui_status($emulate,"ref",2);
add_info($info, "Configure packet generators for injection ratio of $ratio_in \% \n");
next if(!programe_pck_gens($emulate,$i,$ratio_in,$info));
my $avg=read_pack_gen($emulate,$i,$info);
next if (!defined $avg);
my $ref=$emulate->object_get_attribute ("sample$i","result");
my %results;
%results= %{$ref} if(defined $ref);
#push(@results,$avg);
$results{$ratio_in}=$avg;
$emulate->object_add_attribute ("sample$i","result",\%results);
set_gui_status($emulate,"ref",2);
}
$emulate->object_add_attribute ("sample$i","status","done");
978,70 → 1049,40
 
 
sub get_noc_setting_gui {
my ($emulate,$info_text)=@_;
my $table=def_table(20,10,FALSE);# my ($row,$col,$homogeneous)=@_;
my $scrolled_win = new Gtk2::ScrolledWindow (undef, undef);
$scrolled_win->set_policy( "automatic", "automatic" );
$scrolled_win->add_with_viewport($table);
my $row=noc_config ($emulate,$table);
my ($emulate,$info_text)=@_;
my $table=def_table(20,10,FALSE);# my ($row,$col,$homogeneous)=@_;
my $scrolled_win = new Gtk2::ScrolledWindow (undef, undef);
$scrolled_win->set_policy( "automatic", "automatic" );
$scrolled_win->add_with_viewport($table);
my $row=noc_config ($emulate,$table);
my($label,$param,$default,$content,$type,$info);
my @dirs = grep {-d} glob("../src_emulate/fpga/*");
my $fpgas;
foreach my $dir (@dirs) {
my ($name,$path,$suffix) = fileparse("$dir",qr"\..[^.]*$");
$default=$name;
$fpgas= (defined $fpgas)? "$fpgas,$name" : "$name";
my($label,$param,$default,$content,$type,$info);
my @dirs = grep {-d} glob("../src_emulate/fpga/*");
my $fpgas;
foreach my $dir (@dirs) {
my ($name,$path,$suffix) = fileparse("$dir",qr"\..[^.]*$");
$default=$name;
$fpgas= (defined $fpgas)? "$fpgas,$name" : "$name";
}
}
 
$label='simulation param';
$content=$fpgas;
$type='Entry';
$info=" I will add later";
my %simparam;
$simparam{'MAX_PCK_NUM'}=2560000;
$simparam{'MAX_SIM_CLKs'}=1000000;
$simparam{'MAX_PCK_SIZ'}=10;
$simparam{'TIMSTMP_FIFO_NUM'}=16;
foreach my $p (sort keys %simparam){
# print "\$p, \$simparam{\$p}=$p, $simparam{$p}\n";
$row=noc_param_widget ($emulate,$label,$p, $simparam{$p},$type,$content,$info, $table,$row,0,'noc_param');
}
my @fpgainfo = (
{ label=>'FPGA board', param_name=>'FPGA_BOARD', type=>'Combo-box', default_val=>undef, content=>$fpgas, info=>undef, param_parent=>'fpga_param', ref_delay=> undef},
{ label=>'Save as:', param_name=>'SAVE_NAME', type=>"Entry", default_val=>'emulate1', content=>undef, info=>undef, param_parent=>'fpga_param', ref_delay=>undef},
{ label=>"Project directory", param_name=>"SOF_DIR", type=>"DIR_path", default_val=>"$ENV{'PRONOC_WORK'}/emulate", content=>undef, info=>"Define the working directory for generating .sof file", param_parent=>'fpga_param',ref_delay=>undef },
 
);
foreach my $d (@fpgainfo) {
$row=noc_param_widget ($emulate, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,1, $d->{param_parent}, $d->{ref_delay});
}
 
#FPGA NAME
$label='FPGA board';
$param='FPGA_BOARD';
$content=$fpgas;
$type='Combo-box';
$info=" I will add later";
$row=noc_param_widget ($emulate,$label,$param, $default,$type,$content,$info, $table,$row,1,'fpga_param');
#save as
$label='Save as:';
$param='SAVE_NAME';
$default='emulate1';
$content=undef;
$type="Entry";
$info="define generated sof file's name";
$row=noc_param_widget ($emulate,$label,$param, $default,$type,$content,$info, $table,$row,1,'fpga_param');
#Project_dir
$label='Project directory';
$param='SOF_DIR';
$default="../../mpsoc_work/emulate";
$content=undef;
$type="DIR_path";
$info="Define the working directory for generating .sof file";
$row=noc_param_widget ($emulate,$label,$param, $default,$type,$content,$info, $table,$row,1,'fpga_param');
1072,6 → 1113,7
my $fpga_board= $emulate->object_get_attribute ('fpga_param',"FPGA_BOARD");
#create work directory
my $dir_name=$emulate->object_get_attribute ('fpga_param',"SOF_DIR");
$dir_name="$dir_name/$fpga_board";
my $save_name=$emulate->object_get_attribute ('fpga_param',"SAVE_NAME");
$save_name=$fpga_board if (!defined $save_name);
$dir_name= "$dir_name/$save_name";
1080,57 → 1122,89
#copy all noc source codes
my @files =("mpsoc/src_noc/*", "mpsoc/src_emulate/rtl/*","mpsoc/src_peripheral/jtag/jtag_wb/*");
my @files = split(/\s*,\s*/,EMULATION_RTLS);
 
my $dir = Cwd::getcwd();
my $project_dir = abs_path("$dir/../../");
my ($stdout,$exit)=run_cmd_in_back_ground_get_stdout("mkdir -p $dir_name/src/" );
foreach my $f (@files){
($stdout,$exit) =run_cmd_in_back_ground_get_stdout("cp -Rf \"$project_dir\"/$f \"$dir_name/src/\"" );
if($exit != 0 ){ print "$stdout\n"; message_dialog($stdout); return;}
}
copy_file_and_folders(\@files,$project_dir,"$dir_name/src/");
foreach my $f(@files){
my $n="$project_dir/$f";
if (!(-f "$n") && !(-f "$f" ) && !(-d "$n") && !(-d "$f" ) ){
add_info ($info, " WARNING: file/folder \"$f\" ($n) dose not exists \n");
}
}
 
 
#copy fpga board files
($stdout,$exit)=run_cmd_in_back_ground_get_stdout("cp -Rf \"$project_dir/mpsoc/src_emulate/fpga/$fpga_board\"/* \"$dir_name/\"");
if($exit != 0 ){ print "$stdout\n"; message_dialog($stdout); return;}
#generate emulator_top.v file
open(FILE, ">$dir_name/emulator_top.v") || die "Can not open: $!";
print FILE gen_emulate_top_v($emulate);
#generate parameters for emulator_top.v file
my ($localparam, $pass_param)=gen_noc_param_v( $emulate);
open(FILE, ">$dir_name/src/noc_parameters.v") || die "Can not open: $!";
print FILE $localparam;
close(FILE) || die "Error closing file: $!";
open(FILE, ">$dir_name/src/pass_parameters.v") || die "Can not open: $!";
print FILE $pass_param;
close(FILE) || die "Error closing file: $!";
#compile the code
my $Quartus_bin= $ENV{QUARTUS_BIN};
add_info($info, "Start Quartus compilation\n $stdout\n");
($stdout,$exit)=run_cmd_in_back_ground_get_stdout( " cd \"$dir_name/\"
xterm -e $Quartus_bin/quartus_map --64bit $fpga_board --read_settings_files=on
xterm -e $Quartus_bin/quartus_fit --64bit $fpga_board --read_settings_files=on
xterm -e $Quartus_bin/quartus_asm --64bit $fpga_board --read_settings_files=on
xterm -e $Quartus_bin/quartus_sta --64bit $fpga_board
");
if($exit != 0){
print "Quartus compilation failed !\n";
add_info($info, "Quartus compilation failed !\n $stdout\n");
return;
my @compilation_command =("cd \"$dir_name/\" \n xterm -e $Quartus_bin/quartus_map --64bit $fpga_board --read_settings_files=on ",
"cd \"$dir_name/\" \n xterm -e $Quartus_bin/quartus_fit --64bit $fpga_board --read_settings_files=on ",
"cd \"$dir_name/\" \n xterm -e $Quartus_bin/quartus_asm --64bit $fpga_board --read_settings_files=on ",
"cd \"$dir_name/\" \n xterm -e $Quartus_bin/quartus_sta --64bit $fpga_board ");
 
 
 
 
 
foreach my $cmd (@compilation_command){
($stdout,$exit)=run_cmd_in_back_ground_get_stdout( $cmd);
if($exit != 0){
print "Quartus compilation failed !\n";
add_info($info, "Quartus compilation failed !\n$cmd\n $stdout\n");
return;
}
} else {
}
 
#save sof file
my $sofdir="$ENV{PRONOC_WORK}/emulate/sof";
mkpath("$sofdir/",1,01777);
open(FILE, ">$sofdir/$save_name.inf") || die "Can not open: $!";
mkpath("$sofdir/$fpga_board/",1,01777);
open(FILE, ">$sofdir/$fpga_board/$save_name.inf") || die "Can not open: $!";
print FILE perl_file_header("$save_name.inf");
print FILE Data::Dumper->Dump([$emulate->{'noc_param'}],["NoCparam"]);
my %pp;
$pp{'noc_param'}= $emulate->{'noc_param'};
$pp{'fpga_param'}= $emulate->{'fpga_param'};
print FILE Data::Dumper->Dump([\%pp],["emulate_info"]);
close(FILE) || die "Error closing file: $!";
($stdout,$exit)=run_cmd_in_back_ground_get_stdout("cp $dir_name/output_files/$fpga_board.sof $sofdir/$save_name.sof");
if($exit != 0 ){ print "$stdout\n"; message_dialog($stdout); return;}
message_dialog("sof file has been generated successfully"); return;
}
 
 
#find $dir_name -name \*.sof -exec cp '{}' $sofdir/$fpga_board/$save_name.sof"
@files = File::Find::Rule->file()
->name( '*.sof' )
->in( "$dir_name" );
copy($files[0],"$sofdir/$fpga_board/$save_name.sof") or do {
my $err= "Error copy($files[0] , $sofdir/$fpga_board/$save_name.sof";
print "$err\n";
message_dialog($err);
return;
};
message_dialog("sof file has been generated successfully");
/mpsoc/perl_gui/lib/perl/hdr_file_gen.pl
22,7 → 22,7
my @plugs= $soc->soc_get_all_plugs_of_an_instance($id);
my %params= $soc->soc_get_module_param($id);
#add two extra variable the instance name and base addresses
my $core_id= $soc->object_add_attribute('global_param','CORE_ID');
my $core_id= $soc->object_get_attribute('global_param','CORE_ID');
$params{CORE_ID}=(defined $core_id)? $core_id: 0;
$params{IP}=$inst;
$params{CORE}=$id;
64,7 → 64,7
 
 
sub generate_header_file{
my ($soc,$project_dir,$target_dir,$dir)= @_;
my ($soc,$project_dir,$sw_path,$dir)= @_;
my $soc_name=$soc->object_get_attribute('soc_name');
$soc_name = uc($soc_name);
if(!defined $soc_name){$soc_name='soc'};
133,7 → 133,7
open(FILE, ">lib/verilog/tmp") || die "Can not open: $!";
print FILE $content;
close(FILE) || die "Error closing file: $!";
move ("$dir/lib/verilog/tmp","$target_dir/sw/$rename");
move ("$dir/lib/verilog/tmp","$sw_path/$rename");
 
}
148,7 → 148,7
open(FILE, ">lib/verilog/$name.h") || die "Can not open: $!";
print FILE $system_h;
close(FILE) || die "Error closing file: $!";
move ("$dir/lib/verilog/$name.h","$target_dir/sw/");
move ("$dir/lib/verilog/$name.h","$sw_path/");
 
 
/mpsoc/perl_gui/lib/perl/mpsoc_gen.pl
11,7 → 11,6
use POSIX 'strtol';
 
use File::Path;
use File::Find;
use File::Copy;
 
use Cwd 'abs_path';
27,6 → 26,7
require "mpsoc_verilog_gen.pl";
require "hdr_file_gen.pl";
require "readme_gen.pl";
require "soc_gen.pl";
 
sub get_pos{
my ($item,@list)=@_;
51,16 → 51,13
$mpsoc->object_add_attribute_order($attribut1,$param);
$value=$default;
}
if( ! defined $ref_delay){
$ref_delay=($type eq "Entry") ? 10 : 1;
 
}
if ($type eq "Entry"){
$widget=gen_entry($value);
$widget-> signal_connect("changed" => sub{
my $new_param_value=$widget->get_text();
$mpsoc->object_add_attribute($attribut1,$param,$new_param_value);
set_gui_status($mpsoc,"ref",$ref_delay);
set_gui_status($mpsoc,"ref",$ref_delay) if(defined $ref_delay);
 
});
80,7 → 77,7
$widget-> signal_connect("changed" => sub{
my $new_param_value=$widget->get_active_text();
$mpsoc->object_add_attribute($attribut1,$param,$new_param_value);
set_gui_status($mpsoc,"ref",$ref_delay);
set_gui_status($mpsoc,"ref",$ref_delay) if(defined $ref_delay);
 
 
});
97,7 → 94,7
$widget-> signal_connect("value_changed" => sub{
my $new_param_value=$widget->get_value_as_int();
$mpsoc->object_add_attribute($attribut1,$param,$new_param_value);
set_gui_status($mpsoc,"ref",$ref_delay);
set_gui_status($mpsoc,"ref",$ref_delay) if(defined $ref_delay);
 
});
140,7 → 137,7
}
$mpsoc->object_add_attribute($attribut1,$param,$new_val);
#print "\$new_val=$new_val\n";
set_gui_status($mpsoc,"ref",$ref_delay);
set_gui_status($mpsoc,"ref",$ref_delay) if(defined $ref_delay);
});
}
 
150,6 → 147,7
}
elsif ( $type eq "DIR_path"){
$widget =get_dir_in_object ($mpsoc,$attribut1,$param,$value,'ref',10);
set_gui_status($mpsoc,"ref",$ref_delay) if(defined $ref_delay);
}
160,17 → 158,22
 
my $inf_bt= gen_button_message ($info,"icons/help.png");
if($show==1){
my $tmp=gen_label_in_left(" ");
$table->attach_defaults ($label , 0, 4, $row,$row+1);
$table->attach_defaults ($inf_bt , 4, 5, $row,$row+1);
$table->attach_defaults ($widget , 5, 9, $row,$row+1);
$table->attach_defaults ($tmp , 9, 10, $row,$row+1);
attach_widget_to_table ($table,$row,$label,$inf_bt,$widget);
$row++;
}
return $row;
}
 
sub attach_widget_to_table {
my ($table,$row,$label,$inf_bt,$widget)=@_;
my $tmp=gen_label_in_left(" ");
$table->attach ($label , 0, 4, $row,$row+1,'fill','shrink',2,2);
$table->attach ($inf_bt , 4, 5, $row,$row+1,'fill','shrink',2,2);
$table->attach ($widget , 5, 9, $row,$row+1,'fill','shrink',2,2);
$table->attach ($tmp , 9, 10, $row,$row+1,'fill','shrink',2,2);
}
 
 
sub initial_default_param{
my $mpsoc=shift;
my @socs=$mpsoc->mpsoc_get_soc_list();
749,7 → 752,7
$type='Combo-box';
$info=" Input-queued: simple router with low performance and does not support fully adaptive routing.
VC-based routers offer higher performance, fully adaptive routing and traffic isolation for different packet classes.";
$row=noc_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,$show_noc,'noc_type');
$row=noc_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,$show_noc,'noc_type',1);
my $router_type=$mpsoc->object_get_attribute('noc_type',"ROUTER_TYPE");
761,7 → 764,7
$content='2,16,1';
$info= 'Number of NoC routers in row (X dimention)';
$type= 'Spin-button';
$row=noc_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,$show_noc,'noc_param');
$row=noc_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,$show_noc,'noc_param',1);
 
 
772,7 → 775,7
$content='2,16,1';
$info= 'Number of NoC routers in column (Y dimention)';
$type= 'Spin-button';
$row=noc_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,$show_noc,'noc_param');
$row=noc_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,$show_noc,'noc_param',1);
 
if($router_type eq '"VC_BASED"'){
#VC number per port
784,7 → 787,7
$type='Spin-button';
$content='2,16,1';
$info='Number of Virtual Channel per each router port';
$row=noc_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,$show_noc,'noc_param');
$row=noc_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,$show_noc,'noc_param',1);
} else {
$mpsoc->object_add_attribute('noc_param','V',1);
$mpsoc->object_add_attribute('noc_param','C',0);
799,7 → 802,7
$content='2,256,1';
$type='Spin-button';
$info=($router_type eq '"VC_BASED"')? 'Buffer queue size per VC in flits' : 'Buffer queue size in flits';
$row= noc_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,$show_noc,'noc_param');
$row= noc_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,$show_noc,'noc_param',undef);
#packet payload width
$label='payload width';
808,7 → 811,7
$content='32,256,32';
$type='Spin-button';
$info="The packet payload width in bits";
$row=noc_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info,$table,$row,$show_noc,'noc_param');
$row=noc_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info,$table,$row,$show_noc,'noc_param',undef);
 
#topology
$label='Topology';
817,7 → 820,7
$content='"MESH","TORUS"';
$type='Combo-box';
$info="NoC topology";
$row=noc_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,$show_noc,'noc_param');
$row=noc_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,$show_noc,'noc_param',1);
 
#routing algorithm
my $topology=$mpsoc->object_get_attribute('noc_param','TOPOLOGY');
836,7 → 839,7
}
$default=($topology eq '"MESH"')? '"XY"':'"TRANC_XY"';
$info="Select the routing algorithm: XY(DoR) , partially adaptive (Turn models). Fully adaptive (Duato) ";
$row=noc_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,$show_noc,'noc_param');
$row=noc_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,$show_noc,'noc_param',1);
 
 
#SSA
845,8 → 848,8
$default='"NO"';
$content='"YES","NO"';
$type='Combo-box';
$info="Enable single cycle latency on packets traversing in the same direction using static straight allocator (SSA)";
$row=noc_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,$show_noc,'noc_param');
$info="Enable single cycle latency on packets traversing in the same direction using static straight allocator (SSA)";
$row=noc_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,$show_noc,'noc_param',undef);
 
 
 
883,7 → 886,7
$content="0,12,1";
$info="Congestion index determines how congestion information is collected from neighboring routers. Please refer to the usere manual for more information";
$default=3;
$row=noc_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,$adv_set,'noc_param');
$row=noc_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,$adv_set,'noc_param',undef);
}
#Fully adaptive routing setting
899,7 → 902,7
$info="Select the escap VC for fully adaptive routing.";
$row=noc_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,$adv_set,$adv_set,'noc_param');
$row=noc_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,$adv_set, 'noc_param',undef);
}
910,7 → 913,7
$default='"NONATOMIC"';
$content='"ATOMIC","NONATOMIC"';
$type='Combo-box';
$row=noc_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,$adv_set,'noc_param');
$row=noc_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,$adv_set,'noc_param',undef);
 
 
 
923,7 → 926,7
$content='"BASELINE","COMB_SPEC1","COMB_SPEC2","COMB_NONSPEC"';
$type='Combo-box';
$info="The joint VC/ switch allocator type. using canonical combination is not recommanded";
$row=noc_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,$adv_set,'noc_param');
$row=noc_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,$adv_set,'noc_param',undef);
 
}
934,7 → 937,7
$content='"ONE_HOT","BINARY"';
$type='Combo-box';
$info="Crossbar multiplexer type";
$row=noc_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,$adv_set,'noc_param');
$row=noc_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,$adv_set,'noc_param',undef);
if($router_type eq '"VC_BASED"'){
#class
944,7 → 947,7
$info='Number of message classes. Each specific class can use different set of VC';
$content='0,16,1';
$type='Spin-button';
$row=noc_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,$adv_set,'noc_param');
$row=noc_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,$adv_set,'noc_param',5);
 
my $class=$mpsoc->object_get_attribute('noc_param',"C");
961,7 → 964,7
$type="Check-box";
$content=$v;
$info="Select the permitted VCs which the message class $i can be sent via them.";
$row=noc_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,$adv_set,'noc_param');
$row=noc_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,$adv_set,'noc_param',undef);
 
 
}
1138,45 → 1141,57
#
###########
 
sub gen_socs {
my ($mpsoc,$info)=@_;
my $path=$mpsoc->object_get_attribute('setting','soc_path');
$path=~ s/ /\\ /g;
my @socs;
my @files = glob "$path/*.SOC";
my @soc_list=$mpsoc-> mpsoc_get_soc_list();
my @used_socs;
foreach my $soc_name (@soc_list){
my @n=$mpsoc->mpsoc_get_soc_tiles_num($soc_name);
if(scalar @n){
#generate the verilog files of it
push(@used_socs,$soc_name);
}
}
 
 
 
sub gen_all_tiles{
my ($mpsoc,$info, $hw_dir,$sw_dir)=@_;
my $nx= $mpsoc->object_get_attribute('noc_param',"NX");
my $ny= $mpsoc->object_get_attribute('noc_param',"NY");
my $mpsoc_name=$mpsoc->object_get_attribute('mpsoc_name');
my $target_dir = "$ENV{'PRONOC_WORK'}/MPSOC/$mpsoc_name";
for my $p (@files){
# Read
my @generated_tiles;
#print "nx=$nx,ny=$ny\n";
for (my $y=0;$y<$ny;$y++){for (my $x=0; $x<$nx;$x++){
my $tile_num= $y*$nx+$x;
#print "$tile_num\n";
my ($soc_name,$num)= $mpsoc->mpsoc_get_tile_soc_name($tile_num);
my $path=$mpsoc->object_get_attribute('setting','soc_path');
$path=~ s/ /\\ /g;
my $p = "$path/$soc_name.SOC";
my $soc = eval { do $p };
if ($@ || !defined $soc){
show_info(\$info,"**Error reading $p file: $@\n");
next;
}
my $name=$soc->object_get_attribute('soc_name');
if( grep (/^$name$/,@used_socs)){
#generate the soc
generate_soc_files($mpsoc,$soc,$info);
#update core id
$soc->object_add_attribute('global_param','CORE_ID',$tile_num);
};
}
my $sw_path = "$sw_dir/tile$tile_num";
#print "$sw_path\n";
if( grep (/^$soc_name$/,@generated_tiles)){ # This soc is generated before only create the software file
generate_soc($soc,$info,$target_dir,$hw_dir,$sw_path,0,0);
}else{
generate_soc($soc,$info,$target_dir,$hw_dir,$sw_path,0,1);
move ("$hw_dir/$soc_name.v","$hw_dir/tiles/");
}
}}
}
 
 
################
# generate_soc
#################
1190,7 → 1205,7
# Write object file
open(FILE, ">lib/soc/$soc_name.SOC") || die "Can not open: $!";
print FILE perl_file_header("$soc_name.SOC");
print FILE Data::Dumper->Dump([\%$soc],[$soc_name]);
print FILE Data::Dumper->Dump([\%$soc],['mpsoc']);
close(FILE) || die "Error closing file: $!";
# Write verilog file
1203,9 → 1218,9
# copy all files in project work directory
my $dir = Cwd::getcwd();
my $project_dir = abs_path("$dir/../../");
#make target dir
my $project_dir = abs_path("$dir/../../");
my $target_dir = "$project_dir/mpsoc_work/MPSOC/$mpsoc_name";
my $target_dir = "$ENV{'PRONOC_WORK'}/MPSOC/$mpsoc_name";
mkpath("$target_dir/src_verilog/lib/",1,0755);
mkpath("$target_dir/src_verilog/tiles/",1,0755);
mkpath("$target_dir/sw",1,0755);
1271,57 → 1286,141
sub generate_mpsoc{
my ($mpsoc,$info)=@_;
my $name=$mpsoc->object_get_attribute('mpsoc_name');
my $size= (defined $name)? length($name) :0;
if ($size >0){
gen_socs($mpsoc,$info);
my ($file_v,$tmp)=mpsoc_generate_verilog($mpsoc);
if ( $name =~ /\W+/ ){
message_dialog('The mpsoc name must not contain any non-word character:("./\()\':,.;<>~!@#$%^&*|+=[]{}`~?-")!")');
return 0;
}
my $size= (defined $name)? length($name) :0;
if ($size ==0) {
message_dialog("Please define the MPSoC name!");
return 0;
}
# make target dir
my $dir = Cwd::getcwd();
my $target_dir = "$ENV{'PRONOC_WORK'}/MPSOC/$name";
my $hw_dir = "$target_dir/src_verilog";
my $sw_dir = "$target_dir/sw";
mkpath("$hw_dir/lib/",1,0755);
mkpath("$hw_dir/tiles",1,0755);
mkpath("$sw_dir",1,0755);
#generate/copy all tiles HDL/SW codes
gen_all_tiles($mpsoc,$info, $hw_dir,$sw_dir );
#copy all NoC HDL files
my @files = glob( "$dir/../src_noc/*.v" );
copy_file_and_folders(\@files,$dir,"$hw_dir/lib/");
my ($file_v,$top_v)=mpsoc_generate_verilog($mpsoc);
# Write object file
open(FILE, ">lib/mpsoc/$name.MPSOC") || die "Can not open: $!";
print FILE perl_file_header("$name.MPSOC");
print FILE Data::Dumper->Dump([\%$mpsoc],[$name]);
close(FILE) || die "Error closing file: $!";
# Write object file
open(FILE, ">lib/mpsoc/$name.MPSOC") || die "Can not open: $!";
print FILE perl_file_header("$name.MPSOC");
print FILE Data::Dumper->Dump([\%$mpsoc],[$name]);
close(FILE) || die "Error closing file: $!";
# Write verilog file
open(FILE, ">lib/verilog/$name.v") || die "Can not open: $!";
print FILE $file_v;
close(FILE) || die "Error closing file: $!";
# Write verilog file
open(FILE, ">lib/verilog/$name.v") || die "Can not open: $!";
print FILE $file_v;
close(FILE) || die "Error closing file: $!";
my $l=autogen_warning().get_license_header("${name}_top.v");
open(FILE, ">lib/verilog/${name}_top.v") || die "Can not open: $!";
print FILE "$l\n$top_v";
close(FILE) || die "Error closing file: $!";
# copy all files in project work directory
my $dir = Cwd::getcwd();
#make target dir
my $project_dir = abs_path("$dir/../../");
my $target_dir = "$project_dir/mpsoc_work/MPSOC/$name";
mkpath("$target_dir/src_verilog/lib/",1,0755);
mkpath("$target_dir/sw",1,0755);
#gen_socs($mpsoc,$info);
move ("$dir/lib/verilog/$name.v","$target_dir/src_verilog/");
message_dialog("SoC \"$name\" has been created successfully at $target_dir/ " );
#gen_socs($mpsoc,$info);
move ("$dir/lib/verilog/$name.v","$target_dir/src_verilog/");
move ("$dir/lib/verilog/${name}_top.v","$target_dir/src_verilog/");
#generate makefile
open(FILE, ">$sw_dir/Makefile") || die "Can not open: $!";
print FILE mpsoc_sw_make();
close(FILE) || die "Error closing file: $!";
#generate prog_mem
open(FILE, ">$sw_dir/program.sh") || die "Can not open: $!";
print FILE mpsoc_mem_prog();
close(FILE) || die "Error closing file: $!";
message_dialog("SoC \"$name\" has been created successfully at $target_dir/ " );
}else {
message_dialog("Please define the MPSoC name!");
}
return 1;
}
 
sub mpsoc_sw_make {
my $make='
SUBDIRS := $(wildcard */.)
all: $(SUBDIRS)
$(SUBDIRS):
$(MAKE) -C $@
 
.PHONY: all $(SUBDIRS)
clean:
$(MAKE) -C $(CODE_DIR) clean
';
return $make;
}
 
 
sub mpsoc_mem_prog {
my $string='
#!/bin/sh
 
 
JTAG_MAIN="$PRONOC_WORK/toolchain/bin/jtag_main"
 
#reset and disable cpus, then release the reset but keep the cpus disabled
 
$JTAG_MAIN -n 127 -d "I:1,D:2:3,D:2:2,I:0"
 
# jtag instruction
# 0: bypass
# 1: getting data
# jtag data :
# bit 0 is reset
# bit 1 is disable
# I:1 set jtag_enable in active mode
# D:2:3 load jtag_enable data register with 0x3 reset=1 disable=1
# D:2:2 load jtag_enable data register with 0x2 reset=0 disable=1
# I:0 set jtag_enable in bypass mode
 
 
 
#programe the memory
for i in $(ls -d */); do
sh ${i%%/}/write_memory.sh
done
#Enable the cpu
$JTAG_MAIN -n 127 -d "I:1,D:2:0,I:0"
# I:1 set jtag_enable in active mode
# D:2:0 load jtag_enable data register with 0x0 reset=0 disable=0
# I:0 set jtag_enable in bypass mode
';
return $string;
}
 
 
sub get_tile_LIST{
my ($mpsoc,$x,$y,$soc_num,$row,$table)=@_;
my $instance_name=$mpsoc->mpsoc_get_instance_info($soc_num);
1771,40 → 1870,4
 
}
 
##########
 
##########
sub copy_noc_files{
my ($project_dir,$dest)=@_;
my @noc_files=(
'/mpsoc/src_noc/arbiter.v',
'/mpsoc/src_noc/baseline.v',
'/mpsoc/src_noc/canonical_credit_count.v',
'/mpsoc/src_noc/class_table.v',
'/mpsoc/src_noc/combined_vc_sw_alloc.v',
'/mpsoc/src_noc/comb_nonspec.v',
'/mpsoc/src_noc/comb_spec2.v',
'/mpsoc/src_noc/comb-spec1.v',
'/mpsoc/src_noc/congestion_analyzer.v',
'/mpsoc/src_noc/credit_count.v',
'/mpsoc/src_noc/crossbar.v',
'/mpsoc/src_noc/flit_buffer.v',
'/mpsoc/src_noc/inout_ports.v',
'/mpsoc/src_noc/inout_ports.v.classic',
'/mpsoc/src_noc/input_ports.v',
'/mpsoc/src_noc/main_comp.v',
'/mpsoc/src_noc/noc.v',
'/mpsoc/src_noc/route_mesh.v',
'/mpsoc/src_noc/router.v',
'/mpsoc/src_noc/route_torus.v',
'/mpsoc/src_noc/routing.v',
'/mpsoc/src_noc/vc_alloc_request_gen.v',
'/mpsoc/src_noc/ss_allocator.v');
foreach my $f (@noc_files){
copy ("$project_dir$f",$dest);
}
}
/mpsoc/perl_gui/lib/perl/mpsoc_verilog_gen.pl
19,7 → 19,10
//IO
\tinput\tclk,reset;\n";
my $param_as_in_v;
# generate top
my $top_io="\t\t.clk(clk) ,\n\t\t.reset(reset_ored_jtag)";
#generate socs_parameter
my $socs_param= gen_socs_param($mpsoc);
27,10 → 30,10
my ($noc_param,$pass_param)=gen_noc_param_v($mpsoc);
#generate the noc
my $noc_v=gen_noc_v();
my $noc_v=gen_noc_v($pass_param);
#generate socs
my $socs_v=gen_socs_v($mpsoc,\$io_v,\$io_def_v);
my $socs_v=gen_socs_v($mpsoc,\$io_v,\$io_def_v,\$top_io);
#functions
my $functions=get_functions();
44,8 → 47,40
add_text_to_string (\$mpsoc_v,$socs_v);
add_text_to_string (\$mpsoc_v,"\nendmodule\n");
my $top_v = (defined $param_as_in_v )? "module ${mpsoc_name}_top #(\n $param_as_in_v\n)(\n$io_v\n);\n": "module ${mpsoc_name}_top (\n $io_v\n);\n";
add_text_to_string (\$top_v,$socs_param);
add_text_to_string (\$top_v,$io_def_v);
add_text_to_string(\$top_v,"
// Allow software to remote reset/enable the cpu via jtag
 
wire jtag_cpu_en, jtag_system_reset;
 
jtag_system_en jtag_en (
.cpu_en(jtag_cpu_en),
.system_reset(jtag_system_reset)
return $mpsoc_v;
);
wire reset_ored_jtag = reset | jtag_system_reset;
wire processors_en_anded_jtag = processors_en & jtag_cpu_en;
${mpsoc_name} the_${mpsoc_name} (
$top_io
);
 
endmodule
 
 
");
#my $ins= gen_mpsoc_instance_v($mpsoc,$mpsoc_name,$param_pass_v);
 
#add_text_to_string(\$top_v,$local_param_v_all."\n".$io_full_v_all);
#add_text_to_string(\$top_v,$ins);
return ($mpsoc_v,$top_v);
}
 
sub get_functions{
173,8 → 208,8
 
 
sub gen_noc_v{
my $pass_param = shift;
my $noc = read_file("../src_noc/noc.v");
my @noc_param=$noc->get_modules_parameters_not_local_order('noc');
206,9 → 241,9
foreach my $p (@noc_param){
my $param=($i==0)? "\t\t.$p($p)":",\n\t\t.$p($p)";
$i=1;
add_text_to_string(\$noc_v,$param);
#add_text_to_string(\$noc_v,$param);
}
add_text_to_string(\$noc_v,"\n\t)\n\tthe_noc\n\t(\n");
add_text_to_string(\$noc_v,"$pass_param\n\t)\n\tthe_noc\n\t(\n");
my @ports= $noc->get_module_ports_order('noc');
$i=0;
293,7 → 328,8
 
 
sub gen_socs_v{
my ($mpsoc,$io_v_ref,$io_def_v)=@_;
my ($mpsoc,$io_v_ref,$io_def_v,$top_io_ref)=@_;
#generate loop
# my $socs_v='
346,13 → 382,16
for (my $y=0;$y<$ny;$y++){
for (my $x=0; $x<$nx;$x++){
my $tile_num=($nx*$y)+ $x;
my ($soc_name,$n,$soc_num)=$mpsoc->mpsoc_get_tile_soc_name($tile_num);
if(defined $soc_name) {
my ($soc_v,$en)= gen_soc_v($mpsoc,$soc_name,$tile_num,$x,$y,$soc_num,$io_v_ref,$io_def_v);
my ($soc_v,$en)= gen_soc_v($mpsoc,$soc_name,$tile_num,$x,$y,$soc_num,$io_v_ref,$io_def_v,$top_io_ref);
add_text_to_string(\$socs_v,$soc_v);
$processors_en|=$en;
}else{
#this tile is not connected to any ip. the noc input ports will be connected to ground
my $soc_v="\n\n // Tile:$tile_num (x=$x,y=$y) is not assigned to any ip\n";
371,6 → 410,7
if($processors_en){
add_text_to_string($io_v_ref,",\n\tprocessors_en");
add_text_to_string($io_def_v,"\t input processors_en;");
add_text_to_string($top_io_ref,",\n\t\t.processors_en(processors_en_anded_jtag)");
}
386,7 → 426,7
 
 
sub gen_soc_v{
my ($mpsoc,$soc_name,$tile_num,$x,$y,$soc_num,$io_v_ref,$io_def_v)=@_;
my ($mpsoc,$soc_name,$tile_num,$x,$y,$soc_num,$io_v_ref,$io_def_v,$top_io_ref)=@_;
my $soc_v;
my $processor_en=0;
my $xw= log2($mpsoc->object_get_attribute('noc_param',"NX"));
425,8 → 465,7
 
my $dir = Cwd::getcwd();
my $mpsoc_name=$mpsoc->object_get_attribute('mpsoc_name');
my $project_dir = abs_path("$dir/../../");
my $target_dir = "$project_dir/mpsoc_work/MPSOC/$mpsoc_name";
my $target_dir = "$ENV{'PRONOC_WORK'}/MPSOC/$mpsoc_name";
my $soc_file="$target_dir/src_verilog/tiles/$soc_name.v";
my $vdb =read_file($soc_file);
510,6 → 549,7
}
#io name
add_text_to_string($io_v_ref,",\n\t$io_port");
add_text_to_string($top_io_ref,",\n\t\t.$io_port($io_port)");
#io definition
my $new_range = add_instantc_name_to_parameters(\%params,"${soc_name}_$soc_num",$range);
#my $new_range=$range;
/mpsoc/perl_gui/lib/perl/soc_gen.pl
8,7 → 8,7
use POSIX 'strtol';
 
use File::Path;
use File::Find;
#use File::Find;
use File::Copy;
use File::Copy::Recursive qw(dircopy);
use Cwd 'abs_path';
166,7 → 166,8
$max=~ s/\D//g;
$step=~ s/\D//g;
my $spin=gen_spin($min,$max,$step);
$spin->set_value($value);
if(defined $value) {$spin->set_value($value);}
else {$spin->set_value($min);}
$table->attach ($spin, 3, 4, $row, $row+1,'expand','shrink',2,2);
$spin-> signal_connect("value_changed" => sub{ $new_param_value{$p}=$spin->get_value_as_int(); });
853,82 → 854,74
#################
 
sub generate_soc{
my ($soc,$info)=@_;
my $name=$soc->object_get_attribute('soc_name');
if (length($name)>0){
my @tmp=split('_',$name);
if ( $tmp[-1] =~ /^[0-9]+$/ ){
message_dialog("The soc name must not end with '_number'!");
return 0;
}
my ($soc,$info,$target_dir,$hw_path,$sw_path,$gen_top,$gen_hw_lib)=@_;
my $name=$soc->object_get_attribute('soc_name');
my ($file_v,$top_v,$readme,$prog)=soc_generate_verilog($soc);
my ($file_v,$top_v,$readme)=soc_generate_verilog($soc);
# Write object file
open(FILE, ">lib/soc/$name.SOC") || die "Can not open: $!";
print FILE perl_file_header("$name.SOC");
print FILE Data::Dumper->Dump([\%$soc],['soc']);
close(FILE) || die "Error closing file: $!";
# Write object file
open(FILE, ">lib/soc/$name.SOC") || die "Can not open: $!";
print FILE perl_file_header("$name.SOC");
print FILE Data::Dumper->Dump([\%$soc],[$name]);
close(FILE) || die "Error closing file: $!";
# Write verilog file
open(FILE, ">lib/verilog/$name.v") || die "Can not open: $!";
print FILE $file_v;
close(FILE) || die "Error closing file: $!";
# Write verilog file
open(FILE, ">lib/verilog/$name.v") || die "Can not open: $!";
print FILE $file_v;
close(FILE) || die "Error closing file: $!";
# Write Top module file
# Write Top module file
if($gen_top){
my $l=autogen_warning().get_license_header("${name}_top.v");
open(FILE, ">lib/verilog/${name}_top.v") || die "Can not open: $!";
print FILE "$l\n$top_v";
close(FILE) || die "Error closing file: $!";
}
# Write readme file
open(FILE, ">lib/verilog/README") || die "Can not open: $!";
print FILE $readme;
close(FILE) || die "Error closing file: $!";
 
 
# Write memory prog file
open(FILE, ">lib/verilog/write_memory.sh") || die "Can not open: $!";
print FILE $prog;
close(FILE) || die "Error closing file: $!";
my $dir = Cwd::getcwd();
my $project_dir = abs_path("$dir/../../");
if($gen_hw_lib){
 
#make target dir
my $hw_lib="$hw_path/lib";
mkpath("$hw_lib/",1,01777);
mkpath("$sw_path/",1,01777);
#copy hdl codes in src_verilog
# Write readme file
open(FILE, ">lib/verilog/README") || die "Can not open: $!";
print FILE $readme;
close(FILE) || die "Error closing file: $!";
# copy all files in project work directory
my $dir = Cwd::getcwd();
#make target dir
my $project_dir = abs_path("$dir/../../");
my $target_dir = "$project_dir/mpsoc_work/SOC/$name";
mkpath("$target_dir/src_verilog/lib/",1,01777);
mkpath("$target_dir/sw",1,01777);
#copy hdl codes in src_verilog
my ($file_ref,$warnings)= get_all_files_list($soc,"hdl_files");
my ($file_ref,$warnings)= get_all_files_list($soc,"hdl_files");
copy_file_and_folders($file_ref,$project_dir,"$target_dir/src_verilog/lib");
copy_file_and_folders($file_ref,$project_dir,$hw_lib);
show_info(\$info,$warnings) if(defined $warnings);
#copy jtag control files
my @jtags=(("/mpsoc/src_peripheral/jtag/jtag_wb"),("jtag"));
copy_file_and_folders(\@jtags,$project_dir,"$target_dir/src_verilog/lib");
 
#my @pathes=("$dir/../src_peripheral","$dir/../src_noc","$dir/../src_processor");
#foreach my $p(@pathes){
# find(
# sub {
# return unless ( -f $_ );
# $_ =~ /\.v$/ && copy( $File::Find::name, "$target_dir/src_verilog/lib/" );
# },
# $p
# );
#}
#copy jtag control files
my @jtags=(("/mpsoc/src_peripheral/jtag/jtag_wb"),("jtag"));
copy_file_and_folders(\@jtags,$project_dir,$hw_lib);
move ("$dir/lib/verilog/$name.v","$hw_path/");
move ("$dir/lib/verilog/${name}_top.v","$hw_path/");
move ("$dir/lib/verilog/README" ,"$sw_path/");
move ("$dir/lib/verilog/write_memory.sh" ,"$sw_path/");
}
# Copy Software files
my ($file_ref,$warnings)= get_all_files_list($soc,"sw_files");
copy_file_and_folders($file_ref,$project_dir,$sw_path);
move ("$dir/lib/verilog/$name.v","$target_dir/src_verilog/");
move ("$dir/lib/verilog/${name}_top.v","$target_dir/src_verilog/");
move ("$dir/lib/verilog/README" ,"$target_dir/sw/");
# Copy Software files
($file_ref,$warnings)= get_all_files_list($soc,"sw_files");
copy_file_and_folders($file_ref,$project_dir,"$target_dir/sw");
# Write system.h and Software gen files
generate_header_file($soc,$project_dir,$target_dir,$dir);
# Write system.h and Software gen files
generate_header_file($soc,$project_dir,$sw_path,$dir);
935,7 → 928,7
 
 
# Write main.c file if not exist
my $n="$target_dir/sw/main.c";
my $n="$sw_path/main.c";
if (!(-f "$n")) {
# Write main.c
open(FILE, ">$n") || die "Can not open: $!";
947,15 → 940,8
message_dialog("SoC \"$name\" has been created successfully at $target_dir/ " );
exec($^X, $0, @ARGV);# reset ProNoC to apply changes
}else {
message_dialog("Please define the SoC name!");
}
return 1;
 
}
 
 
1419,8 → 1405,8
my $soc = soc->soc_new();
set_gui_status($soc,"ideal",0);
#my $soc= eval { do 'lib/soc/soc.SOC' };
#message_dialog("$ENV{'PRONOC_WORK'}\n");
# main window
#my $window = def_win_size(1000,800,"Top");
# The main table containg the lib tree, selected modules and info section
1471,6 → 1457,55
$main_table->attach ($generate, 10, 12, 19,20,'expand','shrink',2,2);
 
$generate-> signal_connect("clicked" => sub{
my $name=$soc->object_get_attribute('soc_name');
if (length($name)==0){
message_dialog("Please define the SoC name!");
return ;
}
my @tmp=split('_',$name);
if ( $tmp[-1] =~ /^[0-9]+$/ ){
message_dialog("The soc name must not end with '_number'!");
return ;
}
if ( $name =~ /\W+/ ){
message_dialog('The soc name must not contain any non-word character:("./\()\':,.;<>~!@#$%^&*|+=[]{}`~?-")!")');
return ;
}
 
my $target_dir = "$ENV{'PRONOC_WORK'}/SOC/$name";
my $hw_dir = "$target_dir/src_verilog";
my $sw_path = "$target_dir/sw";
$soc->object_add_attribute('global_param','CORE_ID',0);
generate_soc($soc,$info,$target_dir,$hw_dir,$sw_path,1,1);
message_dialog("SoC \"$name\" has been created successfully at $target_dir/ " );
exec($^X, $0, @ARGV);# reset ProNoC to apply changes
});
 
$wb-> signal_connect("clicked" => sub{
wb_address_setting($soc);
});
 
$open-> signal_connect("clicked" => sub{
load_soc($soc,$info);
});
 
my $sc_win = new Gtk2::ScrolledWindow (undef, undef);
$sc_win->set_policy( "automatic", "automatic" );
$sc_win->add_with_viewport($main_table);
 
 
 
#check soc status every 0.5 second. referesh device table if there is any changes
Glib::Timeout->add (100, sub{
my ($state,$timeout)= get_gui_status($soc);
1489,28 → 1524,9
return TRUE;
} );
$generate-> signal_connect("clicked" => sub{
generate_soc($soc,$info);
$refresh_dev_win->clicked;
});
 
$wb-> signal_connect("clicked" => sub{
wb_address_setting($soc);
});
 
$open-> signal_connect("clicked" => sub{
load_soc($soc,$info);
});
 
my $sc_win = new Gtk2::ScrolledWindow (undef, undef);
$sc_win->set_policy( "automatic", "automatic" );
$sc_win->add_with_viewport($main_table);
 
return $sc_win;
#return $main_table;
/mpsoc/perl_gui/lib/perl/temp.pl
1,9 → 1,43
#!/usr/bin/perl
use warnings;
use strict;
use File::System
use List::Util 'shuffle';
 
my $fs = File::System->new('Real');
my $fs = File::System->new('My::File::System::Foo');
(system("ls"));
 
 
sub remove_scolar_from_array{
my ($array_ref,$item)=@_;
my @array=@{$array_ref};
my @new;
foreach my $p (@array){
if($p ne $item ){
push(@new,$p);
}
}
return @new;
}
 
sub random_dest_gen {
my $n=shift;
my @c=(0..$n-1);
my @o;
for (my $i=0; $i<$n; $i++){
my @l= shuffle @c;
@l=remove_scolar_from_array(\@l,$i);
$o[$i]=\@l;
}
return \@o;
 
}
 
my $ref=random_dest_gen(16);
my @random= @{$ref};
 
for (my $i=0; $i<16; $i++){
for (my $j=0; $j<15; $j++){
print @{$random[$i]}[$j];
print ",";
}
print "\n";
}
/mpsoc/perl_gui/lib/perl/verilog_gen.pl
27,7 → 27,13
my @instances=$soc->soc_get_all_instances();
my $io_sim_v;
my $param_as_in_v="\tparameter\tCORE_ID=0";
my $core_id= $soc->object_get_attribute('global_param','CORE_ID');
$core_id= 0 if(!defined $core_id);
my $param_as_in_v="\tparameter\tCORE_ID=$core_id";
 
 
 
 
my $param_pass_v="\t.CORE_ID(CORE_ID)";
my $body_v;
88,8 → 94,8
 
add_text_to_string(\$top_v,$local_param_v_all."\n".$io_full_v_all);
add_text_to_string(\$top_v,$ins);
my $readme=gen_system_info($soc,$param_as_in_v);
return ("$soc_v",$top_v,$readme);
my ($readme,$prog)=gen_system_info($soc,$param_as_in_v);
return ("$soc_v",$top_v,$readme,$prog);
 
 
}
647,15 → 653,22
#my (@newbase,@newend,@connects);
 
$jtag='';
 
my @all_instances=$soc->soc_get_all_instances();
 
my @all_instances=$soc->soc_get_all_instances();
my %jtagwb; my %ram;
foreach my $instance_id (@all_instances){
my $category=$soc->soc_get_category($instance_id);
my @plugs= $soc->soc_get_all_plugs_of_an_instance($instance_id);
foreach my $plug (@plugs){
my @nums=$soc->soc_list_plug_nums($instance_id,$plug);
foreach my $num (@nums){
my ($addr,$base,$end,$name,$connect_id,$connect_socket,$connect_socket_num)=$soc->soc_get_plug($instance_id,$plug,$num);
my $instance_name=$soc->soc_get_instance_name($instance_id);
my $connect_name=$soc->soc_get_instance_name($connect_id);
#get interfaces
663,7 → 676,12
$base=sprintf("0x%08x", $base);
$end=sprintf("0x%08x", $end);
add_text_to_string(\$wb_slaves, "\t$instance_name, $name, $connect_name, $base, $end\n");
add_text_to_string(\$wb_slaves, "\t$instance_name, $name, $connect_name, $base, $end\n");
if ($category eq 'RAM') {
$ram{$instance_id}{'base'}=$base;
$ram{$instance_id}{'end'}=$end;
$ram{$instance_id}{'connect'}=$connect_id;
}
}#if
elsif((defined $connect_socket) && ($connect_socket eq 'wb_master')){
676,8 → 694,9
# get jtag_wbs
if((defined $connect_socket) && ($connect_socket eq 'wb_master') && ($instance_id =~ /jtag_wb/)){
my $index=$soc->soc_get_module_param_value($instance_id,'VJTAG_INDEX');
add_text_to_string(\$jtag, "\t$instance_name, $connect_name, $index\n");
$jtagwb{$connect_id}{'index'}=$index;
}
 
686,7 → 705,70
}#foreach my $plug
}#foreach my $instance_id
 
#Generate memory programming command
my $prog='#!/bin/sh
 
JTAG_MAIN="$PRONOC_WORK/toolchain/bin/jtag_main"
 
';
 
 
foreach my $instance_id (@all_instances){
my $category=$soc->soc_get_category($instance_id);
if ($category eq 'RAM') {
my $jtag_connect=$soc->soc_get_module_param_value($instance_id,'JTAG_CONNECT');
my $aw=$soc->soc_get_module_param_value($instance_id,'Aw');
my $dw=$soc->soc_get_module_param_value($instance_id,'Dw');
my $JTAG_INDEX=$soc->soc_get_module_param_value($instance_id,'JTAG_INDEX');
#check if jtag_index is a parameter
my $v=$soc->soc_get_module_param_value($instance_id,$JTAG_INDEX);
$JTAG_INDEX = $v if (defined $v);
$v= $soc->object_get_attribute('global_param',$JTAG_INDEX);
$JTAG_INDEX = $v if (defined $v);
my $BINFILE=$soc->soc_get_module_param_value($instance_id,'INIT_FILE_NAME');
($BINFILE)=$BINFILE=~ /"([^"]*)"/ if(defined $BINFILE);
$BINFILE=(defined $BINFILE) ? $BINFILE.'.bin' : 'ram0.bin';
my $OFSSET="0x00000000";
my $end=((1<<$aw)*($dw/8))-1;
my $BOUNDRY=sprintf("0x%08x", $end);
if($jtag_connect =~ /JTAG_WB/){
$prog= "$prog \$JTAG_MAIN -n $JTAG_INDEX -s \"$OFSSET\" -e \"$BOUNDRY\" -i \"$BINFILE\" -c";
#print "prog= $prog\n";
}elsif ($jtag_connect eq 'ALTERA_IMCE'){
#TODO add later
} else{
#disabled check if its connected to jtag_wb via the bus
my $connect_id = $ram{$instance_id}{'connect'};
my $OFSSET = $ram{$instance_id}{'base'};
my $BOUNDRY = $ram{$instance_id}{'end'};
if(defined $connect_id){
#print "id=$connect_id\n";
my $JTAG_INDEX= $jtagwb{$connect_id}{'index'};
if(defined $JTAG_INDEX){
$v= $soc->object_get_attribute('global_param',$JTAG_INDEX);
$JTAG_INDEX = $v if (defined $v);
$prog= "$prog \$JTAG_MAIN -n $JTAG_INDEX -s \"$OFSSET\" -e \"$BOUNDRY\" -i \"$BINFILE\" -c";
#print "prog= $prog\n";
}
}
}
}
}
 
 
my $lisence= get_license_header("readme");
my $warning=autogen_warning();
 
705,21 → 787,8
 
sh program.sh
 
but first, you need to update these variables inside the program.sh file
 
OFSSET= [offset_in_hex]
The RAM wishbone bus offset address e.g : 0x0000000.
BOUNDRY=[boundry_in_hex ]
The RAM boundary address in hex e.g: 0x00003fff.
VJTAG_INDEX=[Virtual jtag index number]
BINFILE=[file_name]
memory file in binary format. eg ram00.bin
 
 
you can get OFSSET, BOUNDRY and VJTAG_INDEX values from following
wishbone buse(s) info & Jtag to wishbone interface (jtag_wb) info sections.
Also check the memory and jtag_wb are connected to the same bus (have same \"connected to\" filed).
 
***************************
** soc parameters
***************************
747,7 → 816,10
 
";
 
return $readme;
 
 
 
return ($readme,$prog);
/mpsoc/perl_gui/lib/soc/lm32_test.SOC File deleted
mpsoc/perl_gui/lib/soc/lm32_test.SOC Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: mpsoc/perl_gui/lib/soc/aemb_test.SOC =================================================================== --- mpsoc/perl_gui/lib/soc/aemb_test.SOC (revision 27) +++ mpsoc/perl_gui/lib/soc/aemb_test.SOC (nonexistent) @@ -1,619 +0,0 @@ -$aemb_test = bless( { - 'hdl_files' => undef, - 'modules' => {}, - 'soc_name' => 'aemb_test', - 'top_ip' => bless( { - 'ports' => { - 'led_port_o' => { - 'intfc_port' => 'IO', - 'intfc_name' => 'IO', - 'instance_name' => 'gpo0', - 'range' => 'led_PORT_WIDTH-1 : 0', - 'type' => 'output' - }, - 'ss_reset_in' => { - 'intfc_port' => 'reset_i', - 'intfc_name' => 'plug:reset[0]', - 'instance_name' => 'clk_source0', - 'range' => '', - 'type' => 'input' - }, - 'ss_clk_in' => { - 'intfc_port' => 'clk_i', - 'intfc_name' => 'plug:clk[0]', - 'instance_name' => 'clk_source0', - 'range' => '', - 'type' => 'input' - }, - 'aeMB_sys_ena_i' => { - 'intfc_port' => 'enable_i', - 'intfc_name' => 'plug:enable[0]', - 'instance_name' => 'aeMB0', - 'range' => '', - 'type' => 'input' - } - }, - 'interface' => { - 'plug:enable[0]' => { - 'ports' => { - 'aeMB_sys_ena_i' => { - 'intfc_port' => 'enable_i', - 'instance_name' => 'aeMB0', - 'range' => '', - 'type' => 'input' - } - } - }, - 'IO' => { - 'ports' => { - 'led_port_o' => { - 'intfc_port' => 'IO', - 'instance_name' => 'gpo0', - 'range' => 'led_PORT_WIDTH-1 : 0', - 'type' => 'output' - } - } - }, - 'plug:clk[0]' => { - 'ports' => { - 'ss_clk_in' => { - 'intfc_port' => 'clk_i', - 'instance_name' => 'clk_source0', - 'range' => '', - 'type' => 'input' - } - } - }, - 'plug:reset[0]' => { - 'ports' => { - 'ss_reset_in' => { - 'intfc_port' => 'reset_i', - 'instance_name' => 'clk_source0', - 'range' => '', - 'type' => 'input' - } - } - } - }, - 'instance_ids' => { - 'aeMB0' => { - 'ports' => { - 'aeMB_sys_ena_i' => { - 'intfc_port' => 'enable_i', - 'intfc_name' => 'plug:enable[0]', - 'range' => '', - 'type' => 'input' - } - }, - 'module_name' => 'aeMB_top', - 'category' => 'Processor', - 'instance' => 'aeMB', - 'module' => 'aeMB' - }, - 'clk_source0' => { - 'ports' => { - 'ss_reset_in' => { - 'intfc_port' => 'reset_i', - 'intfc_name' => 'plug:reset[0]', - 'range' => '', - 'type' => 'input' - }, - 'ss_clk_in' => { - 'intfc_port' => 'clk_i', - 'intfc_name' => 'plug:clk[0]', - 'range' => '', - 'type' => 'input' - } - }, - 'module_name' => 'clk_source', - 'category' => 'source', - 'instance' => 'ss', - 'module' => 'clk_source' - }, - 'gpo0' => { - 'parameters' => { - 'led_PORT_WIDTH' => { - 'info' => 'output port width', - 'deafult' => ' 1', - 'global_param' => 1, - 'content' => '1,32,1', - 'redefine_param' => 1, - 'type' => 'Spin-button' - } - }, - 'ports' => { - 'led_port_o' => { - 'intfc_port' => 'IO', - 'intfc_name' => 'IO', - 'range' => 'led_PORT_WIDTH-1 : 0', - 'type' => 'output' - } - }, - 'module_name' => 'gpo', - 'category' => 'GPI', - 'instance' => 'led', - 'module' => 'gpo' - }, - 'wishbone_bus0' => { - 'module_name' => 'wishbone_bus', - 'category' => 'bus', - 'instance' => 'bus', - 'module' => 'wishbone_bus' - }, - 'Altera_single_port_ram0' => { - 'parameters' => { - 'ram_Dw' => { - 'info' => undef, - 'deafult' => '32', - 'global_param' => 1, - 'content' => '8,1024,1', - 'redefine_param' => 1, - 'type' => 'Spin-button' - }, - 'ram_Aw' => { - 'info' => undef, - 'deafult' => 12, - 'global_param' => 1, - 'content' => '4,31,1', - 'redefine_param' => 1, - 'type' => 'Spin-button' - } - }, - 'module_name' => 'Altera_single_port_ram', - 'category' => 'RAM', - 'instance' => 'ram', - 'module' => 'Altera_single_port_ram' - } - } - }, 'ip_gen' ), - 'instances' => { - 'aeMB0' => { - 'aeMB0' => {}, - 'instance_name' => 'aeMB', - 'plugs' => { - 'wb_master' => { - 'connection_num' => undef, - 'value' => 2, - 'type' => 'num', - 'nums' => { - '1' => { - 'connect_socket_num' => '1', - 'connect_id' => 'wishbone_bus0', - 'name' => 'dwb', - 'connect_socket' => 'wb_master' - }, - '0' => { - 'connect_socket_num' => '0', - 'connect_id' => 'wishbone_bus0', - 'name' => 'iwb', - 'connect_socket' => 'wb_master' - } - } - }, - 'interrupt_cpu' => { - 'connection_num' => undef, - 'value' => 1, - 'nums' => { - '0' => { - 'connect_id' => 'NC', - 'connect_socket_num' => undef, - 'name' => 'intrp', - 'connect_socket' => undef - } - }, - 'type' => 'num' - }, - 'enable' => { - 'connection_num' => undef, - 'value' => 1, - 'nums' => { - '0' => { - 'connect_id' => 'IO', - 'connect_socket_num' => undef, - 'name' => 'enable', - 'connect_socket' => undef - } - }, - 'type' => 'num' - }, - 'clk' => { - 'connection_num' => undef, - 'value' => 1, - 'type' => 'num', - 'nums' => { - '0' => { - 'connect_id' => 'clk_source0', - 'connect_socket_num' => '0', - 'name' => 'clk', - 'connect_socket' => 'clk' - } - } - }, - 'reset' => { - 'connection_num' => undef, - 'value' => 1, - 'nums' => { - '0' => { - 'connect_socket_num' => '0', - 'connect_id' => 'clk_source0', - 'name' => 'reset', - 'connect_socket' => 'reset' - } - }, - 'type' => 'num' - } - }, - 'parameters' => { - 'AEMB_XWB' => { - 'value' => ' 7' - }, - 'AEMB_IDX' => { - 'value' => ' 6' - }, - 'AEMB_MUL' => { - 'value' => ' 1' - }, - 'AEMB_IWB' => { - 'value' => ' 32' - }, - 'AEMB_BSF' => { - 'value' => ' 1' - }, - 'AEMB_DWB' => { - 'value' => ' 32' - }, - 'AEMB_ICH' => { - 'value' => ' 11' - } - }, - 'parameters_order' => [ - 'AEMB_IWB', - 'AEMB_DWB', - 'AEMB_XWB', - 'AEMB_ICH', - 'AEMB_IDX', - 'AEMB_BSF', - 'AEMB_MUL' - ], - 'sockets' => {}, - 'module_name' => 'aeMB_top', - 'category' => 'Processor', - 'module' => 'aeMB' - }, - 'clk_source0' => { - 'instance_name' => 'ss', - 'plugs' => { - 'clk' => { - 'connection_num' => undef, - 'value' => 1, - 'type' => 'num', - 'nums' => { - '0' => { - 'connect_socket_num' => undef, - 'connect_id' => 'IO', - 'name' => 'clk', - 'connect_socket' => undef - } - } - }, - 'reset' => { - 'connection_num' => undef, - 'value' => 1, - 'nums' => { - '0' => { - 'connect_id' => 'IO', - 'connect_socket_num' => undef, - 'name' => 'reset', - 'connect_socket' => undef - } - }, - 'type' => 'num' - } - }, - 'parameters' => {}, - 'parameters_order' => [], - 'clk_source0' => {}, - 'sockets' => { - 'reset' => { - 'connection_num' => 'multi connection', - 'value' => 1, - 'nums' => { - '0' => { - 'name' => 'reset' - } - }, - 'type' => 'num' - }, - 'clk' => { - 'connection_num' => 'multi connection', - 'value' => 1, - 'type' => 'num', - 'nums' => { - '0' => { - 'name' => 'clk' - } - } - } - }, - 'module_name' => 'clk_source', - 'category' => 'source', - 'module' => 'clk_source' - }, - 'gpo0' => { - 'gpo0' => {}, - 'instance_name' => 'led', - 'parameters' => { - 'PORT_WIDTH' => { - 'value' => ' 1' - }, - 'Aw' => { - 'value' => ' 2' - }, - 'TAGw' => { - 'value' => ' 3' - }, - 'SELw' => { - 'value' => ' 4' - }, - 'Dw' => { - 'value' => ' 32' - } - }, - 'plugs' => { - 'reset' => { - 'connection_num' => undef, - 'value' => 1, - 'type' => 'num', - 'nums' => { - '0' => { - 'connect_id' => 'clk_source0', - 'connect_socket_num' => '0', - 'name' => 'reset', - 'connect_socket' => 'reset' - } - } - }, - 'clk' => { - 'connection_num' => undef, - 'value' => 1, - 'nums' => { - '0' => { - 'connect_id' => 'clk_source0', - 'connect_socket_num' => '0', - 'name' => 'clk', - 'connect_socket' => 'clk' - } - }, - 'type' => 'num' - }, - 'wb_slave' => { - 'connection_num' => undef, - 'value' => 1, - 'type' => 'num', - 'nums' => { - '0' => { - 'connect_socket_num' => '0', - 'width' => 5, - 'base' => 2432696320, - 'name' => 'wb', - 'connect_socket' => 'wb_slave', - 'end' => 2432696351, - 'connect_id' => 'wishbone_bus0', - 'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O' - } - } - } - }, - 'parameters_order' => [ - 'PORT_WIDTH', - 'Dw', - 'Aw', - 'TAGw', - 'SELw' - ], - 'sockets' => {}, - 'module_name' => 'gpo', - 'category' => 'GPI', - 'module' => 'gpo' - }, - 'wishbone_bus0' => { - 'wishbone_bus0' => {}, - 'instance_name' => 'bus', - 'parameters' => { - 'S' => { - 'value' => 2 - }, - 'SELw' => { - 'value' => '4' - }, - 'Dw' => { - 'value' => '32' - }, - 'BTEw' => { - 'value' => '2 ' - }, - 'Aw' => { - 'value' => '32' - }, - 'M' => { - 'value' => 2 - }, - 'TAGw' => { - 'value' => '3 ' - }, - 'CTIw' => { - 'value' => '3' - } - }, - 'plugs' => { - 'reset' => { - 'connection_num' => undef, - 'value' => 1, - 'type' => 'num', - 'nums' => { - '0' => { - 'connect_socket_num' => '0', - 'connect_id' => 'clk_source0', - 'name' => 'reset', - 'connect_socket' => 'reset' - } - } - }, - 'clk' => { - 'connection_num' => undef, - 'value' => 1, - 'nums' => { - '0' => { - 'connect_socket_num' => '0', - 'connect_id' => 'clk_source0', - 'name' => 'clk', - 'connect_socket' => 'clk' - } - }, - 'type' => 'num' - } - }, - 'parameters_order' => [ - 'S', - 'M', - 'Aw', - 'TAGw', - 'SELw', - 'Dw', - 'CTIw', - 'BTEw' - ], - 'sockets' => { - 'wb_master' => { - 'connection_num' => 'single connection', - 'value' => 'M', - 'type' => 'param', - 'nums' => { - '0' => { - 'name' => 'wb_master' - } - } - }, - 'wb_addr_map' => { - 'connection_num' => 'single connection', - 'value' => 1, - 'nums' => { - '0' => { - 'name' => 'wb_addr_map' - } - }, - 'type' => 'num' - }, - 'wb_slave' => { - 'connection_num' => 'single connection', - 'value' => 'S', - 'nums' => { - '0' => { - 'name' => 'wb_slave' - } - }, - 'type' => 'param' - } - }, - 'module_name' => 'wishbone_bus', - 'category' => 'bus', - 'module' => 'wishbone_bus' - }, - 'Altera_single_port_ram0' => { - 'instance_name' => 'ram', - 'Altera_single_port_ram0' => {}, - 'plugs' => { - 'clk' => { - 'connection_num' => undef, - 'value' => 1, - 'nums' => { - '0' => { - 'connect_socket_num' => '0', - 'connect_id' => 'clk_source0', - 'name' => 'clk', - 'connect_socket' => 'clk' - } - }, - 'type' => 'num' - }, - 'reset' => { - 'connection_num' => undef, - 'value' => 1, - 'type' => 'num', - 'nums' => { - '0' => { - 'connect_id' => 'clk_source0', - 'connect_socket_num' => '0', - 'name' => 'reset', - 'connect_socket' => 'reset' - } - } - }, - 'wb_slave' => { - 'connection_num' => undef, - 'value' => 1, - 'type' => 'num', - 'nums' => { - '0' => { - 'base' => 0, - 'width' => 'WBAw', - 'connect_socket_num' => '1', - 'name' => 'wb_slave', - 'connect_socket' => 'wb_slave', - 'end' => 16383, - 'connect_id' => 'wishbone_bus0', - 'addr' => '0x0000_0000 0x3fff_ffff RAM' - } - } - } - }, - 'parameters' => { - 'RAM_TAG_STRING' => { - 'value' => 'i2s(CORE_ID)' - }, - 'SELw' => { - 'value' => '4' - }, - 'Dw' => { - 'value' => '32' - }, - 'WBAw' => { - 'value' => 'Aw+2' - }, - 'BTEw' => { - 'value' => '2' - }, - 'Aw' => { - 'value' => 12 - }, - 'TAGw' => { - 'value' => '3' - }, - 'CTIw' => { - 'value' => '3' - } - }, - 'parameters_order' => [ - 'Dw', - 'Aw', - 'TAGw', - 'SELw', - 'CTIw', - 'BTEw', - 'RAM_TAG_STRING', - 'WBAw' - ], - 'sockets' => {}, - 'module_name' => 'Altera_single_port_ram', - 'category' => 'RAM', - 'module' => 'Altera_single_port_ram' - } - }, - 'instance_order' => [ - 'gpo0', - 'clk_source0', - 'wishbone_bus0', - 'Altera_single_port_ram0', - 'aeMB0' - ] - }, 'soc' );
mpsoc/perl_gui/lib/soc/aemb_test.SOC Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: mpsoc/perl_gui/lib/soc/aemb_tile.SOC =================================================================== --- mpsoc/perl_gui/lib/soc/aemb_tile.SOC (revision 27) +++ mpsoc/perl_gui/lib/soc/aemb_tile.SOC (nonexistent) @@ -1,1243 +0,0 @@ -$aemb_tile = bless( { - 'hdl_files' => undef, - 'modules' => {}, - 'soc_name' => 'aemb_tile', - 'top_ip' => bless( { - 'ports' => { - 'ni_flit_out_wr' => { - 'intfc_port' => 'flit_out_wr', - 'intfc_name' => 'socket:ni[0]', - 'instance_name' => 'ni0', - 'range' => '', - 'type' => 'output' - }, - 'ni_current_x' => { - 'intfc_port' => 'current_x', - 'intfc_name' => 'socket:ni[0]', - 'instance_name' => 'ni0', - 'range' => 'ni_Xw-1 : 0', - 'type' => 'input' - }, - 'ss_clk_in' => { - 'intfc_port' => 'clk_i', - 'intfc_name' => 'plug:clk[0]', - 'instance_name' => 'clk_source0', - 'range' => '', - 'type' => 'input' - }, - 'aeMB_sys_ena_i' => { - 'intfc_port' => 'enable_i', - 'intfc_name' => 'plug:enable[0]', - 'instance_name' => 'aeMB0', - 'range' => '', - 'type' => 'input' - }, - 'led_port_o' => { - 'intfc_port' => 'IO', - 'intfc_name' => 'IO', - 'instance_name' => 'gpo0', - 'range' => 'led_PORT_WIDTH-1 : 0', - 'type' => 'output' - }, - 'ni_flit_out' => { - 'intfc_port' => 'flit_out', - 'intfc_name' => 'socket:ni[0]', - 'instance_name' => 'ni0', - 'range' => 'ni_Fw-1 : 0', - 'type' => 'output' - }, - 'ni_current_y' => { - 'intfc_port' => 'current_y', - 'intfc_name' => 'socket:ni[0]', - 'instance_name' => 'ni0', - 'range' => 'ni_Yw-1 : 0', - 'type' => 'input' - }, - 'ni_credit_out' => { - 'intfc_port' => 'credit_out', - 'intfc_name' => 'socket:ni[0]', - 'instance_name' => 'ni0', - 'range' => 'ni_V-1: 0', - 'type' => 'output' - }, - 'ni_flit_in_wr' => { - 'intfc_port' => 'flit_in_wr', - 'intfc_name' => 'socket:ni[0]', - 'instance_name' => 'ni0', - 'range' => '', - 'type' => 'input' - }, - 'ni_credit_in' => { - 'intfc_port' => 'credit_in', - 'intfc_name' => 'socket:ni[0]', - 'instance_name' => 'ni0', - 'range' => 'ni_V-1 : 0', - 'type' => 'input' - }, - 'ss_reset_in' => { - 'intfc_port' => 'reset_i', - 'intfc_name' => 'plug:reset[0]', - 'instance_name' => 'clk_source0', - 'range' => '', - 'type' => 'input' - }, - 'ni_flit_in' => { - 'intfc_port' => 'flit_in', - 'intfc_name' => 'socket:ni[0]', - 'instance_name' => 'ni0', - 'range' => 'ni_Fw-1 : 0', - 'type' => 'input' - } - }, - 'interface' => { - 'plug:enable[0]' => { - 'ports' => { - 'aeMB_sys_ena_i' => { - 'intfc_port' => 'enable_i', - 'instance_name' => 'aeMB0', - 'range' => '', - 'type' => 'input' - } - } - }, - 'socket:ni[0]' => { - 'ports' => { - 'ni_flit_out_wr' => { - 'intfc_port' => 'flit_out_wr', - 'instance_name' => 'ni0', - 'range' => '', - 'type' => 'output' - }, - 'ni_current_x' => { - 'intfc_port' => 'current_x', - 'instance_name' => 'ni0', - 'range' => 'ni_Xw-1 : 0', - 'type' => 'input' - }, - 'ni_current_y' => { - 'intfc_port' => 'current_y', - 'instance_name' => 'ni0', - 'range' => 'ni_Yw-1 : 0', - 'type' => 'input' - }, - 'ni_flit_out' => { - 'intfc_port' => 'flit_out', - 'instance_name' => 'ni0', - 'range' => 'ni_Fw-1 : 0', - 'type' => 'output' - }, - 'ni_credit_out' => { - 'intfc_port' => 'credit_out', - 'instance_name' => 'ni0', - 'range' => 'ni_V-1: 0', - 'type' => 'output' - }, - 'ni_flit_in_wr' => { - 'intfc_port' => 'flit_in_wr', - 'instance_name' => 'ni0', - 'range' => '', - 'type' => 'input' - }, - 'ni_credit_in' => { - 'intfc_port' => 'credit_in', - 'instance_name' => 'ni0', - 'range' => 'ni_V-1 : 0', - 'type' => 'input' - }, - 'ni_flit_in' => { - 'intfc_port' => 'flit_in', - 'instance_name' => 'ni0', - 'range' => 'ni_Fw-1 : 0', - 'type' => 'input' - } - } - }, - 'IO' => { - 'ports' => { - 'led_port_o' => { - 'intfc_port' => 'IO', - 'instance_name' => 'gpo0', - 'range' => 'led_PORT_WIDTH-1 : 0', - 'type' => 'output' - } - } - }, - 'plug:clk[0]' => { - 'ports' => { - 'ss_clk_in' => { - 'intfc_port' => 'clk_i', - 'instance_name' => 'clk_source0', - 'range' => '', - 'type' => 'input' - } - } - }, - 'plug:reset[0]' => { - 'ports' => { - 'ss_reset_in' => { - 'intfc_port' => 'reset_i', - 'instance_name' => 'clk_source0', - 'range' => '', - 'type' => 'input' - } - } - } - }, - 'instance_ids' => { - 'aeMB0' => { - 'ports' => { - 'aeMB_sys_ena_i' => { - 'intfc_port' => 'enable_i', - 'intfc_name' => 'plug:enable[0]', - 'range' => '', - 'type' => 'input' - } - }, - 'module_name' => 'aeMB_top', - 'category' => 'Processor', - 'instance' => 'aeMB', - 'module' => 'aeMB' - }, - 'gpo0' => { - 'parameters' => { - 'led_PORT_WIDTH' => { - 'info' => 'output port width', - 'deafult' => ' 1', - 'global_param' => 1, - 'content' => '1,32,1', - 'redefine_param' => 1, - 'type' => 'Spin-button' - } - }, - 'ports' => { - 'led_port_o' => { - 'intfc_port' => 'IO', - 'intfc_name' => 'IO', - 'range' => 'led_PORT_WIDTH-1 : 0', - 'type' => 'output' - } - }, - 'module_name' => 'gpo', - 'category' => 'GPI', - 'instance' => 'led', - 'module' => 'gpo' - }, - 'wishbone_bus0' => { - 'module_name' => 'wishbone_bus', - 'category' => 'bus', - 'instance' => 'bus', - 'module' => 'wishbone_bus' - }, - 'int_ctrl0' => { - 'module_name' => 'int_ctrl', - 'category' => 'interrupt', - 'instance' => 'int_ctrl', - 'module' => 'int_ctrl' - }, - 'Altera_single_port_ram0' => { - 'parameters' => { - 'ram_Dw' => { - 'info' => undef, - 'deafult' => '32', - 'global_param' => 1, - 'content' => '8,1024,1', - 'redefine_param' => 1, - 'type' => 'Spin-button' - }, - 'ram_Aw' => { - 'info' => undef, - 'deafult' => 12, - 'global_param' => 1, - 'content' => '4,31,1', - 'redefine_param' => 1, - 'type' => 'Spin-button' - } - }, - 'module_name' => 'Altera_single_port_ram', - 'category' => 'RAM', - 'instance' => 'ram', - 'module' => 'Altera_single_port_ram' - }, - 'clk_source0' => { - 'ports' => { - 'ss_reset_in' => { - 'intfc_port' => 'reset_i', - 'intfc_name' => 'plug:reset[0]', - 'range' => '', - 'type' => 'input' - }, - 'ss_clk_in' => { - 'intfc_port' => 'clk_i', - 'intfc_name' => 'plug:clk[0]', - 'range' => '', - 'type' => 'input' - } - }, - 'module_name' => 'clk_source', - 'category' => 'source', - 'instance' => 'ss', - 'module' => 'clk_source' - }, - 'ni0' => { - 'parameters' => { - 'ni_TOPOLOGY' => { - 'info' => undef, - 'deafult' => '"MESH"', - 'global_param' => 1, - 'content' => '', - 'redefine_param' => 1, - 'type' => 'Fixed' - }, - 'ni_Fpay' => { - 'info' => undef, - 'deafult' => ' 32', - 'global_param' => 1, - 'content' => '', - 'redefine_param' => 1, - 'type' => 'Fixed' - }, - 'ni_NX' => { - 'info' => undef, - 'deafult' => ' 2', - 'global_param' => 1, - 'content' => '', - 'redefine_param' => 1, - 'type' => 'Fixed' - }, - 'ni_NY' => { - 'info' => undef, - 'deafult' => ' 2', - 'global_param' => 1, - 'content' => '', - 'redefine_param' => 1, - 'type' => 'Fixed' - }, - 'ni_B' => { - 'info' => undef, - 'deafult' => ' 4', - 'global_param' => 1, - 'content' => '', - 'redefine_param' => 1, - 'type' => 'Fixed' - }, - 'ni_V' => { - 'info' => undef, - 'deafult' => ' 4', - 'global_param' => 1, - 'content' => '', - 'redefine_param' => 1, - 'type' => 'Fixed' - }, - 'ni_ROUTE_TYPE' => { - 'info' => undef, - 'deafult' => '"DETERMINISTIC"', - 'global_param' => 1, - 'content' => '', - 'redefine_param' => 1, - 'type' => 'Fixed' - }, - 'ni_P' => { - 'info' => undef, - 'deafult' => ' 5', - 'global_param' => 1, - 'content' => '', - 'redefine_param' => 1, - 'type' => 'Fixed' - }, - 'ni_DEBUG_EN' => { - 'info' => undef, - 'deafult' => '0', - 'global_param' => 1, - 'content' => '', - 'redefine_param' => 1, - 'type' => 'Fixed' - }, - 'ni_ROUTE_NAME' => { - 'info' => undef, - 'deafult' => '"XY"', - 'global_param' => 1, - 'content' => '', - 'redefine_param' => 1, - 'type' => 'Fixed' - } - }, - 'ports' => { - 'ni_flit_out_wr' => { - 'intfc_port' => 'flit_out_wr', - 'intfc_name' => 'socket:ni[0]', - 'range' => '', - 'type' => 'output' - }, - 'ni_current_x' => { - 'intfc_port' => 'current_x', - 'intfc_name' => 'socket:ni[0]', - 'range' => 'ni_Xw-1 : 0', - 'type' => 'input' - }, - 'ni_current_y' => { - 'intfc_port' => 'current_y', - 'intfc_name' => 'socket:ni[0]', - 'range' => 'ni_Yw-1 : 0', - 'type' => 'input' - }, - 'ni_flit_out' => { - 'intfc_port' => 'flit_out', - 'intfc_name' => 'socket:ni[0]', - 'range' => 'ni_Fw-1 : 0', - 'type' => 'output' - }, - 'ni_credit_out' => { - 'intfc_port' => 'credit_out', - 'intfc_name' => 'socket:ni[0]', - 'range' => 'ni_V-1: 0', - 'type' => 'output' - }, - 'ni_flit_in_wr' => { - 'intfc_port' => 'flit_in_wr', - 'intfc_name' => 'socket:ni[0]', - 'range' => '', - 'type' => 'input' - }, - 'ni_credit_in' => { - 'intfc_port' => 'credit_in', - 'intfc_name' => 'socket:ni[0]', - 'range' => 'ni_V-1 : 0', - 'type' => 'input' - }, - 'ni_flit_in' => { - 'intfc_port' => 'flit_in', - 'intfc_name' => 'socket:ni[0]', - 'range' => 'ni_Fw-1 : 0', - 'type' => 'input' - } - }, - 'module_name' => 'ni', - 'category' => 'NoC', - 'instance' => 'ni', - 'module' => 'ni' - }, - 'timer0' => { - 'module_name' => 'timer', - 'category' => 'TIM', - 'instance' => 'timer', - 'module' => 'timer' - } - } - }, 'ip_gen' ), - 'instances' => { - 'aeMB0' => { - 'aeMB0' => {}, - 'instance_name' => 'aeMB', - 'plugs' => { - 'wb_master' => { - 'connection_num' => undef, - 'value' => 2, - 'type' => 'num', - 'nums' => { - '1' => { - 'connect_socket_num' => '1', - 'connect_id' => 'wishbone_bus0', - 'name' => 'dwb', - 'connect_socket' => 'wb_master' - }, - '0' => { - 'connect_socket_num' => '0', - 'connect_id' => 'wishbone_bus0', - 'name' => 'iwb', - 'connect_socket' => 'wb_master' - } - } - }, - 'interrupt_cpu' => { - 'connection_num' => undef, - 'value' => 1, - 'nums' => { - '0' => { - 'connect_id' => 'int_ctrl0', - 'connect_socket_num' => '0', - 'name' => 'intrp', - 'connect_socket' => 'interrupt_cpu' - } - }, - 'type' => 'num' - }, - 'enable' => { - 'connection_num' => undef, - 'value' => 1, - 'nums' => { - '0' => { - 'connect_id' => 'IO', - 'connect_socket_num' => undef, - 'name' => 'enable', - 'connect_socket' => undef - } - }, - 'type' => 'num' - }, - 'clk' => { - 'connection_num' => undef, - 'value' => 1, - 'type' => 'num', - 'nums' => { - '0' => { - 'connect_id' => 'clk_source0', - 'connect_socket_num' => '0', - 'name' => 'clk', - 'connect_socket' => 'clk' - } - } - }, - 'reset' => { - 'connection_num' => undef, - 'value' => 1, - 'nums' => { - '0' => { - 'connect_socket_num' => '0', - 'connect_id' => 'clk_source0', - 'name' => 'reset', - 'connect_socket' => 'reset' - } - }, - 'type' => 'num' - } - }, - 'parameters' => { - 'AEMB_XWB' => { - 'value' => ' 7' - }, - 'AEMB_IDX' => { - 'value' => ' 6' - }, - 'AEMB_MUL' => { - 'value' => ' 1' - }, - 'AEMB_IWB' => { - 'value' => ' 32' - }, - 'AEMB_BSF' => { - 'value' => ' 1' - }, - 'AEMB_DWB' => { - 'value' => ' 32' - }, - 'AEMB_ICH' => { - 'value' => ' 11' - } - }, - 'parameters_order' => [ - 'AEMB_IWB', - 'AEMB_DWB', - 'AEMB_XWB', - 'AEMB_ICH', - 'AEMB_IDX', - 'AEMB_BSF', - 'AEMB_MUL' - ], - 'sockets' => {}, - 'module_name' => 'aeMB_top', - 'category' => 'Processor', - 'module' => 'aeMB' - }, - 'gpo0' => { - 'gpo0' => {}, - 'instance_name' => 'led', - 'parameters' => { - 'PORT_WIDTH' => { - 'value' => ' 1' - }, - 'Aw' => { - 'value' => ' 2' - }, - 'TAGw' => { - 'value' => ' 3' - }, - 'SELw' => { - 'value' => ' 4' - }, - 'Dw' => { - 'value' => ' 32' - } - }, - 'plugs' => { - 'reset' => { - 'connection_num' => undef, - 'value' => 1, - 'type' => 'num', - 'nums' => { - '0' => { - 'connect_id' => 'clk_source0', - 'connect_socket_num' => '0', - 'name' => 'reset', - 'connect_socket' => 'reset' - } - } - }, - 'clk' => { - 'connection_num' => undef, - 'value' => 1, - 'nums' => { - '0' => { - 'connect_id' => 'clk_source0', - 'connect_socket_num' => '0', - 'name' => 'clk', - 'connect_socket' => 'clk' - } - }, - 'type' => 'num' - }, - 'wb_slave' => { - 'connection_num' => undef, - 'value' => 1, - 'type' => 'num', - 'nums' => { - '0' => { - 'connect_socket_num' => '0', - 'width' => 5, - 'base' => 2432696320, - 'name' => 'wb', - 'connect_socket' => 'wb_slave', - 'end' => 2432696351, - 'connect_id' => 'wishbone_bus0', - 'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O' - } - } - } - }, - 'parameters_order' => [ - 'PORT_WIDTH', - 'Dw', - 'Aw', - 'TAGw', - 'SELw' - ], - 'sockets' => {}, - 'module_name' => 'gpo', - 'category' => 'GPI', - 'module' => 'gpo' - }, - 'wishbone_bus0' => { - 'wishbone_bus0' => {}, - 'instance_name' => 'bus', - 'parameters' => { - 'S' => { - 'value' => 5 - }, - 'SELw' => { - 'value' => '4' - }, - 'Dw' => { - 'value' => '32' - }, - 'BTEw' => { - 'value' => '2 ' - }, - 'Aw' => { - 'value' => '32' - }, - 'M' => { - 'value' => 3 - }, - 'TAGw' => { - 'value' => '3 ' - }, - 'CTIw' => { - 'value' => '3' - } - }, - 'plugs' => { - 'reset' => { - 'connection_num' => undef, - 'value' => 1, - 'type' => 'num', - 'nums' => { - '0' => { - 'connect_socket_num' => '0', - 'connect_id' => 'clk_source0', - 'name' => 'reset', - 'connect_socket' => 'reset' - } - } - }, - 'clk' => { - 'connection_num' => undef, - 'value' => 1, - 'nums' => { - '0' => { - 'connect_socket_num' => '0', - 'connect_id' => 'clk_source0', - 'name' => 'clk', - 'connect_socket' => 'clk' - } - }, - 'type' => 'num' - } - }, - 'parameters_order' => [ - 'S', - 'M', - 'Aw', - 'TAGw', - 'SELw', - 'Dw', - 'CTIw', - 'BTEw' - ], - 'sockets' => { - 'wb_master' => { - 'connection_num' => 'single connection', - 'value' => 'M', - 'type' => 'param', - 'nums' => { - '0' => { - 'name' => 'wb_master' - } - } - }, - 'wb_addr_map' => { - 'connection_num' => 'single connection', - 'value' => 1, - 'nums' => { - '0' => { - 'name' => 'wb_addr_map' - } - }, - 'type' => 'num' - }, - 'wb_slave' => { - 'connection_num' => 'single connection', - 'value' => 'S', - 'nums' => { - '0' => { - 'name' => 'wb_slave' - } - }, - 'type' => 'param' - } - }, - 'module_name' => 'wishbone_bus', - 'category' => 'bus', - 'module' => 'wishbone_bus' - }, - 'int_ctrl0' => { - 'instance_name' => 'int_ctrl', - 'int_ctrl0' => {}, - 'plugs' => { - 'reset' => { - 'connection_num' => undef, - 'value' => 1, - 'nums' => { - '0' => { - 'connect_socket_num' => '0', - 'connect_id' => 'clk_source0', - 'name' => 'reset', - 'connect_socket' => 'reset' - } - }, - 'type' => 'num' - }, - 'clk' => { - 'connection_num' => undef, - 'value' => 1, - 'nums' => { - '0' => { - 'connect_socket_num' => '0', - 'connect_id' => 'clk_source0', - 'name' => 'clk', - 'connect_socket' => 'clk' - } - }, - 'type' => 'num' - }, - 'wb_slave' => { - 'connection_num' => undef, - 'value' => 1, - 'nums' => { - '0' => { - 'base' => 2650800128, - 'width' => 5, - 'connect_socket_num' => '3', - 'name' => 'wb', - 'end' => 2650800159, - 'connect_socket' => 'wb_slave', - 'connect_id' => 'wishbone_bus0', - 'addr' => '0x9e00_0000 0x9eff_ffff IDE Controller' - } - }, - 'type' => 'num' - } - }, - 'parameters' => { - 'Aw' => { - 'value' => ' 3' - }, - 'SELw' => { - 'value' => ' 4 ' - }, - 'INT_NUM' => { - 'value' => 2 - }, - 'Dw' => { - 'value' => ' 32' - } - }, - 'parameters_order' => [ - 'INT_NUM', - 'Dw', - 'Aw', - 'SELw' - ], - 'sockets' => { - 'interrupt_cpu' => { - 'connection_num' => 'single connection', - 'value' => 1, - 'nums' => { - '0' => { - 'name' => 'int_cpu' - } - }, - 'type' => 'num' - }, - 'interrupt_peripheral' => { - 'connection_num' => 'single connection', - 'value' => 'INT_NUM', - 'nums' => { - '0' => { - 'name' => 'int_periph' - } - }, - 'type' => 'param' - } - }, - 'module_name' => 'int_ctrl', - 'category' => 'interrupt', - 'module' => 'int_ctrl' - }, - 'Altera_single_port_ram0' => { - 'instance_name' => 'ram', - 'Altera_single_port_ram0' => {}, - 'plugs' => { - 'clk' => { - 'connection_num' => undef, - 'value' => 1, - 'nums' => { - '0' => { - 'connect_socket_num' => '0', - 'connect_id' => 'clk_source0', - 'name' => 'clk', - 'connect_socket' => 'clk' - } - }, - 'type' => 'num' - }, - 'reset' => { - 'connection_num' => undef, - 'value' => 1, - 'type' => 'num', - 'nums' => { - '0' => { - 'connect_id' => 'clk_source0', - 'connect_socket_num' => '0', - 'name' => 'reset', - 'connect_socket' => 'reset' - } - } - }, - 'wb_slave' => { - 'connection_num' => undef, - 'value' => 1, - 'type' => 'num', - 'nums' => { - '0' => { - 'base' => 0, - 'width' => 'WBAw', - 'connect_socket_num' => '1', - 'name' => 'wb_slave', - 'connect_socket' => 'wb_slave', - 'end' => 16383, - 'connect_id' => 'wishbone_bus0', - 'addr' => '0x0000_0000 0x3fff_ffff RAM' - } - } - } - }, - 'parameters' => { - 'RAM_TAG_STRING' => { - 'value' => 'i2s(CORE_ID)' - }, - 'SELw' => { - 'value' => '4' - }, - 'Dw' => { - 'value' => '32' - }, - 'WBAw' => { - 'value' => 'Aw+2' - }, - 'BTEw' => { - 'value' => '2' - }, - 'Aw' => { - 'value' => 12 - }, - 'TAGw' => { - 'value' => '3' - }, - 'CTIw' => { - 'value' => '3' - } - }, - 'parameters_order' => [ - 'Dw', - 'Aw', - 'TAGw', - 'SELw', - 'CTIw', - 'BTEw', - 'RAM_TAG_STRING', - 'WBAw' - ], - 'sockets' => {}, - 'module_name' => 'Altera_single_port_ram', - 'category' => 'RAM', - 'module' => 'Altera_single_port_ram' - }, - 'clk_source0' => { - 'instance_name' => 'ss', - 'plugs' => { - 'clk' => { - 'connection_num' => undef, - 'value' => 1, - 'type' => 'num', - 'nums' => { - '0' => { - 'connect_socket_num' => undef, - 'connect_id' => 'IO', - 'name' => 'clk', - 'connect_socket' => undef - } - } - }, - 'reset' => { - 'connection_num' => undef, - 'value' => 1, - 'nums' => { - '0' => { - 'connect_id' => 'IO', - 'connect_socket_num' => undef, - 'name' => 'reset', - 'connect_socket' => undef - } - }, - 'type' => 'num' - } - }, - 'parameters' => {}, - 'parameters_order' => [], - 'clk_source0' => {}, - 'sockets' => { - 'reset' => { - 'connection_num' => 'multi connection', - 'value' => 1, - 'nums' => { - '0' => { - 'name' => 'reset' - } - }, - 'type' => 'num' - }, - 'clk' => { - 'connection_num' => 'multi connection', - 'value' => 1, - 'type' => 'num', - 'nums' => { - '0' => { - 'name' => 'clk' - } - } - } - }, - 'module_name' => 'clk_source', - 'category' => 'source', - 'module' => 'clk_source' - }, - 'ni0' => { - 'instance_name' => 'ni', - 'plugs' => { - 'wb_master' => { - 'connection_num' => undef, - 'value' => 1, - 'nums' => { - '0' => { - 'connect_socket_num' => '2', - 'connect_id' => 'wishbone_bus0', - 'name' => 'wb_master', - 'connect_socket' => 'wb_master' - } - }, - 'type' => 'num' - }, - 'reset' => { - 'connection_num' => undef, - 'value' => 1, - 'nums' => { - '0' => { - 'connect_socket_num' => '0', - 'connect_id' => 'clk_source0', - 'name' => 'reset', - 'connect_socket' => 'reset' - } - }, - 'type' => 'num' - }, - 'interrupt_peripheral' => { - 'connection_num' => undef, - 'value' => 1, - 'nums' => { - '0' => { - 'connect_socket_num' => '0', - 'connect_id' => 'int_ctrl0', - 'name' => 'int_peripheral', - 'connect_socket' => 'interrupt_peripheral' - } - }, - 'type' => 'num' - }, - 'clk' => { - 'connection_num' => undef, - 'value' => 1, - 'nums' => { - '0' => { - 'connect_socket_num' => '0', - 'connect_id' => 'clk_source0', - 'name' => 'clk', - 'connect_socket' => 'clk' - } - }, - 'type' => 'num' - }, - 'wb_slave' => { - 'connection_num' => undef, - 'value' => 1, - 'nums' => { - '0' => { - 'base' => 3087007744, - 'width' => 5, - 'connect_socket_num' => '2', - 'name' => 'wb_slave', - 'end' => 3087007775, - 'connect_socket' => 'wb_slave', - 'connect_id' => 'wishbone_bus0', - 'addr' => '0xb800_0000 0xbfff_ffff custom devices' - } - }, - 'type' => 'num' - } - }, - 'parameters' => { - 'Dw' => { - 'value' => ' 32' - }, - 'NY' => { - 'value' => ' 2' - }, - 'DEBUG_EN' => { - 'value' => '0' - }, - 'NX' => { - 'value' => ' 2' - }, - 'V' => { - 'value' => ' 4' - }, - 'COMB_PCK_SIZE_W' => { - 'value' => '12' - }, - 'Fw' => { - 'value' => '2+V+Fpay' - }, - 'TAGw' => { - 'value' => '3' - }, - 'COMB_MEM_PTR_W' => { - 'value' => '20' - }, - 'M_Aw' => { - 'value' => '32' - }, - 'ROUTE_NAME' => { - 'value' => '"XY"' - }, - 'Xw ' => { - 'value' => 'log2(NX)' - }, - 'Fpay' => { - 'value' => ' 32' - }, - 'ROUTE_TYPE' => { - 'value' => '"DETERMINISTIC"' - }, - 'SELw' => { - 'value' => '4 ' - }, - 'P' => { - 'value' => ' 5' - }, - 'B' => { - 'value' => ' 4' - }, - 'Xw' => { - 'value' => 'log2(NX)' - }, - 'TOPOLOGY' => { - 'value' => '"MESH"' - }, - 'S_Aw' => { - 'value' => ' 3' - }, - 'Yw' => { - 'value' => 'log2(NY)' - }, - 'Xwj' => { - 'value' => 'fvf' - } - }, - 'parameters_order' => [ - 'V', - 'P', - 'B', - 'NX', - 'NY', - 'Fpay', - 'TOPOLOGY', - 'ROUTE_TYPE', - 'ROUTE_NAME', - 'DEBUG_EN', - 'COMB_MEM_PTR_W', - 'COMB_PCK_SIZE_W', - 'Dw', - 'S_Aw', - 'M_Aw', - 'TAGw', - 'SELw', - 'Yw', - 'Fw', - 'Xw' - ], - 'sockets' => { - 'ni' => { - 'connection_num' => 'single connection', - 'value' => 1, - 'nums' => { - '0' => { - 'name' => 'ni' - } - }, - 'type' => 'num' - } - }, - 'module_name' => 'ni', - 'category' => 'NoC', - 'module' => 'ni' - }, - 'timer0' => { - 'instance_name' => 'timer', - 'plugs' => { - 'reset' => { - 'connection_num' => undef, - 'value' => 1, - 'nums' => { - '0' => { - 'connect_socket_num' => '0', - 'connect_id' => 'clk_source0', - 'name' => 'reset', - 'connect_socket' => 'reset' - } - }, - 'type' => 'num' - }, - 'interrupt_peripheral' => { - 'connection_num' => undef, - 'value' => 1, - 'nums' => { - '0' => { - 'connect_socket_num' => '1', - 'connect_id' => 'int_ctrl0', - 'name' => 'interrupt_peripheral', - 'connect_socket' => 'interrupt_peripheral' - } - }, - 'type' => 'num' - }, - 'clk' => { - 'connection_num' => undef, - 'value' => 1, - 'nums' => { - '0' => { - 'connect_socket_num' => '0', - 'connect_id' => 'clk_source0', - 'name' => 'clk', - 'connect_socket' => 'clk' - } - }, - 'type' => 'num' - }, - 'wb_slave' => { - 'connection_num' => undef, - 'value' => 1, - 'nums' => { - '0' => { - 'base' => 2516582400, - 'width' => 5, - 'connect_socket_num' => '4', - 'name' => 'wb', - 'end' => 2516582431, - 'connect_socket' => 'wb_slave', - 'connect_id' => 'wishbone_bus0', - 'addr' => '0x9600_0000 0x96ff_ffff PWM/Timer/Counter Ctrl' - } - }, - 'type' => 'num' - } - }, - 'parameters' => { - 'Aw' => { - 'value' => ' 3' - }, - 'TAGw' => { - 'value' => '3' - }, - 'SELw' => { - 'value' => ' 4' - }, - 'Dw' => { - 'value' => ' 32' - }, - 'CNTw' => { - 'value' => '32 ' - } - }, - 'parameters_order' => [ - 'CNTw', - 'Dw', - 'Aw', - 'TAGw', - 'SELw' - ], - 'sockets' => {}, - 'module_name' => 'timer', - 'category' => 'TIM', - 'module' => 'timer', - 'timer0' => {} - } - }, - 'instance_order' => [ - 'aeMB0', - 'gpo0', - 'clk_source0', - 'wishbone_bus0', - 'Altera_single_port_ram0', - 'int_ctrl0', - 'timer0', - 'ni0' - ] - }, 'soc' ); Index: mpsoc/perl_gui/lib/soc/Tutorial_lm32.SOC =================================================================== --- mpsoc/perl_gui/lib/soc/Tutorial_lm32.SOC (nonexistent) +++ mpsoc/perl_gui/lib/soc/Tutorial_lm32.SOC (revision 28) @@ -0,0 +1,1063 @@ +####################################################################### +## File: Tutorial_lm32.SOC +## +## Copyright (C) 2014-2016 Alireza Monemi +## +## This file is part of ProNoC 1.5.0 +## +## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT +## MAY CAUSE UNEXPECTED BEHAIVOR. +################################################################################ + +$soc = bless( { + 'hdl_files' => undef, + 'soc_name' => 'Tutorial_lm32', + 'top_ip' => bless( { + 'ports' => { + 'lm32_en_i' => { + 'intfc_port' => 'enable_i', + 'intfc_name' => 'plug:enable[0]', + 'instance_name' => 'lm320', + 'range' => '', + 'type' => 'input' + }, + 'hex0_port_o' => { + 'intfc_port' => 'IO', + 'intfc_name' => 'IO', + 'instance_name' => 'gpo0', + 'range' => 'hex0_PORT_WIDTH-1 : 0', + 'type' => 'output' + }, + 'source_reset_in' => { + 'intfc_port' => 'reset_i', + 'intfc_name' => 'plug:reset[0]', + 'instance_name' => 'clk_source0', + 'range' => '', + 'type' => 'input' + }, + 'ext_int_ext_int_i' => { + 'intfc_port' => 'IO', + 'intfc_name' => 'IO', + 'instance_name' => 'ext_int0', + 'range' => 'ext_int_EXT_INT_NUM-1 : 0', + 'type' => 'input' + }, + 'source_clk_in' => { + 'intfc_port' => 'clk_i', + 'intfc_name' => 'plug:clk[0]', + 'instance_name' => 'clk_source0', + 'range' => '', + 'type' => 'input' + }, + 'hex1_port_o' => { + 'intfc_port' => 'IO', + 'intfc_name' => 'IO', + 'instance_name' => 'gpo1', + 'range' => 'hex1_PORT_WIDTH-1 : 0', + 'type' => 'output' + } + }, + 'interface' => { + 'plug:enable[0]' => { + 'ports' => { + 'lm32_en_i' => { + 'intfc_port' => 'enable_i', + 'instance_name' => 'lm320', + 'range' => '', + 'type' => 'input' + } + } + }, + 'IO' => { + 'ports' => { + 'hex0_port_o' => { + 'intfc_port' => 'IO', + 'instance_name' => 'gpo0', + 'range' => 'hex0_PORT_WIDTH-1 : 0', + 'type' => 'output' + }, + 'ext_int_ext_int_i' => { + 'intfc_port' => 'IO', + 'instance_name' => 'ext_int0', + 'range' => 'ext_int_EXT_INT_NUM-1 : 0', + 'type' => 'input' + }, + 'hex1_port_o' => { + 'intfc_port' => 'IO', + 'instance_name' => 'gpo1', + 'range' => 'hex1_PORT_WIDTH-1 : 0', + 'type' => 'output' + } + } + }, + 'plug:clk[0]' => { + 'ports' => { + 'source_clk_in' => { + 'intfc_port' => 'clk_i', + 'instance_name' => 'clk_source0', + 'range' => '', + 'type' => 'input' + } + } + }, + 'plug:reset[0]' => { + 'ports' => { + 'source_reset_in' => { + 'intfc_port' => 'reset_i', + 'instance_name' => 'clk_source0', + 'range' => '', + 'type' => 'input' + } + } + } + }, + 'instance_ids' => { + 'gpo0' => { + 'parameters' => { + 'hex0_PORT_WIDTH' => { + 'info' => 'output port width', + 'deafult' => 7, + 'global_param' => 'Parameter', + 'content' => '1,32,1', + 'redefine_param' => 1, + 'type' => 'Spin-button' + } + }, + 'ports' => { + 'hex0_port_o' => { + 'intfc_port' => 'IO', + 'intfc_name' => 'IO', + 'range' => 'hex0_PORT_WIDTH-1 : 0', + 'type' => 'output' + } + }, + 'module_name' => 'gpo', + 'category' => 'GPIO', + 'instance' => 'hex0', + 'module' => 'gpo' + }, + 'wishbone_bus0' => { + 'module_name' => 'wishbone_bus', + 'category' => 'Bus', + 'instance' => 'bus', + 'module' => 'wishbone_bus' + }, + 'dual_port_ram0' => { + 'module_name' => 'wb_dual_port_ram', + 'category' => 'RAM', + 'instance' => 'dual_port_ram0', + 'module' => 'dual_port_ram' + }, + 'gpo1' => { + 'parameters' => { + 'hex1_PORT_WIDTH' => { + 'info' => 'output port width', + 'deafult' => 7, + 'global_param' => 'Parameter', + 'content' => '1,32,1', + 'redefine_param' => 1, + 'type' => 'Spin-button' + } + }, + 'ports' => { + 'hex1_port_o' => { + 'intfc_port' => 'IO', + 'intfc_name' => 'IO', + 'range' => 'hex1_PORT_WIDTH-1 : 0', + 'type' => 'output' + } + }, + 'module_name' => 'gpo', + 'category' => 'GPIO', + 'instance' => 'hex1', + 'module' => 'gpo' + }, + 'clk_source0' => { + 'ports' => { + 'source_reset_in' => { + 'intfc_port' => 'reset_i', + 'intfc_name' => 'plug:reset[0]', + 'range' => '', + 'type' => 'input' + }, + 'source_clk_in' => { + 'intfc_port' => 'clk_i', + 'intfc_name' => 'plug:clk[0]', + 'range' => '', + 'type' => 'input' + } + }, + 'module_name' => 'clk_source', + 'category' => 'Source', + 'instance' => 'source', + 'module' => 'clk_source' + }, + 'ext_int0' => { + 'ports' => { + 'ext_int_ext_int_i' => { + 'intfc_port' => 'IO', + 'intfc_name' => 'IO', + 'range' => 'ext_int_EXT_INT_NUM-1 : 0', + 'type' => 'input' + } + }, + 'module_name' => 'ext_int', + 'category' => 'Interrupt', + 'instance' => 'ext_int', + 'module' => 'ext_int' + }, + 'lm320' => { + 'ports' => { + 'lm32_en_i' => { + 'intfc_port' => 'enable_i', + 'intfc_name' => 'plug:enable[0]', + 'range' => '', + 'type' => 'input' + } + }, + 'module_name' => 'lm32', + 'category' => 'Processor', + 'instance' => 'lm32', + 'module' => 'lm32' + }, + 'jtag_wb0' => { + 'parameters' => { + 'jtag_wb_VJTAG_INDEX' => { + 'info' => 'JTAG control host identifies each instance of this IP core by a unique index number. The default value is the tile ID number. You assign an index value between 0 to 255.', + 'deafult' => 'CORE_ID', + 'global_param' => 'Parameter', + 'content' => '', + 'redefine_param' => 1, + 'type' => 'Entry' + } + }, + 'module_name' => 'vjtag_wb', + 'category' => 'JTAG', + 'instance' => 'jtag_wb', + 'module' => 'jtag_wb' + }, + 'timer0' => { + 'module_name' => 'timer', + 'category' => 'Timer', + 'instance' => 'timer', + 'module' => 'timer' + } + } + }, 'ip_gen' ), + 'instances' => { + 'gpo0' => { + 'gpo0' => {}, + 'instance_name' => 'hex0', + 'plugs' => { + 'reset' => { + 'connection_num' => undef, + 'value' => 1, + 'nums' => { + '0' => { + 'connect_socket_num' => '0', + 'connect_id' => 'clk_source0', + 'name' => 'reset', + 'connect_socket' => 'reset' + } + }, + 'type' => 'num' + }, + 'clk' => { + 'connection_num' => undef, + 'value' => 1, + 'nums' => { + '0' => { + 'connect_socket_num' => '0', + 'connect_id' => 'clk_source0', + 'name' => 'clk', + 'connect_socket' => 'clk' + } + }, + 'type' => 'num' + }, + 'wb_slave' => { + 'connection_num' => undef, + 'value' => 1, + 'nums' => { + '0' => { + 'base' => 2432696320, + 'width' => 5, + 'connect_socket_num' => '0', + 'name' => 'wb', + 'end' => 2432696351, + 'connect_socket' => 'wb_slave', + 'connect_id' => 'wishbone_bus0', + 'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O' + } + }, + 'type' => 'num' + } + }, + 'parameters' => { + 'PORT_WIDTH' => { + 'value' => 7 + }, + 'Aw' => { + 'value' => ' 2' + }, + 'TAGw' => { + 'value' => ' 3' + }, + 'SELw' => { + 'value' => ' 4' + }, + 'Dw' => { + 'value' => 'PORT_WIDTH' + } + }, + 'parameters_order' => [ + 'PORT_WIDTH', + 'Aw', + 'TAGw', + 'SELw', + 'Dw' + ], + 'sockets' => {}, + 'module_name' => 'gpo', + 'category' => 'GPIO', + 'module' => 'gpo' + }, + 'dual_port_ram0' => { + 'dual_port_ram0' => {}, + 'instance_name' => 'dual_port_ram0', + 'plugs' => { + 'reset' => { + 'connection_num' => undef, + 'value' => 1, + 'nums' => { + '0' => { + 'connect_socket_num' => '0', + 'connect_id' => 'clk_source0', + 'name' => 'reset', + 'connect_socket' => 'reset' + } + }, + 'type' => 'num' + }, + 'clk' => { + 'connection_num' => undef, + 'value' => 1, + 'nums' => { + '0' => { + 'connect_socket_num' => '0', + 'connect_id' => 'clk_source0', + 'name' => 'clk', + 'connect_socket' => 'clk' + } + }, + 'type' => 'num' + }, + 'wb_slave' => { + 'connection_num' => undef, + 'value' => 2, + 'nums' => { + '1' => { + 'base' => 16384, + 'width' => 'WB_Aw', + 'connect_socket_num' => '5', + 'name' => 'wb_b', + 'end' => 32767, + 'connect_socket' => 'wb_slave', + 'connect_id' => 'wishbone_bus0', + 'addr' => '0x0000_0000 0x3fff_ffff RAM' + }, + '0' => { + 'base' => 0, + 'width' => 'WB_Aw', + 'connect_socket_num' => '4', + 'name' => 'wb_a', + 'end' => 16383, + 'connect_socket' => 'wb_slave', + 'connect_id' => 'wishbone_bus0', + 'addr' => '0x0000_0000 0x3fff_ffff RAM' + } + }, + 'type' => 'num' + } + }, + 'parameters' => { + 'SELw' => { + 'value' => 'Dw/8' + }, + 'PORT_B_BURST_MODE' => { + 'value' => '"ENABLED" ' + }, + 'Dw' => { + 'value' => '32' + }, + 'BTEw' => { + 'value' => '2' + }, + 'WB_Aw' => { + 'value' => 'Aw+2' + }, + 'RAM_INDEX' => { + 'value' => 'CORE_ID' + }, + 'Aw' => { + 'value' => '12' + }, + 'TAGw' => { + 'value' => '3' + }, + 'BYTE_WR_EN' => { + 'value' => '"YES"' + }, + 'PORT_A_BURST_MODE' => { + 'value' => '"ENABLED"' + }, + 'CTIw' => { + 'value' => '3' + }, + 'FPGA_VENDOR' => { + 'value' => '"ALTERA"' + } + }, + 'parameters_order' => [ + 'Dw', + 'Aw', + 'BYTE_WR_EN', + 'FPGA_VENDOR', + 'TAGw', + 'SELw', + 'CTIw', + 'BTEw', + 'WB_Aw', + 'RAM_INDEX', + 'PORT_A_BURST_MODE', + 'PORT_B_BURST_MODE' + ], + 'sockets' => {}, + 'module_name' => 'wb_dual_port_ram', + 'category' => 'RAM', + 'module' => 'dual_port_ram' + }, + 'wishbone_bus0' => { + 'wishbone_bus0' => {}, + 'instance_name' => 'bus', + 'plugs' => { + 'clk' => { + 'connection_num' => undef, + 'value' => 1, + 'type' => 'num', + 'nums' => { + '0' => { + 'connect_id' => 'clk_source0', + 'connect_socket_num' => '0', + 'name' => 'clk', + 'connect_socket' => 'clk' + } + } + }, + 'reset' => { + 'connection_num' => undef, + 'value' => 1, + 'type' => 'num', + 'nums' => { + '0' => { + 'connect_id' => 'clk_source0', + 'connect_socket_num' => '0', + 'name' => 'reset', + 'connect_socket' => 'reset' + } + } + } + }, + 'parameters' => { + 'S' => { + 'value' => 6 + }, + 'SELw' => { + 'value' => 'Dw/8' + }, + 'Dw' => { + 'value' => '32' + }, + 'BTEw' => { + 'value' => '2 ' + }, + 'Aw' => { + 'value' => '32' + }, + 'M' => { + 'value' => 3 + }, + 'TAGw' => { + 'value' => '3' + }, + 'CTIw' => { + 'value' => '3' + } + }, + 'parameters_order' => [ + 'M', + 'S', + 'Dw', + 'Aw', + 'SELw', + 'TAGw', + 'CTIw', + 'BTEw' + ], + 'sockets' => { + 'wb_master' => { + 'connection_num' => 'single connection', + 'value' => 'M', + 'type' => 'param', + 'nums' => { + '0' => { + 'name' => 'wb_master' + } + } + }, + 'wb_addr_map' => { + 'connection_num' => 'single connection', + 'value' => 1, + 'type' => 'num', + 'nums' => { + '0' => { + 'name' => 'wb_addr_map' + } + } + }, + 'wb_slave' => { + 'connection_num' => 'single connection', + 'value' => 'S', + 'type' => 'param', + 'nums' => { + '0' => { + 'name' => 'wb_slave' + } + } + } + }, + 'module_name' => 'wishbone_bus', + 'category' => 'Bus', + 'module' => 'wishbone_bus' + }, + 'gpo1' => { + 'instance_name' => 'hex1', + 'gpo1' => {}, + 'plugs' => { + 'reset' => { + 'connection_num' => undef, + 'value' => 1, + 'nums' => { + '0' => { + 'connect_socket_num' => '0', + 'connect_id' => 'clk_source0', + 'name' => 'reset', + 'connect_socket' => 'reset' + } + }, + 'type' => 'num' + }, + 'clk' => { + 'connection_num' => undef, + 'value' => 1, + 'nums' => { + '0' => { + 'connect_socket_num' => '0', + 'connect_id' => 'clk_source0', + 'name' => 'clk', + 'connect_socket' => 'clk' + } + }, + 'type' => 'num' + }, + 'wb_slave' => { + 'connection_num' => undef, + 'value' => 1, + 'nums' => { + '0' => { + 'base' => 2432696352, + 'width' => 5, + 'connect_socket_num' => '1', + 'name' => 'wb', + 'end' => 2432696383, + 'connect_socket' => 'wb_slave', + 'connect_id' => 'wishbone_bus0', + 'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O' + } + }, + 'type' => 'num' + } + }, + 'parameters' => { + 'PORT_WIDTH' => { + 'value' => 7 + }, + 'Aw' => { + 'value' => ' 2' + }, + 'TAGw' => { + 'value' => ' 3' + }, + 'SELw' => { + 'value' => ' 4' + }, + 'Dw' => { + 'value' => 'PORT_WIDTH' + } + }, + 'parameters_order' => [ + 'PORT_WIDTH', + 'Aw', + 'TAGw', + 'SELw', + 'Dw' + ], + 'sockets' => {}, + 'module_name' => 'gpo', + 'category' => 'GPIO', + 'module' => 'gpo' + }, + 'lm320' => { + 'instance_name' => 'lm32', + 'plugs' => { + 'wb_master' => { + 'connection_num' => undef, + 'value' => 2, + 'type' => 'num', + 'nums' => { + '1' => { + 'connect_id' => 'wishbone_bus0', + 'connect_socket_num' => '2', + 'name' => 'dwb', + 'connect_socket' => 'wb_master' + }, + '0' => { + 'connect_id' => 'wishbone_bus0', + 'connect_socket_num' => '1', + 'name' => 'iwb', + 'connect_socket' => 'wb_master' + } + } + }, + 'enable' => { + 'connection_num' => undef, + 'value' => 1, + 'type' => 'num', + 'nums' => { + '0' => { + 'connect_id' => 'IO', + 'connect_socket_num' => undef, + 'name' => 'enable', + 'connect_socket' => undef + } + } + }, + 'clk' => { + 'connection_num' => undef, + 'value' => 1, + 'type' => 'num', + 'nums' => { + '0' => { + 'connect_id' => 'clk_source0', + 'connect_socket_num' => '0', + 'name' => 'clk', + 'connect_socket' => 'clk' + } + } + }, + 'reset' => { + 'connection_num' => undef, + 'value' => 1, + 'type' => 'num', + 'nums' => { + '0' => { + 'connect_id' => 'clk_source0', + 'connect_socket_num' => '0', + 'name' => 'reset', + 'connect_socket' => 'reset' + } + } + } + }, + 'parameters' => { + 'CFG_PL_BARREL_SHIFT' => { + 'value' => '"ENABLED"' + }, + 'CFG_SIGN_EXTEND' => { + 'value' => '"ENABLED"' + }, + 'CFG_PL_MULTIPLY' => { + 'value' => '"ENABLED"' + }, + 'INTR_NUM' => { + 'value' => '32' + }, + 'CFG_MC_DIVIDE' => { + 'value' => '"DISABLED"' + } + }, + 'lm320' => {}, + 'parameters_order' => [ + 'INTR_NUM', + 'CFG_PL_MULTIPLY', + 'CFG_PL_BARREL_SHIFT', + 'CFG_SIGN_EXTEND', + 'CFG_MC_DIVIDE' + ], + 'sockets' => { + 'interrupt_peripheral' => { + 'connection_num' => 'single connection', + 'value' => 'INTR_NUM', + 'type' => 'param', + 'nums' => { + '0' => { + 'name' => 'interrupt_peripheral' + } + } + } + }, + 'module_name' => 'lm32', + 'category' => 'Processor', + 'module' => 'lm32' + }, + 'clk_source0' => { + 'instance_name' => 'source', + 'plugs' => { + 'clk' => { + 'connection_num' => undef, + 'value' => 1, + 'type' => 'num', + 'nums' => { + '0' => { + 'connect_id' => 'IO', + 'connect_socket_num' => undef, + 'name' => 'clk', + 'connect_socket' => undef + } + } + }, + 'reset' => { + 'connection_num' => undef, + 'value' => 1, + 'type' => 'num', + 'nums' => { + '0' => { + 'connect_id' => 'IO', + 'connect_socket_num' => undef, + 'name' => 'reset', + 'connect_socket' => undef + } + } + } + }, + 'parameters' => {}, + 'clk_source0' => {}, + 'parameters_order' => [], + 'sockets' => { + 'clk' => { + 'connection_num' => 'multi connection', + 'value' => 1, + 'type' => 'num', + 'nums' => { + '0' => { + 'name' => 'clk' + } + } + }, + 'reset' => { + 'connection_num' => 'multi connection', + 'value' => 1, + 'type' => 'num', + 'nums' => { + '0' => { + 'name' => 'reset' + } + } + } + }, + 'module_name' => 'clk_source', + 'category' => 'Source', + 'module' => 'clk_source' + }, + 'ext_int0' => { + 'instance_name' => 'ext_int', + 'plugs' => { + 'clk' => { + 'connection_num' => undef, + 'value' => 1, + 'type' => 'num', + 'nums' => { + '0' => { + 'connect_id' => 'clk_source0', + 'connect_socket_num' => '0', + 'name' => 'clk', + 'connect_socket' => 'clk' + } + } + }, + 'interrupt_peripheral' => { + 'connection_num' => undef, + 'value' => 1, + 'type' => 'num', + 'nums' => { + '0' => { + 'connect_id' => 'lm320', + 'connect_socket_num' => '0', + 'name' => 'interrupt', + 'connect_socket' => 'interrupt_peripheral' + } + } + }, + 'reset' => { + 'connection_num' => undef, + 'value' => 1, + 'type' => 'num', + 'nums' => { + '0' => { + 'connect_id' => 'clk_source0', + 'connect_socket_num' => '0', + 'name' => 'reset', + 'connect_socket' => 'reset' + } + } + }, + 'wb_slave' => { + 'connection_num' => undef, + 'value' => 1, + 'type' => 'num', + 'nums' => { + '0' => { + 'connect_socket_num' => '2', + 'width' => 5, + 'base' => 2650800128, + 'name' => 'wb', + 'connect_socket' => 'wb_slave', + 'end' => 2650800159, + 'connect_id' => 'wishbone_bus0', + 'addr' => '0x9e00_0000 0x9eff_ffff IDE Controller' + } + } + } + }, + 'parameters' => { + 'Aw' => { + 'value' => '3' + }, + 'SELw' => { + 'value' => '4' + }, + 'TAGw' => { + 'value' => '3' + }, + 'Dw' => { + 'value' => '32' + }, + 'EXT_INT_NUM' => { + 'value' => 2 + } + }, + 'ext_int0' => {}, + 'parameters_order' => [ + 'Dw', + 'Aw', + 'TAGw', + 'SELw', + 'EXT_INT_NUM' + ], + 'sockets' => {}, + 'module_name' => 'ext_int', + 'category' => 'Interrupt', + 'module' => 'ext_int' + }, + 'jtag_wb0' => { + 'instance_name' => 'jtag_wb', + 'plugs' => { + 'wb_master' => { + 'connection_num' => undef, + 'value' => 1, + 'type' => 'num', + 'nums' => { + '0' => { + 'connect_id' => 'wishbone_bus0', + 'connect_socket_num' => '0', + 'name' => 'wbm', + 'connect_socket' => 'wb_master' + } + } + }, + 'clk' => { + 'connection_num' => undef, + 'value' => 1, + 'type' => 'num', + 'nums' => { + '0' => { + 'connect_id' => 'clk_source0', + 'connect_socket_num' => '0', + 'name' => 'clk', + 'connect_socket' => 'clk' + } + } + }, + 'reset' => { + 'connection_num' => undef, + 'value' => 1, + 'type' => 'num', + 'nums' => { + '0' => { + 'connect_id' => 'clk_source0', + 'connect_socket_num' => '0', + 'name' => 'reset', + 'connect_socket' => 'reset' + } + } + } + }, + 'parameters' => { + 'AW' => { + 'value' => '32' + }, + 'SELw' => { + 'value' => ' 4' + }, + 'TAGw' => { + 'value' => ' 3' + }, + 'VJTAG_INDEX' => { + 'value' => 'CORE_ID' + }, + 'DW' => { + 'value' => '32' + }, + 'M_Aw' => { + 'value' => ' 32' + }, + 'S_Aw' => { + 'value' => ' 7' + } + }, + 'parameters_order' => [ + 'DW', + 'AW', + 'S_Aw', + 'M_Aw', + 'TAGw', + 'SELw', + 'VJTAG_INDEX' + ], + 'sockets' => {}, + 'module_name' => 'vjtag_wb', + 'jtag_wb0' => {}, + 'category' => 'JTAG', + 'module' => 'jtag_wb' + }, + 'timer0' => { + 'instance_name' => 'timer', + 'plugs' => { + 'reset' => { + 'connection_num' => undef, + 'value' => 1, + 'nums' => { + '0' => { + 'connect_socket_num' => '0', + 'connect_id' => 'clk_source0', + 'name' => 'reset', + 'connect_socket' => 'reset' + } + }, + 'type' => 'num' + }, + 'interrupt_peripheral' => { + 'connection_num' => undef, + 'value' => 1, + 'nums' => { + '0' => { + 'connect_socket_num' => '1', + 'connect_id' => 'lm320', + 'name' => 'interrupt_peripheral', + 'connect_socket' => 'interrupt_peripheral' + } + }, + 'type' => 'num' + }, + 'clk' => { + 'connection_num' => undef, + 'value' => 1, + 'nums' => { + '0' => { + 'connect_socket_num' => '0', + 'connect_id' => 'clk_source0', + 'name' => 'clk', + 'connect_socket' => 'clk' + } + }, + 'type' => 'num' + }, + 'wb_slave' => { + 'connection_num' => undef, + 'value' => 1, + 'nums' => { + '0' => { + 'base' => 2516582400, + 'width' => 5, + 'connect_socket_num' => '3', + 'name' => 'wb', + 'end' => 2516582431, + 'connect_socket' => 'wb_slave', + 'connect_id' => 'wishbone_bus0', + 'addr' => '0x9600_0000 0x96ff_ffff PWM/Timer/Counter Ctrl' + } + }, + 'type' => 'num' + } + }, + 'parameters' => { + 'Aw' => { + 'value' => ' 3' + }, + 'TAGw' => { + 'value' => '3' + }, + 'SELw' => { + 'value' => ' 4' + }, + 'Dw' => { + 'value' => ' 32' + }, + 'CNTw' => { + 'value' => '32 ' + } + }, + 'parameters_order' => [ + 'CNTw', + 'Dw', + 'Aw', + 'TAGw', + 'SELw' + ], + 'sockets' => {}, + 'module_name' => 'timer', + 'category' => 'Timer', + 'module' => 'timer', + 'timer0' => {} + } + }, + 'instance_order' => [ + 'clk_source0', + 'wishbone_bus0', + 'gpo0', + 'gpo1', + 'ext_int0', + 'timer0', + 'jtag_wb0', + 'lm320', + 'dual_port_ram0' + ], + 'modules' => {}, + 'gui_status' => { + 'status' => 'ideal', + 'timeout' => 0 + }, + 'global_param' => { + 'CORE_ID' => 0 + } + }, 'soc' );
mpsoc/perl_gui/lib/soc/Tutorial_lm32.SOC Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: mpsoc/perl_gui/lib/soc/lm32_tile.SOC =================================================================== --- mpsoc/perl_gui/lib/soc/lm32_tile.SOC (revision 27) +++ mpsoc/perl_gui/lib/soc/lm32_tile.SOC (revision 28) @@ -1,480 +1,232 @@ -$lm32_tile = bless( { - 'hdl_files' => undef, - 'modules' => {}, - 'soc_name' => 'lm32_tile', - 'top_ip' => bless( { - 'ports' => { - 'ni_flit_out_wr' => { - 'intfc_port' => 'flit_out_wr', - 'intfc_name' => 'socket:ni[0]', - 'instance_name' => 'ni0', - 'range' => '', - 'type' => 'output' - }, - 'ni_current_x' => { - 'intfc_port' => 'current_x', - 'intfc_name' => 'socket:ni[0]', - 'instance_name' => 'ni0', - 'range' => 'ni_Xw-1 : 0', - 'type' => 'input' - }, - 'ss_clk_in' => { - 'intfc_port' => 'clk_i', - 'intfc_name' => 'plug:clk[0]', - 'instance_name' => 'clk_source0', - 'range' => '', - 'type' => 'input' - }, - 'led_port_o' => { - 'intfc_port' => 'IO', - 'intfc_name' => 'IO', - 'instance_name' => 'gpo0', - 'range' => 'led_PORT_WIDTH-1 : 0', - 'type' => 'output' - }, - 'ni_flit_out' => { - 'intfc_port' => 'flit_out', - 'intfc_name' => 'socket:ni[0]', - 'instance_name' => 'ni0', - 'range' => 'ni_Fw-1 : 0', - 'type' => 'output' - }, - 'ni_current_y' => { - 'intfc_port' => 'current_y', - 'intfc_name' => 'socket:ni[0]', - 'instance_name' => 'ni0', - 'range' => 'ni_Yw-1 : 0', - 'type' => 'input' - }, - 'ni_credit_out' => { - 'intfc_port' => 'credit_out', - 'intfc_name' => 'socket:ni[0]', - 'instance_name' => 'ni0', - 'range' => 'ni_V-1: 0', - 'type' => 'output' - }, - 'ni_flit_in_wr' => { - 'intfc_port' => 'flit_in_wr', - 'intfc_name' => 'socket:ni[0]', - 'instance_name' => 'ni0', - 'range' => '', - 'type' => 'input' - }, - 'ni_credit_in' => { - 'intfc_port' => 'credit_in', - 'intfc_name' => 'socket:ni[0]', - 'instance_name' => 'ni0', - 'range' => 'ni_V-1 : 0', - 'type' => 'input' - }, - 'ss_reset_in' => { - 'intfc_port' => 'reset_i', - 'intfc_name' => 'plug:reset[0]', - 'instance_name' => 'clk_source0', - 'range' => '', - 'type' => 'input' - }, - 'ni_flit_in' => { - 'intfc_port' => 'flit_in', - 'intfc_name' => 'socket:ni[0]', - 'instance_name' => 'ni0', - 'range' => 'ni_Fw-1 : 0', - 'type' => 'input' - } - }, - 'interface' => { - 'socket:ni[0]' => { - 'ports' => { - 'ni_flit_out_wr' => { - 'intfc_port' => 'flit_out_wr', - 'instance_name' => 'ni0', - 'range' => '', - 'type' => 'output' - }, - 'ni_current_x' => { - 'intfc_port' => 'current_x', - 'instance_name' => 'ni0', - 'range' => 'ni_Xw-1 : 0', - 'type' => 'input' - }, - 'ni_current_y' => { - 'intfc_port' => 'current_y', - 'instance_name' => 'ni0', - 'range' => 'ni_Yw-1 : 0', - 'type' => 'input' - }, - 'ni_flit_out' => { - 'intfc_port' => 'flit_out', - 'instance_name' => 'ni0', - 'range' => 'ni_Fw-1 : 0', - 'type' => 'output' - }, - 'ni_credit_out' => { - 'intfc_port' => 'credit_out', - 'instance_name' => 'ni0', - 'range' => 'ni_V-1: 0', - 'type' => 'output' - }, - 'ni_flit_in_wr' => { - 'intfc_port' => 'flit_in_wr', - 'instance_name' => 'ni0', - 'range' => '', - 'type' => 'input' - }, - 'ni_credit_in' => { - 'intfc_port' => 'credit_in', - 'instance_name' => 'ni0', - 'range' => 'ni_V-1 : 0', - 'type' => 'input' - }, - 'ni_flit_in' => { - 'intfc_port' => 'flit_in', - 'instance_name' => 'ni0', - 'range' => 'ni_Fw-1 : 0', - 'type' => 'input' - } +####################################################################### +## File: lm32_tile.SOC +## +## Copyright (C) 2014-2016 Alireza Monemi +## +## This file is part of ProNoC 1.5.0 +## +## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT +## MAY CAUSE UNEXPECTED BEHAIVOR. +################################################################################ + +$soc = bless( { + 'hdl_files' => undef, + 'soc_name' => 'lm32_tile', + 'instances' => { + 'single_port_ram0' => { + 'single_port_ram0' => {}, + 'instance_name' => 'ram', + 'plugs' => { + 'clk' => { + 'connection_num' => undef, + 'value' => 1, + 'type' => 'num', + 'nums' => { + '0' => { + 'connect_id' => 'clk_source0', + 'connect_socket_num' => '0', + 'name' => 'clk', + 'connect_socket' => 'clk' + } } - }, - 'IO' => { - 'ports' => { - 'led_port_o' => { - 'intfc_port' => 'IO', - 'instance_name' => 'gpo0', - 'range' => 'led_PORT_WIDTH-1 : 0', - 'type' => 'output' - } - } - }, - 'plug:clk[0]' => { - 'ports' => { - 'ss_clk_in' => { - 'intfc_port' => 'clk_i', - 'instance_name' => 'clk_source0', - 'range' => '', - 'type' => 'input' - } - } - }, - 'plug:reset[0]' => { - 'ports' => { - 'ss_reset_in' => { - 'intfc_port' => 'reset_i', - 'instance_name' => 'clk_source0', - 'range' => '', - 'type' => 'input' - } - } - } - }, - 'instance_ids' => { - 'lm320' => { - 'module_name' => 'lm32', - 'category' => 'Processor', - 'instance' => 'lm32', - 'module' => 'lm32' - }, - 'clk_source0' => { - 'ports' => { - 'ss_reset_in' => { - 'intfc_port' => 'reset_i', - 'intfc_name' => 'plug:reset[0]', - 'range' => '', - 'type' => 'input' - }, - 'ss_clk_in' => { - 'intfc_port' => 'clk_i', - 'intfc_name' => 'plug:clk[0]', - 'range' => '', - 'type' => 'input' - } - }, - 'module_name' => 'clk_source', - 'category' => 'source', - 'instance' => 'ss', - 'module' => 'clk_source' - }, - 'gpo0' => { - 'parameters' => { - 'led_PORT_WIDTH' => { - 'info' => 'output port width', - 'deafult' => ' 1', - 'global_param' => 1, - 'content' => '1,32,1', - 'redefine_param' => 1, - 'type' => 'Spin-button' - } - }, - 'ports' => { - 'led_port_o' => { - 'intfc_port' => 'IO', - 'intfc_name' => 'IO', - 'range' => 'led_PORT_WIDTH-1 : 0', - 'type' => 'output' - } - }, - 'module_name' => 'gpo', - 'category' => 'GPI', - 'instance' => 'led', - 'module' => 'gpo' - }, - 'wishbone_bus0' => { - 'module_name' => 'wishbone_bus', - 'category' => 'bus', - 'instance' => 'bus', - 'module' => 'wishbone_bus' - }, - 'ni0' => { - 'parameters' => { - 'ni_TOPOLOGY' => { - 'info' => undef, - 'deafult' => '"MESH"', - 'global_param' => 1, - 'content' => '', - 'redefine_param' => 1, - 'type' => 'Fixed' - }, - 'ni_Fpay' => { - 'info' => undef, - 'deafult' => ' 32', - 'global_param' => 1, - 'content' => '', - 'redefine_param' => 1, - 'type' => 'Fixed' - }, - 'ni_NX' => { - 'info' => undef, - 'deafult' => ' 2', - 'global_param' => 1, - 'content' => '', - 'redefine_param' => 1, - 'type' => 'Fixed' - }, - 'ni_NY' => { - 'info' => undef, - 'deafult' => ' 2', - 'global_param' => 1, - 'content' => '', - 'redefine_param' => 1, - 'type' => 'Fixed' - }, - 'ni_B' => { - 'info' => undef, - 'deafult' => ' 4', - 'global_param' => 1, - 'content' => '', - 'redefine_param' => 1, - 'type' => 'Fixed' - }, - 'ni_V' => { - 'info' => undef, - 'deafult' => ' 4', - 'global_param' => 1, - 'content' => '', - 'redefine_param' => 1, - 'type' => 'Fixed' - }, - 'ni_ROUTE_TYPE' => { - 'info' => undef, - 'deafult' => '"DETERMINISTIC"', - 'global_param' => 1, - 'content' => '', - 'redefine_param' => 1, - 'type' => 'Fixed' - }, - 'ni_P' => { - 'info' => undef, - 'deafult' => ' 5', - 'global_param' => 1, - 'content' => '', - 'redefine_param' => 1, - 'type' => 'Fixed' - }, - 'ni_DEBUG_EN' => { - 'info' => undef, - 'deafult' => '0', - 'global_param' => 1, - 'content' => '', - 'redefine_param' => 1, - 'type' => 'Fixed' - }, - 'ni_ROUTE_NAME' => { - 'info' => undef, - 'deafult' => '"XY"', - 'global_param' => 1, - 'content' => '', - 'redefine_param' => 1, - 'type' => 'Fixed' - } - }, - 'ports' => { - 'ni_flit_out_wr' => { - 'intfc_port' => 'flit_out_wr', - 'intfc_name' => 'socket:ni[0]', - 'range' => '', - 'type' => 'output' - }, - 'ni_current_x' => { - 'intfc_port' => 'current_x', - 'intfc_name' => 'socket:ni[0]', - 'range' => 'ni_Xw-1 : 0', - 'type' => 'input' - }, - 'ni_current_y' => { - 'intfc_port' => 'current_y', - 'intfc_name' => 'socket:ni[0]', - 'range' => 'ni_Yw-1 : 0', - 'type' => 'input' - }, - 'ni_flit_out' => { - 'intfc_port' => 'flit_out', - 'intfc_name' => 'socket:ni[0]', - 'range' => 'ni_Fw-1 : 0', - 'type' => 'output' - }, - 'ni_credit_out' => { - 'intfc_port' => 'credit_out', - 'intfc_name' => 'socket:ni[0]', - 'range' => 'ni_V-1: 0', - 'type' => 'output' - }, - 'ni_flit_in_wr' => { - 'intfc_port' => 'flit_in_wr', - 'intfc_name' => 'socket:ni[0]', - 'range' => '', - 'type' => 'input' - }, - 'ni_credit_in' => { - 'intfc_port' => 'credit_in', - 'intfc_name' => 'socket:ni[0]', - 'range' => 'ni_V-1 : 0', - 'type' => 'input' - }, - 'ni_flit_in' => { - 'intfc_port' => 'flit_in', - 'intfc_name' => 'socket:ni[0]', - 'range' => 'ni_Fw-1 : 0', - 'type' => 'input' - } - }, - 'module_name' => 'ni', - 'category' => 'NoC', - 'instance' => 'ni', - 'module' => 'ni' - }, - 'Altera_single_port_ram0' => { - 'parameters' => { - 'ram_Dw' => { - 'info' => undef, - 'deafult' => '32', - 'global_param' => 1, - 'content' => '8,1024,1', - 'redefine_param' => 1, - 'type' => 'Spin-button' - }, - 'ram_Aw' => { - 'info' => undef, - 'deafult' => 12, - 'global_param' => 1, - 'content' => '4,31,1', - 'redefine_param' => 1, - 'type' => 'Spin-button' - } - }, - 'module_name' => 'Altera_single_port_ram', - 'category' => 'RAM', - 'instance' => 'ram', - 'module' => 'Altera_single_port_ram' - }, - 'timer0' => { - 'module_name' => 'timer', - 'category' => 'TIM', - 'instance' => 'timer', - 'module' => 'timer' - } - } - }, 'ip_gen' ), - 'instances' => { - 'clk_source0' => { - 'instance_name' => 'ss', - 'plugs' => { - 'reset' => { - 'connection_num' => undef, - 'value' => 1, - 'type' => 'num', - 'nums' => { - '0' => { - 'connect_socket_num' => undef, - 'connect_id' => 'IO', - 'name' => 'reset', - 'connect_socket' => undef - } - } - }, - 'clk' => { - 'connection_num' => undef, - 'value' => 1, - 'nums' => { - '0' => { - 'connect_id' => 'IO', - 'connect_socket_num' => undef, - 'name' => 'clk', - 'connect_socket' => undef - } - }, - 'type' => 'num' - } - }, - 'parameters' => {}, - 'parameters_order' => [], - 'clk_source0' => {}, - 'sockets' => { - 'clk' => { - 'connection_num' => 'multi connection', - 'value' => 1, - 'nums' => { - '0' => { - 'name' => 'clk' - } - }, - 'type' => 'num' - }, - 'reset' => { - 'connection_num' => 'multi connection', + }, + 'reset' => { + 'connection_num' => undef, + 'value' => 1, + 'type' => 'num', + 'nums' => { + '0' => { + 'connect_id' => 'clk_source0', + 'connect_socket_num' => '0', + 'name' => 'reset', + 'connect_socket' => 'reset' + } + } + }, + 'wb_slave' => { + 'connection_num' => undef, 'value' => 1, 'type' => 'num', 'nums' => { '0' => { - 'name' => 'reset' + 'connect_socket_num' => '0', + 'width' => 'WB_Aw', + 'base' => 0, + 'name' => 'wb', + 'connect_socket' => 'wb_slave', + 'end' => 16383, + 'connect_id' => 'wishbone_bus0', + 'addr' => '0x0000_0000 0x3fff_ffff RAM' } } } + }, + 'parameters' => { + 'SELw' => { + 'value' => 'Dw/8' + }, + 'Dw' => { + 'value' => '32' + }, + 'BTEw' => { + 'value' => '2' + }, + 'WB_Aw' => { + 'value' => 'Aw+2' + }, + 'Aw' => { + 'value' => '12' + }, + 'TAGw' => { + 'value' => '3' + }, + 'JTAG_INDEX' => { + 'value' => 'CORE_ID' + }, + 'BURST_MODE' => { + 'value' => '"ENABLED"' + }, + 'JTAG_CONNECT' => { + 'value' => '"DISABLED"' + }, + 'BYTE_WR_EN' => { + 'value' => '"YES"' + }, + 'INIT_FILE_NAME' => { + 'value' => '"ram0"' + }, + 'CTIw' => { + 'value' => '3' + }, + 'FPGA_VENDOR' => { + 'value' => '"ALTERA"' + } + }, + 'parameters_order' => [ + 'Dw', + 'Aw', + 'BYTE_WR_EN', + 'FPGA_VENDOR', + 'JTAG_CONNECT', + 'JTAG_INDEX', + 'TAGw', + 'SELw', + 'CTIw', + 'BTEw', + 'WB_Aw', + 'BURST_MODE' + ], + 'sockets' => {}, + 'module_name' => 'wb_single_port_ram', + 'category' => 'RAM', + 'module' => 'single_port_ram' + }, + 'lm320' => { + 'instance_name' => 'cpu', + 'plugs' => { + 'wb_master' => { + 'connection_num' => undef, + 'value' => 2, + 'type' => 'num', + 'nums' => { + '1' => { + 'connect_id' => 'wishbone_bus0', + 'connect_socket_num' => '1', + 'name' => 'dwb', + 'connect_socket' => 'wb_master' + }, + '0' => { + 'connect_id' => 'wishbone_bus0', + 'connect_socket_num' => '0', + 'name' => 'iwb', + 'connect_socket' => 'wb_master' + } + } + }, + 'enable' => { + 'connection_num' => undef, + 'value' => 1, + 'type' => 'num', + 'nums' => { + '0' => { + 'connect_id' => 'IO', + 'connect_socket_num' => undef, + 'name' => 'enable', + 'connect_socket' => undef + } + } }, - 'module_name' => 'clk_source', - 'category' => 'source', - 'module' => 'clk_source' - }, - 'lm320' => { - 'instance_name' => 'lm32', + 'clk' => { + 'connection_num' => undef, + 'value' => 1, + 'type' => 'num', + 'nums' => { + '0' => { + 'connect_id' => 'clk_source0', + 'connect_socket_num' => '0', + 'name' => 'clk', + 'connect_socket' => 'clk' + } + } + }, + 'reset' => { + 'connection_num' => undef, + 'value' => 1, + 'type' => 'num', + 'nums' => { + '0' => { + 'connect_id' => 'clk_source0', + 'connect_socket_num' => '0', + 'name' => 'reset', + 'connect_socket' => 'reset' + } + } + } + }, + 'parameters' => { + 'CFG_PL_BARREL_SHIFT' => { + 'value' => '"ENABLED"' + }, + 'CFG_SIGN_EXTEND' => { + 'value' => '"ENABLED"' + }, + 'CFG_PL_MULTIPLY' => { + 'value' => '"ENABLED"' + }, + 'INTR_NUM' => { + 'value' => '32' + }, + 'CFG_MC_DIVIDE' => { + 'value' => '"DISABLED"' + } + }, + 'lm320' => {}, + 'parameters_order' => [ + 'INTR_NUM', + 'CFG_PL_MULTIPLY', + 'CFG_PL_BARREL_SHIFT', + 'CFG_SIGN_EXTEND', + 'CFG_MC_DIVIDE' + ], + 'sockets' => { + 'interrupt_peripheral' => { + 'connection_num' => 'single connection', + 'value' => 'INTR_NUM', + 'type' => 'param', + 'nums' => { + '0' => { + 'name' => 'interrupt_peripheral' + } + } + } + }, + 'module_name' => 'lm32', + 'category' => 'Processor', + 'module' => 'lm32' + }, + 'clk_source0' => { + 'instance_name' => 'ss', 'plugs' => { - 'wb_master' => { - 'connection_num' => undef, - 'value' => 2, - 'type' => 'num', - 'nums' => { - '1' => { - 'connect_id' => 'wishbone_bus0', - 'connect_socket_num' => '1', - 'name' => 'dwb', - 'connect_socket' => 'wb_master' - }, - '0' => { - 'connect_id' => 'wishbone_bus0', - 'connect_socket_num' => '0', - 'name' => 'iwb', - 'connect_socket' => 'wb_master' - } - } - }, 'clk' => { 'connection_num' => undef, 'value' => 1, @@ -481,10 +233,10 @@ 'type' => 'num', 'nums' => { '0' => { - 'connect_id' => 'clk_source0', - 'connect_socket_num' => '0', + 'connect_id' => 'IO', + 'connect_socket_num' => undef, 'name' => 'clk', - 'connect_socket' => 'clk' + 'connect_socket' => undef } } }, @@ -494,601 +246,914 @@ 'type' => 'num', 'nums' => { '0' => { - 'connect_id' => 'clk_source0', - 'connect_socket_num' => '0', + 'connect_id' => 'IO', + 'connect_socket_num' => undef, 'name' => 'reset', - 'connect_socket' => 'reset' + 'connect_socket' => undef } } } }, - 'parameters' => { - 'CFG_PL_BARREL_SHIFT' => { - 'value' => '"ENABLED"' - }, - 'CFG_SIGN_EXTEND' => { - 'value' => '"ENABLED"' - }, - 'CFG_PL_MULTIPLY' => { - 'value' => '"ENABLED"' - }, - 'INTR_NUM' => { - 'value' => '32' - }, - 'CFG_MC_DIVIDE' => { - 'value' => '"DISABLED"' - } - }, - 'lm320' => {}, - 'parameters_order' => [ - 'INTR_NUM', - 'CFG_PL_MULTIPLY', - 'CFG_PL_BARREL_SHIFT', - 'CFG_SIGN_EXTEND', - 'CFG_MC_DIVIDE' - ], + 'parameters' => {}, + 'clk_source0' => {}, + 'parameters_order' => [], 'sockets' => { - 'interrupt_peripheral' => { - 'connection_num' => 'single connection', - 'value' => 'INTR_NUM', - 'type' => 'param', - 'nums' => { - '0' => { - 'name' => 'interrupt_peripheral' - } - } - } + 'clk' => { + 'connection_num' => 'multi connection', + 'value' => 1, + 'type' => 'num', + 'nums' => { + '0' => { + 'name' => 'clk' + } + } + }, + 'reset' => { + 'connection_num' => 'multi connection', + 'value' => 1, + 'type' => 'num', + 'nums' => { + '0' => { + 'name' => 'reset' + } + } + } }, - 'module_name' => 'lm32', - 'category' => 'Processor', - 'module' => 'lm32' + 'module_name' => 'clk_source', + 'category' => 'Source', + 'module' => 'clk_source' }, - 'gpo0' => { - 'gpo0' => {}, - 'instance_name' => 'led', - 'parameters' => { - 'PORT_WIDTH' => { - 'value' => ' 1' - }, - 'Aw' => { - 'value' => ' 2' - }, - 'SELw' => { - 'value' => ' 4' + 'gpo0' => { + 'gpo0' => {}, + 'instance_name' => 'gpo', + 'plugs' => { + 'clk' => { + 'connection_num' => undef, + 'value' => 1, + 'type' => 'num', + 'nums' => { + '0' => { + 'connect_id' => 'clk_source0', + 'connect_socket_num' => '0', + 'name' => 'clk', + 'connect_socket' => 'clk' + } + } + }, + 'reset' => { + 'connection_num' => undef, + 'value' => 1, + 'type' => 'num', + 'nums' => { + '0' => { + 'connect_id' => 'clk_source0', + 'connect_socket_num' => '0', + 'name' => 'reset', + 'connect_socket' => 'reset' + } + } + }, + 'wb_slave' => { + 'connection_num' => undef, + 'value' => 1, + 'type' => 'num', + 'nums' => { + '0' => { + 'connect_socket_num' => '1', + 'width' => 5, + 'base' => 2432696320, + 'name' => 'wb', + 'connect_socket' => 'wb_slave', + 'end' => 2432696351, + 'connect_id' => 'wishbone_bus0', + 'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O' + } + } + } + }, + 'parameters' => { + 'PORT_WIDTH' => { + 'value' => ' 1' }, - 'TAGw' => { - 'value' => ' 3' - }, - 'Dw' => { - 'value' => ' 32' - } - }, - 'plugs' => { - 'clk' => { - 'connection_num' => undef, - 'value' => 1, - 'type' => 'num', - 'nums' => { - '0' => { - 'connect_socket_num' => '0', - 'connect_id' => 'clk_source0', - 'name' => 'clk', - 'connect_socket' => 'clk' - } - } + 'Aw' => { + 'value' => ' 2' + }, + 'SELw' => { + 'value' => ' 4' }, - 'reset' => { - 'connection_num' => undef, - 'value' => 1, - 'nums' => { - '0' => { - 'connect_socket_num' => '0', - 'connect_id' => 'clk_source0', - 'name' => 'reset', - 'connect_socket' => 'reset' - } - }, - 'type' => 'num' - }, - 'wb_slave' => { + 'TAGw' => { + 'value' => ' 3' + }, + 'Dw' => { + 'value' => 'PORT_WIDTH' + } + }, + 'parameters_order' => [ + 'PORT_WIDTH', + 'Aw', + 'TAGw', + 'SELw', + 'Dw' + ], + 'sockets' => {}, + 'module_name' => 'gpo', + 'category' => 'GPIO', + 'module' => 'gpo' + }, + 'wishbone_bus0' => { + 'wishbone_bus0' => {}, + 'instance_name' => 'bus', + 'plugs' => { + 'clk' => { + 'connection_num' => undef, + 'value' => 1, + 'type' => 'num', + 'nums' => { + '0' => { + 'connect_id' => 'clk_source0', + 'connect_socket_num' => '0', + 'name' => 'clk', + 'connect_socket' => 'clk' + } + } + }, + 'reset' => { 'connection_num' => undef, 'value' => 1, + 'type' => 'num', 'nums' => { '0' => { - 'base' => 2432696320, - 'width' => 5, + 'connect_id' => 'clk_source0', 'connect_socket_num' => '0', - 'name' => 'wb', - 'end' => 2432696351, - 'connect_socket' => 'wb_slave', - 'connect_id' => 'wishbone_bus0', - 'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O' + 'name' => 'reset', + 'connect_socket' => 'reset' } - }, - 'type' => 'num' + } } - }, - 'parameters_order' => [ - 'PORT_WIDTH', - 'Dw', - 'Aw', - 'TAGw', - 'SELw' - ], - 'sockets' => {}, - 'module_name' => 'gpo', - 'category' => 'GPI', - 'module' => 'gpo' - }, - 'ni0' => { - 'instance_name' => 'ni', - 'plugs' => { - 'wb_master' => { - 'connection_num' => undef, - 'value' => 1, - 'nums' => { - '0' => { - 'connect_socket_num' => '2', - 'connect_id' => 'wishbone_bus0', - 'name' => 'wb_master', - 'connect_socket' => 'wb_master' - } - }, - 'type' => 'num' - }, - 'reset' => { - 'connection_num' => undef, - 'value' => 1, - 'nums' => { - '0' => { - 'connect_socket_num' => '0', - 'connect_id' => 'clk_source0', - 'name' => 'reset', - 'connect_socket' => 'reset' + }, + 'parameters' => { + 'S' => { + 'value' => 3 + }, + 'SELw' => { + 'value' => 'Dw/8' + }, + 'Dw' => { + 'value' => '32' + }, + 'BTEw' => { + 'value' => '2 ' + }, + 'Aw' => { + 'value' => '32' + }, + 'M' => { + 'value' => 4 + }, + 'TAGw' => { + 'value' => '3' + }, + 'CTIw' => { + 'value' => '3' + } + }, + 'parameters_order' => [ + 'M', + 'S', + 'Dw', + 'Aw', + 'SELw', + 'TAGw', + 'CTIw', + 'BTEw' + ], + 'sockets' => { + 'wb_master' => { + 'connection_num' => 'single connection', + 'value' => 'M', + 'type' => 'param', + 'nums' => { + '0' => { + 'name' => 'wb_master' + } + } + }, + 'wb_addr_map' => { + 'connection_num' => 'single connection', + 'value' => 1, + 'type' => 'num', + 'nums' => { + '0' => { + 'name' => 'wb_addr_map' + } + } + }, + 'wb_slave' => { + 'connection_num' => 'single connection', + 'value' => 'S', + 'type' => 'param', + 'nums' => { + '0' => { + 'name' => 'wb_slave' + } } - }, - 'type' => 'num' - }, - 'interrupt_peripheral' => { - 'connection_num' => undef, - 'value' => 1, - 'nums' => { - '0' => { - 'connect_socket_num' => '0', - 'connect_id' => 'lm320', - 'name' => 'int_peripheral', - 'connect_socket' => 'interrupt_peripheral' - } - }, - 'type' => 'num' - }, - 'clk' => { + } + }, + 'module_name' => 'wishbone_bus', + 'category' => 'Bus', + 'module' => 'wishbone_bus' + }, + 'ni0' => { + 'instance_name' => 'ni', + 'plugs' => { + 'wb_master' => { 'connection_num' => undef, 'value' => 1, + 'type' => 'num', 'nums' => { '0' => { - 'connect_socket_num' => '0', - 'connect_id' => 'clk_source0', - 'name' => 'clk', - 'connect_socket' => 'clk' + 'connect_id' => 'wishbone_bus0', + 'connect_socket_num' => '2', + 'name' => 'wb_master', + 'connect_socket' => 'wb_master' } + } + }, + 'clk' => { + 'connection_num' => undef, + 'value' => 1, + 'type' => 'num', + 'nums' => { + '0' => { + 'connect_id' => 'clk_source0', + 'connect_socket_num' => '0', + 'name' => 'clk', + 'connect_socket' => 'clk' + } + } + }, + 'interrupt_peripheral' => { + 'connection_num' => undef, + 'value' => 1, + 'type' => 'num', + 'nums' => { + '0' => { + 'connect_id' => 'lm320', + 'connect_socket_num' => '0', + 'name' => 'int_peripheral', + 'connect_socket' => 'interrupt_peripheral' + } + } + }, + 'reset' => { + 'connection_num' => undef, + 'value' => 1, + 'type' => 'num', + 'nums' => { + '0' => { + 'connect_id' => 'clk_source0', + 'connect_socket_num' => '0', + 'name' => 'reset', + 'connect_socket' => 'reset' + } + } + }, + 'wb_slave' => { + 'connection_num' => undef, + 'value' => 1, + 'type' => 'num', + 'nums' => { + '0' => { + 'connect_socket_num' => '2', + 'width' => 9, + 'base' => 3087007744, + 'name' => 'wb_slave', + 'connect_socket' => 'wb_slave', + 'end' => 3087008255, + 'connect_id' => 'wishbone_bus0', + 'addr' => '0xb800_0000 0xbfff_ffff custom devices' + } + } + } + }, + 'parameters' => { + 'Dw' => { + 'value' => ' 32' + }, + 'DEBUG_EN' => { + 'value' => '0' + }, + 'NY' => { + 'value' => ' 2' + }, + 'NX' => { + 'value' => ' 2' + }, + 'V' => { + 'value' => ' 4' + }, + 'CONGESTION_INDEX' => { + 'value' => '3' }, - 'type' => 'num' + 'COMB_PCK_SIZE_W' => { + 'value' => '12' + }, + 'Fw' => { + 'value' => '2+V+Fpay' + }, + 'TAGw' => { + 'value' => '3' }, - 'wb_slave' => { + 'COMB_MEM_PTR_W' => { + 'value' => '20' + }, + 'M_Aw' => { + 'value' => '32' + }, + 'ROUTE_NAME' => { + 'value' => '"XY"' + }, + 'Xw ' => { + 'value' => 'log2(NX)' + }, + 'Fpay' => { + 'value' => ' 32' + }, + 'ROUTE_TYPE' => { + 'value' => '"DETERMINISTIC"' + }, + 'SELw' => { + 'value' => '4 ' + }, + 'P' => { + 'value' => ' 5' + }, + 'B' => { + 'value' => ' 4' + }, + 'S_Aw' => { + 'value' => '7' + }, + 'TOPOLOGY' => { + 'value' => '"MESH"' + }, + 'Xw' => { + 'value' => 'log2(NX)' + }, + 'Yw' => { + 'value' => 'log2(NY)' + }, + 'SSA_EN' => { + 'value' => '"NO"' + }, + 'Xwj' => { + 'value' => 'fvf' + } + }, + 'parameters_order' => [ + 'V', + 'B', + 'NX', + 'NY', + 'Fpay', + 'TOPOLOGY', + 'ROUTE_NAME', + 'DEBUG_EN', + 'COMB_MEM_PTR_W', + 'COMB_PCK_SIZE_W', + 'Dw', + 'S_Aw', + 'M_Aw', + 'TAGw', + 'SELw', + 'Yw', + 'Fw', + 'Xw' + ], + 'sockets' => { + 'ni' => { + 'connection_num' => 'single connection', + 'value' => 1, + 'type' => 'num', + 'nums' => { + '0' => { + 'name' => 'ni' + } + } + } + }, + 'ni0' => {}, + 'module_name' => 'ni', + 'category' => 'NoC', + 'module' => 'ni' + }, + 'jtag_wb0' => { + 'instance_name' => 'jtag_wb0', + 'plugs' => { + 'wb_master' => { 'connection_num' => undef, 'value' => 1, 'nums' => { '0' => { - 'base' => 3087007744, - 'width' => 5, - 'connect_socket_num' => '2', - 'name' => 'wb_slave', - 'end' => 3087007775, - 'connect_socket' => 'wb_slave', + 'connect_socket_num' => '3', 'connect_id' => 'wishbone_bus0', - 'addr' => '0xb800_0000 0xbfff_ffff custom devices' + 'name' => 'wbm', + 'connect_socket' => 'wb_master' } }, 'type' => 'num' - } - }, - 'parameters' => { - 'Dw' => { - 'value' => ' 32' - }, - 'NY' => { - 'value' => ' 2' - }, - 'DEBUG_EN' => { - 'value' => '0' - }, - 'NX' => { - 'value' => ' 2' - }, - 'V' => { - 'value' => ' 4' - }, - 'COMB_PCK_SIZE_W' => { - 'value' => '12' - }, - 'Fw' => { - 'value' => '2+V+Fpay' - }, - 'TAGw' => { - 'value' => '3' - }, - 'COMB_MEM_PTR_W' => { - 'value' => '20' - }, - 'M_Aw' => { - 'value' => '32' - }, - 'ROUTE_NAME' => { - 'value' => '"XY"' - }, - 'Xw ' => { - 'value' => 'log2(NX)' - }, - 'Fpay' => { - 'value' => ' 32' - }, - 'ROUTE_TYPE' => { - 'value' => '"DETERMINISTIC"' - }, - 'SELw' => { - 'value' => '4 ' - }, - 'P' => { - 'value' => ' 5' - }, - 'B' => { - 'value' => ' 4' - }, - 'Xw' => { - 'value' => 'log2(NX)' - }, - 'TOPOLOGY' => { - 'value' => '"MESH"' - }, - 'S_Aw' => { - 'value' => ' 3' - }, - 'Yw' => { - 'value' => 'log2(NY)' - }, - 'Xwj' => { - 'value' => 'fvf' - } - }, - 'parameters_order' => [ - 'V', - 'P', - 'B', - 'NX', - 'NY', - 'Fpay', - 'TOPOLOGY', - 'ROUTE_TYPE', - 'ROUTE_NAME', - 'DEBUG_EN', - 'COMB_MEM_PTR_W', - 'COMB_PCK_SIZE_W', - 'Dw', - 'S_Aw', - 'M_Aw', - 'TAGw', - 'SELw', - 'Yw', - 'Fw', - 'Xw' - ], - 'sockets' => { - 'ni' => { - 'connection_num' => 'single connection', + }, + 'reset' => { + 'connection_num' => undef, 'value' => 1, 'nums' => { '0' => { - 'name' => 'ni' + 'connect_socket_num' => '0', + 'connect_id' => 'clk_source0', + 'name' => 'reset', + 'connect_socket' => 'reset' } }, 'type' => 'num' - } - }, - 'module_name' => 'ni', - 'category' => 'NoC', - 'module' => 'ni' + }, + 'clk' => { + 'connection_num' => undef, + 'value' => 1, + 'nums' => { + '0' => { + 'connect_socket_num' => '0', + 'connect_id' => 'clk_source0', + 'name' => 'clk', + 'connect_socket' => 'clk' + } + }, + 'type' => 'num' + } + }, + 'parameters' => { + 'AW' => { + 'value' => '32' + }, + 'TAGw' => { + 'value' => ' 3' + }, + 'SELw' => { + 'value' => ' 4' + }, + 'VJTAG_INDEX' => { + 'value' => 'CORE_ID' + }, + 'DW' => { + 'value' => '32' + }, + 'S_Aw' => { + 'value' => ' 7' + }, + 'M_Aw' => { + 'value' => ' 32' + } + }, + 'parameters_order' => [ + 'DW', + 'AW', + 'S_Aw', + 'M_Aw', + 'TAGw', + 'SELw', + 'VJTAG_INDEX' + ], + 'sockets' => {}, + 'module_name' => 'vjtag_wb', + 'jtag_wb0' => {}, + 'category' => 'JTAG', + 'module' => 'jtag_wb' + } + }, + 'top_ip' => bless( { + 'ports' => { + 'ni_flit_out_wr' => { + 'intfc_port' => 'flit_out_wr', + 'intfc_name' => 'socket:ni[0]', + 'instance_name' => 'ni0', + 'range' => '', + 'type' => 'output' + }, + 'ni_current_x' => { + 'intfc_port' => 'current_x', + 'intfc_name' => 'socket:ni[0]', + 'instance_name' => 'ni0', + 'range' => 'ni_Xw-1 : 0', + 'type' => 'input' + }, + 'ss_clk_in' => { + 'intfc_port' => 'clk_i', + 'intfc_name' => 'plug:clk[0]', + 'instance_name' => 'clk_source0', + 'range' => '', + 'type' => 'input' + }, + 'cpu_en_i' => { + 'intfc_port' => 'enable_i', + 'intfc_name' => 'plug:enable[0]', + 'instance_name' => 'lm320', + 'range' => '', + 'type' => 'input' + }, + 'ni_flit_out' => { + 'intfc_port' => 'flit_out', + 'intfc_name' => 'socket:ni[0]', + 'instance_name' => 'ni0', + 'range' => 'ni_Fw-1 : 0', + 'type' => 'output' + }, + 'ni_current_y' => { + 'intfc_port' => 'current_y', + 'intfc_name' => 'socket:ni[0]', + 'instance_name' => 'ni0', + 'range' => 'ni_Yw-1 : 0', + 'type' => 'input' + }, + 'ni_credit_out' => { + 'intfc_port' => 'credit_out', + 'intfc_name' => 'socket:ni[0]', + 'instance_name' => 'ni0', + 'range' => 'ni_V-1: 0', + 'type' => 'output' + }, + 'ni_flit_in_wr' => { + 'intfc_port' => 'flit_in_wr', + 'intfc_name' => 'socket:ni[0]', + 'instance_name' => 'ni0', + 'range' => '', + 'type' => 'input' + }, + 'gpo_port_o' => { + 'intfc_port' => 'IO', + 'intfc_name' => 'IO', + 'instance_name' => 'gpo0', + 'range' => 'gpo_PORT_WIDTH-1 : 0', + 'type' => 'output' + }, + 'ni_credit_in' => { + 'intfc_port' => 'credit_in', + 'intfc_name' => 'socket:ni[0]', + 'instance_name' => 'ni0', + 'range' => 'ni_V-1 : 0', + 'type' => 'input' + }, + 'ss_reset_in' => { + 'intfc_port' => 'reset_i', + 'intfc_name' => 'plug:reset[0]', + 'instance_name' => 'clk_source0', + 'range' => '', + 'type' => 'input' + }, + 'ni_flit_in' => { + 'intfc_port' => 'flit_in', + 'intfc_name' => 'socket:ni[0]', + 'instance_name' => 'ni0', + 'range' => 'ni_Fw-1 : 0', + 'type' => 'input' + } }, - 'wishbone_bus0' => { - 'wishbone_bus0' => {}, - 'instance_name' => 'bus', - 'parameters' => { - 'S' => { - 'value' => 4 - }, - 'SELw' => { - 'value' => '4' - }, - 'Dw' => { - 'value' => '32' - }, - 'BTEw' => { - 'value' => '2 ' - }, - 'Aw' => { - 'value' => '32' - }, - 'M' => { - 'value' => 3 - }, - 'TAGw' => { - 'value' => '3 ' - }, - 'CTIw' => { - 'value' => '3' - } - }, - 'plugs' => { - 'clk' => { - 'connection_num' => undef, - 'value' => 1, - 'type' => 'num', - 'nums' => { - '0' => { - 'connect_id' => 'clk_source0', - 'connect_socket_num' => '0', - 'name' => 'clk', - 'connect_socket' => 'clk' + 'interface' => { + 'plug:enable[0]' => { + 'ports' => { + 'cpu_en_i' => { + 'intfc_port' => 'enable_i', + 'instance_name' => 'lm320', + 'range' => '', + 'type' => 'input' } - } - }, - 'reset' => { - 'connection_num' => undef, - 'value' => 1, - 'nums' => { - '0' => { - 'connect_id' => 'clk_source0', - 'connect_socket_num' => '0', - 'name' => 'reset', - 'connect_socket' => 'reset' - } - }, - 'type' => 'num' + } + }, + 'socket:ni[0]' => { + 'ports' => { + 'ni_flit_out_wr' => { + 'intfc_port' => 'flit_out_wr', + 'instance_name' => 'ni0', + 'range' => '', + 'type' => 'output' + }, + 'ni_current_x' => { + 'intfc_port' => 'current_x', + 'instance_name' => 'ni0', + 'range' => 'ni_Xw-1 : 0', + 'type' => 'input' + }, + 'ni_current_y' => { + 'intfc_port' => 'current_y', + 'instance_name' => 'ni0', + 'range' => 'ni_Yw-1 : 0', + 'type' => 'input' + }, + 'ni_flit_out' => { + 'intfc_port' => 'flit_out', + 'instance_name' => 'ni0', + 'range' => 'ni_Fw-1 : 0', + 'type' => 'output' + }, + 'ni_credit_out' => { + 'intfc_port' => 'credit_out', + 'instance_name' => 'ni0', + 'range' => 'ni_V-1: 0', + 'type' => 'output' + }, + 'ni_flit_in_wr' => { + 'intfc_port' => 'flit_in_wr', + 'instance_name' => 'ni0', + 'range' => '', + 'type' => 'input' + }, + 'ni_credit_in' => { + 'intfc_port' => 'credit_in', + 'instance_name' => 'ni0', + 'range' => 'ni_V-1 : 0', + 'type' => 'input' + }, + 'ni_flit_in' => { + 'intfc_port' => 'flit_in', + 'instance_name' => 'ni0', + 'range' => 'ni_Fw-1 : 0', + 'type' => 'input' + } + } + }, + 'IO' => { + 'ports' => { + 'gpo_port_o' => { + 'intfc_port' => 'IO', + 'instance_name' => 'gpo0', + 'range' => 'gpo_PORT_WIDTH-1 : 0', + 'type' => 'output' + } + } + }, + 'plug:clk[0]' => { + 'ports' => { + 'ss_clk_in' => { + 'intfc_port' => 'clk_i', + 'instance_name' => 'clk_source0', + 'range' => '', + 'type' => 'input' + } } }, - 'parameters_order' => [ - 'S', - 'M', - 'Aw', - 'TAGw', - 'SELw', - 'Dw', - 'CTIw', - 'BTEw' - ], - 'sockets' => { - 'wb_master' => { - 'connection_num' => 'single connection', - 'value' => 'M', - 'nums' => { - '0' => { - 'name' => 'wb_master' + 'plug:reset[0]' => { + 'ports' => { + 'ss_reset_in' => { + 'intfc_port' => 'reset_i', + 'instance_name' => 'clk_source0', + 'range' => '', + 'type' => 'input' + } + } + } + }, + 'instance_ids' => { + 'single_port_ram0' => { + 'parameters' => { + 'ram_Dw' => { + 'info' => 'Memory data width in Bits.', + 'deafult' => '32', + 'global_param' => 'Parameter', + 'content' => '8,1024,1', + 'redefine_param' => 1, + 'type' => 'Spin-button' + }, + 'ram_Aw' => { + 'info' => 'Memory address width', + 'deafult' => '12', + 'global_param' => 'Parameter', + 'content' => '4,31,1', + 'redefine_param' => 1, + 'type' => 'Spin-button' } - }, - 'type' => 'param' - }, - 'wb_addr_map' => { - 'connection_num' => 'single connection', - 'value' => 1, - 'type' => 'num', - 'nums' => { - '0' => { - 'name' => 'wb_addr_map' - } - } - }, - 'wb_slave' => { - 'connection_num' => 'single connection', - 'value' => 'S', - 'type' => 'param', - 'nums' => { - '0' => { - 'name' => 'wb_slave' - } - } - } - }, - 'module_name' => 'wishbone_bus', - 'category' => 'bus', - 'module' => 'wishbone_bus' - }, - 'Altera_single_port_ram0' => { - 'instance_name' => 'ram', - 'Altera_single_port_ram0' => {}, - 'plugs' => { - 'reset' => { - 'connection_num' => undef, - 'value' => 1, - 'nums' => { - '0' => { - 'connect_socket_num' => '0', - 'connect_id' => 'clk_source0', - 'name' => 'reset', - 'connect_socket' => 'reset' - } + }, + 'module_name' => 'wb_single_port_ram', + 'category' => 'RAM', + 'instance' => 'ram', + 'module' => 'single_port_ram' + }, + 'lm320' => { + 'ports' => { + 'cpu_en_i' => { + 'intfc_port' => 'enable_i', + 'intfc_name' => 'plug:enable[0]', + 'range' => '', + 'type' => 'input' + } + }, + 'module_name' => 'lm32', + 'category' => 'Processor', + 'instance' => 'cpu', + 'module' => 'lm32' + }, + 'clk_source0' => { + 'ports' => { + 'ss_reset_in' => { + 'intfc_port' => 'reset_i', + 'intfc_name' => 'plug:reset[0]', + 'range' => '', + 'type' => 'input' }, - 'type' => 'num' - }, - 'clk' => { - 'connection_num' => undef, - 'value' => 1, - 'type' => 'num', - 'nums' => { - '0' => { - 'connect_id' => 'clk_source0', - 'connect_socket_num' => '0', - 'name' => 'clk', - 'connect_socket' => 'clk' - } + 'ss_clk_in' => { + 'intfc_port' => 'clk_i', + 'intfc_name' => 'plug:clk[0]', + 'range' => '', + 'type' => 'input' } - }, - 'wb_slave' => { - 'connection_num' => undef, - 'value' => 1, - 'nums' => { - '0' => { - 'connect_socket_num' => '1', - 'width' => 'WBAw', - 'base' => 0, - 'name' => 'wb_slave', - 'end' => 16383, - 'connect_socket' => 'wb_slave', - 'connect_id' => 'wishbone_bus0', - 'addr' => '0x0000_0000 0x3fff_ffff RAM' - } - }, - 'type' => 'num' - } - }, - 'parameters' => { - 'RAM_TAG_STRING' => { - 'value' => 'i2s(CORE_ID)' - }, - 'SELw' => { - 'value' => '4' - }, - 'Dw' => { - 'value' => '32' + }, + 'module_name' => 'clk_source', + 'category' => 'Source', + 'instance' => 'ss', + 'module' => 'clk_source' + }, + 'gpo0' => { + 'parameters' => { + 'gpo_PORT_WIDTH' => { + 'info' => 'output port width', + 'deafult' => ' 1', + 'global_param' => 'Parameter', + 'content' => '1,32,1', + 'redefine_param' => 1, + 'type' => 'Spin-button' + } + }, + 'ports' => { + 'gpo_port_o' => { + 'intfc_port' => 'IO', + 'intfc_name' => 'IO', + 'range' => 'gpo_PORT_WIDTH-1 : 0', + 'type' => 'output' + } + }, + 'module_name' => 'gpo', + 'category' => 'GPIO', + 'instance' => 'gpo', + 'module' => 'gpo' + }, + 'wishbone_bus0' => { + 'module_name' => 'wishbone_bus', + 'category' => 'Bus', + 'instance' => 'bus', + 'module' => 'wishbone_bus' + }, + 'ni0' => { + 'parameters' => { + 'ni_TOPOLOGY' => { + 'info' => undef, + 'deafult' => '"MESH"', + 'global_param' => 'Parameter', + 'content' => '', + 'redefine_param' => 1, + 'type' => 'Fixed' + }, + 'ni_Fpay' => { + 'info' => undef, + 'deafult' => ' 32', + 'global_param' => 'Parameter', + 'content' => '', + 'redefine_param' => 1, + 'type' => 'Fixed' + }, + 'ni_NX' => { + 'info' => undef, + 'deafult' => ' 2', + 'global_param' => 'Parameter', + 'content' => '', + 'redefine_param' => 1, + 'type' => 'Fixed' + }, + 'ni_NY' => { + 'info' => undef, + 'deafult' => ' 2', + 'global_param' => 'Parameter', + 'content' => '', + 'redefine_param' => 1, + 'type' => 'Fixed' + }, + 'ni_B' => { + 'info' => '', + 'deafult' => ' 4', + 'global_param' => 'Parameter', + 'content' => '', + 'redefine_param' => 1, + 'type' => 'Fixed' }, - 'WBAw' => { - 'value' => 'Aw+2' - }, - 'BTEw' => { - 'value' => '2' - }, - 'Aw' => { - 'value' => 12 + 'ni_V' => { + 'info' => '', + 'deafult' => ' 4', + 'global_param' => 'Parameter', + 'content' => '', + 'redefine_param' => 1, + 'type' => 'Fixed' }, - 'TAGw' => { - 'value' => '3' + 'ni_DEBUG_EN' => { + 'info' => undef, + 'deafult' => '0', + 'global_param' => 'Parameter', + 'content' => '', + 'redefine_param' => 1, + 'type' => 'Fixed' + }, + 'ni_ROUTE_NAME' => { + 'info' => undef, + 'deafult' => '"XY"', + 'global_param' => 'Parameter', + 'content' => '', + 'redefine_param' => 1, + 'type' => 'Fixed' + } + }, + 'ports' => { + 'ni_flit_out_wr' => { + 'intfc_port' => 'flit_out_wr', + 'intfc_name' => 'socket:ni[0]', + 'range' => '', + 'type' => 'output' + }, + 'ni_current_x' => { + 'intfc_port' => 'current_x', + 'intfc_name' => 'socket:ni[0]', + 'range' => 'ni_Xw-1 : 0', + 'type' => 'input' + }, + 'ni_current_y' => { + 'intfc_port' => 'current_y', + 'intfc_name' => 'socket:ni[0]', + 'range' => 'ni_Yw-1 : 0', + 'type' => 'input' + }, + 'ni_flit_out' => { + 'intfc_port' => 'flit_out', + 'intfc_name' => 'socket:ni[0]', + 'range' => 'ni_Fw-1 : 0', + 'type' => 'output' }, - 'CTIw' => { - 'value' => '3' - } - }, - 'parameters_order' => [ - 'Dw', - 'Aw', - 'TAGw', - 'SELw', - 'CTIw', - 'BTEw', - 'RAM_TAG_STRING', - 'WBAw' - ], - 'sockets' => {}, - 'module_name' => 'Altera_single_port_ram', - 'category' => 'RAM', - 'module' => 'Altera_single_port_ram' - }, - 'timer0' => { - 'instance_name' => 'timer', - 'plugs' => { - 'clk' => { - 'connection_num' => undef, - 'value' => 1, - 'type' => 'num', - 'nums' => { - '0' => { - 'connect_id' => 'clk_source0', - 'connect_socket_num' => '0', - 'name' => 'clk', - 'connect_socket' => 'clk' - } - } - }, - 'interrupt_peripheral' => { - 'connection_num' => undef, - 'value' => 1, - 'type' => 'num', - 'nums' => { - '0' => { - 'connect_id' => 'lm320', - 'connect_socket_num' => '1', - 'name' => 'interrupt_peripheral', - 'connect_socket' => 'interrupt_peripheral' - } - } - }, - 'reset' => { - 'connection_num' => undef, - 'value' => 1, - 'type' => 'num', - 'nums' => { - '0' => { - 'connect_id' => 'clk_source0', - 'connect_socket_num' => '0', - 'name' => 'reset', - 'connect_socket' => 'reset' - } - } - }, - 'wb_slave' => { - 'connection_num' => undef, - 'value' => 1, - 'type' => 'num', - 'nums' => { - '0' => { - 'connect_socket_num' => '3', - 'width' => 5, - 'base' => 2516582400, - 'name' => 'wb', - 'connect_socket' => 'wb_slave', - 'end' => 2516582431, - 'connect_id' => 'wishbone_bus0', - 'addr' => '0x9600_0000 0x96ff_ffff PWM/Timer/Counter Ctrl' - } - } - } - }, - 'parameters' => { - 'Aw' => { - 'value' => ' 3' + 'ni_credit_out' => { + 'intfc_port' => 'credit_out', + 'intfc_name' => 'socket:ni[0]', + 'range' => 'ni_V-1: 0', + 'type' => 'output' + }, + 'ni_flit_in_wr' => { + 'intfc_port' => 'flit_in_wr', + 'intfc_name' => 'socket:ni[0]', + 'range' => '', + 'type' => 'input' + }, + 'ni_credit_in' => { + 'intfc_port' => 'credit_in', + 'intfc_name' => 'socket:ni[0]', + 'range' => 'ni_V-1 : 0', + 'type' => 'input' + }, + 'ni_flit_in' => { + 'intfc_port' => 'flit_in', + 'intfc_name' => 'socket:ni[0]', + 'range' => 'ni_Fw-1 : 0', + 'type' => 'input' + } }, - 'SELw' => { - 'value' => ' 4' - }, - 'TAGw' => { - 'value' => '3' - }, - 'CNTw' => { - 'value' => '32 ' - }, - 'Dw' => { - 'value' => ' 32' - } - }, - 'parameters_order' => [ - 'CNTw', - 'Dw', - 'Aw', - 'TAGw', - 'SELw' - ], - 'sockets' => {}, - 'module_name' => 'timer', - 'category' => 'TIM', - 'timer0' => {}, - 'module' => 'timer' - } - }, - 'instance_order' => [ - 'lm320', - 'gpo0', - 'clk_source0', - 'wishbone_bus0', - 'Altera_single_port_ram0', - 'timer0', - 'ni0' - ] - }, 'soc' ); + 'module_name' => 'ni', + 'category' => 'NoC', + 'instance' => 'ni', + 'module' => 'ni' + }, + 'jtag_wb0' => { + 'parameters' => { + 'jtag_wb0_VJTAG_INDEX' => { + 'info' => 'JTAG control host identifies each instance of this IP core by a unique index number. The default value is the tile ID number. You assign an index value between 0 to 255.', + 'deafult' => 'CORE_ID', + 'global_param' => 'Parameter', + 'content' => '', + 'redefine_param' => 1, + 'type' => 'Entry' + } + }, + 'module_name' => 'vjtag_wb', + 'category' => 'JTAG', + 'instance' => 'jtag_wb0', + 'module' => 'jtag_wb' + } + } + }, 'ip_gen' ), + 'instance_order' => [ + 'lm320', + 'single_port_ram0', + 'gpo0', + 'clk_source0', + 'wishbone_bus0', + 'ni0', + 'jtag_wb0' + ], + 'modules' => {}, + 'gui_status' => { + 'status' => 'ideal', + 'timeout' => 0 + }, + 'global_param' => { + 'CORE_ID' => 3 + } + }, 'soc' ); Index: mpsoc/script/foo =================================================================== --- mpsoc/script/foo (revision 27) +++ mpsoc/script/foo (nonexistent)
mpsoc/script/foo Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: mpsoc/script/Makefile =================================================================== --- mpsoc/script/Makefile (revision 27) +++ mpsoc/script/Makefile (revision 28) @@ -1,26 +1,51 @@ -VERILATED_CPP = /usr/share/verilator/include/verilated.cpp -VERILATED_INC = -I/usr/share/verilator/include +# -*- Makefile -*- +#***************************************************************************** +# +# DESCRIPTION: Verilator Example: Makefile for inside object directory +# +# This is executed in the object directory, and called by ../Makefile +# +# Copyright 2003-2014 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# +#***************************************************************************** + +default: sim + MUDULB = Vnoc MUDULA = Vrouter MUDULC = Vtraffic -sim: - #Compile your test code - g++ -I. -L. $(VERILATED_INC) -o testbench testbench.cpp -l$(MUDULA) -l$(MUDULB) -l$(MUDULC) -Wall -O3 - - -lib: - #Create object files - g++ -c -I. $(VERILATED_INC) $(VERILATED_CPP) -O3 - g++ -c -I. $(VERILATED_INC) $(MUDULA).cpp $(MUDULA)__Syms.cpp -O3 - g++ -c -I. $(VERILATED_INC) $(MUDULB).cpp $(MUDULB)__Syms.cpp -O3 - g++ -c -I. $(VERILATED_INC) $(MUDULC).cpp $(MUDULC)__Syms.cpp -O3 - #Link object files into static library - ar rcs lib$(MUDULA).a $(MUDULA).o $(MUDULA)__Syms.o verilated.o - ar rcs lib$(MUDULB).a $(MUDULB).o $(MUDULB)__Syms.o - ar rcs lib$(MUDULC).a $(MUDULC).o $(MUDULC)__Syms.o - #Remove object files - rm *.o +include Vrouter.mk + +lib: + $(MAKE) -f $(MUDULA).mk + $(MAKE) -f $(MUDULB).mk + $(MAKE) -f $(MUDULC).mk + + +####################################################################### +# Compile flags + +CPPFLAGS += -DVL_DEBUG=1 +ifeq ($(CFG_WITH_CCWARN),yes) # Local... Else don't burden users +CPPFLAGS += -DVL_THREADED=1 +CPPFLAGS += -W -Werror -Wall +endif + +####################################################################### +# Linking final exe -- presumes have a sim_main.cpp + + +sim: testbench.o $(VK_GLOBAL_OBJS) $(MUDULB)__ALL.a $(MUDULA)__ALL.a $(MUDULC)__ALL.a + $(LINK) $(LDFLAGS) -g $^ $(LOADLIBES) $(LDLIBS) -o testbench $(LIBS) -Wall -O3 2>&1 | c++filt + +testbench.o: testbench.cpp $(MUDULA).h $(MUDULB).h $(MUDULC).h + clean: rm *.o *.a main + +
/mpsoc/script/parameter.sh
11,7 → 11,8
 
# NoC parameters:
V=2 # number of VC per port
P=5 # number of port per router
TOPOLOGY="MESH" #"MESH" or "TORUS"
P="(TOPOLOGY==\"RING\")? 3 : 5" # number of port per router
B=4 # buffer space :flit per VC
NX=8 # number of node in x axis
NY=8 # number of node in y axis
21,7 → 22,7
VC_REALLOCATION_TYPE="NONATOMIC" # "ATOMIC" or "NONATOMIC"
COMBINATION_TYPE="COMB_NONSPEC" # "BASELINE" or "COMB_SPEC1" or "COMB_SPEC2" or "COMB_NONSPEC"
FIRST_ARBITER_EXT_P_EN=0
TOPOLOGY="MESH" #"MESH" or "TORUS"
ROUTE_NAME="XY" # Routing algorithm
# mesh : "XY" , "WEST_FIRST" , "NORTH_LAST" , "NEGETIVE_FIRST" , "DUATO"
# torus: "TRANC_XY" , "TRANC_WEST_FIRST", "TRANC_NORTH_LAST", "TRANC_NEGETIVE_FIRST", "TRANC_DUATO"
28,10 → 29,12
CLASS_SETTING="{CVw{1'b1}}"
SSA_EN="NO"
ADD_PIPREG_AFTER_CROSSBAR=0
ADD_PIPREG_BEFORE_CROSSBAR=0
#simulation parameters:
C0_p=100 # the percentage of injected packets with class 0
C1_p=0
85,7 → 88,8
generate_parameter_v (){
printf " \`ifdef INCLUDE_PARAM \n\n" >> parameter.v
printf " parameter V=$V;\n" >> parameter.v
printf " parameter V=$V;\n" >> parameter.v
printf " parameter TOPOLOGY=\"$TOPOLOGY\";\n" >> parameter.v
printf " parameter P=$P;\n" >> parameter.v
printf " parameter B=$B;\n" >> parameter.v
printf " parameter NX=$NX;\n" >> parameter.v
96,7 → 100,7
printf " parameter VC_REALLOCATION_TYPE=\"$VC_REALLOCATION_TYPE\";\n" >> parameter.v
printf " parameter COMBINATION_TYPE=\"$COMBINATION_TYPE\";\n" >> parameter.v
printf " parameter FIRST_ARBITER_EXT_P_EN=$FIRST_ARBITER_EXT_P_EN;\n" >> parameter.v
printf " parameter TOPOLOGY=\"$TOPOLOGY\";\n" >> parameter.v
printf " parameter ROUTE_NAME=\"$ROUTE_NAME\";\n" >> parameter.v
printf " parameter CONGESTION_INDEX=$CONGESTION_INDEX;\n" >> parameter.v
printf " parameter C0_p=$C0_p;\n" >> parameter.v
122,10 → 126,10
printf " parameter AVC_ATOMIC_EN= $AVC_ATOMIC_EN;\n">> parameter.v
printf " parameter AVG_LATENCY_METRIC= \"$AVG_LATENCY_METRIC\";\n">> parameter.v
printf " parameter ADD_PIPREG_AFTER_CROSSBAR= $ADD_PIPREG_AFTER_CROSSBAR;\n" >> parameter.v
printf " parameter ADD_PIPREG_BEFORE_CROSSBAR= $ADD_PIPREG_BEFORE_CROSSBAR;\n" >> parameter.v
printf " parameter CVw=(C==0)? V : C * V;\n" >> parameter.v
printf " parameter [CVw-1: 0] CLASS_SETTING = $CLASS_SETTING;\n">> parameter.v
printf " parameter [V-1 : 0] ESCAP_VC_MASK=$ESCAP_VC_MASK;\n" >> parameter.v
printf " parameter [V-1 : 0] ESCAP_VC_MASK=$ESCAP_VC_MASK;\n" >> parameter.v
printf " parameter SSA_EN= \"$SSA_EN\";\n">> parameter.v
printf " \n\n \`endif " >> parameter.v
170,10 → 174,10
printf "\t #define STND_DEV_EN $STND_DEV_EN\n">> parameter.h
printf "\t #define AVG_LATENCY_METRIC \"$AVG_LATENCY_METRIC\"\n">> parameter.h
printf "\t #define ADD_PIPREG_AFTER_CROSSBAR $ADD_PIPREG_AFTER_CROSSBAR\n" >> parameter.h
printf "\t #define ADD_PIPREG_BEFORE_CROSSBAR $ADD_PIPREG_BEFORE_CROSSBAR\n" >> parameter.h
printf "\t #define CVw (C==0)? V : C * V\n" >> parameter.h
printf "\t #define CLASS_SETTING \"$CLASS_SETTING\"\n">> parameter.h
printf "\t #define ESCAP_VC_MASK $ESCAP_VC_MASK\n">> parameter.h
printf "\t #define ESCAP_VC_MASK $ESCAP_VC_MASK\n">> parameter.h
printf "\t #define SSA_EN \"$SSA_EN\"\n" >> parameter.h
printf " \n\n #endif " >> parameter.h
}
/mpsoc/script/verilator_2D_mesh.sh
115,7 → 115,6
printf " parameter ROUTE_TYPE = (ROUTE_NAME == \"XY\" || ROUTE_NAME == \"TRANC_XY\" )? \"DETERMINISTIC\" : \n" >> parameter.v
printf " (ROUTE_NAME == \"DUATO\" || ROUTE_NAME == \"TRANC_DUATO\" )? \"FULL_ADAPTIVE\": \"PAR_ADAPTIVE\"; \n" >> parameter.v
printf " parameter ADD_PIPREG_AFTER_CROSSBAR= $ADD_PIPREG_AFTER_CROSSBAR;\n" >> parameter.v
printf " parameter ADD_PIPREG_BEFORE_CROSSBAR= $ADD_PIPREG_BEFORE_CROSSBAR;\n" >> parameter.v
printf " parameter CVw=(C==0)? V : C * V;\n" >> parameter.v
printf " parameter [CVw-1: 0] CLASS_SETTING = $CLASS_SETTING;\n">> parameter.v
printf " parameter [V-1 : 0] ESCAP_VC_MASK=$ESCAP_VC_MASK;\n" >> parameter.v
156,7 → 155,6
printf "\t #define PACKET_SIZE $PACKET_SIZE\n" >> parameter.h
printf "\t #define DEBUG_EN $DEBUG_EN \n" >> parameter.h
printf "\t #define ADD_PIPREG_AFTER_CROSSBAR $ADD_PIPREG_AFTER_CROSSBAR\n" >> parameter.h
printf "\t #define ADD_PIPREG_BEFORE_CROSSBAR $ADD_PIPREG_BEFORE_CROSSBAR\n" >> parameter.h
printf "\t #define CVw (C==0)? V : C * V\n" >> parameter.h
printf "\t #define CLASS_SETTING \"$CLASS_SETTING\"\n">> parameter.h
printf "\t #define ESCAP_VC_MASK $ESCAP_VC_MASK\n">> parameter.h
/mpsoc/script/verilator_compile_hw.sh
33,9 → 33,9
cd processed_rtl
 
verilator --cc router_verilator.v --profile-cfuncs --prefix "Vrouter" -O3
verilator --cc noc_connection.sv --prefix "Vnoc" -O3
verilator --cc --profile-cfuncs traffic_gen_verilator.v --prefix "Vtraffic" -O3
verilator --cc router_verilator.v --profile-cfuncs --prefix "Vrouter" -O3 -CFLAGS -O3
verilator --cc noc_connection.sv --prefix "Vnoc" -O3 -CFLAGS -O3
verilator --cc --profile-cfuncs traffic_gen_verilator.v --prefix "Vtraffic" -O3 -CFLAGS -O3
 
 
cp $script_path/Makefile obj_dir/
/mpsoc/script/verilator_multiple/verilator_ssa.sh
0,0 → 1,304
#!/bin/sh
set -e
# Any subsequent commands which fail will cause the shell script to exit immediately
 
my_dir="$(dirname "$0")"
source "$my_dir/../parameter.sh"
 
 
cd ..
script_path=$(pwd)
path=$script_path/..
comp_path=$path/../mpsoc_work/verilator
work_path=$comp_path/work
bin_path=$work_path/bin
multiple_path=$work_path/ssa4
data_path=$multiple_path/data
plot_path=$multiple_path/plot
src_c_path=$path/src_c
plot_c_path=$src_c_path/plot
 
rm -Rf $multiple_path
mkdir -p $data_path
mkdir -p $plot_path
 
#cp $path/src_c/plot/plot $multiple_path/plot_bin
 
 
 
V=4 # number of VC per port
B=5 # buffer space :flit per VC
NX=8 # number of node in x axis
NY=8 # number of node in y axis
C=4 # number of flit class
COMBINATION_TYPE="COMB_NONSPEC" # "BASELINE" or "COMB_SPEC1" or "COMB_SPEC2" or "COMB_NONSPEC"
FIRST_ARBITER_EXT_P_EN=0
ROUTE_NAME="XY"
CLASS_SETTING="16'b111111111111111"
#simulation parameters:
C0_p=25 # the percentage of injected packets with class 0
C1_p=25
C2_p=25
C3_p=25
# Simulation parameters:
#Hotspot Traffic setting
HOTSPOT_PERCENTAGE=3 #maximum 20
HOTSOPT_NUM=4 #maximum 5
HOTSPOT_CORE_1=$(CORE_NUM 2 2)
HOTSPOT_CORE_2=$(CORE_NUM 2 6)
HOTSPOT_CORE_3=$(CORE_NUM 6 2)
HOTSPOT_CORE_4=$(CORE_NUM 6 6)
MAX_PCK_NUM=256000
MAX_SIM_CLKs=100000
MAX_PCK_SIZ=10 # maximum flit number in a single packet
ESCAP_VC_MASK="4'b0001" # mask scape vc
DEBUG_EN=1
CONGESTION_INDEX=3 # 0: packets are routed to the ports with more available VCs
# 1: packets are routed to the ports with more available credits
# 2: packets are routed to the ports connected to the routers with less active ivc requests
# 3: packets are routed to the ports connected to the routers with less active ivc requests that are not granted
 
 
 
 
#
AVC_ATOMIC_EN=0
STND_DEV_EN=0 # 1: generate standard devision
TIMSTMP_FIFO_NUM=8
 
 
 
generate_plot_command(){
 
rm -f plot_command.h
 
cat > plot_command.h << EOF
#ifndef PLOT_COMMAND_H
#define PLOT_COMMAND_H
 
char * commandsForGnuplot[] = {
"set terminal postscript eps enhanced color font 'Helvetica,15'",
"set output 'temp.eps' ",
"set style line 1 lc rgb \"red\" lt 1 lw 2 pt 4 ps 1.5",
"set style line 2 lc rgb \"blue\" lt 1 lw 2 pt 6 ps 1.5",
"set style line 3 lc rgb \"green\" lt 1 lw 2 pt 10 ps 1.5",
"set style line 4 lc rgb '#8B008B' lt 1 lw 2 pt 14 ps 1.5",//darkmagenta
"set style line 5 lc rgb '#B8860B' lt 1 lw 2 pt 2 ps 1.5", //darkgoldenrod
"set style line 6 lc rgb \"gold\" lt 1 lw 2 pt 3 ps 1.5",
"set style line 7 lc rgb '#FF8C00' lt 1 lw 2 pt 10 ps 1.5",//darkorange
"set style line 8 lc rgb \"black\" lt 1 lw 2 pt 1 ps 1.5",
"set style line 9 lc rgb \"spring-green\" lt 1 lw 2 pt 8 ps 1.5",
"set style line 10 lc rgb \"yellow4\" lt 1 lw 2 pt 0 ps 1.5",
"set yrange [0:45]",
"set xrange [0:]",
0
};
 
#endif
 
EOF
 
mv -f plot_command.h $plot_c_path/plot_command.h
cd $plot_c_path
make
cp $plot_c_path/plot $multiple_path/plot_bin
cd $script_path
 
}
 
 
 
 
################
#
# regenerate_NoC
#
################
regenerate_NoC() {
generate_parameter_v
mv -f parameter.v ../src_verilator/
#verilate the NoC and make the library files
#################################################################3
./verilator_compile_hw.sh
 
# compile the testbench file
generate_parameter_h
mv -f parameter.h ../src_verilator/
 
./verilator_compile_sw.sh
cp $bin_path/testbench $multiple_path/$testbench_name
}
 
 
################
#
# merg_files
#
################
merg_files(){
if [ $STND_DEV_EN -eq 1 ]
then
 
target="_std"
else
target="_all"
 
fi
 
data_file=$data_path/${plot_name}${target}".txt"
plot_file=$plot_path/${plot_name}${target}".eps"
printf "#name:"$CURVE_NAME"\n" >> $data_file
cat ${testbench_name}${target}".txt" >> $data_file
printf "\n\n" >> $data_file
./plot_bin $data_file $plot_file "Injection ratio flits/node/clk" "Average latency clk" "outside left"
if [ $C -gt 1 ]
then
data_file=$data_path/$plot_name"_c0.txt"
plot_file=$plot_path/$plot_name"_c0.eps"
printf "#name:"$CURVE_NAME"\n" >> $data_file
cat $testbench_name"_c0.txt" >> $data_file
printf "\n\n" >> $data_file
./plot_bin $data_file $plot_file "Injection ratio flits/node/clk" "Average latency clk" "outside left"
data_file=$data_path/$plot_name"_c1.txt"
plot_file=$plot_path/$plot_name"_c1.eps"
printf "#name:"$CURVE_NAME"\n" >> $data_file
cat $testbench_name"_c1.txt" >> $data_file
printf "\n\n" >> $data_file
./plot_bin $data_file $plot_file "Injection ratio flits/node/clk" "Average latency clk" "outside left"
fi
rm $testbench_name*
}
 
gen_testbench_name(){
testbench_name=$routename"_"$SSA_EN
}
 
gen_plot_name(){
plot_name=$routename"_"$TRAFFIC"_"$PACKET_SIZE
}
 
 
 
 
 
 
################
#
# run_sim
#
################
run_sim(){
 
for SSA_EN in "YES" "NO"
do
gen_testbench_name
regenerate_NoC
done
 
 
 
cd $multiple_path
for SSA_EN in "YES" "NO"
do
gen_testbench_name
CMD="./$testbench_name $testbench_name"
command $CMD &
done
# wait for all simulation to be done
wait
# merge the results in one file
VC_REALLOCATION_TYPE="NONATOMIC"
for SSA_EN in "YES" "NO"
do
gen_testbench_name
gen_plot_name
CURVE_NAME=$SSA_EN
merg_files
done # ROUTE_NAME
 
cd $script_path
}
 
generate_plot_command
 
 
 
 
for PACKET_SIZE in 4 # 6
do
for TRAFFIC in "RANDOM" # "BIT_REVERSE" "BIT_COMPLEMENT" "RANDOM" "HOTSPOT" "TRANSPOSE1" "TORNADO" #"CUSTOM"
do
run_sim
done
done #PACKET_SIZE
mpsoc/script/verilator_multiple/verilator_ssa.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: mpsoc/src_c/Makefile =================================================================== --- mpsoc/src_c/Makefile (revision 27) +++ mpsoc/src_c/Makefile (revision 28) @@ -1,6 +1,6 @@ TOOLCHAIN:=${PRONOC_WORK}/toolchain SUBDIRS = ihex2bin ihex2mif jtag plot -BIN_FILES = ihex2bin/ihex2bin ihex2mif/ihex2mif jtag/jtag_main +BIN_FILES = ihex2bin/ihex2bin ihex2mif/ihex2mif PRONOC_WORK_BIN := $(TOOLCHAIN)/bin @@ -14,5 +14,6 @@ binfiles: mkdir -p $(PRONOC_WORK_BIN) - cp -f $(BIN_FILES) $(PRONOC_WORK_BIN) - + cp -f $(BIN_FILES) $(PRONOC_WORK_BIN) + cp jtag/simple_jtag/jtag_main $(PRONOC_WORK_BIN)/jtag_main +# cp jtag/urjtag-0.10/src/jtag_main $(PRONOC_WORK_BIN)/jtag_main
/mpsoc/src_c/jtag/jinfo Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/mpsoc/src_c/jtag/jinfo
mpsoc/src_c/jtag/jinfo Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: mpsoc/src_c/jtag/jtag-virtual.c =================================================================== --- mpsoc/src_c/jtag/jtag-virtual.c (revision 27) +++ mpsoc/src_c/jtag/jtag-virtual.c (nonexistent) @@ -1,139 +0,0 @@ -/* Copyright 2012 Brian Swetland - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include - -#include "jtag.h" - -int jtag_dr_8x4(unsigned *out) { - unsigned bits = 0; - unsigned tmp; - int n, r; - - for (n = 0; n < 8; n++) { - if ((r = jtag_dr(4, 0, &tmp)) < 0) return r; - bits |= (tmp <<= (n * 4)); - } - *out = bits; - return 0; -} - -/* number of bits needed given a max value 1-255 */ -unsigned needbits(unsigned max) { - if (max > 127) return 8; - if (max > 63) return 7; - if (max > 31) return 6; - if (max > 15) return 5; - if (max > 7) return 4; - if (max > 3) return 3; - if (max > 1) return 2; - return 1; -} - -static unsigned ir_width = 10; - -static unsigned hub_version = 0; -static unsigned hub_nodecount = 0; -static unsigned hub_mfg = 0; - -static unsigned vir_width = 0; -static unsigned vir_width_addr = 0; -static unsigned vir_width_ir = 0; -static unsigned vir_addr = 0; - - -int jtag_vir(unsigned vir) { - int r; - if ((r = jtag_ir(ir_width, 14)) < 0) return r; - if ((r = jtag_dr(vir_width, vir_addr | vir, 0)) < 0) return r; - return 0; -} - -int jtag_vdr(unsigned sz, unsigned bits, unsigned *out) { - int r; - if ((r = jtag_ir(ir_width, 12)) < 0) return r; - if ((r = jtag_dr(sz, bits, out)) < 0) return r; - return 0; -} - -int jtag_vdr_long(unsigned sz, unsigned * bits, unsigned *out, int words) { - int r; - if ((r = jtag_ir(ir_width, 12)) < 0) return r; - if ((r = jtag_dr_long(sz, bits, out, words)) < 0) return r; - return 0; -} - -int jtag_open_virtual_device(unsigned iid) { - unsigned n, bits; - int r; - - if ((r = jtag_open()) < 0) return r; - - if ((r = jtag_reset()) < 0) return r; - - /* select empty node_addr + node_vir -- all zeros */ - if ((r = jtag_ir(ir_width, 14)) < 0) return r; - if ((r = jtag_dr(32, 0, 0)) < 0) return r; - - /* select vdr - this will be the hub info (addr=0,vir=0) */ - if ((r = jtag_ir(ir_width, 12)) < 0) return r; - - /* read hub info */ - if ((r = jtag_dr_8x4(&bits)) < 0) return r; - hub_version = (bits >> 27) & 0x1F; - hub_nodecount = (bits >> 19) & 0xFF; - hub_mfg = (bits >> 8) & 0x7FF; - - if (hub_mfg != 0x06e) { - fprintf(stderr,"HUB: Cannot Find Virtual JTAG HUB\n"); - return -1; - } - - /* altera docs claim this field is the sum of M bits (VIR field) and - * N bits (ADDR field), but empirical evidence suggests it is actually - * just the width of the ADDR field and the docs are wrong... - */ - vir_width_ir = bits & 0xFF; - vir_width_addr = needbits(hub_nodecount); - vir_width = vir_width_ir + vir_width_addr; - - fprintf(stderr,"HUB: Mfg=0x%03x, Ver=0x%02x, Nodes=%d, VIR=%d+%d bits\n", - hub_mfg, hub_version, hub_nodecount, vir_width_addr, vir_width_ir); - - for (n = 0; n < hub_nodecount; n++) { - unsigned node_ver, node_id, node_mfg, node_iid; - if ((r = jtag_dr_8x4(&bits)) < 0) return r; - node_ver = (bits >> 27) & 0x1F; - node_id = (bits >> 19) & 0xFF; - node_mfg = (bits >> 8) & 0x7FF; - node_iid = bits & 0xFF; - - fprintf(stderr,"NODE: Mfg=0x%03x, Ver=0x%02x, ID=0x%02x, IID=0x%02x\n", - node_mfg, node_ver, node_id, node_iid); - - if ((node_id == 0x08) && (node_iid) == iid) { - vir_addr = (n + 1) << vir_width_ir; - } - } - - if ((vir_addr == 0) && (iid < 256)) { - fprintf(stderr,"ERROR: IID 0x%02x not found\n", iid); - return -1; - } - return 0; -} - -
mpsoc/src_c/jtag/jtag-virtual.c Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: mpsoc/src_c/jtag/jtag.h =================================================================== --- mpsoc/src_c/jtag/jtag.h (revision 27) +++ mpsoc/src_c/jtag/jtag.h (nonexistent) @@ -1,50 +0,0 @@ -/* Copyright 2012 Brian Swetland - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef _JTAG_H_ -#define _JTAG_H_ - -int jtag_open(void); -int jtag_close(void); - -/* move into RESET state */ -int jtag_reset(void); - -/* clock count times, TDI=0, TMS=bits[0], bits >>= 1 */ -int jtag_move(int count, unsigned bits); - -/* clock count-1 times, TMS=0, TDI=bits[0], bits >>= 1 - * clock 1 time, TMS=1, TDI=bits[0] - * if out, capture TDO into out - */ -int jtag_shift(int count, unsigned bits, unsigned *out); - - -/* load sz bits into IR */ -int jtag_ir(unsigned sz, unsigned bits); - -/* load sz bits into DR, capture sz bits into out if non-null */ -int jtag_dr(unsigned sz, unsigned bits, unsigned *out); -int jtag_dr_long(unsigned sz, unsigned * bits, unsigned *out, int words); - - - -/* altera virtual jtag support */ -int jtag_open_virtual_device(unsigned iid); -int jtag_vir(unsigned vir); -int jtag_vdr(unsigned sz, unsigned bits, unsigned *out); -int jtag_vdr_long(unsigned , unsigned * , unsigned *, int ); - -#endif
mpsoc/src_c/jtag/jtag.h Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: mpsoc/src_c/jtag/jinfo.c =================================================================== --- mpsoc/src_c/jtag/jinfo.c (revision 27) +++ mpsoc/src_c/jtag/jinfo.c (nonexistent) @@ -1,36 +0,0 @@ -/* Copyright 2012 Brian Swetland - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include "jtag.h" - -int main(int argc, char **argv) { - unsigned bits; - - if (jtag_open() < 0) - return -1; - - if (jtag_reset() < 0) - return -1; - if (jtag_dr(32, 0, &bits) < 0) - return -1; - fprintf(stderr,"IDCODE: %08x\n", bits); - - if (jtag_open_virtual_device(0xffffffff)) - return -1; - - jtag_close(); - return 0; -}
mpsoc/src_c/jtag/jinfo.c Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: mpsoc/src_c/jtag/rom.bin =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: mpsoc/src_c/jtag/rom.bin =================================================================== --- mpsoc/src_c/jtag/rom.bin (revision 27) +++ mpsoc/src_c/jtag/rom.bin (nonexistent)
mpsoc/src_c/jtag/rom.bin Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: mpsoc/src_c/jtag/README =================================================================== --- mpsoc/src_c/jtag/README (revision 27) +++ mpsoc/src_c/jtag/README (nonexistent) @@ -1,20 +0,0 @@ - -Quick hack commandline tools to interact with Altera FPGA Virtual JTAG interfaces, -using the USB Blaster device (as integrated on Terasic dev boards, etc). - -Not terribly fancy or optimized but only depends on libusb-1.0 - -Currently does not support multiple devices on the chain. - -jtag.c - provides simple jtag interface -jtag-virtual.c - provides simple virtual jtag interface - -jload.c - example of using the virtual jtag interface for a downloader interface - with a CTRL/ADDR/DATA register set. CTRL[0] asserts reset, writes to - DATA store to [ADDR] and auto-increment ADRR. - -jinfo.c - dumps idcode and virtual jtag hub and device info table - - -Why? Scripting the Altera quartus_stp tool in TCL was driving me nuts. -
mpsoc/src_c/jtag/README Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: mpsoc/src_c/jtag/jtag_main =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: mpsoc/src_c/jtag/jtag_main =================================================================== --- mpsoc/src_c/jtag/jtag_main (revision 27) +++ mpsoc/src_c/jtag/jtag_main (nonexistent)
mpsoc/src_c/jtag/jtag_main Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: mpsoc/src_c/jtag/jtag_main.c =================================================================== --- mpsoc/src_c/jtag/jtag_main.c (revision 27) +++ mpsoc/src_c/jtag/jtag_main.c (nonexistent) @@ -1,363 +0,0 @@ -#include -#include -#include -#include -#include // getopt -#include -#include -#include "jtag.h" - - - - -#define UPDATE_WB_ADDR 0x7 -#define UPDATE_WB_WR_DATA 0x6 -#define UPDATE_WB_RD_DATA 0x5 -#define RD_WR_STATUS 0x4 - -#define BIT_NUM (word_width<<3) -#define BYTE_NUM word_width -/* Global vars */ -unsigned int index_num=126; -unsigned int word_width=4; // -unsigned int write_verify=0; -unsigned int memory_offset=0; -unsigned int memory_boundary=0xFFFFFFFF; - - - -char * binary_file_name=0; -char enable_binary_send=0; -char * write_data=0; - - - - -/* functions */ -int send_binary_file(); -void usage(); -void processArgs (int , char** ); -int send_data (); -int hexcut( char * , unsigned * , int ); -int vdr_large (unsigned , char * , char *); -void hexgen( char * , unsigned *, int ); - -int main(int argc, char **argv) { - //unsigned bits; - //unsigned int val; - - //unsigned bits; - //unsigned val; - - processArgs (argc, argv ); - printf("index num=%u\n",index_num); - if (jtag_open_virtual_device(index_num)){ - fprintf (stderr, "Error openning jtag IP with %d index num\n",index_num); - return -1; - } - if (enable_binary_send) { - if( send_binary_file() == -1) return -1; - } - - if (write_data!=0){ - printf("send %s to jtag\n",write_data); - send_data(); - - - } - - return 0; -} - - - -void usage(){ - - printf ("usage:./jtag_main [-n index number] [-i file_name][-c][-s rd/wr offset address][-d string]\n"); - - printf ("\t-n index number: the target jtag IP core index number. The default number is 126\n"); - printf ("\t-i file_name: input binary file name (.bin file)\n"); - printf ("\t-w bin file word width in byte. default is 4 bytes (32 bits)\n"); - printf ("\t-c verify after write\n"); - printf ("\t-s memory wr/rd offset address in hex. The default value is 0x0000000\n"); - printf ("\t-e memory boundary address in hex. The default value is 0xFFFFFFFF\n"); - printf ("\t-d string: use for setting instruction or data value to jtag tap. string format : \"instr1,instr2,...,instrn\"\n \tinstri = I:instruct_num: send instruct_num to instruction register \n \tD:data_size_in_bit:data : send data in hex to data register\n \tR:data_size_in_bit:data : Read data register and show it on screan then write given data in hex to data register\n"); - -} - -void processArgs (int argc, char **argv ) -{ - char c; -int p; - - /* don't want getopt to moan - I can do that just fine thanks! */ - opterr = 0; - if (argc < 2) usage(); - while ((c = getopt (argc, argv, "s:e:d:n:i:w:c")) != -1) - { - switch (c) - { - case 'n': /* index number */ - index_num = atoi(optarg); - break; - case 'i': /* input binary file name */ - binary_file_name = optarg; - enable_binary_send=1; - break; - case 'w': /* word width in byte */ - word_width= atoi(optarg); - break; - case 'c': /* word width in byte */ - write_verify= 1; - break; - case 'd': /* word width in byte */ - write_data= optarg; - break; - case 's': /* word width in byte */ - - p=sscanf(optarg,"%x",&memory_offset); - if( p==0){ - fprintf (stderr, "invalid memory offset adress format `%s'.\n", optarg); - usage(); - exit(1); - } - //printf("p=%d,memory_offset=%x\n",p,memory_offset); - break; - case 'e': /* word width in byte */ - p=sscanf(optarg,"%x",&memory_boundary); - if( p==0){ - fprintf (stderr, "invalid memory boundary adress format `%s'.\n", optarg); - usage(); - exit(1); - } - break; - - case '?': - if (isprint (optopt)) - fprintf (stderr, "Unknown option `-%c'.\n", optopt); - else - fprintf (stderr, - "Unknown option character `\\x%x'.\n", - optopt); - default: - usage(); - exit(1); - } - } -} - -unsigned * read_file (FILE * fp, unsigned int * n ){ - - unsigned * buffer; - unsigned val; - unsigned char ch; - unsigned int i=0; - char cnt=0; - unsigned int num=0; - fseek(fp, 0, SEEK_END); // seek to end of file - num = ftell(fp); // get current file pointer - *n=num;// number of bytes from the beginning of the file - num=(num/BYTE_NUM)+2; - fseek(fp, 0, SEEK_SET); - //printf ("num=%u\n",num); - buffer = (unsigned *) malloc(num * sizeof(unsigned)); //memory allocated using malloc - if(buffer == NULL) - { - printf("Error! memory not allocated."); - exit(0); - } - ch=fgetc(fp); - while(!feof(fp)){ - val<<=8; - val|=ch; - cnt++; - //printf("ch=%x\t",ch); - if(cnt==BYTE_NUM){ - //printf("%d:%x\n",i,val); - buffer[i] = val; - val=0; - cnt=0; - i++; - } - ch=fgetc(fp); - } - if( cnt>0){ - val<<=(8 *(BYTE_NUM-cnt)); - printf("%d:%x\n",i,val); - buffer[i] = val; - - } - -return buffer; - -} - - - -int send_data () -{ - char * pch; - char string[100]; - int bit=0, inst=0, d=0; - char out[100]; - pch = strtok (write_data,","); - printf("%s\n",pch); - while (pch != NULL) - { - while(1){ - d=1; - if(sscanf( pch, "D:%d:%s", &bit, string )) break; - if(sscanf( pch, "d:%d:%s", &bit, string )) break; - //if(sscanf( pch, "D:%d:" PRIx64 , &bit, &data )) break; - //if(sscanf( pch, "d:%d:%016x", &bit, &data )) break; - d=2; - if(sscanf( pch, "R:%d:%s",&bit, string)) break; - if(sscanf( pch, "r:%d:%s",&bit, string)) break; - d=0; - if(sscanf( pch, "I:%d", &inst)) break; - if(sscanf( pch, "i:%d", &inst)) break; - printf("invalid format : %s\n",pch); - return -1; - - } - if(d==1){ - //printf ("(bit=%d, data=%s)",bit, string); - //jtag_vdr(bit, data, 0); - vdr_large(bit,string,0); - }if(d==2){ - - vdr_large(bit,string,out); - printf("###read data#%s###read data#\n",out); - }else{ - - jtag_vir(inst); - //printf("%d\n",inst); - } - - pch = strtok (NULL, ","); - - } - return 0; -} - - - -int send_binary_file(){ - FILE *fp; - int i=0; - unsigned out; - unsigned int num=0; - unsigned int mem_size; - unsigned int memory_offset_in_word; - printf("send %s to the wishbone bus\n",binary_file_name); - fp = fopen(binary_file_name,"rb"); - if (!fp) { - fprintf (stderr,"Error: can not open %s file in read mode\n",binary_file_name); - return -1; - } - unsigned * buffer; - buffer=read_file (fp, &num); - mem_size=memory_boundary-memory_offset; - if(num>mem_size){ - printf("\n\n Warning: %s file size (%x) is larger than the given memory size (%x). I will stop writing on end of memory address\n\n",binary_file_name,num,mem_size); - num=mem_size; - } - fclose(fp); - //disable the cpu - jtag_vir(RD_WR_STATUS); - jtag_vdr(BIT_NUM, 0x1, &out); - //getchar(); - jtag_vir(UPDATE_WB_ADDR); - // change memory sizes from byte to word - memory_offset_in_word=memory_offset /BYTE_NUM; - num=num /BYTE_NUM; - - jtag_vdr(BIT_NUM, memory_offset_in_word, 0); - jtag_vir(UPDATE_WB_WR_DATA); - - printf ("start programing\n"); - //printf ("num=%d\n",num); - for(i=0;isize)? 0 : size-count*8; - - sscanf(hexstring+start, "%08x", &val[count-1]); - *(hexstring+start)=0; - } - - // printf("size=%d, hexnum=%u\n",size,hexnum); - - - return hexnum; -} - - -void hexgen( char * hexstring, unsigned * val, int words ){ - size_t count = 0; - sprintf(hexstring,"0x"); - for(count = 0; count < words; count++) { - if(count == 0) sprintf((hexstring+2),"%x",val[words-count-1]); - else sprintf(hexstring,"%08x",val[words-count-1]); - hexstring+=strlen(hexstring); - } - - // return hexnum; -} - -
mpsoc/src_c/jtag/jtag_main.c Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: mpsoc/src_c/jtag/jconsole.c =================================================================== --- mpsoc/src_c/jtag/jconsole.c (revision 27) +++ mpsoc/src_c/jtag/jconsole.c (nonexistent) @@ -1,135 +0,0 @@ -#include -#include -#include -#include -#include - - -#include -#include "jtag.h" - -#define VIR_CTRL 0x0 -#define VIR_ADDR 0x1 -#define VIR_DATA 0x2 -#define VIR_UART 0x7 - - -#define UPDATE_WB_ADDR 0x7 -#define UPDATE_WB_WR_DATA 0x6 -#define UPDATE_WB_RD_DATA 0x5 -#define RD_WR_STATUS 0x4 - -int main(int argc, char **argv) { - //unsigned bits; - //unsigned int val; - - //unsigned bits; - uint32_t val; - FILE *fp; - - if (argc != 2) { - fprintf(stderr,"usage: download bin file\n"); - return -1; - } - fp = fopen(argv[1],"rb"); - if (!fp) return -1; - - if (jtag_open_virtual_device(126)) - return -1; - - - int i=0; - unsigned int out; -//disable the cpu - jtag_vir(RD_WR_STATUS); - jtag_vdr(32, 0xFFFFFFFF, &out); - printf ("status=%x\n",out); - getchar(); -// - jtag_vir(UPDATE_WB_WR_DATA); - unsigned char ch; - char cnt=0; - val=0; - ch=fgetc(fp); - while(!feof(fp)){ - val<<=8; - val|=ch; - cnt++; - printf("ch=%x\t",ch); - if(cnt==4){ - printf("%d:%x\n",i,val); - jtag_vdr(32, val, 0); - val=0; - cnt=0; - i++; - } - ch=fgetc(fp); - } - if( cnt>0){ - val<<=(8 *(4-cnt)); - printf("%d:%x\n",i,val); - jtag_vdr(32, val, 0); - - } - - - getchar(); -/* - printf ("start=\n"); - jtag_vir(UPDATE_WB_ADDR); - jtag_vdr(32, 0, 0); - jtag_vir(UPDATE_WB_WR_DATA); - - for(i=0;i<1000; i++){ - //printf ("addr=\n"); - //scanf("%x", &val); - - jtag_vdr(32, 2*i, 0); - //jtag_vdr(32, 0, &out); - //printf ("out=%x\n",out); - - printf ("data=\n"); - scanf("%x", &val); - jtag_vir(UPDATE_WB_WR_DATA); - jtag_vdr(32, val, 0); - - printf ("data=\n"); - scanf("%x", &val); - jtag_vdr(32, val, 0); - - printf ("data=\n"); - scanf("%x", &val); - jtag_vdr(32, val, 0); - - - } -*/ - printf ("done programing\n"); - jtag_vir(UPDATE_WB_RD_DATA); - jtag_vdr(32, 0, &out); - for(i=1;i<1001; i++){ - jtag_vdr(32, i, &out); - printf ("out[%d]=%x\n",i-1,out); - - - } - - jtag_vir(RD_WR_STATUS); - jtag_vdr(32, 0, &out); - printf ("status=%x\n",out); - for (;;) { - /* - jtag_vdr(9, 0, &bits); - if (bits & 0x100) { - bits &= 0xFF; - if ((bits < ' ') || (bits > 127)) - fputc('.', stderr); - else - fputc(bits, stderr); - } - */ - } - - return 0; -} -
mpsoc/src_c/jtag/jconsole.c Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: mpsoc/src_c/jtag/jtag.c =================================================================== --- mpsoc/src_c/jtag/jtag.c (revision 27) +++ mpsoc/src_c/jtag/jtag.c (nonexistent) @@ -1,321 +0,0 @@ -/* Copyright 2012 Brian Swetland - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#include - -#include - -#define TRACE_USB 0 -#define TRACE_JTAG 0 - -static struct libusb_device_handle *udev; -static int usb_open(unsigned vid, unsigned pid) { - if (libusb_init(NULL) < 0) - return -1; - - if (!(udev = libusb_open_device_with_vid_pid(NULL, vid, pid))) { - fprintf(stderr,"cannot find device\n"); - return -1; - } - - if (libusb_claim_interface(udev, 0) < 0) { - fprintf(stderr,"cannot claim interface\n"); - return -1; - } - return 0; -} -static void usb_close(void) { - libusb_exit(NULL); -} -#if TRACE_USB -static void dump(char *prefix, void *data, int len) { - unsigned char *x = data; - fprintf(stderr,"%s: (%d)", prefix, len); - while (len > 0) { - fprintf(stderr," %02x", *x++); - len--; - } - fprintf(stderr,"\n"); -} -#endif -static int usb_bulk(unsigned char ep, void *data, int len, unsigned timeout) { - int r, xfer; -#if TRACE_USB - if (!(ep & 0x80)) - dump("xmit", data, len); -#endif - r = libusb_bulk_transfer(udev, ep, data, len, &xfer, timeout); - if (r < 0) { - fprintf(stderr,"bulk: error: %d\n", r); - return r; - } -#if TRACE_USB - if (ep & 0x80) - dump("recv", data, xfer); -#endif - return xfer; -} - -#define EP1_IN 0x81 -#define EP2_OUT 0x02 - -#define UB_BYTEMODE 0x80 -#define UB_BITMODE 0x00 -#define UB_READBACK 0x40 - -/* bits in bit mode */ -#define UB_OE 0x20 -#define UB_TDI 0x10 -#define UB_nCS 0x08 -#define UB_nCE 0x04 -#define UB_TMS 0x02 -#define UB_TCK 0x01 -#define BUFF_SZ 512 -/* bytecount for data bytes that follow in byte mode */ -#define UB_COUNT(n) ((n) & 0x3F) - -int jtag_move(int count, unsigned bits){ - unsigned char buf[BUFF_SZ]; - int n = 0; -#if TRACE_JTAG - fprintf(stderr,"move: %08x (%d)\n", bits, count); -#endif - while (count-- > 0) { - if (bits & 1) { - buf[n++] = UB_TMS; - buf[n++] = UB_TMS | UB_TCK; - } else { - buf[n++] = 0; - buf[n++] = UB_TCK; - } - bits >>= 1; - } - return usb_bulk(EP2_OUT, buf, n, 1000); -} - -int jtag_shift(int count, unsigned bits, unsigned *out) { - unsigned char buf[BUFF_SZ]; - unsigned RB = out ? UB_READBACK : 0; - int n = 0; - int readcount = count; - int r,bit; -#if TRACE_JTAG - fprintf(stderr,"xfer: %08x (%d)\n", bits, count); -#endif - while (count-- > 0) { - if (bits & 1) { - buf[n++] = UB_TDI; - buf[n++] = UB_TDI | UB_TCK | RB; - } else { - buf[n++] = 0; - buf[n++] = UB_TCK | RB; - } - bits >>= 1; - } - buf[n-1] |= UB_TMS; - buf[n-2] |= UB_TMS; - r = usb_bulk(EP2_OUT, buf, n, 1000); - if (r < 0) - return r; - if (!out) - return 0; - bits = 0; - bit = 1; - while (readcount > 0) { - r = usb_bulk(EP1_IN, buf, BUFF_SZ, 1000); - if (r < 0) - return r; - if (r < 3) - continue; - for (n = 2; n < r; n++) { - if (buf[n] & 1) - bits |= bit; - bit <<= 1; - readcount--; - if (readcount == 0) { -#if TRACE_JTAG - fprintf(stderr," : %08x\n", bits); -#endif - *out = bits; - return 0; - } - } - } - return -1; -} - - -int jtag_shift_long(int count, unsigned * bits, unsigned *out) { - unsigned char buf[BUFF_SZ]; - unsigned RB = out ? UB_READBACK : 0; - int n = 0; - int readcount = count; - int r,bit; - unsigned int p=0; - -#if TRACE_JTAG - fprintf(stderr,"xfer: %08x (%d)\n", bits[count>>5], count); -#endif - while (count-- > 0) { - p=((readcount-count)-1)>>5; - if (bits[p] & 1) { - buf[n++] = UB_TDI; - buf[n++] = UB_TDI | UB_TCK | RB; - } else { - buf[n++] = 0; - buf[n++] = UB_TCK | RB; - } - bits[p] = bits[p] >> 1; - } - buf[n-1] |= UB_TMS; - buf[n-2] |= UB_TMS; - r = usb_bulk(EP2_OUT, buf, n, 1000); - if (r < 0) - return r; - if (!out) - return 0; - - unsigned B = 0; - bit = 1; - - count=readcount; - int shift=0; - while (readcount > 0) { - - r = usb_bulk(EP1_IN, buf, BUFF_SZ, 1000); - //int j; - //for(j=0;j>5; - //printf("%u",buf[n]&1); - if (buf[n] & 1) - B |= bit; - bit <<= 1; - shift++; - if(shift%32==0){ - bit=1; - out[p]= B; - //printf("out[%u]=%x\n",p, out[p]); - B=0; - - - } - readcount--; - if (readcount == 0) { -#if TRACE_JTAG - fprintf(stderr," : %08x\n", bits[p]); -#endif - out[p]= B; - //printf("out[%u]=%x\n",p, out[p]); - return 0; - } - } - } - return -1; -} - - - -/* JTAG notes - * - * TMS is sampled on +TCK - * Capture-XR state loads shift register on +TCK as state is exited - * Shift-XR state TDO goes active (containing shiftr[0]) on the first -TCK - * after entry, shifts occur on each +TCK, *including* the +TCK - * that will exist Shift-XR when TMS=1 again - * Update-XR update occurs on the -TCK after entry to state - * - * Any -> Reset: 11111 - * Any -> Reset -> RTI: 111110 - * RTI -> ShiftDR: 100 - * ShiftDR shifting: 0 x N - * ShiftDR -> UpdateDR -> RTI: 110 - * ShiftDR -> UpdateDR -> ShiftDR: 11100 - * RTI -> ShiftIR: 1100 - * ShiftIR shifting: 0 x N - * ShiftIR -> UpdateIR -> RTI: 110 - */ - -#define RESET 8,0b01111111 -#define SHIFTDR 3,0b001 -#define SHIFTIR 4,0b0011 -#define DONE 2,0b01 -#define AGAIN 4,0b0011 - -int jtag_ir(unsigned sz, unsigned bits) { - int r; - if ((r = jtag_move(SHIFTIR)) < 0) return r; - if ((r = jtag_shift(sz, bits, 0)) < 0) return r; - if ((r = jtag_move(DONE)) < 0) return r; - return 0; -} - -int jtag_dr(unsigned sz, unsigned bits, unsigned *out) { - int r; - if ((r = jtag_move(SHIFTDR)) < 0) return r; - if ((r = jtag_shift(sz, bits, out)) < 0) return r; - if ((r = jtag_move(DONE)) < 0) return r; - return 0; -} - -int jtag_dr_long(unsigned sz, unsigned * bits, unsigned *out, int words) { - int r; - //unsigned s=32; - if ((r = jtag_move(SHIFTDR)) < 0) return r; - //for(i=0;i
mpsoc/src_c/jtag/jtag.c Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: mpsoc/src_c/jtag/usb-blaster-protocol.txt =================================================================== --- mpsoc/src_c/jtag/usb-blaster-protocol.txt (revision 27) +++ mpsoc/src_c/jtag/usb-blaster-protocol.txt (nonexistent) @@ -1,60 +0,0 @@ -http://sf.net/apps/mediawiki/urjtag/index.php?title=Cable_Altera_USB-Blaster ----------------------------------------------------------------------------- - -Altera USB-Blaster ------------------- - -General -------- - _________ - | | - | AT93C46 | - |_________| - __|__________ _________ - | | | | - USB__| FTDI 245BM |__| EPM7064 |__JTAG (B_TDO,B_TDI,B_TMS,B_TCK) - |_____________| |_________| - __|__________ _|___________ - | | | | - | 6 MHz XTAL | | 24 MHz Osc. | - |_____________| |_____________| - - -Quoting from ixo.de (http://www.ixo.de/info/usb_jtag/) -usb_jtag/device/c51/usbjtag.c comments: - -usb_jtag firmware now happens to behave just like the combination of -FT245BM and Altera-programmed EPM7064 CPLD in Altera's USB-Blaster. -The CPLD knows two major modes: Bit banging mode and Byte shift mode. -It starts in Bit banging mode. While bytes are received from the host -on EP2OUT, each byte B of them is processed as follows: - -Bit banging mode ----------------- -1. Remember bit 6 (0x40) in B as the "Read bit". -2. If bit 7 (0x80) is set, switch to Byte shift mode for the coming X - bytes ( X := B & 0x3F ), and don't do anything else now. -3. Otherwise, set the JTAG signals as follows: - - TCK/DCLK high if bit 0 was set (0x01), otherwise low - - TMS/nCONFIG high if bit 1 was set (0x02), otherwise low - - nCE high if bit 2 was set (0x04), otherwise low - - nCS high if bit 3 was set (0x08), otherwise low - - TDI/ASDI/DATAO high if bit 4 was set (0x10), otherwise low - - Output Enable/LED active if bit 5 was set (0x20), otherwise low -4. If "Read bit" (0x40) was set, record the state of TDO(CONF_DONE) and - DATAOUT/(nSTATUS) pins and put is as a byte( (DATAOUT<<1)|TDO) in the - output FIFO _to_ the host. - -Byte shift mode ---------------- -1. Load shift register with byte from host -2. Do 8 times (i.e. for each bit of the byte; implemented in shift.a51) - - if nCS=1, set carry bit from TDO, else set carry bit from DATAOUT - (Active Serial mode) - - Rotate shift register through carry bit - - TDI := Carry bit - - Raise TCK, then lower TCK. -3. If "Read bit" was set when switching into byte shift mode, record the - shift register content and put it into the FIFO to the host. - -
mpsoc/src_c/jtag/usb-blaster-protocol.txt Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: mpsoc/src_c/jtag/Makefile =================================================================== --- mpsoc/src_c/jtag/Makefile (revision 27) +++ mpsoc/src_c/jtag/Makefile (revision 28) @@ -1,23 +1,3 @@ - -CFLAGS := -g -Wall -LIBS := -lusb-1.0 - -all: jinfo jtag_main - -jinfo.c: jtag.h -jtag_main.c: jtag.h -jtag.c: jtag.h -jtag-virtual.c: jtag.h - - - -JINFO_OBJS := jinfo.o jtag-virtual.o jtag.o -jinfo: $(JINFO_OBJS) - $(CC) -o jinfo $(JINFO_OBJS) $(LIBS) - -JTAG_MAIN_OBJS := jtag_main.o jtag-virtual.o jtag.o -jtag_main: $(JTAG_MAIN_OBJS) - $(CC) -o jtag_main $(JTAG_MAIN_OBJS) $(LIBS) - -clean:: - rm -f jinfo jtag_main *.o +all: + cd simple_jtag; make + #cd urjtag-0.10; ./configure; wait; make Index: mpsoc/src_c/jtag/simple_jtag/Makefile =================================================================== --- mpsoc/src_c/jtag/simple_jtag/Makefile (nonexistent) +++ mpsoc/src_c/jtag/simple_jtag/Makefile (revision 28) @@ -0,0 +1,29 @@ + +CFLAGS := -g -Wall +LIBS := -lusb-1.0 + +all: jinfo jtag_main usblist + + +jinfo.c: jtag.h +jtag_main.c: jtag.h +jtag.c: jtag.h +jtag-virtual.c: jtag.h +list_usb_dev.c: jtag.h + + + +JINFO_OBJS := jinfo.o jtag-virtual.o jtag.o +jinfo: $(JINFO_OBJS) + $(CC) -o jinfo $(JINFO_OBJS) $(LIBS) + +JTAG_MAIN_OBJS := jtag_main.o jtag-virtual.o jtag.o +jtag_main: $(JTAG_MAIN_OBJS) + $(CC) -o jtag_main $(JTAG_MAIN_OBJS) $(LIBS) + +LIST_USB_OBJS := list_usb_dev.o jtag-virtual.o jtag.o +usblist: $(LIST_USB_OBJS) + $(CC) -o list_usb_dev $(LIST_USB_OBJS) $(LIBS) + +clean:: + rm -f jinfo jtag_main list_usb_dev *.o
mpsoc/src_c/jtag/simple_jtag/Makefile Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: mpsoc/src_c/jtag/simple_jtag/README =================================================================== --- mpsoc/src_c/jtag/simple_jtag/README (nonexistent) +++ mpsoc/src_c/jtag/simple_jtag/README (revision 28) @@ -0,0 +1,20 @@ + +Quick hack commandline tools to interact with Altera FPGA Virtual JTAG interfaces, +using the USB Blaster device (as integrated on Terasic dev boards, etc). + +Not terribly fancy or optimized but only depends on libusb-1.0 + +Currently does not support multiple devices on the chain. + +jtag.c - provides simple jtag interface +jtag-virtual.c - provides simple virtual jtag interface + +jload.c - example of using the virtual jtag interface for a downloader interface + with a CTRL/ADDR/DATA register set. CTRL[0] asserts reset, writes to + DATA store to [ADDR] and auto-increment ADRR. + +jinfo.c - dumps idcode and virtual jtag hub and device info table + + +Why? Scripting the Altera quartus_stp tool in TCL was driving me nuts. +
mpsoc/src_c/jtag/simple_jtag/README Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: mpsoc/src_c/jtag/simple_jtag/jconsole.c =================================================================== --- mpsoc/src_c/jtag/simple_jtag/jconsole.c (nonexistent) +++ mpsoc/src_c/jtag/simple_jtag/jconsole.c (revision 28) @@ -0,0 +1,135 @@ +#include +#include +#include +#include +#include + + +#include +#include "jtag.h" + +#define VIR_CTRL 0x0 +#define VIR_ADDR 0x1 +#define VIR_DATA 0x2 +#define VIR_UART 0x7 + + +#define UPDATE_WB_ADDR 0x7 +#define UPDATE_WB_WR_DATA 0x6 +#define UPDATE_WB_RD_DATA 0x5 +#define RD_WR_STATUS 0x4 + +int main(int argc, char **argv) { + //unsigned bits; + //unsigned int val; + + //unsigned bits; + uint32_t val; + FILE *fp; + + if (argc != 2) { + fprintf(stderr,"usage: download bin file\n"); + return -1; + } + fp = fopen(argv[1],"rb"); + if (!fp) return -1; + + if (jtag_open_virtual_device(126)) + return -1; + + + int i=0; + unsigned int out; +//disable the cpu + jtag_vir(RD_WR_STATUS); + jtag_vdr(32, 0xFFFFFFFF, &out); + printf ("status=%x\n",out); + getchar(); +// + jtag_vir(UPDATE_WB_WR_DATA); + unsigned char ch; + char cnt=0; + val=0; + ch=fgetc(fp); + while(!feof(fp)){ + val<<=8; + val|=ch; + cnt++; + printf("ch=%x\t",ch); + if(cnt==4){ + printf("%d:%x\n",i,val); + jtag_vdr(32, val, 0); + val=0; + cnt=0; + i++; + } + ch=fgetc(fp); + } + if( cnt>0){ + val<<=(8 *(4-cnt)); + printf("%d:%x\n",i,val); + jtag_vdr(32, val, 0); + + } + + + getchar(); +/* + printf ("start=\n"); + jtag_vir(UPDATE_WB_ADDR); + jtag_vdr(32, 0, 0); + jtag_vir(UPDATE_WB_WR_DATA); + + for(i=0;i<1000; i++){ + //printf ("addr=\n"); + //scanf("%x", &val); + + jtag_vdr(32, 2*i, 0); + //jtag_vdr(32, 0, &out); + //printf ("out=%x\n",out); + + printf ("data=\n"); + scanf("%x", &val); + jtag_vir(UPDATE_WB_WR_DATA); + jtag_vdr(32, val, 0); + + printf ("data=\n"); + scanf("%x", &val); + jtag_vdr(32, val, 0); + + printf ("data=\n"); + scanf("%x", &val); + jtag_vdr(32, val, 0); + + + } +*/ + printf ("done programing\n"); + jtag_vir(UPDATE_WB_RD_DATA); + jtag_vdr(32, 0, &out); + for(i=1;i<1001; i++){ + jtag_vdr(32, i, &out); + printf ("out[%d]=%x\n",i-1,out); + + + } + + jtag_vir(RD_WR_STATUS); + jtag_vdr(32, 0, &out); + printf ("status=%x\n",out); + for (;;) { + /* + jtag_vdr(9, 0, &bits); + if (bits & 0x100) { + bits &= 0xFF; + if ((bits < ' ') || (bits > 127)) + fputc('.', stderr); + else + fputc(bits, stderr); + } + */ + } + + return 0; +} +
mpsoc/src_c/jtag/simple_jtag/jconsole.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: mpsoc/src_c/jtag/simple_jtag/jinfo.c =================================================================== --- mpsoc/src_c/jtag/simple_jtag/jinfo.c (nonexistent) +++ mpsoc/src_c/jtag/simple_jtag/jinfo.c (revision 28) @@ -0,0 +1,37 @@ +/* Copyright 2012 Brian Swetland + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include "jtag.h" + +int main(int argc, char **argv) { + unsigned bits; + + if (jtag_open() < 0) + return -1; + + if (jtag_reset() < 0) + return -1; + + if (jtag_dr(32, 0, &bits) < 0) + return -1; + fprintf(stderr,"IDCODE: %08x\n", bits); + + if (jtag_open_virtual_device(0xffffffff)) + return -1; + + jtag_close(); + return 0; +}
mpsoc/src_c/jtag/simple_jtag/jinfo.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: mpsoc/src_c/jtag/simple_jtag/jtag-virtual.c =================================================================== --- mpsoc/src_c/jtag/simple_jtag/jtag-virtual.c (nonexistent) +++ mpsoc/src_c/jtag/simple_jtag/jtag-virtual.c (revision 28) @@ -0,0 +1,141 @@ +/* Copyright 2012 Brian Swetland + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include + +#include "jtag.h" + +int jtag_dr_8x4(unsigned *out) { + unsigned bits = 0; + unsigned tmp; + int n, r; + + for (n = 0; n < 8; n++) { + if ((r = jtag_dr(4, 0, &tmp)) < 0) return r; + bits |= (tmp <<= (n * 4)); + } + *out = bits; + return 0; +} + +/* number of bits needed given a max value 1-255 */ +unsigned needbits(unsigned max) { + if (max > 127) return 8; + if (max > 63) return 7; + if (max > 31) return 6; + if (max > 15) return 5; + if (max > 7) return 4; + if (max > 3) return 3; + if (max > 1) return 2; + return 1; +} + +static unsigned ir_width = 10; + +static unsigned hub_version = 0; +static unsigned hub_nodecount = 0; +static unsigned hub_mfg = 0; + +static unsigned vir_width = 0; +static unsigned vir_width_addr = 0; +static unsigned vir_width_ir = 0; +static unsigned vir_addr = 0; + + +int jtag_vir(unsigned vir) { + int r; + if ((r = jtag_ir(ir_width, 14)) < 0) return r; + if ((r = jtag_dr(vir_width, vir_addr | vir, 0)) < 0) return r; + return 0; +} + +int jtag_vdr(unsigned sz, unsigned bits, unsigned *out) { + int r; + if ((r = jtag_ir(ir_width, 12)) < 0) return r; + if ((r = jtag_dr(sz, bits, out)) < 0) return r; + return 0; +} + +int jtag_vdr_long(unsigned sz, unsigned * bits, unsigned *out, int words) { + int r; + if ((r = jtag_ir(ir_width, 12)) < 0) return r; + if ((r = jtag_dr_long(sz, bits, out, words)) < 0) return r; + return 0; +} + +int jtag_open_virtual_device(unsigned iid) { + unsigned n, bits; + int r; + + if ((r = jtag_open()) < 0) return r; + + if ((r = jtag_reset()) < 0) return r; + + /* select empty node_addr + node_vir -- all zeros */ + if ((r = jtag_ir(ir_width, 14)) < 0) return r; + if ((r = jtag_dr(32, 0, 0)) < 0) return r; + + /* select vdr - this will be the hub info (addr=0,vir=0) */ + if ((r = jtag_ir(ir_width, 12)) < 0) return r; + + /* read hub info */ + if ((r = jtag_dr_8x4(&bits)) < 0) return r; + hub_version = (bits >> 27) & 0x1F; + hub_nodecount = (bits >> 19) & 0xFF; + hub_mfg = (bits >> 8) & 0x7FF; + + if (hub_mfg != 0x06e) { + fprintf(stderr,"hub_version=%x, hub_nodecount=%x, hub_mfg=%x \n",hub_version, hub_nodecount, hub_mfg); + + fprintf(stderr,"HUB: Cannot Find Virtual JTAG HUB\n"); + return -1; + } + + /* altera docs claim this field is the sum of M bits (VIR field) and + * N bits (ADDR field), but empirical evidence suggests it is actually + * just the width of the ADDR field and the docs are wrong... + */ + vir_width_ir = bits & 0xFF; + vir_width_addr = needbits(hub_nodecount); + vir_width = vir_width_ir + vir_width_addr; + + fprintf(stderr,"HUB: Mfg=0x%03x, Ver=0x%02x, Nodes=%d, VIR=%d+%d bits\n", + hub_mfg, hub_version, hub_nodecount, vir_width_addr, vir_width_ir); + + for (n = 0; n < hub_nodecount; n++) { + unsigned node_ver, node_id, node_mfg, node_iid; + if ((r = jtag_dr_8x4(&bits)) < 0) return r; + node_ver = (bits >> 27) & 0x1F; + node_id = (bits >> 19) & 0xFF; + node_mfg = (bits >> 8) & 0x7FF; + node_iid = bits & 0xFF; + + fprintf(stderr,"NODE: Mfg=0x%03x, Ver=0x%02x, ID=0x%02x, IID=0x%02x\n", + node_mfg, node_ver, node_id, node_iid); + + if ((node_id == 0x08) && (node_iid) == iid) { + vir_addr = (n + 1) << vir_width_ir; + } + } + + if ((vir_addr == 0) && (iid < 256)) { + fprintf(stderr,"ERROR: IID 0x%02x not found\n", iid); + return -1; + } + return 0; +} + +
mpsoc/src_c/jtag/simple_jtag/jtag-virtual.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: mpsoc/src_c/jtag/simple_jtag/jtag.c =================================================================== --- mpsoc/src_c/jtag/simple_jtag/jtag.c (nonexistent) +++ mpsoc/src_c/jtag/simple_jtag/jtag.c (revision 28) @@ -0,0 +1,332 @@ +/* Copyright 2012 Brian Swetland + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include +#include +#include +#include + +#include + +#define TRACE_USB 0 +#define TRACE_JTAG 0 + +#define TIMOUT 1000 + +/* You may want to change the VENDOR_ID and PRODUCT_ID + * depending on your device. + */ +#define VENDOR_ID 0x09fb // Altera +#define PRODUCT_ID 0x6001 // usb blaster (DE2-115) +// Altera usb blaster product IDs "6001", "6002", "6003", MODE="0666" +// dose not work for USB-Blaster II "6010", "6810" +// run ./list_usb_dev to see the list of all usb devices' vid and pid + +static struct libusb_device_handle *udev; +static int usb_open(unsigned vid, unsigned pid) { + if (libusb_init(NULL) < 0) + return -1; + + if (!(udev = libusb_open_device_with_vid_pid(NULL, vid, pid))) { + fprintf(stderr,"cannot find device\n"); + return -1; + } + + if (libusb_claim_interface(udev, 0) < 0) { + fprintf(stderr,"cannot claim interface\n"); + return -1; + } + return 0; +} +static void usb_close(void) { + libusb_exit(NULL); +} +#if TRACE_USB +static void dump(char *prefix, void *data, int len) { + unsigned char *x = data; + fprintf(stderr,"%s: (%d)", prefix, len); + while (len > 0) { + fprintf(stderr," %02x", *x++); + len--; + } + fprintf(stderr,"\n"); +} +#endif +static int usb_bulk(unsigned char ep, void *data, int len, unsigned timeout) { + int r, xfer; +#if TRACE_USB + if (!(ep & 0x80)) + dump("xmit", data, len); +#endif + r = libusb_bulk_transfer(udev, ep, data, len, &xfer, timeout); + if (r < 0) { + fprintf(stderr,"bulk: error: %d\n", r); + return r; + } +#if TRACE_USB + if (ep & 0x80) + dump("recv", data, xfer); +#endif + return xfer; +} + +#define EP1_IN 0x81 +#define EP2_OUT 0x02 + +#define UB_BYTEMODE 0x80 +#define UB_BITMODE 0x00 +#define UB_READBACK 0x40 + +/* bits in bit mode */ +#define UB_OE 0x20 +#define UB_TDI 0x10 +#define UB_nCS 0x08 +#define UB_nCE 0x04 +#define UB_TMS 0x02 +#define UB_TCK 0x01 +#define BUFF_SZ 512 +/* bytecount for data bytes that follow in byte mode */ +#define UB_COUNT(n) ((n) & 0x3F) + +int jtag_move(int count, unsigned bits){ + unsigned char buf[BUFF_SZ]; + int n = 0; +#if TRACE_JTAG + fprintf(stderr,"move: %08x (%d)\n", bits, count); +#endif + while (count-- > 0) { + if (bits & 1) { + buf[n++] = UB_TMS; + buf[n++] = UB_TMS | UB_TCK; + } else { + buf[n++] = 0; + buf[n++] = UB_TCK; + } + bits >>= 1; + } + return usb_bulk(EP2_OUT, buf, n, TIMOUT); +} + +int jtag_shift(int count, unsigned bits, unsigned *out) { + unsigned char buf[BUFF_SZ]; + unsigned RB = out ? UB_READBACK : 0; + int n = 0; + int readcount = count; + int r,bit; +#if TRACE_JTAG + fprintf(stderr,"xfer: %08x (%d)\n", bits, count); +#endif + while (count-- > 0) { + if (bits & 1) { + buf[n++] = UB_TDI; + buf[n++] = UB_TDI | UB_TCK | RB; + } else { + buf[n++] = 0; + buf[n++] = UB_TCK | RB; + } + bits >>= 1; + } + buf[n-1] |= UB_TMS; + buf[n-2] |= UB_TMS; + r = usb_bulk(EP2_OUT, buf, n, TIMOUT); + if (r < 0) + return r; + if (!out) + return 0; + bits = 0; + bit = 1; + while (readcount > 0) { + r = usb_bulk(EP1_IN, buf, BUFF_SZ, TIMOUT); + if (r < 0) + return r; + if (r < 3) + continue; + for (n = 2; n < r; n++) { + if (buf[n] & 1) + bits |= bit; + bit <<= 1; + readcount--; + if (readcount == 0) { +#if TRACE_JTAG + fprintf(stderr," : %08x\n", bits); +#endif + *out = bits; + return 0; + } + } + } + return -1; +} + + +int jtag_shift_long(int count, unsigned * bits, unsigned *out) { + unsigned char buf[BUFF_SZ]; + unsigned RB = out ? UB_READBACK : 0; + int n = 0; + int readcount = count; + int r,bit; + unsigned int p=0; + +#if TRACE_JTAG + fprintf(stderr,"xfer: %08x (%d)\n", bits[count>>5], count); +#endif + while (count-- > 0) { + p=((readcount-count)-1)>>5; + if (bits[p] & 1) { + buf[n++] = UB_TDI; + buf[n++] = UB_TDI | UB_TCK | RB; + } else { + buf[n++] = 0; + buf[n++] = UB_TCK | RB; + } + bits[p] = bits[p] >> 1; + } + buf[n-1] |= UB_TMS; + buf[n-2] |= UB_TMS; + r = usb_bulk(EP2_OUT, buf, n, TIMOUT); + if (r < 0) + return r; + if (!out) + return 0; + + unsigned B = 0; + bit = 1; + + count=readcount; + int shift=0; + while (readcount > 0) { + + r = usb_bulk(EP1_IN, buf, BUFF_SZ, TIMOUT); + //int j; + //for(j=0;j>5; + //printf("%u",buf[n]&1); + if (buf[n] & 1) + B |= bit; + bit <<= 1; + shift++; + if(shift%32==0){ + bit=1; + out[p]= B; + //printf("out[%u]=%x\n",p, out[p]); + B=0; + + + } + readcount--; + if (readcount == 0 ) { +#if TRACE_JTAG + fprintf(stderr," : %08x\n", bits[p]); +#endif + if (shift%32!=0) out[p]= B; + //printf("out[%u]=%x\n",p, out[p]); + return 0; + } + } + } + return -1; +} + + + +/* JTAG notes + * + * TMS is sampled on +TCK + * Capture-XR state loads shift register on +TCK as state is exited + * Shift-XR state TDO goes active (containing shiftr[0]) on the first -TCK + * after entry, shifts occur on each +TCK, *including* the +TCK + * that will exist Shift-XR when TMS=1 again + * Update-XR update occurs on the -TCK after entry to state + * + * Any -> Reset: 11111 + * Any -> Reset -> RTI: 111110 + * RTI -> ShiftDR: 100 + * ShiftDR shifting: 0 x N + * ShiftDR -> UpdateDR -> RTI: 110 + * ShiftDR -> UpdateDR -> ShiftDR: 11100 + * RTI -> ShiftIR: 1100 + * ShiftIR shifting: 0 x N + * ShiftIR -> UpdateIR -> RTI: 110 + */ + +#define RESET 8,0b01111111 +#define SHIFTDR 3,0b001 +#define SHIFTIR 4,0b0011 +#define DONE 2,0b01 +#define AGAIN 4,0b0011 + +int jtag_ir(unsigned sz, unsigned bits) { + int r; + if ((r = jtag_move(SHIFTIR)) < 0) return r; + if ((r = jtag_shift(sz, bits, 0)) < 0) return r; + if ((r = jtag_move(DONE)) < 0) return r; + return 0; +} + +int jtag_dr(unsigned sz, unsigned bits, unsigned *out) { + int r; + if ((r = jtag_move(SHIFTDR)) < 0) return r; + if ((r = jtag_shift(sz, bits, out)) < 0) return r; + if ((r = jtag_move(DONE)) < 0) return r; + return 0; +} + +int jtag_dr_long(unsigned sz, unsigned * bits, unsigned *out, int words) { + int r; + //unsigned s=32; + if ((r = jtag_move(SHIFTDR)) < 0) return r; + //for(i=0;i
mpsoc/src_c/jtag/simple_jtag/jtag.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: mpsoc/src_c/jtag/simple_jtag/jtag.h =================================================================== --- mpsoc/src_c/jtag/simple_jtag/jtag.h (nonexistent) +++ mpsoc/src_c/jtag/simple_jtag/jtag.h (revision 28) @@ -0,0 +1,50 @@ +/* Copyright 2012 Brian Swetland + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _JTAG_H_ +#define _JTAG_H_ + +int jtag_open(void); +int jtag_close(void); + +/* move into RESET state */ +int jtag_reset(void); + +/* clock count times, TDI=0, TMS=bits[0], bits >>= 1 */ +int jtag_move(int count, unsigned bits); + +/* clock count-1 times, TMS=0, TDI=bits[0], bits >>= 1 + * clock 1 time, TMS=1, TDI=bits[0] + * if out, capture TDO into out + */ +int jtag_shift(int count, unsigned bits, unsigned *out); + + +/* load sz bits into IR */ +int jtag_ir(unsigned sz, unsigned bits); + +/* load sz bits into DR, capture sz bits into out if non-null */ +int jtag_dr(unsigned sz, unsigned bits, unsigned *out); +int jtag_dr_long(unsigned sz, unsigned * bits, unsigned *out, int words); + + + +/* altera virtual jtag support */ +int jtag_open_virtual_device(unsigned iid); +int jtag_vir(unsigned vir); +int jtag_vdr(unsigned sz, unsigned bits, unsigned *out); +int jtag_vdr_long(unsigned , unsigned * , unsigned *, int ); + +#endif
mpsoc/src_c/jtag/simple_jtag/jtag.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: mpsoc/src_c/jtag/simple_jtag/jtag_main.c =================================================================== --- mpsoc/src_c/jtag/simple_jtag/jtag_main.c (nonexistent) +++ mpsoc/src_c/jtag/simple_jtag/jtag_main.c (revision 28) @@ -0,0 +1,438 @@ +#include +#include +#include +#include +#include // getopt +#include +#include +#include "jtag.h" + + + + +#define UPDATE_WB_ADDR 0x7 +#define UPDATE_WB_WR_DATA 0x6 +#define UPDATE_WB_RD_DATA 0x5 +#define RD_WR_STATUS 0x4 + +#define BIT_NUM (word_width<<3) +#define BYTE_NUM word_width +/* Global vars */ +unsigned int index_num=126; +unsigned int word_width=4; // +unsigned int write_verify=0; +unsigned int memory_offset=0; +unsigned int memory_boundary=0xFFFFFFFF; + + + +char * binary_file_name=0; +char enable_binary_send=0; +char * write_data=0; + + + + +/* functions */ +int send_binary_file(); +void usage(); +void processArgs (int , char** ); +int send_data (); +int hexcut( char * , unsigned * , int ); +int vdr_large (unsigned , char * , char *); +void hexgen( char * , unsigned *, int ); + +int main(int argc, char **argv) { + //unsigned bits; + //unsigned int val; + + //unsigned bits; + //unsigned val; + + processArgs (argc, argv ); + printf("index num=%u\n",index_num); + if (jtag_open_virtual_device(index_num)){ + fprintf (stderr, "Error openning jtag IP with %d index num\n",index_num); + return -1; + } + if (enable_binary_send) { + if( send_binary_file() == -1) return -1; + } + + if (write_data!=0){ + printf("send %s to jtag\n",write_data); + send_data(); + + + } + + return 0; +} + + + +void usage(){ + + printf ("usage:./jtag_main [-n index number] [-i file_name][-c][-s rd/wr offset address][-d string]\n"); + + printf ("\t-n index number: the target jtag IP core index number. The default number is 126\n"); + printf ("\t-i file_name: input binary file name (.bin file)\n"); + printf ("\t-w bin file word width in byte. default is 4 bytes (32 bits)\n"); + printf ("\t-c verify after write\n"); + printf ("\t-s memory wr/rd offset address in hex. The default value is 0x0000000\n"); + printf ("\t-e memory boundary address in hex. The default value is 0xFFFFFFFF\n"); + printf ("\t-d string: use for setting instruction or data value to jtag tap. string format : \"instr1,instr2,...,instrn\"\n \tinstri = I:instruct_num: send instruct_num to instruction register \n \tD:data_size_in_bit:data : send data in hex to data register\n \tR:data_size_in_bit:data : Read data register and show it on screan then write given data in hex to data register\n"); + +} + +void processArgs (int argc, char **argv ) +{ + char c; +int p; + + /* don't want getopt to moan - I can do that just fine thanks! */ + opterr = 0; + if (argc < 2) usage(); + while ((c = getopt (argc, argv, "s:e:d:n:i:w:c")) != -1) + { + switch (c) + { + case 'n': /* index number */ + index_num = atoi(optarg); + break; + case 'i': /* input binary file name */ + binary_file_name = optarg; + enable_binary_send=1; + break; + case 'w': /* word width in byte */ + word_width= atoi(optarg); + break; + case 'c': /* word width in byte */ + write_verify= 1; + break; + case 'd': /* word width in byte */ + write_data= optarg; + break; + case 's': /* word width in byte */ + + p=sscanf(optarg,"%x",&memory_offset); + if( p==0){ + fprintf (stderr, "invalid memory offset adress format `%s'.\n", optarg); + usage(); + exit(1); + } + //printf("p=%d,memory_offset=%x\n",p,memory_offset); + break; + case 'e': /* word width in byte */ + p=sscanf(optarg,"%x",&memory_boundary); + if( p==0){ + fprintf (stderr, "invalid memory boundary adress format `%s'.\n", optarg); + usage(); + exit(1); + } + break; + + case '?': + if (isprint (optopt)) + fprintf (stderr, "Unknown option `-%c'.\n", optopt); + else + fprintf (stderr, + "Unknown option character `\\x%x'.\n", + optopt); + default: + usage(); + exit(1); + } + } +} + +unsigned * read_file (FILE * fp, unsigned int * n ){ + + unsigned * buffer; + unsigned val; + unsigned char ch; + unsigned int i=0; + char cnt=0; + unsigned int num=0; + unsigned int width= (BYTE_NUM < sizeof(unsigned )) ? BYTE_NUM : sizeof(unsigned ); //max is 4 then + fseek(fp, 0, SEEK_END); // seek to end of file + num = ftell(fp); // get current file pointer + *n=num;// number of bytes from the beginning of the file + + + + + num=(num/width)+2; + fseek(fp, 0, SEEK_SET); + //printf ("num=%u\n",num); + buffer = (unsigned *) malloc(num * sizeof(unsigned ) ); //memory allocated using malloc + if(buffer == NULL) + { + printf("Error! memory not allocated."); + exit(0); + } + ch=fgetc(fp); + + while(!feof(fp)){ + val<<=8; + val|=ch; + cnt++; + //printf("ch=%x\t",ch); + if(cnt==width){ + //printf("%d:%x\n",i,val); + buffer[i] = val; + val=0; + cnt=0; + i++; + } + ch=fgetc(fp); + } + if( cnt>0){ + val<<=(8 *(width-cnt)); + printf("%d:%x\n",i,val); + buffer[i] = val; + + } + +return buffer; + +} + + + +int send_data () +{ + char * pch; + char string[100]; + int bit=0, inst=0, d=0; + char out[100]; + pch = strtok (write_data,","); + printf("%s\n",pch); + while (pch != NULL) + { + while(1){ + d=1; + if(sscanf( pch, "D:%d:%s", &bit, string )) break; + if(sscanf( pch, "d:%d:%s", &bit, string )) break; + //if(sscanf( pch, "D:%d:" PRIx64 , &bit, &data )) break; + //if(sscanf( pch, "d:%d:%016x", &bit, &data )) break; + d=2; + if(sscanf( pch, "R:%d:%s",&bit, string)) break; + if(sscanf( pch, "r:%d:%s",&bit, string)) break; + d=0; + if(sscanf( pch, "I:%d", &inst)) break; + if(sscanf( pch, "i:%d", &inst)) break; + printf("invalid format : %s\n",pch); + return -1; + + } + if(d==1){ + //printf ("(bit=%d, data=%s)",bit, string); + //jtag_vdr(bit, data, 0); + vdr_large(bit,string,0); + }if(d==2){ + + vdr_large(bit,string,out); + printf("###read data#%s###read data#\n",out); + }else{ + + jtag_vir(inst); + //printf("%d\n",inst); + } + + pch = strtok (NULL, ","); + + } + return 0; +} + +int compare_values( unsigned * val1, unsigned * val2, int words, unsigned int address){ + + int i,error=0; + for(i=0;imem_size){ + printf("\n\n Warning: %s file size (%x) is larger than the given memory size (%x). I will stop writing on end of memory address\n\n",binary_file_name,file_size,mem_size); + file_size=mem_size; + } + fclose(fp); + //disable the cpu + jtag_vir(RD_WR_STATUS); + jtag_vdr(BIT_NUM, 0x1, &out); + //getchar(); + jtag_vir(UPDATE_WB_ADDR); + // change memory sizes from byte to word + memory_offset_in_word=memory_offset /BYTE_NUM; + //size of buffer + num= (BYTE_NUM < sizeof(unsigned )) ? file_size /BYTE_NUM : file_size /sizeof(unsigned ); + + jtag_vdr(BIT_NUM, memory_offset_in_word, 0); + jtag_vir(UPDATE_WB_WR_DATA); + + printf ("start programing\n"); + //printf ("num=%d\n",num); + for(i=0;isize)? 0 : size-count*8; + + sscanf(hexstring+start, "%08x", &val[count-1]); + *(hexstring+start)=0; + } + + // printf("size=%d, hexnum=%u\n",size,hexnum); + + + return hexnum; +} + + +void hexgen( char * hexstring, unsigned * val, int words ){ + size_t count = 0; + sprintf(hexstring,"0x"); + for(count = 0; count < words; count++) { + if(count == 0) sprintf((hexstring+2),"%x",val[words-count-1]); + else sprintf(hexstring,"%08x",val[words-count-1]); + hexstring+=strlen(hexstring); + } + + // return hexnum; +} + +
mpsoc/src_c/jtag/simple_jtag/jtag_main.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: mpsoc/src_c/jtag/simple_jtag/list_usb_dev.c =================================================================== --- mpsoc/src_c/jtag/simple_jtag/list_usb_dev.c (nonexistent) +++ mpsoc/src_c/jtag/simple_jtag/list_usb_dev.c (revision 28) @@ -0,0 +1,59 @@ +#include +#include +#include +#include +#include +#include + + +int main(){ +// discover devices + +if (libusb_init(NULL) < 0) + return -1; + + + + + + + + + + +libusb_context *ctx=NULL; +//uint16_t vendor_id, +//uint16_t product_id + + struct libusb_device **devs; + //struct libusb_device *found = NULL; + struct libusb_device *dev; + //struct libusb_device_handle *handle = NULL; + size_t i = 0; + int r; + if (libusb_get_device_list(ctx, &devs) < 0) + return -1; + while ((dev = devs[i++]) != NULL) { + struct libusb_device_descriptor desc; + r = libusb_get_device_descriptor(dev, &desc); + if (r < 0) + goto out; + printf("vid=%x,\t pid=%x\n",desc.idVendor,desc.idProduct); + //if (desc.idVendor == vendor_id && desc.idProduct == product_id) { + // found = dev; + // break; + //} + } + //if (found) { + // r = libusb_open(found, &handle); + // if (r < 0) + // handle = NULL; + //} +out: + libusb_free_device_list(devs, 1); + //return handle; + +return 0; + +} +
mpsoc/src_c/jtag/simple_jtag/list_usb_dev.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: mpsoc/src_c/jtag/simple_jtag/usb-blaster-protocol.txt =================================================================== --- mpsoc/src_c/jtag/simple_jtag/usb-blaster-protocol.txt (nonexistent) +++ mpsoc/src_c/jtag/simple_jtag/usb-blaster-protocol.txt (revision 28) @@ -0,0 +1,60 @@ +http://sf.net/apps/mediawiki/urjtag/index.php?title=Cable_Altera_USB-Blaster +---------------------------------------------------------------------------- + +Altera USB-Blaster +------------------ + +General +------- + _________ + | | + | AT93C46 | + |_________| + __|__________ _________ + | | | | + USB__| FTDI 245BM |__| EPM7064 |__JTAG (B_TDO,B_TDI,B_TMS,B_TCK) + |_____________| |_________| + __|__________ _|___________ + | | | | + | 6 MHz XTAL | | 24 MHz Osc. | + |_____________| |_____________| + + +Quoting from ixo.de (http://www.ixo.de/info/usb_jtag/) +usb_jtag/device/c51/usbjtag.c comments: + +usb_jtag firmware now happens to behave just like the combination of +FT245BM and Altera-programmed EPM7064 CPLD in Altera's USB-Blaster. +The CPLD knows two major modes: Bit banging mode and Byte shift mode. +It starts in Bit banging mode. While bytes are received from the host +on EP2OUT, each byte B of them is processed as follows: + +Bit banging mode +---------------- +1. Remember bit 6 (0x40) in B as the "Read bit". +2. If bit 7 (0x80) is set, switch to Byte shift mode for the coming X + bytes ( X := B & 0x3F ), and don't do anything else now. +3. Otherwise, set the JTAG signals as follows: + - TCK/DCLK high if bit 0 was set (0x01), otherwise low + - TMS/nCONFIG high if bit 1 was set (0x02), otherwise low + - nCE high if bit 2 was set (0x04), otherwise low + - nCS high if bit 3 was set (0x08), otherwise low + - TDI/ASDI/DATAO high if bit 4 was set (0x10), otherwise low + - Output Enable/LED active if bit 5 was set (0x20), otherwise low +4. If "Read bit" (0x40) was set, record the state of TDO(CONF_DONE) and + DATAOUT/(nSTATUS) pins and put is as a byte( (DATAOUT<<1)|TDO) in the + output FIFO _to_ the host. + +Byte shift mode +--------------- +1. Load shift register with byte from host +2. Do 8 times (i.e. for each bit of the byte; implemented in shift.a51) + - if nCS=1, set carry bit from TDO, else set carry bit from DATAOUT + (Active Serial mode) + - Rotate shift register through carry bit + - TDI := Carry bit + - Raise TCK, then lower TCK. +3. If "Read bit" was set when switching into byte shift mode, record the + shift register content and put it into the FIFO to the host. + +
mpsoc/src_c/jtag/simple_jtag/usb-blaster-protocol.txt Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: mpsoc/src_emulate/fpga/DE4_230/DE4_230.qsf =================================================================== --- mpsoc/src_emulate/fpga/DE4_230/DE4_230.qsf (nonexistent) +++ mpsoc/src_emulate/fpga/DE4_230/DE4_230.qsf (revision 28) @@ -0,0 +1,2288 @@ +#============================================================ +# Build by Terasic System Builder V1.0.0 +#============================================================ + +set_global_assignment -name FAMILY "Stratix IV" +set_global_assignment -name DEVICE EP4SGX230KF40C2 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.1 +set_global_assignment -name LAST_QUARTUS_VERSION "11.1 SP1" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:41:29 NOVEMBER 25,2009" +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 1152 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 2 + +#============================================================ +# Pin Assign +#============================================================ +set_location_assignment PIN_AH5 -to BUTTON[0] +set_location_assignment PIN_AG5 -to BUTTON[1] +set_location_assignment PIN_AG7 -to BUTTON[2] +set_location_assignment PIN_AG8 -to BUTTON[3] +set_location_assignment PIN_V34 -to CPU_RESET_n +set_location_assignment PIN_AK13 -to CSENSE_ADC_F0 +set_location_assignment PIN_AG14 -to CSENSE_CS_n[0] +set_location_assignment PIN_AG15 -to CSENSE_CS_n[1] +set_location_assignment PIN_AH13 -to CSENSE_SCK +set_location_assignment PIN_AJ13 -to CSENSE_SDI +set_location_assignment PIN_AK14 -to CSENSE_SDO +set_location_assignment PIN_G33 -to EEP_SCL +set_location_assignment PIN_F33 -to EEP_SDA +set_location_assignment PIN_B20 -to ETH_INT_n[0] +set_location_assignment PIN_AG30 -to ETH_INT_n[1] +set_location_assignment PIN_AE30 -to ETH_INT_n[2] +set_location_assignment PIN_AE31 -to ETH_INT_n[3] +set_location_assignment PIN_R30 -to ETH_MDC[0] +set_location_assignment PIN_J6 -to ETH_MDC[1] +set_location_assignment PIN_K6 -to ETH_MDC[2] +set_location_assignment PIN_N7 -to ETH_MDC[3] +set_location_assignment PIN_W32 -to ETH_MDIO[0] +set_location_assignment PIN_J5 -to ETH_MDIO[1] +set_location_assignment PIN_K5 -to ETH_MDIO[2] +set_location_assignment PIN_N8 -to ETH_MDIO[3] +set_location_assignment PIN_V29 -to ETH_RST_n +set_location_assignment PIN_U31 -to ETH_RX_p[0] +set_location_assignment PIN_N33 -to ETH_RX_p[1] +set_location_assignment PIN_K34 -to ETH_RX_p[2] +set_location_assignment PIN_J34 -to ETH_RX_p[3] +set_location_assignment PIN_T30 -to ETH_TX_p[0] +set_location_assignment PIN_R32 -to ETH_TX_p[1] +set_location_assignment PIN_M32 -to ETH_TX_p[2] +set_location_assignment PIN_P31 -to ETH_TX_p[3] +set_location_assignment PIN_AC11 -to EXT_IO +set_location_assignment PIN_AP20 -to FAN_CTRL +set_location_assignment PIN_F21 -to FLASH_ADV_n +set_location_assignment PIN_F23 -to FLASH_CE_n +set_location_assignment PIN_E22 -to FLASH_CLK +set_location_assignment PIN_N21 -to FLASH_OE_n +set_location_assignment PIN_G21 -to FLASH_RYBY_n +set_location_assignment PIN_D21 -to FLASH_RESET_n +set_location_assignment PIN_R20 -to FLASH_WE_n +set_location_assignment PIN_G22 -to FSM_A[1] +set_location_assignment PIN_F34 -to FSM_A[10] +set_location_assignment PIN_G35 -to FSM_A[11] +set_location_assignment PIN_E34 -to FSM_A[12] +set_location_assignment PIN_J32 -to FSM_A[13] +set_location_assignment PIN_F35 -to FSM_A[14] +set_location_assignment PIN_C24 -to FSM_A[15] +set_location_assignment PIN_A24 -to FSM_A[16] +set_location_assignment PIN_D23 -to FSM_A[17] +set_location_assignment PIN_D24 -to FSM_A[18] +set_location_assignment PIN_T27 -to FSM_A[19] +set_location_assignment PIN_G23 -to FSM_A[2] +set_location_assignment PIN_T28 -to FSM_A[20] +set_location_assignment PIN_D22 -to FSM_A[21] +set_location_assignment PIN_E23 -to FSM_A[22] +set_location_assignment PIN_N20 -to FSM_A[23] +set_location_assignment PIN_P20 -to FSM_A[24] +set_location_assignment PIN_C22 -to FSM_A[25] +set_location_assignment PIN_A25 -to FSM_A[3] +set_location_assignment PIN_H22 -to FSM_A[4] +set_location_assignment PIN_H23 -to FSM_A[5] +set_location_assignment PIN_J22 -to FSM_A[6] +set_location_assignment PIN_K22 -to FSM_A[7] +set_location_assignment PIN_M21 -to FSM_A[8] +set_location_assignment PIN_J23 -to FSM_A[9] +set_location_assignment PIN_K29 -to FSM_D[0] +set_location_assignment PIN_J30 -to FSM_D[1] +set_location_assignment PIN_C35 -to FSM_D[10] +set_location_assignment PIN_D35 -to FSM_D[11] +set_location_assignment PIN_M22 -to FSM_D[12] +set_location_assignment PIN_M28 -to FSM_D[13] +set_location_assignment PIN_C31 -to FSM_D[14] +set_location_assignment PIN_D31 -to FSM_D[15] +set_location_assignment PIN_K30 -to FSM_D[2] +set_location_assignment PIN_L29 -to FSM_D[3] +set_location_assignment PIN_K31 -to FSM_D[4] +set_location_assignment PIN_E32 -to FSM_D[5] +set_location_assignment PIN_F32 -to FSM_D[6] +set_location_assignment PIN_H32 -to FSM_D[7] +set_location_assignment PIN_B32 -to FSM_D[8] +set_location_assignment PIN_C32 -to FSM_D[9] +set_location_assignment PIN_A21 -to GCLKIN +set_location_assignment PIN_AH19 -to GCLKOUT_FPGA +set_location_assignment PIN_AF6 -to GPIO0_D[0] +set_location_assignment PIN_AU9 -to GPIO0_D[1] +set_location_assignment PIN_AT5 -to GPIO0_D[10] +set_location_assignment PIN_AT8 -to GPIO0_D[11] +set_location_assignment PIN_AP5 -to GPIO0_D[12] +set_location_assignment PIN_AP7 -to GPIO0_D[13] +set_location_assignment PIN_AN5 -to GPIO0_D[14] +set_location_assignment PIN_AN10 -to GPIO0_D[15] +set_location_assignment PIN_AM5 -to GPIO0_D[16] +set_location_assignment PIN_AM10 -to GPIO0_D[17] +set_location_assignment PIN_AL10 -to GPIO0_D[18] +set_location_assignment PIN_AM8 -to GPIO0_D[19] +set_location_assignment PIN_AE5 -to GPIO0_D[2] +set_location_assignment PIN_AL8 -to GPIO0_D[20] +set_location_assignment PIN_AK8 -to GPIO0_D[21] +set_location_assignment PIN_AJ11 -to GPIO0_D[22] +set_location_assignment PIN_AK7 -to GPIO0_D[23] +set_location_assignment PIN_AJ5 -to GPIO0_D[24] +set_location_assignment PIN_AH12 -to GPIO0_D[25] +set_location_assignment PIN_AG10 -to GPIO0_D[26] +set_location_assignment PIN_AG13 -to GPIO0_D[27] +set_location_assignment PIN_AG9 -to GPIO0_D[28] +set_location_assignment PIN_AF11 -to GPIO0_D[29] +set_location_assignment PIN_AR8 -to GPIO0_D[3] +set_location_assignment PIN_AT9 -to GPIO0_D[30] +set_location_assignment PIN_AF10 -to GPIO0_D[31] +set_location_assignment PIN_AD10 -to GPIO0_D[32] +set_location_assignment PIN_AD9 -to GPIO0_D[33] +set_location_assignment PIN_AD12 -to GPIO0_D[34] +set_location_assignment PIN_AD13 -to GPIO0_D[35] +set_location_assignment PIN_AN9 -to GPIO0_D[4] +set_location_assignment PIN_AP9 -to GPIO0_D[5] +set_location_assignment PIN_AV5 -to GPIO0_D[6] +set_location_assignment PIN_AW6 -to GPIO0_D[7] +set_location_assignment PIN_AV7 -to GPIO0_D[8] +set_location_assignment PIN_AW7 -to GPIO0_D[9] +set_location_assignment PIN_AW5 -to GPIO1_D[0] +set_location_assignment PIN_AW8 -to GPIO1_D[1] +set_location_assignment PIN_AU6 -to GPIO1_D[10] +set_location_assignment PIN_AT6 -to GPIO1_D[11] +set_location_assignment PIN_AU7 -to GPIO1_D[12] +set_location_assignment PIN_AR5 -to GPIO1_D[13] +set_location_assignment PIN_AP6 -to GPIO1_D[14] +set_location_assignment PIN_AT7 -to GPIO1_D[15] +set_location_assignment PIN_AN7 -to GPIO1_D[16] +set_location_assignment PIN_AN6 -to GPIO1_D[17] +set_location_assignment PIN_AL6 -to GPIO1_D[18] +set_location_assignment PIN_AM6 -to GPIO1_D[19] +set_location_assignment PIN_AW4 -to GPIO1_D[2] +set_location_assignment PIN_AL5 -to GPIO1_D[20] +set_location_assignment PIN_AL9 -to GPIO1_D[21] +set_location_assignment PIN_AK9 -to GPIO1_D[22] +set_location_assignment PIN_AJ6 -to GPIO1_D[23] +set_location_assignment PIN_AJ10 -to GPIO1_D[24] +set_location_assignment PIN_AH11 -to GPIO1_D[25] +set_location_assignment PIN_AH8 -to GPIO1_D[26] +set_location_assignment PIN_AH9 -to GPIO1_D[27] +set_location_assignment PIN_AG12 -to GPIO1_D[28] +set_location_assignment PIN_AH10 -to GPIO1_D[29] +set_location_assignment PIN_AV10 -to GPIO1_D[3] +set_location_assignment PIN_AF13 -to GPIO1_D[30] +set_location_assignment PIN_AE13 -to GPIO1_D[31] +set_location_assignment PIN_AE10 -to GPIO1_D[32] +set_location_assignment PIN_AP10 -to GPIO1_D[33] +set_location_assignment PIN_AE12 -to GPIO1_D[34] +set_location_assignment PIN_AE11 -to GPIO1_D[35] +set_location_assignment PIN_AV8 -to GPIO1_D[4] +set_location_assignment PIN_AW10 -to GPIO1_D[5] +set_location_assignment PIN_AU10 -to GPIO1_D[6] +set_location_assignment PIN_AU8 -to GPIO1_D[7] +set_location_assignment PIN_AP8 -to GPIO1_D[8] +set_location_assignment PIN_AT10 -to GPIO1_D[9] +set_location_assignment PIN_AA35 -to HSMA_CLKIN_N1 +set_location_assignment PIN_AE35 -to HSMA_CLKIN_N2 +set_location_assignment PIN_AB34 -to HSMA_CLKIN_P1 +set_location_assignment PIN_AF34 -to HSMA_CLKIN_P2 +set_location_assignment PIN_AC34 -to HSMA_CLKIN0 +set_location_assignment PIN_AG35 -to HSMA_CLKOUT_n2 +set_location_assignment PIN_AG34 -to HSMA_CLKOUT_p2 +set_location_assignment PIN_AC26 -to HSMA_D[0] +set_location_assignment PIN_AC31 -to HSMA_D[1] +set_location_assignment PIN_AD26 -to HSMA_D[2] +set_location_assignment PIN_AC32 -to HSMA_D[3] +set_location_assignment PIN_N38 -to HSMA_GXB_RX_p[0] +set_location_assignment PIN_L38 -to HSMA_GXB_RX_p[1] +set_location_assignment PIN_E38 -to HSMA_GXB_RX_p[2] +set_location_assignment PIN_C38 -to HSMA_GXB_RX_p[3] +set_location_assignment PIN_M36 -to HSMA_GXB_TX_p[0] +set_location_assignment PIN_K36 -to HSMA_GXB_TX_p[1] +set_location_assignment PIN_D36 -to HSMA_GXB_TX_p[2] +set_location_assignment PIN_B36 -to HSMA_GXB_TX_p[3] +set_location_assignment PIN_AH28 -to HSMA_OUT_n1 +set_location_assignment PIN_AG28 -to HSMA_OUT_p1 +set_location_assignment PIN_AF29 -to HSMA_OUT0 +set_location_assignment PIN_J38 -to HSMA_REFCLK_p +set_location_assignment PIN_AK33 -to HSMA_RX_n[0] +set_location_assignment PIN_AH35 -to HSMA_RX_n[1] +set_location_assignment PIN_AU33 -to HSMA_RX_n[10] +set_location_assignment PIN_AV34 -to HSMA_RX_n[11] +set_location_assignment PIN_AU32 -to HSMA_RX_n[12] +set_location_assignment PIN_AU31 -to HSMA_RX_n[13] +set_location_assignment PIN_AR35 -to HSMA_RX_n[14] +set_location_assignment PIN_AP33 -to HSMA_RX_n[15] +set_location_assignment PIN_AR34 -to HSMA_RX_n[16] +set_location_assignment PIN_AJ35 -to HSMA_RX_n[2] +set_location_assignment PIN_AK35 -to HSMA_RX_n[3] +set_location_assignment PIN_AP30 -to HSMA_RX_n[4] +set_location_assignment PIN_AM35 -to HSMA_RX_n[5] +set_location_assignment PIN_AN31 -to HSMA_RX_n[6] +set_location_assignment PIN_AP34 -to HSMA_RX_n[7] +set_location_assignment PIN_AR32 -to HSMA_RX_n[8] +set_location_assignment PIN_AT30 -to HSMA_RX_n[9] +set_location_assignment PIN_AJ32 -to HSMA_RX_p[0] +set_location_assignment PIN_AH34 -to HSMA_RX_p[1] +set_location_assignment PIN_AT33 -to HSMA_RX_p[10] +set_location_assignment PIN_AU34 -to HSMA_RX_p[11] +set_location_assignment PIN_AT32 -to HSMA_RX_p[12] +set_location_assignment PIN_AT31 -to HSMA_RX_p[13] +set_location_assignment PIN_AP35 -to HSMA_RX_p[14] +set_location_assignment PIN_AN32 -to HSMA_RX_p[15] +set_location_assignment PIN_AT34 -to HSMA_RX_p[16] +set_location_assignment PIN_AJ34 -to HSMA_RX_p[2] +set_location_assignment PIN_AK34 -to HSMA_RX_p[3] +set_location_assignment PIN_AN30 -to HSMA_RX_p[4] +set_location_assignment PIN_AM34 -to HSMA_RX_p[5] +set_location_assignment PIN_AM31 -to HSMA_RX_p[6] +set_location_assignment PIN_AN33 -to HSMA_RX_p[7] +set_location_assignment PIN_AP32 -to HSMA_RX_p[8] +set_location_assignment PIN_AR31 -to HSMA_RX_p[9] +set_location_assignment PIN_AB28 -to HSMA_TX_n[0] +set_location_assignment PIN_AB31 -to HSMA_TX_n[1] +set_location_assignment PIN_AD31 -to HSMA_TX_n[10] +set_location_assignment PIN_AL32 -to HSMA_TX_n[11] +set_location_assignment PIN_AH27 -to HSMA_TX_n[12] +set_location_assignment PIN_AL31 -to HSMA_TX_n[13] +set_location_assignment PIN_AH30 -to HSMA_TX_n[14] +set_location_assignment PIN_AM29 -to HSMA_TX_n[15] +set_location_assignment PIN_AL30 -to HSMA_TX_n[16] +set_location_assignment PIN_AE27 -to HSMA_TX_n[2] +set_location_assignment PIN_AD29 -to HSMA_TX_n[3] +set_location_assignment PIN_AE29 -to HSMA_TX_n[4] +set_location_assignment PIN_AF26 -to HSMA_TX_n[5] +set_location_assignment PIN_AG32 -to HSMA_TX_n[6] +set_location_assignment PIN_AH29 -to HSMA_TX_n[7] +set_location_assignment PIN_AC29 -to HSMA_TX_n[8] +set_location_assignment PIN_AK29 -to HSMA_TX_n[9] +set_location_assignment PIN_AB27 -to HSMA_TX_p[0] +set_location_assignment PIN_AB30 -to HSMA_TX_p[1] +set_location_assignment PIN_AD30 -to HSMA_TX_p[10] +set_location_assignment PIN_AK32 -to HSMA_TX_p[11] +set_location_assignment PIN_AG27 -to HSMA_TX_p[12] +set_location_assignment PIN_AK31 -to HSMA_TX_p[13] +set_location_assignment PIN_AJ31 -to HSMA_TX_p[14] +set_location_assignment PIN_AL29 -to HSMA_TX_p[15] +set_location_assignment PIN_AK30 -to HSMA_TX_p[16] +set_location_assignment PIN_AD27 -to HSMA_TX_p[2] +set_location_assignment PIN_AD28 -to HSMA_TX_p[3] +set_location_assignment PIN_AE28 -to HSMA_TX_p[4] +set_location_assignment PIN_AE26 -to HSMA_TX_p[5] +set_location_assignment PIN_AG31 -to HSMA_TX_p[6] +set_location_assignment PIN_AG29 -to HSMA_TX_p[7] +set_location_assignment PIN_AC28 -to HSMA_TX_p[8] +set_location_assignment PIN_AJ29 -to HSMA_TX_p[9] +set_location_assignment PIN_W35 -to HSMB_CLKIN_N1 +set_location_assignment PIN_W5 -to HSMB_CLKIN_N2 +set_location_assignment PIN_W34 -to HSMB_CLKIN_P1 +set_location_assignment PIN_W6 -to HSMB_CLKIN_P2 +set_location_assignment PIN_AA5 -to HSMB_CLKIN0 +set_location_assignment PIN_W11 -to HSMB_CLKOUT_n2 +set_location_assignment PIN_W12 -to HSMB_CLKOUT_p2 +set_location_assignment PIN_H10 -to HSMB_D[0] +set_location_assignment PIN_D6 -to HSMB_D[1] +set_location_assignment PIN_G10 -to HSMB_D[2] +set_location_assignment PIN_C6 -to HSMB_D[3] +set_location_assignment PIN_AE2 -to HSMB_GXB_RX_p[0] +set_location_assignment PIN_AC2 -to HSMB_GXB_RX_p[1] +set_location_assignment PIN_U2 -to HSMB_GXB_RX_p[2] +set_location_assignment PIN_R2 -to HSMB_GXB_RX_p[3] +set_location_assignment PIN_N2 -to HSMB_GXB_RX_p[4] +set_location_assignment PIN_L2 -to HSMB_GXB_RX_p[5] +set_location_assignment PIN_E2 -to HSMB_GXB_RX_p[6] +set_location_assignment PIN_C2 -to HSMB_GXB_RX_p[7] +set_location_assignment PIN_AD4 -to HSMB_GXB_TX_p[0] +set_location_assignment PIN_AB4 -to HSMB_GXB_TX_p[1] +set_location_assignment PIN_T4 -to HSMB_GXB_TX_p[2] +set_location_assignment PIN_P4 -to HSMB_GXB_TX_p[3] +set_location_assignment PIN_M4 -to HSMB_GXB_TX_p[4] +set_location_assignment PIN_K4 -to HSMB_GXB_TX_p[5] +set_location_assignment PIN_D4 -to HSMB_GXB_TX_p[6] +set_location_assignment PIN_B4 -to HSMB_GXB_TX_p[7] +set_location_assignment PIN_J8 -to HSMB_OUT_n1 +set_location_assignment PIN_K8 -to HSMB_OUT_p1 +set_location_assignment PIN_L8 -to HSMB_OUT0 +set_location_assignment PIN_AA2 -to HSMB_REFCLK_p +set_location_assignment PIN_C5 -to HSMB_RX_n[0] +set_location_assignment PIN_C10 -to HSMB_RX_n[1] +set_location_assignment PIN_F9 -to HSMB_RX_n[10] +set_location_assignment PIN_N5 -to HSMB_RX_n[11] +set_location_assignment PIN_L5 -to HSMB_RX_n[12] +set_location_assignment PIN_R5 -to HSMB_RX_n[13] +set_location_assignment PIN_P6 -to HSMB_RX_n[14] +set_location_assignment PIN_U5 -to HSMB_RX_n[15] +set_location_assignment PIN_W7 -to HSMB_RX_n[16] +set_location_assignment PIN_C9 -to HSMB_RX_n[2] +set_location_assignment PIN_C8 -to HSMB_RX_n[3] +set_location_assignment PIN_C7 -to HSMB_RX_n[4] +set_location_assignment PIN_E10 -to HSMB_RX_n[5] +set_location_assignment PIN_F5 -to HSMB_RX_n[6] +set_location_assignment PIN_F6 -to HSMB_RX_n[7] +set_location_assignment PIN_E7 -to HSMB_RX_n[8] +set_location_assignment PIN_F8 -to HSMB_RX_n[9] +set_location_assignment PIN_D5 -to HSMB_RX_p[0] +set_location_assignment PIN_D10 -to HSMB_RX_p[1] +set_location_assignment PIN_G9 -to HSMB_RX_p[10] +set_location_assignment PIN_N6 -to HSMB_RX_p[11] +set_location_assignment PIN_M6 -to HSMB_RX_p[12] +set_location_assignment PIN_R6 -to HSMB_RX_p[13] +set_location_assignment PIN_R7 -to HSMB_RX_p[14] +set_location_assignment PIN_V6 -to HSMB_RX_p[15] +set_location_assignment PIN_W8 -to HSMB_RX_p[16] +set_location_assignment PIN_D9 -to HSMB_RX_p[2] +set_location_assignment PIN_D8 -to HSMB_RX_p[3] +set_location_assignment PIN_D7 -to HSMB_RX_p[4] +set_location_assignment PIN_F10 -to HSMB_RX_p[5] +set_location_assignment PIN_G5 -to HSMB_RX_p[6] +set_location_assignment PIN_G6 -to HSMB_RX_p[7] +set_location_assignment PIN_F7 -to HSMB_RX_p[8] +set_location_assignment PIN_G8 -to HSMB_RX_p[9] +set_location_assignment PIN_J9 -to HSMB_TX_n[0] +set_location_assignment PIN_J10 -to HSMB_TX_n[1] +set_location_assignment PIN_L11 -to HSMB_TX_n[10] +set_location_assignment PIN_P8 -to HSMB_TX_n[11] +set_location_assignment PIN_R8 -to HSMB_TX_n[12] +set_location_assignment PIN_T9 -to HSMB_TX_n[13] +set_location_assignment PIN_V9 -to HSMB_TX_n[14] +set_location_assignment PIN_R10 -to HSMB_TX_n[15] +set_location_assignment PIN_V11 -to HSMB_TX_n[16] +set_location_assignment PIN_N10 -to HSMB_TX_n[2] +set_location_assignment PIN_M12 -to HSMB_TX_n[3] +set_location_assignment PIN_R11 -to HSMB_TX_n[4] +set_location_assignment PIN_T12 -to HSMB_TX_n[5] +set_location_assignment PIN_P13 -to HSMB_TX_n[6] +set_location_assignment PIN_G7 -to HSMB_TX_n[7] +set_location_assignment PIN_L10 -to HSMB_TX_n[8] +set_location_assignment PIN_M7 -to HSMB_TX_n[9] +set_location_assignment PIN_K9 -to HSMB_TX_p[0] +set_location_assignment PIN_K10 -to HSMB_TX_p[1] +set_location_assignment PIN_M11 -to HSMB_TX_p[10] +set_location_assignment PIN_N9 -to HSMB_TX_p[11] +set_location_assignment PIN_R9 -to HSMB_TX_p[12] +set_location_assignment PIN_U10 -to HSMB_TX_p[13] +set_location_assignment PIN_V10 -to HSMB_TX_p[14] +set_location_assignment PIN_T10 -to HSMB_TX_p[15] +set_location_assignment PIN_V12 -to HSMB_TX_p[16] +set_location_assignment PIN_N11 -to HSMB_TX_p[2] +set_location_assignment PIN_N12 -to HSMB_TX_p[3] +set_location_assignment PIN_R12 -to HSMB_TX_p[4] +set_location_assignment PIN_T13 -to HSMB_TX_p[5] +set_location_assignment PIN_R13 -to HSMB_TX_p[6] +set_location_assignment PIN_H7 -to HSMB_TX_p[7] +set_location_assignment PIN_M10 -to HSMB_TX_p[8] +set_location_assignment PIN_M8 -to HSMB_TX_p[9] +set_location_assignment PIN_L19 -to HSMC_SCL +set_location_assignment PIN_M19 -to HSMC_SDA +set_location_assignment PIN_V28 -to LED[0] +set_location_assignment PIN_W28 -to LED[1] +set_location_assignment PIN_R29 -to LED[2] +set_location_assignment PIN_P29 -to LED[3] +set_location_assignment PIN_N29 -to LED[4] +set_location_assignment PIN_M29 -to LED[5] +set_location_assignment PIN_M30 -to LED[6] +set_location_assignment PIN_N30 -to LED[7] +set_location_assignment PIN_AV23 -to M1_DDR2_addr[0] +set_location_assignment PIN_AL25 -to M1_DDR2_addr[1] +set_location_assignment PIN_AJ26 -to M1_DDR2_addr[10] +set_location_assignment PIN_AU28 -to M1_DDR2_addr[11] +set_location_assignment PIN_AP26 -to M1_DDR2_addr[12] +set_location_assignment PIN_AD21 -to M1_DDR2_addr[13] +set_location_assignment PIN_AU29 -to M1_DDR2_addr[14] +set_location_assignment PIN_AT29 -to M1_DDR2_addr[15] +set_location_assignment PIN_AW23 -to M1_DDR2_addr[2] +set_location_assignment PIN_AM26 -to M1_DDR2_addr[3] +set_location_assignment PIN_AN26 -to M1_DDR2_addr[4] +set_location_assignment PIN_AK26 -to M1_DDR2_addr[5] +set_location_assignment PIN_AU27 -to M1_DDR2_addr[6] +set_location_assignment PIN_AT27 -to M1_DDR2_addr[7] +set_location_assignment PIN_AL27 -to M1_DDR2_addr[8] +set_location_assignment PIN_AN27 -to M1_DDR2_addr[9] +set_location_assignment PIN_AH26 -to M1_DDR2_ba[0] +set_location_assignment PIN_AD25 -to M1_DDR2_ba[1] +set_location_assignment PIN_AP27 -to M1_DDR2_ba[2] +set_location_assignment PIN_AJ25 -to M1_DDR2_cas_n +set_location_assignment PIN_AT28 -to M1_DDR2_cke[0] +set_location_assignment PIN_AK27 -to M1_DDR2_cke[1] +set_location_assignment PIN_AR28 -to M1_DDR2_clk_n[0] +set_location_assignment PIN_AF20 -to M1_DDR2_clk_n[1] +set_location_assignment PIN_AP28 -to M1_DDR2_clk[0] +set_location_assignment PIN_AE20 -to M1_DDR2_clk[1] +set_location_assignment PIN_AG21 -to M1_DDR2_cs_n[0] +set_location_assignment PIN_AE25 -to M1_DDR2_cs_n[1] +set_location_assignment PIN_AW31 -to M1_DDR2_dm[0] +set_location_assignment PIN_AW26 -to M1_DDR2_dm[1] +set_location_assignment PIN_AU23 -to M1_DDR2_dm[2] +set_location_assignment PIN_AH22 -to M1_DDR2_dm[3] +set_location_assignment PIN_AL17 -to M1_DDR2_dm[4] +set_location_assignment PIN_AT16 -to M1_DDR2_dm[5] +set_location_assignment PIN_AU14 -to M1_DDR2_dm[6] +set_location_assignment PIN_AN13 -to M1_DDR2_dm[7] +set_location_assignment PIN_AV32 -to M1_DDR2_dq[0] +set_location_assignment PIN_AV31 -to M1_DDR2_dq[1] +set_location_assignment PIN_AU25 -to M1_DDR2_dq[10] +set_location_assignment PIN_AT25 -to M1_DDR2_dq[11] +set_location_assignment PIN_AM25 -to M1_DDR2_dq[12] +set_location_assignment PIN_AN25 -to M1_DDR2_dq[13] +set_location_assignment PIN_AR25 -to M1_DDR2_dq[14] +set_location_assignment PIN_AN24 -to M1_DDR2_dq[15] +set_location_assignment PIN_AN23 -to M1_DDR2_dq[16] +set_location_assignment PIN_AP23 -to M1_DDR2_dq[17] +set_location_assignment PIN_AL22 -to M1_DDR2_dq[18] +set_location_assignment PIN_AM22 -to M1_DDR2_dq[19] +set_location_assignment PIN_AW29 -to M1_DDR2_dq[2] +set_location_assignment PIN_AM23 -to M1_DDR2_dq[20] +set_location_assignment PIN_AR23 -to M1_DDR2_dq[21] +set_location_assignment PIN_AT23 -to M1_DDR2_dq[22] +set_location_assignment PIN_AL21 -to M1_DDR2_dq[23] +set_location_assignment PIN_AJ22 -to M1_DDR2_dq[24] +set_location_assignment PIN_AH23 -to M1_DDR2_dq[25] +set_location_assignment PIN_AF22 -to M1_DDR2_dq[26] +set_location_assignment PIN_AE23 -to M1_DDR2_dq[27] +set_location_assignment PIN_AK24 -to M1_DDR2_dq[28] +set_location_assignment PIN_AJ23 -to M1_DDR2_dq[29] +set_location_assignment PIN_AV28 -to M1_DDR2_dq[3] +set_location_assignment PIN_AF23 -to M1_DDR2_dq[30] +set_location_assignment PIN_AE22 -to M1_DDR2_dq[31] +set_location_assignment PIN_AK17 -to M1_DDR2_dq[32] +set_location_assignment PIN_AM17 -to M1_DDR2_dq[33] +set_location_assignment PIN_AH16 -to M1_DDR2_dq[34] +set_location_assignment PIN_AJ16 -to M1_DDR2_dq[35] +set_location_assignment PIN_AG16 -to M1_DDR2_dq[36] +set_location_assignment PIN_AH17 -to M1_DDR2_dq[37] +set_location_assignment PIN_AF17 -to M1_DDR2_dq[38] +set_location_assignment PIN_AE17 -to M1_DDR2_dq[39] +set_location_assignment PIN_AW34 -to M1_DDR2_dq[4] +set_location_assignment PIN_AR17 -to M1_DDR2_dq[40] +set_location_assignment PIN_AN16 -to M1_DDR2_dq[41] +set_location_assignment PIN_AU16 -to M1_DDR2_dq[42] +set_location_assignment PIN_AW16 -to M1_DDR2_dq[43] +set_location_assignment PIN_AN17 -to M1_DDR2_dq[44] +set_location_assignment PIN_AP17 -to M1_DDR2_dq[45] +set_location_assignment PIN_AU15 -to M1_DDR2_dq[46] +set_location_assignment PIN_AT15 -to M1_DDR2_dq[47] +set_location_assignment PIN_AW11 -to M1_DDR2_dq[48] +set_location_assignment PIN_AW12 -to M1_DDR2_dq[49] +set_location_assignment PIN_AW33 -to M1_DDR2_dq[5] +set_location_assignment PIN_AT14 -to M1_DDR2_dq[50] +set_location_assignment PIN_AU12 -to M1_DDR2_dq[51] +set_location_assignment PIN_AW14 -to M1_DDR2_dq[52] +set_location_assignment PIN_AV14 -to M1_DDR2_dq[53] +set_location_assignment PIN_AU11 -to M1_DDR2_dq[54] +set_location_assignment PIN_AT12 -to M1_DDR2_dq[55] +set_location_assignment PIN_AP13 -to M1_DDR2_dq[56] +set_location_assignment PIN_AN14 -to M1_DDR2_dq[57] +set_location_assignment PIN_AL15 -to M1_DDR2_dq[58] +set_location_assignment PIN_AM14 -to M1_DDR2_dq[59] +set_location_assignment PIN_AW28 -to M1_DDR2_dq[6] +set_location_assignment PIN_AR14 -to M1_DDR2_dq[60] +set_location_assignment PIN_AP14 -to M1_DDR2_dq[61] +set_location_assignment PIN_AL14 -to M1_DDR2_dq[62] +set_location_assignment PIN_AL13 -to M1_DDR2_dq[63] +set_location_assignment PIN_AW27 -to M1_DDR2_dq[7] +set_location_assignment PIN_AP25 -to M1_DDR2_dq[8] +set_location_assignment PIN_AV26 -to M1_DDR2_dq[9] +set_location_assignment PIN_AW30 -to M1_DDR2_dqsn[0] +set_location_assignment PIN_AU26 -to M1_DDR2_dqsn[1] +set_location_assignment PIN_AU24 -to M1_DDR2_dqsn[2] +set_location_assignment PIN_AL23 -to M1_DDR2_dqsn[3] +set_location_assignment PIN_AL16 -to M1_DDR2_dqsn[4] +set_location_assignment PIN_AR16 -to M1_DDR2_dqsn[5] +set_location_assignment PIN_AW13 -to M1_DDR2_dqsn[6] +set_location_assignment PIN_AT13 -to M1_DDR2_dqsn[7] +set_location_assignment PIN_AV29 -to M1_DDR2_dqs[0] +set_location_assignment PIN_AT26 -to M1_DDR2_dqs[1] +set_location_assignment PIN_AT24 -to M1_DDR2_dqs[2] +set_location_assignment PIN_AK23 -to M1_DDR2_dqs[3] +set_location_assignment PIN_AK16 -to M1_DDR2_dqs[4] +set_location_assignment PIN_AP16 -to M1_DDR2_dqs[5] +set_location_assignment PIN_AV13 -to M1_DDR2_dqs[6] +set_location_assignment PIN_AR13 -to M1_DDR2_dqs[7] +set_location_assignment PIN_AG20 -to M1_DDR2_odt[0] +set_location_assignment PIN_AE24 -to M1_DDR2_odt[1] +set_location_assignment PIN_AE21 -to M1_DDR2_ras_n +set_location_assignment PIN_AV25 -to M1_DDR2_SA[0] +set_location_assignment PIN_AW25 -to M1_DDR2_SA[1] +set_location_assignment PIN_AH24 -to M1_DDR2_SCL +set_location_assignment PIN_AG24 -to M1_DDR2_SDA +set_location_assignment PIN_AK25 -to M1_DDR2_we_n +set_location_assignment PIN_B14 -to M2_DDR2_addr[0] +set_location_assignment PIN_B11 -to M2_DDR2_addr[1] +set_location_assignment PIN_R18 -to M2_DDR2_addr[10] +set_location_assignment PIN_L14 -to M2_DDR2_addr[11] +set_location_assignment PIN_N15 -to M2_DDR2_addr[12] +set_location_assignment PIN_C19 -to M2_DDR2_addr[13] +set_location_assignment PIN_K14 -to M2_DDR2_addr[14] +set_location_assignment PIN_M13 -to M2_DDR2_addr[15] +set_location_assignment PIN_D14 -to M2_DDR2_addr[2] +set_location_assignment PIN_R14 -to M2_DDR2_addr[3] +set_location_assignment PIN_C13 -to M2_DDR2_addr[4] +set_location_assignment PIN_C11 -to M2_DDR2_addr[5] +set_location_assignment PIN_A11 -to M2_DDR2_addr[6] +set_location_assignment PIN_N13 -to M2_DDR2_addr[7] +set_location_assignment PIN_A10 -to M2_DDR2_addr[8] +set_location_assignment PIN_M14 -to M2_DDR2_addr[9] +set_location_assignment PIN_C12 -to M2_DDR2_ba[0] +set_location_assignment PIN_C14 -to M2_DDR2_ba[1] +set_location_assignment PIN_B10 -to M2_DDR2_ba[2] +set_location_assignment PIN_A13 -to M2_DDR2_cas_n +set_location_assignment PIN_D11 -to M2_DDR2_cke[0] +set_location_assignment PIN_K12 -to M2_DDR2_cke[1] +set_location_assignment PIN_K13 -to M2_DDR2_clk_n[0] +set_location_assignment PIN_A17 -to M2_DDR2_clk_n[1] +set_location_assignment PIN_L13 -to M2_DDR2_clk[0] +set_location_assignment PIN_B17 -to M2_DDR2_clk[1] +set_location_assignment PIN_H19 -to M2_DDR2_cs_n[0] +set_location_assignment PIN_B13 -to M2_DDR2_cs_n[1] +set_location_assignment PIN_H14 -to M2_DDR2_dm[0] +set_location_assignment PIN_M17 -to M2_DDR2_dm[1] +set_location_assignment PIN_G15 -to M2_DDR2_dm[2] +set_location_assignment PIN_F17 -to M2_DDR2_dm[3] +set_location_assignment PIN_P23 -to M2_DDR2_dm[4] +set_location_assignment PIN_B25 -to M2_DDR2_dm[5] +set_location_assignment PIN_D28 -to M2_DDR2_dm[6] +set_location_assignment PIN_C30 -to M2_DDR2_dm[7] +set_location_assignment PIN_F12 -to M2_DDR2_dq[0] +set_location_assignment PIN_H13 -to M2_DDR2_dq[1] +set_location_assignment PIN_L16 -to M2_DDR2_dq[10] +set_location_assignment PIN_K17 -to M2_DDR2_dq[11] +set_location_assignment PIN_P16 -to M2_DDR2_dq[12] +set_location_assignment PIN_N16 -to M2_DDR2_dq[13] +set_location_assignment PIN_J17 -to M2_DDR2_dq[14] +set_location_assignment PIN_H17 -to M2_DDR2_dq[15] +set_location_assignment PIN_B16 -to M2_DDR2_dq[16] +set_location_assignment PIN_A16 -to M2_DDR2_dq[17] +set_location_assignment PIN_F15 -to M2_DDR2_dq[18] +set_location_assignment PIN_D16 -to M2_DDR2_dq[19] +set_location_assignment PIN_E14 -to M2_DDR2_dq[2] +set_location_assignment PIN_C16 -to M2_DDR2_dq[20] +set_location_assignment PIN_E16 -to M2_DDR2_dq[21] +set_location_assignment PIN_G16 -to M2_DDR2_dq[22] +set_location_assignment PIN_G17 -to M2_DDR2_dq[23] +set_location_assignment PIN_C17 -to M2_DDR2_dq[24] +set_location_assignment PIN_E17 -to M2_DDR2_dq[25] +set_location_assignment PIN_F19 -to M2_DDR2_dq[26] +set_location_assignment PIN_G19 -to M2_DDR2_dq[27] +set_location_assignment PIN_C18 -to M2_DDR2_dq[28] +set_location_assignment PIN_D18 -to M2_DDR2_dq[29] +set_location_assignment PIN_F14 -to M2_DDR2_dq[3] +set_location_assignment PIN_F20 -to M2_DDR2_dq[30] +set_location_assignment PIN_G20 -to M2_DDR2_dq[31] +set_location_assignment PIN_N22 -to M2_DDR2_dq[32] +set_location_assignment PIN_M23 -to M2_DDR2_dq[33] +set_location_assignment PIN_K24 -to M2_DDR2_dq[34] +set_location_assignment PIN_J25 -to M2_DDR2_dq[35] +set_location_assignment PIN_R22 -to M2_DDR2_dq[36] +set_location_assignment PIN_P22 -to M2_DDR2_dq[37] +set_location_assignment PIN_M24 -to M2_DDR2_dq[38] +set_location_assignment PIN_J24 -to M2_DDR2_dq[39] +set_location_assignment PIN_J12 -to M2_DDR2_dq[4] +set_location_assignment PIN_G25 -to M2_DDR2_dq[40] +set_location_assignment PIN_C25 -to M2_DDR2_dq[41] +set_location_assignment PIN_A26 -to M2_DDR2_dq[42] +set_location_assignment PIN_C26 -to M2_DDR2_dq[43] +set_location_assignment PIN_G24 -to M2_DDR2_dq[44] +set_location_assignment PIN_F24 -to M2_DDR2_dq[45] +set_location_assignment PIN_D25 -to M2_DDR2_dq[46] +set_location_assignment PIN_D26 -to M2_DDR2_dq[47] +set_location_assignment PIN_F27 -to M2_DDR2_dq[48] +set_location_assignment PIN_G27 -to M2_DDR2_dq[49] +set_location_assignment PIN_J13 -to M2_DDR2_dq[5] +set_location_assignment PIN_F28 -to M2_DDR2_dq[50] +set_location_assignment PIN_H28 -to M2_DDR2_dq[51] +set_location_assignment PIN_H26 -to M2_DDR2_dq[52] +set_location_assignment PIN_J26 -to M2_DDR2_dq[53] +set_location_assignment PIN_E28 -to M2_DDR2_dq[54] +set_location_assignment PIN_G29 -to M2_DDR2_dq[55] +set_location_assignment PIN_C29 -to M2_DDR2_dq[56] +set_location_assignment PIN_A31 -to M2_DDR2_dq[57] +set_location_assignment PIN_C27 -to M2_DDR2_dq[58] +set_location_assignment PIN_D27 -to M2_DDR2_dq[59] +set_location_assignment PIN_G14 -to M2_DDR2_dq[6] +set_location_assignment PIN_A27 -to M2_DDR2_dq[60] +set_location_assignment PIN_A28 -to M2_DDR2_dq[61] +set_location_assignment PIN_B29 -to M2_DDR2_dq[62] +set_location_assignment PIN_B31 -to M2_DDR2_dq[63] +set_location_assignment PIN_D13 -to M2_DDR2_dq[7] +set_location_assignment PIN_P17 -to M2_DDR2_dq[8] +set_location_assignment PIN_N17 -to M2_DDR2_dq[9] +set_location_assignment PIN_E13 -to M2_DDR2_dqsn[0] +set_location_assignment PIN_J16 -to M2_DDR2_dqsn[1] +set_location_assignment PIN_C15 -to M2_DDR2_dqsn[2] +set_location_assignment PIN_F18 -to M2_DDR2_dqsn[3] +set_location_assignment PIN_K23 -to M2_DDR2_dqsn[4] +set_location_assignment PIN_E25 -to M2_DDR2_dqsn[5] +set_location_assignment PIN_D29 -to M2_DDR2_dqsn[6] +set_location_assignment PIN_B28 -to M2_DDR2_dqsn[7] +set_location_assignment PIN_F13 -to M2_DDR2_dqs[0] +set_location_assignment PIN_K16 -to M2_DDR2_dqs[1] +set_location_assignment PIN_D15 -to M2_DDR2_dqs[2] +set_location_assignment PIN_G18 -to M2_DDR2_dqs[3] +set_location_assignment PIN_L23 -to M2_DDR2_dqs[4] +set_location_assignment PIN_F25 -to M2_DDR2_dqs[5] +set_location_assignment PIN_E29 -to M2_DDR2_dqs[6] +set_location_assignment PIN_C28 -to M2_DDR2_dqs[7] +set_location_assignment PIN_D19 -to M2_DDR2_odt[0] +set_location_assignment PIN_A14 -to M2_DDR2_odt[1] +set_location_assignment PIN_J18 -to M2_DDR2_ras_n +set_location_assignment PIN_A18 -to M2_DDR2_SA[0] +set_location_assignment PIN_B19 -to M2_DDR2_SA[1] +set_location_assignment PIN_K15 -to M2_DDR2_SCL +set_location_assignment PIN_J15 -to M2_DDR2_SDA +set_location_assignment PIN_P18 -to M2_DDR2_we_n +set_location_assignment PIN_AW32 -to MAX_CONF_D[0] +set_location_assignment PIN_AG22 -to MAX_CONF_D[1] +set_location_assignment PIN_AV11 -to MAX_CONF_D[2] +set_location_assignment PIN_AG17 -to MAX_CONF_D[3] +set_location_assignment PIN_AP24 -to MAX_I2C_SCLK +set_location_assignment PIN_AN22 -to MAX_I2C_SDAT +set_location_assignment PIN_AC35 -to OSC_50_BANK2 +set_location_assignment PIN_AV22 -to OSC_50_BANK3 +set_location_assignment PIN_AV19 -to OSC_50_BANK4 +set_location_assignment PIN_AC6 -to OSC_50_BANK5 +set_location_assignment PIN_AB6 -to OSC_50_BANK6 +set_location_assignment PIN_A19 -to OSC_50_BANK7 +set_location_assignment PIN_K26 -to OTG_A[1] +set_location_assignment PIN_A29 -to OTG_A[10] +set_location_assignment PIN_J27 -to OTG_A[11] +set_location_assignment PIN_G26 -to OTG_A[12] +set_location_assignment PIN_F26 -to OTG_A[13] +set_location_assignment PIN_G28 -to OTG_A[14] +set_location_assignment PIN_B26 -to OTG_A[15] +set_location_assignment PIN_D17 -to OTG_A[16] +set_location_assignment PIN_F16 -to OTG_A[17] +set_location_assignment PIN_P25 -to OTG_A[2] +set_location_assignment PIN_N25 -to OTG_A[3] +set_location_assignment PIN_R24 -to OTG_A[4] +set_location_assignment PIN_P24 -to OTG_A[5] +set_location_assignment PIN_M25 -to OTG_A[6] +set_location_assignment PIN_L25 -to OTG_A[7] +set_location_assignment PIN_N23 -to OTG_A[8] +set_location_assignment PIN_K28 -to OTG_A[9] +set_location_assignment PIN_P19 -to OTG_CS_n +set_location_assignment PIN_AF16 -to OTG_D[0] +set_location_assignment PIN_AJ14 -to OTG_D[1] +set_location_assignment PIN_AG19 -to OTG_D[10] +set_location_assignment PIN_AM19 -to OTG_D[11] +set_location_assignment PIN_AN19 -to OTG_D[12] +set_location_assignment PIN_AV16 -to OTG_D[13] +set_location_assignment PIN_AT17 -to OTG_D[14] +set_location_assignment PIN_AV17 -to OTG_D[15] +set_location_assignment PIN_AU17 -to OTG_D[16] +set_location_assignment PIN_AW18 -to OTG_D[17] +set_location_assignment PIN_AT18 -to OTG_D[18] +set_location_assignment PIN_AU18 -to OTG_D[19] +set_location_assignment PIN_AD15 -to OTG_D[2] +set_location_assignment PIN_AR19 -to OTG_D[20] +set_location_assignment PIN_AW20 -to OTG_D[21] +set_location_assignment PIN_AW21 -to OTG_D[22] +set_location_assignment PIN_AF19 -to OTG_D[23] +set_location_assignment PIN_AE19 -to OTG_D[24] +set_location_assignment PIN_AE18 -to OTG_D[25] +set_location_assignment PIN_AD19 -to OTG_D[26] +set_location_assignment PIN_G13 -to OTG_D[27] +set_location_assignment PIN_M16 -to OTG_D[28] +set_location_assignment PIN_M27 -to OTG_D[29] +set_location_assignment PIN_AE15 -to OTG_D[3] +set_location_assignment PIN_K27 -to OTG_D[30] +set_location_assignment PIN_L26 -to OTG_D[31] +set_location_assignment PIN_AE16 -to OTG_D[4] +set_location_assignment PIN_AH14 -to OTG_D[5] +set_location_assignment PIN_AM13 -to OTG_D[6] +set_location_assignment PIN_AN15 -to OTG_D[7] +set_location_assignment PIN_AP15 -to OTG_D[8] +set_location_assignment PIN_AG18 -to OTG_D[9] +set_location_assignment PIN_AH20 -to OTG_DC_DACK +set_location_assignment PIN_AP21 -to OTG_DC_DREQ +set_location_assignment PIN_AT22 -to OTG_DC_IRQ +set_location_assignment PIN_AT21 -to OTG_HC_DACK +set_location_assignment PIN_AN21 -to OTG_HC_DREQ +set_location_assignment PIN_AJ20 -to OTG_HC_IRQ +set_location_assignment PIN_N19 -to OTG_OE_n +set_location_assignment PIN_AU22 -to OTG_RESET_n +set_location_assignment PIN_AR22 -to OTG_WE_n +set_location_assignment PIN_V30 -to PCIE_PREST_n +set_location_assignment PIN_AN38 -to PCIE_REFCLK_p +set_location_assignment PIN_AU38 -to PCIE_RX_p[0] +set_location_assignment PIN_AR38 -to PCIE_RX_p[1] +set_location_assignment PIN_AJ38 -to PCIE_RX_p[2] +set_location_assignment PIN_AG38 -to PCIE_RX_p[3] +set_location_assignment PIN_AE38 -to PCIE_RX_p[4] +set_location_assignment PIN_AC38 -to PCIE_RX_p[5] +set_location_assignment PIN_U38 -to PCIE_RX_p[6] +set_location_assignment PIN_R38 -to PCIE_RX_p[7] +set_location_assignment PIN_R31 -to PCIE_SMBCLK +set_location_assignment PIN_W33 -to PCIE_SMBDAT +set_location_assignment PIN_AT36 -to PCIE_TX_p[0] +set_location_assignment PIN_AP36 -to PCIE_TX_p[1] +set_location_assignment PIN_AH36 -to PCIE_TX_p[2] +set_location_assignment PIN_AF36 -to PCIE_TX_p[3] +set_location_assignment PIN_AD36 -to PCIE_TX_p[4] +set_location_assignment PIN_AB36 -to PCIE_TX_p[5] +set_location_assignment PIN_T36 -to PCIE_TX_p[6] +set_location_assignment PIN_P36 -to PCIE_TX_p[7] +set_location_assignment PIN_U35 -to PCIE_WAKE_n +set_location_assignment PIN_B22 -to PLL_CLKIN_p +set_location_assignment PIN_AU2 -to SATA_DEVICE_RX_p[0] +set_location_assignment PIN_AJ2 -to SATA_DEVICE_RX_p[1] +set_location_assignment PIN_AT4 -to SATA_DEVICE_TX_p[0] +set_location_assignment PIN_AH4 -to SATA_DEVICE_TX_p[1] +set_location_assignment PIN_AR2 -to SATA_HOST_RX_p[0] +set_location_assignment PIN_AG2 -to SATA_HOST_RX_p[1] +set_location_assignment PIN_AP4 -to SATA_HOST_TX_p[0] +set_location_assignment PIN_AF4 -to SATA_HOST_TX_p[1] +set_location_assignment PIN_AN2 -to SATA_REFCLK_p +set_location_assignment PIN_AT19 -to SD_CLK +set_location_assignment PIN_AV20 -to SD_CMD +set_location_assignment PIN_AR20 -to SD_DAT[0] +set_location_assignment PIN_AT20 -to SD_DAT[1] +set_location_assignment PIN_AU19 -to SD_DAT[2] +set_location_assignment PIN_AU20 -to SD_DAT[3] +set_location_assignment PIN_AH18 -to SD_WP_n +set_location_assignment PIN_L34 -to SEG0_D[0] +set_location_assignment PIN_M34 -to SEG0_D[1] +set_location_assignment PIN_M33 -to SEG0_D[2] +set_location_assignment PIN_H31 -to SEG0_D[3] +set_location_assignment PIN_J33 -to SEG0_D[4] +set_location_assignment PIN_L35 -to SEG0_D[5] +set_location_assignment PIN_K32 -to SEG0_D[6] +set_location_assignment PIN_AL34 -to SEG0_DP +set_location_assignment PIN_E31 -to SEG1_D[0] +set_location_assignment PIN_F31 -to SEG1_D[1] +set_location_assignment PIN_G31 -to SEG1_D[2] +set_location_assignment PIN_C34 -to SEG1_D[3] +set_location_assignment PIN_C33 -to SEG1_D[4] +set_location_assignment PIN_D33 -to SEG1_D[5] +set_location_assignment PIN_D34 -to SEG1_D[6] +set_location_assignment PIN_AL35 -to SEG1_DP +set_location_assignment PIN_J7 -to SLIDE_SW[0] +set_location_assignment PIN_K7 -to SLIDE_SW[1] +set_location_assignment PIN_AK6 -to SLIDE_SW[2] +set_location_assignment PIN_L7 -to SLIDE_SW[3] +set_location_assignment PIN_B23 -to SMA_CLKIN_p +set_location_assignment PIN_M20 -to SMA_CLKOUT_p +set_location_assignment PIN_W2 -to SMA_GXBCLK_p +set_location_assignment PIN_H35 -to SSRAM_ADV +set_location_assignment PIN_R27 -to SSRAM_BWA_n +set_location_assignment PIN_N31 -to SSRAM_BWB_n +set_location_assignment PIN_R28 -to SSRAM_CE_n +set_location_assignment PIN_N28 -to SSRAM_CKE_n +set_location_assignment PIN_M31 -to SSRAM_CLK +set_location_assignment PIN_H34 -to SSRAM_OE_n +set_location_assignment PIN_L31 -to SSRAM_WE_n +set_location_assignment PIN_AB13 -to SW[0] +set_location_assignment PIN_AB12 -to SW[1] +set_location_assignment PIN_AB11 -to SW[2] +set_location_assignment PIN_AB10 -to SW[3] +set_location_assignment PIN_AB9 -to SW[4] +set_location_assignment PIN_AC8 -to SW[5] +set_location_assignment PIN_AH6 -to SW[6] +set_location_assignment PIN_AG6 -to SW[7] +set_location_assignment PIN_AP19 -to TEMP_INT_n +set_location_assignment PIN_AN18 -to TEMP_SMCLK +set_location_assignment PIN_AP18 -to TEMP_SMDAT +set_location_assignment PIN_AN35 -to UART_CTS +set_location_assignment PIN_AH33 -to UART_RTS +set_location_assignment PIN_AH32 -to UART_RXD +set_location_assignment PIN_AN34 -to UART_TXD + + + + +set_location_assignment PIN_P26 -to termination_blk0~_rup_pad +set_location_assignment PIN_N26 -to termination_blk0~_rdn_pad + + +#============================================================ +# I/O Standard +#============================================================ +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to BUTTON[0] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to BUTTON[1] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to BUTTON[2] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to BUTTON[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to CPU_RESET_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to CSENSE_ADC_F0 +set_instance_assignment -name IO_STANDARD "1.8 V" -to CSENSE_CS_n[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to CSENSE_CS_n[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to CSENSE_SCK +set_instance_assignment -name IO_STANDARD "1.8 V" -to CSENSE_SDI +set_instance_assignment -name IO_STANDARD "1.8 V" -to CSENSE_SDO +set_instance_assignment -name IO_STANDARD "2.5 V" -to EEP_SCL +set_instance_assignment -name IO_STANDARD "2.5 V" -to EEP_SDA +set_instance_assignment -name IO_STANDARD "1.8 V" -to ETH_INT_n[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ETH_INT_n[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ETH_INT_n[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ETH_INT_n[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ETH_MDC[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ETH_MDC[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ETH_MDC[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ETH_MDC[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ETH_MDIO[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ETH_MDIO[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ETH_MDIO[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ETH_MDIO[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ETH_RST_n +set_instance_assignment -name IO_STANDARD LVDS -to ETH_RX_p[0] +set_instance_assignment -name IO_STANDARD LVDS -to ETH_RX_p[1] +set_instance_assignment -name IO_STANDARD LVDS -to ETH_RX_p[2] +set_instance_assignment -name IO_STANDARD LVDS -to ETH_RX_p[3] +set_instance_assignment -name IO_STANDARD LVDS -to ETH_TX_p[0] +set_instance_assignment -name IO_STANDARD LVDS -to ETH_TX_p[1] +set_instance_assignment -name IO_STANDARD LVDS -to ETH_TX_p[2] +set_instance_assignment -name IO_STANDARD LVDS -to ETH_TX_p[3] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to EXT_IO +set_instance_assignment -name IO_STANDARD "1.8 V" -to FAN_CTRL +set_instance_assignment -name IO_STANDARD "2.5 V" -to FLASH_ADV_n +set_instance_assignment -name IO_STANDARD "2.5 V" -to FLASH_CE_n +set_instance_assignment -name IO_STANDARD "2.5 V" -to FLASH_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to FLASH_OE_n +set_instance_assignment -name IO_STANDARD "2.5 V" -to FLASH_RYBY_n +set_instance_assignment -name IO_STANDARD "2.5 V" -to FLASH_RESET_n +set_instance_assignment -name IO_STANDARD "2.5 V" -to FLASH_WE_n +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[10] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[11] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[12] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[13] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[14] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[15] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[16] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[17] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[18] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[19] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[20] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[21] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[22] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[23] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[24] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[25] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[8] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[9] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[10] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[11] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[12] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[13] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[14] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[15] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[8] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[9] +set_instance_assignment -name IO_STANDARD "1.8 V" -to GCLKIN +set_instance_assignment -name IO_STANDARD "1.8 V" -to GCLKOUT_FPGA +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[0] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[1] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[10] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[11] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[12] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[13] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[14] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[15] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[16] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[17] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[18] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[19] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[2] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[20] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[21] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[22] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[23] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[24] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[25] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[26] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[27] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[28] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[29] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[3] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[30] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[31] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[32] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[33] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[34] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[35] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[4] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[5] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[6] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[7] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[8] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO0_D[9] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[0] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[1] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[10] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[11] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[12] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[13] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[14] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[15] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[16] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[17] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[18] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[19] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[2] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[20] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[21] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[22] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[23] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[24] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[25] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[26] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[27] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[28] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[29] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[3] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[30] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[31] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[32] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[33] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[34] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[35] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[4] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[5] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[6] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[7] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[8] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to GPIO1_D[9] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_CLKIN_N1 +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_CLKIN_N2 +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_CLKIN_P1 +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_CLKIN_P2 +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_CLKIN0 +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_CLKOUT_n2 +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_CLKOUT_p2 +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_D[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_D[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_D[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_D[3] +set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to HSMA_GXB_RX_p[0] +set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to HSMA_GXB_RX_p[1] +set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to HSMA_GXB_RX_p[2] +set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to HSMA_GXB_RX_p[3] +set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to HSMA_GXB_TX_p[0] +set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to HSMA_GXB_TX_p[1] +set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to HSMA_GXB_TX_p[2] +set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to HSMA_GXB_TX_p[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_OUT_n1 +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_OUT_p1 +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_OUT0 +set_instance_assignment -name IO_STANDARD LVDS -to HSMA_REFCLK_p +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_n[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_n[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_n[10] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_n[11] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_n[12] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_n[13] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_n[14] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_n[15] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_n[16] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_n[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_n[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_n[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_n[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_n[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_n[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_n[8] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_n[9] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_p[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_p[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_p[10] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_p[11] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_p[12] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_p[13] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_p[14] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_p[15] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_p[16] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_p[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_p[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_p[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_p[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_p[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_p[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_p[8] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_RX_p[9] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_n[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_n[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_n[10] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_n[11] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_n[12] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_n[13] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_n[14] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_n[15] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_n[16] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_n[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_n[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_n[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_n[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_n[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_n[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_n[8] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_n[9] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_p[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_p[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_p[10] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_p[11] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_p[12] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_p[13] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_p[14] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_p[15] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_p[16] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_p[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_p[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_p[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_p[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_p[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_p[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_p[8] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_TX_p[9] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_CLKIN_N1 +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_CLKIN_N2 +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_CLKIN_P1 +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_CLKIN_P2 +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_CLKIN0 +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_CLKOUT_n2 +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_CLKOUT_p2 +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_D[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_D[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_D[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_D[3] +set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to HSMB_GXB_RX_p[0] +set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to HSMB_GXB_RX_p[1] +set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to HSMB_GXB_RX_p[2] +set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to HSMB_GXB_RX_p[3] +set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to HSMB_GXB_RX_p[4] +set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to HSMB_GXB_RX_p[5] +set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to HSMB_GXB_RX_p[6] +set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to HSMB_GXB_RX_p[7] +set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to HSMB_GXB_TX_p[0] +set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to HSMB_GXB_TX_p[1] +set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to HSMB_GXB_TX_p[2] +set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to HSMB_GXB_TX_p[3] +set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to HSMB_GXB_TX_p[4] +set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to HSMB_GXB_TX_p[5] +set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to HSMB_GXB_TX_p[6] +set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to HSMB_GXB_TX_p[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_OUT_n1 +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_OUT_p1 +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_OUT0 +set_instance_assignment -name IO_STANDARD LVDS -to HSMB_REFCLK_p +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_n[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_n[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_n[10] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_n[11] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_n[12] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_n[13] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_n[14] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_n[15] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_n[16] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_n[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_n[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_n[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_n[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_n[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_n[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_n[8] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_n[9] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_p[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_p[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_p[10] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_p[11] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_p[12] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_p[13] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_p[14] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_p[15] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_p[16] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_p[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_p[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_p[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_p[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_p[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_p[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_p[8] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_RX_p[9] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_n[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_n[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_n[10] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_n[11] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_n[12] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_n[13] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_n[14] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_n[15] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_n[16] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_n[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_n[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_n[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_n[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_n[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_n[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_n[8] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_n[9] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_p[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_p[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_p[10] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_p[11] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_p[12] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_p[13] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_p[14] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_p[15] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_p[16] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_p[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_p[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_p[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_p[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_p[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_p[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_p[8] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_TX_p[9] +set_instance_assignment -name IO_STANDARD "1.8 V" -to HSMC_SCL +set_instance_assignment -name IO_STANDARD "1.8 V" -to HSMC_SDA +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[7] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_addr[15] +set_instance_assignment -name IO_STANDARD "1.8 V" -to M1_DDR2_SA[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to M1_DDR2_SA[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to M1_DDR2_SCL +set_instance_assignment -name IO_STANDARD "1.8 V" -to M1_DDR2_SDA +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_addr[15] +set_instance_assignment -name IO_STANDARD "1.8 V" -to M2_DDR2_SA[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to M2_DDR2_SA[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to M2_DDR2_SCL +set_instance_assignment -name IO_STANDARD "1.8 V" -to M2_DDR2_SDA +set_instance_assignment -name IO_STANDARD "1.8 V" -to MAX_CONF_D[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to MAX_CONF_D[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to MAX_CONF_D[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to MAX_CONF_D[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to MAX_I2C_SCLK +set_instance_assignment -name IO_STANDARD "1.8 V" -to MAX_I2C_SDAT +set_instance_assignment -name IO_STANDARD "2.5 V" -to OSC_50_BANK2 +set_instance_assignment -name IO_STANDARD "1.8 V" -to OSC_50_BANK3 +set_instance_assignment -name IO_STANDARD "1.8 V" -to OSC_50_BANK4 +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to OSC_50_BANK5 +set_instance_assignment -name IO_STANDARD "2.5 V" -to OSC_50_BANK6 +set_instance_assignment -name IO_STANDARD "1.8 V" -to OSC_50_BANK7 +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_A[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_A[10] +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_A[11] +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_A[12] +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_A[13] +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_A[14] +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_A[15] +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_A[16] +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_A[17] +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_A[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_A[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_A[4] +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_A[5] +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_A[6] +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_A[7] +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_A[8] +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_A[9] +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_CS_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[10] +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[11] +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[12] +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[13] +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[14] +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[15] +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[16] +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[17] +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[18] +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[19] +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[20] +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[21] +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[22] +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[23] +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[24] +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[25] +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[26] +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[27] +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[28] +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[29] +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[30] +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[31] +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[4] +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[5] +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[6] +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[7] +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[8] +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_D[9] +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_DC_DACK +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_DC_DREQ +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_DC_IRQ +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_HC_DACK +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_HC_DREQ +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_HC_IRQ +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_OE_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_RESET_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to OTG_WE_n +set_instance_assignment -name IO_STANDARD "2.5 V" -to PCIE_PREST_n +set_instance_assignment -name IO_STANDARD HCSL -to PCIE_REFCLK_p +set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_RX_p[0] +set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_RX_p[1] +set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_RX_p[2] +set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_RX_p[3] +set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_RX_p[4] +set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_RX_p[5] +set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_RX_p[6] +set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_RX_p[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to PCIE_SMBCLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to PCIE_SMBDAT +set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_TX_p[0] +set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_TX_p[1] +set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_TX_p[2] +set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_TX_p[3] +set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_TX_p[4] +set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_TX_p[5] +set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_TX_p[6] +set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to PCIE_TX_p[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to PCIE_WAKE_n +set_instance_assignment -name IO_STANDARD LVDS -to PLL_CLKIN_p +set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SATA_DEVICE_RX_p[0] +set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SATA_DEVICE_RX_p[1] +set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SATA_DEVICE_TX_p[0] +set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SATA_DEVICE_TX_p[1] +set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SATA_HOST_RX_p[0] +set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SATA_HOST_RX_p[1] +set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SATA_HOST_TX_p[0] +set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SATA_HOST_TX_p[1] +set_instance_assignment -name IO_STANDARD LVDS -to SATA_REFCLK_p +set_instance_assignment -name IO_STANDARD "1.8 V" -to SD_CLK +set_instance_assignment -name IO_STANDARD "1.8 V" -to SD_CMD +set_instance_assignment -name IO_STANDARD "1.8 V" -to SD_DAT[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to SD_DAT[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to SD_DAT[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to SD_DAT[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to SD_WP_n +set_instance_assignment -name IO_STANDARD "2.5 V" -to SEG0_D[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SEG0_D[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SEG0_D[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SEG0_D[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SEG0_D[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SEG0_D[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SEG0_D[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SEG0_DP +set_instance_assignment -name IO_STANDARD "2.5 V" -to SEG1_D[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SEG1_D[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SEG1_D[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SEG1_D[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SEG1_D[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SEG1_D[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SEG1_D[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SEG1_DP +set_instance_assignment -name IO_STANDARD "2.5 V" -to SLIDE_SW[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SLIDE_SW[1] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to SLIDE_SW[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SLIDE_SW[3] +set_instance_assignment -name IO_STANDARD LVDS -to SMA_CLKIN_p +set_instance_assignment -name IO_STANDARD LVDS -to SMA_CLKOUT_p +set_instance_assignment -name IO_STANDARD LVDS -to SMA_GXBCLK_p +set_instance_assignment -name IO_STANDARD "2.5 V" -to SSRAM_ADV +set_instance_assignment -name IO_STANDARD "2.5 V" -to SSRAM_BWA_n +set_instance_assignment -name IO_STANDARD "2.5 V" -to SSRAM_BWB_n +set_instance_assignment -name IO_STANDARD "2.5 V" -to SSRAM_CE_n +set_instance_assignment -name IO_STANDARD "2.5 V" -to SSRAM_CKE_n +set_instance_assignment -name IO_STANDARD "2.5 V" -to SSRAM_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to SSRAM_OE_n +set_instance_assignment -name IO_STANDARD "2.5 V" -to SSRAM_WE_n +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to SW[0] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to SW[1] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to SW[2] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to SW[3] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to SW[4] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to SW[5] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to SW[6] +set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to SW[7] +set_instance_assignment -name IO_STANDARD "1.8 V" -to TEMP_INT_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to TEMP_SMCLK +set_instance_assignment -name IO_STANDARD "1.8 V" -to TEMP_SMDAT +set_instance_assignment -name IO_STANDARD "2.5 V" -to UART_CTS +set_instance_assignment -name IO_STANDARD "2.5 V" -to UART_RTS +set_instance_assignment -name IO_STANDARD "2.5 V" -to UART_RXD +set_instance_assignment -name IO_STANDARD "2.5 V" -to UART_TXD + + + + + +#============================================================ +# End of pin assignments by Terasic System Builder +#============================================================ + + +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_global_assignment -name MISC_FILE "C:/Documents and Settings/user/DE4_GOLDEN_TOP/DE4_GOLDEN_TOP/DE4_GOLDEN_TOP.dpf" +set_global_assignment -name SEARCH_PATH ddr2 + +#============================================================ +# DDR2 DIM1 setting +#============================================================ + +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_odt[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_odt[0] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_odt[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_odt[1] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M1_DDR2_clk[0] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_clk[0] +set_instance_assignment -name TREAT_BIDIR_AS_OUTPUT ON -to M1_DDR2_clk[1] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M1_DDR2_clk[1] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_clk[1] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M1_DDR2_clk_n[0] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_clk_n[0] +set_instance_assignment -name TREAT_BIDIR_AS_OUTPUT ON -to M1_DDR2_clk_n[1] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M1_DDR2_clk_n[1] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_clk_n[1] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_cs_n[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_cs_n[0] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_cs_n[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_cs_n[1] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_cke[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_cke[0] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_cke[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_cke[1] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_addr[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_addr[0] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_addr[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_addr[1] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_addr[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_addr[2] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_addr[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_addr[3] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_addr[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_addr[4] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_addr[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_addr[5] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_addr[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_addr[6] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_addr[7] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_addr[7] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_addr[8] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_addr[8] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_addr[9] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_addr[9] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_addr[10] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_addr[10] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_addr[11] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_addr[11] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_addr[12] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_addr[12] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_addr[13] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_addr[13] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_addr[14] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_addr[14] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_ba[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_ba[0] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_ba[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_ba[1] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_ba[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_ba[2] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_ras_n +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_ras_n +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_cas_n +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_cas_n +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_we_n +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M1_DDR2_we_n +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[0] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[0] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[0] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[1] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[1] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[1] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[2] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[2] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[2] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[3] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[3] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[3] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[4] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[4] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[4] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[5] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[5] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[5] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[6] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[6] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[6] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[7] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[7] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[7] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[8] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[8] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[8] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[9] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[9] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[9] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[10] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[10] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[10] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[11] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[11] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[11] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[12] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[12] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[12] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[13] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[13] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[13] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[14] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[14] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[14] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[15] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[15] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[15] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[16] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[16] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[16] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[17] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[17] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[17] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[18] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[18] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[18] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[19] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[19] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[19] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[20] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[20] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[20] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[21] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[21] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[21] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[22] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[22] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[22] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[23] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[23] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[23] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[24] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[24] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[24] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[25] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[25] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[25] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[26] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[26] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[26] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[27] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[27] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[27] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[28] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[28] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[28] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[29] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[29] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[29] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[30] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[30] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[30] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[31] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[31] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[31] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[32] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[32] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[32] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[33] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[33] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[33] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[34] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[34] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[34] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[35] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[35] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[35] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[36] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[36] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[36] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[37] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[37] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[37] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[38] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[38] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[38] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[39] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[39] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[39] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[40] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[40] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[40] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[41] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[41] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[41] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[42] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[42] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[42] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[43] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[43] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[43] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[44] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[44] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[44] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[45] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[45] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[45] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[46] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[46] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[46] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[47] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[47] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[47] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[48] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[48] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[48] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[49] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[49] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[49] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[50] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[50] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[50] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[51] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[51] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[51] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[52] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[52] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[52] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[53] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[53] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[53] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[54] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[54] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[54] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[55] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[55] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[55] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[56] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[56] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[56] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[57] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[57] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[57] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[58] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[58] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[58] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[59] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[59] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[59] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[60] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[60] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[60] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[61] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[61] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[61] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[62] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[62] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[62] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dq[63] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[63] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dq[63] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M1_DDR2_dqs[0] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dqs[0] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dqs[0] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M1_DDR2_dqs[1] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dqs[1] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dqs[1] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M1_DDR2_dqs[2] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dqs[2] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dqs[2] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M1_DDR2_dqs[3] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dqs[3] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dqs[3] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M1_DDR2_dqs[4] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dqs[4] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dqs[4] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M1_DDR2_dqs[5] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dqs[5] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dqs[5] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M1_DDR2_dqs[6] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dqs[6] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dqs[6] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M1_DDR2_dqs[7] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dqs[7] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dqs[7] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M1_DDR2_dqsn[0] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dqsn[0] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dqsn[0] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M1_DDR2_dqsn[1] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dqsn[1] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dqsn[1] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M1_DDR2_dqsn[2] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dqsn[2] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dqsn[2] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M1_DDR2_dqsn[3] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dqsn[3] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dqsn[3] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M1_DDR2_dqsn[4] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dqsn[4] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dqsn[4] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M1_DDR2_dqsn[5] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dqsn[5] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dqsn[5] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M1_DDR2_dqsn[6] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dqsn[6] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dqsn[6] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M1_DDR2_dqsn[7] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dqsn[7] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M1_DDR2_dqsn[7] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dm[0] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dm[0] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dm[1] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dm[1] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dm[2] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dm[2] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dm[3] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dm[3] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dm[4] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dm[4] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dm[5] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dm[5] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dm[6] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dm[6] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M1_DDR2_dm[7] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M1_DDR2_dm[7] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[0] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[1] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[2] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[3] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[4] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[5] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[6] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[7] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[8] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[9] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[10] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[11] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[12] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[13] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[14] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[15] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[16] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[17] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[18] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[19] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[20] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[21] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[22] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[23] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[24] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[25] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[26] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[27] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[28] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[29] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[30] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[31] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[32] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[33] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[34] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[35] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[36] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[37] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[38] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[39] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[40] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[41] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[42] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[43] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[44] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[45] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[46] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[47] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[48] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[49] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[50] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[51] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[52] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[53] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[54] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[55] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[56] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[57] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[58] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[59] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[60] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[61] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[62] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dq[63] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dqs[0] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dqs[1] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dqs[2] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dqs[3] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dqs[4] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dqs[5] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dqs[6] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dqs[7] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dqsn[0] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dqsn[1] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dqsn[2] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dqsn[3] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dqsn[4] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dqsn[5] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dqsn[6] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dqsn[7] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dm[0] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dm[1] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dm[2] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dm[3] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dm[4] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dm[5] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dm[6] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to M1_DDR2_dm[7] +set_instance_assignment -name DQ_GROUP 9 -from M1_DDR2_dqs[0] -to M1_DDR2_dq[0..7] +set_instance_assignment -name DQ_GROUP 9 -from M1_DDR2_dqs[0] -to M1_DDR2_dm[0] +set_instance_assignment -name DQSB_DQS_PAIR ON -from M1_DDR2_dqsn[0] -to M1_DDR2_dqs[0] +set_instance_assignment -name DQ_GROUP 9 -from M1_DDR2_dqs[1] -to M1_DDR2_dq[8..15] +set_instance_assignment -name DQ_GROUP 9 -from M1_DDR2_dqs[1] -to M1_DDR2_dm[1] +set_instance_assignment -name DQSB_DQS_PAIR ON -from M1_DDR2_dqsn[1] -to M1_DDR2_dqs[1] +set_instance_assignment -name DQ_GROUP 9 -from M1_DDR2_dqs[2] -to M1_DDR2_dq[16..23] +set_instance_assignment -name DQ_GROUP 9 -from M1_DDR2_dqs[2] -to M1_DDR2_dm[2] +set_instance_assignment -name DQSB_DQS_PAIR ON -from M1_DDR2_dqsn[2] -to M1_DDR2_dqs[2] +set_instance_assignment -name DQ_GROUP 9 -from M1_DDR2_dqs[3] -to M1_DDR2_dq[24..31] +set_instance_assignment -name DQ_GROUP 9 -from M1_DDR2_dqs[3] -to M1_DDR2_dm[3] +set_instance_assignment -name DQSB_DQS_PAIR ON -from M1_DDR2_dqsn[3] -to M1_DDR2_dqs[3] +set_instance_assignment -name DQ_GROUP 9 -from M1_DDR2_dqs[4] -to M1_DDR2_dq[32..39] +set_instance_assignment -name DQ_GROUP 9 -from M1_DDR2_dqs[4] -to M1_DDR2_dm[4] +set_instance_assignment -name DQSB_DQS_PAIR ON -from M1_DDR2_dqsn[4] -to M1_DDR2_dqs[4] +set_instance_assignment -name DQ_GROUP 9 -from M1_DDR2_dqs[5] -to M1_DDR2_dq[40..47] +set_instance_assignment -name DQ_GROUP 9 -from M1_DDR2_dqs[5] -to M1_DDR2_dm[5] +set_instance_assignment -name DQSB_DQS_PAIR ON -from M1_DDR2_dqsn[5] -to M1_DDR2_dqs[5] +set_instance_assignment -name DQ_GROUP 9 -from M1_DDR2_dqs[6] -to M1_DDR2_dq[48..55] +set_instance_assignment -name DQ_GROUP 9 -from M1_DDR2_dqs[6] -to M1_DDR2_dm[6] +set_instance_assignment -name DQSB_DQS_PAIR ON -from M1_DDR2_dqsn[6] -to M1_DDR2_dqs[6] +set_instance_assignment -name DQ_GROUP 9 -from M1_DDR2_dqs[7] -to M1_DDR2_dq[56..63] +set_instance_assignment -name DQ_GROUP 9 -from M1_DDR2_dqs[7] -to M1_DDR2_dm[7] +set_instance_assignment -name DQSB_DQS_PAIR ON -from M1_DDR2_dqsn[7] -to M1_DDR2_dqs[7] + +#============================================================ +# DDR2 DIM2 setting +#============================================================ +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_odt[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_odt[0] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_odt[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_odt[1] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M2_DDR2_clk[0] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_clk[0] +set_instance_assignment -name TREAT_BIDIR_AS_OUTPUT ON -to M2_DDR2_clk[1] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M2_DDR2_clk[1] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_clk[1] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M2_DDR2_clk_n[0] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_clk_n[0] +set_instance_assignment -name TREAT_BIDIR_AS_OUTPUT ON -to M2_DDR2_clk_n[1] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M2_DDR2_clk_n[1] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_clk_n[1] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_cs_n[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_cs_n[0] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_cs_n[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_cs_n[1] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_cke[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_cke[0] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_cke[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_cke[1] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_addr[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_addr[0] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_addr[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_addr[1] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_addr[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_addr[2] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_addr[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_addr[3] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_addr[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_addr[4] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_addr[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_addr[5] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_addr[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_addr[6] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_addr[7] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_addr[7] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_addr[8] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_addr[8] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_addr[9] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_addr[9] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_addr[10] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_addr[10] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_addr[11] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_addr[11] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_addr[12] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_addr[12] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_addr[13] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_addr[13] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_addr[14] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_addr[14] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_ba[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_ba[0] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_ba[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_ba[1] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_ba[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_ba[2] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_ras_n +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_ras_n +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_cas_n +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_cas_n +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_we_n +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to M2_DDR2_we_n +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[0] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[0] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[0] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[1] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[1] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[1] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[2] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[2] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[2] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[3] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[3] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[3] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[4] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[4] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[4] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[5] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[5] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[5] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[6] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[6] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[6] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[7] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[7] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[7] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[8] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[8] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[8] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[9] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[9] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[9] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[10] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[10] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[10] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[11] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[11] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[11] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[12] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[12] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[12] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[13] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[13] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[13] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[14] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[14] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[14] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[15] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[15] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[15] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[16] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[16] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[16] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[17] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[17] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[17] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[18] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[18] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[18] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[19] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[19] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[19] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[20] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[20] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[20] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[21] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[21] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[21] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[22] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[22] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[22] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[23] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[23] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[23] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[24] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[24] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[24] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[25] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[25] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[25] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[26] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[26] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[26] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[27] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[27] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[27] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[28] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[28] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[28] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[29] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[29] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[29] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[30] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[30] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[30] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[31] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[31] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[31] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[32] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[32] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[32] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[33] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[33] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[33] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[34] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[34] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[34] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[35] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[35] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[35] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[36] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[36] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[36] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[37] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[37] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[37] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[38] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[38] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[38] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[39] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[39] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[39] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[40] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[40] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[40] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[41] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[41] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[41] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[42] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[42] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[42] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[43] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[43] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[43] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[44] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[44] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[44] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[45] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[45] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[45] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[46] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[46] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[46] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[47] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[47] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[47] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[48] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[48] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[48] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[49] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[49] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[49] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[50] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[50] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[50] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[51] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[51] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[51] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[52] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[52] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[52] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[53] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[53] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[53] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[54] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[54] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[54] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[55] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[55] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[55] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[56] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[56] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[56] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[57] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[57] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[57] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[58] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[58] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[58] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[59] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[59] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[59] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[60] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[60] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[60] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[61] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[61] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[61] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[62] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[62] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[62] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dq[63] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[63] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dq[63] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M2_DDR2_dqs[0] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dqs[0] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dqs[0] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M2_DDR2_dqs[1] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dqs[1] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dqs[1] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M2_DDR2_dqs[2] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dqs[2] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dqs[2] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M2_DDR2_dqs[3] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dqs[3] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dqs[3] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M2_DDR2_dqs[4] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dqs[4] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dqs[4] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M2_DDR2_dqs[5] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dqs[5] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dqs[5] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M2_DDR2_dqs[6] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dqs[6] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dqs[6] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M2_DDR2_dqs[7] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dqs[7] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dqs[7] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M2_DDR2_dqsn[0] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dqsn[0] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dqsn[0] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M2_DDR2_dqsn[1] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dqsn[1] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dqsn[1] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M2_DDR2_dqsn[2] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dqsn[2] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dqsn[2] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M2_DDR2_dqsn[3] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dqsn[3] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dqsn[3] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M2_DDR2_dqsn[4] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dqsn[4] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dqsn[4] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M2_DDR2_dqsn[5] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dqsn[5] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dqsn[5] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M2_DDR2_dqsn[6] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dqsn[6] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dqsn[6] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to M2_DDR2_dqsn[7] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dqsn[7] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to M2_DDR2_dqsn[7] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dm[0] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dm[0] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dm[1] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dm[1] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dm[2] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dm[2] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dm[3] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dm[3] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dm[4] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dm[4] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dm[5] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dm[5] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dm[6] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dm[6] +set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to M2_DDR2_dm[7] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to M2_DDR2_dm[7] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[0] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[1] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[2] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[3] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[4] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[5] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[6] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[7] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[8] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[9] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[10] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[11] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[12] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[13] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[14] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[15] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[16] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[17] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[18] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[19] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[20] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[21] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[22] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[23] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[24] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[25] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[26] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[27] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[28] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[29] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[30] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[31] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[32] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[33] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[34] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[35] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[36] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[37] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[38] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[39] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[40] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[41] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[42] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[43] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[44] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[45] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[46] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[47] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[48] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[49] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[50] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[51] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[52] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[53] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[54] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[55] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[56] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[57] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[58] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[59] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[60] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[61] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[62] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dq[63] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dqs[0] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dqs[1] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dqs[2] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dqs[3] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dqs[4] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dqs[5] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dqs[6] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dqs[7] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dqsn[0] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dqsn[1] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dqsn[2] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dqsn[3] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dqsn[4] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dqsn[5] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dqsn[6] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dqsn[7] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dm[0] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dm[1] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dm[2] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dm[3] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dm[4] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dm[5] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dm[6] +set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078785 -to M2_DDR2_dm[7] +set_instance_assignment -name DQ_GROUP 9 -from M2_DDR2_dqs[0] -to M2_DDR2_dq[0..7] +set_instance_assignment -name DQ_GROUP 9 -from M2_DDR2_dqs[0] -to M2_DDR2_dm[0] +set_instance_assignment -name DQSB_DQS_PAIR ON -from M2_DDR2_dqsn[0] -to M2_DDR2_dqs[0] +set_instance_assignment -name DQ_GROUP 9 -from M2_DDR2_dqs[1] -to M2_DDR2_dq[8..15] +set_instance_assignment -name DQ_GROUP 9 -from M2_DDR2_dqs[1] -to M2_DDR2_dm[1] +set_instance_assignment -name DQSB_DQS_PAIR ON -from M2_DDR2_dqsn[1] -to M2_DDR2_dqs[1] +set_instance_assignment -name DQ_GROUP 9 -from M2_DDR2_dqs[2] -to M2_DDR2_dq[16..23] +set_instance_assignment -name DQ_GROUP 9 -from M2_DDR2_dqs[2] -to M2_DDR2_dm[2] +set_instance_assignment -name DQSB_DQS_PAIR ON -from M2_DDR2_dqsn[2] -to M2_DDR2_dqs[2] +set_instance_assignment -name DQ_GROUP 9 -from M2_DDR2_dqs[3] -to M2_DDR2_dq[24..31] +set_instance_assignment -name DQ_GROUP 9 -from M2_DDR2_dqs[3] -to M2_DDR2_dm[3] +set_instance_assignment -name DQSB_DQS_PAIR ON -from M2_DDR2_dqsn[3] -to M2_DDR2_dqs[3] +set_instance_assignment -name DQ_GROUP 9 -from M2_DDR2_dqs[4] -to M2_DDR2_dq[32..39] +set_instance_assignment -name DQ_GROUP 9 -from M2_DDR2_dqs[4] -to M2_DDR2_dm[4] +set_instance_assignment -name DQSB_DQS_PAIR ON -from M2_DDR2_dqsn[4] -to M2_DDR2_dqs[4] +set_instance_assignment -name DQ_GROUP 9 -from M2_DDR2_dqs[5] -to M2_DDR2_dq[40..47] +set_instance_assignment -name DQ_GROUP 9 -from M2_DDR2_dqs[5] -to M2_DDR2_dm[5] +set_instance_assignment -name DQSB_DQS_PAIR ON -from M2_DDR2_dqsn[5] -to M2_DDR2_dqs[5] +set_instance_assignment -name DQ_GROUP 9 -from M2_DDR2_dqs[6] -to M2_DDR2_dq[48..55] +set_instance_assignment -name DQ_GROUP 9 -from M2_DDR2_dqs[6] -to M2_DDR2_dm[6] +set_instance_assignment -name DQSB_DQS_PAIR ON -from M2_DDR2_dqsn[6] -to M2_DDR2_dqs[6] +set_instance_assignment -name DQ_GROUP 9 -from M2_DDR2_dqs[7] -to M2_DDR2_dq[56..63] +set_instance_assignment -name DQ_GROUP 9 -from M2_DDR2_dqs[7] -to M2_DDR2_dm[7] +set_instance_assignment -name DQSB_DQS_PAIR ON -from M2_DDR2_dqsn[7] -to M2_DDR2_dqs[7] + +#============================================================ +# END +#============================================================ +set_global_assignment -name MISC_FILE "G:/projet/de4/dev_2/DE4_GOLDEN_TOP/DE4_GOLDEN_TOP.dpf" +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" +set_global_assignment -name MISC_FILE "G:/projet/de4/test/de4_golden_top/DE4_GOLDEN_TOP.dpf" + +set_global_assignment -name MISC_FILE "D:/project/TW/de4/trunk/test/de4_golden_top/DE4_GOLDEN_TOP.dpf" +set_global_assignment -name MISC_FILE "D:/project_bei/de4/trunk/test/de4_golden_top/DE4_GOLDEN_TOP.dpf" +set_location_assignment PIN_AA35 -to HSMA_CLKIN_n1 +set_location_assignment PIN_AE35 -to HSMA_CLKIN_n2 +set_location_assignment PIN_AC10 -to HSMA_CLKIN_p1 +set_location_assignment PIN_W35 -to HSMB_CLKIN_n1 +set_location_assignment PIN_W5 -to HSMB_CLKIN_n2 +set_location_assignment PIN_W34 -to HSMB_CLKIN_p1 +set_location_assignment PIN_W6 -to HSMB_CLKIN_p2 +set_location_assignment PIN_AF34 -to HSMA_CLKIN_p2 +set_location_assignment PIN_AK13 -to CSENSE_ADC_FO +set_instance_assignment -name IO_STANDARD "1.8 V" -to CSENSE_ADC_FO +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_CLKIN_n1 +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_CLKIN_n2 +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_CLKIN_p1 +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMB_CLKIN_p2 +set_global_assignment -name MISC_FILE "D:/project/WH/de4/trunk/test/de4_golden_top/DE4_GOLDEN_TOP.dpf" +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_CLKIN_n1 +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_CLKIN_n2 +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_CLKIN_p1 +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMA_CLKIN_p2 +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name SDC_FILE DE4_GOLDEN_TOP.SDC +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top + + + + +set_global_assignment -name TOP_LEVEL_ENTITY emulator_top + + +set_global_assignment -name VERILOG_FILE src/jtag_wb/vjtag_wb.v +set_global_assignment -name VERILOG_FILE src/jtag_wb/vjtag.v +set_global_assignment -name VERILOG_FILE src/jtag_wb/jtag_system_en.v +set_global_assignment -name VERILOG_FILE src/jtag_wb/jtag_source_probe.v +set_global_assignment -name VERILOG_FILE src/src_noc/vc_alloc_request_gen.v +set_global_assignment -name VERILOG_FILE src/src_noc/traffic_gen_old.v +set_global_assignment -name VERILOG_FILE src/src_noc/traffic_gen.v +set_global_assignment -name VERILOG_FILE src/src_noc/ss_allocator.v +set_global_assignment -name VERILOG_FILE src/src_noc/routing.v +set_global_assignment -name VERILOG_FILE src/src_noc/router.v +set_global_assignment -name VERILOG_FILE src/src_noc/route_torus.v +set_global_assignment -name VERILOG_FILE src/src_noc/route_mesh.v +set_global_assignment -name VERILOG_FILE src/src_noc/noc.v +set_global_assignment -name VERILOG_FILE src/src_noc/main_comp.v +set_global_assignment -name VERILOG_FILE src/src_noc/input_ports.v +set_global_assignment -name VERILOG_FILE src/src_noc/inout_ports.v +set_global_assignment -name VERILOG_FILE src/src_noc/flit_buffer.v +set_global_assignment -name VERILOG_FILE src/src_noc/crossbar.v +set_global_assignment -name VERILOG_FILE src/src_noc/credit_count.v +set_global_assignment -name VERILOG_FILE src/src_noc/congestion_analyzer.v +set_global_assignment -name VERILOG_FILE src/src_noc/combined_vc_sw_alloc.v +set_global_assignment -name VERILOG_FILE src/src_noc/comb_spec2.v +set_global_assignment -name VERILOG_FILE src/src_noc/comb_nonspec.v +set_global_assignment -name VERILOG_FILE "src/src_noc/comb-spec1.v" +set_global_assignment -name VERILOG_FILE src/src_noc/class_table.v +set_global_assignment -name VERILOG_FILE src/src_noc/canonical_credit_count.v +set_global_assignment -name VERILOG_FILE src/src_noc/baseline.v +set_global_assignment -name VERILOG_FILE src/src_noc/arbiter.v +set_global_assignment -name VERILOG_FILE src/src_noc/agent.v +set_global_assignment -name VERILOG_FILE src/reset_jtag.v +set_global_assignment -name VERILOG_FILE src/noc_emulator.v +set_global_assignment -name VERILOG_FILE src/generic_ram.v +set_global_assignment -name VERILOG_FILE src/emulator_top.v +set_global_assignment -name VERILOG_FILE src/altera_reset_synchronizer.v + + + + + + + + + + + +
mpsoc/src_emulate/fpga/DE4_230/DE4_230.qsf Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: mpsoc/src_emulate/fpga/DE4_230/DE4_230.sdc =================================================================== --- mpsoc/src_emulate/fpga/DE4_230/DE4_230.sdc (nonexistent) +++ mpsoc/src_emulate/fpga/DE4_230/DE4_230.sdc (revision 28) @@ -0,0 +1,83 @@ +#************************************************************** +# This .sbc file is created by Terasic Tool. +# Users are recommended to modify this file to match users logic. +#************************************************************** + +#************************************************************** +# Create Clock +#************************************************************** + +#************************************************************** +# Create Generated Clock +#************************************************************** +derive_pll_clocks + + + +#************************************************************** +# Set Clock Latency +#************************************************************** + + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** +derive_clock_uncertainty + + + +#************************************************************** +# Set Input Delay +#************************************************************** + + + +#************************************************************** +# Set Output Delay +#************************************************************** + + + +#************************************************************** +# Set Clock Groups +#************************************************************** + + + +#************************************************************** +# Set False Path +#************************************************************** + + + +#************************************************************** +# Set Multicycle Path +#************************************************************** + + + +#************************************************************** +# Set Maximum Delay +#************************************************************** + + + +#************************************************************** +# Set Minimum Delay +#************************************************************** + + + +#************************************************************** +# Set Input Transition +#************************************************************** + + + +#************************************************************** +# Set Load +#************************************************************** + + +
mpsoc/src_emulate/fpga/DE4_230/DE4_230.sdc Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: mpsoc/src_emulate/fpga/DE4_230/src/altera_reset_synchronizer.v =================================================================== --- mpsoc/src_emulate/fpga/DE4_230/src/altera_reset_synchronizer.v (nonexistent) +++ mpsoc/src_emulate/fpga/DE4_230/src/altera_reset_synchronizer.v (revision 28) @@ -0,0 +1,87 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $ +// $Revision: #1 $ +// $Date: 2013/02/11 $ +// $Author: swbranch $ + +// ----------------------------------------------- +// Reset Synchronizer +// ----------------------------------------------- +`timescale 1 ns / 1 ns + +module altera_reset_synchronizer +#( + parameter ASYNC_RESET = 1, + parameter DEPTH = 2 +) +( + input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */, + + input clk, + output reset_out +); + + // ----------------------------------------------- + // Synchronizer register chain. We cannot reuse the + // standard synchronizer in this implementation + // because our timing constraints are different. + // + // Instead of cutting the timing path to the d-input + // on the first flop we need to cut the aclr input. + // + // We omit the "preserve" attribute on the final + // output register, so that the synthesis tool can + // duplicate it where needed. + // ----------------------------------------------- + (*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain; + reg altera_reset_synchronizer_int_chain_out; + + generate if (ASYNC_RESET) begin + + // ----------------------------------------------- + // Assert asynchronously, deassert synchronously. + // ----------------------------------------------- + always @(posedge clk or posedge reset_in) begin + if (reset_in) begin + altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}}; + altera_reset_synchronizer_int_chain_out <= 1'b1; + end + else begin + altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; + altera_reset_synchronizer_int_chain[DEPTH-1] <= 0; + altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; + end + end + + assign reset_out = altera_reset_synchronizer_int_chain_out; + + end else begin + + // ----------------------------------------------- + // Assert synchronously, deassert synchronously. + // ----------------------------------------------- + always @(posedge clk) begin + altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; + altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in; + altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; + end + + assign reset_out = altera_reset_synchronizer_int_chain_out; + + end + endgenerate + +endmodule +
mpsoc/src_emulate/fpga/DE4_230/src/altera_reset_synchronizer.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: mpsoc/src_emulate/fpga/DE4_230/src/emulator_top.v =================================================================== --- mpsoc/src_emulate/fpga/DE4_230/src/emulator_top.v (nonexistent) +++ mpsoc/src_emulate/fpga/DE4_230/src/emulator_top.v (revision 28) @@ -0,0 +1,160 @@ +module emulator_top +( + +//////// CLOCK ////////// + OSC_50_BANK2, + OSC_50_BANK3, + OSC_50_BANK4, + OSC_50_BANK5, + OSC_50_BANK6, + OSC_50_BANK7, + + //////// CPU RESET ////////// + CPU_RESET_n, + + + //////// LED x 8 ////////// + LED, + + //////// BUTTON x 4 ////////// + BUTTON, + + //////// SWITCH x 8 ////////// + SW, + + //////// SLIDE SWITCH x 4 ////////// + SLIDE_SW + + +); + + + + //////////// CLOCK ////////// + input OSC_50_BANK2; + input OSC_50_BANK3; + input OSC_50_BANK4; + input OSC_50_BANK5; + input OSC_50_BANK6; + input OSC_50_BANK7; + + + //////// CPU RESET ////////// + input CPU_RESET_n; + + + + //////////// LED x 8 ////////// + output [7:0] LED; + + //////////// BUTTON x 4 ////////// + input [3:0] BUTTON; + + //////////// SWITCH x 8 ////////// + input [7:0] SW; + + //////////// SLIDE SWITCH x 4 ////////// + input [3:0] SLIDE_SW; + + + + + + + + + + //NoC parameters will be defined by user + `define NOC_PARAM + `include "noc_parameters.v" + + + + wire clk, reset, reset_noc, reset_injector, reset_noc_sync, reset_injector_sync, done; + wire jtag_reset_injector, jtag_reset_noc; + + + + assign clk = OSC_50_BANK2; + assign reset = ~CPU_RESET_n; + assign LED[0] = ~done; + assign LED[1] = ~reset_noc; + assign LED[2] = ~reset_injector; + assign LED[7:3] = 5'b11111; + + + assign reset = (jtag_reset | reset_in); + + reg[31:0]time_cnt; + + // two reset sources which can be controled using jtag. One for reseting NoC another packet injectors + jtag_source_probe #( + .VJTAG_INDEX(127), + .Dw(2) //source/probe width in bits + )the_reset( + .probe({1'b0,done}), + .source({jtag_reset_injector,jtag_reset_noc}) + ); + + + assign reset_noc = (jtag_reset_noc | reset); + assign reset_injector = (jtag_reset_injector | reset); + + altera_reset_synchronizer noc_rst_sync + ( + .reset_in(reset_noc), + .clk(clk), + .reset_out(reset_noc_sync) + ); + + + altera_reset_synchronizer inject_rst_sync + ( + .reset_in(reset_injector), + .clk(clk), + .reset_out(reset_injector_sync) + ); + + + + noc_emulator #( + `include "pass_parameters.v" + + ) + noc_emulate_top + ( + .reset(reset_noc_sync), + .jtag_ctrl_reset(reset_injector_sync), + .clk(clk), + .done(done) + ); + + + jtag_source_probe #( + .VJTAG_INDEX(126), + .Dw(32) //source/probe width in bits + + + ) + src_pb + ( + .probe(time_cnt), + .source() + ); + + + always @(posedge clk or posedge reset)begin + if(reset) begin + time_cnt<=0; + end else begin + if(!done) time_cnt<=time_cnt+1; + end + end + + + + +endmodule + + +
mpsoc/src_emulate/fpga/DE4_230/src/emulator_top.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: mpsoc/src_emulate/fpga/DE4_230/src/reset_jtag.v =================================================================== --- mpsoc/src_emulate/fpga/DE4_230/src/reset_jtag.v (nonexistent) +++ mpsoc/src_emulate/fpga/DE4_230/src/reset_jtag.v (revision 28) @@ -0,0 +1,107 @@ +// megafunction wizard: %In-System Sources and Probes% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsource_probe + +// ============================================================ +// File Name: reset_jtag.v +// Megafunction Name(s): +// altsource_probe +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.0.0 Build 156 04/24/2013 SJ Full Version +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module reset_jtag ( + probe, + source); + + input [0:0] probe; + output [0:0] source; + + wire [0:0] sub_wire0; + wire [0:0] source = sub_wire0[0:0]; + + altsource_probe altsource_probe_component ( + .probe (probe), + .source (sub_wire0) + // synopsys translate_off + , + .clrn (), + .ena (), + .ir_in (), + .ir_out (), + .jtag_state_cdr (), + .jtag_state_cir (), + .jtag_state_e1dr (), + .jtag_state_sdr (), + .jtag_state_tlr (), + .jtag_state_udr (), + .jtag_state_uir (), + .raw_tck (), + .source_clk (), + .source_ena (), + .tdi (), + .tdo (), + .usr1 () + // synopsys translate_on + ); + defparam + altsource_probe_component.enable_metastability = "NO", + altsource_probe_component.instance_id = "RST", + altsource_probe_component.probe_width = 1, + altsource_probe_component.sld_auto_instance_index = "NO", + altsource_probe_component.sld_instance_index = 127, + altsource_probe_component.source_initial_value = " 0", + altsource_probe_component.source_width = 1; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: ENABLE_METASTABILITY STRING "NO" +// Retrieval info: CONSTANT: INSTANCE_ID STRING "RST" +// Retrieval info: CONSTANT: PROBE_WIDTH NUMERIC "1" +// Retrieval info: CONSTANT: SLD_AUTO_INSTANCE_INDEX STRING "NO" +// Retrieval info: CONSTANT: SLD_INSTANCE_INDEX NUMERIC "127" +// Retrieval info: CONSTANT: SOURCE_INITIAL_VALUE STRING " 0" +// Retrieval info: CONSTANT: SOURCE_WIDTH NUMERIC "1" +// Retrieval info: USED_PORT: probe 0 0 1 0 INPUT NODEFVAL "probe[0..0]" +// Retrieval info: USED_PORT: source 0 0 1 0 OUTPUT NODEFVAL "source[0..0]" +// Retrieval info: CONNECT: @probe 0 0 1 0 probe 0 0 1 0 +// Retrieval info: CONNECT: source 0 0 1 0 @source 0 0 1 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL reset_jtag.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL reset_jtag.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL reset_jtag.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL reset_jtag.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL reset_jtag_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL reset_jtag_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf
mpsoc/src_emulate/fpga/DE4_230/src/reset_jtag.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: mpsoc/src_emulate/fpga/De2-115/De2-115.inf =================================================================== --- mpsoc/src_emulate/fpga/De2-115/De2-115.inf (nonexistent) +++ mpsoc/src_emulate/fpga/De2-115/De2-115.inf (revision 28) @@ -0,0 +1,12 @@ +####################################################################### +## File: De2-115.inf +## +## Copyright (C) 2014-2016 Alireza Monemi +## +## This file is part of ProNoC 1.5.0 +## +############################################################################### + +$board_info = { + 'device_name' => {'EP4CE115F29'} +};
mpsoc/src_emulate/fpga/De2-115/De2-115.inf Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: mpsoc/src_emulate/fpga/De2-115/De2-115.qsf =================================================================== --- mpsoc/src_emulate/fpga/De2-115/De2-115.qsf (revision 27) +++ mpsoc/src_emulate/fpga/De2-115/De2-115.qsf (revision 28) @@ -1271,39 +1271,39 @@ set_instance_assignment -name TSU_REQUIREMENT "10 ns" -from * -to * -set_global_assignment -name VERILOG_FILE src/vjtag_wb.v -set_global_assignment -name VERILOG_FILE src/vjtag.v + +set_global_assignment -name VERILOG_FILE src/jtag_wb/vjtag_wb.v +set_global_assignment -name VERILOG_FILE src/jtag_wb/vjtag.v +set_global_assignment -name VERILOG_FILE src/jtag_wb/jtag_system_en.v +set_global_assignment -name VERILOG_FILE src/jtag_wb/jtag_source_probe.v +set_global_assignment -name VERILOG_FILE src/src_noc/vc_alloc_request_gen.v +set_global_assignment -name VERILOG_FILE src/src_noc/traffic_gen_old.v +set_global_assignment -name VERILOG_FILE src/src_noc/traffic_gen.v +set_global_assignment -name VERILOG_FILE src/src_noc/ss_allocator.v +set_global_assignment -name VERILOG_FILE src/src_noc/routing.v +set_global_assignment -name VERILOG_FILE src/src_noc/router.v +set_global_assignment -name VERILOG_FILE src/src_noc/route_torus.v +set_global_assignment -name VERILOG_FILE src/src_noc/route_mesh.v +set_global_assignment -name VERILOG_FILE src/src_noc/noc.v +set_global_assignment -name VERILOG_FILE src/src_noc/main_comp.v +set_global_assignment -name VERILOG_FILE src/src_noc/input_ports.v +set_global_assignment -name VERILOG_FILE src/src_noc/inout_ports.v +set_global_assignment -name VERILOG_FILE src/src_noc/flit_buffer.v +set_global_assignment -name VERILOG_FILE src/src_noc/crossbar.v +set_global_assignment -name VERILOG_FILE src/src_noc/credit_count.v +set_global_assignment -name VERILOG_FILE src/src_noc/congestion_analyzer.v +set_global_assignment -name VERILOG_FILE src/src_noc/combined_vc_sw_alloc.v +set_global_assignment -name VERILOG_FILE src/src_noc/comb_spec2.v +set_global_assignment -name VERILOG_FILE src/src_noc/comb_nonspec.v +set_global_assignment -name VERILOG_FILE "src/src_noc/comb-spec1.v" +set_global_assignment -name VERILOG_FILE src/src_noc/class_table.v +set_global_assignment -name VERILOG_FILE src/src_noc/canonical_credit_count.v +set_global_assignment -name VERILOG_FILE src/src_noc/baseline.v +set_global_assignment -name VERILOG_FILE src/src_noc/arbiter.v +set_global_assignment -name VERILOG_FILE src/reset_jtag.v set_global_assignment -name VERILOG_FILE src/noc_emulator.v -set_global_assignment -name VERILOG_FILE src/jtag_system_en.v -set_global_assignment -name VERILOG_FILE src/ram_single_port_jtag.v -set_global_assignment -name VERILOG_FILE src/jtag_source_probe.v +set_global_assignment -name VERILOG_FILE src/generic_ram.v +set_global_assignment -name VERILOG_FILE src/emulator_top.v set_global_assignment -name VERILOG_FILE src/altera_reset_synchronizer.v -set_global_assignment -name VERILOG_FILE src/reset_jtag.v -set_global_assignment -name VERILOG_FILE src/vc_alloc_request_gen.v -set_global_assignment -name VERILOG_FILE src/traffic_gen_old.v -set_global_assignment -name VERILOG_FILE src/traffic_gen.v -set_global_assignment -name VERILOG_FILE src/ss_allocator.v -set_global_assignment -name VERILOG_FILE src/routing.v -set_global_assignment -name VERILOG_FILE src/router.v -set_global_assignment -name VERILOG_FILE src/route_torus.v -set_global_assignment -name VERILOG_FILE src/route_mesh.v -set_global_assignment -name VERILOG_FILE src/noc.v -set_global_assignment -name VERILOG_FILE src/main_comp.v -set_global_assignment -name VERILOG_FILE src/input_ports.v -set_global_assignment -name VERILOG_FILE src/inout_ports.v -set_global_assignment -name VERILOG_FILE src/flit_buffer.v -set_global_assignment -name VERILOG_FILE src/crossbar.v -set_global_assignment -name VERILOG_FILE src/credit_count.v -set_global_assignment -name VERILOG_FILE src/congestion_analyzer.v -set_global_assignment -name VERILOG_FILE src/combined_vc_sw_alloc.v -set_global_assignment -name VERILOG_FILE src/comb_spec2.v -set_global_assignment -name VERILOG_FILE src/comb_nonspec.v -set_global_assignment -name VERILOG_FILE "src/comb-spec1.v" -set_global_assignment -name VERILOG_FILE src/class_table.v -set_global_assignment -name VERILOG_FILE src/canonical_credit_count.v -set_global_assignment -name VERILOG_FILE src/baseline.v -set_global_assignment -name VERILOG_FILE src/arbiter.v -set_global_assignment -name VERILOG_FILE src/altera_noc_emulator.v -set_global_assignment -name VERILOG_FILE emulator_top.v -set_global_assignment -name QIP_FILE probe.qip + set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
/mpsoc/src_emulate/fpga/De2-115/src/emulator_top.v
0,0 → 1,103
module emulator_top (
output [0:0]LEDR,
output [1:0]LEDG,
input [0:0]KEY,
input CLOCK_50
);
 
//NoC parameters will be defined by user
`define NOC_PARAM
`include "noc_parameters.v"
 
 
wire clk, reset, reset_noc, reset_injector, reset_noc_sync, reset_injector_sync, done;
wire jtag_reset_injector, jtag_reset_noc;
assign clk = CLOCK_50;
assign reset = ~KEY[0];
assign LEDR[0] = done;
assign LEDG[0] = reset_noc;
assign LEDG[1] = reset_injector;
 
reg[31:0]time_cnt;
 
// two reset sources which can be controled using jtag. One for reseting NoC another packet injectors
jtag_source_probe #(
.VJTAG_INDEX(127),
.Dw(2) //source/probe width in bits
)the_reset(
.probe({1'b0,done}),
.source({jtag_reset_injector,jtag_reset_noc})
);
 
 
assign reset_noc = (jtag_reset_noc | reset);
assign reset_injector = (jtag_reset_injector | reset);
 
altera_reset_synchronizer noc_rst_sync
(
.reset_in(reset_noc),
.clk(clk),
.reset_out(reset_noc_sync)
);
 
 
altera_reset_synchronizer inject_rst_sync
(
.reset_in(reset_injector),
.clk(clk),
.reset_out(reset_injector_sync)
);
noc_emulator #(
`include "pass_parameters.v"
)
noc_emulate_top
(
.reset(reset_noc_sync),
.jtag_ctrl_reset(reset_injector_sync),
.clk(clk),
.done(done)
);
jtag_source_probe #(
.VJTAG_INDEX(126),
.Dw(32) //source/probe width in bits
)
src_pb
(
.probe(time_cnt),
.source()
);
always @(posedge clk or posedge reset)begin
if(reset) begin
time_cnt<=0;
end else begin
if(!done) time_cnt<=time_cnt+1;
end
end
 
 
endmodule
mpsoc/src_emulate/fpga/De2-115/src/emulator_top.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: mpsoc/src_emulate/rtl/noc_emulator.v =================================================================== --- mpsoc/src_emulate/rtl/noc_emulator.v (revision 27) +++ mpsoc/src_emulate/rtl/noc_emulator.v (revision 28) @@ -1,5 +1,10 @@ - - +/************************************** +* Module: emulator +* Date:2017-01-20 +* Author: alireza +* +* Description: +***************************************/ module noc_emulator #( //NoC parameters parameter V = 1, // V @@ -25,81 +30,58 @@ parameter SSA_EN="NO", // "YES" , "NO" // simulation - parameter MAX_PCK_NUM=2560000, - parameter MAX_SIM_CLKs=1000000, - parameter MAX_PCK_SIZ=10, - parameter TIMSTMP_FIFO_NUM=16 - + parameter MAX_PATTERN = 124, + parameter VJTAG_INDEX=128, + parameter TIMSTMP_FIFO_NUM=16 )( + jtag_ctrl_reset, reset, clk, done ); - input reset,clk; - output done; + input reset,jtag_ctrl_reset,clk; + output done; - function integer log2; - input integer number; begin - log2=0; - while(2**log21)? log2(C): 1, - NCw = log2(NC), - RATIOw = log2(100), + localparam Fw = 2+V+Fpay, + NC = (TOPOLOGY=="RING")? NX : NX*NY, NCV = NC * V, - NCFw = NC * Fw, - PCK_CNTw= log2(MAX_PCK_NUM+1), - CLK_CNTw= log2(MAX_SIM_CLKs+1), - PCK_SIZw= log2(MAX_PCK_SIZ+1); + NCFw = NC * Fw; + - wire [Fw-1 : 0] ni_flit_out [NC-1 :0]; - wire [NC-1 : 0] ni_flit_out_wr; - wire [V-1 : 0] ni_credit_in [NC-1 :0]; - wire [Fw-1 : 0] ni_flit_in [NC-1 :0]; - wire [NC-1 : 0] ni_flit_in_wr; - wire [V-1 : 0] ni_credit_out [NC-1 :0]; - wire [NCFw-1 : 0] flit_out_all; - wire [NC-1 : 0] flit_out_wr_all; - wire [NCV-1 : 0] credit_in_all; - wire [NCFw-1 : 0] flit_in_all; - wire [NC-1 : 0] flit_in_wr_all; - wire [NCV-1 : 0] credit_out_all; + localparam PCK_CNTw =30, // 1 G packets + PCK_SIZw =14, // 16 K flit + MAXXw =4, // 16 nodes in x dimention + MAXYw =4, // 16 nodes in y dimention : max emulator size is 16X16 + MAXCw =4; // 16 message classes + + + localparam MAX_PCK_NUM = (2**PCK_CNTw)-1, + MAX_SIM_CLKs = 1_000_000_000, + MAX_PCK_SIZ = (2**PCK_SIZw)-1; // max packet size + + - wire [NC-1 : 0] done_sep; - assign done = &done_sep; + reg start_i; reg [10:0] cnt; - always @(posedge clk or posedge reset) begin - if(reset) begin - cnt <=0; - start_i <=0; - end else begin - if(cnt < 1020) cnt<= cnt+1'b1; - if(cnt== 1000)begin - start_i<=1'b1; - end else if(cnt== 1010)begin - start_i<=1'b0; - end - - - end - end + + + wire [NCFw-1 : 0] noc_flit_out_all; + wire [NC-1 : 0] noc_flit_out_wr_all; + wire [NCV-1 : 0] noc_credit_in_all; + wire [NCFw-1 : 0] noc_flit_in_all; + wire [NC-1 : 0] noc_flit_in_wr_all; + wire [NCV-1 : 0] noc_credit_out_all; + noc #( .V(V), @@ -128,38 +110,19 @@ ) the_noc ( - .flit_out_all(flit_out_all), - .flit_out_wr_all(flit_out_wr_all), - .credit_in_all(credit_in_all), - .flit_in_all(flit_in_all), - .flit_in_wr_all(flit_in_wr_all), - .credit_out_all(credit_out_all), + .flit_out_all(noc_flit_out_all), + .flit_out_wr_all(noc_flit_out_wr_all), + .credit_in_all(noc_credit_in_all), + .flit_in_all(noc_flit_in_all), + .flit_in_wr_all(noc_flit_in_wr_all), + .credit_out_all(noc_credit_out_all), .reset(reset), .clk(clk) ); - wire [NC-1 : 0] start; - - start_delay_gen #( - .NC(NC) //number of cores - - )st_gen( - .clk(clk), - .reset(reset), - .start_i(start_i), - .start_o(start) - ); - - genvar x,y; - - - generate - for (x=0; x1)? log2(C): 1, + localparam Fw = 2+V+Fpay, + NC = (TOPOLOGY=="RING")? NX : NX*NY, NCw = log2(NC), - RATIOw = log2(100), NCV = NC * V, - NCFw = NC * Fw, - PCK_CNTw= log2(MAX_PCK_NUM+1), - CLK_CNTw= log2(MAX_SIM_CLKs+1), - PCK_SIZw= log2(MAX_PCK_SIZ+1); + NCFw = NC * Fw; + + - wire [Fw-1 : 0] ni_flit_out [NC-1 :0]; - wire [NC-1 : 0] ni_flit_out_wr; - wire [V-1 : 0] ni_credit_in [NC-1 :0]; - wire [Fw-1 : 0] ni_flit_in [NC-1 :0]; - wire [NC-1 : 0] ni_flit_in_wr; - wire [V-1 : 0] ni_credit_out [NC-1 :0]; - wire [NCFw-1 : 0] flit_out_all; - wire [NC-1 : 0] flit_out_wr_all; - wire [NCV-1 : 0] credit_in_all; - wire [NCFw-1 : 0] flit_in_all; - wire [NC-1 : 0] flit_in_wr_all; - wire [NCV-1 : 0] credit_out_all; - - wire [NC-1 : 0] done_sep; - assign done = &done_sep; - reg start; - reg [10:0] cnt; + - always @(posedge clk or posedge reset) begin - if(reset) begin - cnt <=0; - start <=0; - end else begin - if(cnt < 1020) cnt<= cnt+1'b1; - if(cnt== 1000)begin - start<=1'b1; - end else if(cnt== 1010)begin - start<=1'b0; - end - - - end - end + input reset,jtag_ctrl_reset, clk; + input start_i; + + output done; + + // NOC interfaces + output [NCFw-1 : 0] flit_out_all; + output [NC-1 : 0] flit_out_wr_all; + input [NCV-1 : 0] credit_in_all; + input [NCFw-1 : 0] flit_in_all; + input [NC-1 : 0] flit_in_wr_all; + output [NCV-1 : 0] credit_out_all; + + + + + wire [Fw-1 : 0] flit_out [NC-1 :0]; + wire [NC-1 : 0] flit_out_wr; + wire [V-1 : 0] credit_in [NC-1 :0]; + wire [Fw-1 : 0] flit_in [NC-1 :0]; + wire [NC-1 : 0] flit_in_wr; + wire [V-1 : 0] credit_out [NC-1 :0]; + + + + + + wire [NC-1 : 0] start; + wire [NC-1 : 0] done_sep; + assign done = &done_sep; + + start_delay_gen #( + .NC(NC) //number of cores - noc #( - .V(V), - .B(B), - .NX(NX), - .NY(NY), - .C(C), - .Fpay(Fpay), - .MUX_TYPE(MUX_TYPE), - .VC_REALLOCATION_TYPE(VC_REALLOCATION_TYPE), - .COMBINATION_TYPE(COMBINATION_TYPE), - .FIRST_ARBITER_EXT_P_EN(FIRST_ARBITER_EXT_P_EN), - .TOPOLOGY(TOPOLOGY), - .ROUTE_NAME(ROUTE_NAME), - .CONGESTION_INDEX(CONGESTION_INDEX), - .DEBUG_EN (DEBUG_EN), - .ROUTE_SUBFUNC(ROUTE_SUBFUNC), - .AVC_ATOMIC_EN(AVC_ATOMIC_EN), - .ADD_PIPREG_AFTER_CROSSBAR(ADD_PIPREG_AFTER_CROSSBAR), - .CVw(CVw), - .CLASS_SETTING(CLASS_SETTING), // shows how each class can use VCs - .ESCAP_VC_MASK(ESCAP_VC_MASK), // - .SSA_EN(SSA_EN) - - - ) - the_noc - ( - .flit_out_all(flit_out_all), - .flit_out_wr_all(flit_out_wr_all), - .credit_in_all(credit_in_all), - .flit_in_all(flit_in_all), - .flit_in_wr_all(flit_in_wr_all), - .credit_out_all(credit_out_all), + )st_gen( + .clk(clk), .reset(reset), - .clk(clk) + .start_i(start_i), + .start_o(start) ); + + + //jtag_emulator_controller + - genvar x,y; + + localparam Dw=64, + Aw =log2(MAX_PATTERN+4); // 124 + 4 =128; 4: ramcounter + total latency + total reseived packet + total sent packet; + + + + wire [Dw-1 : 0] jtag_data ; + wire [Aw-1 : 0] jtag_addr ; + wire jtag_we; + wire [Dw-1 : 0] jtag_q ; + wire [NCw-1: 0] jtag_RAM_select; + wire [NC-1 : 0] jtag_we_sep; + wire [Dw-1 : 0] jtag_q_sep [NC-1 : 0]; + + assign jtag_q = jtag_q_sep[jtag_RAM_select]; + + + + + + jtag_emulator_controller #( + .VJTAG_INDEX(VJTAG_INDEX), + .Dw(Dw), + .Aw(Aw+NCw) + + ) + jtag_controller + ( + .dat_o(jtag_data), + .addr_o({jtag_RAM_select,jtag_addr}), + .we_o(jtag_we), + .q_i(jtag_q), + .clk(clk), + .reset(jtag_ctrl_reset) + + ); + + + + + + genvar x,y; generate - for (x=0; x 1)? log2(C): 1, - Fw = 2+V+Fpay, - RATIOw = log2(100), - PCK_CNTw = log2(MAX_PCK_NUM+1), - CLK_CNTw = log2(MAX_SIM_CLKs+1), - PCK_SIZw = log2(MAX_PCK_SIZ+1); + Fw = 2+V+Fpay; + + //define maximum width for each parameter of packet injector + + localparam RATIOw =7; // log2(100) + + + + localparam Dw=PCK_CNTw+ RATIOw + PCK_SIZw + MAXXw + MAXYw + MAXCw +1;//=64 + localparam Aw=log2(MAX_PATTERN+4); // 124 + 4 =128; 4: ramcounter + total latency + total reseived packet + total sent packet; + + localparam STATE_NUM=6, + IDEAL =1, + SEND_PCK=2, + SAVE_SENT_PCK_NUM=4, + SAVE_RSVD_PCK_NUM=8, + SAVE_LATENCY_NUM=16, + ASSET_DONE=32; + + localparam CLK_CNTw = log2(MAX_SIM_CLKs+1), + MAX_PCK_NUM = (2**PCK_CNTw)-1, + MAX_PCK_SIZ = (2**PCK_SIZw)-1; // max packet size + localparam [Aw-1 : 0] RAM_CNT_ADDR = 0, + PATTERN_START_ADDR=1, + PATTERN_END_ADDR= MAX_PATTERN, + SENT_PCK_ADDR = PATTERN_END_ADDR+1, + RSVD_PCK_ADDR = PATTERN_END_ADDR+2, + LATENCY_ADDR = PATTERN_END_ADDR+3; + input reset, clk; input [Xw-1 :0] current_x; input [Yw-1 :0] current_y; @@ -505,7 +545,15 @@ input start; output reg done; - + reg done_next; + + input [Dw-1 : 0] jtag_data_b; + input [Aw-1 : 0] jtag_addr_b; + input jtag_we_b; + output [Dw-1 : 0] jtag_q_b; + + + // NOC interfaces output [Fw-1 :0] flit_out; output flit_out_wr; @@ -515,35 +563,80 @@ output [V-1 :0] credit_out; + + + + + wire [Dw-1 : 0] q_a; + reg [Aw-1 : 0] addr_a,addr_a_next; + reg we_a; + reg [Dw-1 : 0] data_a; + + + + wire [PCK_CNTw-1 :0] pck_num_to_send_in; + wire [RATIOw-1 :0] ratio,ratio_in; + wire [PCK_SIZw-1 :0] pck_size_in; + wire [MAXXw-1 :0] dest_x_in; + wire [MAXYw-1 :0] dest_y_in; + wire [MAXCw-1 :0] pck_class_in; + wire last_adr_in; + + assign {pck_num_to_send_in,ratio_in, pck_size_in,dest_x_in, dest_y_in,pck_class_in, last_adr_in}= q_a; - - //wires - wire [RATIOw-1 :0] ratio,ratio_in; + wire [Xw-1 :0] dest_x = dest_x_in [Xw-1 :0]; + wire [Yw-1 :0] dest_y = dest_y_in [Yw-1 :0]; + wire [Cw-1 :0] pck_class= pck_class_in[Cw-1 :0]; - wire [PCK_SIZw-1 :0] pck_size; - wire [Xw-1 :0] dest_x; - wire [Yw-1 :0] dest_y; - wire [Cw-1 :0] pck_class_in; - - // - wire update; - wire [CLK_CNTw-1 :0] time_stamp_h2h,time_stamp_h2t; - wire [31 :0] distance; - wire [Cw-1 :0] pck_class_out; + + wire [CLK_CNTw-1 :0] time_stamp_h2t; + wire sent_done, update; + reg [ STATE_NUM-1 : 0] ps,ns; + reg [63 : 0] total_pck_recieved,total_pck_recieved_next,total_pck_sent,total_pck_sent_next; + reg [63 : 0] total_latency_cnt,total_latency_cnt_next; + reg [31 : 0] ram_counter,ram_counter_next; + reg [PCK_CNTw-1 :0] pck_number_sent,pck_number_sent_next; + + reg nvalid_dest,reset_pck_number_sent_old; + wire nvalid_dest_next= (current_x==dest_x && current_y==dest_y); + wire reset_pck_number_sent= ((pck_number_sent==pck_num_to_send_in) | nvalid_dest) & ~reset_pck_number_sent_old; + + assign ratio=(ps==SEND_PCK)? ratio_in : {RATIOw{1'b0}}; + + + - wire [PCK_CNTw-1 :0] pck_number_recieved,pck_num_to_send; - reg [PCK_CNTw-1 :0] pck_number_sent; + + dual_port_ram #( + .Dw (Dw), + .Aw (Aw) + ) + the_ram + ( + .clk (clk), + //port a + .data_a (data_a), + .addr_a (addr_a), + .we_a (we_a), + .q_a (q_a), + + //port b connected to the jtag + .data_b (jtag_data_b), + .addr_b (jtag_addr_b), + .we_b (jtag_we_b), + .q_b (jtag_q_b) + + ); - wire sent_done; - wire hdr_flit_sent; - reg [31 : 0] total_pck_recieved,total_pck_sent; - reg [35 : 0] total_latency_cnt; - reg [31 : 0] ram_counter; - wire [31 : 0] initial_ram_cnt; + + + + - + + traffic_gen #( .V(V), .B(B), @@ -563,22 +656,23 @@ ( //input .ratio (ratio), - .pck_size(pck_size), + .pck_size_in(pck_size_in), .current_x(current_x), .current_y(current_y), .dest_x(dest_x), .dest_y(dest_y), - .pck_class_in(pck_class_in), + .pck_class_in(pck_class), .start(start), .report (), + //output - .pck_number(pck_number_recieved), + .pck_number( ), .sent_done(sent_done), // tail flit has been sent - .hdr_flit_sent(hdr_flit_sent), + .hdr_flit_sent( ), .update(update), // update the noc_analayzer - .distance(distance), - .pck_class_out(pck_class_out), - .time_stamp_h2h(time_stamp_h2h), + .distance( ), + .pck_class_out( ), + .time_stamp_h2h( ), .time_stamp_h2t(time_stamp_h2t), //noc .flit_out(flit_out), @@ -592,124 +686,268 @@ .clk(clk) ); + + + + + + + + + always @ (*)begin + ns=ps; + addr_a_next = addr_a; + pck_number_sent_next = pck_number_sent; + done_next =done; + total_latency_cnt_next = total_latency_cnt; + total_pck_recieved_next = total_pck_recieved; + total_pck_sent_next = total_pck_sent; + ram_counter_next = ram_counter; + data_a = total_pck_sent; + we_a = 0; + + case(ps) + IDEAL : begin + done_next =1'b0; + addr_a_next =RAM_CNT_ADDR; + ram_counter_next = q_a[31:0]; // first ram dada shows howmany times need to read the RAM + if( start) begin + addr_a_next=PATTERN_START_ADDR; + ns= SEND_PCK; + end + + end//IDEAL + SEND_PCK: begin + if (reset_pck_number_sent) begin + pck_number_sent_next={PCK_CNTw{1'b0}}; + if(last_adr_in)begin + if(ram_counter==0)begin + ns = SAVE_SENT_PCK_NUM; + addr_a_next = SENT_PCK_ADDR; + end else addr_a_next = 1; + ram_counter_next=ram_counter-1'b1; + end else begin + addr_a_next=addr_a+1'b1; + + end + + end + else if(sent_done)begin + pck_number_sent_next =pck_number_sent+1'b1; + total_pck_sent_next =total_pck_sent+1'b1; + end + if(update)begin + total_latency_cnt_next = total_latency_cnt + time_stamp_h2t; + total_pck_recieved_next =total_pck_recieved+1'b1; + end + + + + end//SEND_PCk + SAVE_SENT_PCK_NUM: begin + data_a = total_pck_sent; + we_a = 1; + addr_a_next =RSVD_PCK_ADDR ; + ns= SAVE_RSVD_PCK_NUM; + + end + SAVE_RSVD_PCK_NUM: begin + data_a = total_pck_recieved; + addr_a_next =LATENCY_ADDR; + we_a = 1; + ns= SAVE_LATENCY_NUM; + + + end + SAVE_LATENCY_NUM: begin + data_a = total_latency_cnt; + we_a = 1; + ns= ASSET_DONE; + + end + ASSET_DONE: begin + done_next =1'b1; + end + endcase + end//always + + + + always @(posedge clk) begin + if(reset)begin + ps <= IDEAL; + addr_a <={Aw{1'b0}}; + pck_number_sent<={PCK_CNTw{1'b0}}; + done<=1'b0; + total_latency_cnt<=64'd0; + total_pck_recieved<=64'd0; + total_pck_sent<=64'd0; + ram_counter<= 32'd0; + nvalid_dest<=1'b0; + reset_pck_number_sent_old<=1'b0; + end else begin + ps <= ns; + addr_a<= addr_a_next; + pck_number_sent<= pck_number_sent_next; + done <=done_next; + total_latency_cnt<= total_latency_cnt_next; + total_pck_recieved<= total_pck_recieved_next; + total_pck_sent<= total_pck_sent_next; + ram_counter<= ram_counter_next; + nvalid_dest<=nvalid_dest_next; + reset_pck_number_sent_old<=reset_pck_number_sent; + end + end + +endmodule -localparam RAM_TAG_STRING=IP_NUM; -localparam SRC_PRB_TAG=IP_NUM+128; -localparam RAM_ID = {"ENABLE_RUNTIME_MOD=NO"}; -localparam Dw=PCK_CNTw+ RATIOw + PCK_SIZw + Xw + Yw + Cw +1; -localparam Aw=7; -reg [Aw-1 : 0] ram_addr; -wire [Dw-1 : 0] ram_do; -wire last_adr; +/*********************** +* +* jtag_emulator_controller +* +***********************/ -// control/monitor packet injector using In-System Sources and Probes Editor -localparam PRBw=36+32+32, - SRCw=32; - -wire [SRCw-1 : 0] source; -wire [PRBw-1 : 0] probe; -assign probe ={total_latency_cnt, total_pck_recieved,total_pck_sent}; -assign initial_ram_cnt =source; +module jtag_emulator_controller #( + parameter VJTAG_INDEX=126, + parameter Dw=32, + parameter Aw=32 - - ram_single_port_jtag #( - .Dw(Dw), - .Aw(Aw), - .JTAG_INDEX(RAM_TAG_STRING), //use for programming the memory at run time - .BENw(1) - - ) ram_inst - ( - .clk(clk), - .reset(1'b0), - //memory interface - .data_a({Dw{1'b0}}), - .addr_a(ram_addr), - .byteena_a(1'b1), - .we_a(1'b0), - .q_a(ram_do) - - ); +)( + clk, + reset, + + + //wishbone master interface signals + + dat_o, + addr_o, + + we_o, + q_i + + +); + //IO declaration + input reset,clk; + + + //wishbone master interface signals + + output [Dw-1 : 0] dat_o; + output [Aw-1 : 0] addr_o; + output we_o; + input [Dw-1 : 0] q_i; + + + localparam STATE_NUM=3, + IDEAL =1, + WB_WR_DATA=2, + WB_RD_DATA=4; + + reg [STATE_NUM-1 : 0] ps,ns; + + wire [Dw-1 :0] data_out, data_in; + wire wb_wr_addr_en, wb_wr_data_en, wb_rd_data_en; + reg wr_mem_en, wb_cap_rd; + + reg [Aw-1 : 0] wb_addr,wb_addr_next; + reg [Dw-1 : 0] wb_wr_data,wb_rd_data; + reg wb_addr_inc; + + + + assign we_o = wr_mem_en; + assign dat_o = wb_wr_data; + assign addr_o = wb_addr; + assign data_in = wb_rd_data; +//vjtag vjtag signals declaration + - - - -localparam jDw=(PRBw>SRCw)? PRBw : SRCw; - - jtag_source_probe #( - .Dw(jDw), - .VJTAG_INDEX(SRC_PRB_TAG) +localparam VJ_DW= (Dw > Aw)? Dw : Aw; - ) - src_pb + + vjtag_ctrl #( + .DW(VJ_DW), + .VJTAG_INDEX(VJTAG_INDEX) + ) + vjtag_ctrl_inst ( - .probe(probe), - .source(source) - ); - - - - - - - - - assign {pck_num_to_send,ratio_in,pck_size,dest_x,dest_y,pck_class_in,last_adr}=ram_do; + .clk(clk), + .reset(reset), + .data_out(data_out), + .data_in(data_in), + .wb_wr_addr_en(wb_wr_addr_en), + .wb_wr_data_en(wb_wr_data_en), + .wb_rd_data_en(wb_rd_data_en), + .status_i( ) + ); - assign ratio=(done)? {RATIOw{1'b0}} : ratio_in; - wire nvalid_dest= (current_x==dest_x && current_y==dest_y); - wire reset_pck_number_sent= (pck_number_sent==pck_num_to_send) | nvalid_dest; + + + always @(posedge clk or posedge reset) begin + if(reset) begin + wb_addr <= {Aw{1'b0}}; + wb_wr_data <= {Dw{1'b0}}; + ps <= IDEAL; + end else begin + wb_addr <= wb_addr_next; + ps <= ns; + if(wb_wr_data_en) wb_wr_data <= data_out; + if(wb_cap_rd) wb_rd_data <= q_i; + end + end + + - always @(posedge clk) begin - if(reset)begin - ram_addr<={Aw{1'b0}}; - pck_number_sent<={PCK_CNTw{1'b0}}; - done<=1'b0; - total_latency_cnt<=36'd0; - total_pck_recieved<=0; - total_pck_sent<=0; - ram_counter<= initial_ram_cnt; - end else begin - if (reset_pck_number_sent) pck_number_sent<={PCK_CNTw{1'b0}}; - else if(sent_done)begin - pck_number_sent<=pck_number_sent+1'b1; - total_pck_sent <=total_pck_sent+1'b1; - end + + + always @(*)begin + wb_addr_next= wb_addr; + if(wb_wr_addr_en) wb_addr_next = data_out [Aw-1 : 0]; + else if (wb_addr_inc) wb_addr_next = wb_addr + 1'b1; + end + + + + always @(*)begin + ns=ps; + wr_mem_en =1'b0; + + wb_addr_inc=1'b0; + wb_cap_rd=1'b0; + case(ps) + IDEAL : begin + if(wb_wr_data_en) ns= WB_WR_DATA; + if(wb_rd_data_en) ns= WB_RD_DATA; + end + WB_WR_DATA: begin + wr_mem_en =1'b1; + ns=IDEAL; + wb_addr_inc=1'b1; - if(update)begin - total_latency_cnt<= total_latency_cnt + time_stamp_h2t; - total_pck_recieved<=total_pck_recieved+1'b1; - end - - if (reset_pck_number_sent && done==1'b0)begin - if(last_adr)begin - ram_addr<={Aw{1'b0}}; - if(ram_counter==0)begin - done<=1'b1; - end - ram_counter<=ram_counter-1'b1; - end else begin - ram_addr<=ram_addr+1'b1; - - end - end + end + WB_RD_DATA: begin + + wb_cap_rd=1'b1; + ns=IDEAL; + //wb_addr_inc=1'b1; - - end + end + endcase + end - end + //assign led={wb_addr[7:0], wb_wr_data[7:0]}; - endmodule @@ -716,6 +954,9 @@ + + + module start_delay_gen #( parameter NC = 64 //number of cores @@ -773,3 +1014,9 @@ + + + + + +
/mpsoc/src_modelsim/testbench_modelsim.v
22,7 → 22,7
reg start;
wire done;
reg [RATIOw-1:0] ratio;
reg [PCK_SIZw-1 : 0]pck_size;
reg [PCK_SIZw-1 : 0]pck_size_in;
 
 
 
32,7 → 32,7
.clk (clk),
.start (start),
.ratio (ratio),
.pck_size(pck_size),
.pck_size_in(pck_size_in),
.all_done (done)
);
 
47,7 → 47,7
initial begin
reset = 1'b1;
start = 1'b0;
pck_size=4;
pck_size_in=4;
ratio =50;
i=0;
#40
141,7 → 141,7
clk,
start,
ratio,
pck_size,
pck_size_in,
all_done
);
191,7 → 191,7
 
 
input reset ,clk, start;
input [PCK_SIZw-1:0] pck_size;
input [PCK_SIZw-1:0] pck_size_in;
input [RATIOw-1 :0] ratio;
output all_done;
325,7 → 325,7
(
//input
.ratio (ratio),
.pck_size(pck_size),
.pck_size_in(pck_size_in),
.current_x(x[Xw-1 : 0]),
.current_y(y[Yw-1 : 0]),
.dest_x(dest_x[IP_NUM]),
481,7 → 481,7
fp = $fopen("Result.txt","w");
`endif
$fwrite(fp,"TRAFFIC is =%s\n",TRAFFIC);
$fwrite(fp,"Packet size in flit=%d\n ",pck_size);
$fwrite(fp,"Packet size in flit=%d\n ",pck_size_in);
//$fwrite(fp,"ROUTE_ALGRMT =%s",ROUTE_ALGRMT);
$fwrite(fp,"VC_REALLOCATION_TYPE = %s\n",VC_REALLOCATION_TYPE);
$fwrite(fp,"COMBINATION_TYPE = %s\n",COMBINATION_TYPE);
516,7 → 516,7
total_clk = total_clk + clk_count;
total_pck = total_pck + packet_num;
total_router = total_router +1'b1;
ratio_avg <= (total_clk>0)? (total_pck* pck_size*100)/total_clk:0;
ratio_avg <= (total_clk>0)? (total_pck* pck_size_in*100)/total_clk:0;
end
end
if(inject_report_in) begin
525,7 → 525,7
$display("Injection ratio is =%f",ratio_avg);
$display("total_pck =%f",total_pck);
$display("TRAFFIC is =%s",TRAFFIC);
$display("Packet size in flit=%d ",pck_size);
$display("Packet size in flit=%d ",pck_size_in);
$display("total_clk=%d ",total_clk);
$display("ROUTE_NAME =%s",ROUTE_NAME);
$display("ROUTE_TYPE =%s",ROUTE_TYPE);
/mpsoc/src_noc/traffic_gen_old.v File deleted
mpsoc/src_noc/traffic_gen_old.v Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: mpsoc/src_noc/inout_ports.v =================================================================== --- mpsoc/src_noc/inout_ports.v (revision 27) +++ mpsoc/src_noc/inout_ports.v (revision 28) @@ -171,7 +171,9 @@ .NX(NX), // number of node in x axis .NY(NY), // number of node in y axis .X(X), // router x address - .Y(Y) // router y address + .Y(Y), // router y address + .DEBUG_EN(DEBUG_EN), + .ESCAP_VC_MASK(ESCAP_VC_MASK) ) the_ssa @@ -183,7 +185,7 @@ .ovc_avalable_all(ovc_avalable_all), .ivc_request_all(ivc_request_all), .assigned_ovc_not_full_all(assigned_ovc_not_full_all), - .dest_port_all(dest_port_all), + .dest_port_all(dest_port_coded_all), .assigned_ovc_num_all(assigned_ovc_num_all), .ovc_is_assigned_all(ovc_is_assigned_all), .clk(clk), @@ -190,7 +192,7 @@ .reset(reset), .ovc_allocated_all(ssa_ovc_allocated_all), - .ovc_released_all(ssa_ovc_released_all), + .ovc_released_all(ssa_ovc_released_all), .granted_ovc_num_all(ssa_granted_ovc_num_all), .ivc_num_getting_sw_grant_all(ssa_ivc_num_getting_sw_grant_all), .ivc_num_getting_ovc_grant_all(ssa_ivc_num_getting_ovc_grant_all),
/mpsoc/src_noc/noc.v
197,8 → 197,9
end else begin :mesh_torus
for (x=0; x<NX; x=x+1) begin :x_loop
for (y=0; y<NY; y=y+1) begin: y_loop
for (y=0; y<NY; y=y+1) begin: y_loop
for (x=0; x<NX; x=x+1) begin :x_loop
localparam IP_NUM = (y * NX) + x;
/mpsoc/src_noc/ss_allocator.v
23,7 → 23,9
parameter NY = 4, // number of node in y axis
parameter TOPOLOGY = "MESH",
parameter X = 0, // router x address
parameter Y = 0 // router y address
parameter Y = 0, // router y address
parameter DEBUG_EN = 1,
parameter [V-1 : 0] ESCAP_VC_MASK = 4'b1000
)
(
flit_in_we_all,
143,7 → 145,9
.V(V),
.P(P),
.Fpay(Fpay),
.ROUTE_TYPE(ROUTE_TYPE)
.ROUTE_TYPE(ROUTE_TYPE),
.DEBUG_EN(DEBUG_EN),
.ESCAP_VC_MASK(ESCAP_VC_MASK)
)
the_ssa_per_vc
(
164,7 → 168,12
.ivc_num_getting_ovc_grant(ivc_num_getting_ovc_grant_all[i]),
.ivc_reset(ivc_reset_all[i]),
.decreased_credit_in_ss_ovc(decreased_credit_in_ss_ovc_all[(SS_PORT*V)+(i%V)])
// .predict_flit_wr(predict_flit_wr_all[PREDICT_PO]),
//synthesis translate_off
//synopsys translate_off
,.clk(clk)
//synthesis translate_on
//synopsys translate_on
// .predict_flit_wr(predict_flit_wr_all[PREDICT_PO]),
 
);
222,7 → 231,9
parameter V = 4, // vc_num_per_port
parameter P = 5, // router port num
parameter Fpay = 32, //pa
parameter ROUTE_TYPE="DETERMINISTIC" // "DETERMINISTIC", "FULL_ADAPTIVE", "PAR_ADAPTIVE"
parameter ROUTE_TYPE="DETERMINISTIC", // "DETERMINISTIC", "FULL_ADAPTIVE", "PAR_ADAPTIVE"
parameter DEBUG_EN = 1,
parameter [V-1 : 0] ESCAP_VC_MASK = 4'b1000
)
(
flit_in_we,
241,7 → 252,12
ovc_released,
ovc_allocated,
decreased_credit_in_ss_ovc,
ivc_reset
ivc_reset
//synthesis translate_off
//synopsys translate_off
,clk
//synthesis translate_on
//synopsys translate_on
);
251,7 → 267,8
 
 
 
localparam SSA_EN = ((ROUTE_TYPE == "FULL_ADAPTIVE") && (SS_PORT==2 || SS_PORT == 4) && ((1<<V_LOCAL & ~ESCAP_VC_MASK ) != {V{1'b0}})) ? 1'b0 :1'b1;
283,6 → 300,11
output ivc_reset;
output decreased_credit_in_ss_ovc;
 
//synthesis translate_off
//synopsys translate_off
input clk;
//synthesis translate_on
//synopsys translate_on
 
 
 
397,7 → 419,26
assign ss_port_hdr_flit = b;
assign ss_port_nonhdr_flit = bb;
end
end
 
 
 
//synthesis translate_off
//synopsys translate_off
 
if(DEBUG_EN) begin :dbg
always @(posedge clk) begin
//if(!reset)begin
if(ivc_num_getting_sw_grant & aa & bb) $display("%t: SSA ERROR: There are two output ports that a non-header flit can be sent to. %m",$time);
//end
end
end //dbg
 
//synopsys translate_on
//synthesis translate_on
 
 
 
end //adaptive
endgenerate
 
 
412,9 → 453,15
// check if ssa is permited by input port
 
wire ssa_permited_by_iport;
assign ssa_permited_by_iport = ss_ovc_ready & (~ivc_request) & condition_1_2_valid;
 
 
generate
if (SSA_EN) begin : enable
assign ssa_permited_by_iport = ss_ovc_ready & (~ivc_request) & condition_1_2_valid;
end else begin : disabled
assign ssa_permited_by_iport = 1'b0;
end
endgenerate
 
/*********************************
check incomming packet conditions
/mpsoc/src_noc/traffic_gen.v
28,7 → 28,7
(
//input
ratio,
pck_size,
pck_size_in,
current_x,
current_y,
dest_x,
113,7 → 113,7
input [Xw-1 :0] dest_x;
input [Yw-1 :0] dest_y;
output [PCK_CNTw-1 :0] pck_number;
input [PCK_SIZw-1 :0] pck_size;
input [PCK_SIZw-1 :0] pck_size_in;
output reg sent_done;
output hdr_flit_sent;
input [Cw-1 :0] pck_class_in;
132,7 → 132,7
 
reg inject_en,cand_wr_vc_en,pck_rd;
 
reg [PCK_SIZw-1 :0] pck_size, pck_size_next;
261,9 → 261,19
assign time_stamp_h2h = rsv_time_stamp[rd_vc_bin] - flit_in[CLK_CNTw-1 : 0];
assign time_stamp_h2t = clk_counter - flit_in[CLK_CNTw-1 : 0];
 
assign flit_out = (hdr_flit) ? {2'b10,wr_vc,wr_class_hdr,wr_destport_hdr,wr_des_x_addr,wr_des_y_addr,wr_src_x_addr,wr_src_y_addr}:
(tail_flit) ? {2'b01,wr_vc,{(Fpay-CLK_CNTw){1'b0}},wr_timestamp}:
{2'b00,wr_vc,{(Fpay-PCK_SIZw-PCK_CNTw){1'd0}},pck_number,flit_counter};
wire [Fpay-1 : 0] flit_out_pyload;
wire [1 : 0] flit_out_hdr;
assign flit_out_pyload = (hdr_flit) ? {wr_class_hdr,wr_destport_hdr,wr_des_x_addr,wr_des_y_addr,wr_src_x_addr,wr_src_y_addr}:
(tail_flit) ? wr_timestamp:
{pck_number,flit_counter};
assign flit_out_hdr = (hdr_flit) ? 2'b10:
(tail_flit) ? 2'b01:
2'b00;
assign flit_out = {flit_out_hdr, wr_vc, flit_out_pyload };
 
assign {rd_hdr_flg,rd_vc,rd_class_hdr,rd_destport_hdr,rd_des_x_addr,rd_des_y_addr,rd_src_x_addr,rd_src_y_addr} = flit_in;
 
338,9 → 348,11
pck_rd = 1'b0;
ns = ps;
pck_rd =1'b0;
pck_size_next = pck_size;
case (ps)
IDEAL: begin
pck_size_next = pck_size_in;
if(pck_ready ) begin
if(wr_vc_avb && valid_dst)begin
pck_rd=1'b1;
360,6 → 372,7
flit_cnt_inc = 1'b1;
end else begin
flit_cnt_rst = 1'b1;
pck_size_next = pck_size_in;
sent_done =1'b1;
cand_wr_vc_en =1'b1;
if(cand_vc>0) begin
399,6 → 412,7
credit_out <= {V{1'd0}};
rsv_counter <= 0;
clk_counter <= 0;
pck_size <= 0;
end
411,7 → 425,7
if (flit_cnt_rst) flit_counter <= {PCK_SIZw{1'b0}};
else if(flit_cnt_inc) flit_counter <= flit_counter + 1'b1;
credit_out <= credit_out_next;
pck_size <= pck_size_next;
//sink
if(flit_in_wr) begin
461,7 → 475,7
wire [PCK_CNTw-1 : 0] rsv_pck_number;
reg [PCK_CNTw-1 : 0] old_pck_number [V-1 : 0];
assign {rsv_pck_number,rsv_flit_counter}=flit_in [PCK_CNTw+PCK_SIZw-1 : 0];
assign {rsv_pck_number,rsv_flit_counter}=flit_in;
integer ii;
always @(posedge clk or posedge reset )begin
577,9 → 591,9
case(sent)
1'b1: begin
next_state = state + off_clks;
next_flit_counter = (flit_counter == pck_size-1'b1) ? {PCK_SIZw{1'b0}} : flit_counter +1'b1;
next_flit_counter = (flit_counter >= pck_size-1'b1) ? {PCK_SIZw{1'b0}} : flit_counter +1'b1;
next_inject = (flit_counter=={PCK_SIZw{1'b0}});
if (next_flit_counter == pck_size-1'b1) begin
if (next_flit_counter >= pck_size-1'b1) begin
if( next_state >= STATE_INIT ) next_sent =1'b0;
end
end
882,3 → 896,4
 
 
/mpsoc/src_noc/traffic_gen.v.old
0,0 → 1,842
/**********************************
 
traffic_gen
 
 
**********************************/
`timescale 1ns/1ps
 
 
module traffic_gen_old#(
parameter V = 4, // VC num per port
parameter P = 5, // router port num
parameter B = 4, // buffer space :flit per VC
parameter NX= 4, // number of node in x axis
parameter NY= 4, // number of node in y axis
parameter C = 4, // number of flit class
parameter Fpay = 32,
parameter VC_REALLOCATION_TYPE = "NONATOMIC",// "ATOMIC" , "NONATOMIC"
parameter TOPOLOGY = "MESH",
parameter ROUTE_NAME = "XY",
parameter ROUTE_TYPE = "DETERMINISTIC",// "DETERMINISTIC", "FULL_ADAPTIVE", "PAR_ADAPTIVE"
parameter TRAFFIC = "RANDOM",
// "RANDOM", "TRANSPOSE1","TRANSPOSE2", "HOTSPOT", "BIT_REVERSE", "BIT_COMPLEMENT", "CUSTOM"
parameter CLASS_3_TRAFFIC_PATTERN= 1,
/*
0: 25 % class 0 , 75 % class 1
1: 50 % class 0 , 50 % class 1
2: 75 % class 0 , 25 % class 1
*/
//setting for hotspot
parameter HOTSPOT_PERCENTAGE = 3, //maximum 20
parameter HOTSOPT_NUM = 4, //maximum 4
parameter HOTSPOT_CORE_1 = 10,
parameter HOTSPOT_CORE_2 = 11,
parameter HOTSPOT_CORE_3 = 12,
parameter HOTSPOT_CORE_4 = 13,
parameter HOTSPOT_CORE_5 = 14,
//parameter PCK_SIZE_IN_FLIT = 6,
//total number of packets which is sent by a router
parameter TOTAL_PKT_PER_ROUTER = 200,
parameter MAX_DELAY_BTWN_PCKTS = 1024,
parameter TIMSTAMP_STRT_ON= "INJECT_EN"// "INJECT_EN", "HDR_FLIT_WR"
)
(
delay,
pck_size,
pck_counter,
current_x,
current_y,
reset,
clk,
start,
done,
update, // update the noc_analayzer
distance,
msg_class,
time_stamp,
flit_out,
flit_out_wr,
credit_in,
flit_in,
flit_in_wr,
credit_out,
report
);
 
function integer log2;
input integer number; begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
localparam P_1 = P-1 ;
localparam Xw = log2(NX), // number of node in x axis
Yw = log2(NY), // number of node in y axis
Cw = log2(C),
Fw = 2+V+Fpay,
Dw = log2(MAX_DELAY_BTWN_PCKTS+1),
PCK_CNTw = log2(TOTAL_PKT_PER_ROUTER+1);
 
localparam CLASS_IN_HDR_WIDTH =8,
DEST_IN_HDR_WIDTH =8,
X_Y_IN_HDR_WIDTH =4;
/*
reg inject_en;
pck_size,
wr_des_x_addr,
wr_des_y_addr,
wr_class_hdr,
*/
input reset, clk;
/*
input inject_en;
input [15 :0] pck_size;
*/
input [Dw-1 :0] delay;
input start;
output done;
output update;
output [31 :0] time_stamp;
output [31 :0] distance;
output [Cw-1 :0] msg_class;
input [Xw-1 :0] current_x;
input [Yw-1 :0] current_y;
output [PCK_CNTw-1 :0] pck_counter;
input [15 :0] pck_size;
// NOC interfaces
output [Fw-1 :0] flit_out;
output reg flit_out_wr;
input [V-1 :0] credit_in;
input [Fw-1 :0] flit_in;
input flit_in_wr;
output reg [V-1 :0] credit_out;
reg sent_done;
input report;
wire [X_Y_IN_HDR_WIDTH-1 :0] wr_des_x_addr,wr_src_x_addr;
wire [X_Y_IN_HDR_WIDTH-1 :0] wr_des_y_addr,wr_src_y_addr;
wire [CLASS_IN_HDR_WIDTH-1 :0] wr_class_hdr;
wire [V-1 :0] full_vc,empty_vc;
reg [V-1 :0] wr_vc,wr_vc_next;
reg [15 :0] counter;
reg counter_inc,counter_reset;
wire wr_vc_is_full,wr_vc_avb,wr_vc_is_empty;
 
wire [P_1-1 :0] destport;
reg [V-1 :0] credit_out_next;
reg [31 :0] clk_counter,clk_counter_lathched;
wire [V-1 :0] ovc_wr_in;
wire hdr_flit,tail_flit;
wire [DEST_IN_HDR_WIDTH-1 :0] wr_destport_hdr;
// noc_analyze
localparam VC_NUM_BCD_WIDTH = log2(V);
 
reg [X_Y_IN_HDR_WIDTH-1 : 0] rsv_pck_src_x [V-1:0];
reg [X_Y_IN_HDR_WIDTH-1 : 0] rsv_pck_src_y [V-1:0];
reg [Cw-1 : 0] rsv_pck_class [V-1:0];
wire[V-1 :0] rd_vc;
wire [1 : 0] rd_hdr_flg;
wire [CLASS_IN_HDR_WIDTH-1 : 0] rd_class_hdr;
wire [DEST_IN_HDR_WIDTH-1 : 0] rd_destport_hdr;
wire [X_Y_IN_HDR_WIDTH-1 : 0] rd_des_x_addr, rd_des_y_addr,rd_src_x_addr,rd_src_y_addr;
wire[VC_NUM_BCD_WIDTH-1 : 0] rd_vc_bin,wr_vc_bin;
reg [31 : 0] sent_time_stamp[V-1:0];
reg [31 : 0] rsv_time_stamp[V-1:0];
reg cand_wr_vc_en;
wire [V-1 : 0] cand_vc;
wire [Xw-1 : 0] dest_x;
wire [Yw-1 : 0] dest_y;
wire inject_en;
assign update = flit_in_wr & flit_in[Fw-2];
assign hdr_flit = (counter == 0);
assign tail_flit = (counter == pck_size-1'b1);
assign wr_destport_hdr= {{DEST_IN_HDR_WIDTH-P_1{1'b0}},destport};
assign flit_out= (hdr_flit) ? {2'b10,wr_vc,wr_class_hdr,wr_destport_hdr,wr_des_x_addr,wr_des_y_addr,wr_src_x_addr,wr_src_y_addr}:
(tail_flit) ? {2'b01,wr_vc,sent_time_stamp[wr_vc_bin]}:
{2'b00,wr_vc,{16{1'd0}},counter};
 
assign {rd_hdr_flg,rd_vc,rd_class_hdr,rd_destport_hdr,rd_des_x_addr,rd_des_y_addr,rd_src_x_addr,rd_src_y_addr} = flit_in;
 
one_hot_to_bin #( .ONE_HOT_WIDTH (V)) conv1
(
.one_hot_code (rd_vc),
.bin_code (rd_vc_bin)
);
one_hot_to_bin #( .ONE_HOT_WIDTH (V)) conv2
(
.one_hot_code (wr_vc),
.bin_code (wr_vc_bin)
);
assign ovc_wr_in = (flit_out_wr ) ? wr_vc : {V{1'b0}};
 
assign wr_vc_is_full = | ( full_vc & wr_vc);
assign wr_vc_is_empty = | ( empty_vc & wr_vc);
generate
if(VC_REALLOCATION_TYPE == "NONATOMIC") begin
assign wr_vc_avb = ~wr_vc_is_full;
end else begin
assign wr_vc_avb = wr_vc_is_empty;
end
endgenerate
ni_conventional_routing #(
.P(P),
.NX(NX),
.NY(NY),
.ROUTE_TYPE(ROUTE_TYPE),
.TOPOLOGY(TOPOLOGY),
.ROUTE_NAME(ROUTE_NAME),
.LOCATED_IN_NI(1)
)
conv_routing(
.current_x( current_x),
.current_y( current_y),
.dest_x (wr_des_x_addr [Xw-1 :0]),
.dest_y (wr_des_y_addr [Yw-1 :0]),
.destport (destport)
);
output_vc_status #(
.V (V),
.B (B),
.CAND_VC_SEL_MODE (0) // 0: use arbieration between not full vcs, 1: select the vc with moast availble free space
)
nic_ovc_status
(
.wr_in (ovc_wr_in),
.credit_in (credit_in),
.full_vc (full_vc),
.empty_vc (empty_vc),
.cand_vc (cand_vc),
.cand_wr_vc_en (cand_wr_vc_en),
.clk (clk),
.reset (reset)
);
send_traffic #(
.V(V),
.C(C),
.NX(NX),
.NY(NY),
.TRAFFIC(TRAFFIC),
.CLASS_3_TRAFFIC_PATTERN(CLASS_3_TRAFFIC_PATTERN),
.HOTSPOT_PERCENTAGE(HOTSPOT_PERCENTAGE),
.HOTSOPT_NUM(HOTSOPT_NUM),
.HOTSPOT_CORE_1(HOTSPOT_CORE_1),
.HOTSPOT_CORE_2(HOTSPOT_CORE_2),
.HOTSPOT_CORE_3(HOTSPOT_CORE_3),
.HOTSPOT_CORE_4(HOTSPOT_CORE_4),
.HOTSPOT_CORE_5(HOTSPOT_CORE_5),
.MAX_DELAY_BTWN_PCKTS(MAX_DELAY_BTWN_PCKTS),
.TOTAL_PKT_PER_ROUTER(TOTAL_PKT_PER_ROUTER)
)
send_traffic(
.pck_counter(pck_counter),
.send_start(start),
.sent_done(sent_done),
.current_x(current_x),
.current_y(current_y),
.delay(delay),
.clk(clk),
.reset(reset),
.dest_x(dest_x),
.dest_y(dest_y),
.class_hdr(wr_class_hdr),
.inject_en(inject_en),
.done(done)
);
assign wr_des_x_addr[Xw-1 : 0]= dest_x;
assign wr_des_x_addr[X_Y_IN_HDR_WIDTH-1 : Xw]= 0;
assign wr_des_y_addr[Yw-1 : 0]= dest_y;
assign wr_des_y_addr[X_Y_IN_HDR_WIDTH-1 : Yw]= 0;
assign wr_src_x_addr[Xw-1 : 0]= current_x;
assign wr_src_x_addr[X_Y_IN_HDR_WIDTH-1 : Xw]= 0;
assign wr_src_y_addr[Yw-1 : 0]= current_y;
assign wr_src_y_addr[X_Y_IN_HDR_WIDTH-1 : Yw]= 0;
reg [2:0] ps,ns;
localparam IDEAL =3'b001, SENT =3'b010, WAIT=3'b100;
reg capture_done;
always @(*)begin
wr_vc_next = wr_vc;
cand_wr_vc_en = 1'b0;
flit_out_wr = 1'b0;
counter_inc = 1'b0;
counter_reset = 1'b0;
credit_out_next = {V{1'd0}};
sent_done =1'b0;
ns =ps;
case (ps)
IDEAL: begin
if(inject_en) begin
if(wr_vc_avb)begin
flit_out_wr = 1'b1;
counter_inc = 1'b1;
ns = SENT;
end//wr_vc
end //injection_en
end //IDEAL
SENT: begin
if(!wr_vc_is_full)begin
flit_out_wr = 1'b1;
if(counter < pck_size-1) begin
counter_inc = 1'b1;
end else begin
counter_reset = 1'b1;
sent_done =1'b1;
cand_wr_vc_en =1'b1;
if(cand_vc>0) begin
wr_vc_next = cand_vc;
ns =IDEAL;
end else ns = WAIT;
end//else
end // if wr_vc_is_full
end//SENT
WAIT:begin
cand_wr_vc_en =1'b1;
if(cand_vc>0) begin
wr_vc_next = cand_vc;
ns =IDEAL;
end
end
default: begin
ns =IDEAL;
end
endcase
// packet sink
if(flit_in_wr) begin
credit_out_next = rd_vc;
end else credit_out_next = {V{1'd0}};
end
integer rsv_counter,last_pck_time;
 
always @(posedge clk or posedge reset )begin
if(reset) begin
ps <= IDEAL;
wr_vc <=1;
counter <= 16'd0;
credit_out <= {V{1'd0}};
rsv_counter <= 0;
clk_counter <= 0;
capture_done <= 0;
clk_counter_lathched<=0;
end
else begin
//injection
ps <= ns;
clk_counter <= clk_counter+1'b1;
wr_vc <=wr_vc_next;
if (counter_reset) counter <= 16'd0;
else if(counter_inc) counter <= counter+1'b1;
credit_out <= credit_out_next;
//sink
if(flit_in_wr) begin
if (flit_in[Fw-1])begin
rsv_pck_src_x[rd_vc_bin] <= rd_src_x_addr;
rsv_pck_src_y[rd_vc_bin] <= rd_src_y_addr;
rsv_pck_class[rd_vc_bin] <= rd_class_hdr[Cw-1 : 0];
rsv_time_stamp[rd_vc_bin] <= clk_counter;
rsv_counter <= rsv_counter+1'b1;
// distance <= {{(32-8){1'b0}},flit_in[7:0]};
// synthesis translate_off
last_pck_time<=$time;
//$display ("%d,\t toptal of %d pcks have been recived in core (%d,%d)", last_pck_time,rsv_counter,X,Y);
// synthesis translate_on
end
end
// synthesis translate_off
if(report) begin
$display ("%t,\t toptal of %d pcks have been recived in core (%d,%d)", last_pck_time,rsv_counter,current_x,current_y);
end
// synthesis translate_on
if (counter_reset) capture_done <= 1'b0;
else if(inject_en) capture_done <= 1'b1;
if(TIMSTAMP_STRT_ON == "INJECT_EN")begin
if(~capture_done & inject_en) begin
clk_counter_lathched <= clk_counter;
if( hdr_flit && flit_out_wr) sent_time_stamp[wr_vc_bin] <= clk_counter;
end else if( hdr_flit && flit_out_wr) sent_time_stamp[wr_vc_bin] <= clk_counter_lathched;
end else begin
if( hdr_flit && flit_out_wr) sent_time_stamp[wr_vc_bin] <= clk_counter;
end
end
end//always
 
 
wire [X_Y_IN_HDR_WIDTH-1 : 0] src_x,src_y,dst_x,dst_y,x_offset,y_offset;
assign src_x = rsv_pck_src_x[rd_vc_bin];
assign src_y = rsv_pck_src_y[rd_vc_bin];
assign msg_class = rsv_pck_class[rd_vc_bin];
assign dst_x = current_x;
assign dst_y = current_y;
assign x_offset = (src_x> dst_x)? src_x - dst_x : dst_x - src_x;
assign y_offset = (src_y> dst_y)? src_y - dst_y : dst_y - src_y;
 
assign distance = (TOPOLOGY=="MESH")?x_offset+y_offset+1: 0;
assign time_stamp = rsv_time_stamp[rd_vc_bin] - flit_in[31 :0];
 
// synthesis translate_off
always @(posedge clk) begin
if(flit_out_wr && hdr_flit && wr_des_x_addr == current_x && wr_des_y_addr == current_y) $display("%t: Error: The source and destination address of injected packet is the same in router(%d,%d) ",$time, wr_des_x_addr ,wr_des_y_addr);
if(flit_in_wr && rd_hdr_flg[1] && rd_des_x_addr!= current_x && rd_des_y_addr!= current_y ) $display("%t: Error: packet with des(%d,%d) has been recieved in wrong router (%d,%d). ",$time,rd_des_x_addr, rd_des_y_addr, current_x , current_y);
end
// synthesis translate_on
 
endmodule
 
 
 
 
 
 
/**************************************
*
*
*
***************************************/
module send_traffic #(
parameter V = 4,
parameter C = 4, // number of flit class
parameter NX = 8, // number of node in x axis
parameter NY = 8, // number of node in y axis
parameter TRAFFIC = "RANDOM",
// "RANDOM", "TRANSPOSE1","TRANSPOSE2", "HOTSPOT", "BIT_REVERSE", "BIT_COMPLEMENT", "CUSTOM";
parameter CLASS_3_TRAFFIC_PATTERN= 1,
/*
0: 25 % class 0 , 75 % class 1
1: 50 % class 0 , 50 % class 1
2: 75 % class 0 , 25 % class 1
*/
//setting for hotspot
parameter HOTSPOT_PERCENTAGE = 3, //maximum 20
parameter HOTSOPT_NUM = 4, //maximum 4
parameter HOTSPOT_CORE_1 = 10,
parameter HOTSPOT_CORE_2 = 11,
parameter HOTSPOT_CORE_3 = 12,
parameter HOTSPOT_CORE_4 = 13,
parameter HOTSPOT_CORE_5 = 14,
parameter MAX_DELAY_BTWN_PCKTS = 100,
//total number of packets which is sent by a router
parameter TOTAL_PKT_PER_ROUTER = 200
)
(
pck_counter,
send_start,
sent_done,
current_x,
current_y,
delay,
clk,
reset,
dest_x,
dest_y,
class_hdr,
inject_en,
done
 
);
 
function integer log2;
input integer number; begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
localparam Xw=log2(NX),
Yw=log2(NY),
Dw=log2(MAX_DELAY_BTWN_PCKTS+1),
PCK_CNTw=log2(TOTAL_PKT_PER_ROUTER+1);
localparam NC = NX*NY, //flit width;
NCw = log2(NC),
Cw = log2(C),
Vw = log2(V);
localparam CLASS_IN_HDR_WIDTH =8;
input send_start,sent_done;
input [Xw-1 : 0] current_x;
input [Yw-1 : 0] current_y;
input [Dw-1 : 0] delay;
input clk,reset;
output reg [PCK_CNTw-1: 0] pck_counter;
output [Xw-1 : 0] dest_x;
output [Yw-1 : 0] dest_y;
output [CLASS_IN_HDR_WIDTH-1 :0] class_hdr;
output reg inject_en;
output reg done;
 
//generate the base addresses
localparam ST_NUMBER = 5,
IDEAL_ST = 1,
WARM_UP = 2,
SEND_ST = 4,
DELAY_ST = 8,
END_ST = 16;
reg [ST_NUMBER-1 : 0] ps;
reg [Dw-1 : 0] clk_delay_counter;
wire [NCw-1 : 0] dest_ip_num;
wire send_en;
//reg core_num;
//reg [ST_NUMBER-1:0] ps;
always @(posedge clk or posedge reset) begin
if(reset) begin
ps<=IDEAL_ST;
inject_en <= 1'b0;
clk_delay_counter<=0;
done <= 1'b0;
pck_counter<= 0;
clk_delay_counter<= dest_x+dest_y+2;
end else begin
case(ps)
IDEAL_ST: begin
inject_en <= 1'b0;
ps<=IDEAL_ST;
if(send_start & send_en) begin
ps<=WARM_UP;
end
if( ~send_en) done <=1;
end
WARM_UP: begin
clk_delay_counter<=clk_delay_counter-1'b1;
if(clk_delay_counter==0) ps<=SEND_ST;
end
SEND_ST: begin
done <= 1'b0;
inject_en <= 1'b1;
clk_delay_counter <=0;
if( sent_done )begin
pck_counter <= pck_counter+1'b1;
if(pck_counter==TOTAL_PKT_PER_ROUTER-1'b1) begin
ps <= END_ST;
inject_en <= 1'b0;
end
else if(delay>0) begin
inject_en <= 1'b0;
ps <= DELAY_ST;
end
end
end
DELAY_ST: begin
inject_en <= 1'b0;
clk_delay_counter <=clk_delay_counter +1'b1;
if(clk_delay_counter >= delay) begin
inject_en <= 1'b1;
ps<= SEND_ST;
end
end
END_ST: begin
inject_en <= 1'b0;
clk_delay_counter <=clk_delay_counter +1'b1;
ps<= IDEAL_ST;
done <= 1'b1;
end
default ps<=IDEAL_ST;
endcase
end//else
end
/***************************
 
traffic
 
*****************************/
 
 
wire [NCw-1 : 0] ip_num;
wire [Cw-1 : 0] rnd_class;
assign ip_num = current_y * NX + current_x;
genvar i;
generate
 
if(CLASS_3_TRAFFIC_PATTERN== 1) begin
 
pseudo_random #(
.MAX_RND (C-1),
.MAX_CORE (NC-1),
.MAX_NUM (TOTAL_PKT_PER_ROUTER)
)
rnd_gen
(
.core(ip_num),
.num(pck_counter),
.rnd(rnd_class),
.rnd_en(1'b1),
.reset(reset),
.clk(clk)
);
end else if(CLASS_3_TRAFFIC_PATTERN== 0) begin
pseudo_hotspot #(
.MAX_RND(1), // c=0 or 1
.MAX_CORE(NC-1),
.MAX_NUM(TOTAL_PKT_PER_ROUTER),
.HOTSPOT_PERCENTAGE(50),
.HOTSOPT_NUM(1),
.HOTSPOT_CORE_1(1)
)
rnd_class_gen
(
.core(ip_num),
.num(pck_counter),
.rnd(rnd_class ),
.rnd_en(1'b1),
.reset(reset),
.clk(clk)
);
end else begin
pseudo_hotspot #(
.MAX_RND (1), // c=0 or 1
.MAX_CORE (NC-1),
.MAX_NUM (TOTAL_PKT_PER_ROUTER),
.HOTSPOT_PERCENTAGE (50),
.HOTSOPT_NUM (1),
.HOTSPOT_CORE_1(0)
)
rnd_class_gen
(
.core(ip_num),
.num(pck_counter),
.rnd(rnd_class ),
.rnd_en(1'b1),
.reset(reset),
.clk(clk)
);
end
assign class_hdr ={{(CLASS_IN_HDR_WIDTH-Vw){1'b0}},rnd_class };
if (TRAFFIC == "RANDOM") begin
pseudo_random_no_core #(
.MAX_RND (NC-1),
.MAX_CORE (NC-1 ),
.MAX_NUM (TOTAL_PKT_PER_ROUTER)
)
rnd_dest_gen
(
.core (ip_num),
.num (pck_counter),
.rnd (dest_ip_num),
.rnd_en (1'b1),
.reset (reset),
.clk (clk)
 
);
assign dest_x = (dest_ip_num %NX );
assign dest_y = (dest_ip_num /NX );
end else if (TRAFFIC == "HOTSPOT") begin
pseudo_hotspot_no_core #(
.MAX_RND (NC-1 ),
.MAX_CORE (NC-1 ),
.MAX_NUM (TOTAL_PKT_PER_ROUTER),
.HOTSPOT_PERCENTAGE (HOTSPOT_PERCENTAGE), //maximum 25%
.HOTSOPT_NUM (HOTSOPT_NUM), //maximum 4
.HOTSPOT_CORE_1 (HOTSPOT_CORE_1),
.HOTSPOT_CORE_2 (HOTSPOT_CORE_2),
.HOTSPOT_CORE_3 (HOTSPOT_CORE_3),
.HOTSPOT_CORE_4 (HOTSPOT_CORE_4),
.HOTSPOT_CORE_5 (HOTSPOT_CORE_5)
)rnd_dest_gen
(
.core (ip_num),
.num (pck_counter),
.rnd (dest_ip_num),
.rnd_en(1'b1),
.reset (reset),
.clk (clk)
 
);
assign dest_x = (dest_ip_num %NX );
assign dest_y = (dest_ip_num /NX );
end else if( TRAFFIC == "TRANSPOSE1") begin
assign dest_x = NX-current_y-1;
assign dest_y = NY-current_x-1;
end else if( TRAFFIC == "TRANSPOSE2") begin :transpose2
assign dest_x = current_y;
assign dest_y = current_x;
end else if( TRAFFIC == "BIT_REVERSE") begin :bitreverse
wire [(Xw+Yw)-1 : 0] joint_addr, reverse_addr;
assign joint_addr = {current_x,current_y};
for(i=0; i<(Xw+Yw); i=i+1'b1) begin :lp//reverse the address
assign reverse_addr[i] = joint_addr [((Xw+Yw)-1)-i];
end
assign {dest_x,dest_y } = reverse_addr;
end else if( TRAFFIC == "BIT_COMPLEMENT") begin :bitcomp
assign dest_x = ~current_x;
assign dest_y = ~current_y;
end else if(TRAFFIC == "CUSTOM" )begin
/*
assign send_en = (current_x==0 && current_y==0);// core (0,0) sends packets to (7,7)
assign dest_x = 7;
assign dest_y = 7;
*/
reg [Xw-1 : 0]dest_xx;
reg [Yw-1 : 0]dest_yy;
reg send_enen;
always @(*) begin
send_enen=1'b0;
if((current_x==0) && (current_y== 0)) begin
dest_xx= 1; dest_yy= 1; send_enen=1'b1;
end
if((current_x==0) && (current_y== 1)) begin
dest_xx= 1; dest_yy= 2; send_enen=1'b1;
end
if((current_x==1) && (current_y== 0)) begin
dest_xx= 1; dest_yy= 7; send_enen=1'b1;
end
if((current_x==1) && (current_y== 1)) begin
dest_xx= 1; dest_yy= 6; send_enen=1'b1;
end
if((current_x==1) && (current_y== 2)) begin
dest_xx= 1; dest_yy= 5; send_enen=1'b1;
end
if((current_x==1) && (current_y== 3)) begin
dest_xx= 1; dest_yy= 4; send_enen=1'b1;
end
end
/*
0 0 1 1
0 1 1 2
1 0 1 7
1 1 1 6
1 2 1 5
1 3 1 4
*/
assign send_en = send_enen;
assign dest_y = dest_yy;
assign dest_x = dest_xx;
end
//check if destination address is valid
if(TRAFFIC != "CUSTOM" )begin
assign send_en = ({dest_x,dest_y} != {current_x,current_y} ) & (dest_x <= (NX-1)) & (dest_y <= (NY-1));
end
endgenerate
endmodule
 
 
mpsoc/src_noc/traffic_gen.v.old Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: mpsoc/src_peripheral/GCD/gcd.v =================================================================== --- mpsoc/src_peripheral/GCD/gcd.v (revision 27) +++ mpsoc/src_peripheral/GCD/gcd.v (nonexistent) @@ -1,184 +0,0 @@ -/************************ -* GCD -*************************/ - -module gcd #( -parameter GCDw=32 - -)( clk, reset, enable, in1, in2, done, gcd); - input clk, reset; - input [GCDw-1 : 0] in1, in2; - output [GCDw-1 : 0] gcd; - input enable; - output done; - wire ldG, ldP, ldQ, selP0, selQ0, selP, selQ; - wire AeqB, AltB; - - gcd_cu CU( - .clk (clk), - .reset (reset), - .AeqB (AeqB), - .AltB (AltB), - .enable (enable), - .ldG (ldG), - .ldP (ldP), - .ldQ (ldQ), - .selP0 (selP0), - .selQ0 (selQ0), - .selP (selP), - .selQ (selQ), - .done (done) - ); - - - gcd_dpu #( - .GCDw(GCDw) - )DPU( - .clk (clk), - .reset (reset), - .in1 (in1), - .in2 (in2), - .gcd (gcd), - .AeqB (AeqB), - .AltB (AltB), - .ldG (ldG), - .ldP (ldP), - .ldQ (ldQ), - .selP0 (selP0), - .selQ0 (selQ0), - .selP (selP), - .selQ (selQ) - ); - - -endmodule - - - - -/************************ -* gcd_cu -*************************/ - -module gcd_cu (clk, reset, ldG, ldP, ldQ, selP0, selQ0, selP, selQ, AeqB, AltB, done, enable); - input clk, reset; - input AeqB, AltB, enable; - output ldG, ldP, ldQ, selP0, selQ0, selP, selQ, done; - reg ldG, ldP, ldQ, selP0, selQ0, selP, selQ, done; - - - //State encoding - parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10; - reg [1:0] y; - always @ (posedge reset or posedge clk) begin - if (reset == 1) y <= S0; - else begin - case (y) - S0: begin if (enable == 1) y <= S1; - else y <= S0; - end - S1: begin if (AeqB == 1) y <= S2; - else y <= S1; - end - S2: begin if (enable == 0) y <= S0; - else y <= S2; - end - default: y <= S0; - endcase - end - end - - - always @ (y or enable or AeqB or AltB) begin - ldG = 1'b0; ldP = 1'b0; ldQ = 1'b0; - selP0 = 1'b0; - selQ0 = 1'b0; - selP = 1'b0; - selQ = 1'b0; - done = 1'b0; - case (y) - S0: begin - done = 1'b1; - if (enable == 1)begin - selP0 = 1; ldP = 1; selQ0 = 1; ldQ = 1; done = 0; - end - end - - S1: begin - if (AeqB == 1) begin - ldG = 1; - done = 1; - end - else if (AltB == 1) begin - ldQ = 1; - end - else begin - ldP = 1; selP = 1; selQ = 1; - end - end - S2: begin - ldG = 1; - done = 1; - end - default: ; - endcase - end - endmodule - - - -/************************ -* gcd_dpu -*************************/ - -module gcd_dpu #( - parameter GCDw=32 - -)( clk, reset, in1, in2, gcd, ldG, ldP, ldQ, selP0, selQ0, selP, selQ, AeqB, AltB); - input clk, reset; - input [GCDw-1:0] in1, in2; - output [GCDw-1:0] gcd; - input ldG, ldP, ldQ, selP0, selQ0, selP, selQ; - output AeqB, AltB; - reg [GCDw-1:0] reg_P, reg_Q; - wire [GCDw-1:0] wire_ALU; - reg [GCDw-1:0] gcd; - wire AeqB, AltB; - //RegP with Multiplex 2:1 - always @ (posedge clk or posedge reset)begin - if (reset == 1) reg_P <= 0; - else begin - if (ldP == 1)begin - if (selP0==1) reg_P <= in1; - else reg_P <= wire_ALU; - end - end - end - - //RegQ with Multiplex 2:1 - always @ (posedge clk or posedge reset) begin - if (reset == 1) reg_Q <= 0; - else begin - if (ldQ == 1)begin - if (selQ0==1) reg_Q <= in2; - else reg_Q <= wire_ALU; - end - end - end - - //RegG with enable signal - always @ (posedge clk or posedge reset)begin - if (reset == 1) gcd <= {GCDw{1'b0}}; - else begin - if (ldG == 1) gcd <= reg_P; - end - end - - //Comparator - assign AeqB = (reg_P == reg_Q)? 1'b1 : 1'b0; - assign AltB = (reg_P < reg_Q) ? 1'b1 : 1'b0; - - //Subtractor - assign wire_ALU = ((selP == 1) & (selQ == 1)) ? (reg_P - reg_Q) : (reg_Q - reg_P); -endmodule -
mpsoc/src_peripheral/GCD/gcd.v Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: mpsoc/src_peripheral/GCD/gcd_ip.v =================================================================== --- mpsoc/src_peripheral/GCD/gcd_ip.v (revision 27) +++ mpsoc/src_peripheral/GCD/gcd_ip.v (nonexistent) @@ -1,133 +0,0 @@ -module gcd_ip#( - parameter GCDw=32, - parameter Dw =GCDw, - parameter Aw =5, - parameter TAGw =3, - parameter SELw =4 -) -( - clk, - reset, - //wishbone bus interface - s_dat_i, - s_sel_i, - s_addr_i, - s_tag_i, - s_stb_i, - s_cyc_i, - s_we_i, - s_dat_o, - s_ack_o, - s_err_o, - s_rty_o - -); - input clk; - input reset; - - //wishbone bus interface - input [Dw-1 : 0] s_dat_i; - input [SELw-1 : 0] s_sel_i; - input [Aw-1 : 0] s_addr_i; - input [TAGw-1 : 0] s_tag_i; - input s_stb_i; - input s_cyc_i; - input s_we_i; - - output [Dw-1 : 0] s_dat_o; - output reg s_ack_o; - output s_err_o; - output s_rty_o; - - //Wishbone bus registers address - localparam DONE_REG_ADDR=0; - localparam IN_1_REG_ADDR=1; - localparam IN_2_REG_ADDR=2; - localparam GCD_REG_ADDR=3; - - assign s_err_o = 1'b0; - assign s_rty_o = 1'b0; - - wire[GCDw-1 :0] gcd; - reg [GCDw-1 :0] readdata,in1,in2; - wire done; - - assign s_dat_o =readdata; - - always @ (posedge clk or posedge reset) begin - if(reset) begin - s_ack_o <= 1'b0; - end else begin - s_ack_o <= (s_stb_i & ~s_ack_o); - end //reset - end//always - - always @ (posedge clk or posedge reset) begin - if(reset) begin - readdata <= 0; - in1 <= 0; - in2 <= 0; - end else begin - if(s_stb_i && s_we_i) begin //write regiters - if(s_addr_i==IN_1_REG_ADDR[Aw-1: 0]) in1 <= s_dat_i; - else if(s_addr_i==IN_2_REG_ADDR[Aw-1: 0]) in2 <= s_dat_i; - end //sa_stb_i && sa_we_i - else begin //read registers - if (s_addr_i==DONE_REG_ADDR) readdata<={{GCDw{1'b0}},done}; - if (s_addr_i==GCD_REG_ADDR) readdata<=gcd; - end - end //reset - end//always - - // start gcd calculation by writiing on in2 register - wire start=(s_stb_i && s_we_i && (s_addr_i==IN_2_REG_ADDR[Aw-1: 0])); - reg ps,ns; - reg gcd_reset,gcd_reset_next; - reg gcd_en,gcd_en_next; - - always @ (posedge clk or posedge reset) begin - if(reset) begin - ps<=1'b0; - gcd_reset<=1'b1; - gcd_en<=1'b0; - end else begin - ps<=ns; - gcd_en<=gcd_en_next; - gcd_reset<=gcd_reset_next; - end - end - - always @(*)begin - gcd_reset_next=1'b0; - gcd_en_next=1'b0; - ns=ps; - case(ps) - 1'b0:begin - if(start) begin - ns=1'b1; - gcd_reset_next=1'b1; - end - end - 1'b1:begin - gcd_en_next=1'b1; - ns=1'b0; - end - endcase - end - - - gcd #( - .GCDw(GCDw) - ) the_gcd - ( - .clk (clk), - .reset (gcd_reset), - .enable (gcd_en), - .in1 (in1), - .in2 (in2), - .done (done), - .gcd (gcd) - ); - -endmodule -
mpsoc/src_peripheral/GCD/gcd_ip.v Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: mpsoc/src_peripheral/jtag/jtag_intfc.v =================================================================== --- mpsoc/src_peripheral/jtag/jtag_intfc.v (revision 27) +++ mpsoc/src_peripheral/jtag/jtag_intfc.v (revision 28) @@ -142,7 +142,7 @@ wire start_source; wire [WR_RAMw :0] wr_pck_size; wire [X_Y_IN_HDR_WIDTH-1 :0] x_dest,y_dest; - wire [31: :0] memory_pointer; + wire [31 :0] memory_pointer; localparam SOURCEw=32+WR_RAMw+1+X_Y_IN_HDR_WIDTH+X_Y_IN_HDR_WIDTH;
/mpsoc/src_peripheral/jtag/jtag_wb/vjtag_wb.v
109,8 → 109,8
always @(*)begin
wb_addr_next= wb_addr;
if(wb_wr_addr_en) wb_addr_next <= data_out [AW-1 : 0];
else if (wb_addr_inc) wb_addr_next <= wb_addr +1'b1;
if(wb_wr_addr_en) wb_addr_next = data_out [AW-1 : 0];
else if (wb_addr_inc) wb_addr_next = wb_addr +1'b1;
end
/mpsoc/src_peripheral/ram/old/general_dual_port_ram.v File deleted
mpsoc/src_peripheral/ram/old/general_dual_port_ram.v Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: mpsoc/src_peripheral/ram/old/ram (copy).v =================================================================== --- mpsoc/src_peripheral/ram/old/ram (copy).v (revision 27) +++ mpsoc/src_peripheral/ram/old/ram (copy).v (nonexistent) @@ -1,455 +0,0 @@ -/********************************************************************* - - File: prog_ram.v - - Copyright (C) 2014 Alireza Monemi - - This program is free software: you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation, either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - - Purpose: - program ram. The ram is assigned with a ram id and can be programed - using quartus in system memory contents editor in order to program the chip - - Info: monemi@fkegraduate.utm.my - -****************************************************************/ - - -`timescale 1ns / 1ps - - - -module prog_ram_single_port #( - parameter Dw =32, - parameter Aw =10, - parameter TAGw =3, - parameter SELw =4, - parameter FPGA_FAMILY= "ALTERA", - parameter RAM_TAG_STRING ="2" - -) -( - clk, - reset, - - //wishbone bus interface - sa_dat_i, - sa_sel_i, - sa_addr_i, - sa_tag_i, - sa_stb_i, - sa_cyc_i, - sa_we_i, - sa_dat_o, - sa_ack_o, - sa_err_o, - sa_rty_o - -); - input clk; - input reset; - - - - //wishbone bus interface - input [Dw-1 : 0] sa_dat_i; - input [SELw-1 : 0] sa_sel_i; - input [Aw-1 : 0] sa_addr_i; - input [TAGw-1 : 0] sa_tag_i; - input sa_stb_i; - input sa_cyc_i; - input sa_we_i; - - output [Dw-1 : 0] sa_dat_o; - output sa_ack_o; - output sa_err_o; - output sa_rty_o; - - - - - wire [TAGw-1 : 0] sa_cti_i; - - assign sa_cti_i = sa_tag_i; - - - wire [Dw-1 : 0] data_a; - wire [Aw-1 : 0] addr_a; - wire we_a; - wire [(Dw-1) : 0] q_a; - reg sa_ack_classic, sa_ack_classic_next; - wire sa_ack_burst; - - assign sa_dat_o = q_a; - assign data_a = sa_dat_i ; - assign addr_a = sa_addr_i; - assign we_a = sa_stb_i & sa_we_i; - assign sa_ack_burst = sa_stb_i ; //the ack is registerd inside the master in burst mode - assign sa_err_o = 1'b0; - assign sa_rty_o = 1'b0; - - assign sa_ack_o = (sa_cti_i == 3'b000 ) ? sa_ack_classic : sa_ack_burst; - - - always @(*) begin - sa_ack_classic_next = (~sa_ack_o) & sa_stb_i; - end - - always @(posedge clk ) begin - if(reset) begin - sa_ack_classic <= 1'b0; - end else begin - sa_ack_classic <= sa_ack_classic_next; - end - end - -`ifdef MODEL_TECH - localparam INIT_FILE = {"../../sw/ram",RAM_TAG_STRING,".mif"}; -`else - localparam INIT_FILE = {"sw/ram",RAM_TAG_STRING,".mif"}; -`endif - - - -generate - if(FPGA_FAMILY == "ALTERA") begin :altera_atlsyncram - - localparam RAM_ID = {"ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=",RAM_TAG_STRING}; - - - - altsyncram #( - .operation_mode("SINGLE_PORT"), - .width_a(Dw), - .lpm_hint(RAM_ID), - .read_during_write_mode_mixed_ports("DONT_CARE"), - .widthad_a(Aw), - .width_byteena_a(4), - .init_file(INIT_FILE) - - ) ram_inst( - .clock0 (clk), - .address_a (addr_a), - .wren_a (we_a), - .data_a (data_a), - .q_a (q_a), - .byteena_a (sa_sel_i), - - .wren_b ( ), - .rden_a ( ), - .rden_b ( ), - .data_b ( ), - .address_b ( ), - .clock1 ( ), - .clocken0 ( ), - .clocken1 ( ), - .clocken2 ( ), - .clocken3 ( ), - .aclr0 ( ), - .aclr1 ( ), - .byteena_b ( ), - .addressstall_a ( ), - .addressstall_b ( ), - .q_b ( ), - .eccstatus ( ) - ); - - - - - end else begin : other_ram - - - - single_port_ram #( - .Dw(Dw), - .Aw(Aw) - ) - single_port_ram( - .data(data_a), - .addr(addr_a), - .we(we_a), - .clk(clk), - .q(q_a) - ); - - - end - endgenerate - - - - -endmodule - - - - -/********************************* - - prog_ram_dual_port - - -******************************/ - - -module prog_ram_dual_port #( - parameter Dw =32, - parameter Aw =10, - parameter TAGw =3 - ) - ( - clk, - reset, - sa_dat_i, sb_dat_i, - sa_addr_i, sb_addr_i, - sa_tag_i, sb_tag_i, - sa_stb_i,sb_stb_i, - sa_we_i,sb_we_i, - sa_dat_o, sb_dat_o, - sa_ack_o,sb_ack_o - ); - input clk; - input reset; - - input [Dw-1 : 0] sa_dat_i, sb_dat_i; - //input [SELw-1 : 0] sa_sel_i,sb_sel_i; - input [Aw-1 : 0] sa_addr_i, sb_addr_i; - input [TAGw-1 : 0] sa_tag_i, sb_tag_i; - input sa_stb_i,sb_stb_i; - input sa_we_i,sb_we_i; - - output [Dw-1 : 0] sa_dat_o, sb_dat_o; - output sa_ack_o,sb_ack_o; - - wire [TAGw-1 : 0] sa_cti_i, sb_cti_i; - - assign sa_cti_i = sa_tag_i; - assign sb_cti_i= sb_tag_i; - - wire [(Dw-1) :0] data_a, data_b; - wire [(Aw-1) :0] addr_a, addr_b; - wire we_a, we_b; - wire [(Dw-1) :0] q_a, q_b; - reg sa_ack_classic, sb_ack_classic,sa_ack_classic_next,sb_ack_classic_next; - wire sa_ack_burst,sb_ack_burst; - - assign sa_dat_o = q_a; - assign data_a = sa_dat_i ; - assign addr_a = sa_addr_i; - assign we_a = sa_stb_i & sa_we_i; - assign sa_ack_burst = sa_stb_i ; //the ack is registerd inside the master in burst mode - - - assign sa_ack_o = (sa_cti_i == 3'b000 ) ? sa_ack_classic : sa_ack_burst; - - - - - always @(*) begin - sa_ack_classic_next = (~sa_ack_o) & sa_stb_i; - end - - always @(posedge clk ) begin - if(reset) begin - sa_ack_classic <= 1'b0; - end else begin - sa_ack_classic <= sa_ack_classic_next; - end - end - - - - - assign sb_dat_o = q_b; - assign data_b = sb_dat_i ; - assign addr_b = sb_addr_i; - assign we_b = sb_stb_i & sb_we_i; - assign sb_ack_burst = sb_stb_i ; - assign sb_ack_o = (sb_cti_i == 3'b000 ) ? sb_ack_classic : sb_ack_burst; - - - - always @(*) begin - sb_ack_classic_next = (~sb_ack_o) & sb_stb_i; - end - - always @(posedge clk ) begin - if(reset) begin - sb_ack_classic <= 1'b0; - end else begin - sb_ack_classic <= sb_ack_classic_next; - end - end - - - dual_port_ram - #( - .Dw (Dw), - .Aw (Aw) - ) - the_ram - ( - .data_a (data_a), - .data_b (data_b), - .addr_a (addr_a), - .addr_b (addr_b), - .we_a (we_a), - .we_b (we_b), - .clk (clk), - .q_a (q_a), - .q_b (q_b)); - - - - - - - - -endmodule - - -/******************* - - dual_port_ram - -********************/ - - -// Quartus II Verilog Template -// True Dual Port RAM with single clock - - -module dual_port_ram -#( - parameter Dw=8, - parameter Aw=6 -) -( - data_a, - data_b, - addr_a, - addr_b, - we_a, - we_b, - clk, - q_a, - q_b -); - - - input [(Dw-1):0] data_a, data_b; - input [(Aw-1):0] addr_a, addr_b; - input we_a, we_b, clk; - output reg [(Dw-1):0] q_a, q_b; - - // Declare the RAM variable - reg [Dw-1:0] ram[2**Aw-1:0]; - - // Port A - always @ (posedge clk) - begin - if (we_a) - begin - ram[addr_a] <= data_a; - q_a <= data_a; - end - else - begin - q_a <= ram[addr_a]; - end - end - - // Port B - always @ (posedge clk) - begin - if (we_b) - begin - ram[addr_b] <= data_b; - q_b <= data_b; - end - else - begin - q_b <= ram[addr_b]; - end - end - - - /* - //synthesis translate_off - integer i; - initial begin - - for(i=0;i<2**Aw;i=i+1) - ram[i]=i+ (CORE_NUMBER << 25); - end //initial - - - //synthesis translate_on - */ -endmodule - - -/***************************** - - single_port_ram - - -*****************************/ - -// Quartus II Verilog Template -// Single port RAM with single read/write address - -module single_port_ram #( - parameter Dw=8, - parameter Aw=6 -) -( - data, - addr, - we, - clk, - q -); - - input [(Dw-1):0] data; - input [(Aw-1):0] addr; - input we, clk; - output [(Dw-1):0] q; - - // Declare the RAM variable - reg [Dw-1:0] ram[2**Aw-1:0]; - - // Variable to hold the registered read address - reg [Aw-1:0] addr_reg; - - always @ (posedge clk) - begin - // Write - if (we) - ram[addr] <= data; - - addr_reg <= addr; - end - - // Continuous assignment implies read returns NEW data. - // This is the natural behavior of the TriMatrix memory - // blocks in Single Port mode. - assign q = ram[addr_reg]; - -endmodule - -
mpsoc/src_peripheral/ram/old/ram (copy).v Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: mpsoc/src_peripheral/ram/old/test =================================================================== --- mpsoc/src_peripheral/ram/old/test (revision 27) +++ mpsoc/src_peripheral/ram/old/test (nonexistent) @@ -1,2697 +0,0 @@ -module byte_enabled_true_dual_port_ram #( - parameter int - BYTE_WIDTH = 8, - ADDRESS_WIDTH = 6, - BYTES = 4, - DATA_WIDTH_R = BYTE_WIDTH * BYTES -) -( - input [ADDRESS_WIDTH-1:0] addr1, - input [ADDRESS_WIDTH-1:0] addr2, - input [BYTES-1:0] be1, - input [BYTES-1:0] be2, - input [DATA_WIDTH_R-1:0] data_in1, - input [DATA_WIDTH_R-1:0] data_in2, - input we1, we2, clk, - output [DATA_WIDTH_R-1:0] data_out1, - output [DATA_WIDTH_R-1:0] data_out2 -); - -generate -if (BYTES==1) begin : byte_en1 - byte_enabled_true_dual_port_ram_1 - #( - .BYTE_WIDTH(BYTE_WIDTH), - .ADDRESS_WIDTH(ADDRESS_WIDTH) - ) - ram_inst - ( - .addr1(addr1), - .addr2(addr2), - .be1(be1), - .be2(be2), - .data_in1(data_in1), - .data_in2(data_in2), - .we1(we1), - .we2(we2), - .clk(clk), - .data_out1(data_out1), - .data_out2(data_out2) - ); -end -if (BYTES==2) begin : byte_en2 - byte_enabled_true_dual_port_ram_2 - #( - .BYTE_WIDTH(BYTE_WIDTH), - .ADDRESS_WIDTH(ADDRESS_WIDTH) - ) - ram_inst - ( - .addr1(addr1), - .addr2(addr2), - .be1(be1), - .be2(be2), - .data_in1(data_in1), - .data_in2(data_in2), - .we1(we1), - .we2(we2), - .clk(clk), - .data_out1(data_out1), - .data_out2(data_out2) - ); -end -if (BYTES==3) begin : byte_en3 - byte_enabled_true_dual_port_ram_3 - #( - .BYTE_WIDTH(BYTE_WIDTH), - .ADDRESS_WIDTH(ADDRESS_WIDTH) - ) - ram_inst - ( - .addr1(addr1), - .addr2(addr2), - .be1(be1), - .be2(be2), - .data_in1(data_in1), - .data_in2(data_in2), - .we1(we1), - .we2(we2), - .clk(clk), - .data_out1(data_out1), - .data_out2(data_out2) - ); -end -if (BYTES==4) begin : byte_en4 - byte_enabled_true_dual_port_ram_4 - #( - .BYTE_WIDTH(BYTE_WIDTH), - .ADDRESS_WIDTH(ADDRESS_WIDTH) - ) - ram_inst - ( - .addr1(addr1), - .addr2(addr2), - .be1(be1), - .be2(be2), - .data_in1(data_in1), - .data_in2(data_in2), - .we1(we1), - .we2(we2), - .clk(clk), - .data_out1(data_out1), - .data_out2(data_out2) - ); -end -if (BYTES==5) begin : byte_en5 - byte_enabled_true_dual_port_ram_5 - #( - .BYTE_WIDTH(BYTE_WIDTH), - .ADDRESS_WIDTH(ADDRESS_WIDTH) - ) - ram_inst - ( - .addr1(addr1), - .addr2(addr2), - .be1(be1), - .be2(be2), - .data_in1(data_in1), - .data_in2(data_in2), - .we1(we1), - .we2(we2), - .clk(clk), - .data_out1(data_out1), - .data_out2(data_out2) - ); -end -if (BYTES==6) begin : byte_en6 - byte_enabled_true_dual_port_ram_6 - #( - .BYTE_WIDTH(BYTE_WIDTH), - .ADDRESS_WIDTH(ADDRESS_WIDTH) - ) - ram_inst - ( - .addr1(addr1), - .addr2(addr2), - .be1(be1), - .be2(be2), - .data_in1(data_in1), - .data_in2(data_in2), - .we1(we1), - .we2(we2), - .clk(clk), - .data_out1(data_out1), - .data_out2(data_out2) - ); -end -if (BYTES==7) begin : byte_en7 - byte_enabled_true_dual_port_ram_7 - #( - .BYTE_WIDTH(BYTE_WIDTH), - .ADDRESS_WIDTH(ADDRESS_WIDTH) - ) - ram_inst - ( - .addr1(addr1), - .addr2(addr2), - .be1(be1), - .be2(be2), - .data_in1(data_in1), - .data_in2(data_in2), - .we1(we1), - .we2(we2), - .clk(clk), - .data_out1(data_out1), - .data_out2(data_out2) - ); -end -if (BYTES==8) begin : byte_en8 - byte_enabled_true_dual_port_ram_8 - #( - .BYTE_WIDTH(BYTE_WIDTH), - .ADDRESS_WIDTH(ADDRESS_WIDTH) - ) - ram_inst - ( - .addr1(addr1), - .addr2(addr2), - .be1(be1), - .be2(be2), - .data_in1(data_in1), - .data_in2(data_in2), - .we1(we1), - .we2(we2), - .clk(clk), - .data_out1(data_out1), - .data_out2(data_out2) - ); -end -if (BYTES==9) begin : byte_en9 - byte_enabled_true_dual_port_ram_9 - #( - .BYTE_WIDTH(BYTE_WIDTH), - .ADDRESS_WIDTH(ADDRESS_WIDTH) - ) - ram_inst - ( - .addr1(addr1), - .addr2(addr2), - .be1(be1), - .be2(be2), - .data_in1(data_in1), - .data_in2(data_in2), - .we1(we1), - .we2(we2), - .clk(clk), - .data_out1(data_out1), - .data_out2(data_out2) - ); -end -if (BYTES==10) begin : byte_en10 - byte_enabled_true_dual_port_ram_10 - #( - .BYTE_WIDTH(BYTE_WIDTH), - .ADDRESS_WIDTH(ADDRESS_WIDTH) - ) - ram_inst - ( - .addr1(addr1), - .addr2(addr2), - .be1(be1), - .be2(be2), - .data_in1(data_in1), - .data_in2(data_in2), - .we1(we1), - .we2(we2), - .clk(clk), - .data_out1(data_out1), - .data_out2(data_out2) - ); -end -if (BYTES==11) begin : byte_en11 - byte_enabled_true_dual_port_ram_11 - #( - .BYTE_WIDTH(BYTE_WIDTH), - .ADDRESS_WIDTH(ADDRESS_WIDTH) - ) - ram_inst - ( - .addr1(addr1), - .addr2(addr2), - .be1(be1), - .be2(be2), - .data_in1(data_in1), - .data_in2(data_in2), - .we1(we1), - .we2(we2), - .clk(clk), - .data_out1(data_out1), - .data_out2(data_out2) - ); -end -if (BYTES==12) begin : byte_en12 - byte_enabled_true_dual_port_ram_12 - #( - .BYTE_WIDTH(BYTE_WIDTH), - .ADDRESS_WIDTH(ADDRESS_WIDTH) - ) - ram_inst - ( - .addr1(addr1), - .addr2(addr2), - .be1(be1), - .be2(be2), - .data_in1(data_in1), - .data_in2(data_in2), - .we1(we1), - .we2(we2), - .clk(clk), - .data_out1(data_out1), - .data_out2(data_out2) - ); -end -if (BYTES==13) begin : byte_en13 - byte_enabled_true_dual_port_ram_13 - #( - .BYTE_WIDTH(BYTE_WIDTH), - .ADDRESS_WIDTH(ADDRESS_WIDTH) - ) - ram_inst - ( - .addr1(addr1), - .addr2(addr2), - .be1(be1), - .be2(be2), - .data_in1(data_in1), - .data_in2(data_in2), - .we1(we1), - .we2(we2), - .clk(clk), - .data_out1(data_out1), - .data_out2(data_out2) - ); -end -if (BYTES==14) begin : byte_en14 - byte_enabled_true_dual_port_ram_14 - #( - .BYTE_WIDTH(BYTE_WIDTH), - .ADDRESS_WIDTH(ADDRESS_WIDTH) - ) - ram_inst - ( - .addr1(addr1), - .addr2(addr2), - .be1(be1), - .be2(be2), - .data_in1(data_in1), - .data_in2(data_in2), - .we1(we1), - .we2(we2), - .clk(clk), - .data_out1(data_out1), - .data_out2(data_out2) - ); -end -if (BYTES==15) begin : byte_en15 - byte_enabled_true_dual_port_ram_15 - #( - .BYTE_WIDTH(BYTE_WIDTH), - .ADDRESS_WIDTH(ADDRESS_WIDTH) - ) - ram_inst - ( - .addr1(addr1), - .addr2(addr2), - .be1(be1), - .be2(be2), - .data_in1(data_in1), - .data_in2(data_in2), - .we1(we1), - .we2(we2), - .clk(clk), - .data_out1(data_out1), - .data_out2(data_out2) - ); -end -endgenerate -endmodule: byte_enabled_true_dual_port_ram - -module byte_enabled_true_dual_port_ram_1 #( - parameter int - BYTE_WIDTH = 8, - ADDRESS_WIDTH = 6, - BYTES = 1, - DATA_WIDTH_R = BYTE_WIDTH * BYTES -) -( - input [ADDRESS_WIDTH-1:0] addr1, - input [ADDRESS_WIDTH-1:0] addr2, - input [BYTES-1:0] be1, - input [BYTES-1:0] be2, - input [DATA_WIDTH_R-1:0] data_in1, - input [DATA_WIDTH_R-1:0] data_in2, - input we1, we2, clk, - output [DATA_WIDTH_R-1:0] data_out1, - output [DATA_WIDTH_R-1:0] data_out2 -); - -wire [BYTE_WIDTH-1 : 0] data_in_sep1[BYTES-1 : 0]; -wire [BYTE_WIDTH-1 : 0] data_in_sep2[BYTES-1 : 0]; - -genvar i; -generate -for (i=0;i
mpsoc/src_peripheral/ram/old/test Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: mpsoc/src_peripheral/ram/old/Altera_single_port_ram.v =================================================================== --- mpsoc/src_peripheral/ram/old/Altera_single_port_ram.v (revision 27) +++ mpsoc/src_peripheral/ram/old/Altera_single_port_ram.v (nonexistent) @@ -1,184 +0,0 @@ -/********************************************************************* - - File: Altera_single_port_ram.v - - Copyright (C) 2014 Alireza Monemi - - This program is free software: you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation, either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - - Purpose: - Altera_single_port_ram. The ram is assigned with a ram id and can be programed - using quartus in system memory contents editor in order to program the chip - - Info: monemi@fkegraduate.utm.my - -****************************************************************/ - - -`timescale 1ns / 1ps - - - -module Altera_single_port_ram #( - parameter Dw =32, - parameter Aw =10, - parameter TAGw =3, - parameter SELw =4, - parameter CTIw = 3, - parameter BTEw = 2, - parameter RAM_TAG_STRING="2" //use for programming the memory at run time - -) -( - clk, - reset, - - //wishbone bus interface - sa_dat_i, - sa_sel_i, - sa_addr_i, - sa_tag_i, - sa_cti_i, - sa_bte_i, - sa_stb_i, - sa_cyc_i, - sa_we_i, - sa_dat_o, - sa_ack_o, - sa_err_o, - sa_rty_o - -); - input clk; - input reset; - - - - //wishbone bus interface - input [Dw-1 : 0] sa_dat_i; - input [SELw-1 : 0] sa_sel_i; - input [Aw-1 : 0] sa_addr_i; - input [TAGw-1 : 0] sa_tag_i; - input sa_stb_i; - input sa_cyc_i; - input sa_we_i; - input [CTIw-1 : 0] sa_cti_i; - input [BTEw-1 : 0] sa_bte_i; - - output [Dw-1 : 0] sa_dat_o; - output sa_ack_o; - output sa_err_o; - output sa_rty_o; - - - - - wire [TAGw-1 : 0] sa_cti_i; - - - - wire [Dw-1 : 0] data_a; - wire [Aw-1 : 0] addr_a; - wire we_a; - wire [(Dw-1) : 0] q_a; - reg sa_ack_classic, sa_ack_classic_next; - wire sa_ack_ni_burst; - - assign sa_dat_o = q_a; - assign data_a = sa_dat_i ; - assign addr_a = sa_addr_i; - assign we_a = sa_stb_i & sa_we_i; - assign sa_ack_ni_burst = sa_stb_i ; //the ack is registerd inside the master in burst mode - assign sa_err_o = 1'b0; - assign sa_rty_o = 1'b0; - - - - // 3'b100 is reserved in wb4 interface. It used for ni - assign sa_ack_o = (sa_cti_i == 3'b100 ) ? sa_ack_ni_burst: sa_ack_classic; - - localparam CLASSIC =3'b000, - CONSTANT_BURST = 3'b001, - INCRMNT_BURST = 3'b010, - END_BURST = 3'b111; - - always @(*) begin - case(sa_cti_i) - CLASSIC: sa_ack_classic_next = (~sa_ack_o) & sa_stb_i; - default: sa_ack_classic_next = sa_stb_i; - endcase - end - - always @(posedge clk ) begin - if(reset) begin - sa_ack_classic <= 1'b0; - end else begin - sa_ack_classic <= sa_ack_classic_next; - end - end - -`ifdef MODEL_TECH - localparam INIT_FILE = {"../../sw/ram",RAM_TAG_STRING,".mif"}; -`else - localparam INIT_FILE = {"sw/ram",RAM_TAG_STRING,".mif"}; -`endif - - - - - - localparam RAM_ID = {"ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=",RAM_TAG_STRING}; - - - - altsyncram #( - .operation_mode("SINGLE_PORT"), - .width_a(Dw), - .lpm_hint(RAM_ID), - .read_during_write_mode_mixed_ports("DONT_CARE"), - .widthad_a(Aw), - .width_byteena_a(4), - .init_file(INIT_FILE) - - ) ram_inst( - .clock0 (clk), - .address_a (addr_a), - .wren_a (we_a), - .data_a (data_a), - .q_a (q_a), - .byteena_a (sa_sel_i), - - .wren_b ( ), - .rden_a ( ), - .rden_b ( ), - .data_b ( ), - .address_b ( ), - .clock1 ( ), - .clocken0 ( ), - .clocken1 ( ), - .clocken2 ( ), - .clocken3 ( ), - .aclr0 ( ), - .aclr1 ( ), - .byteena_b ( ), - .addressstall_a ( ), - .addressstall_b ( ), - .q_b ( ), - .eccstatus ( ) - ); - -endmodule - -
mpsoc/src_peripheral/ram/old/Altera_single_port_ram.v Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: mpsoc/src_peripheral/ram/old/Altera_single_port_ram2.v =================================================================== --- mpsoc/src_peripheral/ram/old/Altera_single_port_ram2.v (revision 27) +++ mpsoc/src_peripheral/ram/old/Altera_single_port_ram2.v (nonexistent) @@ -1,416 +0,0 @@ -/********************************************************************* - - File: Altera_single_port_ram.v - - Copyright (C) 2014 Alireza Monemi - - This program is free software: you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation, either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - - Purpose: - Altera_single_port_ram. The ram is assigned with a ram id and can be - read/written using jtag_man - - Info: monemi@fkegraduate.utm.my - -****************************************************************/ - - -`timescale 1ns / 1ps - - - -module Altera_single_port_ram2 #( - parameter Dw =32, - parameter Aw =10, - parameter TAGw =3, - parameter SELw =4, - parameter CTIw = 3, - parameter BTEw = 2, - parameter RAM_TAG_STRING="2" //use for programming the memory at run time - -) -( - clk, - reset, - - //wishbone bus interface - sa_dat_i, - sa_sel_i, - sa_addr_i, - sa_tag_i, - sa_cti_i, - sa_bte_i, - sa_stb_i, - sa_cyc_i, - sa_we_i, - sa_dat_o, - sa_ack_o, - sa_err_o, - sa_rty_o - -); - input clk; - input reset; - - - function integer log2; - input integer number; begin - log2=0; - while(2**log2
mpsoc/src_peripheral/ram/old/Altera_single_port_ram2.v Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: mpsoc/src_peripheral/ram/old/gen.pl =================================================================== --- mpsoc/src_peripheral/ram/old/gen.pl (revision 27) +++ mpsoc/src_peripheral/ram/old/gen.pl (nonexistent) @@ -1,261 +0,0 @@ -#! /usr/bin/perl -w -my $B=16; - - - - -my $file= 'module byte_enabled_true_dual_port_ram #( - parameter int - BYTE_WIDTH = 8, - ADDRESS_WIDTH = 6, - BYTES = 4, - DATA_WIDTH_R = BYTE_WIDTH * BYTES -) -( - input [ADDRESS_WIDTH-1:0] addr1, - input [ADDRESS_WIDTH-1:0] addr2, - input [BYTES-1:0] be1, - input [BYTES-1:0] be2, - input [DATA_WIDTH_R-1:0] data_in1, - input [DATA_WIDTH_R-1:0] data_in2, - input we1, we2, clk, - output [DATA_WIDTH_R-1:0] data_out1, - output [DATA_WIDTH_R-1:0] data_out2 -); - -generate -'; - -for (my $i=1; $i<$B; $i++){ - -$file=$file."if (BYTES==$i) begin : byte_en$i - byte_enabled_true_dual_port_ram_$i - #( - .BYTE_WIDTH(BYTE_WIDTH), - .ADDRESS_WIDTH(ADDRESS_WIDTH) - ) - ram_inst - ( - .addr1(addr1), - .addr2(addr2), - .be1(be1), - .be2(be2), - .data_in1(data_in1), - .data_in2(data_in2), - .we1(we1), - .we2(we2), - .clk(clk), - .data_out1(data_out1), - .data_out2(data_out2) - ); -end -"; -} -$file=$file."endgenerate -endmodule: byte_enabled_true_dual_port_ram\n"; - - - - -for (my $i=1; $i<$B; $i++){ - - -$file=$file." -module byte_enabled_true_dual_port_ram_$i #( - parameter int - BYTE_WIDTH = 8, - ADDRESS_WIDTH = 6, - BYTES = $i, - DATA_WIDTH_R = BYTE_WIDTH * BYTES -) -( - input [ADDRESS_WIDTH-1:0] addr1, - input [ADDRESS_WIDTH-1:0] addr2, - input [BYTES-1:0] be1, - input [BYTES-1:0] be2, - input [DATA_WIDTH_R-1:0] data_in1, - input [DATA_WIDTH_R-1:0] data_in2, - input we1, we2, clk, - output [DATA_WIDTH_R-1:0] data_out1, - output [DATA_WIDTH_R-1:0] data_out2 -); - -wire [BYTE_WIDTH-1 : 0] data_in_sep1[BYTES-1 : 0]; -wire [BYTE_WIDTH-1 : 0] data_in_sep2[BYTES-1 : 0]; - -genvar i; -generate -for (i=0;i
mpsoc/src_peripheral/ram/old/gen.pl Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: mpsoc/src_peripheral/ram/old/Altera_dual_port_ram.v =================================================================== --- mpsoc/src_peripheral/ram/old/Altera_dual_port_ram.v (revision 27) +++ mpsoc/src_peripheral/ram/old/Altera_dual_port_ram.v (nonexistent) @@ -1,261 +0,0 @@ -/********************************************************************* - - File: Altera_dual_port_ram.v - - Copyright (C) 2014 Alireza Monemi - - This program is free software: you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation, either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - - Purpose: - Altera_dual_port_ram. - - Info: monemi@fkegraduate.utm.my - -****************************************************************/ - - -`timescale 1ns / 1ps - - - -module Altera_dual_port_ram #( - parameter Dw =32, - parameter Aw =10, - parameter TAGw =3, - parameter SELw =4, - parameter CTIw = 3, - parameter BTEw = 2, - parameter RAM_TAG_STRING =0 // used only for initialling the memory - - -) -( - clk, - reset, - - //wishbone bus interface - sa_dat_i, - sa_sel_i, - sa_addr_i, - sa_tag_i, - sa_cti_i, - sa_bte_i, - sa_stb_i, - sa_cyc_i, - sa_we_i, - sa_dat_o, - sa_ack_o, - sa_err_o, - sa_rty_o, - - //wishbone bus interface - sb_dat_i, - sb_sel_i, - sb_addr_i, - sb_tag_i, - sb_cti_i, - sb_bte_i, - sb_stb_i, - sb_cyc_i, - sb_we_i, - sb_dat_o, - sb_ack_o, - sb_err_o, - sb_rty_o - - -); - input clk; - input reset; - - - function integer log2; - input integer number; begin - log2=0; - while(2**log2
mpsoc/src_peripheral/ram/old/Altera_dual_port_ram.v Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: mpsoc/src_peripheral/ram/old/general_single_port_ram.v =================================================================== --- mpsoc/src_peripheral/ram/old/general_single_port_ram.v (revision 27) +++ mpsoc/src_peripheral/ram/old/general_single_port_ram.v (nonexistent) @@ -1,187 +0,0 @@ -/********************************************************************* - - File: general_single_port_ram.v - - Copyright (C) 2014 Alireza Monemi - - This program is free software: you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation, either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - - Purpose: - ram_single_port. General single port ram. Does not support - byte enable - - Info: monemi@fkegraduate.utm.my - -****************************************************************/ - - -`timescale 1ns / 1ps - - - -module general_single_port_ram #( - parameter Dw =32, - parameter Aw =10, - parameter TAGw =3 - -) -( - clk, - reset, - - //wishbone bus interface - sa_dat_i, - // sa_sel_i, - sa_addr_i, - sa_tag_i, - sa_stb_i, - sa_cyc_i, - sa_we_i, - sa_dat_o, - sa_ack_o, - sa_err_o, - sa_rty_o - -); - input clk; - input reset; - - - - //wishbone bus interface - input [Dw-1 : 0] sa_dat_i; - // input [SELw-1 : 0] sa_sel_i; - input [Aw-1 : 0] sa_addr_i; - input [TAGw-1 : 0] sa_tag_i; - input sa_stb_i; - input sa_cyc_i; - input sa_we_i; - - output [Dw-1 : 0] sa_dat_o; - output sa_ack_o; - output sa_err_o; - output sa_rty_o; - - - - - wire [TAGw-1 : 0] sa_cti_i; - - assign sa_cti_i = sa_tag_i; - - - wire [Dw-1 : 0] data_a; - wire [Aw-1 : 0] addr_a; - wire we_a; - wire [(Dw-1) : 0] q_a; - reg sa_ack_classic, sa_ack_classic_next; - wire sa_ack_burst; - - assign sa_dat_o = q_a; - assign data_a = sa_dat_i ; - assign addr_a = sa_addr_i; - assign we_a = sa_stb_i & sa_we_i; - assign sa_ack_burst = sa_stb_i ; //the ack is registerd inside the master in burst mode - assign sa_err_o = 1'b0; - assign sa_rty_o = 1'b0; - - assign sa_ack_o = (sa_cti_i == 3'b000 ) ? sa_ack_classic : sa_ack_burst; - - - always @(*) begin - sa_ack_classic_next = (~sa_ack_o) & sa_stb_i; - end - - always @(posedge clk ) begin - if(reset) begin - sa_ack_classic <= 1'b0; - end else begin - sa_ack_classic <= sa_ack_classic_next; - end - end - - - - - single_port_ram #( - .Dw(Dw), - .Aw(Aw) - ) - single_port_ram( - .data(data_a), - .addr(addr_a), - .we(we_a), - .clk(clk), - .q(q_a) - ); - - - - - -endmodule - - - -/***************************** - - single_port_ram - - -*****************************/ - -// Quartus II Verilog Template -// Single port RAM with single read/write address - -module single_port_ram #( - parameter Dw=8, - parameter Aw=6 -) -( - data, - addr, - we, - clk, - q -); - - input [(Dw-1):0] data; - input [(Aw-1):0] addr; - input we, clk; - output [(Dw-1):0] q; - - // Declare the RAM variable - reg [Dw-1:0] ram[2**Aw-1:0]; - - // Variable to hold the registered read address - reg [Aw-1:0] addr_reg; - - always @ (posedge clk) - begin - // Write - if (we) - ram[addr] <= data; - - addr_reg <= addr; - end - - // Continuous assignment implies read returns NEW data. - // This is the natural behavior of the TriMatrix memory - // blocks in Single Port mode. - assign q = ram[addr_reg]; - -endmodule - -
mpsoc/src_peripheral/ram/old/general_single_port_ram.v Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: mpsoc/src_verilator/noc_connection.sv =================================================================== --- mpsoc/src_verilator/noc_connection.sv (revision 27) +++ mpsoc/src_verilator/noc_connection.sv (revision 28) @@ -59,6 +59,7 @@ `define INCLUDE_PARAM `include"parameter.v" + localparam CONGw= (CONGESTION_INDEX==3)? 3: (CONGESTION_INDEX==5)? 3: @@ -72,7 +73,7 @@ P_1 = P-1 , Fw = 2+V+Fpay, //flit width; PFw = P * Fw, - NC = NX * NY, //number of cores + NC = (TOPOLOGY=="RING")? NX : NX*NY, //number of cores NCFw = NC * Fw, NCV = NC * V; @@ -110,7 +111,45 @@ genvar x,y; generate + if( TOPOLOGY == "RING") begin : ring + for (x=0; x
/mpsoc/src_verilator/parameter.h
2,10 → 2,10
#define INCLUDE_PARAM
 
#define V 4
#define B 4
#define B 5
#define NX 8
#define NY 8
#define C 1
#define C 4
#define Fpay 32
#define MUX_TYPE "ONE_HOT"
#define VC_REALLOCATION_TYPE "NONATOMIC"
13,23 → 13,23
#define FIRST_ARBITER_EXT_P_EN 0
#define TOPOLOGY "MESH"
#define ROUTE_NAME "XY"
#define C0_p 100
#define C1_p 0
#define C2_p 0
#define C3_p 0
#define C0_p 25
#define C1_p 25
#define C2_p 25
#define C3_p 25
#define TRAFFIC "RANDOM"
#define HOTSPOT_PERCENTAGE 3
#define HOTSOPT_NUM 4
#define HOTSPOT_CORE_1 9
#define HOTSPOT_CORE_2 25
#define HOTSPOT_CORE_3 11
#define HOTSPOT_CORE_4 27
#define HOTSPOT_CORE_1 18
#define HOTSPOT_CORE_2 50
#define HOTSPOT_CORE_3 22
#define HOTSPOT_CORE_4 54
#define HOTSPOT_CORE_5 18
#define MAX_PCK_NUM 128000
#define MAX_PCK_NUM 256000
#define MAX_SIM_CLKs 100000
#define MAX_PCK_SIZ 10
#define TIMSTMP_FIFO_NUM 64
#define PACKET_SIZE 2
#define TIMSTMP_FIFO_NUM 8
#define PACKET_SIZE 4
#define DEBUG_EN 1
#define ROUTE_SUBFUNC "NORTH_LAST"
#define AVC_ATOMIC_EN 0
37,10 → 37,10
#define STND_DEV_EN 0
#define AVG_LATENCY_METRIC "HEAD_2_TAIL"
#define ADD_PIPREG_AFTER_CROSSBAR 0
#define ADD_PIPREG_BEFORE_CROSSBAR 0
#define CVw (C==0)? V : C * V
#define CLASS_SETTING 8'b11111111
#define ESCAP_VC_MASK 1
#define CLASS_SETTING "16'b111111111111111"
#define ESCAP_VC_MASK 4'b0001
#define SSA_EN "NO"
 
#endif
/mpsoc/src_verilator/parameter.v
1,35 → 1,35
`ifdef INCLUDE_PARAM
 
parameter V=4;
parameter P=5;
parameter B=4;
parameter TOPOLOGY="MESH";
parameter P=(TOPOLOGY=="RING")? 3 : 5;
parameter B=5;
parameter NX=8;
parameter NY=8;
parameter C=1;
parameter C=4;
parameter Fpay=32;
parameter MUX_TYPE="ONE_HOT";
parameter VC_REALLOCATION_TYPE="NONATOMIC";
parameter COMBINATION_TYPE="COMB_NONSPEC";
parameter FIRST_ARBITER_EXT_P_EN=0;
parameter TOPOLOGY="MESH";
parameter ROUTE_NAME="XY";
parameter CONGESTION_INDEX=3;
parameter C0_p=100;
parameter C1_p=0;
parameter C2_p=0;
parameter C3_p=0;
parameter C0_p=25;
parameter C1_p=25;
parameter C2_p=25;
parameter C3_p=25;
parameter TRAFFIC="RANDOM";
parameter HOTSPOT_PERCENTAGE=3;
parameter HOTSOPT_NUM=4;
parameter HOTSPOT_CORE_1=9;
parameter HOTSPOT_CORE_2=25;
parameter HOTSPOT_CORE_3=11;
parameter HOTSPOT_CORE_4=27;
parameter HOTSPOT_CORE_1=18;
parameter HOTSPOT_CORE_2=50;
parameter HOTSPOT_CORE_3=22;
parameter HOTSPOT_CORE_4=54;
parameter HOTSPOT_CORE_5=18;
parameter MAX_PCK_NUM=128000;
parameter MAX_PCK_NUM=256000;
parameter MAX_SIM_CLKs=100000;
parameter MAX_PCK_SIZ=10;
parameter TIMSTMP_FIFO_NUM=64;
parameter TIMSTMP_FIFO_NUM=8;
parameter ROUTE_TYPE = (ROUTE_NAME == "XY" || ROUTE_NAME == "TRANC_XY" )? "DETERMINISTIC" :
(ROUTE_NAME == "DUATO" || ROUTE_NAME == "TRANC_DUATO" )? "FULL_ADAPTIVE": "PAR_ADAPTIVE";
parameter DEBUG_EN=1;
37,10 → 37,10
parameter AVC_ATOMIC_EN= 0;
parameter AVG_LATENCY_METRIC= "HEAD_2_TAIL";
parameter ADD_PIPREG_AFTER_CROSSBAR= 0;
parameter ADD_PIPREG_BEFORE_CROSSBAR= 0;
parameter CVw=(C==0)? V : C * V;
parameter [CVw-1: 0] CLASS_SETTING = 8'b11111111;
parameter [V-1 : 0] ESCAP_VC_MASK=1;
parameter [CVw-1: 0] CLASS_SETTING = 16'b111111111111111;
parameter [V-1 : 0] ESCAP_VC_MASK=4'b0001;
parameter SSA_EN= "NO";
 
`endif
/mpsoc/src_verilator/router_verilator.v
1,4 → 1,4
module router_verilator
module router_verilator
(
current_x,
current_y,
73,7 → 73,7
 
router # (
.V(V),
.V(V),
.P(P),
.B(B),
.NX(NX),
93,10 → 93,10
.CONGw(CONGw),
.DEBUG_EN(DEBUG_EN),
.ADD_PIPREG_AFTER_CROSSBAR(ADD_PIPREG_AFTER_CROSSBAR),
.ADD_PIPREG_BEFORE_CROSSBAR(ADD_PIPREG_BEFORE_CROSSBAR),
.CVw(CVw),
.CLASS_SETTING(CLASS_SETTING),
.ESCAP_VC_MASK(ESCAP_VC_MASK)
.ESCAP_VC_MASK(ESCAP_VC_MASK),
.SSA_EN(SSA_EN)
)
/mpsoc/src_verilator/testbench.cpp
7,12 → 7,16
#include "Vrouter.h" // From Verilating "router.v"
#include "Vnoc.h"
#include "Vtraffic.h"
 
 
 
 
#include "parameter.h"
//#include "traffic_tabel.h"
 
 
#define NC (NX*NY)
#define RATIO_INIT 5
#define RATIO_INIT 2
 
unsigned char FIXED_SRC_DST_PAIR;
 
353,7 → 357,8
sum_clk_pow2+=(double)clk_num_h2h * (double) clk_num_h2h;
sum_clk_pow2_per_class[class_num]+=(double)clk_num_h2h * (double) clk_num_h2h;
#endif
sum_clk_per_hop+= ((double)clk_num_h2h/(double)distance);
sum_clk_per_hop+= ((double)clk_num_h2h/(double)distance);
total_pck_num_per_class[class_num]+=1;
sum_clk_h2h_per_class[class_num]+=clk_num_h2h ;
sum_clk_h2t_per_class[class_num]+=clk_num_h2t ;
412,11 → 417,13
sprintf(file_name,"%s_all.txt",out_file_name);
//update_file(file_name ,ratio,avg_latency );
if(strcmp (AVG_LATENCY_METRIC,"HEAD_2_TAIL")==0){
printf(" Total number of packet = %d \n average latency per hop = %f \n average latency = %f\n",total_pck_num,avg_latency_per_hop,avg_latency_flit);
printf(" Total number of packet = %d \n average latency per hop = %f \n average latency = %f\n",total_pck_num,avg_latency_per_hop,avg_latency_pck);
update_file(file_name ,avg_throughput,avg_latency_pck);
}else{
printf(" Total number of packet = %d \n average latency per hop = %f \n average latency = %f\n",total_pck_num,avg_latency_per_hop,avg_latency_flit);
update_file(file_name ,avg_throughput,avg_latency_flit);
}else{
printf(" Total number of packet = %d \n average latency per hop = %f \n average latency = %f\n",total_pck_num,avg_latency_per_hop,avg_latency_pck);
update_file(file_name ,avg_throughput,avg_latency_pck);
}
//fwrite(fp,"%d,%f,%f,%f,",total_pck_num,avg_latency_per_hop,avg_latency,max_latency_per_hop);
min_avg_latency_per_class=1000000;
426,16 → 433,20
avg_latency_pck = (total_pck_num_per_class[i]>0)? (double)sum_clk_h2t_per_class[i]/total_pck_num_per_class[i]:0;
avg_latency_per_hop = (total_pck_num_per_class[i]>0)? (double)sum_clk_per_hop_per_class[i]/total_pck_num_per_class[i]:0;
if(strcmp (AVG_LATENCY_METRIC,"HEAD_2_TAIL")==0){
printf ("\nclass : %d \n",i);
printf (" Total number of packet = %d \n avg_throughput = %f \n average latency per hop = %f \n average latency = %f\n",total_pck_num_per_class[i],avg_throughput,avg_latency_per_hop,avg_latency_flit);
sprintf(file_name,"%s_c%u.txt",out_file_name,i);
update_file( file_name,avg_throughput,avg_latency_flit );
}else{
printf ("\nclass : %d \n",i);
printf ("\nclass : %d \n",i);
printf (" Total number of packet = %d \n avg_throughput = %f \n average latency per hop = %f \n average latency = %f\n",total_pck_num_per_class[i],avg_throughput,avg_latency_per_hop,avg_latency_pck);
sprintf(file_name,"%s_c%u.txt",out_file_name,i);
update_file( file_name,avg_throughput,avg_latency_pck );
}else{
 
printf ("\nclass : %d \n",i);
printf (" Total number of packet = %d \n avg_throughput = %f \n average latency per hop = %f \n average latency = %f\n",total_pck_num_per_class[i],avg_throughput,avg_latency_per_hop,avg_latency_flit);
sprintf(file_name,"%s_c%u.txt",out_file_name,i);
update_file( file_name,avg_throughput,avg_latency_flit );
 
 
 
}
if(min_avg_latency_per_class > avg_latency_flit) min_avg_latency_per_class=avg_latency_flit;
 
472,7 → 483,7
printf ("\tAVC_ATOMIC_EN:%d \n", AVC_ATOMIC_EN);
printf ("\tCongestion Index:%d \n",CONGESTION_INDEX);
printf ("\tADD_PIPREG_AFTER_CROSSBAR:%d\n",ADD_PIPREG_AFTER_CROSSBAR);
printf ("\tADD_PIPREG_BEFORE_CROSSBAR:%d\n",ADD_PIPREG_BEFORE_CROSSBAR);
 
 
#if(DEBUG_EN)
498,6 → 509,7
printf ("\t Simulation timeout =%d\n", MAX_SIM_CLKs);
printf ("\t Simulation ends on total packet num of =%d\n", MAX_PCK_NUM);
printf ("\tPacket size: %u flits\n",PACKET_SIZE);
printf ("\t SSA_EN enabled:%s \n",SSA_EN);
}
 
 
550,7 → 562,7
int update_ratio(){
//printf("current_avg_latency=%f\n",current_avg_latency_flit);
if(current_avg_latency_flit <= (2*first_avg_latency_flit)) ratio+=2;
else if(current_avg_latency_flit <= (6*first_avg_latency_flit)) ratio+=1;
else if(current_avg_latency_flit <= (4*first_avg_latency_flit)) ratio+=1;
else return 1;
return 0;
}
692,8 → 704,19
(*dest_y) = ((current_y + ((NY/2)-1))%NY);
 
 
}
} else if( strcmp(TRAFFIC ,"CUSTOM") == 0){
//[(x+(k/2-1)) mod k, (y+(k/2-1)) mod k],
if(current_x ==0 && current_y == 0 ){
(*dest_x) = NX-1;
(*dest_y) = NY-1;
}else{// make it unvalid
(*dest_x) = current_x;
(*dest_y) = current_y;
 
}
 
}
 
else printf ("traffic %s is an unsupported traffic pattern\n",TRAFFIC);
 
}
/mpsoc/src_verilator/traffic_gen_verilator.v
8,7 → 8,7
module traffic_gen_verilator (
//input
ratio,
pck_size,
pck_size_in,
current_x,
current_y,
dest_x,
82,7 → 82,7
input [Xw-1 :0] dest_x;
input [Yw-1 :0] dest_y;
output [PCK_CNTw-1 :0] pck_number;
input [PCK_SIZw-1 :0] pck_size;
input [PCK_SIZw-1 :0] pck_size_in;
output sent_done;
output hdr_flit_sent;
input [Cw-1 :0] pck_class_in;
100,28 → 100,14
 
traffic_gen #(
.V(V),
.P(P),
.B(B),
.NX(NX),
.NY(NY),
.Fpay(Fpay),
.C(C),
.VC_REALLOCATION_TYPE(VC_REALLOCATION_TYPE),
.TOPOLOGY(TOPOLOGY),
.ROUTE_NAME(ROUTE_NAME),
.ROUTE_TYPE(ROUTE_TYPE),
.TRAFFIC(TRAFFIC),
.HOTSPOT_PERCENTAGE(HOTSPOT_PERCENTAGE),
.HOTSOPT_NUM(HOTSOPT_NUM),
.HOTSPOT_CORE_1(HOTSPOT_CORE_1),
.HOTSPOT_CORE_2(HOTSPOT_CORE_2),
.HOTSPOT_CORE_3(HOTSPOT_CORE_3),
.HOTSPOT_CORE_4(HOTSPOT_CORE_4),
.HOTSPOT_CORE_5(HOTSPOT_CORE_5),
.C(C),
.C0_p(C0_p),
.C1_p(C1_p),
.C2_p(C2_p),
.C3_p(C3_p),
.MAX_PCK_NUM(MAX_PCK_NUM),
.MAX_SIM_CLKs(MAX_SIM_CLKs),
.MAX_PCK_SIZ(MAX_PCK_SIZ),
131,7 → 117,7
(
//input
.ratio (ratio),
.pck_size(pck_size),
.pck_size_in(pck_size_in),
.current_x(current_x),
.current_y(current_y),
.dest_x(dest_x),
161,7 → 147,9
);
// always @(posedge start ) begin
// $display(" (%d,%d) start at %t",current_x, current_y,$time);
//end
 
endmodule
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.