mpsoc/Integration_test/src/src.pl
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: mpsoc/Integration_test/src/deafult_noc_param
===================================================================
--- mpsoc/Integration_test/src/deafult_noc_param (revision 54)
+++ mpsoc/Integration_test/src/deafult_noc_param (nonexistent)
@@ -1,81 +0,0 @@
-$model = bless( {
- 'noc_param' => {
-"TOPOLOGY" => "\"MESH\"",
-"T1" => "8",
-"T2" => "8",
-"T3" => "1",
-"V" => "2",
-"B" => "4",
-"LB" => "B",
-"Fpay" => "32",
-"ROUTE_NAME" => "\"XY\"",
-"PCK_TYPE" => " \"MULTI_FLIT\"",
-"MIN_PCK_SIZE" => "2",
-"BYTE_EN" => "0",
-"SSA_EN" => "\"NO\"",
-"CONGESTION_INDEX" => "3",
-"ESCAP_VC_MASK" => "2'b01",
-"VC_REALLOCATION_TYPE" => "\"NONATOMIC\"",
-"COMBINATION_TYPE" => "\"COMB_NONSPEC\"",
-"MUX_TYPE" => "\"BINARY\"",
-"C" => "0",
-"CLASS_SETTING"=> "{V{1'b1}}",
-"DEBUG_EN" => "1",
-"ADD_PIPREG_AFTER_CROSSBAR" => "1'b0",
-"FIRST_ARBITER_EXT_P_EN" => "1",
-"SWA_ARBITER_TYPE" => "\"RRA\"",
-"WEIGHTw" => "4",
-"AVC_ATOMIC_EN" => "0",
-"CLASS_SETTING" => "{V{1'b1}}",
-"SMART_MAX" => "0",
-"SELF_LOOP_EN" => "\"NO\"",
-"MAX_PCK_NUM " => " 1000000000",
-"MAX_PCK_SIZ " => " 16383" ,
-"MAX_SIM_CLKs" => " 1000000000",
-"TIMSTMP_FIFO_NUM " => " 16",
-"CVw"=> "(C==0)? V : C * V"
- },
-
-
- 'parameters_order' => {
-'noc_param' =>
-[
- 'TOPOLOGY',
- 'T1',
- 'T2',
- 'T3',
- 'V',
- 'B',
- 'LB',
- 'Fpay',
- 'ROUTE_NAME',
- 'PCK_TYPE',
- 'MIN_PCK_SIZE',
- 'BYTE_EN',
- 'SSA_EN',
- 'SMART_MAX',
- 'CONGESTION_INDEX',
- 'ESCAP_VC_MASK',
- 'VC_REALLOCATION_TYPE',
- 'COMBINATION_TYPE',
- 'MUX_TYPE',
- 'C',
-'CLASS_SETTING',
- 'DEBUG_EN',
- 'ADD_PIPREG_AFTER_CROSSBAR',
- 'FIRST_ARBITER_EXT_P_EN',
- 'SWA_ARBITER_TYPE',
- 'WEIGHTw',
- 'SELF_LOOP_EN',
- 'AVC_ATOMIC_EN',
-"MAX_PCK_NUM " ,
-"MAX_PCK_SIZ ",
-"MAX_SIM_CLKs",
-"TIMSTMP_FIFO_NUM ",
-"CVw"
- ],
-
-}
-
- },
-);
Index: mpsoc/Integration_test/models/fmesh_8x8_2cycle_xy
===================================================================
--- mpsoc/Integration_test/models/fmesh_8x8_2cycle_xy (revision 54)
+++ mpsoc/Integration_test/models/fmesh_8x8_2cycle_xy (nonexistent)
@@ -1,7 +0,0 @@
-$model = bless( {
- 'compile' => "verilate_mesh.sh",
- 'noc_param'=> {
- "TOPOLOGY" => "\"FMESH\"",
- "ROUTE_NAME" => "\"XY\"",
- }
-}, 'ProNOC' );
Index: mpsoc/Integration_test/models/Fattree_k3_L3_st
===================================================================
--- mpsoc/Integration_test/models/Fattree_k3_L3_st (revision 54)
+++ mpsoc/Integration_test/models/Fattree_k3_L3_st (nonexistent)
@@ -1,9 +0,0 @@
-$model = bless( {
- 'noc_param'=> {
- "TOPOLOGY" => "\"FATTREE\"",
- "T1" => "3",
- "T2" => "3",
- "B" => "5",
- "ROUTE_NAME" => "\"NCA_STRAIGHT_UP\"",
- }
-}, 'ProNOC' );
Index: mpsoc/Integration_test/models/mesh_8x8_2cycle_west_first
===================================================================
--- mpsoc/Integration_test/models/mesh_8x8_2cycle_west_first (revision 54)
+++ mpsoc/Integration_test/models/mesh_8x8_2cycle_west_first (nonexistent)
@@ -1,6 +0,0 @@
-$model = bless( {
- 'compile' => "verilate_mesh.sh",
- 'noc_param'=> {
- "ROUTE_NAME" => "\"WEST_FIRST\"",
- }
-}, 'ProNOC' );
Index: mpsoc/Integration_test/models/mesh_8x8_sbp6_xy
===================================================================
--- mpsoc/Integration_test/models/mesh_8x8_sbp6_xy (revision 54)
+++ mpsoc/Integration_test/models/mesh_8x8_sbp6_xy (nonexistent)
@@ -1,6 +0,0 @@
-$model = bless( {
- 'compile' => "verilate_mesh.sh",
- 'noc_param'=> {
- "SMART_MAX" => "6",
- }
-}, 'ProNOC' );
Index: mpsoc/Integration_test/models/mesh_8x8_2cycle_adaptive
===================================================================
--- mpsoc/Integration_test/models/mesh_8x8_2cycle_adaptive (revision 54)
+++ mpsoc/Integration_test/models/mesh_8x8_2cycle_adaptive (nonexistent)
@@ -1,7 +0,0 @@
-$model = bless( {
- 'compile' => "verilate_mesh.sh",
- 'noc_param'=> {
- "ROUTE_NAME" => "\"DUATO\"",
- "ESCAP_VC_MASK" => "2'b01"
- }
-}, 'ProNOC' );
Index: mpsoc/Integration_test/models/mesh_2x2_openpiton
===================================================================
--- mpsoc/Integration_test/models/mesh_2x2_openpiton (revision 54)
+++ mpsoc/Integration_test/models/mesh_2x2_openpiton (nonexistent)
@@ -1,14 +0,0 @@
-$model = bless( {
- 'compile' => "verilate_mesh.sh",
- 'noc_param'=> {
- "T1" => "2",
- "T2" => "2",
- "V" => "1",
- "ESCAP_VC_MASK" => "1'b1",
- "B" => "4",
- "LB" => "16",
- "Fpay" => "64",
- "SSA_EN" => "\"YES\"",
- "SELF_LOOP_EN" => "\"YES\"",
- }
-}, 'ProNOC' );
Index: mpsoc/Integration_test/models/mesh_8x8_2cycle_xy
===================================================================
--- mpsoc/Integration_test/models/mesh_8x8_2cycle_xy (revision 54)
+++ mpsoc/Integration_test/models/mesh_8x8_2cycle_xy (nonexistent)
@@ -1,6 +0,0 @@
-$model = bless( {
- 'compile' => "verilate_mesh.sh",
- 'noc_param'=> {
- "ROUTE_NAME" => "\"XY\"",
- }
-}, 'ProNOC' );
Index: mpsoc/Integration_test/models/torus_8x8_2cycle_xy
===================================================================
--- mpsoc/Integration_test/models/torus_8x8_2cycle_xy (revision 54)
+++ mpsoc/Integration_test/models/torus_8x8_2cycle_xy (nonexistent)
@@ -1,7 +0,0 @@
-$model = bless( {
- 'compile' => "verilate_mesh.sh",
- 'noc_param'=> {
- "TOPOLOGY" => "\"TORUS\"",
- "ROUTE_NAME" => "\"TRANC_XY\"",
- }
-}, 'ProNOC' );
Index: mpsoc/Integration_test/models/mesh_8x8_b2
===================================================================
--- mpsoc/Integration_test/models/mesh_8x8_b2 (revision 54)
+++ mpsoc/Integration_test/models/mesh_8x8_b2 (nonexistent)
@@ -1,7 +0,0 @@
-$model = bless( {
- 'noc_param'=> {
- "ROUTE_NAME" => "\"XY\"",
- "B"=> "2",
- "LB"=> 2
- }
-}, 'ProNOC' );
Index: mpsoc/Integration_test/models/fmesh_1x1_openpiton
===================================================================
--- mpsoc/Integration_test/models/fmesh_1x1_openpiton (revision 54)
+++ mpsoc/Integration_test/models/fmesh_1x1_openpiton (nonexistent)
@@ -1,16 +0,0 @@
-$model = bless( {
- 'compile' => "verilate_mesh.sh",
- 'noc_param'=> {
- "TOPOLOGY"=> "\"FMESH\"",
- "T1" => "1",
- "T2" => "1",
- "V" => "1",
- "ESCAP_VC_MASK" => "1'b1",
- "B" => "4",
- "LB" => "16",
- "Fpay" => "64",
- "SSA_EN" => "\"YES\"",
- "SELF_LOOP_EN" => "\"YES\"",
- "MIN_PCK_SIZE" => "1"
- }
-}, 'ProNOC' );
Index: mpsoc/Integration_test/models/mesh_4x4x3_2cycle_xy
===================================================================
--- mpsoc/Integration_test/models/mesh_4x4x3_2cycle_xy (revision 54)
+++ mpsoc/Integration_test/models/mesh_4x4x3_2cycle_xy (nonexistent)
@@ -1,10 +0,0 @@
-$model = bless( {
- 'compile' => "verilate_mesh.sh",
- 'noc_param'=> {
- "T1" => "4",
- "T2" => "4",
- "T3" => "3",
- "TOPOLOGY" => "\"MESH\"",
- "ROUTE_NAME" => "\"XY\"",
- }
-}, 'ProNOC' );
Index: mpsoc/Integration_test/models/custom1_topology
===================================================================
--- mpsoc/Integration_test/models/custom1_topology (revision 54)
+++ mpsoc/Integration_test/models/custom1_topology (nonexistent)
@@ -1,13 +0,0 @@
-$model = bless( {
- 'compile' => "verilate_mesh.sh",
- 'noc_param'=> {
- "TOPOLOGY"=>"\"custom1\"",
- "CUSTOM_TOPOLOGY_NAME"=>"\"custom1\"",
- "T1" => "16",
- "T2" => "16",
- "T3" => "5",
- "ROUTE_NAME" =>"\"custom\""
- }
-}, 'ProNOC' );
-
-
Index: mpsoc/Integration_test/models/fmesh_2x2_openpiton
===================================================================
--- mpsoc/Integration_test/models/fmesh_2x2_openpiton (revision 54)
+++ mpsoc/Integration_test/models/fmesh_2x2_openpiton (nonexistent)
@@ -1,15 +0,0 @@
-$model = bless( {
- 'compile' => "verilate_mesh.sh",
- 'noc_param'=> {
- "TOPOLOGY"=> "\"FMESH\"",
- "T1" => "2",
- "T2" => "2",
- "V" => "1",
- "ESCAP_VC_MASK" => "1'b1",
- "B" => "4",
- "LB" => "16",
- "Fpay" => "64",
- "SSA_EN" => "\"YES\"",
- "SELF_LOOP_EN" => "\"YES\"",
- }
-}, 'ProNOC' );
Index: mpsoc/Integration_test/models/bintree_k3_L3_st
===================================================================
--- mpsoc/Integration_test/models/bintree_k3_L3_st (revision 54)
+++ mpsoc/Integration_test/models/bintree_k3_L3_st (nonexistent)
@@ -1,9 +0,0 @@
-$model = bless( {
- 'noc_param'=> {
- "TOPOLOGY" => "\"TREE\"",
- "T1" => "3",
- "T2" => "3",
- "B" => "5",
- "ROUTE_NAME" => "\"NCA\"",
- }
-}, 'ProNOC' );
Index: mpsoc/Integration_test/models/mesh_8x8_ssa_xy
===================================================================
--- mpsoc/Integration_test/models/mesh_8x8_ssa_xy (revision 54)
+++ mpsoc/Integration_test/models/mesh_8x8_ssa_xy (nonexistent)
@@ -1,6 +0,0 @@
-$model = bless( {
- 'compile' => "verilate_mesh.sh",
- 'noc_param'=> {
- "SSA_EN" => "\"YES\"",
- }
-}, 'ProNOC' );
Index: mpsoc/Integration_test/verify.perl
===================================================================
--- mpsoc/Integration_test/verify.perl (revision 54)
+++ mpsoc/Integration_test/verify.perl (nonexistent)
@@ -1,90 +0,0 @@
-#!/usr/bin/perl -w
-package ProNOC;
-
-
-
-
-use File::Copy::Recursive qw(dircopy);
-use File::Basename;
-use File::Copy;
-use Data::Dumper;
-use File::Find::Rule;
-
-#add home dir in perl 5.6
-use FindBin;
-use lib $FindBin::Bin;
-use constant::boolean;
-
-
-
-
-use strict;
-use warnings;
-
-use base 'Class::Accessor::Fast';
-
-__PACKAGE__->mk_accessors(qw{
- models
-});
-
-my $app = __PACKAGE__->new();
-
-
-
-my $dirname = dirname(__FILE__);
-require "$dirname/src/src.pl";
-
-my $paralel_run= 4;
-#defne minimum , maximum and increasing step of injection ratio
-my ($MIN,$MAX,$STEP)= (5,80,25);
-
-
-
-if(defined $ARGV[0]){
- $paralel_run= $ARGV[0] if(is_integer($ARGV[0]));
-}
-
-if(defined $ARGV[1]){
- $MIN= $ARGV[1] if(is_integer($ARGV[1]));
-}
-
-if(defined $ARGV[2]){
- $MAX= $ARGV[2] if(is_integer($ARGV[2]));
-}
-
-if(defined $ARGV[3]){
- $STEP= $ARGV[3] if(is_integer($ARGV[3]));
-}
-
-my @inputs =($paralel_run,$MIN,$MAX,$STEP);
-
-
-print "Maximum number of parallel simulation is $paralel_run.\n The injection ratio is set as MIN=$MIN,MAX=$MAX,STEP=$STEP.\n";
-
-
-
-
-my @log_report_match =("Error","Warning" );
-
-
-
-save_file ("$dirname/report","Verification Results:\n");
-
-
-copy_src_files();
-
-gen_models();
-
-compile_models($app,\@inputs);
-
-check_compilation($app,\@log_report_match,\@inputs);
-
-run_all_models($app,\@inputs);
-
-
-
-print "done!\n"
-
-
-
-
mpsoc/rtl/src_modelsim/old.zip
Property changes :
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: mpsoc/rtl/src_noc/mesh_torus.v
===================================================================
--- mpsoc/rtl/src_noc/mesh_torus.v (revision 54)
+++ mpsoc/rtl/src_noc/mesh_torus.v (nonexistent)
@@ -1,1880 +0,0 @@
-
-`timescale 1ns/1ps
-
-/**********************************************************************
-** File: mesh_torus.v
-**
-** Copyright (C) 2014-2017 Alireza Monemi
-**
-** This file is part of ProNoC
-**
-** ProNoC ( stands for Prototype Network-on-chip) is free software:
-** you can redistribute it and/or modify it under the terms of the GNU
-** Lesser General Public License as published by the Free Software Foundation,
-** either version 2 of the License, or (at your option) any later version.
-**
-** ProNoC is distributed in the hope that it will be useful, but WITHOUT
-** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
-** Public License for more details.
-**
-** You should have received a copy of the GNU Lesser General Public
-** License along with ProNoC. If not, see
.
-**
-**
-** Description:
-**
-**
-***************************************/
-
-
-
-
-/*****************************************
-
-pre-sel[xy]
- y
-1 | 3
- |
- -------x
-0 | 2
- |
-
-*****************************************/
-
-
-module mesh_torus_vc_alloc_request_gen_adaptive #(
- parameter ROUTE_TYPE = "FULL_ADAPTIVE", // "FULL_ADAPTIVE", "PAR_ADAPTIVE"
- parameter V = 4,
- parameter DSTPw=4,
- parameter SSA_EN ="NO",
- parameter PPSw=4,
- parameter [V-1 : 0] ESCAP_VC_MASK = 4'b1000 // mask scape vc, valid only for full adaptive
-
-)(
- ovc_avalable_all,
- dest_port_coded_all,
- candidate_ovc_all,
- ivc_request_all,
- ovc_is_assigned_all,
- masked_ovc_request_all,
- port_pre_sel,
- swap_port_presel,
- destport_clear_all,
- ivc_num_getting_ovc_grant,
- ssa_ivc_num_getting_ovc_grant_all,
- sel,
- reset,
- clk
-
-);
- localparam P = 5;
-
- localparam P_1 = P-1,
- PV = V * P,
- PVV = PV * V,
- VP_1 = V * P_1,
- PVDSTPw = PV * DSTPw;
-
- localparam LOCAL = 3'd0,
- EAST = 3'd1,
- NORTH = 3'd2,
- WEST = 3'd3,
- SOUTH = 3'd4;
-
- input [PV-1 : 0] ovc_avalable_all;
- input [PVDSTPw-1 : 0] dest_port_coded_all;
- input [PV-1 : 0] ivc_request_all;
- input [PV-1 : 0] ovc_is_assigned_all;
- output [PVV-1 : 0] masked_ovc_request_all;
- input [PVV-1 : 0] candidate_ovc_all;
- input [PPSw-1 : 0] port_pre_sel;
- output [PV-1 : 0] swap_port_presel;
- output [PV-1 : 0] sel;
- output [PVDSTPw-1 : 0] destport_clear_all;
- input [PV-1 : 0] ivc_num_getting_ovc_grant;
- input [PV-1 : 0] ssa_ivc_num_getting_ovc_grant_all;
- input reset,clk;
-
-
- wire [PV-1 : 0] non_assigned_ovc_request_all;
- wire [PV-1 : 0] y_evc_forbiden,x_evc_forbiden;
- wire [V-1 : 0] ovc_avb_x_plus,ovc_avb_x_minus,ovc_avb_y_plus,ovc_avb_y_minus,ovc_avb_local;
- wire [VP_1-1 : 0] ovc_avalable_perport [P-1 : 0];
- wire [PPSw-1 : 0] port_pre_sel_perport [P-1 : 0];
- wire [PVV-1 : 0] candidate_ovc_x_all, candidate_ovc_y_all;
-
-
- assign non_assigned_ovc_request_all = ivc_request_all & ~ovc_is_assigned_all;
- assign {ovc_avb_y_minus,ovc_avb_x_minus,ovc_avb_y_plus,ovc_avb_x_plus,ovc_avb_local} = ovc_avalable_all;
-
-
-
- assign ovc_avalable_perport[LOCAL] = {ovc_avb_x_plus,ovc_avb_x_minus,ovc_avb_y_plus,ovc_avb_y_minus};
- assign ovc_avalable_perport[EAST] = {ovc_avb_local,ovc_avb_x_minus,ovc_avb_y_plus,ovc_avb_y_minus};
- assign ovc_avalable_perport[NORTH] = {ovc_avb_x_plus,ovc_avb_x_minus,ovc_avb_local,ovc_avb_y_minus};
- assign ovc_avalable_perport[WEST] = {ovc_avb_x_plus,ovc_avb_local,ovc_avb_y_plus,ovc_avb_y_minus};
- assign ovc_avalable_perport[SOUTH] = {ovc_avb_x_plus,ovc_avb_x_minus,ovc_avb_y_plus,ovc_avb_local};
-
-
-
- assign port_pre_sel_perport[LOCAL] = port_pre_sel;
- assign port_pre_sel_perport[EAST] = {2'b00,port_pre_sel[1:0]};
- assign port_pre_sel_perport[NORTH] = {1'b0,port_pre_sel[2],1'b0,port_pre_sel[0]};
- assign port_pre_sel_perport[WEST] = {port_pre_sel[3:2],2'b0};
- assign port_pre_sel_perport[SOUTH] = {port_pre_sel[3],1'b0,port_pre_sel[1],1'b0};
-
-
- wire [PV-1 : 0] avc_unavailable;
- genvar i;
- generate
-
-
- for(i=0;i< PV;i=i+1) begin :all_vc_loop
-
- mesh_torus_adaptive_avb_ovc_mux #(
- .V(V)
- )
- the_adaptive_avb_ovc_mux
- (
- .ovc_avalable (ovc_avalable_perport [i/V]),
- .sel (sel [i]),
- .candidate_ovc_x (candidate_ovc_x_all [((i+1)*V)-1 : i*V]),
- .candidate_ovc_y (candidate_ovc_y_all [((i+1)*V)-1 : i*V]),
- .non_assigned_ovc_request (non_assigned_ovc_request_all[i]),
- .xydir (dest_port_coded_all [((i+1)*DSTPw)-1 : ((i+1)*DSTPw)-2]),
- .masked_ovc_request (masked_ovc_request_all [((i+1)*V)-1 : i*V])
- );
-
- mesh_torus_port_selector #(
- .SW_LOC (i/V),
- .PPSw(PPSw)
- )
- the_portsel
- (
- .port_pre_sel (port_pre_sel_perport[i/V]),
- .swap_port_presel (swap_port_presel[i]),
- .sel (sel[i]),
- .dest_port_in (dest_port_coded_all[((i+1)*DSTPw)-1 : i*DSTPw]),
- .y_evc_forbiden (y_evc_forbiden[i]),
- .x_evc_forbiden (x_evc_forbiden[i])
- );
-
- mesh_tori_dspt_clear_gen #(
- .SSA_EN(SSA_EN),
- .DSTPw(DSTPw),
- .SW_LOC(i/V)
- )
- dspt_clear_gen
- (
- .destport_clear(destport_clear_all[((i+1)*DSTPw)-1 : i*DSTPw]),
- .ivc_num_getting_ovc_grant(ivc_num_getting_ovc_grant[i]),
- .sel(sel[i]),
- .ssa_ivc_num_getting_ovc_grant(ssa_ivc_num_getting_ovc_grant_all[i])
- );
-
-
- /* verilator lint_off WIDTH */
- if(ROUTE_TYPE == "FULL_ADAPTIVE") begin: full_adpt
- /* verilator lint_on WIDTH */
- assign candidate_ovc_y_all[((i+1)*V)-1 : i*V] = (y_evc_forbiden[i]) ? candidate_ovc_all[((i+1)*V)-1 : i*V] & (~ESCAP_VC_MASK) : candidate_ovc_all[((i+1)*V)-1 : i*V];
- assign candidate_ovc_x_all[((i+1)*V)-1 : i*V] = (x_evc_forbiden[i]) ? candidate_ovc_all[((i+1)*V)-1 : i*V] & (~ESCAP_VC_MASK) : candidate_ovc_all[((i+1)*V)-1 : i*V];
- assign avc_unavailable[i] = (masked_ovc_request_all [((i+1)*V)-1 : i*V] & ~ESCAP_VC_MASK) == {V{1'b0}};
-
-
- mesh_torus_swap_port_presel_gen #(
- .V(V),
- .ESCAP_VC_MASK(ESCAP_VC_MASK),
- .VC_NUM(i)
- )
- the_swap_port_presel
- (
- .avc_unavailable(avc_unavailable[i]),
- .y_evc_forbiden(y_evc_forbiden[i]),
- .x_evc_forbiden(x_evc_forbiden[i]),
- .non_assigned_ovc_request(non_assigned_ovc_request_all[i]),
- .sel(sel[i]),
- .clk(clk),
- .reset(reset),
- .swap_port_presel(swap_port_presel[i])
- );
-
-
- end else begin : partial_adpt
- assign candidate_ovc_y_all[((i+1)*V)-1 : i*V] = candidate_ovc_all [((i+1)*V)-1 : i*V];
- assign candidate_ovc_x_all[((i+1)*V)-1 : i*V] = candidate_ovc_all [((i+1)*V)-1 : i*V];
- assign swap_port_presel[i]=1'b0;
- assign avc_unavailable[i]=1'b0;
-
- end// ROUTE_TYPE
- end//for
-
-endgenerate
-endmodule
-
-
-
-module mesh_tori_dspt_clear_gen #(
- parameter SSA_EN="YES",
- parameter DSTPw =4,
- parameter SW_LOC=0
-
-)(
- destport_clear,
- ivc_num_getting_ovc_grant,
- sel,
- ssa_ivc_num_getting_ovc_grant
-
-);
-
- output [DSTPw-1 : 0] destport_clear;
- input ivc_num_getting_ovc_grant;
- input sel;
- input ssa_ivc_num_getting_ovc_grant;
-
- localparam
- LOCAL = 3'd0,
- EAST = 3'd1,
- WEST = 3'd3;
-
-generate
- /* verilator lint_off WIDTH */
- if ( SSA_EN=="YES" ) begin :predict_if
- /* verilator lint_on WIDTH */
- if (SW_LOC == LOCAL ) begin :local_if
- assign destport_clear= (ivc_num_getting_ovc_grant)?{2'b00,sel,~sel} :{DSTPw{1'b0}};
- end else if (SW_LOC == EAST || SW_LOC == WEST ) begin :xdir_if
- assign destport_clear = (ivc_num_getting_ovc_grant)? {2'b00,sel,~sel} :
- (ssa_ivc_num_getting_ovc_grant)? 4'b0001: //clear b
- 4'b0000;
- end else begin : ydir_if
- assign destport_clear = (ivc_num_getting_ovc_grant)? {2'b00,sel,~sel} :
- (ssa_ivc_num_getting_ovc_grant)? 4'b0010: //clear a
- 4'b0000;
- end
- end else begin :nopredict_if
- assign destport_clear = (ivc_num_getting_ovc_grant )? {2'b00,sel,~sel} :{DSTPw{1'b0}};
- end// nopredict_if
-endgenerate
-endmodule
-
-
-
-module mesh_torus_mask_non_assignable_destport #(
- parameter TOPOLOGY="MESH",
- parameter ROUTE_NAME="XY",
- parameter SW_LOC=0,
- parameter P=5,
- parameter SELF_LOOP_EN="NO"
-)
-(
- odd_column,// use only for odd even routing
- dest_port_in,
- dest_port_out
-);
-
- localparam P_1 = (SELF_LOOP_EN=="NO") ? P-1 : P;
- input [P_1-1 : 0 ] dest_port_in;
- output [P_1-1 : 0 ] dest_port_out;
- input odd_column;
-
- wire [P-2 : 0] dest_port_in_tmp,dest_port_out_tmp;
-
- generate
- if(SELF_LOOP_EN == "NO") begin :nslp
- assign dest_port_in_tmp = dest_port_in;
- assign dest_port_out = dest_port_out_tmp;
- end else begin :slp
- remove_sw_loc_one_hot #(
- .P(P),
- .SW_LOC(SW_LOC)
- )
- remove_sw_loc
- (
- .destport_in(dest_port_in),
- .destport_out(dest_port_in_tmp)
- );
- //currently loop-back only can happen in local ports.
- //Current supported routing algorithms does not results in loop-back in other ports
- wire sw_loc_val = (SW_LOC>0 && SW_LOC<5) ? 1'b0 : dest_port_in [SW_LOC];
-
- add_sw_loc_one_hot_val #(
- .P(P),
- .SW_LOC(SW_LOC)
- )add_sw_loc
- (
- .sw_loc_val(sw_loc_val),
- .destport_in (dest_port_out_tmp),
- .destport_out(dest_port_out)
- );
-
-
-
-
- end
- endgenerate
-
- mesh_torus_mask_non_assignable_destport_no_self_loop # (
- .TOPOLOGY(TOPOLOGY),
- .ROUTE_NAME(ROUTE_NAME),
- .SW_LOC(SW_LOC),
- .P(P)
- )
- mask_no_self_loop
- (
- .dest_port_in(dest_port_in_tmp),
- .dest_port_out(dest_port_out_tmp),
- .odd_column(odd_column)
- );
-
-
-endmodule
-
-module mesh_torus_mask_non_assignable_destport_no_self_loop #(
- parameter TOPOLOGY="MESH",
- parameter ROUTE_NAME="XY",
- parameter SW_LOC=0,
- parameter P=5
-)
-(
- odd_column,// use only for odd even routing
- dest_port_in,
- dest_port_out
-);
-
-localparam
- EAST = 1,
- NORTH = 2,
- WEST = 3,
- SOUTH = 4;
-
-//port number in north port
-localparam
- N_LOCAL = 0,
- N_EAST = 1,
- N_WEST = 2,
- N_SOUTH = 3;
-
- // port number in south port
- localparam
- S_LOCAL = 0,
- S_EAST = 1,
- S_NORTH = 2,
- S_WEST = 3;
-
- // port number in east port
- localparam
- E_LOCAL = 0,
- E_NORTH = 1,
- E_WEST = 2,
- E_SOUTH = 3;
-
- // port number in east port
- localparam
- W_LOCAL = 0,
- W_EAST = 1,
- W_NORTH = 2,
- W_SOUTH = 3;
-
-
- localparam P_1 = P-1;
- input [P_1-1 : 0 ] dest_port_in;
- output [P_1-1 : 0 ] dest_port_out;
- input odd_column;
-
-
- generate
- if(P>5)begin :p5
- assign dest_port_out[P_1-1:4] = dest_port_in[P_1-1:4]; //other local ports
- end
-
-
- /* verilator lint_off WIDTH */
- if (TOPOLOGY == "RING" || TOPOLOGY == "LINE") begin : oneD // A port can send packets to all other ports in these topologies
- /* verilator lint_on WIDTH */
- assign dest_port_out = dest_port_in;
- end else begin : towD
- /*XY*/
- /* verilator lint_off WIDTH */
- if ( ROUTE_NAME == "XY" || ROUTE_NAME == "TRANC_XY") begin :xy
- /* verilator lint_on WIDTH */
- if (SW_LOC == NORTH ) begin : nort_p // The port located in y axsis does not send packets to x dimension
- assign dest_port_out[N_LOCAL]= dest_port_in[N_LOCAL];
- assign dest_port_out[N_EAST]= 1'b0; // mask east port
- assign dest_port_out[N_WEST]= 1'b0; // mask west port
- assign dest_port_out[N_SOUTH]= dest_port_in[N_SOUTH];
- end else if ( SW_LOC == SOUTH) begin : south_p
- assign dest_port_out[S_LOCAL]= dest_port_in[S_LOCAL];
- assign dest_port_out[S_EAST]= 1'b0; // mask east port
- assign dest_port_out[S_NORTH]= dest_port_in[S_NORTH];
- assign dest_port_out[S_WEST]= 1'b0; // mask west port
- end else begin : non_vertical
- assign dest_port_out[3:0] = dest_port_in[3:0];
- end
- /*WEST-FIRST*/
- /* verilator lint_off WIDTH */
- end else if ( ROUTE_NAME == "WEST_FIRST" || ROUTE_NAME == "TRANC_WEST_FIRST") begin :west_first
- /* verilator lint_on WIDTH */
- // SW & NW are forbidden
- if (SW_LOC == NORTH ) begin : nort_p // north port does not send packets to the west port.
- assign dest_port_out[N_LOCAL]= dest_port_in[N_LOCAL];
- assign dest_port_out[N_EAST]= dest_port_in[N_EAST];
- assign dest_port_out[N_WEST]= 1'b0; // mask west port
- assign dest_port_out[N_SOUTH]= dest_port_in[N_SOUTH];
- end else if ( SW_LOC == SOUTH) begin : south_p // south port does not sends packet to west
- assign dest_port_out[S_LOCAL]= dest_port_in[S_LOCAL];
- assign dest_port_out[S_EAST]= dest_port_in[S_EAST];
- assign dest_port_out[S_NORTH]= dest_port_in[S_NORTH];
- assign dest_port_out[S_WEST]= 1'b0; // mask west port
- end else begin : non_vertical
- assign dest_port_out[3:0] = dest_port_in[3:0];
- end
- /*NORTH_LAST*/
- /* verilator lint_off WIDTH */
- end else if ( ROUTE_NAME == "NORTH_LAST" || ROUTE_NAME == "TRANC_NORTH_LAST") begin :north_last
- /* verilator lint_on WIDTH */
- //NE & NW are forbidden
- if (SW_LOC == SOUTH ) begin : south_p // north port does not send packets to the east nor to the west port.
- assign dest_port_out[S_LOCAL]= dest_port_in[S_LOCAL];
- assign dest_port_out[S_EAST]= 1'b0; // mask east port
- assign dest_port_out[S_WEST]= 1'b0; // mask west port
- assign dest_port_out[S_NORTH]= dest_port_in[S_NORTH];
- end else begin : other_p
- assign dest_port_out[3:0] = dest_port_in[3:0];
- end
- /*NEGETIVE_FIRST*/
- /* verilator lint_off WIDTH */
- end else if ( ROUTE_NAME == "NEGETIVE_FIRST" || ROUTE_NAME == "TRANC_NEGETIVE_FIRST") begin :negetive_first
- /* verilator lint_on WIDTH */
- //ES & NW is forbiden
- if (SW_LOC == SOUTH ) begin : south_p // south port does not send packets to the west port. NW is forbiden
- assign dest_port_out[S_LOCAL]= dest_port_in[S_LOCAL];
- assign dest_port_out[S_EAST]= dest_port_in[S_EAST];
- assign dest_port_out[S_WEST]= 1'b0; // mask west port
- assign dest_port_out[S_NORTH]= dest_port_in[S_NORTH];
- end else if ( SW_LOC == WEST) begin : west_p // west port does not sends packet to south. ES is forbiden
- assign dest_port_out[W_LOCAL]= dest_port_in[W_LOCAL];
- assign dest_port_out[W_NORTH]= dest_port_in[W_NORTH];
- assign dest_port_out[W_EAST] = dest_port_in[W_EAST];
- assign dest_port_out[W_SOUTH]= 1'b0; //mask south port
- end else begin : other_p
- assign dest_port_out[3:0] = dest_port_in[3:0];
- end
- /*ODD_EVEN*/
- /* verilator lint_off WIDTH */
- end else if ( ROUTE_NAME == "ODD_EVEN" ) begin : odd_even
- /* verilator lint_on WIDTH */
- //Odd column : NW and SW turns are not allowed
- //Even column: EN and ES turns are not allowed
-
- if (SW_LOC == NORTH ) begin : nort_p // north port does not send packets to the west port in odd columns. SW is forbiden
- assign dest_port_out[N_LOCAL]= dest_port_in[N_LOCAL];
- assign dest_port_out[N_EAST]= dest_port_in[N_EAST];
- assign dest_port_out[N_WEST]= (odd_column)? 1'b0: dest_port_in[N_WEST]; // mask west port in odd columns
- assign dest_port_out[N_SOUTH]= dest_port_in[N_SOUTH];
- end else if (SW_LOC == SOUTH) begin : south_p // south port does not sends packet to west in odd columns. NW is forbiden
- assign dest_port_out[S_LOCAL]= dest_port_in[S_LOCAL];
- assign dest_port_out[S_EAST]= dest_port_in[S_EAST];
- assign dest_port_out[S_NORTH]= dest_port_in[S_NORTH];
- assign dest_port_out[S_WEST]= (odd_column)? 1'b0: dest_port_in[S_WEST]; // mask west port in odd columns
-
-
- end else if (SW_LOC == WEST) begin : west_p // WEST port does not sends packet to north and south ports in even columns
- //ES & EN forbiden
- assign dest_port_out[W_LOCAL]= dest_port_in[W_LOCAL];
- assign dest_port_out[W_NORTH]= (odd_column)? dest_port_in[W_NORTH] : 1'b0; //mask north in even columns
- assign dest_port_out[W_EAST] = dest_port_in[W_EAST];
- assign dest_port_out[W_SOUTH]= (odd_column)? dest_port_in[W_SOUTH] : 1'b0; //mask south in even columns
- end else begin: other_p
- assign dest_port_out[3:0] = dest_port_in[3:0];
- end
-
- end else begin : f_adptv
- assign dest_port_out[3:0] = dest_port_in[3:0];
- end
- end
- endgenerate
-endmodule
-
-
-
-
-/**********************
-
- swap_port_presel_gen
-
-**********************/
-
-module mesh_torus_swap_port_presel_gen #(
- parameter V = 4,
- parameter [V-1 : 0] ESCAP_VC_MASK = 4'b1000, // mask scape vc, valid only for full adaptive
- parameter VC_NUM=0
-
-)(
- avc_unavailable,
- swap_port_presel,
- y_evc_forbiden,
- x_evc_forbiden,
- non_assigned_ovc_request,
- sel,
- clk,
- reset
-
-);
-
- localparam LOCAL_VC_NUM= VC_NUM % V;
-
-
-
- input avc_unavailable;
- input y_evc_forbiden,x_evc_forbiden;
- input non_assigned_ovc_request,sel;
- input clk,reset;
- output swap_port_presel;
- reg swap_reg;
-
- wire swap_port_presel_next;
-
-
- wire evc_forbiden;
-
-
- /************************
-
- destination-port_in
- x: 1 EAST, 0 WEST
- y: 1 NORTH, 0 SOUTH
- ab: 00 : LOCAL, 10: xdir, 01: ydir, 11 x&y dir
- sel:
- 0: xdir
- 1: ydir
- port_pre_sel
- 0: xdir
- 1: ydir
-
-************************/
-
-
- //For an EVC sender, if the use of EVC in destination port is restricted while the destination port has no available AVC,
- //the port pre selection must swap
-
-
- // generate
- // check if it is an evc sender
- // if(ESCAP_VC_MASK[LOCAL_VC_NUM]== 1'b0)begin
- //its not EVC
- // assign swap_port_presel=1'b0;
-
- // end else begin // the sender is an EVC
-
- assign evc_forbiden = (sel)? y_evc_forbiden : x_evc_forbiden;
- assign swap_port_presel_next= non_assigned_ovc_request & evc_forbiden & avc_unavailable;
-
-`ifdef SYNC_RESET_MODE
- always @ (posedge clk )begin
-`else
- always @ (posedge clk or posedge reset)begin
-`endif
- if(reset)begin
- swap_reg<=1'b0;
- end else begin
- swap_reg<=swap_port_presel_next;
- end
- end
- assign swap_port_presel = swap_reg;
-
- //end //else
-
-
-
- //endgenerate
-
-
-
-endmodule
-
-
-
-
-/************************
-
- adaptive_avb_ovc_mux
-
-
-************************/
-module mesh_torus_adaptive_avb_ovc_mux #(
- parameter V= 4
-)(
- ovc_avalable,
- sel,
- candidate_ovc_x,
- candidate_ovc_y,
- non_assigned_ovc_request,
- xydir,
- masked_ovc_request
-
-
-);
- localparam P = 5;
- localparam P_1 = P-1,
- VP_1 = V * P_1;
-
- input [VP_1-1 : 0] ovc_avalable;
- input sel;
- input [V-1 : 0] candidate_ovc_x;
- input [V-1 : 0] candidate_ovc_y;
- input non_assigned_ovc_request;
- input [1 : 0] xydir;
- output [V-1 : 0] masked_ovc_request;
- wire x,y;
- wire [V-1 : 0] ovc_avb_x_plus,ovc_avb_x_minus,ovc_avb_y_plus,ovc_avb_y_minus;
- wire [V-1 : 0] mux_out_x,mux_out_y;
- wire [V-1 : 0] ovc_request_x,ovc_request_y,masked_ovc_request_x,masked_ovc_request_y;
-
- assign {x,y}= xydir;
- assign {ovc_avb_x_plus,ovc_avb_x_minus,ovc_avb_y_plus,ovc_avb_y_minus}=ovc_avalable;
- //first level mux
- //assign mux_out_x = (x)? ovc_avb_x_plus : ovc_avb_x_minus;
- //assign mux_out_y = (y)? ovc_avb_y_plus : ovc_avb_y_minus;
- assign mux_out_x = (ovc_avb_x_plus &{V{x}}) | (ovc_avb_x_minus &{V{~x}});
- assign mux_out_y = (ovc_avb_y_plus &{V{y}}) | (ovc_avb_y_minus &{V{~y}});
-
-
- //assign ovc_request_x = (non_assigned_ovc_request)? candidate_ovc_x : {V{1'b0}};
- //assign ovc_request_y = (non_assigned_ovc_request)? candidate_ovc_y : {V{1'b0}};
- assign ovc_request_x = candidate_ovc_x & {V{non_assigned_ovc_request}};
- assign ovc_request_y = candidate_ovc_y & {V{non_assigned_ovc_request}};
-
- //mask unavailble ovc
- assign masked_ovc_request_x = mux_out_x & ovc_request_x;
- assign masked_ovc_request_y = mux_out_y & ovc_request_y;
-
- //second mux
- // assign masked_ovc_request = (sel)? masked_ovc_request_y: masked_ovc_request_x;
- assign masked_ovc_request = (masked_ovc_request_y & {V{sel}})| (masked_ovc_request_x & {V{~sel}});
-
-
-endmodule
-
-
-
-
-
-/*****************************************************
-
- port_selector
-
-
-*****************************************************/
-
-
-module mesh_torus_port_selector #(
- parameter SW_LOC = 0,
- parameter PPSw=4
-)
-(
- port_pre_sel,
- dest_port_in,
- swap_port_presel,
- sel,
- y_evc_forbiden,
- x_evc_forbiden
-);
-
-/************************
-
- destination-port_in
- x: 1 EAST, 0 WEST
- y: 1 NORTH, 0 SOUTH
- ab: 00 : LOCAL, 10: xdir, 01: ydir, 11 x&y dir
- sel:
- 0: xdir
- 1: ydir
- port_pre_sel
- 0: xdir
- 1: ydir
-
-************************/
-
-
- //input reset,clk;
- input [PPSw-1:0] port_pre_sel;
- // input port_pre_sel_ld;
- output sel;
- input [3:0] dest_port_in;
- input swap_port_presel;
- // output route_subfunc_violated;
- output y_evc_forbiden, x_evc_forbiden;
-
- wire x,y,a,b;
- wire [PPSw-1:0] port_pre_sel_final;
- //reg [3:0] port_pre_sel_delayed , port_pre_sel_latched;
- // wire o1,o2;
-
-
- localparam LOCAL = 0,
- EAST = 1,
- NORTH = 2,
- WEST = 3,
- SOUTH = 4;
-
- localparam LOCAL_SEL = (SW_LOC == NORTH || SW_LOC == SOUTH )? 1'b1 : 1'b0;
- assign port_pre_sel_final= (swap_port_presel)? ~port_pre_sel: port_pre_sel;
- assign {x,y,a,b} = dest_port_in;
-
-
- wire sel_in,sel_pre, overwrite;
- wire [1:0] xy;
-
- assign xy={x,y};
- assign sel_pre= port_pre_sel_final[xy];
-
- assign overwrite= a&b;
- generate
- if(LOCAL_SEL)begin :local_p
- assign sel_in= b | ~a;
- end else begin :nonlocal_p
- assign sel_in= b ;
- end
- endgenerate
-
- assign sel= (overwrite)? sel_pre : sel_in;
-
-// check if EVC is allowed to be used
-
- // Using of all EVCs located in y dimension are restricted when the packet can be sent into both x&y direction
- assign y_evc_forbiden = a&b;
-
- //there is no restriction in using EVCs located in x dimension
- assign x_evc_forbiden = 1'b0;
- //assign route_subfunc_violated = a&b;
- /* verilator lint_off WIDTH */
- endmodule
-
-
-
-/*******************
- mesh_torus_adaptive_lk_dest_encoder
-********************/
-
-
-
-module mesh_torus_adaptive_lk_dest_encoder #(
- parameter V=4,
- parameter P=5,
- parameter DSTPw=P-1,
- parameter Fw=37,
- parameter DST_P_MSB=11,
- parameter DST_P_LSB=8
-
-)(
- sel,
- flit_in,
- dest_coded_out,
- vc_num_delayed,
- lk_dest
-);
-
- input [V-1 : 0] sel;
- output [DSTPw-1 : 0]dest_coded_out;
- input [V-1 : 0] vc_num_delayed;
- input [DSTPw-1 : 0] lk_dest;
- input [Fw-1 : 0] flit_in;
-
- wire [1 : 0] ab,xy;
- wire sel_muxed;
-
- onehot_mux_1D #(
- .W(1),
- .N(V)
- )
- sel_mux
- (
- .in(sel),
- .out(sel_muxed),
- .sel(vc_num_delayed)
- );
-
-
- //lkdestport = {lkdestport_x[1:0],lkdestport_y[1:0]};
- // sel: 0: xdir 1: ydir
- assign ab = (sel_muxed)? lk_dest[1:0] : lk_dest[3:2];
- //if ab==00 change x and y direction
- assign xy = (ab>0)? flit_in[DST_P_MSB : DST_P_LSB+2] : ~flit_in[DST_P_MSB : DST_P_LSB+2] ;
-
- assign dest_coded_out={xy,ab};
-
-endmodule
-
-
-module mesh_torus_dtrmn_dest_encoder #(
- parameter P=5,
- parameter DSTPw=P-1,
- parameter Fw=37,
- parameter DST_P_MSB=11,
- parameter DST_P_LSB=8
-
-)(
- flit_in,
- dest_coded_out,
- lk_dest
-);
-
-
- output [DSTPw-1 : 0]dest_coded_out;
-
- input [DSTPw-1 : 0] lk_dest;
- input [Fw-1 : 0] flit_in;
-
- wire [1 : 0] ab,xy;
-
-
- //lkdestport = {lkdestport_x[1:0],lkdestport_y[1:0]};
- // sel: 0: xdir 1: ydir
- assign ab = lk_dest[1:0];
- //if ab==00 change x and y direction
- assign xy = (ab>0)? flit_in[DST_P_MSB : DST_P_LSB+2] : ~flit_in[DST_P_MSB : DST_P_LSB+2] ;
-
- assign dest_coded_out={xy,ab};
-
-endmodule
-
-
-/********************
-
- distance_gen
-
-********************/
-
-module mesh_torus_distance_gen #(
- parameter T1= 4, // number of node in x axis
- parameter T2= 4, // number of node in y axis
- parameter T3= 4,
- parameter EAw=4,
- parameter DISTw=4,
- parameter TOPOLOGY = "MESH"
-
-)(
- src_e_addr,
- dest_e_addr,
- distance
-);
-
- function integer log2;
- input integer number; begin
- log2=(number <=1) ? 1: 0;
- while(2**log2
dest_x)? src_x - dest_x : dest_x - src_x;
- y_offset = (src_y> dest_y)? src_y - dest_y : dest_y - src_y;
- end
-
-
-
- end else begin : twoD //torus ring
-
- wire tranc_x_plus,tranc_x_min,tranc_y_plus,tranc_y_min,same_x,same_y;
-
- /* verilator lint_off WIDTH */
- always @ (*) begin
- x_offset= {Xw{1'b0}};
- y_offset= {Yw{1'b0}};
-
- //x_offset
- if(same_x) x_offset= {Xw{1'b0}};
- else if(tranc_x_plus) begin
- if(dest_x > src_x) x_offset= dest_x-src_x;
- else x_offset= (NX-src_x)+dest_x;
- end
- else if(tranc_x_min) begin
- if(dest_x < src_x) x_offset= src_x-dest_x;
- else x_offset= src_x+(NX-dest_x);
-
- end
-
- //y_offset
- if(same_y) y_offset= {Yw{1'b0}};
- else if(tranc_y_plus) begin
- if(dest_y > src_y) y_offset= dest_y-src_y;
- else y_offset= (NY-src_y)+dest_y;
- end
- else if(tranc_y_min) begin
- if(dest_y < src_y) y_offset= src_y-dest_y;
- else y_offset= src_y+(NY-dest_y);
-
- end
-
-
- end
- /* verilator lint_on WIDTH */
-
-
- tranc_dir #(
- .NX(NX),
- .NY(NY)
- )
- tranc_dir
- (
- .tranc_x_plus(tranc_x_plus),
- .tranc_x_min(tranc_x_min),
- .tranc_y_plus(tranc_y_plus),
- .tranc_y_min(tranc_y_min),
- .same_x(same_x),
- .same_y(same_y),
- .current_x(src_x),
- .current_y(src_y),
- .dest_x(dest_x),
- .dest_y(dest_y)
- );
-
-
- end
- endgenerate
- /* verilator lint_off WIDTH */
- assign distance = x_offset+y_offset+1'b1;
- /* verilator lint_on WIDTH */
-endmodule
-
-
-module mesh_torus_ssa_check_destport #(
- parameter ROUTE_TYPE="DETERMINISTIC",
- parameter SW_LOC = 0,
- parameter P=5,
- parameter DEBUG_EN = 0,
- parameter DSTPw = P-1,
- parameter SS_PORT=0
-)(
- destport_encoded, //exsited packet dest port
- destport_in_encoded, // incomming packet dest port
- ss_port_hdr_flit,
- ss_port_nonhdr_flit
-//synthesis translate_off
-//synopsys translate_off
- ,clk,
- ivc_num_getting_sw_grant,
- hdr_flg
-//synopsys translate_on
-//synthesis translate_on
-
-);
-
- input [DSTPw-1 : 0] destport_encoded, destport_in_encoded;
- output ss_port_hdr_flit, ss_port_nonhdr_flit;
-//synthesis translate_off
-//synopsys translate_off
- input clk, ivc_num_getting_sw_grant,hdr_flg;
-//synopsys translate_on
-//synthesis translate_on
-
-//MESH, TORUS Topology p=5
- localparam LOCAL = 0,
- EAST = 1,
- WEST = 3;
-
-
-/************************
- destination port is coded
- destination-port_in
- x: 1 EAST, 0 WEST
- y: 1 NORTH, 0 SOUTH
- ab: 00 : LOCAL, 10: xdir, 01: ydir, 11 x&y dir
- sel:
- 0: xdir
- 1: ydir
- port_pre_sel
- 0: xdir
- 1: ydir
-
-************************/
-wire a,b,aa,bb;
-assign {a,b} = destport_in_encoded[1:0];
-assign {aa,bb} = destport_encoded[1:0];
-
-generate
- if( SS_PORT == LOCAL) begin :local_p
- assign ss_port_hdr_flit = 1'b0;
- assign ss_port_nonhdr_flit = 1'b0;
- end else if ((SS_PORT == EAST) || SS_PORT == WEST )begin :xdir
- assign ss_port_hdr_flit = a;
- assign ss_port_nonhdr_flit = aa;
- end else begin :ydir
- assign ss_port_hdr_flit = b;
- assign ss_port_nonhdr_flit = bb;
- end
-
-//synthesis translate_off
-//synopsys translate_off
-
-if(DEBUG_EN) begin :dbg
- always @(posedge clk) begin
- //if(!reset)begin
- if(ivc_num_getting_sw_grant & aa & bb & ~hdr_flg) begin
- $display("%t: SSA ERROR: There are two output ports that a non-header flit can be sent to. %m",$time);
- $finish;
- end
- //end
- end
-end //dbg
-
-//synopsys translate_on
-//synthesis translate_on
-
-
-endgenerate
-endmodule
-
-
-module line_ring_ssa_check_destport #(
- parameter ROUTE_TYPE="DETERMINISTIC",
- parameter SW_LOC = 0,
- parameter P=3,
- parameter DEBUG_EN = 0,
- parameter DSTPw = P-1,
- parameter SS_PORT=0
-)(
- destport_encoded, //exsited packet dest port
- destport_in_encoded, // incomming packet dest port
- ss_port_hdr_flit,
- ss_port_nonhdr_flit
-
-);
-
- input [DSTPw-1 : 0] destport_encoded, destport_in_encoded;
- output ss_port_hdr_flit, ss_port_nonhdr_flit;
-
-
-
-wire [P-1 : 0] dest_port_num,assigned_dest_port_num;
-
-
-
- line_ring_decode_dstport cnv1(
- .dstport_one_hot(dest_port_num),
- .dstport_encoded(destport_in_encoded)
- );
-
- line_ring_decode_dstport cnv2(
- .dstport_one_hot(assigned_dest_port_num),
- .dstport_encoded(destport_encoded)
- );
-
- assign ss_port_hdr_flit = dest_port_num [SS_PORT];
-
- assign ss_port_nonhdr_flit = assigned_dest_port_num[SS_PORT];
-
-endmodule
-
-
-/*
-module mesh_torus_add_ss_port #(
- parameter SW_LOC=1,
- parameter P=5,
- parameter SELF_LOOP_EN="NO"
-)(
- destport_in,
- destport_out
-);
- localparam
- P_1 = (SELF_LOOP_EN == "NO") ? P-1 : P,
- LOCAL = 0,
- EAST = 1,
- NORTH = 2,
- WEST = 3,
- SOUTH = 4;
-
-
- localparam NO_SELF_LOOP = (SELF_LOOP_EN == "NO") ? 1 : 0;
- localparam SS_PORT_P5 = (SW_LOC== EAST )? WEST- NO_SELF_LOOP : // the sender port must be removed from destination port code
- (SW_LOC== NORTH )? SOUTH- NO_SELF_LOOP: // the sender port must be removed from destination port code
- (SW_LOC== WEST )? EAST :
- NORTH ;
-
- localparam SS_PORT_P3 = (SELF_LOOP_EN == "NO") ? 1 :
-
-
- localparam SS_PORT = (P==5) ? SS_PORT_P5: SS_PORT_P3;
-
-
-
-
- input [P_1-1 : 0] destport_in;
- output reg [P_1-1 : 0] destport_out;
-
-
-
- always @(*)begin
- destport_out=destport_in;
- if( SW_LOC != LOCAL ) begin
- if(destport_in=={P_1{1'b0}}) destport_out[SS_PORT]= 1'b1;
- end
- end
-
-
-endmodule
-*/
-
-/**************
- *
- * ************/
-
- module mesh_tori_router_addr_decode #(
- parameter TOPOLOGY = "MESH",
- parameter T1=4,
- parameter T2=4,
- parameter T3=4,
- parameter RAw=6
-)(
- r_addr,
- rx,
- ry,
- valid
-);
-
- function integer log2;
- input integer number; begin
- log2=(number <=1) ? 1: 0;
- while(2**log2
mpsoc/rtl/src_noc/mesh_torus.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: mpsoc/rtl/src_noc/flit_buffer.v
===================================================================
--- mpsoc/rtl/src_noc/flit_buffer.v (revision 54)
+++ mpsoc/rtl/src_noc/flit_buffer.v (nonexistent)
@@ -1,1252 +0,0 @@
-`timescale 1ns/1ps
-
-/**********************************************************************
-** File: flit_buffer.v
-**
-** Copyright (C) 2014-2017 Alireza Monemi
-**
-** This file is part of ProNoC
-**
-** ProNoC ( stands for Prototype Network-on-chip) is free software:
-** you can redistribute it and/or modify it under the terms of the GNU
-** Lesser General Public License as published by the Free Software Foundation,
-** either version 2 of the License, or (at your option) any later version.
-**
-** ProNoC is distributed in the hope that it will be useful, but WITHOUT
-** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
-** Public License for more details.
-**
-** You should have received a copy of the GNU Lesser General Public
-** License along with ProNoC. If not, see
.
-**
-**
-** Description:
-** Input buffer module. All VCs located in the same router
-** input port share one single FPGA BRAM
-**
-**************************************************************/
-
-
-module flit_buffer #(
- parameter V = 4,
- parameter B = 4, // buffer space :flit per VC
- parameter Fw = 36,
- parameter PCK_TYPE = "MULTI_FLIT",
- parameter DEBUG_EN = 1,
- parameter SSA_EN="YES" // "YES" , "NO"
- )
- (
- din, // Data in
- vc_num_wr,//write vertual chanel
- vc_num_rd,//read vertual chanel
- wr_en, // Write enable
- rd_en, // Read the next word
- dout, // Data out
- vc_not_empty,
- reset,
- clk,
- ssa_rd
- );
-
-
- function integer log2;
- input integer number; begin
- log2=(number <=1) ? 1: 0;
- while(2**log2
= B-1);
- assign vc_not_empty [i] = (depth[i] > 0);
-
-
-`ifdef SYNC_RESET_MODE
- always @ (posedge clk )begin
-`else
- always @ (posedge clk or posedge reset)begin
-`endif
- if (reset) begin
- rd_ptr [i] <= {Bw{1'b0}};
- wr_ptr [i] <= {Bw{1'b0}};
- depth [i] <= {DEPTHw{1'b0}};
- end
- else begin
- if (wr[i] ) wr_ptr[i] <= wr_ptr [i]+ 1'h1;
- if (rd[i] ) rd_ptr [i]<= rd_ptr [i]+ 1'h1;
- if (wr[i] & ~rd[i]) depth [i]<= depth[i] + 1'h1;
- else if (~wr[i] & rd[i]) depth [i]<= depth[i] - 1'h1;
- end//else
- end//always
-
-
-//synthesis translate_off
-//synopsys translate_off
-
- always @(posedge clk) begin
- if(~reset)begin
- if (wr[i] && (depth[i] == B [DEPTHw-1 : 0]) && !rd[i])begin
- $display("%t: ERROR: Attempt to write to full FIFO:FIFO size is %d. %m",$time,B);
- $finish;
- end
- /* verilator lint_off WIDTH */
- if (rd[i] && (depth[i] == {DEPTHw{1'b0}} && SSA_EN !="YES" ))begin
- $display("%t: ERROR: Attempt to read an empty FIFO: %m",$time);
- $finish;
- end
- if (rd[i] && !wr[i] && (depth[i] == {DEPTHw{1'b0}} && SSA_EN =="YES" ))begin
- $display("%t: ERROR: Attempt to read an empty FIFO: %m",$time);
- $finish;
- end
- /* verilator lint_on WIDTH */
- end//~reset
- //if (wr_en) $display($time, " %h is written on fifo ",din);
- end//always
-//synopsys translate_on
-//synthesis translate_on
- end//for
-
-
-
- end else begin :no_pow2 //pow2
-
-
-
-
-
- /*****************
- Buffer width is not power of 2
- ******************/
-
-
-
-
-
- //pointers
- reg [BVw- 1 : 0] rd_ptr [V-1 :0];
- reg [BVw- 1 : 0] wr_ptr [V-1 :0];
-
- // memory address
- wire [BVw- 1 : 0] wr_addr;
- wire [BVw- 1 : 0] rd_addr;
-
- //pointer array
- wire [BVwV- 1 : 0] wr_addr_all;
- wire [BVwV- 1 : 0] rd_addr_all;
-
- for(i=0;i 0);
-
- /* verilator lint_off WIDTH */
-`ifdef SYNC_RESET_MODE
- always @ (posedge clk )begin
-`else
- always @ (posedge clk or posedge reset)begin
-`endif
- if (reset) begin
-
- rd_ptr [i] <= (B*i);
- wr_ptr [i] <= (B*i);
- depth [i] <= {DEPTHw{1'b0}};
- end
- else begin
- if (wr[i] ) wr_ptr[i] <=(wr_ptr[i]==(B*(i+1))-1)? (B*i) : wr_ptr [i]+ 1'h1;
- if (rd[i] ) rd_ptr[i] <=(rd_ptr[i]==(B*(i+1))-1)? (B*i) : rd_ptr [i]+ 1'h1;
- if (wr[i] & ~rd[i]) depth [i]<=depth[i] + 1'h1;
- else if (~wr[i] & rd[i]) depth [i]<= depth[i] - 1'h1;
- end//else
- end//always
- /* verilator lint_on WIDTH */
-
-//synthesis translate_off
-//synopsys translate_off
-
- always @(posedge clk) begin
- if(~reset)begin
- if (wr[i] && (depth[i] == B[DEPTHw-1 : 0]) && !rd[i]) begin
- $display("%t: ERROR: Attempt to write to full FIFO:FIFO size is %d. %m",$time,B);
- $finish;
- end
- /* verilator lint_off WIDTH */
- if (rd[i] && (depth[i] == {DEPTHw{1'b0}} && SSA_EN !="YES" )) begin
- $display("%t: ERROR: Attempt to read an empty FIFO: %m",$time);
- $finish;
- end
- if (rd[i] && !wr[i] && (depth[i] == {DEPTHw{1'b0}} && SSA_EN =="YES" )) begin
- $display("%t: ERROR: Attempt to read an empty FIFO: %m",$time);
- $finish;
- end
- /* verilator lint_on WIDTH */
-
- //if (wr_en) $display($time, " %h is written on fifo ",din);
- end//~reset
- end//always
-
-//synopsys translate_on
-//synthesis translate_on
-
-
-
- end//FOR
-
-
- onehot_mux_1D #(
- .W(BVw),
- .N(V)
- )
- wr_mux
- (
- .in(wr_addr_all),
- .out(wr_addr),
- .sel(vc_num_wr)
- );
-
- onehot_mux_1D #(
- .W(BVw),
- .N(V)
- )
- rd_mux
- (
- .in(rd_addr_all),
- .out(rd_addr),
- .sel(vc_num_rd)
- );
-
- fifo_ram_mem_size #(
- .DATA_WIDTH (RAM_DATA_WIDTH),
- .MEM_SIZE (BV ),
- .SSA_EN(SSA_EN)
- )
- the_queue
- (
- .wr_data (fifo_ram_din),
- .wr_addr (wr_addr),
- .rd_addr (rd_addr),
- .wr_en (wr_en),
- .rd_en (rd_en),
- .clk (clk),
- .rd_data (fifo_ram_dout)
- );
-
-
-
-
-
-
- end
- endgenerate
-
-
-
-
-
-
-//synthesis translate_off
-//synopsys translate_off
-generate
-if(DEBUG_EN) begin :dbg
- always @(posedge clk) begin
- if(~reset)begin
- if(wr_en && vc_num_wr == {V{1'b0}})begin
- $display("%t: ERROR: Attempt to write when no wr VC is asserted: %m",$time);
- $finish;
- end
- if(rd_en && vc_num_rd == {V{1'b0}})begin
- $display("%t: ERROR: Attempt to read when no rd VC is asserted: %m",$time);
- $finish;
- end
- end
- end
-end
-endgenerate
-//synopsys translate_on
-//synthesis translate_on
-
-endmodule
-
-
-
-/****************************
-
- fifo_ram
-
-*****************************/
-
-
-
-module fifo_ram #(
- parameter DATA_WIDTH = 32,
- parameter ADDR_WIDTH = 8,
- parameter SSA_EN="YES" // "YES" , "NO"
- )
- (
- wr_data,
- wr_addr,
- rd_addr,
- wr_en,
- rd_en,
- clk,
- rd_data
- );
-
-
- input [DATA_WIDTH-1 : 0] wr_data;
- input [ADDR_WIDTH-1 : 0] wr_addr;
- input [ADDR_WIDTH-1 : 0] rd_addr;
- input wr_en;
- input rd_en;
- input clk;
- output [DATA_WIDTH-1 : 0] rd_data;
-
-
-
- reg [DATA_WIDTH-1:0] memory_rd_data;
- // memory
- reg [DATA_WIDTH-1:0] queue [2**ADDR_WIDTH-1:0] /* synthesis ramstyle = "no_rw_check , M9K" */;
- always @(posedge clk ) begin
- if (wr_en)
- queue[wr_addr] <= wr_data;
- if (rd_en)
- memory_rd_data <= queue[rd_addr];
- end
-
-
-
-
-
-
-
- generate
- /* verilator lint_off WIDTH */
- if(SSA_EN =="YES") begin :predict
- /* verilator lint_on WIDTH */
- //add bypass
- reg [DATA_WIDTH-1:0] bypass_reg;
- reg rd_en_delayed;
- always @(posedge clk ) begin
- bypass_reg <=wr_data;
- rd_en_delayed <=rd_en;
- end
-
- assign rd_data = (rd_en_delayed)? memory_rd_data : bypass_reg;
-
-
-
- end else begin : no_predict
- assign rd_data = memory_rd_data;
- end
- endgenerate
-endmodule
-
-
-
-/*********************
-*
-* fifo_ram_mem_size
-*
-**********************/
-
-
-module fifo_ram_mem_size #(
- parameter DATA_WIDTH = 32,
- parameter MEM_SIZE = 200,
- parameter SSA_EN = "YES" // "YES" , "NO"
- )
- (
- wr_data,
- wr_addr,
- rd_addr,
- wr_en,
- rd_en,
- clk,
- rd_data
- );
-
-
- function integer log2;
- input integer number; begin
- log2=(number <=1) ? 1: 0;
- while(2**log22) begin :mwb2
- wire [MUX_SEL_WIDTH-1 : 0] mux_sel;
- wire [DEPTH_DATA_WIDTH-1 : 0] depth_2;
- wire empty;
- wire out_sel ;
- if(DATA_WIDTH>1) begin :wb1
- wire [MAX_DEPTH-2 : 0] mux_in [DATA_WIDTH-1 :0];
- wire [DATA_WIDTH-1 : 0] mux_out;
- reg [MAX_DEPTH-2 : 0] shiftreg [DATA_WIDTH-1 :0];
-
- for(i=0;i= MAX_DEPTH [DEPTH_DATA_WIDTH-1 : 0] -1'b1;
- assign empty = depth == {DEPTH_DATA_WIDTH{1'b0}};
- assign recieve_more_than_0 = ~ empty;
- assign recieve_more_than_1 = ~( depth == {DEPTH_DATA_WIDTH{1'b0}} || depth== 1 );
- assign out_sel = (recieve_more_than_1) ? 1'b1 : 1'b0;
- assign out_ld = (depth !=0 )? rd_en : wr_en;
- assign depth_2 = depth - 2;
- assign mux_sel = depth_2[MUX_SEL_WIDTH-1 : 0] ;
-
- end else if ( MAX_DEPTH == 2) begin :mw2
-
- reg [DATA_WIDTH-1 : 0] register;
-
-
- always @(posedge clk ) begin
- if(wr_en) register <= din;
- end //always
-
- assign full = depth == MAX_DEPTH [DEPTH_DATA_WIDTH-1 : 0];
- assign nearly_full = depth >= MAX_DEPTH [DEPTH_DATA_WIDTH-1 : 0] -1'b1;
- assign out_ld = (depth !=0 )? rd_en : wr_en;
- assign recieve_more_than_0 = (depth != {DEPTH_DATA_WIDTH{1'b0}});
- assign recieve_more_than_1 = ~( depth == 0 || depth== 1 );
- assign dout_next = (recieve_more_than_1) ? register : din;
-
-
- end else begin :mw1 // MAX_DEPTH == 1
- assign out_ld = wr_en;
- assign dout_next = din;
- assign full = depth == MAX_DEPTH [DEPTH_DATA_WIDTH-1 : 0];
- assign nearly_full= 1'b1;
- assign recieve_more_than_0 = full;
- assign recieve_more_than_1 = 1'b0;
- end
-
-
-
- endgenerate
-
-
-
-
- `ifdef SYNC_RESET_MODE
- always @ (posedge clk )begin
- `else
- always @ (posedge clk or posedge reset)begin
- `endif
- if (reset) begin
- depth <= {DEPTH_DATA_WIDTH{1'b0}};
- end else begin
- if (wr_en & ~rd_en) depth <= depth + 1'h1;
- else if (~wr_en & rd_en) depth <= depth - 1'h1;
- end
- end//always
-
-
- `ifdef SYNC_RESET_MODE
- always @ (posedge clk )begin
- `else
- always @ (posedge clk or posedge reset)begin
- `endif
- if (reset) begin
- dout <= {DATA_WIDTH{1'b0}};
- end else begin
- if (out_ld) dout <= dout_next;
- end
- end//always
-
-//synthesis translate_off
-//synopsys translate_off
- always @(posedge clk)
- begin
- if(~reset)begin
- if (wr_en & ~rd_en & full) begin
- $display("%t: ERROR: Attempt to write to full FIFO:FIFO size is %d. %m",$time,MAX_DEPTH);
- $finish;
- end
- /* verilator lint_off WIDTH */
- if (rd_en & !recieve_more_than_0 & IGNORE_SAME_LOC_RD_WR_WARNING == "NO") begin
- $display("%t ERROR: Attempt to read an empty FIFO: %m", $time);
- $finish;
- end
- if (rd_en & ~wr_en & !recieve_more_than_0 & (IGNORE_SAME_LOC_RD_WR_WARNING == "YES")) begin
- $display("%t ERROR: Attempt to read an empty FIFO: %m", $time);
- $finish;
- end
- /* verilator lint_on WIDTH */
- end //~reset
- end // always @ (posedge clk)
-
-//synopsys translate_on
-//synthesis translate_on
-
-
-
-
-endmodule
-
-
-
-
-
-
-
-
-
-
-/*********************
-
- fwft_fifo_with_output_clear
- each individual output bit has
- its own clear signal
-
-**********************/
-
-
-
-
-
-module fwft_fifo_with_output_clear #(
- parameter DATA_WIDTH = 2,
- parameter MAX_DEPTH = 2,
- parameter IGNORE_SAME_LOC_RD_WR_WARNING="NO" // "YES" , "NO"
- )
- (
- din, // Data in
- wr_en, // Write enable
- rd_en, // Read the next word
- dout, // Data out
- full,
- nearly_full,
- recieve_more_than_0,
- recieve_more_than_1,
- reset,
- clk,
- clear
-
- );
-
- input [DATA_WIDTH-1:0] din;
- input wr_en;
- input rd_en;
- output reg [DATA_WIDTH-1:0] dout;
- output full;
- output nearly_full;
- output recieve_more_than_0;
- output recieve_more_than_1;
- input reset;
- input clk;
- input [DATA_WIDTH-1:0] clear;
-
- function integer log2;
- input integer number; begin
- log2=(number <=1) ? 1: 0;
- while(2**log22) begin :mwb2
- wire [MUX_SEL_WIDTH-1 : 0] mux_sel;
- wire [DEPTH_DATA_WIDTH-1 : 0] depth_2;
- wire empty;
- wire out_sel ;
- if(DATA_WIDTH>1) begin :wb1
- wire [MAX_DEPTH-2 : 0] mux_in [DATA_WIDTH-1 :0];
- wire [DATA_WIDTH-1 : 0] mux_out;
- reg [MAX_DEPTH-2 : 0] shiftreg [DATA_WIDTH-1 :0];
-
- for(i=0;i= MAX_DEPTH [DEPTH_DATA_WIDTH-1 : 0] -1'b1;
- assign empty = depth == {DEPTH_DATA_WIDTH{1'b0}};
- assign recieve_more_than_0 = ~ empty;
- assign recieve_more_than_1 = ~( depth == {DEPTH_DATA_WIDTH{1'b0}} || depth== 1 );
- assign out_sel = (recieve_more_than_1) ? 1'b1 : 1'b0;
- assign out_ld = (depth !=0 )? rd_en : wr_en;
- assign depth_2 = depth-2'd2;
- assign mux_sel = depth_2[MUX_SEL_WIDTH-1 : 0] ;
-
- end else if ( MAX_DEPTH == 2) begin :mw2
-
- reg [DATA_WIDTH-1 : 0] register;
-
- always @(posedge clk ) begin
- if(wr_en) register <= din;
- end //always
-
- assign full = depth == MAX_DEPTH [DEPTH_DATA_WIDTH-1 : 0];
- assign nearly_full = depth >= MAX_DEPTH [DEPTH_DATA_WIDTH-1 : 0] -1'b1;
- assign out_ld = (depth !=0 )? rd_en : wr_en;
- assign recieve_more_than_0 = (depth != {DEPTH_DATA_WIDTH{1'b0}});
- assign recieve_more_than_1 = ~( depth == 0 || depth== 1 );
- assign dout_next = (recieve_more_than_1) ? register : din;
-
- end else begin :mw1 // MAX_DEPTH == 1
- assign out_ld = wr_en;
- assign dout_next = din;
- assign full = depth == MAX_DEPTH [DEPTH_DATA_WIDTH-1 : 0];
- assign nearly_full= 1'b1;
- assign recieve_more_than_0 = full;
- assign recieve_more_than_1 = 1'b0;
- end
-endgenerate
-
-`ifdef SYNC_RESET_MODE
- always @ (posedge clk )begin
-`else
- always @ (posedge clk or posedge reset)begin
-`endif
- if (reset) begin
- depth <= {DEPTH_DATA_WIDTH{1'b0}};
- end else begin
- if (wr_en & ~rd_en) depth <= depth + 1'h1;
- else if (~wr_en & rd_en) depth <= depth - 1'h1;
- end
- end//always
-
- generate
- for(i=0;i= MAX_DEPTH [DEPTH_DATA_WIDTH-1 : 0] -1'b1;
- assign empty = depth == {DEPTH_DATA_WIDTH{1'b0}};
- assign recieve_more_than_0 = ~ empty;
- assign recieve_more_than_1 = ~( depth == {DEPTH_DATA_WIDTH{1'b0}} || depth== 1 );
-
-
-
-
-//synthesis translate_off
-//synopsys translate_off
- always @(posedge clk)
- begin
- if(~reset)begin
- if (wr_en & ~rd_en & full) begin
- $display("%t: ERROR: Attempt to write to full FIFO:FIFO size is %d. %m",$time,MAX_DEPTH);
- $finish;
- end
- /* verilator lint_off WIDTH */
- if (rd_en & !recieve_more_than_0 & IGNORE_SAME_LOC_RD_WR_WARNING == "NO") begin
- $display("%t ERROR: Attempt to read an empty FIFO: %m", $time);
- $finish;
- end
- if (rd_en & ~wr_en & !recieve_more_than_0 & (IGNORE_SAME_LOC_RD_WR_WARNING == "YES")) begin
- $display("%t ERROR: Attempt to read an empty FIFO: %m", $time);
- $finish;
- end
- /* verilator lint_on WIDTH */
- end //~reset
- end // always @ (posedge clk)
-
-//synopsys translate_on
-//synthesis translate_on
-
-
-
-
-endmodule
-
-
-
-
-
-
-
-
-
-/**********************************
-
- bram_based_fifo
-
-*********************************/
-
-
-module bram_based_fifo #(
- parameter Dw = 72,//data_width
- parameter B = 10// buffer num
-)(
- din,
- wr_en,
- rd_en,
- dout,
- full,
- nearly_full,
- empty,
- reset,
- clk
-);
-
-
- function integer log2;
- input integer number; begin
- log2=(number <=1) ? 1: 0;
- while(2**log2=Bint2; // B-1
-assign empty = depth == {DEPTHw{1'b0}};
-
-//synthesis translate_off
-//synopsys translate_off
-always @(posedge clk)
-begin
- if(~reset)begin
- if (wr_en && depth == B[DEPTHw-1 : 0] && !rd_en) begin
- $display(" %t: ERROR: Attempt to write to full FIFO: %m",$time);
- $finish;
- end
- if (rd_en && depth == {DEPTHw{1'b0}}) begin
- $display("%t: ERROR: Attempt to read an empty FIFO: %m",$time);
- $finish;
- end
- end//~reset
-end
-//synopsys translate_on
-//synthesis translate_on
-
-endmodule // fifo
-
-
mpsoc/rtl/src_noc/flit_buffer.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: mpsoc/rtl/src_noc/combined_vc_sw_alloc.v
===================================================================
--- mpsoc/rtl/src_noc/combined_vc_sw_alloc.v (revision 54)
+++ mpsoc/rtl/src_noc/combined_vc_sw_alloc.v (nonexistent)
@@ -1,287 +0,0 @@
-`timescale 1ns/1ps
-/**********************************************************************
-** File: combined_vc_sw_alloc.v
-**
-** Copyright (C) 2014-2017 Alireza Monemi
-**
-** This file is part of ProNoC
-**
-** ProNoC ( stands for Prototype Network-on-chip) is free software:
-** you can redistribute it and/or modify it under the terms of the GNU
-** Lesser General Public License as published by the Free Software Foundation,
-** either version 2 of the License, or (at your option) any later version.
-**
-** ProNoC is distributed in the hope that it will be useful, but WITHOUT
-** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
-** Public License for more details.
-**
-** You should have received a copy of the GNU Lesser General Public
-** License along with ProNoC. If not, see
.
-**
-**
-** Description:
-** combined VC/SW allocator. VC allocation is done in parallel with swich allocator
-** for header flits which are successfully get sw grant
-*************************************/
-
-
-module combined_vc_sw_alloc #(
- parameter V = 4, //VC number per port
- parameter P = 5, //port number
- parameter COMBINATION_TYPE = "BASELINE",// "BASELINE", "COMB_SPEC1", "COMB_SPEC2", "COMB_NONSPEC"
- parameter FIRST_ARBITER_EXT_P_EN = 1,
- parameter DEBUG_EN = 1,
- parameter SWA_ARBITER_TYPE = "RRA",//"RRA","WRRA". RRA: Round Robin Arbiter WRRA weighted Round Robin Arbiter
- parameter MIN_PCK_SIZE=2, //minimum packet size in flits. The minimum value is 1.
- parameter SELF_LOOP_EN= "NO"
-)
-(
-
- dest_port_all,
- masked_ovc_request_all,
- ovc_is_assigned_all,
- ivc_request_all,
- assigned_ovc_not_full_all,
- ovc_allocated_all,
- granted_ovc_num_all,
- ivc_num_getting_ovc_grant,
- ivc_num_getting_sw_grant,
- spec_first_arbiter_granted_ivc_all,
- nonspec_first_arbiter_granted_ivc_all,
- granted_dest_port_all,
- nonspec_granted_dest_port_all,
- spec_granted_dest_port_all,
- any_ivc_sw_request_granted_all,
- any_ovc_granted_in_outport_all,
- spec_ovc_num_all,
- vc_weight_is_consumed_all,
- iport_weight_is_consumed_all,
- pck_is_single_flit_all,
- granted_dst_is_from_a_single_flit_pck,
- clk,
- reset
-
-);
-
-
- localparam
- PV = V * P,
- PVV = PV * V,
- P_1 = (SELF_LOOP_EN == "NO")? P-1 : P,
- PP_1 = P_1 * P,
- PVP_1 = PV * P_1;
-
- input [PVP_1-1 : 0] dest_port_all;
- input [PVV-1 : 0] masked_ovc_request_all;
- input [PV-1 : 0] ovc_is_assigned_all;
- input [PV-1 : 0] ivc_request_all;
- input [PV-1 : 0] assigned_ovc_not_full_all;
- output [PV-1 : 0] ovc_allocated_all;
- output [PVV-1 : 0] granted_ovc_num_all;
- output [PV-1 : 0] ivc_num_getting_ovc_grant;
- output [PV-1 : 0] ivc_num_getting_sw_grant;
- output [PV-1 : 0] nonspec_first_arbiter_granted_ivc_all;
- output [PV-1 : 0] spec_first_arbiter_granted_ivc_all;
- output [P-1 : 0] any_ivc_sw_request_granted_all;
- output [P-1 : 0] any_ovc_granted_in_outport_all;
- output [PP_1-1 : 0] granted_dest_port_all;
- output [PP_1-1 : 0] nonspec_granted_dest_port_all;
- output [PP_1-1 : 0] spec_granted_dest_port_all;
- output [PVV-1 : 0] spec_ovc_num_all;
- // input [PVP_1-1 : 0] lk_destination_all;
- input [PV-1 : 0] vc_weight_is_consumed_all;
- input [P-1 : 0] iport_weight_is_consumed_all;
- input [PV-1 : 0] pck_is_single_flit_all;
- output [P-1 : 0] granted_dst_is_from_a_single_flit_pck;
-
- input clk,reset;
-
- generate
- /* verilator lint_off WIDTH */
- if(COMBINATION_TYPE == "BASELINE") begin : canonical_comb_gen
- /* verilator lint_on WIDTH */
- baseline_allocator #(
- .V(V),
- .P(P),
- .TREE_ARBITER_EN(1),
- .DEBUG_EN(DEBUG_EN),
- .SWA_ARBITER_TYPE (SWA_ARBITER_TYPE),
- .SELF_LOOP_EN(SELF_LOOP_EN)
- )
- the_base_line
- (
- .dest_port_all(dest_port_all),
- .masked_ovc_request_all(masked_ovc_request_all),
- .ovc_is_assigned_all(ovc_is_assigned_all),
- .ivc_request_all(ivc_request_all),
- .assigned_ovc_not_full_all(assigned_ovc_not_full_all),
- .ovc_allocated_all(ovc_allocated_all),
- .granted_ovc_num_all(granted_ovc_num_all),
- .ivc_num_getting_ovc_grant(ivc_num_getting_ovc_grant),
- .ivc_num_getting_sw_grant(ivc_num_getting_sw_grant),
- .spec_first_arbiter_granted_ivc_all(spec_first_arbiter_granted_ivc_all),
- .nonspec_first_arbiter_granted_ivc_all(nonspec_first_arbiter_granted_ivc_all),
- .granted_dest_port_all(granted_dest_port_all),
- .nonspec_granted_dest_port_all(nonspec_granted_dest_port_all),
- .spec_granted_dest_port_all(spec_granted_dest_port_all),
- .any_ivc_sw_request_granted_all(any_ivc_sw_request_granted_all),
- .spec_ovc_num_all(spec_ovc_num_all),
- .vc_weight_is_consumed_all(vc_weight_is_consumed_all),
- .iport_weight_is_consumed_all(iport_weight_is_consumed_all),
- .clk(clk),
- .reset(reset)
-
- );
- /* verilator lint_off WIDTH */
- end else if(COMBINATION_TYPE == "COMB_SPEC1") begin : spec1
- /* verilator lint_on WIDTH */
- comb_spec1_allocator #(
- .V(V),
- .P(P),
- .DEBUG_EN(DEBUG_EN),
- .SWA_ARBITER_TYPE (SWA_ARBITER_TYPE),
- .MIN_PCK_SIZE(MIN_PCK_SIZE),
- .SELF_LOOP_EN(SELF_LOOP_EN)
-
- )
- the_comb_spec1
- (
- .dest_port_all(dest_port_all),
- .masked_ovc_request_all(masked_ovc_request_all),
- .ovc_is_assigned_all(ovc_is_assigned_all),
- .ivc_request_all(ivc_request_all),
- .assigned_ovc_not_full_all(assigned_ovc_not_full_all),
- .ovc_allocated_all(ovc_allocated_all),
- .granted_ovc_num_all(granted_ovc_num_all),
- .ivc_num_getting_ovc_grant(ivc_num_getting_ovc_grant),
- .ivc_num_getting_sw_grant(ivc_num_getting_sw_grant),
- .spec_first_arbiter_granted_ivc_all(spec_first_arbiter_granted_ivc_all),
- .nonspec_first_arbiter_granted_ivc_all(nonspec_first_arbiter_granted_ivc_all),
- .granted_dest_port_all(granted_dest_port_all),
- .nonspec_granted_dest_port_all(nonspec_granted_dest_port_all),
- .any_ivc_sw_request_granted_all(any_ivc_sw_request_granted_all),
- .vc_weight_is_consumed_all(vc_weight_is_consumed_all),
- .iport_weight_is_consumed_all(iport_weight_is_consumed_all),
- .pck_is_single_flit_all(pck_is_single_flit_all),
- .granted_dst_is_from_a_single_flit_pck(granted_dst_is_from_a_single_flit_pck),
- .clk(clk),
- .reset(reset)
- );
-
- assign spec_granted_dest_port_all = {PP_1{1'bx}};
- assign spec_ovc_num_all = {PVV{1'bx}};
- /* verilator lint_off WIDTH */
- end else if (COMBINATION_TYPE == "COMB_SPEC2") begin :spec2
- /* verilator lint_on WIDTH */
- comb_spec2_allocator #(
- .V(V),
- .P(P),
- .DEBUG_EN(DEBUG_EN),
- .SWA_ARBITER_TYPE (SWA_ARBITER_TYPE),
- .MIN_PCK_SIZE(MIN_PCK_SIZE),
- .SELF_LOOP_EN(SELF_LOOP_EN)
- )
- the_comb_spec2
- (
- .dest_port_all(dest_port_all),
- .masked_ovc_request_all(masked_ovc_request_all),
- .ovc_is_assigned_all(ovc_is_assigned_all),
- .ivc_request_all(ivc_request_all),
- .assigned_ovc_not_full_all(assigned_ovc_not_full_all),
- .ovc_allocated_all(ovc_allocated_all),
- .granted_ovc_num_all(granted_ovc_num_all),
- .ivc_num_getting_ovc_grant(ivc_num_getting_ovc_grant),
- .ivc_num_getting_sw_grant(ivc_num_getting_sw_grant),
- .spec_first_arbiter_granted_ivc_all(spec_first_arbiter_granted_ivc_all),
- .nonspec_first_arbiter_granted_ivc_all(nonspec_first_arbiter_granted_ivc_all),
- .granted_dest_port_all(granted_dest_port_all),
- .nonspec_granted_dest_port_all(nonspec_granted_dest_port_all),
- .any_ivc_sw_request_granted_all(any_ivc_sw_request_granted_all),
- .vc_weight_is_consumed_all(vc_weight_is_consumed_all),
- .iport_weight_is_consumed_all(iport_weight_is_consumed_all),
- .pck_is_single_flit_all(pck_is_single_flit_all),
- .granted_dst_is_from_a_single_flit_pck(granted_dst_is_from_a_single_flit_pck),
- .clk(clk),
- .reset(reset)
- );
-
- assign spec_granted_dest_port_all = {PP_1{1'bx}};
- assign spec_ovc_num_all = {PVV{1'bx}};
-
-
- end else begin : nonspec
- if(V>7)begin :cmb_v2
-
- comb_nonspec_v2_allocator #(
- .V(V),
- .P(P),
- .FIRST_ARBITER_EXT_P_EN(FIRST_ARBITER_EXT_P_EN),
- .SWA_ARBITER_TYPE (SWA_ARBITER_TYPE),
- .MIN_PCK_SIZE(MIN_PCK_SIZE),
- .SELF_LOOP_EN(SELF_LOOP_EN)
- )
- nonspec_comb
- (
- .dest_port_all(dest_port_all),
- .masked_ovc_request_all(masked_ovc_request_all),
- .ovc_is_assigned_all(ovc_is_assigned_all),
- .ivc_request_all(ivc_request_all),
- .assigned_ovc_not_full_all(assigned_ovc_not_full_all),
- .ovc_allocated_all(ovc_allocated_all),
- .granted_ovc_num_all(granted_ovc_num_all),
- .ivc_num_getting_ovc_grant(ivc_num_getting_ovc_grant),
- .ivc_num_getting_sw_grant(ivc_num_getting_sw_grant),
- .nonspec_first_arbiter_granted_ivc_all(nonspec_first_arbiter_granted_ivc_all),
- .granted_dest_port_all(granted_dest_port_all),
- .any_ivc_sw_request_granted_all(any_ivc_sw_request_granted_all),
- .any_ovc_granted_in_outport_all(any_ovc_granted_in_outport_all),
- .vc_weight_is_consumed_all(vc_weight_is_consumed_all),
- .iport_weight_is_consumed_all(iport_weight_is_consumed_all),
- .pck_is_single_flit_all(pck_is_single_flit_all),
- .granted_dst_is_from_a_single_flit_pck(granted_dst_is_from_a_single_flit_pck),
- .clk(clk),
- .reset(reset)
- );
-
- end else begin :cmb_v1
-
- comb_nonspec_allocator #(
- .V(V),
- .P(P),
- .FIRST_ARBITER_EXT_P_EN(FIRST_ARBITER_EXT_P_EN),
- .SWA_ARBITER_TYPE (SWA_ARBITER_TYPE),
- .MIN_PCK_SIZE(MIN_PCK_SIZE),
- .SELF_LOOP_EN(SELF_LOOP_EN)
- )
- nonspec_comb
- (
- .dest_port_all(dest_port_all),
- .masked_ovc_request_all(masked_ovc_request_all),
- .ovc_is_assigned_all(ovc_is_assigned_all),
- .ivc_request_all(ivc_request_all),
- .assigned_ovc_not_full_all(assigned_ovc_not_full_all),
- .ovc_allocated_all(ovc_allocated_all),
- .granted_ovc_num_all(granted_ovc_num_all),
- .ivc_num_getting_ovc_grant(ivc_num_getting_ovc_grant),
- .ivc_num_getting_sw_grant(ivc_num_getting_sw_grant),
- .nonspec_first_arbiter_granted_ivc_all(nonspec_first_arbiter_granted_ivc_all),
- .granted_dest_port_all(granted_dest_port_all),
- .any_ivc_sw_request_granted_all(any_ivc_sw_request_granted_all),
- .any_ovc_granted_in_outport_all(any_ovc_granted_in_outport_all),
- .vc_weight_is_consumed_all(vc_weight_is_consumed_all),
- .iport_weight_is_consumed_all(iport_weight_is_consumed_all),
- .pck_is_single_flit_all(pck_is_single_flit_all),
- .granted_dst_is_from_a_single_flit_pck(granted_dst_is_from_a_single_flit_pck),
- .clk(clk),
- .reset(reset)
- );
- end
-
- assign nonspec_granted_dest_port_all = granted_dest_port_all;
- assign spec_granted_dest_port_all = {PP_1{1'bx}};
- assign spec_ovc_num_all = {PVV{1'bx}};
- assign spec_first_arbiter_granted_ivc_all = nonspec_first_arbiter_granted_ivc_all ;
- end
-endgenerate
-endmodule
mpsoc/rtl/src_noc/combined_vc_sw_alloc.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: mpsoc/rtl/src_noc/comb_nonspec.v
===================================================================
--- mpsoc/rtl/src_noc/comb_nonspec.v (revision 54)
+++ mpsoc/rtl/src_noc/comb_nonspec.v (nonexistent)
@@ -1,970 +0,0 @@
-`timescale 1ns/1ps
-
-/**********************************************************************
-** File: comb-nonspec.v
-**
-** Copyright (C) 2014-2017 Alireza Monemi
-**
-** This file is part of ProNoC
-**
-** ProNoC ( stands for Prototype Network-on-chip) is free software:
-** you can redistribute it and/or modify it under the terms of the GNU
-** Lesser General Public License as published by the Free Software Foundation,
-** either version 2 of the License, or (at your option) any later version.
-**
-** ProNoC is distributed in the hope that it will be useful, but WITHOUT
-** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
-** Public License for more details.
-**
-** You should have received a copy of the GNU Lesser General Public
-** License along with ProNoC. If not, see
.
-**
-**
-** Description:
-** VC allocator combined with non-speculative switch
-** allocator where the free VC availability is checked at
-** the beginning of switch allocation (comb-nonspec).
-**
-***********************************************************************/
-
-
-module comb_nonspec_allocator #(
- parameter V = 4,
- parameter P = 5,
- parameter FIRST_ARBITER_EXT_P_EN = 1,
- // parameter VC_ARBITER_TYPE = "RRA", // "RRA", "FIX_PR"
- parameter SWA_ARBITER_TYPE = "WRRA",// "RRA", "WRRA"
- parameter MIN_PCK_SIZE=2, //minimum packet size in flits. The minimum value is 1.
- parameter SELF_LOOP_EN= "NO"
-)(
- //VC allocator
- //input
- dest_port_all, // from input port
- ovc_is_assigned_all, //
- masked_ovc_request_all,
- pck_is_single_flit_all,
-
-
- //output
- ovc_allocated_all,//to the output port
- granted_ovc_num_all, // to the input port
- ivc_num_getting_ovc_grant,
-
- //switch_alloc
- ivc_request_all,
- assigned_ovc_not_full_all,
- vc_weight_is_consumed_all,
- iport_weight_is_consumed_all,
-
- //output
- granted_dest_port_all,
- ivc_num_getting_sw_grant,
- nonspec_first_arbiter_granted_ivc_all,
- any_ivc_sw_request_granted_all,
- any_ovc_granted_in_outport_all,
- granted_dst_is_from_a_single_flit_pck,
-
- // global
- clk,
- reset
-
-);
-
- localparam
- P_1 = (SELF_LOOP_EN == "NO")? P-1 : P,
- PV = V * P,
- VV = V * V,
- VP_1 = V * P_1,
- PP_1 = P_1 * P,
- PVV = PV * V,
- PVP_1 = PV * P_1;
-
-
- input [PVV-1 : 0] masked_ovc_request_all;
- input [PVP_1-1 : 0] dest_port_all;
- input [PV-1 : 0] ovc_is_assigned_all;
- input [PV-1 : 0] pck_is_single_flit_all;
- output [PV-1 : 0] ovc_allocated_all;
- output [PVV-1 : 0] granted_ovc_num_all;
- output [PV-1 : 0] ivc_num_getting_ovc_grant;
- input [PV-1 : 0] ivc_request_all;
- input [PV-1 : 0] assigned_ovc_not_full_all;
- output [PP_1-1 : 0] granted_dest_port_all;
- output [PV-1 : 0] ivc_num_getting_sw_grant;
- output [P-1 : 0] any_ivc_sw_request_granted_all;
- output [P-1 : 0] any_ovc_granted_in_outport_all;
- output [PV-1 : 0] nonspec_first_arbiter_granted_ivc_all;
- // input [PVP_1-1 : 0] lk_destination_all;
- input clk,reset;
- input [PV-1 : 0] vc_weight_is_consumed_all;
- input [P-1 : 0] iport_weight_is_consumed_all;
- output [P-1 : 0] granted_dst_is_from_a_single_flit_pck;
-
-
-
- //internal wires switch allocator
- wire [PV-1 : 0] first_arbiter_granted_ivc_all;
- wire [PV-1 : 0] ivc_request_masked_all;
- wire [P-1 : 0] any_cand_ovc_exsit;
-
- assign nonspec_first_arbiter_granted_ivc_all = first_arbiter_granted_ivc_all;
-
-
- //nonspeculative switch allocator
- nonspec_sw_alloc #(
- .V(V),
- .P(P),
- .FIRST_ARBITER_EXT_P_EN(FIRST_ARBITER_EXT_P_EN),
- .SWA_ARBITER_TYPE (SWA_ARBITER_TYPE),
- .MIN_PCK_SIZE(MIN_PCK_SIZE),
- .SELF_LOOP_EN(SELF_LOOP_EN)
- )
- nonspeculative_sw_allocator
- (
-
- .ivc_granted_all (ivc_num_getting_sw_grant),
- .ivc_request_masked_all (ivc_request_masked_all),
- .pck_is_single_flit_all(pck_is_single_flit_all),
- .granted_dst_is_from_a_single_flit_pck(granted_dst_is_from_a_single_flit_pck),
- .dest_port_all (dest_port_all),
- .granted_dest_port_all (granted_dest_port_all),
- .first_arbiter_granted_ivc_all (first_arbiter_granted_ivc_all),
- .any_ivc_granted_all (any_ivc_sw_request_granted_all),
- .any_ovc_granted_all (any_ovc_granted_in_outport_all),
- .vc_weight_is_consumed_all(vc_weight_is_consumed_all),
- .iport_weight_is_consumed_all(iport_weight_is_consumed_all),
- .clk (clk),
- .reset (reset)
-
- );
-
-
-
- wire [PVV-1 : 0] masked_ovc_request_all;
- wire [V-1 : 0] masked_non_assigned_request [PV-1 : 0] ;
- wire [PV-1 : 0] masked_assigned_request;
- wire [PV-1 : 0] assigned_ovc_request_all ;
- wire [VV-1 : 0] masked_candidate_ovc_per_port [P-1 : 0] ;
- wire [V-1 : 0] first_arbiter_granted_ivc_per_port[P-1 : 0] ;
- wire [V-1 : 0] candidate_ovc_local_num [P-1 : 0] ;
- wire [V-1 : 0] first_arbiter_ovc_granted [PV-1 : 0];
- wire [P_1-1 : 0] granted_dest_port_per_port [P-1 : 0];
- wire [VP_1-1 : 0] cand_ovc_granted [P-1 : 0];
- wire [P_1-1 : 0] ovc_allocated_all_gen [PV-1 : 0];
- wire [V-1 : 0] granted_ovc_local_num_per_port [P-1 : 0];
- wire [V-1 : 0] ivc_local_num_getting_ovc_grant[P-1 : 0];
- wire [V : 0] summ_in [PV-1 : 0];
- wire [V-1 : 0] vc_pririty [PV-1 : 0] ;
-
- assign assigned_ovc_request_all = ivc_request_all & ovc_is_assigned_all;
-
- genvar i,j;
-
-
- generate
- // IVC loop
- for(i=0;i< PV;i=i+1) begin :total_vc_loop
-
- // mask unavailable ovc from requests
- assign masked_non_assigned_request [i] = masked_ovc_request_all [(i+1)*V-1 : i*V ];
- assign masked_assigned_request [i] = assigned_ovc_not_full_all [i] & assigned_ovc_request_all [i];
-
- // summing assigned and non-assigned VC requests
- assign summ_in[i] ={masked_non_assigned_request [i],masked_assigned_request [i]};
- assign ivc_request_masked_all[i] = | summ_in[i];
-
-
- //first level arbiter to candidate only one OVC
- // if(VC_ARBITER_TYPE=="RRA")begin :round_robin
-
- arbiter #(
- .ARBITER_WIDTH(V)
- )
- ovc_arbiter
- (
- .clk (clk),
- .reset (reset),
- .request (masked_non_assigned_request [i]),
- .grant (first_arbiter_ovc_granted[i]),
- .any_grant ()
- );
- /*
- end else begin :fixarb
-
- vc_priority_based_dest_port#(
- .P(P),
- .V(V)
- )
- priority_setting
- (
- .dest_port(lk_destination_all [((i+1)*P_1)-1 : i*P_1]),
- .vc_pririty(vc_pririty[i])
- );
-
-
-
- arbiter_ext_priority #(
- .ARBITER_WIDTH (V)
- )
- ovc_arbiter
- (
- .request (masked_non_assigned_request [i]),
- .priority_in(vc_pririty[i]),
- .grant(first_arbiter_ovc_granted[i]),
- .any_grant()
- );
-
- end
- */
-
- end//for
-
-
- for(i=0;i< P;i=i+1) begin :port_loop3
- for(j=0;j< V;j=j+1) begin :vc_loop
- //merge masked_candidate_ovc in each port
- assign masked_candidate_ovc_per_port[i][(j+1)*V-1 : j*V] = first_arbiter_ovc_granted [i*V+j];
- end//for j
-
- assign first_arbiter_granted_ivc_per_port[i]=first_arbiter_granted_ivc_all[(i+1)*V-1 : i*V];
- assign granted_dest_port_per_port[i]=granted_dest_port_all[(i+1)*P_1-1 : i*P_1];
-
-
- // multiplex candidate OVC of first level switch allocatore winner
- onehot_mux_1D #(
- .W (V),
- .N (V)
- )
- multiplexer2
- (
- .in (masked_candidate_ovc_per_port [i]),
- .out (candidate_ovc_local_num [i]),
- .sel (first_arbiter_granted_ivc_per_port [i])
-
- );
-
- assign any_cand_ovc_exsit[i] = | candidate_ovc_local_num [i];
-
-
- //demultiplexer
- one_hot_demux #(
- .IN_WIDTH(V),
- .SEL_WIDTH(P_1)
- )
- demux1
- (
- .demux_sel(granted_dest_port_per_port [i]),//selectore
- .demux_in(candidate_ovc_local_num[i]),//repeated
- .demux_out(cand_ovc_granted [i])
- );
-
- assign granted_ovc_local_num_per_port [i]=(any_ivc_sw_request_granted_all[i] )? candidate_ovc_local_num[i] : {V{1'b0}};
- assign ivc_local_num_getting_ovc_grant [i]= (any_ivc_sw_request_granted_all[i] & any_cand_ovc_exsit[i])? first_arbiter_granted_ivc_per_port [i] : {V{1'b0}};
- assign ivc_num_getting_ovc_grant [(i+1)*V-1 : i*V] = ivc_local_num_getting_ovc_grant[i];
- for(j=0;j
j) begin: hh
- assign ovc_allocated_all_gen[i][j] = cand_ovc_granted[j][i-V];
-
- end
- end else begin : slp
- assign ovc_allocated_all_gen[i][j] = cand_ovc_granted[j][i];
- end
- end//j
-
- assign ovc_allocated_all [i] = |ovc_allocated_all_gen[i];
-
- end//i
-
- endgenerate
-
-endmodule
-
-
-
-
-/**************************************************************
-*
-* comb_nonspec_v2
-*
-* first arbiter has been shifted after first multiplexer
-*
-*
-*********************************************************/
-
-
-
-module comb_nonspec_v2_allocator #(
- parameter V = 4,
- parameter P = 5,
- parameter FIRST_ARBITER_EXT_P_EN = 1,
- parameter SWA_ARBITER_TYPE = "WRRA",
- parameter MIN_PCK_SIZE=2, //minimum packet size in flits. The minimum value is 1.
- parameter SELF_LOOP_EN= "NO"
-
-)(
- //VC allocator
- //input
- dest_port_all, // from input port
- ovc_is_assigned_all, //
- masked_ovc_request_all,
- pck_is_single_flit_all,
-
- //output
- ovc_allocated_all,//to the output port
- granted_ovc_num_all, // to the input port
- ivc_num_getting_ovc_grant,
-
- //switch_alloc
- ivc_request_all,
- assigned_ovc_not_full_all,
- vc_weight_is_consumed_all,
- iport_weight_is_consumed_all,
-
- //output
- granted_dest_port_all,
- ivc_num_getting_sw_grant,
- nonspec_first_arbiter_granted_ivc_all,
- any_ivc_sw_request_granted_all,
- any_ovc_granted_in_outport_all,
- granted_dst_is_from_a_single_flit_pck,
-
- // global
- clk,
- reset
-
-);
-
-
- localparam
- P_1 = (SELF_LOOP_EN == "NO") ? P-1 :P,
- PV = V * P,
- VV = V * V,
- VP_1 = V * P_1,
- PP_1 = P_1 * P,
- PVV = PV * V,
- PVP_1 = PV * P_1;
-
-
-
-
- input [PVV-1 : 0] masked_ovc_request_all;
- input [PVP_1-1 : 0] dest_port_all;
- input [PV-1 : 0] ovc_is_assigned_all;
- input [PV-1 : 0] pck_is_single_flit_all;
- output [PV-1 : 0] ovc_allocated_all;
- output [PVV-1 : 0] granted_ovc_num_all;
- output [PV-1 : 0] ivc_num_getting_ovc_grant;
- input [PV-1 : 0] ivc_request_all;
- input [PV-1 : 0] assigned_ovc_not_full_all;
- output [PP_1-1 : 0] granted_dest_port_all;
- output [PV-1 : 0] ivc_num_getting_sw_grant;
- output [P-1 : 0] any_ivc_sw_request_granted_all;
- output [P-1 : 0] any_ovc_granted_in_outport_all;
- output [PV-1 : 0] nonspec_first_arbiter_granted_ivc_all;
- input clk,reset;
- input [PV-1 : 0] vc_weight_is_consumed_all;
- input [P-1 : 0] iport_weight_is_consumed_all;
-
- //internal wires switch allocator
- wire [PV-1 : 0] first_arbiter_granted_ivc_all;
- wire [PV-1 : 0] ivc_request_masked_all;
- wire [P-1 : 0] any_cand_ovc_exsit;
- output [P-1 : 0] granted_dst_is_from_a_single_flit_pck;
-
- assign nonspec_first_arbiter_granted_ivc_all = first_arbiter_granted_ivc_all;
-
- //nonspeculative switch allocator
- nonspec_sw_alloc #(
- .V(V),
- .P(P),
- .FIRST_ARBITER_EXT_P_EN(FIRST_ARBITER_EXT_P_EN),
- .SWA_ARBITER_TYPE(SWA_ARBITER_TYPE),
- .MIN_PCK_SIZE(MIN_PCK_SIZE)
- )
- nonspeculative_sw_allocator
- (
-
- .ivc_granted_all (ivc_num_getting_sw_grant),
- .ivc_request_masked_all (ivc_request_masked_all),
- .pck_is_single_flit_all(pck_is_single_flit_all),
- .granted_dst_is_from_a_single_flit_pck(granted_dst_is_from_a_single_flit_pck),
- .dest_port_all (dest_port_all),
- .granted_dest_port_all (granted_dest_port_all),
- .first_arbiter_granted_ivc_all (first_arbiter_granted_ivc_all),
- //.first_arbiter_granted_port_all (first_arbiter_granted_port_all),
- .any_ivc_granted_all (any_ivc_sw_request_granted_all),
- .any_ovc_granted_all (any_ovc_granted_in_outport_all),
- .vc_weight_is_consumed_all(vc_weight_is_consumed_all),
- .iport_weight_is_consumed_all(iport_weight_is_consumed_all),
- .clk (clk),
- .reset (reset)
-
- );
-
- wire [V-1 : 0] masked_non_assigned_request [PV-1 : 0] ;
- wire [PV-1 : 0] masked_assigned_request;
- wire [PV-1 : 0] assigned_ovc_request_all;
- wire [VV-1 : 0] masked_non_assigned_request_per_port [P-1 : 0] ;
- wire [V-1 : 0] first_arbiter_granted_ivc_per_port[P-1 : 0] ;
- wire [V-1 : 0] candidate_ovc_local_num [P-1 : 0] ;
- wire [V-1 : 0] first_arbiter_ovc_granted [P-1:0];
- wire [P_1-1 : 0] granted_dest_port_per_port [P-1 : 0];
- wire [VP_1-1 : 0] cand_ovc_granted [P-1 : 0];
- wire [P_1-1 : 0] ovc_allocated_all_gen [PV-1 : 0];
- wire [V-1 : 0] granted_ovc_local_num_per_port [P-1 : 0];
- wire [V-1 : 0] ivc_local_num_getting_ovc_grant[P-1 : 0];
- wire [V : 0] summ_in [PV-1 : 0];
-
-
- assign assigned_ovc_request_all = ivc_request_all & ovc_is_assigned_all;
-
- genvar i,j;
- generate
-
- // IVC loop
- for(i=0;i< PV;i=i+1) begin :total_vc_loop
-
- // mask unavailable ovc from requests
- assign masked_non_assigned_request [i] = masked_ovc_request_all [(i+1)*V-1 : i*V ];
- assign masked_assigned_request [i] = assigned_ovc_not_full_all[i] & assigned_ovc_request_all[i];
-
- // summing assigned and non-assigned VC requests
- assign summ_in[i] ={masked_non_assigned_request [i],masked_assigned_request [i]};
- assign ivc_request_masked_all[i] = | summ_in[i];
-
- end//for
-
-
- for(i=0;i< P;i=i+1) begin :port_loop3
- for(j=0;j< V;j=j+1) begin :vc_loop
- //merge masked_candidate_ovc in each port
- assign masked_non_assigned_request_per_port[i][(j+1)*V-1 : j*V] = masked_non_assigned_request [i*V+j];
- end//for j
-
- assign first_arbiter_granted_ivc_per_port[i]=first_arbiter_granted_ivc_all[(i+1)*V-1 : i*V];
-
- assign granted_dest_port_per_port[i]=granted_dest_port_all[(i+1)*P_1-1 : i*P_1];
-
-
- onehot_mux_1D #(
- .W (V),
- .N (V)
- )
- multiplexer2
- (
- .in (masked_non_assigned_request_per_port [i]),
- .out (candidate_ovc_local_num [i]),
- .sel (first_arbiter_granted_ivc_per_port [i])
-
- );
-
-
- assign any_cand_ovc_exsit[i] = | candidate_ovc_local_num [i];
-
- //first level arbiter to candidate only one OVC
- arbiter #(
- .ARBITER_WIDTH (V)
- )
- first_arbiter
- (
- .clk (clk),
- .reset (reset),
- .request (candidate_ovc_local_num[i]),
- .grant (first_arbiter_ovc_granted[i]),
- .any_grant ( )
- );
-
-
- //demultiplexer
- one_hot_demux #(
- .IN_WIDTH (V),
- .SEL_WIDTH (P_1)
- )
- demux1
- (
- .demux_sel (granted_dest_port_per_port [i]),//selectore
- .demux_in (first_arbiter_ovc_granted[i]),//repeated
- .demux_out (cand_ovc_granted [i])
- );
-
-
- assign granted_ovc_local_num_per_port [i]=(any_ivc_sw_request_granted_all[i] )? first_arbiter_ovc_granted[i] : {V{1'b0}};
- assign ivc_local_num_getting_ovc_grant [i]= (any_ivc_sw_request_granted_all[i] & any_cand_ovc_exsit[i])? first_arbiter_granted_ivc_per_port [i] : {V{1'b0}};
- assign ivc_num_getting_ovc_grant [(i+1)*V-1 : i*V] = ivc_local_num_getting_ovc_grant[i];
- for(j=0;jj) begin: hh
- assign ovc_allocated_all_gen[i][j] = cand_ovc_granted[j][i-V];
-
- end
- end//j
-
- assign ovc_allocated_all [i] = |ovc_allocated_all_gen[i];
-
- end//i
-
- endgenerate
-
-
-endmodule
-
-
-/********************************************
-*
-* nonspeculative switch allocator
-*
-******************************************/
-
-module nonspec_sw_alloc #(
- parameter V = 4,
- parameter P = 5,
- parameter FIRST_ARBITER_EXT_P_EN = 1,
- parameter SWA_ARBITER_TYPE = "WRRA",
- parameter MIN_PCK_SIZE=2, //minimum packet size in flits. The minimum value is 1.
- parameter SELF_LOOP_EN="NO"
-
-)(
-
- ivc_granted_all,
- ivc_request_masked_all,
- pck_is_single_flit_all,
- granted_dst_is_from_a_single_flit_pck,
- dest_port_all,
- granted_dest_port_all,
- first_arbiter_granted_ivc_all,
- //first_arbiter_granted_port_all,
- any_ivc_granted_all,
- any_ovc_granted_all,
- vc_weight_is_consumed_all,
- iport_weight_is_consumed_all,
- clk,
- reset
-
-);
-
- localparam
- P_1 = (SELF_LOOP_EN== "NO") ? P-1 : P,
- PV = V * P,
- VP_1 = V * P_1,
- PP_1 = P_1 * P,
- PVP_1 = PV * P_1,
- PP = P*P;
-
-
- output [PV-1 : 0] ivc_granted_all;
- output [P-1 : 0] granted_dst_is_from_a_single_flit_pck;
- input [PV-1 : 0] ivc_request_masked_all;
- input [PV-1 : 0] pck_is_single_flit_all;
- input [PVP_1-1 : 0] dest_port_all;
- output [PP_1-1 : 0] granted_dest_port_all;
- output [PV-1 : 0] first_arbiter_granted_ivc_all;
- //output [PP_1-1 : 0] first_arbiter_granted_port_all;
- output [P-1 : 0] any_ivc_granted_all; //any ivc is granted in input port [i]
- output [P-1 : 0] any_ovc_granted_all; //any ovc is granted in output port [i]
- input clk, reset;
- input [PV-1 : 0] vc_weight_is_consumed_all;
- input [P-1: 0] iport_weight_is_consumed_all;
-
- //separte input per port
- wire [V-1 : 0] ivc_granted [P-1 : 0];
- wire [V-1 : 0] pck_is_single_flit [P-1 : 0];
- wire [VP_1-1 : 0] dest_port_ivc [P-1 : 0];
- wire [P_1-1 : 0] granted_dest_port [P-1 : 0];
- wire [P_1-1 : 0] single_flit_granted_dst [P-1 : 0];
- wire [PP-1 : 0] single_flit_granted_dst_all;
-
- // internal wires
- wire [V-1 : 0] ivc_masked [P-1 : 0];//output of mask and
- wire [V-1 : 0] first_arbiter_grant [P-1 : 0];//output of first arbiter
- wire [P-1 : 0] single_flit_pck_local_grant;
- wire [P_1-1 : 0] dest_port [P-1 : 0];//output of multiplexer
- wire [P_1-1 : 0] second_arbiter_request [P-1 : 0];
- wire [P_1-1 : 0] second_arbiter_grant [P-1 : 0];
- wire [P_1-1 : 0] second_arbiter_weight_consumed [P-1 : 0];
- wire [V-1 : 0] vc_weight_is_consumed [P-1 : 0];
- wire [P-1 :0] winner_weight_consumed;
-
- genvar i,j;
- generate
-
- for(i=0;i< P;i=i+1) begin :port_loop
- //assign in/out to the port based wires
- //output
- assign ivc_granted_all [(i+1)*V-1 : i*V] = ivc_granted [i];
- assign granted_dest_port_all [(i+1)*P_1-1 : i*P_1] = granted_dest_port[i];
- assign first_arbiter_granted_ivc_all[(i+1)*V-1 : i*V]= first_arbiter_grant[i];
- //input
- assign ivc_masked[i] = ivc_request_masked_all [(i+1)*V-1 : i*V];
-
- assign dest_port_ivc[i] = dest_port_all [(i+1)*VP_1-1 : i*VP_1];
- assign vc_weight_is_consumed[i] = vc_weight_is_consumed_all [(i+1)*V-1 : i*V];
-
- //first level arbiter
- swa_input_port_arbiter #(
- .ARBITER_WIDTH(V),
- .EXT_P_EN(FIRST_ARBITER_EXT_P_EN),
- .ARBITER_TYPE(SWA_ARBITER_TYPE)
- )
- input_arbiter
- (
- .ext_pr_en_i(any_ivc_granted_all[i]),
- .request(ivc_masked [i]),
- .grant(first_arbiter_grant[i]),
- .any_grant( ),
- .clk(clk),
- .reset(reset),
- .vc_weight_is_consumed(vc_weight_is_consumed[i]),
- .winner_weight_consumed(winner_weight_consumed[i])
- );
-
-
-
- //destination port multiplexer
- onehot_mux_1D #(
- .W (P_1),
- .N (V)
- )
- multiplexer
- (
- .in (dest_port_ivc [i]),
- .out (dest_port [i]),
- .sel(first_arbiter_grant[i])
-
- );
- if(MIN_PCK_SIZE == 1) begin :single_flit_supported
- //single_flit req multiplexer
- assign pck_is_single_flit[i] = pck_is_single_flit_all [(i+1)*V-1 : i*V];
- onehot_mux_1D #(
- .W (1),
- .N (V)
- )
- multiplexer2
- (
- .in (pck_is_single_flit [i]),
- .out (single_flit_pck_local_grant[i]),
- .sel (first_arbiter_grant[i])
-
- );
-
- assign single_flit_granted_dst[i] = (single_flit_pck_local_grant[i])? granted_dest_port[i] : {P_1{1'b0}};
-
- if (SELF_LOOP_EN == "NO") begin :nslp
- add_sw_loc_one_hot #(
- .P(P),
- .SW_LOC(i)
- )
- add_sw_loc
- (
- .destport_in(single_flit_granted_dst[i]),
- .destport_out(single_flit_granted_dst_all[(i+1)*P-1 : i*P])
- );
- end else begin :slp
- assign single_flit_granted_dst_all[(i+1)*P-1 : i*P] = single_flit_granted_dst[i];
- end
-
- end else begin : single_flit_notsupported
- assign single_flit_pck_local_grant[i] = 1'bx;
- assign single_flit_granted_dst[i] = {P_1{1'bx}};
- assign single_flit_granted_dst_all[(i+1)*P-1 : i*P]={P{1'b0}};
- end
- //second arbiter input/output generate
-
-
- for(j=0;jj)begin: hh
- assign second_arbiter_request[i][j] = dest_port [j][i-1] ;
- //assign second_arbiter_weight_consumed[i][j] =winner_weight_consumed[j];
- assign second_arbiter_weight_consumed[i][j] =iport_weight_is_consumed_all[j];
- assign granted_dest_port[j][i-1] = second_arbiter_grant [i][j] ;
- end
- //if(i==j) wires are left disconnected
- end else begin :slp
- assign second_arbiter_request[i][j] = dest_port[j][i];
- assign second_arbiter_weight_consumed[i][j] =iport_weight_is_consumed_all[j] ;
- assign granted_dest_port[j][i] = second_arbiter_grant [i][j] ;
- end
- end
-
-
- //second level arbiter
- swa_output_port_arbiter #(
- .ARBITER_WIDTH(P_1),
- .ARBITER_TYPE(SWA_ARBITER_TYPE) // RRA, WRRA
- )
- output_arbiter
- (
- .weight_consumed(second_arbiter_weight_consumed[i]), // only used for WRRA
- .clk(clk),
- .reset(reset),
- .request(second_arbiter_request [i]),
- .grant(second_arbiter_grant [i]),
- .any_grant(any_ovc_granted_all [i])
- );
-
-
- //any ivc
- assign any_ivc_granted_all[i] = | granted_dest_port[i];
- assign ivc_granted[i] = (any_ivc_granted_all[i]) ? first_arbiter_grant[i] : {V{1'b0}};
-
-
- end//for
- endgenerate
-
-
- custom_or #(
- .IN_NUM(P),
- .OUT_WIDTH(P)
- )
- or_dst
- (
- .or_in(single_flit_granted_dst_all),
- .or_out(granted_dst_is_from_a_single_flit_pck)
- );
-
-endmodule
-
-
-
-/*******************
-* swa_input_port_arbiter
-*
-********************/
-
-
-module swa_input_port_arbiter #(
- parameter ARBITER_WIDTH =4,
- parameter EXT_P_EN = 1,
- parameter ARBITER_TYPE = "WRRA"// RRA, WRRA
-
-)(
- ext_pr_en_i, // it is used only if the EXT_P_EN is 1
- clk,
- reset,
- request,
- grant,
- any_grant,
- vc_weight_is_consumed, // only for WRRA
- winner_weight_consumed // only for WRRA
-);
-
-
-
-
-
- input ext_pr_en_i;
- input [ARBITER_WIDTH-1 : 0] request;
- output[ARBITER_WIDTH-1 : 0] grant;
- output any_grant;
- input clk;
- input reset;
- input [ARBITER_WIDTH-1 : 0] vc_weight_is_consumed;
- output winner_weight_consumed;
-
-
- generate
- /* verilator lint_off WIDTH */
- if(ARBITER_TYPE != "RRA") begin : wrra_m
- /* verilator lint_on WIDTH */
-
- // one hot mux
- onehot_mux_1D #(
- .W(1),
- .N(ARBITER_WIDTH)
- )
- mux
- (
- .in(vc_weight_is_consumed),
- .out(winner_weight_consumed),
- .sel(grant)
- );
-
- wire priority_en = (EXT_P_EN == 1) ? ext_pr_en_i & winner_weight_consumed : winner_weight_consumed;
-
- //round robin arbiter with external priority
-
- arbiter_priority_en #(
- .ARBITER_WIDTH(ARBITER_WIDTH)
- )
- rra
- (
- .request(request),
- .grant(grant),
- .any_grant(any_grant),
- .clk(clk),
- .reset(reset),
- .priority_en(priority_en)
- );
-
- end else begin : rra_m //RRA
- assign winner_weight_consumed = 1'bx;
- if(EXT_P_EN==1) begin : arbiter_ext_en
-
- arbiter_priority_en #(
- .ARBITER_WIDTH (ARBITER_WIDTH)
- )
- arb
- (
- .clk (clk),
- .reset (reset),
- .request (request),
- .grant (grant),
- .any_grant (any_grant ),
- .priority_en (ext_pr_en_i)
- );
-
- end else begin: first_lvl_arbiter_internal_en
-
- arbiter #(
- .ARBITER_WIDTH (ARBITER_WIDTH)
- )
- arb
- (
- .clk (clk),
- .reset (reset),
- .request (request),
- .grant (grant),
- .any_grant (any_grant )
- );
-
- end//else
-
- end
- endgenerate
-
-endmodule
-
-
-
-
-/*******************
-* swa_output_port_arbiter
-*
-********************/
-
-
-module swa_output_port_arbiter #(
- parameter ARBITER_WIDTH =4,
- parameter ARBITER_TYPE = "WRRA" // RRA, WRRA
-
-
-)(
- weight_consumed, // only used for WRRA
- clk,
- reset,
- request,
- grant,
- any_grant
-);
-
-
-
- input [ARBITER_WIDTH-1 : 0] request;
- output [ARBITER_WIDTH-1 : 0] grant;
- output any_grant;
- input clk;
- input reset;
- input [ARBITER_WIDTH-1 : 0] weight_consumed;
-
-
-
- generate
- /* verilator lint_off WIDTH */
- if(ARBITER_TYPE == "WRRA") begin : wrra_mine
- /* verilator lint_on WIDTH */
- // second level wrra priority is only changed if the granted request weight is consumed
- wire pr_en;
-
- onehot_mux_1D #(
- .W(1),
- .N(ARBITER_WIDTH)
- )
- multiplexer
- (
- .in(weight_consumed),
- .out(pr_en),
- .sel(grant)
-
- );
-
-
- arbiter_priority_en #(
- .ARBITER_WIDTH (ARBITER_WIDTH)
- )
- arb
- (
- .clk (clk),
- .reset (reset),
- .request (request),
- .grant (grant),
- .any_grant (any_grant ),
- .priority_en (pr_en)
- );
-
-
- /* verilator lint_off WIDTH */
- end else if(ARBITER_TYPE == "WRRA_CLASSIC") begin : wrra_classic
- /* verilator lint_on WIDTH */
- // use classic WRRA. only for compasrion with propsoed wrra
-
- wire [ARBITER_WIDTH-1 : 0] masked_req= request & ~weight_consumed;
- wire sel = |masked_req;
- wire [ARBITER_WIDTH-1 : 0] mux_req = (sel==1'b1)? masked_req : request;
-
- arbiter #(
- .ARBITER_WIDTH (ARBITER_WIDTH )
- )
- arb
- (
- .clk (clk),
- .reset (reset),
- .request (mux_req),
- .grant (grant),
- .any_grant (any_grant )
- );
-
-
-
- end else begin : rra_m
-
- arbiter #(
- .ARBITER_WIDTH (ARBITER_WIDTH )
- )
- arb
- (
- .clk (clk),
- .reset (reset),
- .request (request),
- .grant (grant),
- .any_grant (any_grant )
- );
-
- end
- endgenerate
-endmodule
-
mpsoc/rtl/src_noc/comb_nonspec.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: mpsoc/rtl/src_noc/inout_ports.sv
===================================================================
--- mpsoc/rtl/src_noc/inout_ports.sv (revision 54)
+++ mpsoc/rtl/src_noc/inout_ports.sv (revision 55)
@@ -316,6 +316,7 @@
the_ssa
(
.ivc_info(ivc_info),
+ .ovc_info(ovc_info),
.flit_in_wr_all(flit_in_wr_all),
.flit_in_all(flit_in_all),
.any_ivc_sw_request_granted_all(any_ivc_sw_request_granted_all),
Index: mpsoc/rtl/src_noc/output_ports.sv
===================================================================
--- mpsoc/rtl/src_noc/output_ports.sv (revision 54)
+++ mpsoc/rtl/src_noc/output_ports.sv (revision 55)
@@ -112,6 +112,8 @@
input smart_ctrl_t smart_ctrl_in [P-1: 0];
input [CRDTw-1 : 0 ] credit_init_val_in [P-1 : 0][V-1 : 0];
+ wire [PVV-1 : 0] ssa_granted_ovc_num_all;
+
logic [PV-1 : 0] ovc_status;
logic [PV-1 : 0] ovc_status_next;
wire [PV-1 : 0] assigned_ovc_is_full_all;
@@ -196,7 +198,7 @@
wire [PV-1 : 0] non_smart_ovc_allocated_all;
generate
for(i=0;i
/mpsoc/rtl/src_noc/pronoc_pkg.sv
62,7 → 62,7
/* verilator lint_off WIDTH */ |
localparam |
DISTw = (TOPOLOGY=="FATTREE" || TOPOLOGY=="TREE" ) ? log2(2*L+1): log2(NR+1), |
OVC_ALLOC_MODE= (B<=4 && SSA_EN=="NO")? 1'b1 : 1'b0; |
OVC_ALLOC_MODE= ((V==1 || B<=4) )? 1'b1 : 1'b0; |
/* verilator lint_on WIDTH */ |
|
// 0: The new ovc is allocated only if its not nearly full. Results in a simpler sw_mask_gen logic |
/mpsoc/rtl/src_noc/router_two_stage.sv
551,6 → 551,55
*/ |
|
|
//TRACE_DUMP_PER is defined in pronoc_def file |
|
|
`ifdef TRACE_DUMP_PER_NoC |
pronoc_trace_dump #( |
.P(P), |
.TRACE_DUMP_PER("NOC"), //NOC, ROUTER, PORT |
.CYCLE_REPORT(0) // 1 : enable, 0 : disable |
|
)dump1 |
( |
.current_r_id(current_r_id), |
.chan_in(chan_in), |
.chan_out(chan_out), |
.clk(clk) |
); |
`endif |
`ifdef TRACE_DUMP_PER_ROUTER |
pronoc_trace_dump #( |
.P(P), |
.TRACE_DUMP_PER("ROUTER"), //NOC, ROUTER, PORT |
.CYCLE_REPORT(0) // 1 : enable, 0 : disable |
|
)dump2 |
( |
.current_r_id(current_r_id), |
.chan_in(chan_in), |
.chan_out(chan_out), |
.clk(clk) |
); |
`endif |
`ifdef TRACE_DUMP_PER_PORT |
pronoc_trace_dump #( |
.P(P), |
.TRACE_DUMP_PER("PORT"), //NOC, ROUTER, PORT |
.CYCLE_REPORT(0) // 1 : enable, 0 : disable |
|
)dump3 |
( |
.current_r_id(current_r_id), |
.chan_in(chan_in), |
.chan_out(chan_out), |
.clk(clk) |
); |
`endif |
|
|
|
|
//synopsys translate_on |
//synthesis translate_on |
|
559,6 → 608,8
|
|
|
|
|
module credit_release_gen |
import pronoc_pkg::*; |
#( |
600,3 → 651,108
|
endmodule |
|
|
|
|
//synthesis translate_off |
module pronoc_trace_dump |
import pronoc_pkg::*; |
#( |
parameter P = 6, |
parameter TRACE_DUMP_PER= "ROUTER", //NOC, ROUTER, PORT |
parameter CYCLE_REPORT=0 // 1 : enable, 0 : disable |
|
)( |
current_r_id, |
chan_in, |
chan_out, |
clk |
); |
|
input [31:0] current_r_id; |
input flit_chanel_t chan_in [P-1 : 0]; |
input flit_chanel_t chan_out [P-1 : 0]; |
input clk; |
|
pronoc_trace_dump_sub #( |
.P(P), |
.TRACE_DUMP_PER(TRACE_DUMP_PER), //NOC, ROUTER, PORT |
.DIRECTION("in"), // in,out |
.CYCLE_REPORT(CYCLE_REPORT) // 1 : enable, 0 : disable |
|
)dump_in |
( |
.current_r_id(current_r_id), |
.chan_in(chan_in), |
.clk(clk) |
); |
|
pronoc_trace_dump_sub #( |
.P(P), |
.TRACE_DUMP_PER(TRACE_DUMP_PER), //NOC, ROUTER, PORT |
.DIRECTION("out"), // in,out |
.CYCLE_REPORT(CYCLE_REPORT) // 1 : enable, 0 : disable |
|
)dump_out |
( |
.current_r_id(current_r_id), |
.chan_in(chan_out), |
.clk(clk) |
); |
endmodule |
|
module pronoc_trace_dump_sub |
import pronoc_pkg::*; |
#( |
parameter P = 6, |
parameter TRACE_DUMP_PER= "ROUTER", //NOC, ROUTER, PORT |
parameter DIRECTION="in", // in,out |
parameter CYCLE_REPORT=0 // 1 : enable, 0 : disable |
|
)( |
current_r_id, |
chan_in, |
clk |
); |
|
input [31:0] current_r_id; |
input flit_chanel_t chan_in [P-1 : 0]; |
input clk; |
|
integer out; |
string fname [P-1 : 0]; |
|
genvar p; |
generate |
for (p=0;p<P;p++)begin |
initial begin |
/* verilator lint_off WIDTH */ |
if(TRACE_DUMP_PER == "PORT" ) fname[p] = $sformatf("trace_dump_R%0d_P%0d.out",current_r_id,p); |
if(TRACE_DUMP_PER == "ROUTER") fname[p] = $sformatf("trace_dump_R%0d.out",current_r_id); |
if(TRACE_DUMP_PER == "NOC" ) fname[p] = $sformatf("trace_dump.out",current_r_id,p); |
/* verilator lint_on WIDTH */ |
out = $fopen(fname[p],"w"); |
$fclose(out); |
end |
|
|
always @(posedge clk) begin |
if(chan_in[p].flit_wr) begin |
out = $fopen(fname[p],"a"); |
if(CYCLE_REPORT) $fwrite(out,"%t:",$time); |
$fwrite(out, "Flit %s: Port %0d, Payload: %h\n",DIRECTION, p, chan_in[p].flit); |
$fclose(out); |
end |
if(chan_in[p].credit>0) begin |
out = $fopen(fname[p],"a"); |
if(CYCLE_REPORT) $fwrite(out,"%t:",$time); |
$fwrite(out, "credit %s:%h Port %0d\n",DIRECTION, chan_in[p].credit,p); |
$fclose(out); |
end |
end |
|
end |
endgenerate |
endmodule |
//synthesis translate_on |
|
/mpsoc/rtl/src_noc/ss_allocator.sv
52,6 → 52,7
// assigned_ovc_num_all, |
// ovc_is_assigned_all, |
ivc_info, |
ovc_info, |
ssa_ctrl_o |
); |
|
88,6 → 89,7
|
input reset,clk; |
input ivc_info_t ivc_info [P-1 : 0][V-1 : 0]; |
input ovc_info_t ovc_info [P-1 : 0][V-1 : 0]; |
output ssa_ctrl_t ssa_ctrl_o [P-1 : 0]; |
|
|
114,6 → 116,7
wire [PVDSTPw-1 : 0] dest_port_encoded_all; |
wire [PVV-1 : 0] assigned_ovc_num_all; |
wire [PV-1 : 0] ovc_is_assigned_all; |
wire [MAX_P-1 : 0] destport_one_hot [PV-1 : 0]; |
|
genvar i; |
// there is no ssa for local port in 5 and 3 port routers |
124,11 → 127,14
localparam SS_PORT = strieght_port (P,C_PORT); |
|
assign ivc_request_all[i] = ivc_info[C_PORT][i%V].ivc_req; |
assign assigned_ovc_not_full_all[i] = ivc_info[C_PORT][i%V].assigned_ovc_not_full; |
assign assigned_ovc_not_full_all[i] = ~ovc_info[SS_PORT][i%V].full; |
//assign assigned_ovc_not_full_all[i] = ivc_info[C_PORT][i%V].assigned_ovc_not_full; |
|
assign dest_port_encoded_all [(i+1)*DSTPw-1 : i*DSTPw] = ivc_info[C_PORT][i%V].dest_port_encoded; |
assign assigned_ovc_num_all[(i+1)*V-1 : i*V] = ivc_info[C_PORT][i%V].assigned_ovc_num; |
assign ovc_is_assigned_all[i] = ivc_info[C_PORT][i%V].ovc_is_assigned; |
|
assign destport_one_hot[i] = ivc_info[C_PORT][i%V].destport_one_hot; |
|
|
if (SS_PORT == DISABLED)begin : no_prefrable |
184,6 → 190,7
.ivc_num_getting_ovc_grant(ivc_num_getting_ovc_grant_all[i]), |
.ivc_reset(ivc_reset_all[i]), |
.single_flit_pck(single_flit_pck_all[i]), |
.destport_one_hot(destport_one_hot[i]), |
.decreased_credit_in_ss_ovc(decreased_credit_in_ss_ovc[i]) |
//synthesis translate_off |
//synopsys translate_off |
265,6 → 272,7
ovc_allocated, |
decreased_credit_in_ss_ovc, |
single_flit_pck, |
destport_one_hot, |
ivc_reset |
//synthesis translate_off |
//synopsys translate_off |
296,6 → 304,7
input [DSTPw-1 : 0] destport_encoded;//exsited packet destination port |
input assigned_to_ssovc; |
input ovc_is_assigned; |
input [MAX_P-1 : 0] destport_one_hot; |
|
output reg [V-1 : 0] granted_ovc_num; |
output ivc_num_getting_sw_grant; |
339,6 → 348,7
|
|
wire condition_1_2_valid; |
wire [DAw-1 : 0] dest_e_addr_in; |
|
extract_header_flit_info #( |
.DATA_w(0) |
350,7 → 360,7
.class_o(), |
.destport_o(destport_in_encoded), |
.src_e_addr_o( ), |
.dest_e_addr_o( ), |
.dest_e_addr_o(dest_e_addr_in ), |
.vc_num_o(vc_num_in), |
.hdr_flit_wr_o( ), |
.hdr_flg_o(hdr_flg), |
369,13 → 379,9
//check destination port is ss |
wire ss_port_hdr_flit, ss_port_nonhdr_flit; |
|
ssa_check_destport #( |
.TOPOLOGY(TOPOLOGY), |
.ROUTE_TYPE(ROUTE_TYPE), |
ssa_check_destport #( |
.SW_LOC(SW_LOC), |
.P(P), |
.DEBUG_EN(DEBUG_EN), |
.DSTPw(DSTPw), |
.P(P), |
.SS_PORT(SS_PORT) |
) |
check_destport |
382,7 → 388,10
( |
.destport_encoded(destport_encoded), |
.destport_in_encoded(destport_in_encoded), |
.destport_one_hot(destport_one_hot), |
.ss_port_hdr_flit(ss_port_hdr_flit), |
.dest_e_addr_in(dest_e_addr_in), |
|
.ss_port_nonhdr_flit(ss_port_nonhdr_flit) |
//synthesis translate_off |
//synopsys translate_off |
446,19 → 455,20
|
|
|
module ssa_check_destport #( |
parameter TOPOLOGY = "MESH", |
parameter ROUTE_TYPE="DETERMINISTIC", |
module ssa_check_destport |
import pronoc_pkg::*; |
#( |
parameter SW_LOC = 0, |
parameter P=5, |
parameter DEBUG_EN = 0, |
parameter DSTPw = P-1, |
parameter P=5, |
parameter SS_PORT=0 |
)( |
destport_encoded, //non header flit dest port |
destport_in_encoded, // header flit packet dest port |
ss_port_hdr_flit, // asserted if the header incomming flit goes to ss port |
ss_port_nonhdr_flit // assert if the body or tail incomming flit goes to ss port |
ss_port_nonhdr_flit, // assert if the body or tail incomming flit goes to ss port |
dest_e_addr_in, |
destport_one_hot |
|
//synthesis translate_off |
//synopsys translate_off |
,clk, |
475,6 → 485,8
//synthesis translate_on |
|
input [DSTPw-1 : 0] destport_encoded, destport_in_encoded; |
input [MAX_P-1 : 0] destport_one_hot; // buffered flit destination port |
input [DAw-1 : 0] dest_e_addr_in; |
output ss_port_hdr_flit, ss_port_nonhdr_flit; |
|
generate |
494,7 → 506,7
.ss_port_nonhdr_flit(ss_port_nonhdr_flit) |
); |
/* verilator lint_off WIDTH */ |
end else if (TOPOLOGY == "MESH" || TOPOLOGY == "TORUS" || TOPOLOGY == "FMESH") begin : mesh |
end else if (TOPOLOGY == "MESH" || TOPOLOGY == "TORUS" ) begin : mesh |
/* verilator lint_on WIDTH */ |
|
mesh_torus_ssa_check_destport #( |
520,6 → 532,61
//synthesis translate_on |
|
); |
/* verilator lint_off WIDTH */ |
end else if (TOPOLOGY == "FMESH") begin :fmesh |
/* verilator lint_on WIDTH */ |
localparam |
ELw = log2(T3), |
Pw = log2(P), |
PLw = (TOPOLOGY == "FMESH") ? Pw : ELw; |
|
wire [Pw-1 : 0] endp_p_in; |
wire [MAX_P-1 : 0] destport_one_hot_in; |
|
fmesh_endp_addr_decode #( |
.T1(T1), |
.T2(T2), |
.T3(T3), |
.EAw(EAw) |
) |
endp_addr_decode |
( |
.e_addr(dest_e_addr_in), |
.ex(), |
.ey(), |
.ep(endp_p_in), |
.valid() |
); |
|
destp_generator #( |
.TOPOLOGY(TOPOLOGY), |
.ROUTE_NAME(ROUTE_NAME), |
.ROUTE_TYPE(ROUTE_TYPE), |
.T1(T1), |
.NL(T3), |
.P(P), |
.DSTPw(DSTPw), |
.PLw(PLw), |
.PPSw(PPSw), |
.SELF_LOOP_EN (SELF_LOOP_EN), |
.SW_LOC(SW_LOC), |
.CAST_TYPE(CAST_TYPE) |
) |
decoder |
( |
.destport_one_hot (destport_one_hot_in), |
.dest_port_encoded(destport_in_encoded), |
.dest_port_out( ), |
.endp_localp_num(endp_p_in), |
.swap_port_presel(1'b0), |
.port_pre_sel({PPSw{1'b0}}), |
.odd_column(1'b0) |
); |
|
|
assign ss_port_nonhdr_flit = destport_one_hot [SS_PORT]; |
assign ss_port_hdr_flit = destport_one_hot_in [SS_PORT]; |
|
end else begin : line |
line_ring_ssa_check_destport #( |
.ROUTE_TYPE(ROUTE_TYPE), |
/mpsoc/script/server/kc07/run.sh
5,8 → 5,9
|
source "my_password.sh" |
|
remote_folder="kc07_mesh6" |
source_path="$PRONOC_WORK/MPSOC/kc07_mesh6" |
remote_folder="mor1k_test" |
#source_path="$PRONOC_WORK/MPSOC/kc07_mesh6" |
source_path="$PRONOC_WORK/SOC/mor1k_test" |
ProNoC_HOME="../../.." |
|
echo "$PRONOC_WORK" |
22,10 → 23,7
|
my_array=("$source_path/src_verilog " |
"$source_path/sw " |
"$source_path/xilinx_compile " |
"$source_path/xilinx_mem " |
"$source_path/*.tcl " |
"$source_path/*.xdc ") |
"$source_path/Vivado") |
|
|
|
mpsoc/src_c/bin2mem/bin2mem
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: mpsoc/src_c/bin2mif/bin2mif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: mpsoc/src_c/bin2mif/bin2mif
===================================================================
--- mpsoc/src_c/bin2mif/bin2mif (revision 54)
+++ mpsoc/src_c/bin2mif/bin2mif (nonexistent)
mpsoc/src_c/bin2mif/bin2mif
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: mpsoc/src_c/bin2str/bin2str
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: mpsoc/src_c/bin2str/bin2str
===================================================================
--- mpsoc/src_c/bin2str/bin2str (revision 54)
+++ mpsoc/src_c/bin2str/bin2str (nonexistent)
mpsoc/src_c/bin2str/bin2str
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: mpsoc/src_c/plot/plot
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: mpsoc/src_c/plot/plot
===================================================================
--- mpsoc/src_c/plot/plot (revision 54)
+++ mpsoc/src_c/plot/plot (nonexistent)
mpsoc/src_c/plot/plot
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
