OpenCores
URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

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    /an-fpga-implementation-of-low-latency-noc-based-mpsoc
    from Rev 32 to Rev 33
    ↔ Reverse comparison
  •

Rev 32 → Rev 33

/trunk/mpsoc/perl_gui/lib/emulate/tran1.EML
0,0 → 1,600
#######################################################################
## File: tran1.EML
##
## Copyright (C) 2014-2016 Alireza Monemi
##
## This file is part of ProNoC 1.5.1
##
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
## MAY CAUSE UNEXPECTED BEHAIVOR.
################################################################################
 
$tran1 = bless( {
'graph_save' => {
'name' => '/home/alireza/mywork/mpsoc_doc/ProNoC/result/tran1.png',
'extension' => 'png',
'save' => 0
},
'fpga_param' => {
'SAVE_NAME' => 'emulate1',
'FPGA_BOARD' => undef,
'SOF_DIR' => '/home/alireza/mywork/mpsoc_work/emulate'
},
'sample1' => {
'noc_info' => {
'ROUTE_NAME' => '"XY"',
'SSA_EN' => '"YES"',
'DEBUG_EN' => '0',
'B' => 4,
'MUX_TYPE' => '"BINARY"',
'C' => 0,
'NX' => 8,
'TOPOLOGY' => '"MESH"',
'Fpay' => '32',
'ROUTE_SUBFUNC' => '"XY"',
'V' => 2,
'NY' => 8,
'AVC_ATOMIC_EN' => 0,
'COMBINATION_TYPE' => '"COMB_NONSPEC"',
'VC_REALLOCATION_TYPE' => '"NONATOMIC"',
'FIRST_ARBITER_EXT_P_EN' => 0,
'ADD_PIPREG_AFTER_CROSSBAR' => '1\'b0'
},
'status' => 'done',
'PCK_SIZE' => 4,
'sof_file' => '/home/alireza/mywork/mpsoc_work/emulate/sof/DE4_230/xy_ssa.sof',
'color' => 15,
'result' => {
'4' => '15.3',
'2' => '15.3',
'18' => '80.5',
'8' => '17.2',
'20' => '77.0',
'10' => '15.8',
'14' => '18.7',
'16' => '28.1',
'12' => '16.8',
'6' => '16.0'
},
'line_name' => 'xy_ssa',
'SIM_CLOCK_LIMIT' => 100000000,
'PCK_NUM_LIMIT' => 500000,
'ratios' => '2:20:2',
'traffic' => 'transposed 1'
},
'setting' => {
'soc_path' => 'lib/soc',
'show_tile_setting' => 0,
'show_adv_setting' => 0,
'show_noc_setting' => 1
},
'noc_type' => {
'ROUTER_TYPE' => '"VC_BASED"'
},
'parameters_order' => {
'noc_param' => [
'NX',
'NY',
'V',
'B',
'Fpay',
'TOPOLOGY',
'ROUTE_NAME',
'SSA_EN',
'VC_REALLOCATION_TYPE',
'COMBINATION_TYPE',
'MUX_TYPE',
'C',
'DEBUG_EN',
'ADD_PIPREG_AFTER_CROSSBAR',
'FIRST_ARBITER_EXT_P_EN',
'AVC_ATOMIC_EN',
'ROUTE_SUBFUNC'
],
'sample4' => [
'line_name',
'traffic',
'PCK_SIZE',
'PCK_NUM_LIMIT',
'SIM_CLOCK_LIMIT'
],
'sample2' => [
'line_name',
'traffic',
'PCK_SIZE',
'PCK_NUM_LIMIT',
'SIM_CLOCK_LIMIT'
],
'noc_type' => [
'ROUTER_TYPE'
],
'graph_param' => [
'G_Title',
'Y_Title',
'X_Title',
'legend_placement',
'Y_MIN',
'X_MIN',
'LINEw',
'G_Title',
'G_Title',
'G_Title'
],
'sample5' => [
'line_name',
'traffic',
'PCK_SIZE',
'PCK_NUM_LIMIT',
'SIM_CLOCK_LIMIT'
],
'sample1' => [
'line_name',
'traffic',
'PCK_SIZE',
'PCK_NUM_LIMIT',
'SIM_CLOCK_LIMIT'
],
'fpga_param' => [
'FPGA_BOARD',
'SAVE_NAME',
'SOF_DIR',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD',
'FPGA_BOARD'
],
'sample3' => [
'line_name',
'traffic',
'PCK_SIZE',
'PCK_NUM_LIMIT',
'SIM_CLOCK_LIMIT'
]
},
'file_name' => undef,
'gui_status' => {
'status' => 'ideal',
'timeout' => 0
},
'graph_param' => {
'X_MIN' => 2,
'Y_Title' => 'Latency (clock)',
'X_Title' => 'Load per router (flits/clock (%))',
'G_Title' => undef,
'legend_placement' => 'BL',
'LINEw' => 3,
'Y_MIN' => 0
},
'sample5' => {
'traffic' => 'transposed 1',
'ratios' => '2:33:2',
'PCK_NUM_LIMIT' => 500000,
'SIM_CLOCK_LIMIT' => 100000000,
'line_name' => 'no_vc',
'result' => {
'14' => '171.4',
'20' => '260.2',
'2' => '19.5',
'4' => '19.5',
'18' => '229.7',
'8' => '22.1',
'6' => '20.2',
'12' => '108.8',
'30' => '307.1',
'28' => '310.6',
'22' => '321.3',
'10' => '34.5',
'32' => '438.4',
'26' => '316.8',
'16' => '167.5',
'24' => '319.8'
},
'color' => 24,
'status' => 'done',
'sof_file' => '/home/alireza/mywork/mpsoc_work/emulate/sof/DE4_230/no_vc.sof',
'PCK_SIZE' => 4,
'noc_info' => {
'NY' => 8,
'AVC_ATOMIC_EN' => 0,
'V' => 1,
'TOPOLOGY' => '"MESH"',
'ROUTE_SUBFUNC' => '"XY"',
'Fpay' => '32',
'VC_REALLOCATION_TYPE' => '"NONATOMIC"',
'FIRST_ARBITER_EXT_P_EN' => 0,
'COMBINATION_TYPE' => '"COMB_NONSPEC"',
'ADD_PIPREG_AFTER_CROSSBAR' => '1\'b0',
'ROUTE_NAME' => '"XY"',
'SSA_EN' => '"NO"',
'NX' => 8,
'C' => 0,
'MUX_TYPE' => '"BINARY"',
'B' => 4,
'DEBUG_EN' => '0'
}
},
'process_notebook' => {
'currentpage' => 0
},
'sample3' => {
'ratios' => '2:25:2',
'traffic' => 'transposed 1',
'SIM_CLOCK_LIMIT' => 100000000,
'PCK_NUM_LIMIT' => 500000,
'line_name' => 'full_ssa',
'color' => 23,
'status' => 'done',
'PCK_SIZE' => 4,
'sof_file' => '/home/alireza/mywork/mpsoc_work/emulate/sof/DE4_230/full_ssa.sof',
'result' => {
'4' => '15.9',
'2' => '15.9',
'8' => '17.9',
'18' => '21.1',
'22' => '29.3',
'20' => '23.7',
'10' => '16.5',
'14' => '19.5',
'24' => '69.2',
'12' => '17.6',
'16' => '19.7',
'6' => '16.9'
},
'noc_info' => {
'TOPOLOGY' => '"MESH"',
'ROUTE_SUBFUNC' => '"XY"',
'Fpay' => '32',
'V' => 2,
'CONGESTION_INDEX' => 3,
'NY' => 8,
'AVC_ATOMIC_EN' => 0,
'ESCAP_VC_MASK' => '2\'b01',
'COMBINATION_TYPE' => '"COMB_NONSPEC"',
'VC_REALLOCATION_TYPE' => '"NONATOMIC"',
'FIRST_ARBITER_EXT_P_EN' => 0,
'ADD_PIPREG_AFTER_CROSSBAR' => '1\'b0',
'ROUTE_NAME' => '"DUATO"',
'SSA_EN' => '"YES"',
'DEBUG_EN' => '0',
'B' => 4,
'C' => 0,
'MUX_TYPE' => '"BINARY"',
'NX' => 8
}
},
'noc_param' => {
'COMBINATION_TYPE' => '"COMB_NONSPEC"',
'FIRST_ARBITER_EXT_P_EN' => 0,
'VC_REALLOCATION_TYPE' => '"NONATOMIC"',
'TOPOLOGY' => '"MESH"',
'Fpay' => '32',
'ROUTE_SUBFUNC' => '"XY"',
'V' => '2',
'NY' => ' 2',
'AVC_ATOMIC_EN' => 0,
'ADD_PIPREG_AFTER_CROSSBAR' => '1\'b0',
'ROUTE_NAME' => '"XY"',
'DEBUG_EN' => '0',
'B' => '4',
'C' => 0,
'MUX_TYPE' => '"BINARY"',
'NX' => ' 2',
'SSA_EN' => '"NO"'
},
'sample4' => {
'ratios' => '2:25:2',
'traffic' => 'transposed 1',
'SIM_CLOCK_LIMIT' => 100000000,
'PCK_NUM_LIMIT' => 500000,
'line_name' => 'full_no_ssa',
'status' => 'done',
'sof_file' => '/home/alireza/mywork/mpsoc_work/emulate/sof/DE4_230/full_no_ssa.sof',
'PCK_SIZE' => 4,
'color' => 27,
'result' => {
'12' => '20.5',
'16' => '21.9',
'6' => '19.3',
'24' => '84.2',
'20' => '24.9',
'10' => '19.4',
'22' => '32.0',
'14' => '21.9',
'8' => '19.9',
'18' => '22.5',
'4' => '18.9',
'2' => '19.0'
},
'noc_info' => {
'ROUTE_NAME' => '"DUATO"',
'C' => 0,
'MUX_TYPE' => '"BINARY"',
'NX' => 8,
'DEBUG_EN' => '0',
'B' => 4,
'SSA_EN' => '"NO"',
'VC_REALLOCATION_TYPE' => '"NONATOMIC"',
'FIRST_ARBITER_EXT_P_EN' => 0,
'ESCAP_VC_MASK' => '2\'b01',
'COMBINATION_TYPE' => '"COMB_NONSPEC"',
'CONGESTION_INDEX' => 3,
'AVC_ATOMIC_EN' => 0,
'NY' => 8,
'Fpay' => '32',
'TOPOLOGY' => '"MESH"',
'ROUTE_SUBFUNC' => '"XY"',
'V' => 2,
'ADD_PIPREG_AFTER_CROSSBAR' => '1\'b0'
}
},
'status' => 'ideal',
'emulate_name' => 'tran1',
'sample2' => {
'line_name' => 'xy_no_ssa',
'PCK_NUM_LIMIT' => 500000,
'SIM_CLOCK_LIMIT' => 100000000,
'traffic' => 'transposed 1',
'ratios' => '2:18:2',
'noc_info' => {
'MUX_TYPE' => '"BINARY"',
'C' => 0,
'NX' => 8,
'DEBUG_EN' => '0',
'B' => 4,
'SSA_EN' => '"NO"',
'ROUTE_NAME' => '"XY"',
'ADD_PIPREG_AFTER_CROSSBAR' => '1\'b0',
'VC_REALLOCATION_TYPE' => '"NONATOMIC"',
'FIRST_ARBITER_EXT_P_EN' => 0,
'COMBINATION_TYPE' => '"COMB_NONSPEC"',
'NY' => 8,
'AVC_ATOMIC_EN' => 0,
'Fpay' => '32',
'ROUTE_SUBFUNC' => '"XY"',
'TOPOLOGY' => '"MESH"',
'V' => 2
},
'result' => {
'2' => '18.9',
'4' => '18.9',
'8' => '20.1',
'18' => '82.1',
'14' => '21.6',
'10' => '19.1',
'6' => '19.2',
'12' => '19.8',
'16' => '30.5'
},
'color' => 10,
'status' => 'done',
'sof_file' => '/home/alireza/mywork/mpsoc_work/emulate/sof/DE4_230/xy_no_ssa.sof',
'PCK_SIZE' => 4
},
'graph_scale' => '4',
'emulate_num' => 5
}, 'emulator' );
/trunk/mpsoc/perl_gui/lib/simulate/example1.SIM
0,0 → 1,195
#######################################################################
## File: example1.SIM
##
## Copyright (C) 2014-2016 Alireza Monemi
##
## This file is part of ProNoC 1.5.1
##
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
## MAY CAUSE UNEXPECTED BEHAIVOR.
################################################################################
 
$example1 = bless( {
'sample2' => {
'result' => {
'12' => ' 20.676769',
'24' => ' 108.607381',
'6' => ' 19.712610',
'14' => ' 22.158923',
'2' => ' 19.481100',
'20' => ' 27.025779',
'4' => ' 19.490490',
'10' => ' 20.444416',
'18' => ' 23.458541',
'16' => ' 22.327683',
'22' => ' 54.241596',
'8' => ' 21.067223'
},
'traffic' => 'transposed 2',
'PCK_NUM_LIMIT' => 200000,
'PCK_SIZE' => 4,
'color' => 23,
'noc_info' => {
'ESCAP_VC_MASK' => '2\'b01',
'ROUTE_NAME' => '"DUATO"',
'ROUTE_SUBFUNC' => '"XY"',
'V' => '2',
'Fpay' => '32',
'COMBINATION_TYPE' => '"COMB_NONSPEC"',
'CONGESTION_INDEX' => 3,
'NX' => 8,
'FIRST_ARBITER_EXT_P_EN' => 0,
'NY' => 8,
'C' => 0,
'DEBUG_EN' => '0',
'SSA_EN' => '"NO"',
'MUX_TYPE' => '"BINARY"',
'B' => '4',
'VC_REALLOCATION_TYPE' => '"NONATOMIC"',
'TOPOLOGY' => '"MESH"',
'ADD_PIPREG_AFTER_CROSSBAR' => '1\'b0',
'AVC_ATOMIC_EN' => 0
},
'ratios' => '2:26:2',
'status' => 'run',
'line_name' => 'full',
'sof_file' => '/home/alireza/mywork/mpsoc_work/simulate/mesh_8x8_full',
'SIM_CLOCK_LIMIT' => 100000
},
'setting' => {
'show_noc_setting' => 1,
'show_adv_setting' => 0,
'soc_path' => 'lib/soc',
'show_tile_setting' => 0
},
'graph_save' => {},
'status' => 'run',
'graph_scale' => 5,
'sample1' => {
'ratios' => '14:18:2',
'noc_info' => {
'CONGESTION_INDEX' => 3,
'NX' => 8,
'DEBUG_EN' => '0',
'SSA_EN' => '"NO"',
'C' => 0,
'FIRST_ARBITER_EXT_P_EN' => 0,
'NY' => 8,
'ROUTE_NAME' => '"XY"',
'ESCAP_VC_MASK' => '2\'b01',
'Fpay' => '32',
'COMBINATION_TYPE' => '"COMB_NONSPEC"',
'ROUTE_SUBFUNC' => '"XY"',
'V' => '2',
'TOPOLOGY' => '"MESH"',
'AVC_ATOMIC_EN' => 0,
'ADD_PIPREG_AFTER_CROSSBAR' => '1\'b0',
'MUX_TYPE' => '"BINARY"',
'B' => '4',
'VC_REALLOCATION_TYPE' => '"NONATOMIC"'
},
'PCK_NUM_LIMIT' => 200000,
'color' => 11,
'PCK_SIZE' => 4,
'traffic' => 'transposed 2',
'result' => {
'2' => ' 19.427565',
'14' => ' 22.569334',
'6' => ' 19.702457',
'12' => ' 20.088549',
'8' => ' 21.298512',
'16' => ' 56.009655',
'18' => ' 98.052215',
'10' => ' 19.695515',
'4' => ' 19.428024'
},
'sof_file' => '/home/alireza/mywork/mpsoc_work/simulate/mesh_8x8_xy',
'line_name' => 'xy',
'SIM_CLOCK_LIMIT' => 100000,
'status' => 'done'
},
'gui_status' => {
'status' => 'ideal',
'timeout' => 0
},
'emulate_num' => 2,
'graph_param' => {},
'file_name' => undef,
'simulate_name' => 'example1',
'process_notebook' => {
'currentpage' => 0
},
'noc_param' => {
'FIRST_ARBITER_EXT_P_EN' => 0,
'NY' => 8,
'C' => 0,
'SSA_EN' => '"NO"',
'DEBUG_EN' => '0',
'CONGESTION_INDEX' => 3,
'NX' => 8,
'ROUTE_SUBFUNC' => '"XY"',
'V' => '2',
'Fpay' => '32',
'COMBINATION_TYPE' => '"COMB_NONSPEC"',
'ESCAP_VC_MASK' => '2\'b01',
'ROUTE_NAME' => '"DUATO"',
'ADD_PIPREG_AFTER_CROSSBAR' => '1\'b0',
'AVC_ATOMIC_EN' => 0,
'TOPOLOGY' => '"MESH"',
'VC_REALLOCATION_TYPE' => '"NONATOMIC"',
'B' => '4',
'MUX_TYPE' => '"BINARY"'
},
'parameters_order' => {
'noc_type' => [
'ROUTER_TYPE'
],
'sample1' => [
'line_name',
'traffic',
'PCK_SIZE',
'PCK_NUM_LIMIT',
'SIM_CLOCK_LIMIT'
],
'noc_param' => [
'NX',
'NY',
'V',
'B',
'Fpay',
'TOPOLOGY',
'ROUTE_NAME',
'SSA_EN',
'CONGESTION_INDEX',
'ESCAP_VC_MASK',
'VC_REALLOCATION_TYPE',
'COMBINATION_TYPE',
'MUX_TYPE',
'C',
'DEBUG_EN',
'ADD_PIPREG_AFTER_CROSSBAR',
'FIRST_ARBITER_EXT_P_EN',
'AVC_ATOMIC_EN',
'ROUTE_SUBFUNC'
],
'sample2' => [
'line_name',
'traffic',
'PCK_SIZE',
'PCK_NUM_LIMIT',
'SIM_CLOCK_LIMIT'
],
'sim_param' => [
'SAVE_NAME',
'BIN_DIR'
]
},
'sim_param' => {
'SAVE_NAME' => 'mesh_8x8_full',
'BIN_DIR' => '/home/alireza/mywork/mpsoc_work/simulate'
},
'active_setting' => undef,
'noc_type' => {
'ROUTER_TYPE' => '"VC_BASED"'
}
}, 'emulator' );

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