URL https://opencores.org/ocsvn/ao68000/ao68000/trunk

Subversion Repositories ao68000

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/ao68000
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from Rev 1 to Rev 2
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Compare Path: Rev

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Rev 1 → Rev 2

/trunk/bench/sw_emulators/winuae/table68k

0,0 → 1,279

/trunk/bench/sw_emulators/winuae/ao.c

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/trunk/bench/sw_emulators/winuae/gencpu.c

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/trunk/bench/sw_emulators/winuae/readcpu.c

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/trunk/bench/sw_emulators/winuae/ao.h

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/trunk/bench/sw_emulators/winuae/readcpu.h

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/trunk/bench/sw_emulators/winuae/build68k.c

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/trunk/bench/sw_emulators/winuae/Makefile

0,0 → 1,29

/trunk/bench/verilog/tb_ao68000/tb_ao68000.v

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/trunk/bench/verilog/tb_ao68000/Makefile

0,0 → 1,20

/trunk/rtl/verilog/full_system/serial_txd.v

0,0 → 1,81

/trunk/rtl/verilog/full_system/early_boot.v

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/trunk/rtl/verilog/full_system/timer.v

0,0 → 1,63

/trunk/rtl/verilog/full_system/ssram.v

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/trunk/rtl/verilog/full_system/full_system.v

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/trunk/rtl/verilog/full_system/sd.v

0,0 → 1,1018

/trunk/rtl/verilog/ao68000/ao68000.v

0,0 → 1,3002

/trunk/rtl/verilog/ao68000/microcode/microcode_locations.v

0,0 → 1,115

/trunk/rtl/verilog/ao68000/microcode/readme.txt

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/trunk/rtl/verilog/ao68000/microcode/microcode.mif

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/trunk/rtl/verilog/ao68000/microcode_params.v

0,0 → 1,273

/trunk/rtl/verilog/ao68000/altera_specific/microcode_rom.v

0,0 → 1,53

/trunk/rtl/verilog/ao68000/altera_specific/register_ram.v

0,0 → 1,59

/trunk/rtl/verilog/ao68000/altera_specific/alu_mult_div.v

0,0 → 1,117

/trunk/doc/doxygen_generated.tar.gz Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

/trunk/doc/doxygen_generated.tar.gz

trunk/doc/doxygen_generated.tar.gz Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/doc/src/specification_template.odt =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/src/specification_template.odt =================================================================== --- trunk/doc/src/specification_template.odt (nonexistent) +++ trunk/doc/src/specification_template.odt (revision 2)

trunk/doc/src/specification_template.odt Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/doc/src/directory.txt =================================================================== --- trunk/doc/src/directory.txt (nonexistent) +++ trunk/doc/src/directory.txt (revision 2) @@ -0,0 +1,48 @@ +- bench ........................................................................ Testbench sources + - sw_simulators ............................................................ Software MC68000 emulators + - winuae ............................................................... WinUAE MC68000 processor emulator + - verilog .................................................................. Verilog language testbenches + - tb_ao68000 ........................................................... ao68000 testbench for comparison with software emulators + +- doc .......................................................................... Project documentation + - doxygen .................................................................. Doxygen auto-generated documentation + - html ................................................................. Doxygen HTML documentation + - img ...................................................................... Documentation images + - out ...................................................................... Output of specification extraction tool + - src ...................................................................... Documentation sources + +- rtl .......................................................................... RTL core sources + - verilog .................................................................. Verilog language RTL sources + - ao68000 .............................................................. ao68000 core sources + - altera_specific .................................................. Altera specific modules + - microcode ........................................................ Microcode with locations + - full_system .......................................................... System-on-Chip example for ao68000 + +- sim .......................................................................... Simulation scripts and binaries + - rtl_sim .................................................................. RTL simulation scripts + - bin .................................................................. Scripts for compiling testbench tb_ao68000 + - run .................................................................. Testbench build directory + - rtl_sw_compare ........................................................... ao68000 RTL comparison with MC68000 software emulators + - bin .................................................................. Scripts to prepare the comparison + - run .................................................................. Comparison run directory + - sw_emulators ............................................................. MC68000 software emulator scripts + - bin .................................................................. Scripts for compiling WinUAE software MC68000 emulator + - run .................................................................. WinUAE build directory + +- sw ........................................................................... Software projects and tools + - ao68000_tool ............................................................. ao68000_tool NetBeans project + - build ................................................................ Compiled classes + - dist ................................................................. Final compiled and assembled JAR + - nbproject ............................................................ NetBeans project directory + - src .................................................................. ao68000_tool sources + - test ................................................................. Tests directory + - linux .................................................................... Linux kernel sources for ao68000 support + - linux-2.6.33.1-ao68000 ............................................... Linux kernel version 2.6.33.1 + - nbcd_abcd_sbcd ........................................................... Binary Coded Decimal test tool + +- syn .......................................................................... Synthesis directory + - altera ................................................................... Altera Quartus II synthesis tool support + - bin .................................................................. Synthesis scripts + - run .................................................................. System-on-Chip full_system project files + - out .................................................................. Synthesis directory + Index: trunk/doc/src/old_notes.txt =================================================================== --- trunk/doc/src/old_notes.txt (nonexistent) +++ trunk/doc/src/old_notes.txt (revision 2) @@ -0,0 +1,1348 @@ +******************************************************************************************************************************************* +NOTE: The information bellow is not current. It is here only for historical reasons. +******************************************************************************************************************************************* + +if( ir[15:12] == 4'b0000 && ir[8] == 1'b0 && ir[11:9] != 3'b100 && ir[11:9] != 3'b110 && + ir[15:0] != 16'b0000_000_0_00_111100 && ir[15:0] != 16'b0000_000_0_01_111100 && + ir[15:0] != 16'b0000_001_0_00_111100 && ir[15:0] != 16'b0000_001_0_01_111100 && + ir[15:0] != 16'b0000_101_0_00_111100 && ir[15:0] != 16'b0000_101_0_01_111100 +) + ANDI,EORI,ORI,ADDI,SUBI ++++ + if( ir[7:6] == 2'b00 ) load ir1[7:0] to operand1[7:0] + else if( ir[7:6] == 2'b01 ) load ir1[15:0] to operand1[15:0] + else if( ir[7:6] == 2'b10 ) load { ir1, ir2 } to operand1[31:0] + + move operand1 to operand2 + + operation size: + if( ir[7:6] == 2'b00 ) byte + else if( ir[7:6] == 2'b01 ) word + else if( ir[7:6] == 2'b10 ) long + + load (ea) from ir[5:0] to operand1: data alter + Dn 000, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001 + + perform ALU operation: + if( ir[11:9] == 3'b000 ) OR + else if( ir[11:9] == 3'b001 ) AND + else if( ir[11:9] == 3'b010 ) SUB + else if( ir[11:9] == 3'b011 ) ADD + else if( ir[11:9] == 3'b101 ) EOR + + update CCR: + ANDI,EORI,ORI: X not affected; C cleared; V cleared; Z set if zero else clear; N set if MSB set else cleared + ADDI,SUBI: same as ADD: X=C set if carry[borrow] generated else cleared; V set if overflow else cleared; Z set if result zero else cleared; + N set if result negative else cleared + + save result to (ea) from ir[5:0] + + update PC + +if( ir[15:0] == 16'b0000_000_0_00_111100 || ir[15:0] == 16'b0000_000_0_01_111100 || + ir[15:0] == 16'b0000_001_0_00_111100 || ir[15:0] == 16'b0000_001_0_01_111100 || + ir[15:0] == 16'b0000_101_0_00_111100 || ir[15:0] == 16'b0000_101_0_01_111100 +) + ORI to CCR,ORI to SR,ANDI to CCR,ANDI to SR,EORI to CCR,EORI to SR ++++ + if( ir[7:6] == 2'b00 ) load ir1[7:0] to operand1[7:0] + else if( ir[7:6] == 2'b01 ) load ir1[15:0] to operand1[15:0] + else if( ir[7:6] == 2'b10 ) load { ir1, ir2 } to operand1[31:0] + + move operand1 to operand2 + + operation size: + if( ir[7:6] == 2'b00 ) byte + else if( ir[7:6] == 2'b01 ) word + else if( ir[7:6] == 2'b10 ) long + + move SR to operand1 + + perform ALU operation: + if( ir[11:9] == 3'b000 ) OR + else if( ir[11:9] == 3'b001 ) AND + else if( ir[11:9] == 3'b101 ) EOR + + move result to operand1 + + save operand1 to CCR/SR + + update CCR: + result + + update PC + +if( ir[15:12] == 4'b0000 && ir[8] == 1'b0 && ir[11:9] = 3'b110 ) + CMPI ++++ + if( ir[7:6] == 2'b00 ) load ir1[7:0] to operand2[7:0] + else if( ir[7:6] == 2'b01 ) load ir1[15:0] to operand2[15:0] + else if( ir[7:6] == 2'b10 ) load { ir1, ir2 } to operand2[31:0] + + operation size: + if( ir[7:6] == 2'b00 ) byte + else if( ir[7:6] == 2'b01 ) word + else if( ir[7:6] == 2'b10 ) long + + load (ea) from ir[5:0] to operand1: data alter + Dn 000, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001 + + perform ALU operation: + if( ir[11:9] == 3'b110 ) CMP=SUB + + update CCR: + CMPI: same as CMP: X not affected; C set if borrow else cleared; V set if overflow else cleared; Z set if zero else cleared; + N set if negative else cleared + + update PC + +if( ir[15:12] == 4'b0000 && ir[11:8] == 4'b1000 && ir[7:6] != 2'b00 ) + BCHG,BCLR,BSET immediate ++++ + load ir1[7:0] to operand1[7:0] + + move operand1 to operand2 + + load (ea) form ir[5:0] to operand1: data alter + data alter: Dn 000, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001 + + operation size: + if( ir[5:3] == 3'b000 ) long + else if( ir[5:3] != 3'b000 ) byte + + perform bit operation: + test( of Destination ) -> Z; test( of Destination )[0][1] -> of Destination + if( ir[7:6] == 2'b01 ) BCHG + else if( ir[7:6] == 2'b10 ) BCLR + else if( ir[7:6] == 2'b11 ) BSET + + update CCR: X,N,V,C not affected; Z set if bit tested is zero else cleared + + save result to (ea) form ir[5:0] + + update PC + +if( ir[15:12] == 4'b0000 && ir[11:8] == 4'b1000 && ir[7:6] == 2'b00 ) + BTST immediate ++++ + load ir1[7:0] to operand1[7:0] + + move operand1 to operand2 + + load (ea) form ir[5:0] to operand1: data address + data address: Dn 000, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001, (d16, PC) 111 010, (d8, PC, Xn) 111 011 + + operation size: + if( ir[5:3] == 3'b000 ) long + else if( ir[5:3] != 3'b000 ) byte + + perform bit operation: + test( of Destination ) -> Z + if( ir[7:6] == 2'b00 ) BTST + + update CCR: X,N,V,C not affected; Z set if bit tested is zero else cleared + + update PC + +if( ir[15:12] == 4'b0000 && ir[8] == 1'b1 && ir[5:3] != 3'b001 && ir[8:6] != 3'b100 ) + BCHG,BCLR,BSET register ++++ + load (ea) from ir[11:9] to operand1[7:0]: Dn + + move operand1 to operand2 + + load (ea) form ir[5:0] to operand1: data alter + data alter: Dn 000, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001 + + operation size: + if( ir[5:3] == 3'b000 ) long + else if( ir[5:3] != 3'b000 ) byte + + perform bit operation: + test( of Destination ) -> Z; test( of Destination )[0][1] -> of Destination + if( ir[7:6] == 2'b01 ) BCHG + else if( ir[7:6] == 2'b10 ) BCLR + else if( ir[7:6] == 2'b11 ) BSET + + update CCR: X,N,V,C not affected; Z set if bit tested is zero else cleared + + save result to (ea) form ir[5:0] + + update PC + +if( ir[15:12] == 4'b0000 && ir[8] == 1'b1 && ir[5:3] != 3'b001 && ir[8:6] == 3'b100 ) + BTST register ++++ + load (ea) from ir[11:9] to operand1[7:0]: Dn + + move operand1 to operand2 + + load (ea) form ir[5:0] to operand1: data address + data address: Dn 000, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001, (d16, PC) 111 010, (d8, PC, Xn) 111 011 + + operation size: + if( ir[5:3] == 3'b000 ) long + else if( ir[5:3] != 3'b000 ) byte + + perform bit operation: + test( of Destination ) -> Z + if( ir[7:6] == 2'b00 ) BTST + + update CCR: X,N,V,C not affected; Z set if bit tested is zero else cleared + + update PC + +if( ir[15:12] == 4'b0000 && ir[8] == 1'b1 && ir[5:3] == 3'b001 && ( ir[7:6] == 2'b00 || ir[7:6] == 2'b01 ) ) + MOVEP memory to register ++++ + operation size: + if( ir[7:6] == 2'b00 ) word + if( ir[7:6] == 2'b01 ) long + + load ea from ir[2:0] to address register: (d16, An) + + do + load from (address) to operand1 register, long + move two alternate bytes to result register + increment ea by 4 + repeat for long + + save result to (ea) from ir[11:9]: Dn, word ( ir[7:6] == 2'b00 ), long ( ir[7:6] == 2'b01 ) + + update CCR: no change + update PC + +if( ir[15:12] == 4'b0000 && ir[8] == 1'b1 && ir[5:3] == 3'b001 && ( ir[7:6] == 2'b10 || ir[7:6] == 2'b11 ) ) + MOVEP register to memory ++++ + operation size: + if( ir[7:6] == 2'b10 ) word + if( ir[7:6] == 2'b11 ) long + + load (ea) from ir[11:9] to operand1: Dn, long + + load ea from ir[2:0] to address register: (d16, An) + + do + move two alternate bytes to result register + save result register to (addreess), long, only selected bytes + increment ea by 4 + repeat for long + + update CCR: no change + update PC + +if( ir[15:14] == 2'b00 && ir[13:12] != 2'b00 && ir[8:6] != 3'b001) + MOVE ++++ + size of operation: ir[13:12]: 01,11,10 byte,word,long + + load (ea) from ir[5:0] to operand1: all modes. + all modes: Dn 000, An (word, long) 001, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001, #data 111 100, (d16, PC) 111 010, (d8, PC, Xn) 111 011 + + copy operand1 to result register + + save result to (ea) from ir[11:6]: data alter. + data alter: Dn 000, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001, + + CC: X not affected; C cleared; V cleared; Z set if zero else cleared; N set if negative else cleared + + update PC + +if( ir[15:14] == 2'b00 && (ir[13:12] == 2'b11 || ir[13:12] == 2'b10) && ir[8:6] == 3'b001) + MOVEA ++++ + size of operation: ir[13:12]: 11,10 word,long + + load (ea) from ir[5:0] to operand1: all modes. + all modes: Dn 000, An (word, long) 001, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001, #data 111 100, (d16, PC) 111 010, (d8, PC, Xn) 111 011 + + copy operand1 to result register + + save result to (ea) from ir[11:6]: An + + CC: not affected + + update PC + +if( ir[15:12] == 4'b1100 && (ir[8:4] == 5'b10100 || 5'b11000) ) + EXG ++++ + load (ea) from ir[5:0] to operand1: Dn, An + + perform ALU operation: move operand1 to result register + + load (ea) from ir[11:9] with mode in ir[7:3] to operand1: Dn (5'b01000 or 5'b10001), An (5'b01001) + + save result to (ea) from ir[11:9] with mode in ir[7:3]: Dn (5'b01000 or 5'b10001), An (5'b01001), + + perform ALU operation: move operand1 to result register + + save result to (ea) from ir[5:0]: Dn, An + + CC: not affected + + update PC + +if( ir[15:12] == 4'b1011 && (ir[8:6] == 3'b100 || 3'b101 || 3'b110) && ir[5:3] == 3'b001 ) + CMPM ++++ + load (ea) from ir[2:0] to operand1: postincrement (An)+ + + move operand1 to operand2 + + load (ea) from ir[11:9] to operand1: postincrement (An)+ + + ALU operation size: + if( ir[7:6] == 2'b00 ) byte + else if( ir[7:6] == 2'b01 ) word + else if( ir[7:6] == 2'b10 ) long + + perform ALU operation: CMPM == SUB + + CC: X not affected; C set if borrow else cleared; V set if overflow else cleared; Z set if zero else cleared; N set if negative else cleared + Ax dest, Ay source: postincrement: +(An) + + update PC + +if( ir[15:12] == 4'b1011 && (ir[8:6] == 3'b100 || 3'b101 || 3'b110) && ir[5:3] != 3'b001 ) + EOR ++++ + load (ea) from ir[11:9] to operand1: Dn + + move operand1 to operand2 + + load (ea) from ir[5:0] to operand1: data alter + data alter: Dn 000, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001, + + ALU operation size: + if( ir[7:6] == 2'b00 ) byte + else if( ir[7:6] == 2'b01 ) word + else if( ir[7:6] == 2'b10 ) long + + perform ALU operation: EOR + + CC: X not affected; C cleared; V cleared; Z set if zero else clear; N set if MSB set else cleared + + save result to (ea) from ir[5:0]: data alter + data alter: Dn 000, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001, + update PC + +if( (ir[15:12] == 4'b1101 || 4'b1001 || 4'b1100 || 4'b1000) && + (ir[8:4] == 5'b10001 || 5'b10010 || 5'b10011 || 5'b10101 || 5'b10110 || 5'b10111 || 5'b11001 || 5'b11010 || 5'b11011) ) + + ADD to mem,SUB to mem,AND to mem,OR to mem ++++ + load (ea) from ir[11:9] to operand1: Dn + + move operand1 to operand2 + + load (ea) indexed by ir[5:0] to operand1: memory alter + memory alter: (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001 + + ALU operation size: + if( ir[7:6] == 2'b00 ) byte + else if( ir[7:6] == 2'b01 ) word + else if( ir[7:6] == 2'b10 ) long + + perform ALU operation: + if( ir[15:12] == 4'b1101 ) ADD + else if( ir[15:12] == 4'b1001 ) SUB + else if( ir[15:12] == 4'b1100 ) AND + else if( ir[15:12] == 4'b1000 ) OR + + if( ADD,SUB ) + CC: X=C set if carry[borrow] generated else cleared; V set if overflow else cleared; Z set if result zero else cleared; + N set if result negative else cleared + else if( AND,OR ) + CC: X not affected; C cleared; V cleared; Z set if zero else clear; N set if MSB set else cleared + + save result to (ea) from ir[5:0]: memory alter + memory alter: (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001 + + update PC + +if( (ir[15:12] == 4'b1101 || 4'b1001 || 4'b1100 || 4'b1000) && (ir[8:6] == 3'b000 || 3'b001 || 3'b010) ) + ADD to Dn,SUB to Dn,AND to Dn,OR to Dn ++++ + load (ea) from ir[5:0] to operand1: all modes + all modes: Dn 000, An (word, long) 001, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001, #data 111 100, (d16, PC) 111 010, (d8, PC, Xn) 111 011 + + move operand1 to operand2 + + load (ea) from ir[11:9] to operand1: Dn + + ALU operation size: + if( ir[7:6] == 2'b00 ) byte + else if( ir[7:6] == 2'b01 ) word + else if( ir[7:6] == 2'b10 ) long + + perform ALU operation: + if( ir[15:12] == 4'b1101 ) ADD + else if( ir[15:12] == 4'b1001 ) SUB + else if( ir[15:12] == 4'b1100 ) AND + else if( ir[15:12] == 4'b1000 ) OR + + if( ADD,SUB ) + CC: X=C set if carry[borrow] generated else cleared; V set if overflow else cleared; Z set if result zero else cleared; + N set if result negative else cleared + else if( AND,OR ) + CC: X not affected; C cleared; V cleared; Z set if zero else clear; N set if MSB set else cleared + + save result to (ea) from ir[11:9]: Dn + + update PC + +if( (ir[15:12] == 4'b1011) && (ir[8:6] == 3'b000 || 3'b001 || 3'b010) ) + CMP ++++ + load (ea) from ir[5:0] to operand1: all modes + all modes: Dn 000, An (word, long) 001, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001, #data 111 100, (d16, PC) 111 010, (d8, PC, Xn) 111 011 + + move operand1 to operand2 + + load (ea) from ir[11:9] to operand1: Dn + + ALU operation size: + if( ir[7:6] == 2'b00 ) byte + else if( ir[7:6] == 2'b01 ) word + else if( ir[7:6] == 2'b10 ) long + + perform ALU operation: + if( ir[15:12] == 4'b1011 ) CMP=SUB + + CC: X not affected; C set if borrow else cleared; V set if overflow else cleared; Z set if zero else cleared; N set if negative else cleared + + update PC + +if( (ir[15:12] == 4'b1100 || 4'b1000) && ir[7:6] == 2'b11 ) + MULS,MULU,DIVS,DIVU ++++ + load (ea) from ir[5:0] to operand1: data + data: Dn 000, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001, #data 111 100, (d16, PC) 111 010, (d8, PC, Xn) 111 011 + + move operand1 to operand2 + + load (ea) from ir[11:9] to operand1: Dn + + perform ALU operation: + if( ir[15:12] == 4'b1100 && ir[8] == 1'b0 ) MULU + else if( ir[15:12] == 4'b1100 && ir[8] == 1'b1 ) MULS + else if( ir[15:12] == 4'b1000 && ir[8] == 1'b0 ) DIVU + else if( ir[15:12] == 4'b1000 && ir[8] == 1'b1 ) DIVS + + if( MULU/MULS ) + CC: X not affected; C cleared; V cleared; Z set if zero else cleared; N set if negative else cleared + else if( DIVU/DIVS ) + CC: X not affected; C cleared; V set if overflow else if trap undefined else cleared; + Z set if quotient zero else if trap or overflow undefined else cleared; + N set if quotient negative else if trap or overflow undefined else cleared; + + save result to (ea) from ir[11:9]: Dn + + update PC + +if( (ir[15:12] == 4'b1101 || 4'b1001) && (ir[8:6] == 3'b011 || 3'b111) ) + ADDA,SUBA ++++ + load (ea) from ir[5:0] to operand1: all modes + all modes: Dn 000, An (word, long) 001, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001, #data 111 100, (d16, PC) 111 010, (d8, PC, Xn) 111 011 + + move operand1 to operand2 + + load (ea) from ir[11:9] to operand1: An + + ALU operation size, source is sign-extended: + if( ir[8] == 1'b0 ) word + else if( ir[8] == 1'b1 ) long + + perform ALU operation: + if( ir[14:12] == 3'b101 ) ADD + else if( ir[14:12] == 3'b001 ) SUB + + CC: not affected + + save result sign-extended to (ea) from ir[11:9]: An + + update PC + +if( (ir[15:12] == 4'b1011) && (ir[8:6] == 3'b011 || 3'b111) ) + CMPA ++++ + load (ea) from ir[5:0] to operand1: all modes + all modes: Dn 000, An (word, long) 001, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001, #data 111 100, (d16, PC) 111 010, (d8, PC, Xn) 111 011 + + move operand1 to operand2 + + load (ea) from ir[11:9] to operand1: An + + ALU operation size, source is sign-extended: + if( ir[8] == 1'b0 ) word + else if( ir[8] == 1'b1 ) long + + perform ALU operation: + if( ir[14:12] == 3'b011 ) CMP==SUB + + CC: X not affected; C set if borrow else cleared; V set if overflow else cleared; Z set if zero else cleared; N set if negative else cleared + + update PC + +if( ((ir[15:12] == 4'b1100 || 4'b1000) && ir[8:4] == 5'b10000) || ((if[15:12] == 4'b1101 || 4'b1001) && (ir[8:4] == 5'b10000 || 5'b10100 || 5'b11000) ) + ABCD,SBCD,ADDX,SUBX ++++ + load (ea) from ir[2:0] to operand1: Dn (ir[3] == 1'b0), -(An) (ir[3] == 1'b1) + + move operand1 to operand2 + + load (ea) from ir[11:9] to operand1: Dn (ir[3] == 1'b0), -(An) (ir[3] == 1'b1) + + + ALU operation size: + if( ir[7:6] == 2'b00 ) byte + else if( ir[7:6] == 2'b01 ) word + else if( ir[7:6] == 2'b10 ) long + + perform ALU operation: + if( ir[14:12] == 3'b100 ) ABCD + else if( ir[14:12] == 3'b000 ) SBCD + else if( ir[14:12] == 3'b101 ) ADDX + else if( ir[14:12] == 3'b001 ) SUBX + + if( ir[12] == 1'b0 /ABCD,SBCD/ ) + CC: X=C set if decimal carry [borrow] else cleared; Z cleared if result nonzero else unchanged; N,V undefined + else + CC: X=C set if carry[borrow] else cleared; V set if overflow else cleared; Z cleared if nonzero else unchanged; N set if negative else cleared + + save result to (ea) from ir[11:9]: Dn (ir[3] == 1'b0), -(An) (ir[3] == 1'b1) + + update PC + +if( ir[15:12] == 4'b1110 && ir[7:6] == 2'b11 && ir[11] == 1'b0 ) + ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR all memory ++++ + load (ea) from ir[5:0] to operand1: memory alter + memory alter: (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001 + load 1'b1 to operand2 + + ALU operation size: word + + ALU shift/rotate direction: + if( ir[8] == 1'b0 ) right + else if( ir[8] == 1'b1 ) left + + perform ALU operation: + if( ir[10:9] == 2'b00 ) ASL/ASR + else if( ir[10:9] == 2'b01 ) LSL,LSR + else if( ir[10:9] == 2'b11 ) ROL,ROR + else if( ir[10:9] == 2'b10 ) ROXL,ROXR + + CC: X set to last bit, unchanged if zero shift[same][not affected][same set]; N set if MSB bit is set else cleared; Z set if zero else cleared; + V set if MSB bit changed during shift else cleared[cleared][cleared][cleared]; C set to last bit, cleared if zero shift[same][same][set to X] + + save result to (ea) from ir[5:0]: memory alter + memory alter: (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001 + update PC + +if( ir[15:12] == 4'b1110 && (ir[7:6] == 2'b00 || 2'b01 || 2'b10) ) + ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR all immediate/register ++++ + load (ea) from ir[11:9] to operand1: Dn + + move operand1 to operand2 + + load (ea) from ir[2:0] to operand1: Dn + + if( ir[5] == 1'b0 ) + if( ir[11:9] == 3'b000 ) load 4'b1000 to operand2 + else load ir[11:9] to operand2 + else if( ir[5] == 1'b1 ) + perform operand2 modulo 64 + + ALU operation size: + if( ir[7:6] == 2'b00 ) byte + else if( ir[7:6] == 2'b01 ) word + else if( ir[7:6] == 2'b10 ) long + + ALU shift/rotate direction: + if( ir[8] == 1'b0 ) right + else if( ir[8] == 1'b1 ) left + + perform ALU operation: + if( ir[4:3] == 2'b00 ) ASL/ASR + else if( ir[4:3] == 2'b01 ) LSL,LSR + else if( ir[4:3] == 2'b11 ) ROL,ROR + else if( ir[4:3] == 2'b10 ) ROXL,ROXR + + CC: X set to last bit, unchanged if zero shift[same][not affected][same set]; N set if MSB bit is set else cleared; Z set if zero else cleared; + V set if MSB bit changed during shift else cleared[cleared][cleared][cleared]; C set to last bit, cleared if zero shift[same][same][set to X] + + save result to (ea) from ir[2:0]: Dn + + update PC + +if( ir[15:12] == 4'b0111 && ir[8] == 1'b0 ) + MOVEQ ++++ + load ir[7:0] sign-extended to result register + + CC: X not affected; C cleared; V cleared; Z set if zero else cleared; N set if negative else cleared + + save result to (ea) from ir[11:9]: Dn + + update PC + +if( ir[15:12] == 4'b0110 && ir[11:8] == 4'b0001 ) + BSR ++++ + CC: not affected + + SP -= 4 + + move PC to operand1 + move operand1 to result + + save result to (ea): (SP) + + if( ir[7:0] == 8'b0 ) + add to PC: ir1[15:0] + else + add to PC: ir[7:0] + + return + +if( ir[15:12] == 4'b0110 && ir[11:8] != 4'b0001 ) + Bcc,BRA ++++ + condition: high(!C & !Z) 0010, low or same(C | V) 0011, + carry clear(!C) 0100, carry set(C) 0101, not equal(Z) 0110, equal(!Z) 0111, + overflow clear(!V) 1000, overflow set(V) 1001, plus(!N) 1010, minus(N) 1011, + greater or equal(N & V | !N & !V) 1100, less than(N & !V | !N & V) 1101, + greater than(N & V & !Z | !N & !V & !Z) 1110, less or equal(Z | N & !V | !N & V) 1111 + + CC: not affected + + if( contidtion on ir[11:8] true ) + if( ir[7:0] == 8'b0 ) + add to PC: ir1[15:0] + else + add to PC: ir[7:0] + + return + + update PC + +if( ir[15:12] == 4'b0101 && ir[7:6] == 2'b11 && ir[5:3] != 2'b001 ) + Scc ++++ + condition: true(1) 0000, false(0) 0001, high(!C & !Z) 0010, low or same(C | V) 0011, + carry clear(!C) 0100, carry set(C) 0101, not equal(Z) 0110, equal(!Z) 0111, + overflow clear(!V) 1000, overflow set(V) 1001, plus(!N) 1010, minus(N) 1011, + greater or equal(N & V | !N & !V) 1100, less than(N & !V | !N & V), + greater than(N & V & !Z | !N & !V & !Z), less or equal(Z | N & !V | !N & V) 1111 + + if( contidtion on ir[11:8] false ) + load 8'b00000000 to result + else + load 8'b11111111 to result + + operation size: byte + + save result to (ea) from ir[5:0]: data alter. + data alter: Dn 000, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001, + CC: not affected + + update PC + +if( ir[15:12] == 4'b0101 && ir[7:6] == 2'b11 && ir[5:3] == 2'b001 ) + DBcc ++++ + condition: true(1) 0000, false(0) 0001, high(!C & !Z) 0010, low or same(C | V) 0011, + carry clear(!C) 0100, carry set(C) 0101, not equal(Z) 0110, equal(!Z) 0111, + overflow clear(!V) 1000, overflow set(V) 1001, plus(!N) 1010, minus(N) 1011, + greater or equal(N & V | !N & !V) 1100, less than(N & !V | !N & V), + greater than(N & V & !Z | !N & !V & !Z), less or equal(Z | N & !V | !N & V) 1111 + + CC: not affected + + if( condition on ir[11:8] false ) + load (ea) from ir[2:0] to operand1: Dn + + load 1'b1 to operand2 + + ALU operation size: word + + perform ALU operation: SUB + + save result to (ea) from ir[2:0]: Dn + + if( result != -1 ) + add to PC: ir1[15:0] + return + + update PC + +if( ir[15:12] == 4'b0101 && ir[7:6] != 2'b11 && ir[5:3] != 3'b001 ) + ADDQ,SUBQ not An ++++ + if( ir[11:9] == 3'b000 ) + load 4'b1000 to operand2 + else + load ir[11:9] to operand2 + + load (ea) from by ir[5:0] to operand1: data alter + data alter: Dn 000, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001, + + ALU operation size: + if( ir[7:6] == 2'b10 ) long + else if( ir[7:6] == 2'b01 ) word + else if( ir[7:6] == 2'b00 ) byte + + perform ALU operation: + if( ir[8] == 1'b0 ) ADDQ + else if( ir[8] == 1'b1 ) SUBQ + + CC: X=C set if carry[borrow] generated else cleared; V set if overflow else cleared; Z set if result zero else cleared; + N set if result negative else cleared + + save result to (ea) from ir[5:0] + + update PC + +if( ir[15:12] == 4'b0101 && ir[7:6] != 2'b11 && ir[5:3] == 3'b001) + ADDQ,SUBQ An ++++ + if( ir[11:9] == 3'b000 ) + load 4'b1000 to operand2 + else + load ir[11:9] to operand2 + + load (ea) from by ir[2:0] to operand1: An + + ALU operation size: long + + perform ALU operation: + if( ir[8] == 1'b0 ) ADD + else if( ir[8] == 1'b1 ) SUB + + CC: not affected + + save result to (ea) from ir[2:0]: An + + update PC + +if( ir[15:0] == 16'b0100 1110 0111 0001 ) + NOP ++++ + CC: not affected + + update PC + +if( ir[15:0] == 16'b0100 1110 0111 0000 ) + RESET ++++ + hold REST output for 124 clock cycles + + CC: not affected + + update PC + +if( ir[15:0] == 16'b0100 1110 0111 0010 ) + STOP ++++ + copy ir1[15:0] to SR + + Resume when trace, interrupt or rest. + +if( ir[15:5] == 12'b0100 1110 0100 ) + TRAP ++++ + TRAP with vector indexed by ir[3:0] + + CC: not affected + +if( ir[15:0] == 16'b0100 1110 0111 0110 ) + TRAPV ++++ + if( V ) TRAP + + CC: not affected + + update PC + +if( ir[15:0] == 16'b0100 1110 0111 0011 || ir[15:0] == 16'b0100 1110 0111 0111 ) + RTE,RTR ++++ + load (ea) to operand1: (SP) + + perform ALU operation: + if(ir[2] == 1'b0) move operand1 to SR + else if(ir[2] == 1'b1) move operand1 to CCR + + SP += 2 + + load (ea) to operand1: (SP) + move operand1 to result + move result to PC + + SP += 4 + +if( ir[15:0] == 16'b0100 1110 0111 0101 ) + RTS ++++ + load (ea) to operand1: (SP) + move operand1 to result + move result to PC + + SP += 4 + +if( ir[15:6] == 10'b0100 1110 11 ) + JMP ++++ + load (ea) from ir[5:0] to operand1: control + control: (An) 010, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001, (d16, PC) 111 010, (d8, PC, Xn) 111 011 + + perform ALU operation: move operand1 to result + + copy result register to PC + + CC: not affected + +if( ir[15:6] == 10'b0100 1110 10 ) + JSR ++++ + SP -= 4 + + move PC to operand1 + move operand1 to result + save result to (ea): (SP) + + load (ea) from ir[5:0] to operand1: control + control: (An) 010, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001, (d16, PC) 111 010, (d8, PC, Xn) 111 011 + + perform ALU operation: move operand1 to result + + copy result register to PC + + CC: not affected + +if( ir[15:3] == 13'b0100 1110 0101 0 ) + LINK ++++ + SP -= 4 + + load (ea) from ir[2:0] to operand1: An + + perform ALU operation: move operand1 to result + + save result to (ea): (SP) + + load (ea) to operand1: SP + move operand1 to result + + save result to (ea) from ir[2:0]: An + + add to SP: ir1[15:0] + + CC: not affected + + update PC + +if( ir[15:3] == 13'b0100 1110 0101 1 ) + ULNK ++++ + load (ea) from ir[2:0] to operand1: An + + perform ALU operation: move operand1 to result + + save result to (ea): SP + + load ea to operand1: (SP) + move operand1 to result + + save result to (ea) from ir[2:0]: An + + SP += 4 + + CC: not affected + + update PC + +if( ir[15:8] == 8'b0100 1010 && ir[7:6] != 2'b11 ) + TST ++++ + ea operation size: + if( ir[7:6] == 2'b00 ) byte + else if( ir[7:6] == 2'b01 ) word + else if( ir[7:6] == 2'b10 ) long + + load (ea) from ir[5:0] to operand1: data alter + data alter: Dn 000, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001, + + perform ALU TST operation: set CC + + CC: X not affected; C cleared; V cleared; Z set if zero else cleared; N set if MSB bit set else cleared + + update PC + +if( ir[15:6] == 10'b0100 1010 11 && ir[5:0] != 6'b111000 ) + TAS ++++ + ea operation size: byte + + enable READ-MODIFY-WRITE bus cycle + + load (ea) from ir[5:0] to operand1: data alter + data alter: Dn 000, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001, + + perform ALU TAS operation: set bit 7 in result register + + CC: X not affected; C cleared; V cleared; Z set if zero else cleared; N set if MSB bit set else cleared + + save result to (ea) from ir[5:0]: data alter + + disable READ-MODIFY-WRITE bus cycle + + update PC + +if( ir[15:12] == 4'b0100 && ir[8:6] == 3'b110 ) + CHK ++++ + load (ea) from ir[5:0] to operand1: data + data: Dn 000, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001, #data 111 100, (d16, PC) 111 010, (d8, PC, Xn) 111 011 + + move operand1 to operand2 + + load (ea) from ir[11:9] to operand1: Dn + + + ALU operation size: word + + perform ALU CHK operation: operand1 < 0 or operand1 - operand2 > 0 + + CC: X not affected; N set if operand1 < 0; cleared if operand1 - operand2 > 0 else undefined; C,V,Z udefined + + if( ALU check ) trap CHK + + update PC + +if( ir[15:12] == 4'b0100 && ir[8:6] == 3'b111 ) + LEA ++++ + load ea from ir[5:0] to address register: control + control: (An) 010, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001, (d16, PC) 111 010, (d8, PC, Xn) 111 011 + + move address register to operand1 + perform ALU operation: move operand1 to result register + + save result to (ea) from ir[11:9]: An + + CC: not affected + + update PC + +if( ir[15:6] == 10'b0100 1000 01 && ir[5:3] != 3'b000 ) + PEA ++++ + load ea from ir[5:0] to address register: control + control: (An) 010, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001, (d16, PC) 111 010, (d8, PC, Xn) 111 011 + + SP -= 4 + + move address register to operand1 + move operand1 to result + + save result to (ea): (SP) + + CC: not affected + + update PC + +if( ir[15:6] == 10'b0100 0100 11 || ir[15:6] == 10'b0100 0110 11 ) + MOVE TO CCR, MOVE TO SR ++++ + ea operation size: word + + load (ea) from ir[5:0] to operand1: data + data: Dn 000, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001, #data 111 100, (d16, PC) 111 010, (d8, PC, Xn) 111 011 + + if( ir[11:8] == 4'b0110 /MOVE TO SR/ ) + copy word form operand1 register to SR + else + copy lower byte form operand1 register to CCR + + update PC + +if( ir[15:6] == 10'b0100 0000 11 ) + MOVE FROM SR ++++ + copy SR register to result register + + ea operation size: word + + save result to (ea) from ir[5:0]: data alter + data alter: Dn 000, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001, + + CC: not affected + + update PC + +if( ir[15:3] == 12'b0100 1110 0110 0 ) + MOVE USP to USP ++++ + load (ea) from ir[2:0] to operand1: An + + perform ALU operation: move operand1 to result + + move result to USP + + CC: not affected + + update PC + +if( ir[15:3] == 13'b0100 1110 0110 1 ) + MOVE USP to An ++++ + move USP to operand1 + + perform ALU operation: move operand1 to result + + save result to (ea) from ir[2:0]: An + + CC: not affected + + update PC + +if( ir[15:12] == 4'b0100 && ( (ir[11:8] == 4'b0000 && ir[7:6] != 2'b11) || (ir[11:8] == 4'b0010) || (ir[11:8] == 4'b0100 && ir[7:6] != 2'b11) || + (ir[11:8] == 4'b0110 && ir[7:6] != 2'b11) || (ir[11:6] == 6'b1000 00) ) ) ++++ + NEGX,CLR,NEG,NOT,NBCD + + load (ea) from ir[5:0] to operand1: data alter + data alter: Dn 000, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001 + + ALU operation size: + NEGX: ir[7:6]: 00,01,10 byte,word,long + CLR: ir[7:6]: 00,01,10 byte,word,long + NEG: ir[7:6]: 00,01,10 byte,word,long + NOT: ir[7:6]: 00,01,10 byte,word,long + NBCD: ir[7:6]: 00 byte + + perform ALU operation: + NEGX: ir[11:8] == 4'b0000 + CLR: ir[11:8] == 4'b0010 + NEG: ir[11:8] == 4'b0100 + NOT: ir[11:8] == 4'b0110 + NBCD: ir[11:6] == 6'b1000 00 + + CC: + NEGX: X=C set if borrow else clear; V set if overflow else clear; Z cleared if nonzero else unchanged; N set if negative else clear + CLR: X not affected; C cleared; V cleared; Z set; N cleared + NEG: X=C clear if zero else set; V set if overflow else clear; Z set if zero else clear; N set if negative else clear + NOT: X not affected; C cleared; V cleared; Z set if zero else cleared; N set if negative else cleared + NBCD: X=C set if decimal borrow else cleared; Z cleared if nonzero else unchanged; N,V undefined + + save result to (ea) from ir[5:0]: data alter + + update PC + +if( ir[15:12] == 4'b0100 && (ir[11:3] == 9'b1000 01 000 || (ir[11:7] == 5'b1000 1 && ir[5:3] == 3'b000) ) + SWAP,EXT ++++ + load (ea) from ir[5:0] to operand1: Dn + + ALU operation size: word + SWAP: ir[7:6]: 01 long + EXT: ir[7:6]: 10,11 byte to word, word to long + + perform ALU operation: + SWAP: ir[11:6] == 6'b1000 01 + EXT: ir[11:7] == 5'b1000 1 + + CC: + SWAP: X not affected; C cleared; V cleared; Z set if 32 bits are zero else cleared; N set if result MSB set else cleared + EXT: X not affected; C cleared; V cleared; Z set if zero else cleared; N set if negative else cleared + + save result to (ea) from ir[5:0]: Dn + + update PC + +if( ir[15:7] == 9'b0100 1100 1 && ir[5:3] != 3'b000 ) + MOVEM memory to register ++++ + operation size: + if( ir[6] == 1'b0 ) word + else if ir[6] == 1'b1 ) long + + load ea from ir[5:0] to address register: control or postincrement + (An) 010, (An)+ 011, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001, (d16, PC) 111 010, (d8, PC, Xn) 111 011 + + register selection order: D0,D1,...D7,A0,A1,...,A7 + + do + if( ir1[0] == 1'b1 ) + read from (ea) to operand1 + + perform ALU operation: move operand1 with sign-extension to result + + save result to selected register + + update address register + + shift ir1 + loop 16 times + + if( ir[5:3] == 3'b011 ) save address register back to An indexed by ir[2:0] + + CC: not affected + + update PC + +if( ir[15:7] == 9'b0100 1000 1 && ir[5:3] == 3'b100 ) + MOVEM register to memory, predecrement ++++ + operation size: + if( ir[6] == 1'b0 ) word + else if ir[6] == 1'b1 ) long + + load ea from ir[5:0] to address register: control alter or predecrement + (An) 010, -(An) 100, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001, + + register selection order: A7,A6,..A0,D7,D6,....D0 + + do + if( ir1[0] == 1'b1 ) + save selected register to operand1 + + perform ALU operation: move operand1 to result + + save result to (ea) + + update address register + + shift ir1 + loop 16 times + + if( ir[5:3] == 3'b100 ) save address register back to An indexed by ir[2:0] + + CC: not affected + + update PC + +if( ir[15:7] == 9'b0100 1000 1 && ir[5:3] != 3'b000 && ir[5:3] != 3b100 ) + MOVEM register to memory, control ++++ + operation size: + if( ir[6] == 1'b0 ) word + else if ir[6] == 1'b1 ) long + + load ea from ir[5:0] to address register: control alter or predecrement + (An) 010, -(An) 100, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001, + + register selection order: D0,D1,...D7,A0,A1,...,A7 + + do + if( ir1[0] == 1'b1 ) + save selected register to operand1 + + perform ALU operation: move operand1 to result + + save result to (ea) + + update address register + + shift ir1 + loop 16 times + + CC: not affected + + update PC + +*/ + +/* + +>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> +microinstructions + +MOVE_ea_reg_TO_An_address +MOVE_ea_reg_TO_Dn_address +MOVE_ir1_brief_ext_TO_An_Dn_addresses // ir_valid +MOVE_An_output_TO_address +MOVE_Dn_output_TO_OP1 +MOVE_An_output_TO_OP1 +MOVE_zeros_TO_index +MOVE_ir1_brief_ext_TO_index // ir_valid +MOVE_ir1_byte_TO_offset // ir_valid +MOVE_ir1_word_TO_offset // ir_valid +MOVE_base_index_offset_TO_address +MOVE_ir1_absolute_word_TO_address // ir_valid +MOVE_ir1_ir2_absolute_long_TO_address // ir_valid +MOVE_pc_index_offset_TO_address +MOVE_trap_TO_address +MOVE_result_TO_An_input +MOVE_result_TO_Dn_input(size=) +MOVE_address_TO_An_input +MOVE_result_TO_data + +MOVE_OP1_TO_OP2 +MOVE_OP2_TO_OP1 +MOVE_ADDR_TO_OP1 +MOVE_data_TO_OP1 +MOVE_immediate_TO_OP1(size=) +MOVE_result_TO_OP1 +MOVE_moveq_TO_OP1 +MOVE_PC_NEXT_TO_OP1 +MOVE_zeros_TO_OP1 +MOVE_ones_TO_OP1 +MOVE_SR_TO_OP1 +MOVE_USP_TO_OP1 +MOVE_ir_TO_OP1 +MOVE_address_bus_info_TO_OP2 +MOVE_1_TO_OP2 +MOVE_offset_TO_OP2 +MOVE_count_TO_OP2 +MOVE_addq_subq_TO_OP2 +MOVE_result_TO_PC +MOVE_result_TO_USP +MOVE_zeros_TO_movem_mod_reg +MOVE_001111_TO_movem_mod_reg +MOVE_OP1_TO_movem_reg +MOVE_zeros_TO_movem_loop +MOVE_prefetch_ir_TO_ir +MOVE_interrupt_mask_TO_sr +MOVE_1_0_supervisor_trace_TO_sr +MOVE_reset_mask_TO_sr +MOVE_prefetch_ir_TO_PC +MOVE_prefetch_ir_TO_SSP + +MOVE_illegal_instr_TO_TRAP +MOVE_divide_by_zero_TO_TRAP +MOVE_chk_TO_TRAP +MOVE_trapv_TO_TRAP +MOVE_priv_viol_TO_TRAP +MOVE_trap_TO_TRAP +MOVE_decoder_trap_TO_TRAP +MOVE_trace_TO_TRAP +MOVE_interrupt_trap_TO_TRAP + +MOVE_0_TO_stop_flag +MOVE_1_TO_stop_flag +MOVE_sr15_TO_trace_flag +MOVE_0_TO_group_0_flag +MOVE_1_TO_group_0_flag +MOVE_0_TO_read_modify_write_flag +MOVE_1_TO_read_modify_write_flag +MOVE_0_TO_instruction_flag +MOVE_1_TO_instruction_flag +MOVE_1_TO_blocked_flag +MOVE_0_TO_read_flag +MOVE_1_To_read_flag +MOVE_0_TO_write_flag +MOVE_1_TO_write_flag +MOVE_0_TO_interrupt_flag +MOVE_1_TO_interrupt_flag +MOVE_1_TO_reset_flag +MOVE_0_TO_reset_flag + +INCR_ADDR_BY_SIZE(size=) +DECR_ADDR_BY_SIZE(size=) +DECR_OP2_BY_1 +CALL procedure +RETURN +INCR_movem_loop_BY_1 +INCR_movem_mod_reg_BY_1 +DECR_movem_mod_reg_BY_1 +JMP: local label, trap, instr_fin, instr_fin_pc_loaded, +SHIFT_RIGHT_movem_reg +INCR_PC_BY_2 +INCR_PC_BY_4 +INCR_PC_BY_size(size=) + +BRANCH(movem_loop == 4'b1000) +BRANCH(movem_reg[0] == 0) +BRANCH(operand2[5:0] == 6'b0) +BRANCH(special == 2'b01) +BRANCH(special == 2'b10) +BRANCH(condition == 1'b0) +BRANCH(condition == 1'b1) +BRANCH(result[15:0] == 16'hFFFF) +BRANCH(V == 1'b0) +BRANCH(stop_flag == 1'b1) +BRANCH(ir[7:0] != 8'b0) +BRANCH(decoder_trap == 8'b0) +BRANCH(trace_flag == 1'b0) +BRANCH(group_0_flag == 0) + +WAIT_RESET, WAIT_MEMORY_READ(size, address), WAIT_MEMORY_WRITE(size, address, select), WAIT_interrupt, WAIT_blocked +WAIT_prefetch_ir_valid + +subprocedures: +ea(size=, reg=, mod=, type=, select=) + +LOAD_EA: to address register +PERFORM_EA_READ: to operand1 +PERFORM_EA_WRITE: from result +SAVE_EA + +>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> + +TYPE.ALL: all + Dn 000, An (word, long) 001, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001, #data 111 100, (d16, PC) 111 010, (d8, PC, Xn) 111 011 +TYPE.CONTROL_POSTINC: control or postincrement + (An) 010, (An)+ 011, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001, (d16, PC) 111 010, (d8, PC, Xn) 111 011 +TYPE.CONTROLALTER_PREDEC: control alter or predecrement + (An) 010, -(An) 100, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001, +TYPE.CONTROL: control + (An) 010, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001, (d16, PC) 111 010, (d8, PC, Xn) 111 011 +TYPE.DATAALTER: data alter + Dn 000, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001, +TYPE.DN_AN: Dn, An + Dn 000, An 001 +TYPE.MEMORYALTER: memory alter + (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001 +TYPE.DATA: data + Dn 000, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001, #data 111 100, (d16, PC) 111 010, (d8, PC, Xn) 111 011 + + Index: trunk/doc/src/mc68000.txt =================================================================== --- trunk/doc/src/mc68000.txt (nonexistent) +++ trunk/doc/src/mc68000.txt (revision 2) @@ -0,0 +1,1120 @@ +Registers: +D0,D1,D2,D3,D4,D5,D6,D7 32-bit +A0,A1,A2,A3,A4,A5,A6 32-bit +A7 USP 32-bit +A7' SSP 32-bit +PC 32-bit +CCR condition code reg, SR status register 8-bit User, 16-bit Supervisor + +Address registers: +base address registers, word and long-word operations, +operations always affect 32-bits, word operations sign-extended +All 16: index registers + +SR +Condition Code Register: +0: C Carry +1: V Overflow +2: Z Zero +3: N Negative +4: X Extend +Status register: +8-10: I Interrupt mask +13: S Supervisor +15: T Trace mode + +MC68000 Addressing modes + Number of extension words +Register Direct Addressing + Data Register Direct = Dn 0 + Address Register Direct = An 0 +Absolute Data Addressing + Absolute Short = (Next Word) 1 + Absolute Long = (Next Two Words) 2 +Program Counter Relative Addressing + Relative with Offset = (PC + d16) 1 + Relative with Index and Offset = (PC + Rn + d8) 1* +Register Indirect Addressing + Register Indirect = (An) 0 + Postincrement Register Indirect = (An), An <- An + N 0 + Predecrement Register Indirect An <- An–N, = (An) 0 + Register Indirect with Offset = (An + d16) 1 + Indexed Register Indirect with Offset = (An + Rn + d8) 1* +Immediate Data Addressing + Immediate DATA = Next Word(s) 1 or 2 + Quick Immediate Inherent Data 0 +Implied Addressing + Implied Register = SR, USP, SSP, PC 0 + +N = 1 for byte, 2 for word, and 4 for long word. If An is the stack pointer and + the operand size is byte, N = 2 to keep the stack pointer on a word + boundary. + +1*: format of brief extension word +Data/Address(1 bit) Rn(3 bits) word/long(1 bit) 000 d8(8 bits) +word/long: size of sign-extended index register + +Exceptions +0 Reset: Initial SSP (Supervisor Program Space) +1 Reset: Initial PC (Supervisor Program Space) + +2 Bus Error From external logic +3 Address Error Odd address fetch +4 Illegal Instruction $4AFA, $4AFB, $4AFC +5 Zero Divide +6 CHK Instruction Trap check bounds +7 TRAPV Instruction Trap overflow +8 Privilege Violation +9 Trace +10 Line 1010 Emulator Illegal instruction +11 Line 1111 Emulator Illegal instruction +12-14 RESERVED +15 Uninitialized Interrupt Vector Default for uninitialized ext hw +16-23 RESERVED +24 Spurious Interrupt Bus error while int ack cycle +25 Level 1 Interrupt Autovector +26 Level 2 Interrupt Autovector +27 Level 3 Interrupt Autovector +28 Level 4 Interrupt Autovector +29 Level 5 Interrupt Autovector +30 Level 6 Interrupt Autovector +31 Level 7 Interrupt Autovector +32-47 Trap Instruction Vectors Trap instruction +48-63 RESERVED +64-255 User Interrupt Vectors + +Ack cycle: DACK + vector number, VPA, AVEC, BERR + +Privilege violations: PC address current +AND Immediate to SR +EOR Immediate to SR +OR Immediate to SR +MOVE to SR? +MOVE USP +RESET +RTE +STOP + +Tracing +Not: when interrupt, illegal, privileged, reset, bus error, address error +Before: pending interrupt +After: instruction generated exception + +Stack Frame +Reset: +None + +Bus/Address error: +00. reset, 01. address error, 02. bus error: immediate reaction: abort current bus cycle, abort instruction or exception processing +if bus error/address error while address error,bus error or reset: block processor +address error: access word or long operand or instruction from odd address +bus error: BERR +processing an instruction: normal state or in group 2 exception +not processing an instruction: group 0 or 1 exception +Stack frame: +Undefined 11 bits, Read/Write bit 4, Instruction/Not bit 3, Function code bits 2-0, +Access address 32 bits, +Instruction register 16 bits, +Status register 16 bits, +Program counter 32 bits + +Rest: +Status register, Program counter + +Processing sequence +From TRAP: 1 -> S-bit of SR; SSP -= 4; PC -> (SSP); SSP -= 2; SR -> (SSP) +From ILLEGAL: SSP -= 4; PC -> (SSP); SSP -= 2; SR -> (SSP) +Copy status register +Enter Supervisor mode +Turn off tracing +Reset, interrupt exceptions: update interrupt priority mask +Determine vector number +Save on stack using SSP + +PC value in exceptions: + usualy: trap: trace: interrupt: with address of next instruction, + address and bus errors: advanced 2-10 bytes after first word of current instruction + privilege violation: illegal: address of first word of current instruction + + +Without: +- Function Codes +- Bus arbitration +- Synchronous 6800 bus cycles + + +Operation code map: +0000 Bit Manipulation/MOVEP/Immediate +0001 Move Byte +0010 Move Long +0011 Move Word +0100 Miscellaneous +0101 ADDQ/SUBQ/Scc/DBcc/TRAPc +0110 Bcc/BSR/BRA +0111 MOVEQ +1000 OR/DIV/SBCD +1001 SUB/SUBX +1010 (Unassigned, Reserved) +1011 CMP/EOR +1100 AND/MUL/ABCD/EXG +1101 ADD/ADDX +1110 Shift/Rotate/Bit Field +1111 Coprocessor Interface/MC68040 and CPU32 Extensions + + +******************************************************************************************************************************************* +******************************************************************************************************************************************* +******************************************************************************************************************************************* + + +******************************************************************************************************************************************* +* add, sub +******************************************************************************************************************************************* +* +ABCD Add Decimal with Extend +[SBCD Subtract Decimal with Extend] + Destination10 +[-] Source10 +[-] X -> Destination + Byte operation, packed BCD + CC: X=C set if decimal carry [borrow] else cleared; Z cleared if result nonzero else unchanged; N,V undefined + 1100[1000] Ry dest(3 bits) 1 0000 R/M Rx source(3 bits) + R/M = 0 data registers, 1 = address registers predecrement: -(An) +* +ADD Add +[SUB Subtract] + Destination +[-] Source -> Destination + Byte, Word, Long + CC: X=C set if carry[borrow] generated else cleared; V set if overflow else cleared; Z set if result zero else cleared; + N set if result negative else cleared + 1101[1001] register(3 bits) opmode(3 bits) ea mode register (3,3 bits) + register: data reg + opmode: 000,001,010 byte,word,long: ea +[-] Dn -> Dn; 100, 101, 110 byte,word,long: Dn +[-] ea -> ea + ea source, all modes: Dn 000, An (word, long) 001, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001, #data 111 100, (d16, PC) 111 010, (d8, PC, Xn) 111 011 + ea dest, memory alter: (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001 +* +ADDA Add Address +[SUBA Subtract Address] + Destination +[-] Source -> Destination + Word, Long + CC: not affected + 1101[1001] register(3 bits) opmode(3 bits) ea mode register(3,3 bits) + register: destination An + opmode: 011 word operation sign extended to 32 bits; 111 long operation + ea source, all modes. +* +ADDI Add Immediate +[SUBI Subtract Immediate] + Destination +[-] Immediate data -> Destination + Byte, Word, Long + CC: same as ADD + 0000 0110[0100] size(2 bits) ea mode register(3,3 bits); imm16 next word, imm8 lower order byte of next word, imm32 two next words + size: 00,01,10 byte,word,long + ea dest, data alter: Dn 000, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001, +* +ADDQ Add Quick +[SUBQ Subtract Quick] + Destination +[-] Immediate data -> Destination + Byte, Word, Long + CC: same as ADD,ADDA; not affected when destiantion is An + 0101 data(3 bits) 0[1] size(2 bits) ea mode register (3,3 bits) + data: immediate data: 0=8, 1=1, ..., 7=7 + size: 00,01,10 byte,word,long + ea dest, alter: Dn 000, An (word, long) 001, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001, +* +ADDX Add with Extend +[SUBX Subtract with Extend] + Destination +[-] Source +[-] X -> Destination + Byte, Word, Long + CC: X=C set if carry[borrow] else cleared; V set if overflow else cleared; Z cleared if nonzero else unchanged; N set if negative else cleared + 1101[1001] Ry dest(3 bits) 1 size(2 bits) 00 R/M Rx source(3 bits) + R/M = 0 data registers, 1 = address registers predecrement: -(An) + size: 00,01,10 byte,word,long + +******************************************************************************************************************************************* +* cmp +******************************************************************************************************************************************* +* +CMP Compare + Destination - Source -> CC + Byte, Word, Long + CC: X not affected; C set if borrow else cleared; V set if overflow else cleared; Z set if zero else cleared; N set if negative else cleared + 1011 register(3 bits) opmode(3 bits) ea mode register(3,3 bits) + register: destination Dn + opmode: 000,001,010 byte,word,long: Dn - ea + ea source, all modes. +* +CMPA Compare Address + Destination - Source -> CC + CC: same as CMP + 1011 register(3 bits) opmode(3 bits) ea mode register(3,3 bits) + register: destination An + opmode: 011 word operation sign extended to 32 bits; 111 long operation + ea source, all modes. +* +CMPI Compare Immediate + Destination - Immediate Data -> CC + Byte, Word, Long + CC: same as CMP + 0000 1100 size(2 bits) ea mode register(3,3 bits); imm16 next word, imm8 lower order byte of next word, imm32 two next words + size: 00,01,10 byte,word,long + ea dest, data alter. +* +CMPM Compare Memory to Memory + Destination - Source -> CC + Byte, Word, Long + CC: same as CMP + 1011 Ax dest(3 bits) 1 size(2 bits) 00 1 Ay source(3 bits) + Ax dest, Ay source: postincrement: +(An) + size: 00,01,10 byte,word,long + +******************************************************************************************************************************************* +* mul, div +******************************************************************************************************************************************* +* +MULS Signed Multiply +[MULU Unsigned Multiply] + Source x Destination -> Destination + Word operation: source and dest 16 bit lower order -> destination 32 bit + CC: X not affected; C cleared; V cleared; Z set if zero else cleared; N set if negative else cleared + 1100 Dn dest(3 bits) 1[0] 11 ea mode register(3,3 bits) + ea source, data: Dn 000, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001, #data 111 100, (d16, PC) 111 010, (d8, PC, Xn) 111 011 + +* +DIVS Signed Divide +[DIVU Unsigned Divide] + Destination / Source -> Destination + Word operation: dest 32 bits, source 16 bits -> 16 bit MSB remainder, 16 bit LSB quotient, sign of remainder = sign of dividend + CC: X not affected; C cleared; V set if overflow else if trap undefined else cleared; + Z set if quotient zero else if trap or overflow undefined else cleared; + Z set if quotient negative else if trap or overflow undefined else cleared; + 1000 Dn dest(3 bits) 1[0] 11 ea mode register(3,3 bits) + ea source, data. + + Overflow: if quotient larger than a 16-bit signed integer. + Division by 0: trap. + If overflow detected: operands unaffected. + +******************************************************************************************************************************************* +* ext, neg +******************************************************************************************************************************************* +* +EXT Sign Extend + Destination sign-extended -> Destination + Word, Long + CC: X not affected; C cleared; V cleared; Z set if zero else cleared; N set if negative else cleared + 0100 100 opmode(3 bits) 00 0 Dn dest(3 bits) + opmode: 010,011 byte to word, word to long +* +NEGX Negate with Extend + 0 - Destination - X -> Destination + Byte, Word, Long + CC: X=C set if borrow else clear; V set if overflow else clear; Z set if nonzero else unchanged; N set if negative else clear + 0100 0000 size(2 bits) ea mode register(3,3 bits) + size: 00,01,10 byte,word,long + ea dest, data alter. +* +NBCD Negate Decimal with Extend + 0 - Destination10 - X -> Destination + Byte operation + CC: X=C set if decimal borrow else cleared; Z cleared if nonzero else unchanged; N,V undefined + 0100 1000 00 ea mode register(3,3 bits) + ea dest, data alter. +* +NEG Negate + 0 - Destination -> Destination + Byte, Word, Long + CC: X=C clear if zero else set; V set if overflow else clear; Z set if zero else clear; N set if negative else clear + 0100 0100 size(2 bits) ea mode register(3,3 bits) + size: 00,01,10 byte,word,long + ea dest, data alter. + +******************************************************************************************************************************************* +* and,eor,or,not +******************************************************************************************************************************************* +* +AND Logical AND +[OR Logical Inclusive-OR] + Source &[|] Destination -> Destination + Byte, Word, Long: not on An + CC: X not affected; C cleared; V cleared; Z set if zero else clear; N set if MSB set else cleared + 1100[1000] Dn register(3 bits) opmode(3 bits) ea mode register(3,3 bits) + opmode: 000,001,010 byte,word,long: ea & Dn -> Dn; 100,101,110 byte,word,long: Dn & ea -> ea + ea source, data. + ea dest, memory alter. +* +ANDI Logical AND Immediate +[EORI Logical Exclusive-OR Immediate] +[ORI Logical Inclusive-OR Immediate] + Immediate data &[^][|] Destination -> Destination + Byte, Word, Long + CC: X not affected; C cleared; V cleared; Z set if zero else clear; N set if MSB set else cleared + 0000 0010[1010][0000] size(2 bits) ea mode register(3,3 bits); imm16 next word, imm8 lower order byte of next word, imm32 two next words + size: 00,01,10 byte,word,long + ea dest, data alter. +* +ANDI to CCR AND Immediate to Condition Code Register +[EORI to CCR Exclusive-OR Immediate to Condition Code Register] +[ORI to CCR Inclusive-OR Immediate to Condition Code Register] + Source &[^][|] CCR -> CCR + Byte operation + CC: result + 0000 0010[1010][0000] 00 111 100; 0000 0000 data(8 bit) +* +ANDI to SR AND Immediate to Status Register/Privilege/ +[EORI to SR Exclusive-OR Immediate to Status Register/Privilege/] +[ORI to SR Inclusive-OR Immediate to Status Register/Privilege/] + Source &[^][|] SR -> SR + Word operation + CC: result + 0000 0010[1010][0000] 01 111 100; data(16 bit) +* +EOR Logical Exclusive-OR + Source ^ Destination -> Destination + Byte, Word, Long + CC: X not affected; C cleared; V cleared; Z set if zero else clear; N set if MSB set else cleared + 1011 Dn source(3 bits) opmode(3 bits) ea mode register(3,3 bits) + opmode: 100,101,110 byte,word,long: ea ^ Dn -> ea + ea dest, data alter. +* +NOT Logical Complement + ~ Destination -> Destination + Byte, Word, Long + CC: X not affected; C cleared; V cleared; Z set if zero else cleared; N set if negative else cleared + 0100 0110 size(2 bits) ea mode register(3,3 bits) + size: 00,01,10 byte,word,long + ea dest, data alter. + +******************************************************************************************************************************************* +* shift,rotate +******************************************************************************************************************************************* +* +ASL, ASR Arithmetic Shift Left and Right +[LSL, LSR Logical Shift Left and Right] +[ROL, ROR Rotate Left and Right] +[ROXL, ROXR Rotate with Extend Left and Right] + Destination shifted[shifted][rotated][rotated with X] by count -> Destination + Byte, Word, Long, in memory: 1 bit shift[shift][rotate][rotate] and word + CC: X set to last bit, unchanged if zero shift[same][not affected][same set]; N set if MSB bit is set else cleared; + Z set if zero else cleared; V set if MSB bit changed during shift else cleared[cleared][cleared][cleared]; + C set to last bit, cleared if zero shift[same][same][set to X] + 1110 count/register(3 bits) dr(1 bit) size(2 bits) i/r(1 bit) 00[01][11][10] Dn dest(3 bit) + i/r = 0 count/register=count: 0=8, 1=1, ..., 7=7; i/r = 0 count/register=register: modulo 64 + dr = 0 right shift; dr = 1 left shift + size: 00,01,10 byte,word,long + 1110 000[001][011][010] dr(1 bit) 11 ea mode register(3,3 bits) + dr = 0 right shift; dr = 1 left shift + ea dest: memory alter. + +******************************************************************************************************************************************* +* move,clr,exg,swap +******************************************************************************************************************************************* +* +MOVE Move + Source -> Destination + Byte, Word, Long + CC: X not affected; C cleared; V cleared; Z set if zero else cleared; N set if negative else cleared + 00 size(2 bits) ea dest register mode(3,3 bits) ea source mode register(3,3 bits) + size: 01,11,10 byte,word,long + ea dest, data alter. + ea source, all modes. +* +MOVEA Move Address + Source -> Destination + Word, Long + CC: not affected + 00 size(2 bits) An dest(3 bits) 0 01 ea source mode register(3,3 bits) + size: 11,10 word,long: word operands are sign extended + ea source, all modes. +* +MOVE to CCR Move to Condition Code Register + Source -> CC + Word operation: upper byte ignored + 0100 0100 11 ea source mode register(3,3 bits) + ea source, data. +* +MOVE from SR Move from Status Register + SR -> Destination + Word operation + CC: not affected + 0100 0000 11 ea dest mode register(3,3 bits) + ea dest, data alter. +* +MOVE to SR Move to Status Register/Privileged/ + Source -> SR + Word operation + CC: result + 0100 0110 11 ea source mode register(3,3 bits) + ea source, data. +* +MOVE USP Move User Stack Pointer/Privileged/ + USP -> An; An -> USP + Long operation + CC: not affected + 0100 1110 0110 dr(1 bit) An reg(3 bits) + dr: 0 An -> USP; 1 USP -> An +* +MOVEM Move Multiple Registers + Registers -> Destination; Source -> Registers + Word, Long: word operations to An or Dn are sign extended + CC: not affected + 0100 1 dr(1 bit) 00 1 size(1 bit) ea mode register(3,3 bits); register list mask + dr: 0 register to memory; 1 memory to register + size: 0,1 word,long operation + ea dest: register to memory, control alter or predecrement available: + (An) 010, -(An) 100, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001, + ea source: memory to register, control or postincrement available: + (An) 010, (An)+ 011, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001, (d16, PC) 111 010, (d8, PC, Xn) 111 011 + list mask: control or postincrement: A7-A0, D7-D0; predecrement: D0-D7; A0-A7 +* +MOVEP Move Peripheral + Source -> Destination + Word, Long + CC: not affected + 0000 data reg(3 bits) opmode(3 bits) 00 1 address reg(3 bits); 16 bit displacement + opmode: 100,101 word,long: memory -> register; 110,111 word,long: register -> memory + address reg: (An, d16) +* +MOVEQ Move Quick + Immediate data -> Destination + Long operation; 8 bit data is sign extended to 32 bits + CC: X not affected; C cleared; V cleared; Z set if zero else cleared; N set if negative else cleared + 0111 Dn dest(3 bits) 0 data(8 bits) +* +CLR Clear + 0 -> Destination + Byte, Word, Long + CC: X not affected; C cleared; V cleared; Z set; N cleared + 0100 0010 size(2 bits) ea dest mode register(3,3 bits) + size: 00,01,10 byte,word,long + ea dest, data alter. +* +EXG Exchange Registers + Rx <-> Ry + Long operation + CC: not affected + 1100 Rx reg(3 bits) 1 opmode(5 bits) Ry reg(3 bits) + Rx reg: if Dn <-> An always Dn + Ry reg: if Dn <-> An always An + opmode: 01000 data regs; 01001 address regs; 10001 mix regs +* +SWAP Swap Register Words + Reg 31-16 <-> Reg 15-0 + Word operation + CC: X not affected; C cleared; V cleared; Z set if 32 bits are zero else cleared; N set if result MSB set else cleared + 0100 1000 0100 0 reg(3 bits) + +******************************************************************************************************************************************* +* branch,jump +******************************************************************************************************************************************* +* +Bcc Branch Conditionally + if condition PC + d8/d16 -> PC + Byte, Word + CC: not affected + 0110 condition(4 bits) disp8(8 bit); 16 bit displacement if disp8 == 0 + condition: high(!C & !Z) 0010, low or same(C | V) 0011, + carry clear(!C) 0100, carry set(C) 0101, not equal(Z) 0110, equal(!Z) 0111, + overflow clear(!V) 1000, overflow set(V) 1001, plus(!N) 1010, minus(N) 1011, + greater or equal(N & V | !N & !V) 1100, less than(N & !V | !N & V) 1101, + greater than(N & V & !Z | !N & !V & !Z) 1110, less or equal(Z | N & !V | !N & V) 1111 +* +BRA Branch + if condition PC + d8/d16 -> PC + Byte, Word + CC: not affected + 0110 0000 disp8(8 bit); 16 bit displacement if disp8 == 0 +* +BSR Branch to Subroutine + SP -= 4; PC -> (SP); PC + d8/d16 -> PC + Byte, Word + CC: not affected + 0110 0001 disp8(8 bit); 16 bit displacement if disp8 == 0 +* +DBcc Test Condition, Decrement, and Branch + if !condition { Dn(lower order 16 bits) -= 1; if Dn != -1 then PC + d16 -> PC } + Word operation + CC: not affected + 0101 condition(4 bits) 1100 1 Dn register(3 bits); 16 bit displacement + condition: true(1) 0000, false(0) 0001, high(!C & !Z) 0010, low or same(C | V) 0011, + carry clear(!C) 0100, carry set(C) 0101, not equal(Z) 0110, equal(!Z) 0111, + overflow clear(!V) 1000, overflow set(V) 1001, plus(!N) 1010, minus(N) 1011, + greater or equal(N & V | !N & !V) 1100, less than(N & !V | !N & V), + greater than(N & V & !Z | !N & !V & !Z), less or equal(Z | N & !V | !N & V) 1111 +* +JMP Jump + Destination address -> PC + Unsized + CC: not affected + 0100 1110 11 ea mode register(3,3 bits) + ea, control: (An) 010, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001, (d16, PC) 111 010, (d8, PC, Xn) 111 011 +* +JSR Jump to Subroutine + SP -= 4; PC -> (SP); Destination address -> PC + Unsized + CC: not affected + 0100 1110 10 ea mode register(3,3 bits) + ea, control. +* +RTR Return and Restore + (SP) -> CC; SP += 2; (SP) -> PC; SP += 4 + Unsized + CC: set from stack; supervisor bits unaffected + 0100 1110 0111 0111 +* +RTS Return from Subroutine + (SP) -> PC; SP += 4 + Unsized + CC: not affected + 0100 1110 0111 0101 + +******************************************************************************************************************************************* +* test bit,test,check +******************************************************************************************************************************************* +* +BCHG Test Bit and Change +[BCLR Test Bit and Clear] +[BSET Test Bit and Set] +[BTST Test Bit] + test( of Destination ) -> Z; test( of Destination )[0][1][nothing] -> of Destination + Byte, Long + CC: X,N,V,C not affected; Z set if bit tested is zero else cleared + 0000 Dn reg(3 bits) 101[110][111][100] ea mode register(3,3 bits) + Dn reg: bit number + ea dest, data alter.[same][same][data address]; Dn is long operation else byte operation + 0000 1000 01[10][11][00] ea mode register(3,3 bits); 0000 0000 bit number(8 bits) + ea dest, data alter[same][same][data address]; Dn is long operation else byte operation + + ea data address Dn 000, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110, + (xxx).W 111 000, (xxx).L 111 001, (d16, PC) 111 010, (d8, PC, Xn) 111 011 +* +Scc Set Conditionally + if condition 1s -> Destination else 0s -> Destination + Byte operation + CC: not affected + 0101 condition(4 bits) 11 ea mode register(3,3 bits) + condition: same as in DBcc + ea dest, data alter. +* +TAS Test Operand and Set/Read-modify-write bus operation/ + Destination tested -> CC; 1 -> bit 7 of destination + Byte operation + CC: X not affected; C cleared; V cleared; Z set if zero else cleared; N set if MSB bit set else cleared + 0100 1010 11 ea mode register(3,3 bits) + ea operand, data alter. +* +TST Test Operand + Destination tested -> CC + Byte, Word, Long + CC: X not affected; C cleared; V cleared; Z set if zero else cleared; N set if MSB bit set else cleared + 0100 1010 size(2 bits) ea mode register(3,3 bits) + size: 00,01,10 byte,word,long + ea operand, data alter. +* +CHK Check Register Against Bound + if Dn < 0 or Dn > Source then TRAP + Word operation + CC: X not affected; N set if Dn < 0; cleared if Dn > Source else undefined; C,V,Z udefined + 0100 Dn reg(3 bits) size(2 bits) 0 ea mode register(3,3 bits) + size: 11 word + ea source, data. + +******************************************************************************************************************************************* +* address,stack +******************************************************************************************************************************************* +* +LEA Load Effective Address + ea -> An + Long operation + CC: not affected + 0100 An reg(3 bits) 1 11 ea mode register(3,3 bits) + ea, control. +* +PEA Push Effective Address + SP -= 4; ea -> (SP) + Long operation + CC: not affected + 0100 1000 01 ea mode register(3,3 bits) + ea, control. +* +LINK Link and Allocate + SP -= 4; An -> (SP); SP -> An; SP + d16 -> SP + Word operation + CC: not affected + 0100 1110 0101 0 An reg(3 bits); 16 bit displacement +* +UNLK Unlink + An -> SP; (SP) -> An; Sp += 4 + Unsized + CC: not affected + 0100 1110 0101 1 An reg(3 bits) + +******************************************************************************************************************************************* +* exceptions +******************************************************************************************************************************************* +* +ILLEGAL Take Illegal Instruction Trap + SSP -= 4; PC -> (SSP); SSP -= 2; SR -> (SSP) + Unsized + CC: not affected + 0100 1010 1111 1100 +* +TRAP Trap + 1 -> S-bit of SR; SSP -= 4; PC -> (SSP); SSP -= 2; SR -> (SSP) + Unsized + CC: not affected + 0100 1110 0100 vector(4 bits) +* +TRAPV Trap on Overflow + if V then TRAP + Unsized + CC: not affected + 0100 1110 0111 0110 +* +RTE Return from Exception/Privileged/ + if S-bit set in SR then { (SP) -> SR; SP += 2; (SP) -> PC; SP += 4; restore state and dealocate rest of stack according to (SP) } else TRAP + Unsized + CC: set from stack + 0100 1110 0111 0011 + +******************************************************************************************************************************************* +* control +******************************************************************************************************************************************* +* +NOP No Operation + None + Unsized + CC: not affected + 0100 1110 0111 0001 +* +RESET Reset External Devices/Privileged/ + if S-bit set in SR then { assert !RESET line for 124 clock cycles } else TRAP + Unsized + CC: not affected + 0100 1110 0111 0000 +* +STOP Stop/Privileged/ + if S-bit set in SR then { immediate data -> SR; STOP } else TRAP + Unsized + CC: set according to immediate data + 0100 1110 0111 0010; 16 bit immediate data + + Resume when trace, interrupt or rest. + +******************************************************************************************************************************************* +******************************************************************************************************************************************* +******************************************************************************************************************************************* + +0000 0010[1010][0000] size(2 bits) ea mode register(3,3 bits); imm16 next word, imm8 lower order byte of next word, imm32 two next words + ANDI,EORI,ORI + +0000 0010[1010][0000] 00 111 100; 0000 0000 data(8 bit) ANDI to CCR,EORI to CCR,ORI to CCR +0000 0010[1010][0000] 01 111 100; data(16 bit) ANDI to SR,EORI to SR,ORI to SR + +0000 0110[0100] size(2 bits) ea mode register(3,3 bits); imm16 next word, imm8 lower order byte of next word, imm32 two next words + ADDI,SUBI + +0000 1000 01[10][11][00] ea mode register(3,3 bits); 0000 0000 bit number(8 bits) BCHG,BCLR,BSET,BTST + +0000 1100 size(2 bits) ea mode register(3,3 bits); imm16 next word, imm8 lower order byte of next word, imm32 two next words + CMPI + +0000 Dn reg(3 bits) 101[110][111][100] ea mode register(3,3 bits) BCHG,BCLR,BSET,BTST + +0000 Dn reg(3 bits) opmode(3 bits) 001 address reg(3 bits); 16 bit displacement MOVEP + +00 size(2 bits) ea dest register mode(3,3 bits) ea source mode register(3,3 bits) MOVE +00 size(2 bits) An dest(3 bits) 001 ea source mode register(3,3 bits) MOVEA + +if( 0000 000 0 ** !111100 ) ORI +if( 0000 000 0 00 111100 ) ORI to CCR +if( 0000 000 0 01 111100 ) ORI to SR +if( 0000 001 0 ** !111100 ) ANDI +if( 0000 001 0 00 111100 ) ANDI to CCR +if( 0000 001 0 01 111100 ) ANDI to SR +if( 0000 010 0 ) SUBI +if( 0000 011 0 ) ADDI +if( 0000 100 0 ) BCHG,BCLR,BSET,BTST +if( 0000 101 0 ** !111100 ) EORI +if( 0000 101 0 00 111100 ) EORI to CCR +if( 0000 101 0 01 111100 ) EORI to SR +if( 0000 110 0 ) CMPI +if( 0000 *** 1** !001 ) BCHG,BCLR,BSET,BTST +if( 0000 *** 1** 001 ) MOVEP +if( 00 !00 *** !001 ) MOVE +if( 00 !00 *** 001 ) MOVEA + +******************************************************************************************************************************************* + +0100 0000 size(2 bits) ea mode register(3,3 bits) NEGX +0100 0000 11 ea dest mode register(3,3 bits) MOVE FROM SR + +0100 Dn reg(3 bits) 1 10 ea mode register(3,3 bits) CHK +0100 An reg(3 bits) 1 11 ea mode register(3,3 bits) LEA + +0100 0010 size(2 bits) ea dest mode register(3,3 bits) CLR + +0100 0100 size(2 bits) ea mode register(3,3 bits) NEG +0100 0100 11 ea source mode register(3,3 bits) MOVE TO CCR + +0100 0110 size(2 bits) ea mode register(3,3 bits) NOT +0100 0110 11 ea source mode register(3,3 bits) MOVE TO SR + +0100 1000 00 ea mode register(3,3 bits) NBCD +0100 1000 01 000 reg(3 bits) SWAP +0100 1000 01 ea mode register(3,3 bits) PEA +0100 100 opmode(3 bits) 000 Dn dest(3 bits) EXT + +0100 1 dr(1 bit) 00 1 size(1 bit) ea mode register(3,3 bits); register list mask MOVEM + +0100 1010 size(2 bits) ea mode register(3,3 bits) TST +0100 1010 11 ea mode register(3,3 bits) TAS +0100 1010 1111 1100 ILLEGAL + +0100 1110 0100 vector(4 bits) TRAP + +0100 1110 0101 0 An reg(3 bits); 16 bit displacement LNK +0100 1110 0101 1 An reg(3 bits) UNLK + +0100 1110 0110 dr(1 bit) An reg(3 bits) MOVE USP + +0100 1110 0111 0000 RESET +0100 1110 0111 0001 NOP +0100 1110 0111 0010 STOP +0100 1110 0111 0011 RTE +0100 1110 0111 0101 RTS +0100 1110 0111 0110 TRAPV +0100 1110 0111 0111 RTR + +0100 1110 10 ea mode register(3,3 bits) JSR +0100 1110 11 ea mode register(3,3 bits) JMP + +if( 0100 0000 00|01|10 ) NEGX +if( 0100 0000 11 ) MOVE FROM SR +if( 0100 ***1 10 ) CHK +if( 0100 ***1 11 ) LEA +if( 0100 0010 ) CLR +if( 0100 0100 00|01|10 ) NEG +if( 0100 0100 11 ) MOVE TO CCR +if( 0100 0110 00|01|10 ) NOT +if( 0100 0110 11 ) MOVE TO SR +if( 0100 1000 00 ) NBCD +if( 0100 1000 01 000 ) SWAP +if( 0100 1000 01 !000 ) PEA +if( 0100 1000 1* 000 ) EXT +if( 0100 1*00 1* !000 ) MOVEM +if( 0100 1010 00|01|10 ) TST +if( 0100 1010 11 !111100 ) TAS +if( 0100 1010 11 111100 ) ILLEGAL +if( 0100 1110 0100 ) TRAP +if( 0100 1110 0101 0 ) LNK +if( 0100 1110 0101 1 ) ULNK +if( 0100 1110 0110 ) MOVE USP +if( 0100 1110 0111 0000 ) RESET +if( 0100 1110 0111 0001 ) NOP +if( 0100 1110 0111 0010 ) STOP +if( 0100 1110 0111 0011 ) RTE +if( 0100 1110 0111 0101 ) RTS +if( 0100 1110 0111 0110 ) TRAPV +if( 0100 1110 0111 0111 ) RTR +if( 0100 1110 10 ) JSR +if( 0100 1110 11 ) JMP + +******************************************************************************************************************************************* + +0101 data(3 bits) 0[1] size(2 bits) ea mode register (3,3 bits) ADDQ,SUBQ +0101 condition(4 bits) 11 ea mode register(3,3 bits) Scc +0101 condition(4 bits) 11 001 Dn register(3 bits); 16 bit displacement DBcc + +if( 0101 *** 0 !11 ) ADDQ +if( 0101 *** 1 !11 ) SUBQ +if( 0101 *** * 11 !001 ) Scc +if( 0101 *** * 11 001 ) DBcc + +******************************************************************************************************************************************* + +0110 0000 disp8(8 bit); 16 bit displacement if disp8 == 0 BRA +0110 0001 disp8(8 bit); 16 bit displacement if disp8 == 0 BSR +0110 condition(4 bits) disp8(8 bit); 16 bit displacement if disp8 == 0 Bcc + +if( 0110 0000 ) BRA +if( 0110 0001 ) BSR +if( 0110 !000 ) Bcc + +******************************************************************************************************************************************* + +0111 Dn dest(3 bits) 0 data(8 bits) MOVEQ + +******************************************************************************************************************************************* + +1011 register(3 bits) opmode(3 bits) ea mode register(3,3 bits) CMP + +1011 Dn source(3 bits) opmode(3 bits) ea mode register(3,3 bits) EOR +1011 Ax dest(3 bits) 1 size(2 bits) 001 Ay source(3 bits) CMPM + +1011 register(3 bits) opmode(3 bits) ea mode register(3,3 bits) CMPA + +if( 1011 *** 000|001|010 ) CMP +if( 1011 *** 100|101|110 001 ) CMPM +if( 1011 *** 100|101|110 !001 ) EOR +if( 1011 *** 011|111 ) CMPA + +******************************************************************************************************************************************* + +1000 Dn dest(3 bits) 1[0] 11 ea mode register(3,3 bits) DIVS,DIVU + +1100[1000] Ry dest(3 bits) 1 0000 R/M Rx source(3 bits) ABCD,SBCD +1100[1000] Dn register(3 bits) opmode(3 bits) ea mode register(3,3 bits) AND,OR + +1100 Rx reg(3 bits) 1 opmode(5 bits) Ry reg(3 bits) EXG +1100 Dn dest(3 bits) 1[0] 11 ea mode register(3,3 bits) MULS,MULU + +if( 1000 *** 011 ) DIVU +if( 1000 *** 111 ) DIVS +if( 1000 *** 10000 ) SBCD +if( 1000 *** 000**|001**|010**|10001|10010|10011|101**|110** ) OR + +if( 1100 *** 011 ) MULU +if( 1100 *** 111 ) MULS +if( 1100 *** 10000 ) ABCD +if( 1100 *** 000**|001**|010**|10001|10010|10011|10101|10110|10111|11001|11010|11011 ) AND +if( 1100 *** 10100|11000 ) EXG + +******************************************************************************************************************************************* + +1101[1001] register(3 bits) opmode(3 bits) ea mode register (3,3 bits) ADD,SUB +1101[1001] register(3 bits) opmode(3 bits) ea mode register(3,3 bits) ADDA,SUBA +1101[1001] Ry dest(3 bits) 1 size(2 bits) 00 R/M Rx source(3 bits) ADDX,SUBX + +if( 1001 *** 000|001|010|10001|10010|10011|10101|10110|10111|11001|11010|11011 ) SUB +if( 1001 *** 011|111 ) SUBA +if( 1001 *** 10000|10100|11000 ) SUBX +if( 1101 *** 000|001|010|10001|10010|10011|10101|10110|10111|11001|11010|11011 ) ADD +if( 1101 *** 011|111 ) ADDA +if( 1101 *** 10000|10100|11000) ADDX + +******************************************************************************************************************************************* + +1110 count/register(3 bits) dr(1 bit) size(2 bits) i/r(1 bit) 00[01][11][10] Dn dest(3 bit) ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR +1110 000[001][011][010] dr(1 bit) 11 ea mode register(3,3 bits) ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR + +if( 1110 *** * !11 ) ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR +if( 1110 *** * 11 ) ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR + +******************************************************************************************************************************************* + +microcode +instruction: XXXX *** XXX + +0000 *** 000 ORI,ORI to CCR,ANDI,ANDI to CCR,SUBI,ADDI,BCHG,BCLR,BSET,BTST,EORI,EORI to CCR,CMPI +0000 *** 001 ORI,ORI to SR,ANDI,ANDI to SR,SUBI,ADDI,BCHG,BCLR,BSET,BTST,EORI,EORI to SR,CMPI +0000 *** 010 ORI,ANDI,SUBI,ADDI,BCHG,BCLR,BSET,BTST,EORI,CMPI +0000 *** 011 ORI,ANDI,SUBI,ADDI,BCHG,BCLR,BSET,BTST,EORI,CMPI +0000 *** 100 BCHG,BCLR,BSET,BTST,MOVEP +0000 *** 101 BCHG,BCLR,BSET,BTST,MOVEP +0000 *** 110 BCHG,BCLR,BSET,BTST,MOVEP +0000 *** 111 BCHG,BCLR,BSET,BTST,MOVEP + +0001 *** 000 MOVE +0001 *** 001 MOVEA +0001 *** 010 MOVE +0001 *** 011 MOVE +0001 *** 100 MOVE +0001 *** 101 MOVE +0001 *** 110 MOVE +0001 *** 111 MOVE + +0010 *** 000 MOVE +0010 *** 001 MOVEA +0010 *** 010 MOVE +0010 *** 011 MOVE +0010 *** 100 MOVE +0010 *** 101 MOVE +0010 *** 110 MOVE +0010 *** 111 MOVE + +0011 *** 000 MOVE +0011 *** 001 MOVEA +0011 *** 010 MOVE +0011 *** 011 MOVE +0011 *** 100 MOVE +0011 *** 101 MOVE +0011 *** 110 MOVE +0011 *** 111 MOVE + +0100 *** 000 NEGX,CLR,NEG,NOT,NBCD,TST +0100 *** 001 NEGX,CLR,NEG,NOT,SWAP,PEA,TST,TRAP,LNK,ULNK,MOVE USP,RESET,NOP,STOP,RTE,RTS,TRAPV,RTR +0100 *** 010 NEGX,CLR,NEG,NOT,EXT,MOVEM,TST,JSR +0100 *** 011 MOVE FROM SR,CLR,MOVE TO CCR,MOVE TO SR,EXT,MOVEM,TAS,ILLEGAL,JMP +0100 *** 100 invalid +0100 *** 101 invalid +0100 *** 110 CHK +0100 *** 111 LEA + +0101 *** 000 ADDQ +0101 *** 001 ADDQ +0101 *** 010 ADDQ +0101 *** 011 Scc,DBcc +0101 *** 100 SUBQ +0101 *** 101 SUBQ +0101 *** 110 SUBQ +0101 *** 111 Scc,DBcc + +0110 *** 000 BRA,Bcc +0110 *** 001 BRA,Bcc +0110 *** 010 BRA,Bcc +0110 *** 011 BRA,Bcc +0110 *** 100 BSR,Bcc +0110 *** 101 BSR,Bcc +0110 *** 110 BSR,Bcc +0110 *** 111 BSR,Bcc + +0111 *** 000 MOVEQ +0111 *** 001 MOVEQ +0111 *** 010 MOVEQ +0111 *** 011 MOVEQ +0111 *** 100 invalid +0111 *** 101 invalid +0111 *** 110 invalid +0111 *** 111 invalid + +1000 *** 000 OR +1000 *** 001 OR +1000 *** 010 OR +1000 *** 011 DIVU +1000 *** 100 SBCD,OR +1000 *** 101 OR +1000 *** 110 OR +1000 *** 111 DIVS + +1001 *** 000 SUB +1001 *** 001 SUB +1001 *** 010 SUB +1001 *** 011 SUBA +1001 *** 100 SUB,SUBX +1001 *** 101 SUB,SUBX +1001 *** 110 SUB,SUBX +1001 *** 111 SUBA + +1010 *** 000 invalid +1010 *** 001 invalid +1010 *** 010 invalid +1010 *** 011 invalid +1010 *** 100 invalid +1010 *** 101 invalid +1010 *** 110 invalid +1010 *** 111 invalid + +1011 *** 000 CMP +1011 *** 001 CMP +1011 *** 010 CMP +1011 *** 011 CMPA +1011 *** 100 CMPM,EOR +1011 *** 101 CMPM,EOR +1011 *** 110 CMPM,EOR +1011 *** 111 CMPA + +1100 *** 000 AND +1100 *** 001 AND +1100 *** 010 AND +1100 *** 011 MULU +1100 *** 100 ABCD,AND +1100 *** 101 EXG,AND +1100 *** 110 EXG,AND +1100 *** 111 MULS + +1101 *** 000 ADD +1101 *** 001 ADD +1101 *** 010 ADD +1101 *** 011 ADDA +1101 *** 100 ADD,ADDX +1101 *** 101 ADD,ADDX +1101 *** 110 ADD,ADDX +1101 *** 111 ADDA + +1110 *** 000 ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR reg +1110 *** 001 ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR reg +1110 *** 010 ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR reg +1110 *** 011 ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR ea +1110 *** 100 ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR reg +1110 *** 101 ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR reg +1110 *** 110 ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR reg +1110 *** 111 ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR ea + +1111 *** 000 invalid +1111 *** 001 invalid +1111 *** 010 invalid +1111 *** 011 invalid +1111 *** 100 invalid +1111 *** 101 invalid +1111 *** 110 invalid +1111 *** 111 invalid + +>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> +Original MC68000 Ports: + +Address bus: A23-A1, output +Data bus: D15-D0, bidirectional + +Address Strobe: output +Read/Write: 0 - write, 1 - read +Upper and Lower data strobes: output + +Data transfer acknowlege: input + +A,D,AS,R/W,UDS,LDS: all tri-state + +BERR: input +BERR: perform exception handling, while BERR asserted wait in Hi-Z +BERR + HALT: retry bus cycle, HALT longer than BERR for at least 1 clock cycle, while HALT asserted wait in Hi-Z, + not for read-modify-write, retry count not limited + + +FC[2:0]: valid with Address Strobe + 0 - undefined + 1 - user data + 2 - user program + 3 - undefined + 4 - undefined + 5 - supervisor data : all exception vector entries except reset + 6 - supervisor program : exception vector for reset + 7 - cpu space : interrupt acknowlege bus cycle + +interrupt IPL[2:0]: + assert IPL until processor signals interrupt acknowlege +interrupt acknowlege bus cycle: + FC: 7 + A23-A4: high, A3-A1: interrupt number output + D15-D8 ignored, D7-D0 + DACK: vector number + input VPA: autovector, complete 6800 read cycle: assert VMA + input BERR: spurious interrupt + +HALT, RESET: inout +input HALT + RESET: processor reset +output RESET: RESET opcode: reset external devices +output HALT: processor blocked +input HALT: stop bus activity after current bus cycle, Hi-Z all three-state lines, bus arbitration as usual + + +bus request: input, at any time +bus grant: output, bus is to be released after current cycle +bus grant acknowlege: input, bus in use by external device + +E: clock: output, 6 clocks low, 4 clocks high +Valid Peripheral Address: input, use autovector in interrupt acknowlege cycle, device is 6800 type: synchronize data on E +Valid Memory Address: output, memory address valid and processor synchronized on E + +>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> +Backup +>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> + +//----- flip_flop_registers +//ir1,ir2: +// required by: ANDI,EORI,ORI,ANDI to CCR,EORI to CCR,ORI to CCR,ANDI to SR,EORI to SR,ORI to SR,ADDI,SUBI + Index: trunk/doc/src/openoffice_macro.txt =================================================================== --- trunk/doc/src/openoffice_macro.txt (nonexistent) +++ trunk/doc/src/openoffice_macro.txt (revision 2) @@ -0,0 +1,27 @@ +REM ***** BASIC ***** + +Sub Main(srcUrl as String, destUrl as String, search as String, replaceUrl as String, doClose as Boolean) +Dim Doc As Object +Dim SearchDesc As Object +Dim Str As String +Dim Found As Object +Dim aOptions() As Object + +Doc = StarDesktop.loadComponentFromURL(srcUrl, "_blank", 0, aOptions) +SearchDesc = Doc.createSearchDescriptor + + +SearchDesc.SearchString = search + +Found = Doc.findFirst(SearchDesc) + +Found.insertDocumentFromURL( replaceUrl, aOptions ) + +Doc.storeAsURL(destUrl, aOptions) + +if(doClose) then +Doc.close(True) +endif + +End Sub + Index: trunk/doc/src/documentation.v =================================================================== --- trunk/doc/src/documentation.v (nonexistent) +++ trunk/doc/src/documentation.v (revision 2) @@ -0,0 +1,579 @@ +/* + * Copyright 2010, Aleksander Osman, alfik@poczta.fm. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, are + * permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND + * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* This file contains only Doxygen documentation. +*/ + +/*! \file documentation.v + * \brief ao68000 Doxygen documentation. + */ + +/*! \mainpage + *

+ * OpenCores ao68000 IP Core. + * \author Aleksander Osman, + * \date 28.03.2010 + * \version 1.0 + *

+ * \image html ./doc/img/opencores.jpg + *

+ * + *

+ * Contents: + * - Specification, automatically generated from: + * - \subpage page_spec_revisions, + * - \subpage page_spec_introduction, + * - \subpage page_spec_architecture, + * - \subpage page_spec_operation, + * - \subpage page_spec_registers, + * - \subpage page_spec_clocks, + * - \subpage page_spec_ports, + * - \subpage page_spec_references. + * - \subpage page_directory, + * - \subpage page_tool, + * - \subpage page_verification, + * - \subpage page_mc68000, + * - \subpage page_old_notes, + * - \subpage page_microcode_compilation, + * - \subpage page_microcode_operations, + * - \subpage page_microcode, + * - \subpage page_soc_linux. + *

+ * \image html ./doc/img/wishbone_compatible.png + *

+ * + * Structure Diagram: + * \image html structure.png + */ + + +/*! \page page_spec_introduction Introduction + * + * The OpenCores ao68000 IP Core is a Motorola MC68000 compatible processor. + * + *

Features

+ * - CISC processor with microcode, + * - WISHBONE revision B.3 compatible MASTER interface, + * - not cycle exact with the MC68000, some instructions take more cycles to complete, some less, + * - Uses about 7500 LE on Altera Cyclone II and about 45000 bits of RAM for microcode, + * - Tested against the WinUAE M68000 software emulator. Every 16-bit instruction was tested with random register contents and RAM contents + * (\ref page_verification). The result of execution was compared, + * - Runs Linux kernel version 2.6.33.1 up to init process lookup (\ref page_soc_linux), + * - Contains a simple prefetch which is capable of holding up to 5 16-bit instruction words, + * - Document generated by Doxygen (www.doxygen.org) with doxverilog patch (http://developer.berlios.de/projects/doxverilog/). The specification + * is automatically extracted from the Doxygen HTML output. + * + *

WISHBONE compatibility

+ * - Version: WISHBONE specification Revision B.3, + * - General description: 32-bit WISHBONE Master interface, + * - WISHBONE signals described in \ref page_spec_ports, + * - Supported cycles: Master Read/Write, Master Block Read/Write, Master Read-Modify-Write for TAS instruction, + * Register Feedback Bus Cycles as described in chapter 4 of the WISHBONE specification, + * - Use of ERR_I: on memory access – bus error, on interrupt acknowledge: spurious interrupt, + * - Use of RTY_I: on memory access – repeat access, on interrupt acknowledge: generate auto-vector, + * - WISHBONE data port size: 32-bit, + * - Data port granularity: 8-bits, + * - Data port maximum operand size: 32-bits, + * - Data transfer ordering: BIG ENDIAN, + * - Data transfer sequencing: UNDEFINED, + * - Constraints on CLK_I signal: described in \ref page_spec_clocks, maximum frequency: about 70 MHz. + * + *

Use

+ * The ao68000 can be used as an processor in a System-on-Chip booting Linux kernel up to init program lookup (\ref page_soc_linux). + * + *

Similar projects

+ * Other free soft-core implementations of M68000 microprocessor include: + * - OpenCores TG68 (http://www.opencores.org/project,tg68) - runs Amiga software, used as part of the Minimig Core, + * - Suska Atari VHDL WF_68K00_IP Core (http://www.experiment-s.de/en) - runs Atari software, + * - OpenCores K68 (http://www.opencores.org/project,k68) - no user and supervisor modes distinction, executes most instructions, but not all. + * - OpenCores ae68 (http://www.opencores.org/project,ae68) - no files uploaded as of 27.03.2010. + * + *

Limitations

+ * - microcode not optimized: some instructions take more cycles to execute than the original MC68000, + * - TRACE not tested, + * - the core is large compared to other implementations. + * + *

TODO

+ * - optimize the microcode and count the exact cycle count for every instruction, + * - test TRACE, + * - run WISHBONE verification models, + * - more documentation of the ao68000 module: signal description, operation, FSM in bus_control, + * - describe changes done in WinUAE sources (copy from ao.c), + * - describe microcode words and subprocedures, + * - document the full_system modules, + * - prepare scripts for VATS: run_sim -r -> regresion test, + * - use memories from OpenCore common. + * + *

Status

+ * - Tested with WinUAE software MC68000 emulator, + * - Booted Linux kernel up to init process lookup. + * + *

Requirements

+ * - Icarus Verilog simulator (http://www.icarus.com/eda/verilog/) is required to compile the tb_ao68000 testbench, + * - Access to Altera Quartus II instalation directory (directory eda/sim_lib/) is required to compile the tb_ao68000 testbench, + * - GCC (http://gcc.gnu.org) is required to compile the WinUAE MC68000 software emulator, + * - Java runtime (http://java.sun.com) is required to run the ao68000_tool (\ref page_tool), + * - Java SDK (http://java.sun.com) is required to compile the ao68000_tool (\ref page_tool), + * - Apache Ant (http://ant.apache.org) is required to compile the ao68000_tool (\ref page_tool), + * - Altera Quartus II synthesis tool (http://www.altera.com) is required to synthesise the full_system System-on-Chip + * (\ref page_soc_linux). + * + *

Glossary

+ * - ao68000 - the ao68000 IP Core processor, + * - MC68000 - the original Motorola MC68000 processor. + */ + +/*! \page page_spec_revisions Revision History + * + * + * + * + *

Rev.	Date	Author	Description
1.0	28.03.2010	Aleksander Osman	First Draft

+ */ + +/*! \page page_directory Directory structure + * The ao68000 project consists of the following directories: + * + * \verbinclude ./doc/src/directory.txt + */ + +/*! \page page_verification Processor verification + * The ao68000 IP Core is verified with the WinUAE MC68000 software emulator. + * The verification is based on the idea that given the same contents of: + * - every register in the processor, + * - all memory locations that are read during execution, + * + * the result of execution, that is the contents of: + * - every register in the processor, + * - all memory locations written during execution, + * + * should be the same for the IP Core and the software emulator. + * + *

Verification procedure

+ * The verification is performed in the following way: + * - the WinUAE MC68000 software emulator is compiled. The sources of the emulator are located at: ./bench/sw_emulators/winuae/. + * The makefile with instructions to compile the emulator are located at: ./sim/sw_emulators/bin/Makefile. + * The compiled binary is located at: ./sim/sw_emulators/run/winuae/ao. + * - the ao68000 testbench is compiled. The sources of the testbench are located at: ./bench/verilog/tb_ao68000/. + * The makefile with instructions to compile the testbench are located at: ./sim/rtl_sim/bin/Makefile. + * The compiled Icarus Verilog script is located at: ./sim/rtl_sim/run/tb_ao68000/tb_ao68000. + * - Both of the above executable programs accept arguments that specify the values of: + * - memory locations that are read during execution, + * - the contents of every register in the processor. + * - The result of executing both of the programs is the contents of: + * - memory locations written during execution, + * - the contents of every register in the processor after execution. + * - The tool ./sw/ao68000_tool/dist/ao68000_tool.jar (\ref page_tool) is used to run both of the executable programs and + * compare the result of execution. The tool is capable of executing multiple concurrent simulations in order to utilize current + * multicore processors. The makefile containing instructions to run the tool is located in: ./sim/rtl_sw_compare/bin/Makefile. + * + *

Requirements

+ * - Icarus Verilog simulator (http://www.icarus.com/eda/verilog/) is required to compile the tb_ao68000 testbench, + * - Access to Altera Quartus II instalation (directory eda/sim_lib/) is required to compile the tb_ao68000 testbench, + * - GCC (http://gcc.gnu.org) is required to compile the WinUAE MC68000 software emulator, + * - Java runtime (http://java.sun.com) is required to run the ao68000_tool (\ref page_tool). + */ +/*! \page page_tool ao68000_tool documentation + * + * The ao68000_tool is used to: + * - generate a microcode operations Java file, which contains all available microcode operations (\ref page_microcode_operations): + * ./sw/ao68000_tool/src/ao68000_tool/Parser.java. It is generated from ./rtl/verilog/ao68000/microcode_params.v, + * - generate microcode for ao680000 (\ref page_microcode_compilation) with microcode locations. The microcode + * is generated and stored into an Altera MIF format file located at: + * ./sw/ao68000_tool/microcode.mif. The microcode locations are + * save at:./rtl/verilog/ao68000/microcode/microcode_locations.v, + * - run and compare the results of ao68000 RTL simulation of + * ao68000/sim/rtl_sim/run/tb_ao68000/tb_ao68000 with the software MC68000 + * emulation of ao68000/sim/sw_emulators/winuae/ao (\ref page_verification), + * - extract the specification contents from Doxygen HTML output, to generate the specification ODT file. + * + * The tool is located at: ./sw/ao68000_tool/dist/ao68000_tool.jar. The makefile containing instructions to compile + * the tool is available at: ./sw/ao68000_tool/Makefile. To recompile the tool, ant (http://ant.apache.org) is required. + */ + +/*! \page page_mc68000 MC68000 notes + * \verbinclude ./doc/src/mc68000.txt + */ + +/*! \page page_old_notes Old ao68000 notes + * \verbinclude ./doc/src/old_notes.txt + */ + +/*! \page page_microcode_compilation Microcode compilation + * The ao68000 microcode is represented as an Java program. Execution of this program results in generating the binary + * microcode. + * + *

Microcode operations

+ * All possible microcode operations are described in microcode_params.v. + * The locations of: + * - each operation in the microcode word, + * - every procedure in the microcode + * + * are defined in the auto-generated microcode_locations.v file. All the available operation are also represented as Java functions and + * saved in an auto-generated file, located at ./sw/ao68000_tool/src/ao68000_tool/Parser.java (\ref page_microcode_operations). + * These two auto-generated files are generated by the tool ao68000_tool.jar (\ref page_tool). + * + *

Microcode compilation

+ * The source for the microcode is located at ./sw/ao68000_tool/src/ao68000_tool/Microcode.java (\ref page_microcode). + * + * The compiled microcode, in Altera MIF format, is located at ./rtl/verilog/ao68000/microcode/microcode.mif. + * + * The tool ao68000_tool.jar (\ref page_tool) is used to compile the microcode source and transform it into a MIF file. + * The makefile containing instructions for performing the compilation is located at ./sw/ao68000_tool/Makefile. + */ + + +/*! \page page_microcode_operations Microcode operations + * The listing below represents operations available in the \ref page_microcode. It is taken from: + * ./sw/ao68000_tool/src/ao68000_tool/Parser.java. More information about the microcode structure and compilation is available at + * \ref page_microcode_compilation. + * + * \include ./sw/ao68000_tool/src/ao68000_tool/Parser.java + */ + +/*! \page page_microcode Microcode + * The listing below represents the microcode. + * It is taken from ./sw/ao68000_tool/src/ao68000_tool/Microcode.java. More information about the microcode structure and + * compilation is available at \ref page_microcode_compilation. + * + * \include ./sw/ao68000_tool/src/ao68000_tool/Microcode.java + */ + +/*! \page page_spec_architecture Architecture + * + *

+ * **Figure 1:** Simplified block diagram of ao68000 top module. + *
+ * \image html ./doc/img/architecture.png + *

+ *

ao68000

+ * \copydoc ao68000 + * + *

bus_control

+ * \copydoc bus_control + * + *

registers

+ * \copydoc registers + * + *

memory_registers

+ * \copydoc memory_registers + * + *

decoder

+ * \copydoc decoder + * + *

condition

+ * \copydoc condition + * + *

alu

+ * \copydoc alu + * + *

microcode_branch

+ * \copydoc microcode_branch + */ + +/*! \page page_spec_operation Operation + * The ao68000 IP Core is designed to operate in a similar way as the original MC68000. The most import differences are: + * - the core IO ports are compatible with the WISHBONE specification, + * - the execution of instructions in the ao68000 core is not cycle-exact with the original MC68000 and usually takes a few cycles longer. + * + *

Setting up the core

+ * The ao68000 IP Core has an WISHBONE MASTER interface. All standard memory access bus cycles conform to the WISHBONE specification. + * These cycles include: + * - instruction fetch, + * - data read, + * - data write. + * + * The cycles are either Single, Block or Read-Modify-Write (for the TAS instruction). When waiting to finish a bus cycle + * the ao68000 reacts on the following input signals: + * - ACK_I: the cycle is completed successfully, + * - RTY_I: the cycle is immediately repeated, the processor does not continue its operation before the current bus cycle is finished. + * In case of the Read-Modify-Write cycle - only the current bus cycle is repeated: either the read or write. + * - ERR_I: the cycle is terminated and a bus error is processed. In case of double bus error the processor enters the blocked state. + * + * There is also a special bus cycle: the interrupt acknowledge cycle. This cycle is a reaction on receiving a external interrupt from + * the ipl_i inputs. The processor only samples the ipl_i lines after processing an instruction, so the interrupt lines have to be asserted + * for some time before the core reacts. The interrupt acknowledge cycle is performed in the following way: + * - ADR_O is set to { 27'b111_1111_1111_1111_1111_1111_1111, 3 bits indicating the interrupt priority level for this cycle }, + * - SEL_O is set to 4'b1111, + * - fc_o is set to 3'b111 to indicate a CPU Cycle as in the original MC68000. + * + * The ao68000 reacts on the following signals when waiting to finish a interrupt acknowledge bus cycle: + * - ACK_I: the cycle is completed successfully and the interrupt vector is read from DAT_I[7:0], + * - RTY_I: the cycle is completed successfully and the processor generates a auto-vector internally, + * - ERR_I: the cycle is terminated and the processor starts processing a spurious interrupt exception. + * + * Every bus cycle is supplemented with output tags: + * - WISHBONE standard tags: SGL_O, BLK_O, RMW_O, CTI_O, BTE_O, + * - ao68000 custom tag: fc_o that operates like the Function Code of the original MC68000. + * + * The ao68000 core has two additional outputs that are used to indicate the state of the processor: + * - reset_o is a external device reset signal. It is asserted when processing the RESET instruction. It is asserted for 124 bus cycles. + * After that the processor returns to normal instruction processing. + * - blocked_o is an output that indicates that the processor is blocked after a double bus error. When this output line is asserted + * the processor is blocked and does not process any instructions. The only way to continue processing instructions is to reset + * the core. + * + *

Resetting the core

+ * The ao68000 core is reset with a standard synchronous WISHBONE RST_I input. One clock cycle with RST_I asserted is enough to reset + * the core. After deasserting the signal, the core starts its standard startup sequence, which is similar to the one performed + * by the original MC68000: + * - the value of the SSP register is read from address 0, + * - the value of the PC is read from address 1. + * + * An identical sequence is performed when powering up the core for the first time. + * + *

Processor modes

+ * The ao68000 core has two modes of operation - exactly like the original MC68000: + * - Supervisor mode + * - User mode. + * + * Performing a privileged instruction when running in user mode results in a privilege exception, just like in MC68000. + * + *

Processor states

+ * The ao68000 core can be in one of the following states: + * - instruction processing, which includes group 2 exception processing, + * - group 0 and group 1 exception processing, + * - external device reset state when processing the RESET instruction, + * - blocked state after a double bus error. + */ + +/*! \page page_spec_registers Registers + * The ao68000 IP Core is a WISHBONE Master and does not contain any registers available for reading or writing from outside of the core. + */ + +/*! \page page_spec_clocks Clocks + * + * + * + * + * + * + * + * + *

**Table 1:** List of clocks.
Name	Source	Rates (MHz)			Remarks	Description
		Max	Min	Resolution
CLK_I	Input Port	70	-	-	-	System clock.

+ */ + +/*! \page page_spec_ports IO Ports + *

WISHBONE IO Ports

+ * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *

**Table 1:** List of WISHBONE IO ports.
Port	Width	Direction	Description
CLK_I	1	Input	\copydoc CLK_I
RST_I	1	Input	\copydoc RST_I
CYC_O	1	Output	\copydoc CYC_O
ADR_O	30	Output	\copydoc ADR_O
DAT_O	32	Output	\copydoc DAT_O
DAT_I	32	Input	\copydoc DAT_I
SEL_O	4	Output	\copydoc SEL_O
STB_O	1	Output	\copydoc STB_O
WE_O	1	Output	\copydoc WE_O
ACK_I	1	Input	\copydoc ACK_I
ERR_I	1	Input	\copydoc ERR_I
RTY_I	1	Input	\copydoc RTY_I
SGL_O	1	Output	\copydoc SGL_O
BLK_O	1	Output	\copydoc BLK_O
RMW_O	1	Output	\copydoc RMW_O
CTI_O	3	Output	\copydoc CTI_O
BTE_O	2	Output	\copydoc BTE_O
fc_o	3	Output	\copydoc fc_o

+ * + *

Other IO Ports

+ * + * + * + * + * + * + * + *

**Table 2:** List of Other IO ports.
Port	Width	Direction	Description
ipl_i	3	Input	\copydoc ipl_i
reset_o	1	Output	\copydoc reset_o
blocked_o	1	Output	\copydoc blocked_o

+ */ + +/*! \addtogroup CLK_I CLK_I Port + * WISHBONE Clock Input + */ +/*! \addtogroup RST_I RST_I Port + * WISHBONE Reset Input + */ +/*! \addtogroup CYC_O CYC_O Port + * WISHBONE Master Cycle Output + */ +/*! \addtogroup ADR_O ADR_O Port + * WISHBONE Master Address Output + */ +/*! \addtogroup DAT_O DAT_O Port + * WISHBONE Master Data Output + */ +/*! \addtogroup DAT_I DAT_I Port + * WISHBONE Master Data Input + */ +/*! \addtogroup SEL_O SEL_O Port + * WISHBONE Master Byte Select + */ +/*! \addtogroup STB_O STB_O Port + * WISHBONE Master Strobe Output + */ +/*! \addtogroup WE_O WE_O Port + * WISHBONE Master Write Enable Output + */ +/*! \addtogroup ACK_I ACK_I Port + * WISHBONE Master Acknowledge Input: + * - on normal cycle: acknowledge, + * - on interrupt acknowledge cycle: external vector provided on DAT_I[7:0]. + */ +/*! \addtogroup ERR_I ERR_I Port + * WISHBONE Master Error Input + * - on normal cycle: bus error, + * - on interrupt acknowledge cycle: spurious interrupt. + */ +/*! \addtogroup RTY_I RTY_I Port + * WISHBONE Master Retry Input + * - on normal cycle: retry bus cycle, + * - on interrupt acknowledge: use auto-vector. + */ +/*! \addtogroup SGL_O SGL_O Port + * WISHBONE Cycle Tag, TAG_TYPE: TGC_O, Single Bus Cycle. + */ +/*! \addtogroup BLK_O BLK_O Port + * WISHBONE Cycle Tag, TAG_TYPE: TGC_O, Block Bus Cycle. + */ +/*! \addtogroup RMW_O RMW_O Port + * WISHBONE Cycle Tag, TAG_TYPE: TGC_O, Read-Modify-Write Cycle. + */ +/*! \addtogroup CTI_O CTI_O Port + * WISHBONE Address Tag, TAG_TYPE: TGA_O, Cycle Type Identifier, + * Incrementing Bus Cycle or End-of-Burst Cycle. + */ +/*! \addtogroup BTE_O BTE_O Port + * WISHBONE Address Tag, TAG_TYPE: TGA_O, Burst Type Extension, + * always Linear Burst. + */ +/*! \addtogroup fc_o fc_o Port + * Custom TAG_TYPE: TGC_O, Cycle Tag, + * Processor Function Code: + * - 1 - user data, + * - 2 - user program, + * - 5 - supervisor data : all exception vector entries except reset, + * - 6 - supervisor program : exception vector for reset, + * - 7 - cpu space: interrupt acknowledge. + */ +/*! \addtogroup ipl_i ipl_i Port + * Interrupt Priority Level + * Interrupt acknowledge cycle: + * - ACK_I: interrupt vector on DAT_I[7:0], + * - ERR_I: spurious interrupt, + * - RTY_I: auto-vector. + */ +/*! \addtogroup reset_o reset_o Port + * External device reset. Output high when processing the RESET instruction. + */ +/*! \addtogroup blocked_o blocked_o Port + * Processor blocked indicator. The processor is blocked after a double bus error. + */ + +/*! \page page_spec_references References + *

+ * Specification for the: WISHBONE System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores.
+ * Revision: B.3.
+ * Released: September 7, 2002.
+ * Available from: http://www.opencores.org.
+ *
+ * M68000 8-/16-/32-Bit Microprocessors User’s Manual.
+ * Ninth Edition.
+ * Freescale Semiconductor, Inc.
+ * Available from: http://www.freescale.com.
+ *
+ * MOTOROLA M68000 FAMILY Programmer’s Reference Manual (Includes CPU32 Instructions).
+ * MOTOROLA INC., 1992. M68000PM/AD REV.1.
+ * Available form: http://www.freescale.com.
+ *
+ * ao68000 Doxygen(Design) Documentation.
+ *

+ */ + +/*! \page page_soc_linux System-on-Chip example with ao68000 running Linux + * The ao68000 IP Core is capable of booting the Linux kernel (http://www.kernel.org) up to the init program search. + * + *

Requirements

+ * - Linux kernel sources (http://www.kernel.org), tested with version 2.6.33.1, + * - a MC68000 toolchain (http://www.gnu.org), tested with binutils-2.20 and gcc-core-4.4.3, + * - a development board to run the system, tested with Terasic DE2-70 board (http://www.terasic.com.tw), + * - a SDHC card, + * - a serial cable to view the output of kernel execution on a serial terminal program. + * + *

System-on-Chip

+ * In order to test the ao68000 processor by booting the Linux kernel, a System-on-Chip is prepared and located at: + * ./rtl/verilog/full_system/. The system consists of: + * - an early boot state machine: early_boot.v, + * - a SDHC card controller: sd.v, + * - a serial line transmitter: serial_txd.v, + * - a SSRAM controller: ssram.v, + * - a simple timer: timer.v, + * - a top level module, that instantiates the above modules and the ao68000 processor: full_system.v. + * + *

Step-by-step instruction to prepare the system

+ * - download the Linux kernel (linux-2.6.33.1.tar.bz2), + * - download the toolchain (binutils-2.20.tar.bz2, gcc-core-4.4.3.tar.bz2), + * - configure and make Binutils:
+ * ./configure --prefix=(build prefix) --target=m68knommu-none-linux
+ * make
+ * make install
+ * - configure and make GCC: + *

./../gcc-4.4.3/configure --prefix=(build prefix) --target=m68knommu-none-linux








    + *          --disable-threads --disable-shared --disable-libmudflap --disable-libssp --disable-libiberty --disable-zlib --disable-libgomp

+ *
+ * make
+ * make install
+ * - patch the Linux kernel sources by copying the contents of the directory ./sw/linux/linux-2.6.33.1-ao68000/ into the Linux kernel + * sources directory, + * - configure and make the Linux kernel:
+ * make menuconfig ARCH=m68knommu CROSS_COMPILE=(build prefix)/bin/m68knommu-none-linux-
+ * make ARCH=m68knommu CROSS_COMPILE=(build prefix)/bin/m68knommu-none-linux-
+ * - convert the Linux kernel binary in ELF format into a flat binary format: + * (build prefix)//bin/m68knommu-none-linux-objcopy -O binary vmlinux vmlinux.bin
+ * - synthesise the full_system with the Altera Quartus II tool. The instructions to perform the synthesis are located in the makefile + * located at: ./syn/altera/bin/Makefile, + * - prepare a SDHC card with the software: + * - copy the first 8 bytes of memory form the file ./sw/linux/sector0.dat:
+ * dd if=sector0.dat of=/dev/(SD card device) + * This file contains the SSP and PC values read by the ao68000 processor after booting. + * - copy the Linux kernel flat binary, at offset 1024:
+ * dd if=vmlinux.bin of=/dev/(SD card device) bs=1024 seek=1
+ * - insert the SDHC card into the reader in the Terasic DE2-70 board, + * - load the synthesised SOF file into the FPGA + * - look at the output of the kernel console by opening a serial terminal application and reading the output of the board. + * + *

Notes

+ * - the SLOB allocator and not the default SLAB allocator had to be selected because of a problem in the kernel sources + * (in_interrupt() check in ./kernel/slab.c:2109 before enabling the interrupts), + * - the source file in the Linux kernel: ./init/initramfs.c compiled with the GCC option -m68000 contains illegal code + * to execute on a MC68000 (copy a long word from an unaligned address). Even after correcting this problem, the kernel did not want to boot + * reliably (sometimes it booted and found the init program, sometimes not). + * + *

Linux console output

+ * The output of the running kernel is presented below: + * \verbinclude ./doc/src/linux_booting.txt + */ + Index: trunk/doc/src/linux_booting.txt =================================================================== --- trunk/doc/src/linux_booting.txt (nonexistent) +++ trunk/doc/src/linux_booting.txt (revision 2) @@ -0,0 +1,34 @@ +Linux version 2.6.33.1 (alek@gesserit) (gcc version 4.4.3 (GCC) ) #11 Sun Mar 21 + 13:47:14 CET 2010 + +AO68000 support Aleksander Osman + +uClinux/AO68000 + +Flat model support (C) 1998,1999 Kenneth Albanowski, D. Jeff Dionne +Built 1 zonelists in Zone order, mobility grouping off. Total pages: 254 +Kernel command line: +PID hash table entries: 16 (order: -6, 64 bytes) +Dentry cache hash table entries: 1024 (order: 0, 4096 bytes) +Inode-cache hash table entries: 1024 (order: 0, 4096 bytes) +Memory available: 400k/1024k RAM, (492k kernel code, 74k data) +Hierarchical RCU implementation. +RCU-based detection of stalled CPUs is enabled. +NR_IRQS:32 +console [ttyDE20] enabled +Calibrating delay loop... 6.55 BogoMIPS (lpj=32768) +Mount-cache hash table entries: 512 +Switching to clocksource jiffies +Freeing unused kernel memory: 20k freed (0x81000 - 0x85000) +Warning: unable to open an initial console. +Kernel panic - not syncing: No init found. Try passing init= option to kernel. +Stack from 000c6f9a: + 000c6fca 0007272a 00077560 00087332 00087332 00000400 000765f6 000c6fd6 + 00000001 00080fb8 00000698 000765ee 00080ff8 00000752 000765f6 000765ee + 000765e4 000765da 000765cf 0008691c 000811f8 00000b00 000862d4 00000dc2 + 00000000 + +Call Trace with CONFIG_FRAME_POINTER disabled: + [0007272a] [00077560] [00000400] [000765f6] [00000698] + [000765ee] [00000752] [000765f6] [000765ee] [000765e4] + [000765da] [000765cf] [000811f8] [00000b00] [00000dc2] Index: trunk/doc/specification.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/specification.pdf =================================================================== --- trunk/doc/specification.pdf (nonexistent) +++ trunk/doc/specification.pdf (revision 2)

trunk/doc/specification.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/doc/README.txt =================================================================== --- trunk/doc/README.txt (nonexistent) +++ trunk/doc/README.txt (revision 2) @@ -0,0 +1,13 @@ +The ao68000 core documentation is generated by the Doxygen tool +(www.doxygen.org) with the doxverilog patch +(http://developer.berlios.de/projects/doxverilog/). + +A generated copy of the documentation is included. Because of its size, it is +stored in an compressed archive: doxygen_generated.tar.gz. + +To decompress it type: +make unpack + +To open the documentation, open the file: +./doxygen/html/index.html +in a browser. Index: trunk/doc/doxygen.cfg =================================================================== --- trunk/doc/doxygen.cfg (nonexistent) +++ trunk/doc/doxygen.cfg (revision 2) @@ -0,0 +1,258 @@ +# Doxyfile 1.5.8 + +#--------------------------------------------------------------------------- +# Project related configuration options +#--------------------------------------------------------------------------- +DOXYFILE_ENCODING = UTF-8 +PROJECT_NAME = ao68000 +PROJECT_NUMBER = +OUTPUT_DIRECTORY = ./doxygen +CREATE_SUBDIRS = NO +OUTPUT_LANGUAGE = English +BRIEF_MEMBER_DESC = YES +REPEAT_BRIEF = YES +ABBREVIATE_BRIEF = +ALWAYS_DETAILED_SEC = NO +INLINE_INHERITED_MEMB = NO +FULL_PATH_NAMES = NO +STRIP_FROM_PATH = +STRIP_FROM_INC_PATH = +SHORT_NAMES = NO +JAVADOC_AUTOBRIEF = NO +QT_AUTOBRIEF = NO +MULTILINE_CPP_IS_BRIEF = NO +INHERIT_DOCS = YES +SEPARATE_MEMBER_PAGES = NO +TAB_SIZE = 4 +ALIASES = +OPTIMIZE_OUTPUT_FOR_C = NO +OPTIMIZE_OUTPUT_JAVA = NO +OPTIMIZE_FOR_FORTRAN = NO +OPTIMIZE_OUTPUT_VERILOG= YES +OPTIMIZE_OUTPUT_VHDL = NO +EXTENSION_MAPPING = +BUILTIN_STL_SUPPORT = NO +CPP_CLI_SUPPORT = NO +SIP_SUPPORT = NO +IDL_PROPERTY_SUPPORT = YES +DISTRIBUTE_GROUP_DOC = NO +SUBGROUPING = YES +TYPEDEF_HIDES_STRUCT = NO +SYMBOL_CACHE_SIZE = 0 +#--------------------------------------------------------------------------- +# Build related configuration options +#--------------------------------------------------------------------------- +EXTRACT_ALL = YES +EXTRACT_PRIVATE = NO +EXTRACT_STATIC = NO +EXTRACT_LOCAL_CLASSES = YES +EXTRACT_LOCAL_METHODS = NO +EXTRACT_ANON_NSPACES = NO +HIDE_UNDOC_MEMBERS = NO +HIDE_UNDOC_CLASSES = NO +HIDE_FRIEND_COMPOUNDS = NO +HIDE_IN_BODY_DOCS = NO +INTERNAL_DOCS = YES +CASE_SENSE_NAMES = YES +HIDE_SCOPE_NAMES = NO +SHOW_INCLUDE_FILES = YES +INLINE_INFO = YES +SORT_MEMBER_DOCS = YES +SORT_BRIEF_DOCS = NO +SORT_GROUP_NAMES = NO +SORT_BY_SCOPE_NAME = NO +GENERATE_TODOLIST = YES +GENERATE_TESTLIST = YES +GENERATE_BUGLIST = YES +GENERATE_DEPRECATEDLIST= YES +ENABLED_SECTIONS = +MAX_INITIALIZER_LINES = 30 +SHOW_USED_FILES = YES +SHOW_DIRECTORIES = NO +SHOW_FILES = YES +SHOW_NAMESPACES = YES +FILE_VERSION_FILTER = +LAYOUT_FILE = +#--------------------------------------------------------------------------- +# configuration options related to warning and progress messages +#--------------------------------------------------------------------------- +QUIET = NO +WARNINGS = YES +WARN_IF_UNDOCUMENTED = YES +WARN_IF_DOC_ERROR = YES +WARN_NO_PARAMDOC = NO +WARN_FORMAT = "$file:$line: $text" +WARN_LOGFILE = +#--------------------------------------------------------------------------- +# configuration options related to the input files +#--------------------------------------------------------------------------- +INPUT = ./../rtl/verilog/ao68000 ./../doc/src +INPUT_ENCODING = UTF-8 +FILE_PATTERNS = *.v +RECURSIVE = YES +EXCLUDE = +EXCLUDE_SYMLINKS = NO +EXCLUDE_PATTERNS = +EXCLUDE_SYMBOLS = +EXAMPLE_PATH = ./.. +EXAMPLE_PATTERNS = +EXAMPLE_RECURSIVE = NO +IMAGE_PATH = ./img +INPUT_FILTER = +FILTER_PATTERNS = +FILTER_SOURCE_FILES = NO +#--------------------------------------------------------------------------- +# configuration options related to source browsing +#--------------------------------------------------------------------------- +SOURCE_BROWSER = YES +INLINE_SOURCES = YES +STRIP_CODE_COMMENTS = YES +REFERENCED_BY_RELATION = NO +REFERENCES_RELATION = NO +REFERENCES_LINK_SOURCE = YES +USE_HTAGS = NO +VERBATIM_HEADERS = YES +#--------------------------------------------------------------------------- +# configuration options related to the alphabetical class index +#--------------------------------------------------------------------------- +ALPHABETICAL_INDEX = NO +COLS_IN_ALPHA_INDEX = 5 +IGNORE_PREFIX = +#--------------------------------------------------------------------------- +# configuration options related to the HTML output +#--------------------------------------------------------------------------- +GENERATE_HTML = YES +HTML_OUTPUT = html +HTML_FILE_EXTENSION = .html +HTML_HEADER = +HTML_FOOTER = +HTML_STYLESHEET = +HTML_ALIGN_MEMBERS = YES +HTML_DYNAMIC_SECTIONS = NO +GENERATE_DOCSET = NO +DOCSET_FEEDNAME = "Doxygen generated docs" +DOCSET_BUNDLE_ID = org.doxygen.Project +GENERATE_HTMLHELP = NO +CHM_FILE = +HHC_LOCATION = +GENERATE_CHI = NO +CHM_INDEX_ENCODING = +BINARY_TOC = NO +TOC_EXPAND = NO +GENERATE_QHP = NO +QCH_FILE = +QHP_NAMESPACE = +QHP_VIRTUAL_FOLDER = doc +QHP_CUST_FILTER_NAME = +QHP_CUST_FILTER_ATTRS = +QHP_SECT_FILTER_ATTRS = +QHG_LOCATION = +DISABLE_INDEX = NO +ENUM_VALUES_PER_LINE = 4 +GENERATE_TREEVIEW = NONE +TREEVIEW_WIDTH = 250 +FORMULA_FONTSIZE = 10 +#--------------------------------------------------------------------------- +# configuration options related to the LaTeX output +#--------------------------------------------------------------------------- +GENERATE_LATEX = NO +LATEX_OUTPUT = latex +LATEX_CMD_NAME = latex +MAKEINDEX_CMD_NAME = makeindex +COMPACT_LATEX = NO +PAPER_TYPE = a4wide +EXTRA_PACKAGES = +LATEX_HEADER = +PDF_HYPERLINKS = YES +USE_PDFLATEX = YES +LATEX_BATCHMODE = NO +LATEX_HIDE_INDICES = NO +#--------------------------------------------------------------------------- +# configuration options related to the RTF output +#--------------------------------------------------------------------------- +GENERATE_RTF = NO +RTF_OUTPUT = rtf +COMPACT_RTF = NO +RTF_HYPERLINKS = NO +RTF_STYLESHEET_FILE = +RTF_EXTENSIONS_FILE = +#--------------------------------------------------------------------------- +# configuration options related to the man page output +#--------------------------------------------------------------------------- +GENERATE_MAN = NO +MAN_OUTPUT = man +MAN_EXTENSION = .3 +MAN_LINKS = NO +#--------------------------------------------------------------------------- +# configuration options related to the XML output +#--------------------------------------------------------------------------- +GENERATE_XML = NO +XML_OUTPUT = xml +XML_SCHEMA = +XML_DTD = +XML_PROGRAMLISTING = YES +#--------------------------------------------------------------------------- +# configuration options for the AutoGen Definitions output +#--------------------------------------------------------------------------- +GENERATE_AUTOGEN_DEF = NO +#--------------------------------------------------------------------------- +# configuration options related to the Perl module output +#--------------------------------------------------------------------------- +GENERATE_PERLMOD = NO +PERLMOD_LATEX = NO +PERLMOD_PRETTY = YES +PERLMOD_MAKEVAR_PREFIX = +#--------------------------------------------------------------------------- +# Configuration options related to the preprocessor +#--------------------------------------------------------------------------- +ENABLE_PREPROCESSING = YES +MACRO_EXPANSION = NO +EXPAND_ONLY_PREDEF = NO +SEARCH_INCLUDES = YES +INCLUDE_PATH = ./../rtl/verilog/ao68000 +INCLUDE_FILE_PATTERNS = *.v +PREDEFINED = +EXPAND_AS_DEFINED = +SKIP_FUNCTION_MACROS = YES +#--------------------------------------------------------------------------- +# Configuration::additions related to external references +#--------------------------------------------------------------------------- +TAGFILES = +GENERATE_TAGFILE = +ALLEXTERNALS = NO +EXTERNAL_GROUPS = YES +PERL_PATH = /usr/bin/perl +#--------------------------------------------------------------------------- +# Configuration options related to the dot tool +#--------------------------------------------------------------------------- +CLASS_DIAGRAMS = YES +MSCGEN_PATH = +HIDE_UNDOC_RELATIONS = YES +HAVE_DOT = NO +DOT_FONTNAME = FreeSans +DOT_FONTSIZE = 10 +DOT_FONTPATH = +CLASS_GRAPH = YES +COLLABORATION_GRAPH = YES +GROUP_GRAPHS = YES +UML_LOOK = NO +TEMPLATE_RELATIONS = NO +INCLUDE_GRAPH = YES +INCLUDED_BY_GRAPH = YES +CALL_GRAPH = NO +CALLER_GRAPH = NO +GRAPHICAL_HIERARCHY = YES +DIRECTORY_GRAPH = YES +DOT_IMAGE_FORMAT = png +DOT_PATH = +DOTFILE_DIRS = +DOT_GRAPH_MAX_NODES = 50 +MAX_DOT_GRAPH_DEPTH = 0 +DOT_TRANSPARENT = NO +DOT_MULTI_TARGETS = NO +GENERATE_LEGEND = YES +DOT_CLEANUP = YES +#--------------------------------------------------------------------------- +# Options related to the search engine +#--------------------------------------------------------------------------- +SEARCHENGINE = NO Index: trunk/doc/img/wishbone_compatible.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/img/wishbone_compatible.png =================================================================== --- trunk/doc/img/wishbone_compatible.png (nonexistent) +++ trunk/doc/img/wishbone_compatible.png (revision 2)

trunk/doc/img/wishbone_compatible.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/doc/img/structure.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/img/structure.png =================================================================== --- trunk/doc/img/structure.png (nonexistent) +++ trunk/doc/img/structure.png (revision 2)

trunk/doc/img/structure.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/doc/img/architecture.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/img/architecture.png =================================================================== --- trunk/doc/img/architecture.png (nonexistent) +++ trunk/doc/img/architecture.png (revision 2)

trunk/doc/img/architecture.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/doc/img/structure.graphml =================================================================== --- trunk/doc/img/structure.graphml (nonexistent) +++ trunk/doc/img/structure.graphml (revision 2) @@ -0,0 +1,774 @@ + + + + + + + + + + + + + + + + + + Dn Addr (3) + + + + + + + + + + + An Addr (3) + + + + + + + + + + + Dn RAM + + + + + + + + + + + An RAM + + + + + + + + + + + Dn output + + + + + + + + + + + An output + + + + + + + + + + + USP + + + + + + + + + + + SR + + + + + + + + + + + CCR + + + + + + + + + + + Operand1 (32) + + + + + + + + + + + Operand2 (32) + + + + + + + + + + + ALU + +AND,OR,EOR +ADD,SUB +MULU,MULS,DIVU,DIVS + + + + + + + + + + + Result register (32) + + + + + + + + + + + PC (32) + + + + + + + + + + + ir (16) + + + + + + + + + + + prefetch (80) + + + + + + + + + + + Shift + + + + + + + + + + + address (32) + + + + + + + + + + + size (2) + + + + + + + + + + + data (32) + + + + + + + + + + + Bus cycle +unit + + + + + + + + + + + fc (3) + + + + + + + + + + + Prefetch unit + + + + + + + + + + + Decode unit + + + + + + + + + + + Efficient Address +unit + + + + + + + + + + + ipl (3) + + + + + + + + + + + Reset +Blocked +(2) + + + + + + + + + + + Micrcode ROM + +45 kilobits + + + + + + + + + + + Micro PC (9) + + + + + + + + + + + Micro word (88) + + + + + + + + + + + Increment + + + + + + + + + + + Decrement + + + + + + + + + + + Index register (32) + + + + + + + + + + + select (4) + + + + + + + + + + + ea_reg (3) + + + + + + + + + + + ea_mod (3) + + + + + + + + + + + ea_type (4) + + + + + + + + + + + movem_modreg (6) + + + + + + + + + + + movem_loop (5) + + + + + + + + + + + trap (8) + + + + + + + + + + + Offset register (32) + + + + + + + + + + + movem_reg (16) + + + + + + + + + + + ALU unit + + + + + + + + + + + Microcode unit + + + + + + + + + + + Register file + + + + + + + + + + + stop_flag (1) + + + + + + + + + + + trace_flag (1) + + + + + + + + + + + group_0_flag (1) + + + + + + + + + + + instruction_flag (1) + + + + + + + + + + + read_modify_write_flag (1) + + + + + + + + + + + do_reset_flag (1) + + + + + + + + + + + do_interrupt_flag (1) + + + + + + + + + + + do_read_flag (1) + + + + + + + + + + + do_write_flag (1) + + + + + + + + + + + do_blocked_flag (1) + + + + + + + + + + + data_write (32) + + + + + + + + + + + An input (32) + + + + + + + + + + + Status unit + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: trunk/doc/img/architecture.graphml =================================================================== --- trunk/doc/img/architecture.graphml (nonexistent) +++ trunk/doc/img/architecture.graphml (revision 2) @@ -0,0 +1,363 @@ + + + + + + + + + + + + + + + + + + ao68000 + + + + + + + + + + + bus_control + + + + + + + + + + + registers + + + + + + + + + + + memory_registers + + + + + + + + + + + decoder + + + + + + + + + + + condition + + + + + + + + + + + alu + + + + + + + + + + + microcode_branch + + + + + + + + + + + WISHBONE bus + + + + + + + + + + + Interrupt input + +Reset output + +Blocked output + + + + + + + + + + + microcode + + + + + + + + + + + Dn and An +registers + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: trunk/doc/img/opencores.jpg =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/img/opencores.jpg =================================================================== --- trunk/doc/img/opencores.jpg (nonexistent) +++ trunk/doc/img/opencores.jpg (revision 2)

trunk/doc/img/opencores.jpg Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/doc/Makefile =================================================================== --- trunk/doc/Makefile (nonexistent) +++ trunk/doc/Makefile (revision 2) @@ -0,0 +1,57 @@ +ifndef BROWSER +BROWSER := firefox +endif + +ifndef AO68000_BASE +AO68000_BASE := $(CURDIR)/.. +endif + +help: + @echo -e "Select operation to perform. Type 'make' followed by the name of the operation." + @echo + @echo -e "Available operations:" + @echo -e "unpack \t- unpack generated doxygen HTML documentation." + @echo -e "doxygen \t- run the doxygen tool on the ao68000 project." + @echo -e " \t- Doxverilog version required." + @echo -e "view \t- open generated doxygen HTML documentation in a browser." + @echo -e "spec_extract \t- generate the specification.odt file from the HTML docs." + @echo + @exit 0 + +unpack: + tar -x -z -f doxygen_generated.tar.gz + +doxygen: doxygen.cfg ./doxygen +ifndef DOXVERILOG + @echo "DOXVERILOG environment variable not set. Set it to a Doxverilog executable." + @exit 1 +endif + $(DOXVERILOG) doxygen.cfg + +view: doxygen + $(BROWSER) ./doxygen/html/index.html & + +spec_extract: ./doxygen + mkdir -p ./out/spec_extract + java -jar $(AO68000_BASE)/sw/ao68000_tool/dist/ao68000_tool.jar spec_extract $(AO68000_BASE)/doc/doxygen/html/page_spec_references.html $(AO68000_BASE)/doc/out/spec_extract/references.html + java -jar $(AO68000_BASE)/sw/ao68000_tool/dist/ao68000_tool.jar spec_extract $(AO68000_BASE)/doc/doxygen/html/page_spec_ports.html $(AO68000_BASE)/doc/out/spec_extract/ports.html + java -jar $(AO68000_BASE)/sw/ao68000_tool/dist/ao68000_tool.jar spec_extract $(AO68000_BASE)/doc/doxygen/html/page_spec_clocks.html $(AO68000_BASE)/doc/out/spec_extract/clocks.html + java -jar $(AO68000_BASE)/sw/ao68000_tool/dist/ao68000_tool.jar spec_extract $(AO68000_BASE)/doc/doxygen/html/page_spec_registers.html $(AO68000_BASE)/doc/out/spec_extract/registers.html + java -jar $(AO68000_BASE)/sw/ao68000_tool/dist/ao68000_tool.jar spec_extract $(AO68000_BASE)/doc/doxygen/html/page_spec_operation.html $(AO68000_BASE)/doc/out/spec_extract/operation.html + java -jar $(AO68000_BASE)/sw/ao68000_tool/dist/ao68000_tool.jar spec_extract $(AO68000_BASE)/doc/doxygen/html/page_spec_architecture.html $(AO68000_BASE)/doc/out/spec_extract/architecture.html + java -jar $(AO68000_BASE)/sw/ao68000_tool/dist/ao68000_tool.jar spec_extract $(AO68000_BASE)/doc/doxygen/html/page_spec_introduction.html $(AO68000_BASE)/doc/out/spec_extract/introduction.html + java -jar $(AO68000_BASE)/sw/ao68000_tool/dist/ao68000_tool.jar spec_extract $(AO68000_BASE)/doc/doxygen/html/page_spec_revisions.html $(AO68000_BASE)/doc/out/spec_extract/revisions.html + + soffice "macro:///Standard.Module1.Main(file://$(AO68000_BASE)/doc/src/specification_template.odt,file://$(AO68000_BASE)/doc/out/spec_extract/specification.odt,,file://$(AO68000_BASE)/doc/out/spec_extract/references.html,True)" + soffice "macro:///Standard.Module1.Main(file://$(AO68000_BASE)/doc/out/spec_extract/specification.odt,file://$(AO68000_BASE)/doc/out/spec_extract/specification.odt,,file://$(AO68000_BASE)/doc/out/spec_extract/ports.html,True)" + soffice "macro:///Standard.Module1.Main(file://$(AO68000_BASE)/doc/out/spec_extract/specification.odt,file://$(AO68000_BASE)/doc/out/spec_extract/specification.odt,,file://$(AO68000_BASE)/doc/out/spec_extract/clocks.html,True)" + soffice "macro:///Standard.Module1.Main(file://$(AO68000_BASE)/doc/out/spec_extract/specification.odt,file://$(AO68000_BASE)/doc/out/spec_extract/specification.odt,,file://$(AO68000_BASE)/doc/out/spec_extract/registers.html,True)" + soffice "macro:///Standard.Module1.Main(file://$(AO68000_BASE)/doc/out/spec_extract/specification.odt,file://$(AO68000_BASE)/doc/out/spec_extract/specification.odt,,file://$(AO68000_BASE)/doc/out/spec_extract/operation.html,True)" + soffice "macro:///Standard.Module1.Main(file://$(AO68000_BASE)/doc/out/spec_extract/specification.odt,file://$(AO68000_BASE)/doc/out/spec_extract/specification.odt,,file://$(AO68000_BASE)/doc/out/spec_extract/architecture.html,True)" + soffice "macro:///Standard.Module1.Main(file://$(AO68000_BASE)/doc/out/spec_extract/specification.odt,file://$(AO68000_BASE)/doc/out/spec_extract/specification.odt,,file://$(AO68000_BASE)/doc/out/spec_extract/introduction.html,True)" + soffice "macro:///Standard.Module1.Main(file://$(AO68000_BASE)/doc/out/spec_extract/specification.odt,file://$(AO68000_BASE)/doc/out/spec_extract/specification.odt,,file://$(AO68000_BASE)/doc/out/spec_extract/revisions.html,False)" + +clean: + rm -R -f ./doxygen + rm -R -f ./out/spec_extract + Index: trunk/sim/rtl_sw_compare/bin/Makefile =================================================================== --- trunk/sim/rtl_sw_compare/bin/Makefile (nonexistent) +++ trunk/sim/rtl_sw_compare/bin/Makefile (revision 2) @@ -0,0 +1,42 @@ +AO68000_BASE := $(CURDIR)/../../.. +export AO68000_BASE + +DEST_DIR := $(AO68000_BASE)/sim/rtl_sw_compare/run + +START_IR_DEC := 0 +END_IR_DEC := 65536 +TERM_PROGRAM := xterm +COUNT := 2 +COUNT_LIST := $(wordlist 1,$(COUNT),0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19) + +STEP = `expr $ $(END_IR_DEC) - $(START_IR_DEC) $ / $(COUNT)` + +help: + @echo -e "Select RTL-SW comparison profile. Type 'make' followed by the name of the profile." + @echo + @echo -e "Available profiles:" + @echo -e "tb_ao68000_with_winuae \t- compare tb_ao68000 RTL project with winuae software project." + @echo + @exit 0 + +tb_ao68000_with_winuae: + $(foreach i,$(COUNT_LIST), mkdir -p $(DEST_DIR)/tb_ao68000_$(i); ) + $(foreach i,$(COUNT_LIST), mkdir -p $(DEST_DIR)/tb_ao68000_$(i)/microcode; ) + $(foreach i,$(COUNT_LIST), mkdir -p $(DEST_DIR)/tb_ao68000_$(i)/bin; ) + $(foreach i,$(COUNT_LIST), mkdir -p $(DEST_DIR)/tb_ao68000_$(i)/vcd; ) + $(foreach i,$(COUNT_LIST), cp $(AO68000_BASE)/rtl/verilog/ao68000/microcode/microcode.mif $(DEST_DIR)/tb_ao68000_$(i)/microcode; ) + $(foreach i,$(COUNT_LIST), echo -e "#!/bin/bash\n$(AO68000_BASE)/sim/rtl_sim/run/tb_ao68000/tb_ao68000 \$$@" \ + > $(DEST_DIR)/tb_ao68000_$(i)/bin/run.sh; \ + ) + $(foreach i,$(COUNT_LIST), chmod +x $(DEST_DIR)/tb_ao68000_$(i)/bin/run.sh; ) + $(foreach i,$(COUNT_LIST), $(TERM_PROGRAM) -e java -jar $(AO68000_BASE)/sw/ao68000_tool/dist/ao68000_tool.jar test \ + $(AO68000_BASE)/sim/sw_emulators/run/winuae/ao \ + $(DEST_DIR)/tb_ao68000_$(i)/bin/run.sh \ + `expr $(i) \* $ \( $(END_IR_DEC) - $(START_IR_DEC) $ / $(COUNT) \)` \ + `expr $ $(i) + 1 $ \* $ \( $(END_IR_DEC) - $(START_IR_DEC) $ / $(COUNT) \)` \ + & \ + ) + +clean: + rm -f -R $(DEST_DIR)/tb_ao68000_* + Index: trunk/sim/sw_emulators/bin/Makefile =================================================================== --- trunk/sim/sw_emulators/bin/Makefile (nonexistent) +++ trunk/sim/sw_emulators/bin/Makefile (revision 2) @@ -0,0 +1,22 @@ +AO68000_BASE := $(CURDIR)/../../.. +export AO68000_BASE + +SRC_DIR := $(AO68000_BASE)/bench/sw_emulators +DEST_DIR := $(AO68000_BASE)/sim/sw_emulators/run + +help: + @echo -e "Select software MC68000 emulator to compile. Type 'make' followed by the name of the project." + @echo + @echo -e "Available projects:" + @echo -e "winuae \t- MC68000 emulator from the WinUAE project (www.winuae.net)." + @echo + @exit 0 + +winuae: + mkdir -p $(DEST_DIR)/winuae + cp $(SRC_DIR)/winuae/Makefile $(DEST_DIR)/winuae + $(MAKE) -C $(DEST_DIR)/winuae VPATH=$(SRC_DIR)/winuae + +clean: + rm -f -R $(DEST_DIR)/winuae + Index: trunk/sim/rtl_sim/bin/Makefile =================================================================== --- trunk/sim/rtl_sim/bin/Makefile (nonexistent) +++ trunk/sim/rtl_sim/bin/Makefile (revision 2) @@ -0,0 +1,21 @@ +AO68000_BASE := $(CURDIR)/../../.. +export AO68000_BASE + +SRC_DIR := $(AO68000_BASE)/bench/verilog +DEST_DIR := $(AO68000_BASE)/sim/rtl_sim/run + +help: + @echo -e "Select RTL simulation to compile. Type 'make' followed by the name of the project." + @echo + @echo -e "Available projects:" + @echo -e "tb_ao68000 \t- testbench for ao68000." + @echo + @exit 0 + +tb_ao68000: + mkdir -p $(DEST_DIR)/tb_ao68000 + cp $(SRC_DIR)/tb_ao68000/Makefile $(DEST_DIR)/tb_ao68000 + $(MAKE) -C $(DEST_DIR)/tb_ao68000 VPATH=$(SRC_DIR)/tb_ao68000 + +clean: + rm -f -R $(DEST_DIR)/tb_ao68000 Index: trunk/sw/linux/linux-2.6.33.1-ao68000/arch/m68knommu/kernel/time.c =================================================================== --- trunk/sw/linux/linux-2.6.33.1-ao68000/arch/m68knommu/kernel/time.c (nonexistent) +++ trunk/sw/linux/linux-2.6.33.1-ao68000/arch/m68knommu/kernel/time.c (revision 2) @@ -0,0 +1,93 @@ +/* + * linux/arch/m68knommu/kernel/time.c + * + * Copyright (C) 1991, 1992, 1995 Linus Torvalds + * + * This file contains the m68k-specific time handling details. + * Most of the stuff is located in the machine specific files. + * + * 1997-09-10 Updated NTP code according to technical memorandum Jan '96 + * "A Kernel Model for Precision Timekeeping" by Dave Mills + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define TICK_SIZE (tick_nsec / 1000) + +static inline int set_rtc_mmss(unsigned long nowtime) +{ + if (mach_set_clock_mmss) + return mach_set_clock_mmss (nowtime); + return -1; +} + +#ifndef CONFIG_GENERIC_CLOCKEVENTS +/* + * timer_interrupt() needs to keep up the real-time clock, + * as well as call the "do_timer()" routine every clocktick + */ +irqreturn_t arch_timer_interrupt(int irq, void *dummy) +{ + unsigned long flags; + + + if (current->pid) + profile_tick(CPU_PROFILING); + + write_seqlock_irqsave(&xtime_lock, flags); + + do_timer(1); + + +#ifndef CONFIG_SMP + update_process_times(user_mode(get_irq_regs())); +#endif + + write_sequnlock_irqrestore(&xtime_lock, flags); + + return(IRQ_HANDLED); +} +#endif + +static unsigned long read_rtc_mmss(void) +{ + unsigned int year, mon, day, hour, min, sec; + + if (mach_gettod) + mach_gettod(&year, &mon, &day, &hour, &min, &sec); + else + year = mon = day = hour = min = sec = 0; + + if ((year += 1900) < 1970) + year += 100; + + return mktime(year, mon, day, hour, min, sec); +} + +void read_persistent_clock(struct timespec *ts) +{ + ts->tv_sec = read_rtc_mmss(); + ts->tv_nsec = 0; +} + +int update_persistent_clock(struct timespec now) +{ + return set_rtc_mmss(now.tv_sec); +} + +void time_init(void) +{ + hw_timer_init(); +} Index: trunk/sw/linux/linux-2.6.33.1-ao68000/arch/m68knommu/kernel/setup.c =================================================================== --- trunk/sw/linux/linux-2.6.33.1-ao68000/arch/m68knommu/kernel/setup.c (nonexistent) +++ trunk/sw/linux/linux-2.6.33.1-ao68000/arch/m68knommu/kernel/setup.c (revision 2) @@ -0,0 +1,358 @@ +/* + * linux/arch/m68knommu/kernel/setup.c + * + * Copyright (C) 1999-2007 Greg Ungerer (gerg@snapgear.com) + * Copyright (C) 1998,1999 D. Jeff Dionne + * Copyleft ()) 2000 James D. Schettine {james@telos-systems.com} + * Copyright (C) 1998 Kenneth Albanowski + * Copyright (C) 1995 Hamish Macdonald + * Copyright (C) 2000 Lineo Inc. (www.lineo.com) + * Copyright (C) 2001 Lineo, Inc. + * + * 68VZ328 Fixes/support Evan Stawnyczy + */ + +/* + * This file handles the architecture-dependent parts of system setup + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +unsigned long memory_start; +unsigned long memory_end; + +EXPORT_SYMBOL(memory_start); +EXPORT_SYMBOL(memory_end); + +char __initdata command_line[COMMAND_LINE_SIZE]; + +/* machine dependent timer functions */ +void (*mach_gettod)(int*, int*, int*, int*, int*, int*); +int (*mach_set_clock_mmss)(unsigned long); + +/* machine dependent reboot functions */ +void (*mach_reset)(void); +void (*mach_halt)(void); +void (*mach_power_off)(void); + +#ifdef CONFIG_M68000 + #define CPU "MC68000" +#endif +#ifdef CONFIG_M68328 + #define CPU "MC68328" +#endif +#ifdef CONFIG_M68EZ328 + #define CPU "MC68EZ328" +#endif +#ifdef CONFIG_M68VZ328 + #define CPU "MC68VZ328" +#endif +#ifdef CONFIG_M68360 + #define CPU "MC68360" +#endif +#if defined(CONFIG_M5206) + #define CPU "COLDFIRE(m5206)" +#endif +#if defined(CONFIG_M5206e) + #define CPU "COLDFIRE(m5206e)" +#endif +#if defined(CONFIG_M520x) + #define CPU "COLDFIRE(m520x)" +#endif +#if defined(CONFIG_M523x) + #define CPU "COLDFIRE(m523x)" +#endif +#if defined(CONFIG_M5249) + #define CPU "COLDFIRE(m5249)" +#endif +#if defined(CONFIG_M5271) + #define CPU "COLDFIRE(m5270/5271)" +#endif +#if defined(CONFIG_M5272) + #define CPU "COLDFIRE(m5272)" +#endif +#if defined(CONFIG_M5275) + #define CPU "COLDFIRE(m5274/5275)" +#endif +#if defined(CONFIG_M528x) + #define CPU "COLDFIRE(m5280/5282)" +#endif +#if defined(CONFIG_M5307) + #define CPU "COLDFIRE(m5307)" +#endif +#if defined(CONFIG_M532x) + #define CPU "COLDFIRE(m532x)" +#endif +#if defined(CONFIG_M5407) + #define CPU "COLDFIRE(m5407)" +#endif +#if defined(CONFIG_AO68000) + #define CPU "AO68000" +#endif +#ifndef CPU + #define CPU "UNKNOWN" +#endif + +extern int _stext, _etext, _sdata, _edata, _sbss, _ebss, _end; +extern int _ramstart, _ramend; + +#if defined(CONFIG_UBOOT) +/* + * parse_uboot_commandline + * + * Copies u-boot commandline arguments and store them in the proper linux + * variables. + * + * Assumes: + * _init_sp global contains the address in the stack pointer when the + * kernel starts (see head.S::_start) + * + * U-Boot calling convention: + * (*kernel) (kbd, initrd_start, initrd_end, cmd_start, cmd_end); + * + * _init_sp can be parsed as such + * + * _init_sp+00 = u-boot cmd after jsr into kernel (skip) + * _init_sp+04 = &kernel board_info (residual data) + * _init_sp+08 = &initrd_start + * _init_sp+12 = &initrd_end + * _init_sp+16 = &cmd_start + * _init_sp+20 = &cmd_end + * + * This also assumes that the memory locations pointed to are still + * unmodified. U-boot places them near the end of external SDRAM. + * + * Argument(s): + * commandp = the linux commandline arg container to fill. + * size = the sizeof commandp. + * + * Returns: + */ +void parse_uboot_commandline(char *commandp, int size) +{ + extern unsigned long _init_sp; + unsigned long *sp; + unsigned long uboot_kbd; + unsigned long uboot_initrd_start, uboot_initrd_end; + unsigned long uboot_cmd_start, uboot_cmd_end; + + + sp = (unsigned long *)_init_sp; + uboot_kbd = sp[1]; + uboot_initrd_start = sp[2]; + uboot_initrd_end = sp[3]; + uboot_cmd_start = sp[4]; + uboot_cmd_end = sp[5]; + + if (uboot_cmd_start && uboot_cmd_end) + strncpy(commandp, (const char *)uboot_cmd_start, size); +#if defined(CONFIG_BLK_DEV_INITRD) + if (uboot_initrd_start && uboot_initrd_end && + (uboot_initrd_end > uboot_initrd_start)) { + initrd_start = uboot_initrd_start; + initrd_end = uboot_initrd_end; + ROOT_DEV = Root_RAM0; + printk(KERN_INFO "initrd at 0x%lx:0x%lx\n", + initrd_start, initrd_end); + } +#endif /* if defined(CONFIG_BLK_DEV_INITRD) */ +} +#endif /* #if defined(CONFIG_UBOOT) */ + +void __init setup_arch(char **cmdline_p) +{ + int bootmap_size; + + memory_start = PAGE_ALIGN(_ramstart); + memory_end = _ramend; + + init_mm.start_code = (unsigned long) &_stext; + init_mm.end_code = (unsigned long) &_etext; + init_mm.end_data = (unsigned long) &_edata; + init_mm.brk = (unsigned long) 0; + + config_BSP(&command_line[0], sizeof(command_line)); + +#if defined(CONFIG_BOOTPARAM) + strncpy(&command_line[0], CONFIG_BOOTPARAM_STRING, sizeof(command_line)); + command_line[sizeof(command_line) - 1] = 0; +#endif /* CONFIG_BOOTPARAM */ + +#if defined(CONFIG_UBOOT) + /* CONFIG_UBOOT and CONFIG_BOOTPARAM defined, concatenate cmdline */ + #if defined(CONFIG_BOOTPARAM) + /* Add the whitespace separator */ + command_line[strlen(CONFIG_BOOTPARAM_STRING)] = ' '; + /* Parse uboot command line into the rest of the buffer */ + parse_uboot_commandline( + &command_line[(strlen(CONFIG_BOOTPARAM_STRING)+1)], + (sizeof(command_line) - + (strlen(CONFIG_BOOTPARAM_STRING)+1))); + /* Only CONFIG_UBOOT defined, create cmdline */ + #else + parse_uboot_commandline(&command_line[0], sizeof(command_line)); + #endif /* CONFIG_BOOTPARAM */ + command_line[sizeof(command_line) - 1] = 0; +#endif /* CONFIG_UBOOT */ + printk(KERN_INFO "\x0F\r\n\nuClinux/" CPU "\n"); + +#ifdef CONFIG_UCDIMM + printk(KERN_INFO "uCdimm by Lineo, Inc. \n"); +#endif +#ifdef CONFIG_M68VZ328 + printk(KERN_INFO "M68VZ328 support by Evan Stawnyczy \n"); +#endif +#ifdef CONFIG_COLDFIRE + printk(KERN_INFO "COLDFIRE port done by Greg Ungerer, gerg@snapgear.com\n"); +#ifdef CONFIG_M5307 + printk(KERN_INFO "Modified for M5307 by Dave Miller, dmiller@intellistor.com\n"); +#endif +#ifdef CONFIG_ELITE + printk(KERN_INFO "Modified for M5206eLITE by Rob Scott, rscott@mtrob.fdns.net\n"); +#endif +#endif + printk(KERN_INFO "Flat model support (C) 1998,1999 Kenneth Albanowski, D. Jeff Dionne\n"); + +#if defined( CONFIG_PILOT ) && defined( CONFIG_M68328 ) + printk(KERN_INFO "TRG SuperPilot FLASH card support \n"); +#endif +#if defined( CONFIG_PILOT ) && defined( CONFIG_M68EZ328 ) + printk(KERN_INFO "PalmV support by Lineo Inc. \n"); +#endif +#if defined (CONFIG_M68360) + printk(KERN_INFO "QUICC port done by SED Systems ,\n"); + printk(KERN_INFO "based on 2.0.38 port by Lineo Inc. .\n"); +#endif +#ifdef CONFIG_DRAGEN2 + printk(KERN_INFO "DragonEngine II board support by Georges Menie\n"); +#endif +#ifdef CONFIG_M5235EVB + printk(KERN_INFO "Motorola M5235EVB support (C)2005 Syn-tech Systems, Inc. (Jate Sujjavanich)\n"); +#endif + + pr_debug("KERNEL -> TEXT=0x%06x-0x%06x DATA=0x%06x-0x%06x " + "BSS=0x%06x-0x%06x\n", (int) &_stext, (int) &_etext, + (int) &_sdata, (int) &_edata, + (int) &_sbss, (int) &_ebss); + pr_debug("MEMORY -> ROMFS=0x%06x-0x%06x MEM=0x%06x-0x%06x\n ", + (int) &_ebss, (int) memory_start, + (int) memory_start, (int) memory_end); + + /* Keep a copy of command line */ + *cmdline_p = &command_line[0]; + memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE); + boot_command_line[COMMAND_LINE_SIZE-1] = 0; + +#ifdef DEBUG + if (strlen(*cmdline_p)) + printk(KERN_DEBUG "Command line: '%s'\n", *cmdline_p); +#endif +#if defined(CONFIG_FRAMEBUFFER_CONSOLE) && defined(CONFIG_DUMMY_CONSOLE) + conswitchp = &dummy_con; +#endif + + /* + * Give all the memory to the bootmap allocator, tell it to put the + * boot mem_map at the start of memory. + */ + bootmap_size = init_bootmem_node( + NODE_DATA(0), + memory_start >> PAGE_SHIFT, /* map goes here */ + PAGE_OFFSET >> PAGE_SHIFT, /* 0 on coldfire */ + memory_end >> PAGE_SHIFT); + /* + * Free the usable memory, we have to make sure we do not free + * the bootmem bitmap so we then reserve it after freeing it :-) + */ + + free_bootmem(memory_start, memory_end - memory_start); + reserve_bootmem(memory_start, bootmap_size, BOOTMEM_DEFAULT); + +#if defined(CONFIG_UBOOT) && defined(CONFIG_BLK_DEV_INITRD) + if ((initrd_start > 0) && (initrd_start < initrd_end) && + (initrd_end < memory_end)) + reserve_bootmem(initrd_start, initrd_end - initrd_start, + BOOTMEM_DEFAULT); +#endif /* if defined(CONFIG_BLK_DEV_INITRD) */ + + /* + * Get kmalloc into gear. + */ + paging_init(); +} + +/* + * Get CPU information for use by the procfs. + */ +static int show_cpuinfo(struct seq_file *m, void *v) +{ + char *cpu, *mmu, *fpu; + u_long clockfreq; + + cpu = CPU; + mmu = "none"; + fpu = "none"; + +#ifdef CONFIG_COLDFIRE + clockfreq = (loops_per_jiffy * HZ) * 3; +#else + clockfreq = (loops_per_jiffy * HZ) * 16; +#endif + + seq_printf(m, "CPU:\t\t%s\n" + "MMU:\t\t%s\n" + "FPU:\t\t%s\n" + "Clocking:\t%lu.%1luMHz\n" + "BogoMips:\t%lu.%02lu\n" + "Calibration:\t%lu loops\n", + cpu, mmu, fpu, + clockfreq / 1000000, + (clockfreq / 100000) % 10, + (loops_per_jiffy * HZ) / 500000, + ((loops_per_jiffy * HZ) / 5000) % 100, + (loops_per_jiffy * HZ)); + + return 0; +} + +static void *c_start(struct seq_file *m, loff_t *pos) +{ + return *pos < NR_CPUS ? ((void *) 0x12345678) : NULL; +} + +static void *c_next(struct seq_file *m, void *v, loff_t *pos) +{ + ++*pos; + return c_start(m, pos); +} + +static void c_stop(struct seq_file *m, void *v) +{ +} + +const struct seq_operations cpuinfo_op = { + .start = c_start, + .next = c_next, + .stop = c_stop, + .show = show_cpuinfo, +}; + Index: trunk/sw/linux/linux-2.6.33.1-ao68000/arch/m68knommu/kernel/vmlinux.lds.S =================================================================== --- trunk/sw/linux/linux-2.6.33.1-ao68000/arch/m68knommu/kernel/vmlinux.lds.S (nonexistent) +++ trunk/sw/linux/linux-2.6.33.1-ao68000/arch/m68knommu/kernel/vmlinux.lds.S (revision 2) @@ -0,0 +1,182 @@ +/* + * vmlinux.lds.S -- master linker script for m68knommu arch + * + * (C) Copyright 2002-2006, Greg Ungerer + * + * This linker script is equiped to build either ROM loaded or RAM + * run kernels. + */ + +#include +#include +#include + +#if defined(CONFIG_RAMKERNEL) +#define RAM_START CONFIG_KERNELBASE +#define RAM_LENGTH (CONFIG_RAMBASE + CONFIG_RAMSIZE - CONFIG_KERNELBASE) +#define TEXT ram +#define DATA ram +#define INIT ram +#define BSSS ram +#endif +#if defined(CONFIG_ROMKERNEL) || defined(CONFIG_HIMEMKERNEL) +#define RAM_START CONFIG_RAMBASE +#define RAM_LENGTH CONFIG_RAMSIZE +#define ROMVEC_START CONFIG_ROMVEC +#define ROMVEC_LENGTH CONFIG_ROMVECSIZE +#define ROM_START CONFIG_ROMSTART +#define ROM_LENGTH CONFIG_ROMSIZE +#define TEXT rom +#define DATA ram +#define INIT ram +#define BSSS ram +#endif + +#ifndef DATA_ADDR +#define DATA_ADDR +#endif + + +OUTPUT_ARCH(m68k) +ENTRY(_start) + +MEMORY { + ram : ORIGIN = RAM_START, LENGTH = RAM_LENGTH +#ifdef ROM_START + romvec : ORIGIN = ROMVEC_START, LENGTH = ROMVEC_LENGTH + rom : ORIGIN = ROM_START, LENGTH = ROM_LENGTH +#endif +} + +jiffies = jiffies_64 + 4; + +SECTIONS { + +#ifdef ROMVEC_START + . = ROMVEC_START ; + .romvec : { + __rom_start = . ; + _romvec = .; + *(.data.initvect) + } > romvec +#endif + + .text : { + _text = .; + _stext = . ; + HEAD_TEXT + TEXT_TEXT + SCHED_TEXT + LOCK_TEXT + *(.text.lock) + + . = ALIGN(16); /* Exception table */ + __start___ex_table = .; + *(__ex_table) + __stop___ex_table = .; + + *(.rodata) *(.rodata.*) + *(__vermagic) /* Kernel version magic */ + *(__markers_strings) + *(.rodata1) + *(.rodata.str1.1) + + /* Kernel symbol table: Normal symbols */ + . = ALIGN(4); + __start___ksymtab = .; + *(__ksymtab) + __stop___ksymtab = .; + + /* Kernel symbol table: GPL-only symbols */ + __start___ksymtab_gpl = .; + *(__ksymtab_gpl) + __stop___ksymtab_gpl = .; + + /* Kernel symbol table: Normal unused symbols */ + __start___ksymtab_unused = .; + *(__ksymtab_unused) + __stop___ksymtab_unused = .; + + /* Kernel symbol table: GPL-only unused symbols */ + __start___ksymtab_unused_gpl = .; + *(__ksymtab_unused_gpl) + __stop___ksymtab_unused_gpl = .; + + /* Kernel symbol table: GPL-future symbols */ + __start___ksymtab_gpl_future = .; + *(__ksymtab_gpl_future) + __stop___ksymtab_gpl_future = .; + + /* Kernel symbol table: Normal symbols */ + __start___kcrctab = .; + *(__kcrctab) + __stop___kcrctab = .; + + /* Kernel symbol table: GPL-only symbols */ + __start___kcrctab_gpl = .; + *(__kcrctab_gpl) + __stop___kcrctab_gpl = .; + + /* Kernel symbol table: Normal unused symbols */ + __start___kcrctab_unused = .; + *(__kcrctab_unused) + __stop___kcrctab_unused = .; + + /* Kernel symbol table: GPL-only unused symbols */ + __start___kcrctab_unused_gpl = .; + *(__kcrctab_unused_gpl) + __stop___kcrctab_unused_gpl = .; + + /* Kernel symbol table: GPL-future symbols */ + __start___kcrctab_gpl_future = .; + *(__kcrctab_gpl_future) + __stop___kcrctab_gpl_future = .; + + /* Kernel symbol table: strings */ + *(__ksymtab_strings) + + /* Built-in module parameters */ + . = ALIGN(4) ; + __start___param = .; + *(__param) + __stop___param = .; + + *(.note.gnu.build-id) + + . = ALIGN(4) ; + _etext = . ; + } > TEXT + + .data DATA_ADDR : { + . = ALIGN(4); + _sdata = . ; + DATA_DATA + CACHELINE_ALIGNED_DATA(32) + INIT_TASK_DATA(THREAD_SIZE) + _edata = . ; + } > DATA + + .init.text : { + . = ALIGN(PAGE_SIZE); + __init_begin = .; + } > INIT + INIT_TEXT_SECTION(PAGE_SIZE) > INIT + INIT_DATA_SECTION(16) > INIT + .init.data : { + . = ALIGN(PAGE_SIZE); + __init_end = .; + } > INIT + + .bss : { + . = ALIGN(4); + _sbss = . ; + *(.bss) + *(COMMON) + . = ALIGN(4) ; + _ebss = . ; + _end = . ; + } > BSSS + + DISCARDS +} + Index: trunk/sw/linux/linux-2.6.33.1-ao68000/arch/m68knommu/Kconfig =================================================================== --- trunk/sw/linux/linux-2.6.33.1-ao68000/arch/m68knommu/Kconfig (nonexistent) +++ trunk/sw/linux/linux-2.6.33.1-ao68000/arch/m68knommu/Kconfig (revision 2) @@ -0,0 +1,752 @@ +# +# For a description of the syntax of this configuration file, +# see Documentation/kbuild/kconfig-language.txt. +# + +mainmenu "uClinux/68k (w/o MMU) Kernel Configuration" + +config M68K + bool + default y + select HAVE_IDE + +config MMU + bool + default n + +config NO_DMA + bool + depends on !COLDFIRE + default y + +config FPU + bool + default n + +config ZONE_DMA + bool + default y + +config RWSEM_GENERIC_SPINLOCK + bool + default y + +config RWSEM_XCHGADD_ALGORITHM + bool + default n + +config ARCH_HAS_ILOG2_U32 + bool + default n + +config ARCH_HAS_ILOG2_U64 + bool + default n + +config GENERIC_FIND_NEXT_BIT + bool + default y + +config GENERIC_GPIO + bool + default n + +config GENERIC_HWEIGHT + bool + default y + +config GENERIC_HARDIRQS + bool + default y + +config GENERIC_CALIBRATE_DELAY + bool + default y + +config GENERIC_TIME + bool + default y + +config GENERIC_CMOS_UPDATE + bool + default y + +config TIME_LOW_RES + bool + default y + +config GENERIC_CLOCKEVENTS + bool + default n + +config NO_IOPORT + def_bool y + +source "init/Kconfig" + +source "kernel/Kconfig.freezer" + +menu "Processor type and features" + +choice + prompt "CPU" + default M68EZ328 + +config M68328 + bool "MC68328" + help + Motorola 68328 processor support. + +config AO68000 + bool "AO68000" + help + AO68000 soft core support. + +config M68EZ328 + bool "MC68EZ328" + help + Motorola 68EX328 processor support. + +config M68VZ328 + bool "MC68VZ328" + help + Motorola 68VZ328 processor support. + +config M68360 + bool "MC68360" + help + Motorola 68360 processor support. + +config M5206 + bool "MCF5206" + help + Motorola ColdFire 5206 processor support. + +config M5206e + bool "MCF5206e" + help + Motorola ColdFire 5206e processor support. + +config M520x + bool "MCF520x" + select GENERIC_CLOCKEVENTS + help + Freescale Coldfire 5207/5208 processor support. + +config M523x + bool "MCF523x" + select GENERIC_CLOCKEVENTS + help + Freescale Coldfire 5230/1/2/4/5 processor support + +config M5249 + bool "MCF5249" + help + Motorola ColdFire 5249 processor support. + +config M5271 + bool "MCF5271" + help + Freescale (Motorola) ColdFire 5270/5271 processor support. + +config M5272 + bool "MCF5272" + help + Motorola ColdFire 5272 processor support. + +config M5275 + bool "MCF5275" + help + Freescale (Motorola) ColdFire 5274/5275 processor support. + +config M528x + bool "MCF528x" + select GENERIC_CLOCKEVENTS + help + Motorola ColdFire 5280/5282 processor support. + +config M5307 + bool "MCF5307" + help + Motorola ColdFire 5307 processor support. + +config M532x + bool "MCF532x" + help + Freescale (Motorola) ColdFire 532x processor support. + +config M5407 + bool "MCF5407" + help + Motorola ColdFire 5407 processor support. + +endchoice + +config M527x + bool + depends on (M5271 || M5275) + select GENERIC_CLOCKEVENTS + default y + +config COLDFIRE + bool + depends on (M5206 || M5206e || M520x || M523x || M5249 || M527x || M5272 || M528x || M5307 || M532x || M5407) + select GENERIC_GPIO + select ARCH_REQUIRE_GPIOLIB + default y + +config CLOCK_SET + bool "Enable setting the CPU clock frequency" + default n + help + On some CPU's you do not need to know what the core CPU clock + frequency is. On these you can disable clock setting. On some + traditional 68K parts, and on all ColdFire parts you need to set + the appropriate CPU clock frequency. On these devices many of the + onboard peripherals derive their timing from the master CPU clock + frequency. + +config CLOCK_FREQ + int "Set the core clock frequency" + default "66666666" + depends on CLOCK_SET + help + Define the CPU clock frequency in use. This is the core clock + frequency, it may or may not be the same as the external clock + crystal fitted to your board. Some processors have an internal + PLL and can have their frequency programmed at run time, others + use internal dividers. In general the kernel won't setup a PLL + if it is fitted (there are some exceptions). This value will be + specific to the exact CPU that you are using. + +config CLOCK_DIV + int "Set the core/bus clock divide ratio" + default "1" + depends on CLOCK_SET + help + On many SoC style CPUs the master CPU clock is also used to drive + on-chip peripherals. The clock that is distributed to these + peripherals is sometimes a fixed ratio of the master clock + frequency. If so then set this to the divider ratio of the + master clock to the peripheral clock. If not sure then select 1. + +config OLDMASK + bool "Old mask 5307 (1H55J) silicon" + depends on M5307 + help + Build support for the older revision ColdFire 5307 silicon. + Specifically this is the 1H55J mask revision. + +comment "Platform" + +config TERASICDE2 + bool "Terasic DE2-70 FPGA development board support" + depends on AO68000 + help + Support for the Terasic DE2-70 FPGA development board. + +config PILOT3 + bool "Pilot 1000/5000, PalmPilot Personal/Pro, or PalmIII support" + depends on M68328 + help + Support for the Palm Pilot 1000/5000, Personal/Pro and PalmIII. + +config XCOPILOT_BUGS + bool "(X)Copilot support" + depends on PILOT3 + help + Support the bugs of Xcopilot. + +config UC5272 + bool 'Arcturus Networks uC5272 dimm board support' + depends on M5272 + help + Support for the Arcturus Networks uC5272 dimm board. + +config UC5282 + bool "Arcturus Networks uC5282 board support" + depends on M528x + help + Support for the Arcturus Networks uC5282 dimm board. + +config UCSIMM + bool "uCsimm module support" + depends on M68EZ328 + help + Support for the Arcturus Networks uCsimm module. + +config UCDIMM + bool "uDsimm module support" + depends on M68VZ328 + help + Support for the Arcturus Networks uDsimm module. + +config DRAGEN2 + bool "DragenEngine II board support" + depends on M68VZ328 + help + Support for the DragenEngine II board. + +config DIRECT_IO_ACCESS + bool "Allow user to access IO directly" + depends on (UCSIMM || UCDIMM || DRAGEN2) + help + Disable the CPU internal registers protection in user mode, + to allow a user application to read/write them. + +config INIT_LCD + bool "Initialize LCD" + depends on (UCSIMM || UCDIMM || DRAGEN2) + help + Initialize the LCD controller of the 68x328 processor. + +config MEMORY_RESERVE + int "Memory reservation (MiB)" + depends on (UCSIMM || UCDIMM) + help + Reserve certain memory regions on 68x328 based boards. + +config UCQUICC + bool "Lineo uCquicc board support" + depends on M68360 + help + Support for the Lineo uCquicc board. + +config ARN5206 + bool "Arnewsh 5206 board support" + depends on M5206 + help + Support for the Arnewsh 5206 board. + +config M5206eC3 + bool "Motorola M5206eC3 board support" + depends on M5206e + help + Support for the Motorola M5206eC3 board. + +config ELITE + bool "Motorola M5206eLITE board support" + depends on M5206e + help + Support for the Motorola M5206eLITE board. + +config M5208EVB + bool "Freescale M5208EVB board support" + depends on M520x + help + Support for the Freescale Coldfire M5208EVB. + +config M5235EVB + bool "Freescale M5235EVB support" + depends on M523x + help + Support for the Freescale M5235EVB board. + +config M5249C3 + bool "Motorola M5249C3 board support" + depends on M5249 + help + Support for the Motorola M5249C3 board. + +config M5271EVB + bool "Freescale (Motorola) M5271EVB board support" + depends on M5271 + help + Support for the Freescale (Motorola) M5271EVB board. + +config M5275EVB + bool "Freescale (Motorola) M5275EVB board support" + depends on M5275 + help + Support for the Freescale (Motorola) M5275EVB board. + +config M5272C3 + bool "Motorola M5272C3 board support" + depends on M5272 + help + Support for the Motorola M5272C3 board. + +config COBRA5272 + bool "senTec COBRA5272 board support" + depends on M5272 + help + Support for the senTec COBRA5272 board. + +config AVNET5282 + bool "Avnet 5282 board support" + depends on M528x + help + Support for the Avnet 5282 board. + +config M5282EVB + bool "Motorola M5282EVB board support" + depends on M528x + help + Support for the Motorola M5282EVB board. + +config COBRA5282 + bool "senTec COBRA5282 board support" + depends on M528x + help + Support for the senTec COBRA5282 board. + +config SOM5282EM + bool "EMAC.Inc SOM5282EM board support" + depends on M528x + help + Support for the EMAC.Inc SOM5282EM module. + +config WILDFIRE + bool "Intec Automation Inc. WildFire board support" + depends on M528x + help + Support for the Intec Automation Inc. WildFire. + +config WILDFIREMOD + bool "Intec Automation Inc. WildFire module support" + depends on M528x + help + Support for the Intec Automation Inc. WildFire module. + +config ARN5307 + bool "Arnewsh 5307 board support" + depends on M5307 + help + Support for the Arnewsh 5307 board. + +config M5307C3 + bool "Motorola M5307C3 board support" + depends on M5307 + help + Support for the Motorola M5307C3 board. + +config SECUREEDGEMP3 + bool "SnapGear SecureEdge/MP3 platform support" + depends on M5307 + help + Support for the SnapGear SecureEdge/MP3 platform. + +config M5329EVB + bool "Freescale (Motorola) M5329EVB board support" + depends on M532x + help + Support for the Freescale (Motorola) M5329EVB board. + +config COBRA5329 + bool "senTec COBRA5329 board support" + depends on M532x + help + Support for the senTec COBRA5329 board. + +config M5407C3 + bool "Motorola M5407C3 board support" + depends on M5407 + help + Support for the Motorola M5407C3 board. + +config CLEOPATRA + bool "Feith CLEOPATRA board support" + depends on (M5307 || M5407) + help + Support for the Feith Cleopatra boards. + +config CANCam + bool "Feith CANCam board support" + depends on M5272 + help + Support for the Feith CANCam board. + +config SCALES + bool "Feith SCALES board support" + depends on M5272 + help + Support for the Feith SCALES board. + +config NETtel + bool "SecureEdge/NETtel board support" + depends on (M5206e || M5272 || M5307) + help + Support for the SnapGear NETtel/SecureEdge/SnapGear boards. + +config SNAPGEAR + bool "SnapGear router board support" + depends on NETtel + help + Special additional support for SnapGear router boards. + +config CPU16B + bool "Sneha Technologies S.L. Sarasvati board support" + depends on M5272 + help + Support for the SNEHA CPU16B board. + +config MOD5272 + bool "Netburner MOD-5272 board support" + depends on M5272 + help + Support for the Netburner MOD-5272 board. + +config SAVANTrosie1 + bool "Savant Rosie1 board support" + depends on M523x + help + Support for the Savant Rosie1 board. + +config ROMFS_FROM_ROM + bool "ROMFS image not RAM resident" + depends on (NETtel || SNAPGEAR) + help + The ROMfs filesystem will stay resident in the FLASH/ROM, not be + moved into RAM. + +config PILOT + bool + default y + depends on (PILOT3 || PILOT5) + +config ARNEWSH + bool + default y + depends on (ARN5206 || ARN5307) + +config FREESCALE + bool + default y + depends on (M5206eC3 || M5208EVB || M5235EVB || M5249C3 || M5271EVB || M5272C3 || M5275EVB || M5282EVB || M5307C3 || M5329EVB || M5407C3) + +config HW_FEITH + bool + default y + depends on (CLEOPATRA || CANCam || SCALES) + +config senTec + bool + default y + depends on (COBRA5272 || COBRA5282) + +config EMAC_INC + bool + default y + depends on (SOM5282EM) + +config SNEHA + bool + default y + depends on CPU16B + +config SAVANT + bool + default y + depends on SAVANTrosie1 + +config AVNET + bool + default y + depends on (AVNET5282) + +config UBOOT + bool "Support for U-Boot command line parameters" + help + If you say Y here kernel will try to collect command + line parameters from the initial u-boot stack. + default n + +config 4KSTACKS + bool "Use 4Kb for kernel stacks instead of 8Kb" + default y + help + If you say Y here the kernel will use a 4Kb stacksize for the + kernel stack attached to each process/thread. This facilitates + running more threads on a system and also reduces the pressure + on the VM subsystem for higher order allocations. + +config HZ + int + default 1000 if CLEOPATRA + default 100 + +comment "RAM configuration" + +config RAMBASE + hex "Address of the base of RAM" + default "0" + help + Define the address that RAM starts at. On many platforms this is + 0, the base of the address space. And this is the default. Some + platforms choose to setup their RAM at other addresses within the + processor address space. + +config RAMSIZE + hex "Size of RAM (in bytes)" + default "0x400000" + help + Define the size of the system RAM. If you select 0 then the + kernel will try to probe the RAM size at runtime. This is not + supported on all CPU types. + +config VECTORBASE + hex "Address of the base of system vectors" + default "0" + help + Define the address of the system vectors. Commonly this is + put at the start of RAM, but it doesn't have to be. On ColdFire + platforms this address is programmed into the VBR register, thus + actually setting the address to use. + +config KERNELBASE + hex "Address of the base of kernel code" + default "0x400" + help + Typically on m68k systems the kernel will not start at the base + of RAM, but usually some small offset from it. Define the start + address of the kernel here. The most common setup will have the + processor vectors at the base of RAM and then the start of the + kernel. On some platforms some RAM is reserved for boot loaders + and the kernel starts after that. The 0x400 default was based on + a system with the RAM based at address 0, and leaving enough room + for the theoretical maximum number of 256 vectors. + +choice + prompt "RAM bus width" + default RAMAUTOBIT + +config RAMAUTOBIT + bool "AUTO" + help + Select the physical RAM data bus size. Not needed on most platforms, + so you can generally choose AUTO. + +config RAM8BIT + bool "8bit" + help + Configure RAM bus to be 8 bits wide. + +config RAM16BIT + bool "16bit" + help + Configure RAM bus to be 16 bits wide. + +config RAM32BIT + bool "32bit" + help + Configure RAM bus to be 32 bits wide. + +endchoice + +comment "ROM configuration" + +config ROM + bool "Specify ROM linker regions" + default n + help + Define a ROM region for the linker script. This creates a kernel + that can be stored in flash, with possibly the text, and data + regions being copied out to RAM at startup. + +config ROMBASE + hex "Address of the base of ROM device" + default "0" + depends on ROM + help + Define the address that the ROM region starts at. Some platforms + use this to set their chip select region accordingly for the boot + device. + +config ROMVEC + hex "Address of the base of the ROM vectors" + default "0" + depends on ROM + help + This is almost always the same as the base of the ROM. Since on all + 68000 type variants the vectors are at the base of the boot device + on system startup. + +config ROMVECSIZE + hex "Size of ROM vector region (in bytes)" + default "0x400" + depends on ROM + help + Define the size of the vector region in ROM. For most 68000 + variants this would be 0x400 bytes in size. Set to 0 if you do + not want a vector region at the start of the ROM. + +config ROMSTART + hex "Address of the base of system image in ROM" + default "0x400" + depends on ROM + help + Define the start address of the system image in ROM. Commonly this + is strait after the ROM vectors. + +config ROMSIZE + hex "Size of the ROM device" + default "0x100000" + depends on ROM + help + Size of the ROM device. On some platforms this is used to setup + the chip select that controls the boot ROM device. + +choice + prompt "Kernel executes from" + ---help--- + Choose the memory type that the kernel will be running in. + +config RAMKERNEL + bool "RAM" + help + The kernel will be resident in RAM when running. + +config ROMKERNEL + bool "ROM" + help + The kernel will be resident in FLASH/ROM when running. This is + often referred to as Execute-in-Place (XIP), since the kernel + code executes from the position it is stored in the FLASH/ROM. + +endchoice + +if COLDFIRE +source "kernel/Kconfig.preempt" +endif + +source "kernel/time/Kconfig" + +source "mm/Kconfig" + +endmenu + +config ISA_DMA_API + bool + depends on !M5272 + default y + +source "drivers/pcmcia/Kconfig" + +menu "Executable file formats" + +source "fs/Kconfig.binfmt" + +endmenu + +menu "Power management options" + +config PM + bool "Power Management support" + help + Support processor power management modes + +endmenu + +source "net/Kconfig" + +source "drivers/Kconfig" + +source "fs/Kconfig" + +source "arch/m68knommu/Kconfig.debug" + +source "security/Kconfig" + +source "crypto/Kconfig" + +source "lib/Kconfig" Index: trunk/sw/linux/linux-2.6.33.1-ao68000/arch/m68knommu/platform/ao68000/head-ram.S =================================================================== --- trunk/sw/linux/linux-2.6.33.1-ao68000/arch/m68knommu/platform/ao68000/head-ram.S (nonexistent) +++ trunk/sw/linux/linux-2.6.33.1-ao68000/arch/m68knommu/platform/ao68000/head-ram.S (revision 2) @@ -0,0 +1,61 @@ +#include + + .global __main + .global __rom_start + + .global _rambase + .global _ramvec + .global _ramstart + .global _ramend + + .global splash_bits + .global _start + .global _stext + .global _edata + + .text + +_start: +_stext: + movew #0x2700, %sr /* Exceptions off! */ + + moveal #(CONFIG_RAMBASE + CONFIG_RAMSIZE), %ssp + moveal #_sbss, %a0 + moveal #_ebss, %a1 + + /* Copy 0 to %a0 until %a0 >= %a1 */ +L1: + movel #0, %a0@+ + cmpal %a0, %a1 + bhi L1 + + /* Thread */ + lea init_thread_union, %a0 + lea PAGE_SIZE(%a0), %sp + +lp: + jsr start_kernel + jmp lp +_exit: + + jmp _exit + +__main: + /* nothing */ + rts + + .data + +/* + * Set up the usable of RAM stuff. Size of RAM is determined then + * an initial stack set up at the end. + */ +.align 4 +_ramvec: +.long 0 +_rambase: +.long 0 +_ramstart: +.long _ebss +_ramend: +.long (CONFIG_RAMBASE + CONFIG_RAMSIZE) Index: trunk/sw/linux/linux-2.6.33.1-ao68000/arch/m68knommu/platform/ao68000/entry.S =================================================================== --- trunk/sw/linux/linux-2.6.33.1-ao68000/arch/m68knommu/platform/ao68000/entry.S (nonexistent) +++ trunk/sw/linux/linux-2.6.33.1-ao68000/arch/m68knommu/platform/ao68000/entry.S (revision 2) @@ -0,0 +1,302 @@ +/* + * linux/arch/m68knommu/platform/68328/entry.S + * + * Copyright (C) 1991, 1992 Linus Torvalds + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file README.legal in the main directory of this archive + * for more details. + * + * Linux/m68k support by Hamish Macdonald + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +.text + +.globl system_call +.globl resume +.globl ret_from_exception +.globl ret_from_signal +.globl sys_call_table +.globl ret_from_interrupt +.globl bad_interrupt +.globl inthandler1 +.globl inthandler2 +.globl inthandler3 +.globl inthandler4 +.globl inthandler5 +.globl inthandler6 +.globl inthandler7 + +.globl trap3 +.globl trap4 +.globl trap5 +.globl trap6 +.globl trap7 +.globl trap8 +.globl trap9 +.globl trap10 + +trap3: + move.b #0x33, (0xE0000000) + jmp trap +trap4: + move.b #0x34, (0xE0000000) + jmp trap +trap5: + move.b #0x35, (0xE0000000) + jmp trap +trap6: + move.b #0x36, (0xE0000000) + jmp trap +trap7: + move.b #0x37, (0xE0000000) + jmp trap +trap8: + move.b #0x38, (0xE0000000) + jmp trap +trap9: + move.b #0x39, (0xE0000000) + jmp trap +trap10: + move.b #0x3A, (0xE0000000) + jmp trap + +badsys: + movel #-ENOSYS,%sp@(PT_OFF_D0) + jra ret_from_exception + +do_trace: + movel #-ENOSYS,%sp@(PT_OFF_D0) /* needed for strace*/ + subql #4,%sp + SAVE_SWITCH_STACK + jbsr syscall_trace + RESTORE_SWITCH_STACK + addql #4,%sp + movel %sp@(PT_OFF_ORIG_D0),%d1 + movel #-ENOSYS,%d0 + cmpl #NR_syscalls,%d1 + jcc 1f + lsl #2,%d1 + lea sys_call_table, %a0 + jbsr %a0@(%d1) + +1: movel %d0,%sp@(PT_OFF_D0) /* save the return value */ + subql #4,%sp /* dummy return address */ + SAVE_SWITCH_STACK + jbsr syscall_trace + +ret_from_signal: + RESTORE_SWITCH_STACK + addql #4,%sp + jra ret_from_exception + +ENTRY(system_call) + SAVE_ALL + + /* save top of frame*/ + pea %sp@ + jbsr set_esp0 + addql #4,%sp + + movel %sp@(PT_OFF_ORIG_D0),%d0 + + movel %sp,%d1 /* get thread_info pointer */ + andl #-THREAD_SIZE,%d1 + movel %d1,%a2 + btst #TIF_SYSCALL_TRACE,%a2@(TI_FLAGS) + jne do_trace + cmpl #NR_syscalls,%d0 + jcc badsys + lsl #2,%d0 + lea sys_call_table,%a0 + movel %a0@(%d0), %a0 + jbsr %a0@ + movel %d0,%sp@(PT_OFF_D0) /* save the return value*/ + +ret_from_exception: + btst #5,%sp@(PT_OFF_SR) /* check if returning to kernel*/ + jeq Luser_return /* if so, skip resched, signals*/ + +Lkernel_return: + RESTORE_ALL + +Luser_return: + /* only allow interrupts when we are really the last one on the*/ + /* kernel stack, otherwise stack overflow can occur during*/ + /* heavy interrupt load*/ + andw #ALLOWINT,%sr + + movel %sp,%d1 /* get thread_info pointer */ + andl #-THREAD_SIZE,%d1 + movel %d1,%a2 + move %a2@(TI_FLAGS),%d1 /* thread_info->flags */ + andl #_TIF_WORK_MASK,%d1 + jne Lwork_to_do + RESTORE_ALL + +Lwork_to_do: + movel %a2@(TI_FLAGS),%d1 /* thread_info->flags */ + btst #TIF_NEED_RESCHED,%d1 + jne reschedule + +Lsignal_return: + subql #4,%sp /* dummy return address*/ + SAVE_SWITCH_STACK + pea %sp@(SWITCH_STACK_SIZE) + clrl %sp@- + bsrw do_signal + addql #8,%sp + RESTORE_SWITCH_STACK + addql #4,%sp +Lreturn: + RESTORE_ALL + +/* + * This is the main interrupt handler, responsible for calling process_int() + */ +inthandler1: + SAVE_ALL + movew %sp@(PT_OFF_VECTOR), %d0 + and #0x3ff, %d0 + + movel %sp,%sp@- + movel #1,%sp@- /* put vector # on stack*/ + jbsr process_int /* process the IRQ*/ +3: addql #8,%sp /* pop parameters off stack*/ + bra ret_from_interrupt + +inthandler2: + SAVE_ALL + movew %sp@(PT_OFF_VECTOR), %d0 + and #0x3ff, %d0 + + movel %sp,%sp@- + movel #2,%sp@- /* put vector # on stack*/ + jbsr process_int /* process the IRQ*/ +3: addql #8,%sp /* pop parameters off stack*/ + bra ret_from_interrupt + +inthandler3: + SAVE_ALL + movew %sp@(PT_OFF_VECTOR), %d0 + and #0x3ff, %d0 + + movel %sp,%sp@- + movel #3,%sp@- /* put vector # on stack*/ + jbsr process_int /* process the IRQ*/ +3: addql #8,%sp /* pop parameters off stack*/ + bra ret_from_interrupt + +inthandler4: + SAVE_ALL + movew %sp@(PT_OFF_VECTOR), %d0 + and #0x3ff, %d0 + + movel %sp,%sp@- + movel #4,%sp@- /* put vector # on stack*/ + jbsr process_int /* process the IRQ*/ +3: addql #8,%sp /* pop parameters off stack*/ + bra ret_from_interrupt + +inthandler5: + SAVE_ALL + movew %sp@(PT_OFF_VECTOR), %d0 + and #0x3ff, %d0 + + movel %sp,%sp@- + movel #5,%sp@- /* put vector # on stack*/ + jbsr process_int /* process the IRQ*/ +3: addql #8,%sp /* pop parameters off stack*/ + bra ret_from_interrupt + +inthandler6: + SAVE_ALL + movew %sp@(PT_OFF_VECTOR), %d0 + and #0x3ff, %d0 + + movel %sp,%sp@- + movel #6,%sp@- /* put vector # on stack*/ + jbsr process_int /* process the IRQ*/ +3: addql #8,%sp /* pop parameters off stack*/ + bra ret_from_interrupt + +inthandler7: + SAVE_ALL + movew %sp@(PT_OFF_VECTOR), %d0 + and #0x3ff, %d0 + + movel %sp,%sp@- + movel #7,%sp@- /* put vector # on stack*/ + jbsr process_int /* process the IRQ*/ +3: addql #8,%sp /* pop parameters off stack*/ + bra ret_from_interrupt + +inthandler: + SAVE_ALL + movew %sp@(PT_OFF_VECTOR), %d0 + and #0x3ff, %d0 + + movel %sp,%sp@- + movel %d0,%sp@- /* put vector # on stack*/ + jbsr process_int /* process the IRQ*/ +3: addql #8,%sp /* pop parameters off stack*/ + bra ret_from_interrupt + +ret_from_interrupt: + /*jeq 1f*/ +2: + RESTORE_ALL + + /*ALIGN*/ +1: + moveb %sp@(PT_OFF_SR), %d0 + and #7, %d0 + jhi 2b + + /* check if we need to do software interrupts */ + /*tst.l irq_stat+CPUSTAT_SOFTIRQ_PENDING*/ + jeq ret_from_exception + + pea ret_from_exception + jra do_softirq + + +/* + * Handler for uninitialized and spurious interrupts. + */ +ENTRY(bad_interrupt) + addql #1,num_spurious + rte + +/* + * Beware - when entering resume, prev (the current task) is + * in a0, next (the new task) is in a1,so don't change these + * registers until their contents are no longer needed. + */ +ENTRY(resume) + movel %a0,%d1 /* save prev thread in d1 */ + movew %sr,%a0@(TASK_THREAD+THREAD_SR) /* save sr */ + movel %usp,%a2 /* save usp */ + movel %a2,%a0@(TASK_THREAD+THREAD_USP) + + SAVE_SWITCH_STACK + movel %sp,%a0@(TASK_THREAD+THREAD_KSP) /* save kernel stack */ + movel %a1@(TASK_THREAD+THREAD_KSP),%sp /* restore new thread stack */ + RESTORE_SWITCH_STACK + + movel %a1@(TASK_THREAD+THREAD_USP),%a0 /* restore user stack */ + movel %a0,%usp + movew %a1@(TASK_THREAD+THREAD_SR),%sr /* restore thread status reg */ + rts + Index: trunk/sw/linux/linux-2.6.33.1-ao68000/arch/m68knommu/platform/ao68000/config.c =================================================================== --- trunk/sw/linux/linux-2.6.33.1-ao68000/arch/m68knommu/platform/ao68000/config.c (nonexistent) +++ trunk/sw/linux/linux-2.6.33.1-ao68000/arch/m68knommu/platform/ao68000/config.c (revision 2) @@ -0,0 +1,127 @@ +/***************************************************************************/ + +/* + * linux/arch/m68knommu/platform/ao68000/config.c + * + * Copyright (C) 1993 Hamish Macdonald + * Copyright (C) 1999 D. Jeff Dionne + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + * + * VZ Support/Fixes Evan Stawnyczy + */ + +/***************************************************************************/ + +#include +#include +#include +#include + + +// EARLY PRINTK from arch/arm/kernel/early_printk.c --------------------------------- +#include +#include + +//extern void printch(int); + +static void early_write(const char *s, unsigned n) +{ + volatile char *uart = (char *)0xE0000000; + + while(n-- > 0) { + uart[0] = s[0]; + s++; + } +} + +static void early_console_write(struct console *con, const char *s, unsigned n) +{ + early_write(s, n); +} + +static struct console early_console = { + .name = "earlycon", + .write = early_console_write, + .flags = CON_PRINTBUFFER | CON_BOOT, + .index = -1, +}; + +asmlinkage void early_printk(const char *fmt, ...) +{ + char buf[512]; + int n; + va_list ap; + + va_start(ap, fmt); + n = vscnprintf(buf, sizeof(buf), fmt, ap); + early_write(buf, n); + va_end(ap); +} + +static int __init setup_early_printk(char *buf) +{ + // blockes if called in (in_interrupt()) in kernel/printk.c + register_console(&early_console); + return 0; +} +//------------------------------------------------------------------------------------------ + + +/***************************************************************************/ + +void m68328_timer_gettod(int *year, int *mon, int *day, int *hour, int *min, int *sec) +{ + *year = *mon = *day = 1; + *hour = 2; + *min = 3; + *sec = 4; +} + +/***************************************************************************/ + +void m68328_reset (void) +{ + local_irq_disable(); + while(1) { ; } +} + +/***************************************************************************/ + +void config_BSP(char *command, int len) +{ +// setup_early_printk(command); + + printk(KERN_INFO "\nAO68000 support Aleksander Osman \n"); + + mach_gettod = m68328_timer_gettod; + mach_reset = m68328_reset; +} + +/***************************************************************************/ + +static irqreturn_t hw_tick(int irq, void *dummy) +{ + return arch_timer_interrupt(irq, dummy); +} + +/***************************************************************************/ + +static struct irqaction ao68000_timer_irq = { + .name = "timer", + .flags = IRQF_DISABLED | IRQF_TIMER, + .handler = hw_tick, +}; + +/***************************************************************************/ + + +void hw_timer_init(void) +{ + /* set ISR */ + setup_irq(0x01, &ao68000_timer_irq); +} + +/***************************************************************************/ Index: trunk/sw/linux/linux-2.6.33.1-ao68000/arch/m68knommu/platform/ao68000/Makefile =================================================================== --- trunk/sw/linux/linux-2.6.33.1-ao68000/arch/m68knommu/platform/ao68000/Makefile (nonexistent) +++ trunk/sw/linux/linux-2.6.33.1-ao68000/arch/m68knommu/platform/ao68000/Makefile (revision 2) @@ -0,0 +1,16 @@ +# +# Makefile for arch/m68knommu/platform/ao68000. +# + +head-y = head-$(MODEL).o + +obj-y += entry.o ints.o +#timers.o +obj-$(CONFIG_AO68000) += config.o + +extra-y := head.o + +$(obj)/head.o: $(obj)/$(head-y) + ln -sf $(head-y) $(obj)/head.o + +clean-files := $(obj)/head.o $(head-y) Index: trunk/sw/linux/linux-2.6.33.1-ao68000/arch/m68knommu/platform/ao68000/ints.c =================================================================== --- trunk/sw/linux/linux-2.6.33.1-ao68000/arch/m68knommu/platform/ao68000/ints.c (nonexistent) +++ trunk/sw/linux/linux-2.6.33.1-ao68000/arch/m68knommu/platform/ao68000/ints.c (revision 2) @@ -0,0 +1,142 @@ +/* + * linux/arch/m68knommu/platform/ao68000/ints.c + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + * + * Copyright 1996 Roman Zippel + * Copyright 1999 D. Jeff Dionne + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_M68328) +#include +#elif defined(CONFIG_M68EZ328) +#include +#elif defined(CONFIG_M68VZ328) +#include +#endif + +/* assembler routines */ +asmlinkage void system_call(void); +asmlinkage void buserr(void); +asmlinkage void trap(void); +asmlinkage void trap3(void); +asmlinkage void trap4(void); +asmlinkage void trap5(void); +asmlinkage void trap6(void); +asmlinkage void trap7(void); +asmlinkage void trap8(void); +asmlinkage void trap9(void); +asmlinkage void trap10(void); +asmlinkage void trap11(void); +asmlinkage void trap12(void); +asmlinkage void trap13(void); +asmlinkage void trap14(void); +asmlinkage void trap15(void); +asmlinkage void trap33(void); +asmlinkage void trap34(void); +asmlinkage void trap35(void); +asmlinkage void trap36(void); +asmlinkage void trap37(void); +asmlinkage void trap38(void); +asmlinkage void trap39(void); +asmlinkage void trap40(void); +asmlinkage void trap41(void); +asmlinkage void trap42(void); +asmlinkage void trap43(void); +asmlinkage void trap44(void); +asmlinkage void trap45(void); +asmlinkage void trap46(void); +asmlinkage void trap47(void); +asmlinkage irqreturn_t bad_interrupt(int, void *); +asmlinkage irqreturn_t inthandler(void); +asmlinkage irqreturn_t inthandler1(void); +asmlinkage irqreturn_t inthandler2(void); +asmlinkage irqreturn_t inthandler3(void); +asmlinkage irqreturn_t inthandler4(void); +asmlinkage irqreturn_t inthandler5(void); +asmlinkage irqreturn_t inthandler6(void); +asmlinkage irqreturn_t inthandler7(void); + +extern e_vector *_ramvec; + +/* The number of spurious interrupts */ +volatile unsigned int num_spurious; + +/* The 68k family did not have a good way to determine the source + * of interrupts until later in the family. The EC000 core does + * not provide the vector number on the stack, we vector everything + * into one vector and look in the blasted mask register... + * This code is designed to be fast, almost constant time, not clean! + */ +asmlinkage void process_int(int vec, struct pt_regs *fp) +{ + do_IRQ(vec, fp); +} + +static void intc_irq_unmask(unsigned int irq) +{ +} + +static void intc_irq_mask(unsigned int irq) +{ +} + +static struct irq_chip intc_irq_chip = { + .name = "M68K-INTC", + .mask = intc_irq_mask, + .unmask = intc_irq_unmask, +}; + +/* + * This function should be called during kernel startup to initialize + * the machine vector table. + */ +void __init init_IRQ(void) +{ + int i; + + _ramvec[2] = (e_vector) buserr; + + /* set up the vectors */ + _ramvec[3] = (e_vector) trap3; + _ramvec[4] = (e_vector) trap4; + _ramvec[5] = (e_vector) trap5; + _ramvec[6] = (e_vector) trap6; + _ramvec[7] = (e_vector) trap7; + _ramvec[8] = (e_vector) trap8; + _ramvec[9] = (e_vector) trap9; + _ramvec[10] = (e_vector) trap10; + + for (i = 11; i < 24; ++i) _ramvec[i] = (e_vector) trap; + + _ramvec[25] = (e_vector) inthandler1; + _ramvec[26] = (e_vector) inthandler2; + _ramvec[27] = (e_vector) inthandler3; + _ramvec[28] = (e_vector) inthandler4; + _ramvec[29] = (e_vector) inthandler5; + _ramvec[30] = (e_vector) inthandler6; + _ramvec[31] = (e_vector) inthandler7; + + _ramvec[32] = (e_vector) system_call; + + for(i=33; i<256; i++) _ramvec[i] = (e_vector) trap; //bad_interrupt + + for (i = 0; (i < NR_IRQS); i++) { + irq_desc[i].status = IRQ_DISABLED; + irq_desc[i].action = NULL; + irq_desc[i].depth = 1; + irq_desc[i].chip = &intc_irq_chip; + } +} + Index: trunk/sw/linux/linux-2.6.33.1-ao68000/arch/m68knommu/defconfig =================================================================== --- trunk/sw/linux/linux-2.6.33.1-ao68000/arch/m68knommu/defconfig (nonexistent) +++ trunk/sw/linux/linux-2.6.33.1-ao68000/arch/m68knommu/defconfig (revision 2) @@ -0,0 +1,378 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.33.1 +# Sun Mar 21 13:19:24 2010 +# +CONFIG_M68K=y +# CONFIG_MMU is not set +CONFIG_NO_DMA=y +# CONFIG_FPU is not set +CONFIG_ZONE_DMA=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_FIND_NEXT_BIT=y +# CONFIG_GENERIC_GPIO is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_TIME_LOW_RES=y +# CONFIG_GENERIC_CLOCKEVENTS is not set +CONFIG_NO_IOPORT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +# CONFIG_SYSVIPC is not set +# CONFIG_BSD_PROCESS_ACCT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +# CONFIG_BLK_DEV_INITRD is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_EMBEDDED=y +CONFIG_UID16=y +# CONFIG_KALLSYMS is not set +# CONFIG_HOTPLUG is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +# CONFIG_FUTEX is not set +# CONFIG_EPOLL is not set +# CONFIG_SIGNALFD is not set +# CONFIG_TIMERFD is not set +# CONFIG_EVENTFD is not set +CONFIG_AIO=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_VM_EVENT_COUNTERS is not set +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +# CONFIG_SLUB is not set +CONFIG_SLOB=y +# CONFIG_MMAP_ALLOW_UNINITIALIZED is not set +# CONFIG_PROFILING is not set + +# +# GCOV-based kernel profiling +# +# CONFIG_SLOW_WORK is not set +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_BASE_SMALL=0 +# CONFIG_MODULES is not set +# CONFIG_BLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +# CONFIG_FREEZER is not set + +# +# Processor type and features +# +# CONFIG_M68328 is not set +CONFIG_AO68000=y +# CONFIG_M68EZ328 is not set +# CONFIG_M68VZ328 is not set +# CONFIG_M68360 is not set +# CONFIG_M5206 is not set +# CONFIG_M5206e is not set +# CONFIG_M520x is not set +# CONFIG_M523x is not set +# CONFIG_M5249 is not set +# CONFIG_M5271 is not set +# CONFIG_M5272 is not set +# CONFIG_M5275 is not set +# CONFIG_M528x is not set +# CONFIG_M5307 is not set +# CONFIG_M532x is not set +# CONFIG_M5407 is not set +# CONFIG_CLOCK_SET is not set + +# +# Platform +# +CONFIG_TERASICDE2=y +# CONFIG_UBOOT is not set +CONFIG_4KSTACKS=y +CONFIG_HZ=100 + +# +# RAM configuration +# +CONFIG_RAMBASE=0x0 +CONFIG_RAMSIZE=0x100000 +CONFIG_VECTORBASE=0x0 +CONFIG_KERNELBASE=0x400 +CONFIG_RAMAUTOBIT=y +# CONFIG_RAM8BIT is not set +# CONFIG_RAM16BIT is not set +# CONFIG_RAM32BIT is not set + +# +# ROM configuration +# +# CONFIG_ROM is not set +CONFIG_RAMKERNEL=y +# CONFIG_ROMKERNEL is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_VIRT_TO_BUS=y +CONFIG_NOMMU_INITIAL_TRIM_EXCESS=1 +CONFIG_ISA_DMA_API=y + +# +# Executable file formats +# +CONFIG_BINFMT_FLAT=y +# CONFIG_BINFMT_ZFLAT is not set +# CONFIG_BINFMT_SHARED_FLAT is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set +# CONFIG_NET is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y + +# +# SCSI device support +# +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +# CONFIG_INPUT is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +# CONFIG_VT is not set +# CONFIG_DEVKMEM is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set +CONFIG_DE2_70_CONSOLE=y + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_UNIX98_PTYS is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_GEN_RTC is not set +# CONFIG_R3964 is not set +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_SOUND is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_RTC_CLASS is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# TI VLYNQ +# +# CONFIG_STAGING is not set + +# +# File systems +# +# CONFIG_FILE_LOCKING is not set +# CONFIG_FSNOTIFY is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY is not set +# CONFIG_INOTIFY_USER is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# Pseudo filesystems +# +# CONFIG_PROC_FS is not set +# CONFIG_SYSFS is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_MISC_FILESYSTEMS is not set +# CONFIG_NLS is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_MEMORY_INIT is not set +CONFIG_RCU_CPU_STALL_DETECTOR=y +# CONFIG_SAMPLES is not set +# CONFIG_FULLDEBUG is not set +CONFIG_BOOTPARAM=y +CONFIG_BOOTPARAM_STRING="" +# CONFIG_NO_KERNEL_MSG is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITYFS is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +# CONFIG_CRYPTO is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_GENERIC_FIND_LAST_BIT=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +# CONFIG_CRC32 is not set +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_HAS_IOMEM=y Index: trunk/sw/linux/linux-2.6.33.1-ao68000/arch/m68knommu/configs/ao68000_defconfig =================================================================== --- trunk/sw/linux/linux-2.6.33.1-ao68000/arch/m68knommu/configs/ao68000_defconfig (nonexistent) +++ trunk/sw/linux/linux-2.6.33.1-ao68000/arch/m68knommu/configs/ao68000_defconfig (revision 2) @@ -0,0 +1,378 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.33.1 +# Sun Mar 21 13:19:24 2010 +# +CONFIG_M68K=y +# CONFIG_MMU is not set +CONFIG_NO_DMA=y +# CONFIG_FPU is not set +CONFIG_ZONE_DMA=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_FIND_NEXT_BIT=y +# CONFIG_GENERIC_GPIO is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_TIME_LOW_RES=y +# CONFIG_GENERIC_CLOCKEVENTS is not set +CONFIG_NO_IOPORT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +# CONFIG_SYSVIPC is not set +# CONFIG_BSD_PROCESS_ACCT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +# CONFIG_BLK_DEV_INITRD is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_EMBEDDED=y +CONFIG_UID16=y +# CONFIG_KALLSYMS is not set +# CONFIG_HOTPLUG is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +# CONFIG_FUTEX is not set +# CONFIG_EPOLL is not set +# CONFIG_SIGNALFD is not set +# CONFIG_TIMERFD is not set +# CONFIG_EVENTFD is not set +CONFIG_AIO=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_VM_EVENT_COUNTERS is not set +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +# CONFIG_SLUB is not set +CONFIG_SLOB=y +# CONFIG_MMAP_ALLOW_UNINITIALIZED is not set +# CONFIG_PROFILING is not set + +# +# GCOV-based kernel profiling +# +# CONFIG_SLOW_WORK is not set +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_BASE_SMALL=0 +# CONFIG_MODULES is not set +# CONFIG_BLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +# CONFIG_FREEZER is not set + +# +# Processor type and features +# +# CONFIG_M68328 is not set +CONFIG_AO68000=y +# CONFIG_M68EZ328 is not set +# CONFIG_M68VZ328 is not set +# CONFIG_M68360 is not set +# CONFIG_M5206 is not set +# CONFIG_M5206e is not set +# CONFIG_M520x is not set +# CONFIG_M523x is not set +# CONFIG_M5249 is not set +# CONFIG_M5271 is not set +# CONFIG_M5272 is not set +# CONFIG_M5275 is not set +# CONFIG_M528x is not set +# CONFIG_M5307 is not set +# CONFIG_M532x is not set +# CONFIG_M5407 is not set +# CONFIG_CLOCK_SET is not set + +# +# Platform +# +CONFIG_TERASICDE2=y +# CONFIG_UBOOT is not set +CONFIG_4KSTACKS=y +CONFIG_HZ=100 + +# +# RAM configuration +# +CONFIG_RAMBASE=0x0 +CONFIG_RAMSIZE=0x100000 +CONFIG_VECTORBASE=0x0 +CONFIG_KERNELBASE=0x400 +CONFIG_RAMAUTOBIT=y +# CONFIG_RAM8BIT is not set +# CONFIG_RAM16BIT is not set +# CONFIG_RAM32BIT is not set + +# +# ROM configuration +# +# CONFIG_ROM is not set +CONFIG_RAMKERNEL=y +# CONFIG_ROMKERNEL is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_VIRT_TO_BUS=y +CONFIG_NOMMU_INITIAL_TRIM_EXCESS=1 +CONFIG_ISA_DMA_API=y + +# +# Executable file formats +# +CONFIG_BINFMT_FLAT=y +# CONFIG_BINFMT_ZFLAT is not set +# CONFIG_BINFMT_SHARED_FLAT is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set +# CONFIG_NET is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y + +# +# SCSI device support +# +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +# CONFIG_INPUT is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +# CONFIG_VT is not set +# CONFIG_DEVKMEM is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set +CONFIG_DE2_70_CONSOLE=y + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_UNIX98_PTYS is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_GEN_RTC is not set +# CONFIG_R3964 is not set +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_SOUND is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_RTC_CLASS is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# TI VLYNQ +# +# CONFIG_STAGING is not set + +# +# File systems +# +# CONFIG_FILE_LOCKING is not set +# CONFIG_FSNOTIFY is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY is not set +# CONFIG_INOTIFY_USER is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# Pseudo filesystems +# +# CONFIG_PROC_FS is not set +# CONFIG_SYSFS is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_MISC_FILESYSTEMS is not set +# CONFIG_NLS is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_MEMORY_INIT is not set +CONFIG_RCU_CPU_STALL_DETECTOR=y +# CONFIG_SAMPLES is not set +# CONFIG_FULLDEBUG is not set +CONFIG_BOOTPARAM=y +CONFIG_BOOTPARAM_STRING="" +# CONFIG_NO_KERNEL_MSG is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITYFS is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +# CONFIG_CRYPTO is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_GENERIC_FIND_LAST_BIT=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +# CONFIG_CRC32 is not set +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_HAS_IOMEM=y Index: trunk/sw/linux/linux-2.6.33.1-ao68000/arch/m68knommu/Makefile =================================================================== --- trunk/sw/linux/linux-2.6.33.1-ao68000/arch/m68knommu/Makefile (nonexistent) +++ trunk/sw/linux/linux-2.6.33.1-ao68000/arch/m68knommu/Makefile (revision 2) @@ -0,0 +1,129 @@ +# +# arch/m68knommu/Makefile +# +# This file is subject to the terms and conditions of the GNU General Public +# License. See the file "COPYING" in the main directory of this archive +# for more details. +# +# (C) Copyright 2002, Greg Ungerer +# + +KBUILD_DEFCONFIG := ao68000_defconfig + +platform-$(CONFIG_M68328) := 68328 +platform-$(CONFIG_M68EZ328) := 68EZ328 +platform-$(CONFIG_M68VZ328) := 68VZ328 +platform-$(CONFIG_M68360) := 68360 +platform-$(CONFIG_M5206) := 5206 +platform-$(CONFIG_M5206e) := 5206e +platform-$(CONFIG_M520x) := 520x +platform-$(CONFIG_M523x) := 523x +platform-$(CONFIG_M5249) := 5249 +platform-$(CONFIG_M527x) := 527x +platform-$(CONFIG_M5272) := 5272 +platform-$(CONFIG_M528x) := 528x +platform-$(CONFIG_M5307) := 5307 +platform-$(CONFIG_M532x) := 532x +platform-$(CONFIG_M5407) := 5407 +platform-$(CONFIG_AO68000) := ao68000 +PLATFORM := $(platform-y) + +board-$(CONFIG_PILOT) := pilot +board-$(CONFIG_UC5272) := UC5272 +board-$(CONFIG_UC5282) := UC5282 +board-$(CONFIG_UCSIMM) := ucsimm +board-$(CONFIG_UCDIMM) := ucdimm +board-$(CONFIG_UCQUICC) := uCquicc +board-$(CONFIG_DRAGEN2) := de2 +board-$(CONFIG_ARNEWSH) := ARNEWSH +board-$(CONFIG_FREESCALE) := FREESCALE +board-$(CONFIG_M5235EVB) := M5235EVB +board-$(CONFIG_M5271EVB) := M5271EVB +board-$(CONFIG_M5275EVB) := M5275EVB +board-$(CONFIG_M5282EVB) := M5282EVB +board-$(CONFIG_ELITE) := eLITE +board-$(CONFIG_NETtel) := NETtel +board-$(CONFIG_SECUREEDGEMP3) := MP3 +board-$(CONFIG_CLEOPATRA) := CLEOPATRA +board-$(CONFIG_senTec) := senTec +board-$(CONFIG_SNEHA) := SNEHA +board-$(CONFIG_M5208EVB) := M5208EVB +board-$(CONFIG_MOD5272) := MOD5272 +board-$(CONFIG_AVNET) := AVNET +board-$(CONFIG_SAVANT) := SAVANT +board-$(CONFIG_TERASICDE2) := TERASICDE2 + +BOARD := $(board-y) + +model-$(CONFIG_RAMKERNEL) := ram +model-$(CONFIG_ROMKERNEL) := rom +MODEL := $(model-y) + +# +# Some code support is grouped together for a common cpu-subclass (for +# example all ColdFire cpu's are very similar). Determine the sub-class +# for the selected cpu. ONLY need to define this for the non-base member +# of the family. +# +cpuclass-$(CONFIG_M5206) := coldfire +cpuclass-$(CONFIG_M5206e) := coldfire +cpuclass-$(CONFIG_M520x) := coldfire +cpuclass-$(CONFIG_M523x) := coldfire +cpuclass-$(CONFIG_M5249) := coldfire +cpuclass-$(CONFIG_M527x) := coldfire +cpuclass-$(CONFIG_M5272) := coldfire +cpuclass-$(CONFIG_M528x) := coldfire +cpuclass-$(CONFIG_M5307) := coldfire +cpuclass-$(CONFIG_M532x) := coldfire +cpuclass-$(CONFIG_M5407) := coldfire +cpuclass-$(CONFIG_M68328) := 68328 +cpuclass-$(CONFIG_M68EZ328) := 68328 +cpuclass-$(CONFIG_M68VZ328) := 68328 +cpuclass-$(CONFIG_M68360) := 68360 +cpuclass-$(CONFIG_AO68000) := ao68000 +CPUCLASS := $(cpuclass-y) + +ifneq ($(CPUCLASS),$(PLATFORM)) +CLASSDIR := arch/m68knommu/platform/$(cpuclass-y)/ +endif + +export PLATFORM BOARD MODEL CPUCLASS + +# +# Some CFLAG additions based on specific CPU type. +# +cflags-$(CONFIG_M5206) := $(call cc-option,-mcpu=5206,-m5200) +cflags-$(CONFIG_M5206e) := $(call cc-option,-m5206e,-m5200) +cflags-$(CONFIG_M520x) := $(call cc-option,-mcpu=5208,-m5200) +cflags-$(CONFIG_M523x) := $(call cc-option,-mcpu=523x,-m5307) +cflags-$(CONFIG_M5249) := $(call cc-option,-mcpu=5249,-m5200) +cflags-$(CONFIG_M5271) := $(call cc-option,-mcpu=5271,-m5307) +cflags-$(CONFIG_M5272) := $(call cc-option,-mcpu=5271,-m5200) +cflags-$(CONFIG_M5275) := $(call cc-option,-mcpu=5275,-m5307) +cflags-$(CONFIG_M528x) := $(call cc-option,-m528x,-m5307) +cflags-$(CONFIG_M5307) := $(call cc-option,-m5307,-m5200) +cflags-$(CONFIG_M532x) := $(call cc-option,-mcpu=532x,-m5307) +cflags-$(CONFIG_M5407) := $(call cc-option,-m5407,-m5200) +cflags-$(CONFIG_M68328) := -m68000 +cflags-$(CONFIG_M68EZ328) := -m68000 +cflags-$(CONFIG_M68VZ328) := -m68000 +cflags-$(CONFIG_M68360) := -m68332 +cflags-$(CONFIG_AO68000) := -m68000 + +KBUILD_AFLAGS += $(cflags-y) +KBUILD_AFLAGS += -D__uClinux__ + +KBUILD_CFLAGS += $(cflags-y) +KBUILD_CFLAGS += -D__uClinux__ +KBUILD_CFLAGS += -DUTS_SYSNAME=\"uClinux\" + +head-y := arch/m68knommu/platform/$(cpuclass-y)/head.o + +core-y += arch/m68knommu/kernel/ \ + arch/m68knommu/mm/ \ + $(CLASSDIR) \ + arch/m68knommu/platform/$(PLATFORM)/ +libs-y += arch/m68knommu/lib/ + +archclean: + Index: trunk/sw/linux/linux-2.6.33.1-ao68000/arch/m68k/include/asm/delay_no.h =================================================================== --- trunk/sw/linux/linux-2.6.33.1-ao68000/arch/m68k/include/asm/delay_no.h (nonexistent) +++ trunk/sw/linux/linux-2.6.33.1-ao68000/arch/m68k/include/asm/delay_no.h (revision 2) @@ -0,0 +1,76 @@ +#ifndef _M68KNOMMU_DELAY_H +#define _M68KNOMMU_DELAY_H + +/* + * Copyright (C) 1994 Hamish Macdonald + * Copyright (C) 2004 Greg Ungerer + */ + +#include + +static inline void __delay(unsigned long loops) +{ +#if defined(CONFIG_COLDFIRE) + /* The coldfire runs this loop at significantly different speeds + * depending upon long word alignment or not. We'll pad it to + * long word alignment which is the faster version. + * The 0x4a8e is of course a 'tstl %fp' instruction. This is better + * than using a NOP (0x4e71) instruction because it executes in one + * cycle not three and doesn't allow for an arbitary delay waiting + * for bus cycles to finish. Also fp/a6 isn't likely to cause a + * stall waiting for the register to become valid if such is added + * to the coldfire at some stage. + */ + __asm__ __volatile__ ( ".balignw 4, 0x4a8e\n\t" + "1: subql #1, %0\n\t" + "jcc 1b" + : "=d" (loops) : "0" (loops)); +#else + __asm__ __volatile__ ( "1: subql #1, %0\n\t" + "jcc 1b" + : "=d" (loops) : "0" (loops)); +#endif +} + +/* + * Ideally we use a 32*32->64 multiply to calculate the number of + * loop iterations, but the older standard 68k and ColdFire do not + * have this instruction. So for them we have a clsoe approximation + * loop using 32*32->32 multiplies only. This calculation based on + * the ARM version of delay. + * + * We want to implement: + * + * loops = (usecs * 0x10c6 * HZ * loops_per_jiffy) / 2^32 + */ + +#define HZSCALE (268435456 / (1000000/HZ)) + +extern unsigned long loops_per_jiffy; + +static inline void _udelay(unsigned long usecs) +{ +#if defined(CONFIG_M68328) || defined(CONFIG_M68EZ328) || \ + defined(CONFIG_M68VZ328) || defined(CONFIG_M68360) || \ + defined(CONFIG_COLDFIRE) || defined(CONFIG_AO68000) + __delay((((usecs * HZSCALE) >> 11) * (loops_per_jiffy >> 11)) >> 6); +#else + unsigned long tmp; + + usecs *= 4295; /* 2**32 / 1000000 */ + __asm__ ("mulul %2,%0:%1" + : "=d" (usecs), "=d" (tmp) + : "d" (usecs), "1" (loops_per_jiffy*HZ)); + __delay(usecs); +#endif +} + +/* + * Moved the udelay() function into library code, no longer inlined. + * I had to change the algorithm because we are overflowing now on + * the faster ColdFire parts. The code is a little bigger, so it makes + * sense to library it. + */ +extern void udelay(unsigned long usecs); + +#endif /* defined(_M68KNOMMU_DELAY_H) */ Index: trunk/sw/linux/linux-2.6.33.1-ao68000/drivers/serial/Kconfig =================================================================== --- trunk/sw/linux/linux-2.6.33.1-ao68000/drivers/serial/Kconfig (nonexistent) +++ trunk/sw/linux/linux-2.6.33.1-ao68000/drivers/serial/Kconfig (revision 2) @@ -0,0 +1,1499 @@ +# +# Serial device configuration +# + +menu "Serial drivers" + depends on HAS_IOMEM + +# +# The new 8250/16550 serial drivers +config SERIAL_8250 + tristate "8250/16550 and compatible serial support" + select SERIAL_CORE + ---help--- + This selects whether you want to include the driver for the standard + serial ports. The standard answer is Y. People who might say N + here are those that are setting up dedicated Ethernet WWW/FTP + servers, or users that have one of the various bus mice instead of a + serial mouse and don't intend to use their machine's standard serial + port for anything. (Note that the Cyclades and Stallion multi + serial port drivers do not need this driver built in for them to + work.) + + To compile this driver as a module, choose M here: the + module will be called 8250. + [WARNING: Do not compile this driver as a module if you are using + non-standard serial ports, since the configuration information will + be lost when the driver is unloaded. This limitation may be lifted + in the future.] + + BTW1: If you have a mouseman serial mouse which is not recognized by + the X window system, try running gpm first. + + BTW2: If you intend to use a software modem (also called Winmodem) + under Linux, forget it. These modems are crippled and require + proprietary drivers which are only available under Windows. + + Most people will say Y or M here, so that they can use serial mice, + modems and similar devices connecting to the standard serial ports. + +config DE2_70_CONSOLE + bool "Console on Terasic DE2-70 board" + select SERIAL_CORE_CONSOLE + help + Select console. + +config SERIAL_8250_CONSOLE + bool "Console on 8250/16550 and compatible serial port" + depends on SERIAL_8250=y + select SERIAL_CORE_CONSOLE + ---help--- + If you say Y here, it will be possible to use a serial port as the + system console (the system console is the device which receives all + kernel messages and warnings and which allows logins in single user + mode). This could be useful if some terminal or printer is connected + to that serial port. + + Even if you say Y here, the currently visible virtual console + (/dev/tty0) will still be used as the system console by default, but + you can alter that using a kernel command line option such as + "console=ttyS1". (Try "man bootparam" or see the documentation of + your boot loader (grub or lilo or loadlin) about how to pass options + to the kernel at boot time.) + + If you don't have a VGA card installed and you say Y here, the + kernel will automatically use the first serial line, /dev/ttyS0, as + system console. + + You can set that using a kernel command line option such as + "console=uart8250,io,0x3f8,9600n8" + "console=uart8250,mmio,0xff5e0000,115200n8". + and it will switch to normal serial console when the corresponding + port is ready. + "earlycon=uart8250,io,0x3f8,9600n8" + "earlycon=uart8250,mmio,0xff5e0000,115200n8". + it will not only setup early console. + + If unsure, say N. + +config FIX_EARLYCON_MEM + bool + depends on X86 + default y + +config SERIAL_8250_GSC + tristate + depends on SERIAL_8250 && GSC + default SERIAL_8250 + +config SERIAL_8250_PCI + tristate "8250/16550 PCI device support" if EMBEDDED + depends on SERIAL_8250 && PCI + default SERIAL_8250 + help + This builds standard PCI serial support. You may be able to + disable this feature if you only need legacy serial support. + Saves about 9K. + +config SERIAL_8250_PNP + tristate "8250/16550 PNP device support" if EMBEDDED + depends on SERIAL_8250 && PNP + default SERIAL_8250 + help + This builds standard PNP serial support. You may be able to + disable this feature if you only need legacy serial support. + +config SERIAL_8250_HP300 + tristate + depends on SERIAL_8250 && HP300 + default SERIAL_8250 + +config SERIAL_8250_CS + tristate "8250/16550 PCMCIA device support" + depends on PCMCIA && SERIAL_8250 + ---help--- + Say Y here to enable support for 16-bit PCMCIA serial devices, + including serial port cards, modems, and the modem functions of + multi-function Ethernet/modem cards. (PCMCIA- or PC-cards are + credit-card size devices often used with laptops.) + + To compile this driver as a module, choose M here: the + module will be called serial_cs. + + If unsure, say N. + +config SERIAL_8250_NR_UARTS + int "Maximum number of 8250/16550 serial ports" + depends on SERIAL_8250 + default "4" + help + Set this to the number of serial ports you want the driver + to support. This includes any ports discovered via ACPI or + PCI enumeration and any ports that may be added at run-time + via hot-plug, or any ISA multi-port serial cards. + +config SERIAL_8250_RUNTIME_UARTS + int "Number of 8250/16550 serial ports to register at runtime" + depends on SERIAL_8250 + range 0 SERIAL_8250_NR_UARTS + default "4" + help + Set this to the maximum number of serial ports you want + the kernel to register at boot time. This can be overridden + with the module parameter "nr_uarts", or boot-time parameter + 8250.nr_uarts + +config SERIAL_8250_EXTENDED + bool "Extended 8250/16550 serial driver options" + depends on SERIAL_8250 + help + If you wish to use any non-standard features of the standard "dumb" + driver, say Y here. This includes HUB6 support, shared serial + interrupts, special multiport support, support for more than the + four COM 1/2/3/4 boards, etc. + + Note that the answer to this question won't directly affect the + kernel: saying N will just cause the configurator to skip all + the questions about serial driver options. If unsure, say N. + +config SERIAL_8250_MANY_PORTS + bool "Support more than 4 legacy serial ports" + depends on SERIAL_8250_EXTENDED && !IA64 + help + Say Y here if you have dumb serial boards other than the four + standard COM 1/2/3/4 ports. This may happen if you have an AST + FourPort, Accent Async, Boca (read the Boca mini-HOWTO, available + from ), or other custom + serial port hardware which acts similar to standard serial port + hardware. If you only use the standard COM 1/2/3/4 ports, you can + say N here to save some memory. You can also say Y if you have an + "intelligent" multiport card such as Cyclades, Digiboards, etc. + +# +# Multi-port serial cards +# + +config SERIAL_8250_FOURPORT + tristate "Support Fourport cards" + depends on SERIAL_8250 != n && ISA && SERIAL_8250_MANY_PORTS + help + Say Y here if you have an AST FourPort serial board. + + To compile this driver as a module, choose M here: the module + will be called 8250_fourport. + +config SERIAL_8250_ACCENT + tristate "Support Accent cards" + depends on SERIAL_8250 != n && ISA && SERIAL_8250_MANY_PORTS + help + Say Y here if you have an Accent Async serial board. + + To compile this driver as a module, choose M here: the module + will be called 8250_accent. + +config SERIAL_8250_BOCA + tristate "Support Boca cards" + depends on SERIAL_8250 != n && ISA && SERIAL_8250_MANY_PORTS + help + Say Y here if you have a Boca serial board. Please read the Boca + mini-HOWTO, available from + + To compile this driver as a module, choose M here: the module + will be called 8250_boca. + +config SERIAL_8250_EXAR_ST16C554 + tristate "Support Exar ST16C554/554D Quad UART" + depends on SERIAL_8250 != n && ISA && SERIAL_8250_MANY_PORTS + help + The Uplogix Envoy TU301 uses this Exar Quad UART. If you are + tinkering with your Envoy TU301, or have a machine with this UART, + say Y here. + + To compile this driver as a module, choose M here: the module + will be called 8250_exar_st16c554. + +config SERIAL_8250_HUB6 + tristate "Support Hub6 cards" + depends on SERIAL_8250 != n && ISA && SERIAL_8250_MANY_PORTS + help + Say Y here if you have a HUB6 serial board. + + To compile this driver as a module, choose M here: the module + will be called 8250_hub6. + +config SERIAL_8250_SHARE_IRQ + bool "Support for sharing serial interrupts" + depends on SERIAL_8250_EXTENDED + help + Some serial boards have hardware support which allows multiple dumb + serial ports on the same board to share a single IRQ. To enable + support for this in the serial driver, say Y here. + +config SERIAL_8250_DETECT_IRQ + bool "Autodetect IRQ on standard ports (unsafe)" + depends on SERIAL_8250_EXTENDED + help + Say Y here if you want the kernel to try to guess which IRQ + to use for your serial port. + + This is considered unsafe; it is far better to configure the IRQ in + a boot script using the setserial command. + + If unsure, say N. + +config SERIAL_8250_RSA + bool "Support RSA serial ports" + depends on SERIAL_8250_EXTENDED + help + ::: To be written ::: + +config SERIAL_8250_MCA + tristate "Support 8250-type ports on MCA buses" + depends on SERIAL_8250 != n && MCA + help + Say Y here if you have a MCA serial ports. + + To compile this driver as a module, choose M here: the module + will be called 8250_mca. + +config SERIAL_8250_ACORN + tristate "Acorn expansion card serial port support" + depends on ARCH_ACORN && SERIAL_8250 + help + If you have an Atomwide Serial card or Serial Port card for an Acorn + system, say Y to this option. The driver can handle 1, 2, or 3 port + cards. If unsure, say N. + +config SERIAL_8250_AU1X00 + bool "Au1x00 serial port support" + depends on SERIAL_8250 != n && SOC_AU1X00 + help + If you have an Au1x00 SOC based board and want to use the serial port, + say Y to this option. The driver can handle up to 4 serial ports, + depending on the SOC. If unsure, say N. + +config SERIAL_8250_RM9K + bool "Support for MIPS RM9xxx integrated serial port" + depends on SERIAL_8250 != n && SERIAL_RM9000 + select SERIAL_8250_SHARE_IRQ + help + Selecting this option will add support for the integrated serial + port hardware found on MIPS RM9122 and similar processors. + If unsure, say N. + +comment "Non-8250 serial port support" + +config SERIAL_AMBA_PL010 + tristate "ARM AMBA PL010 serial port support" + depends on ARM_AMBA && (BROKEN || !ARCH_VERSATILE) + select SERIAL_CORE + help + This selects the ARM(R) AMBA(R) PrimeCell PL010 UART. If you have + an Integrator/AP or Integrator/PP2 platform, or if you have a + Cirrus Logic EP93xx CPU, say Y or M here. + + If unsure, say N. + +config SERIAL_AMBA_PL010_CONSOLE + bool "Support for console on AMBA serial port" + depends on SERIAL_AMBA_PL010=y + select SERIAL_CORE_CONSOLE + ---help--- + Say Y here if you wish to use an AMBA PrimeCell UART as the system + console (the system console is the device which receives all kernel + messages and warnings and which allows logins in single user mode). + + Even if you say Y here, the currently visible framebuffer console + (/dev/tty0) will still be used as the system console by default, but + you can alter that using a kernel command line option such as + "console=ttyAM0". (Try "man bootparam" or see the documentation of + your boot loader (lilo or loadlin) about how to pass options to the + kernel at boot time.) + +config SERIAL_AMBA_PL011 + tristate "ARM AMBA PL011 serial port support" + depends on ARM_AMBA + select SERIAL_CORE + help + This selects the ARM(R) AMBA(R) PrimeCell PL011 UART. If you have + an Integrator/PP2, Integrator/CP or Versatile platform, say Y or M + here. + + If unsure, say N. + +config SERIAL_AMBA_PL011_CONSOLE + bool "Support for console on AMBA serial port" + depends on SERIAL_AMBA_PL011=y + select SERIAL_CORE_CONSOLE + ---help--- + Say Y here if you wish to use an AMBA PrimeCell UART as the system + console (the system console is the device which receives all kernel + messages and warnings and which allows logins in single user mode). + + Even if you say Y here, the currently visible framebuffer console + (/dev/tty0) will still be used as the system console by default, but + you can alter that using a kernel command line option such as + "console=ttyAMA0". (Try "man bootparam" or see the documentation of + your boot loader (lilo or loadlin) about how to pass options to the + kernel at boot time.) + +config SERIAL_SB1250_DUART + tristate "BCM1xxx on-chip DUART serial support" + depends on SIBYTE_SB1xxx_SOC=y + select SERIAL_CORE + default y + ---help--- + Support for the asynchronous serial interface (DUART) included in + the BCM1250 and derived System-On-a-Chip (SOC) devices. Note that + the letter D in DUART stands for "dual", which is how the device + is implemented. Depending on the SOC configuration there may be + one or more DUARTs available of which all are handled. + + If unsure, say Y. To compile this driver as a module, choose M here: + the module will be called sb1250-duart. + +config SERIAL_SB1250_DUART_CONSOLE + bool "Support for console on a BCM1xxx DUART serial port" + depends on SERIAL_SB1250_DUART=y + select SERIAL_CORE_CONSOLE + default y + ---help--- + If you say Y here, it will be possible to use a serial port as the + system console (the system console is the device which receives all + kernel messages and warnings and which allows logins in single user + mode). + + If unsure, say Y. + +config SERIAL_ATMEL + bool "AT91 / AT32 on-chip serial port support" + depends on (ARM && ARCH_AT91) || AVR32 + select SERIAL_CORE + help + This enables the driver for the on-chip UARTs of the Atmel + AT91 and AT32 processors. + +config SERIAL_ATMEL_CONSOLE + bool "Support for console on AT91 / AT32 serial port" + depends on SERIAL_ATMEL=y + select SERIAL_CORE_CONSOLE + help + Say Y here if you wish to use an on-chip UART on a Atmel + AT91 or AT32 processor as the system console (the system + console is the device which receives all kernel messages and + warnings and which allows logins in single user mode). + +config SERIAL_ATMEL_PDC + bool "Support DMA transfers on AT91 / AT32 serial port" + depends on SERIAL_ATMEL + default y + help + Say Y here if you wish to use the PDC to do DMA transfers to + and from the Atmel AT91 / AT32 serial port. In order to + actually use DMA transfers, make sure that the use_dma_tx + and use_dma_rx members in the atmel_uart_data struct is set + appropriately for each port. + + Note that break and error handling currently doesn't work + properly when DMA is enabled. Make sure that ports where + this matters don't use DMA. + +config SERIAL_ATMEL_TTYAT + bool "Install as device ttyATn instead of ttySn" + depends on SERIAL_ATMEL=y + help + Say Y here if you wish to have the internal AT91 / AT32 UARTs + appear as /dev/ttyATn (major 204, minor starting at 154) + instead of the normal /dev/ttySn (major 4, minor starting at + 64). This is necessary if you also want other UARTs, such as + external 8250/16C550 compatible UARTs. + The ttySn nodes are legally reserved for the 8250 serial driver + but are often misused by other serial drivers. + + To use this, you should create suitable ttyATn device nodes in + /dev/, and pass "console=ttyATn" to the kernel. + + Say Y if you have an external 8250/16C550 UART. If unsure, say N. + +config SERIAL_KS8695 + bool "Micrel KS8695 (Centaur) serial port support" + depends on ARCH_KS8695 + select SERIAL_CORE + help + This selects the Micrel Centaur KS8695 UART. Say Y here. + +config SERIAL_KS8695_CONSOLE + bool "Support for console on KS8695 (Centaur) serial port" + depends on SERIAL_KS8695=y + select SERIAL_CORE_CONSOLE + help + Say Y here if you wish to use a KS8695 (Centaur) UART as the + system console (the system console is the device which + receives all kernel messages and warnings and which allows + logins in single user mode). + +config SERIAL_CLPS711X + tristate "CLPS711X serial port support" + depends on ARM && ARCH_CLPS711X + select SERIAL_CORE + help + ::: To be written ::: + +config SERIAL_CLPS711X_CONSOLE + bool "Support for console on CLPS711X serial port" + depends on SERIAL_CLPS711X=y + select SERIAL_CORE_CONSOLE + help + Even if you say Y here, the currently visible virtual console + (/dev/tty0) will still be used as the system console by default, but + you can alter that using a kernel command line option such as + "console=ttyCL1". (Try "man bootparam" or see the documentation of + your boot loader (lilo or loadlin) about how to pass options to the + kernel at boot time.) + +config SERIAL_SAMSUNG + tristate "Samsung SoC serial support" + depends on ARM && PLAT_S3C + select SERIAL_CORE + help + Support for the on-chip UARTs on the Samsung S3C24XX series CPUs, + providing /dev/ttySAC0, 1 and 2 (note, some machines may not + provide all of these ports, depending on how the serial port + pins are configured. + +config SERIAL_SAMSUNG_UARTS + int + depends on ARM && PLAT_S3C + default 2 if ARCH_S3C2400 + default 4 if ARCH_S5PC1XX || ARCH_S3C64XX || CPU_S3C2443 + default 3 + help + Select the number of available UART ports for the Samsung S3C + serial driver + +config SERIAL_SAMSUNG_DEBUG + bool "Samsung SoC serial debug" + depends on SERIAL_SAMSUNG && DEBUG_LL + help + Add support for debugging the serial driver. Since this is + generally being used as a console, we use our own output + routines that go via the low-level debug printascii() + function. + +config SERIAL_SAMSUNG_CONSOLE + bool "Support for console on Samsung SoC serial port" + depends on SERIAL_SAMSUNG=y + select SERIAL_CORE_CONSOLE + help + Allow selection of the S3C24XX on-board serial ports for use as + an virtual console. + + Even if you say Y here, the currently visible virtual console + (/dev/tty0) will still be used as the system console by default, but + you can alter that using a kernel command line option such as + "console=ttySACx". (Try "man bootparam" or see the documentation of + your boot loader about how to pass options to the kernel at + boot time.) + +config SERIAL_S3C2400 + tristate "Samsung S3C2410 Serial port support" + depends on ARM && SERIAL_SAMSUNG && CPU_S3C2400 + default y if CPU_S3C2400 + help + Serial port support for the Samsung S3C2400 SoC + +config SERIAL_S3C2410 + tristate "Samsung S3C2410 Serial port support" + depends on SERIAL_SAMSUNG && CPU_S3C2410 + default y if CPU_S3C2410 + help + Serial port support for the Samsung S3C2410 SoC + +config SERIAL_S3C2412 + tristate "Samsung S3C2412/S3C2413 Serial port support" + depends on SERIAL_SAMSUNG && CPU_S3C2412 + default y if CPU_S3C2412 + help + Serial port support for the Samsung S3C2412 and S3C2413 SoC + +config SERIAL_S3C2440 + tristate "Samsung S3C2440/S3C2442 Serial port support" + depends on SERIAL_SAMSUNG && (CPU_S3C2440 || CPU_S3C2442) + default y if CPU_S3C2440 + default y if CPU_S3C2442 + help + Serial port support for the Samsung S3C2440 and S3C2442 SoC + +config SERIAL_S3C24A0 + tristate "Samsung S3C24A0 Serial port support" + depends on SERIAL_SAMSUNG && CPU_S3C24A0 + default y if CPU_S3C24A0 + help + Serial port support for the Samsung S3C24A0 SoC + +config SERIAL_S3C6400 + tristate "Samsung S3C6400/S3C6410 Serial port support" + depends on SERIAL_SAMSUNG && (CPU_S3C6400 || CPU_S3C6410) + default y + help + Serial port support for the Samsung S3C6400 and S3C6410 + SoCs + +config SERIAL_S5PC100 + tristate "Samsung S5PC100 Serial port support" + depends on SERIAL_SAMSUNG && CPU_S5PC100 + default y + help + Serial port support for the Samsung S5PC100 SoCs + +config SERIAL_MAX3100 + tristate "MAX3100 support" + depends on SPI + select SERIAL_CORE + help + MAX3100 chip support + +config SERIAL_DZ + bool "DECstation DZ serial driver" + depends on MACH_DECSTATION && 32BIT + select SERIAL_CORE + default y + ---help--- + DZ11-family serial controllers for DECstations and VAXstations, + including the DC7085, M7814, and M7819. + +config SERIAL_DZ_CONSOLE + bool "Support console on DECstation DZ serial driver" + depends on SERIAL_DZ=y + select SERIAL_CORE_CONSOLE + default y + ---help--- + If you say Y here, it will be possible to use a serial port as the + system console (the system console is the device which receives all + kernel messages and warnings and which allows logins in single user + mode). + + Note that the firmware uses ttyS3 as the serial console on + DECstations that use this driver. + + If unsure, say Y. + +config SERIAL_ZS + tristate "DECstation Z85C30 serial support" + depends on MACH_DECSTATION + select SERIAL_CORE + default y + ---help--- + Support for the Zilog 85C350 serial communications controller used + for serial ports in newer DECstation systems. These include the + DECsystem 5900 and all models of the DECstation and DECsystem 5000 + systems except from model 200. + + If unsure, say Y. To compile this driver as a module, choose M here: + the module will be called zs. + +config SERIAL_ZS_CONSOLE + bool "Support for console on a DECstation Z85C30 serial port" + depends on SERIAL_ZS=y + select SERIAL_CORE_CONSOLE + default y + ---help--- + If you say Y here, it will be possible to use a serial port as the + system console (the system console is the device which receives all + kernel messages and warnings and which allows logins in single user + mode). + + Note that the firmware uses ttyS1 as the serial console on the + Maxine and ttyS3 on the others using this driver. + + If unsure, say Y. + +config SERIAL_21285 + tristate "DC21285 serial port support" + depends on ARM && FOOTBRIDGE + select SERIAL_CORE + help + If you have a machine based on a 21285 (Footbridge) StrongARM(R)/ + PCI bridge you can enable its onboard serial port by enabling this + option. + +config SERIAL_21285_CONSOLE + bool "Console on DC21285 serial port" + depends on SERIAL_21285=y + select SERIAL_CORE_CONSOLE + help + If you have enabled the serial port on the 21285 footbridge you can + make it the console by answering Y to this option. + + Even if you say Y here, the currently visible virtual console + (/dev/tty0) will still be used as the system console by default, but + you can alter that using a kernel command line option such as + "console=ttyFB". (Try "man bootparam" or see the documentation of + your boot loader (lilo or loadlin) about how to pass options to the + kernel at boot time.) + +config SERIAL_MPSC + bool "Marvell MPSC serial port support" + depends on PPC32 && MV64X60 + select SERIAL_CORE + help + Say Y here if you want to use the Marvell MPSC serial controller. + +config SERIAL_MPSC_CONSOLE + bool "Support for console on Marvell MPSC serial port" + depends on SERIAL_MPSC + select SERIAL_CORE_CONSOLE + help + Say Y here if you want to support a serial console on a Marvell MPSC. + +config SERIAL_PXA + bool "PXA serial port support" + depends on ARCH_PXA || ARCH_MMP + select SERIAL_CORE + help + If you have a machine based on an Intel XScale PXA2xx CPU you + can enable its onboard serial ports by enabling this option. + +config SERIAL_PXA_CONSOLE + bool "Console on PXA serial port" + depends on SERIAL_PXA + select SERIAL_CORE_CONSOLE + help + If you have enabled the serial port on the Intel XScale PXA + CPU you can make it the console by answering Y to this option. + + Even if you say Y here, the currently visible virtual console + (/dev/tty0) will still be used as the system console by default, but + you can alter that using a kernel command line option such as + "console=ttySA0". (Try "man bootparam" or see the documentation of + your boot loader (lilo or loadlin) about how to pass options to the + kernel at boot time.) + +config SERIAL_SA1100 + bool "SA1100 serial port support" + depends on ARM && ARCH_SA1100 + select SERIAL_CORE + help + If you have a machine based on a SA1100/SA1110 StrongARM(R) CPU you + can enable its onboard serial port by enabling this option. + Please read for further + info. + +config SERIAL_SA1100_CONSOLE + bool "Console on SA1100 serial port" + depends on SERIAL_SA1100 + select SERIAL_CORE_CONSOLE + help + If you have enabled the serial port on the SA1100/SA1110 StrongARM + CPU you can make it the console by answering Y to this option. + + Even if you say Y here, the currently visible virtual console + (/dev/tty0) will still be used as the system console by default, but + you can alter that using a kernel command line option such as + "console=ttySA0". (Try "man bootparam" or see the documentation of + your boot loader (lilo or loadlin) about how to pass options to the + kernel at boot time.) + +config SERIAL_BFIN + tristate "Blackfin serial port support" + depends on BLACKFIN + select SERIAL_CORE + select SERIAL_BFIN_UART0 if (BF531 || BF532 || BF533 || BF561) + help + Add support for the built-in UARTs on the Blackfin. + + To compile this driver as a module, choose M here: the + module will be called bfin_5xx. + +config SERIAL_BFIN_CONSOLE + bool "Console on Blackfin serial port" + depends on SERIAL_BFIN=y + select SERIAL_CORE_CONSOLE + +choice + prompt "UART Mode" + depends on SERIAL_BFIN + default SERIAL_BFIN_DMA + help + This driver supports the built-in serial ports of the Blackfin family + of CPUs + +config SERIAL_BFIN_DMA + bool "DMA mode" + depends on !DMA_UNCACHED_NONE && KGDB_SERIAL_CONSOLE=n + help + This driver works under DMA mode. If this option is selected, the + blackfin simple dma driver is also enabled. + +config SERIAL_BFIN_PIO + bool "PIO mode" + help + This driver works under PIO mode. + +endchoice + +config SERIAL_BFIN_UART0 + bool "Enable UART0" + depends on SERIAL_BFIN + help + Enable UART0 + +config BFIN_UART0_CTSRTS + bool "Enable UART0 hardware flow control" + depends on SERIAL_BFIN_UART0 + help + Enable hardware flow control in the driver. Using GPIO emulate the CTS/RTS + signal. + +config UART0_CTS_PIN + int "UART0 CTS pin" + depends on BFIN_UART0_CTSRTS && !BF548 + default 23 + help + The default pin is GPIO_GP7. + Refer to arch/blackfin/mach-*/include/mach/gpio.h to see the GPIO map. + +config UART0_RTS_PIN + int "UART0 RTS pin" + depends on BFIN_UART0_CTSRTS && !BF548 + default 22 + help + The default pin is GPIO_GP6. + Refer to arch/blackfin/mach-*/include/mach/gpio.h to see the GPIO map. + +config SERIAL_BFIN_UART1 + bool "Enable UART1" + depends on SERIAL_BFIN && (!BF531 && !BF532 && !BF533 && !BF561) + help + Enable UART1 + +config BFIN_UART1_CTSRTS + bool "Enable UART1 hardware flow control" + depends on SERIAL_BFIN_UART1 + help + Enable hardware flow control in the driver. Using GPIO emulate the CTS/RTS + signal. + +config UART1_CTS_PIN + int "UART1 CTS pin" + depends on BFIN_UART1_CTSRTS && !BF548 + default -1 + help + Refer to arch/blackfin/mach-*/include/mach/gpio.h to see the GPIO map. + +config UART1_RTS_PIN + int "UART1 RTS pin" + depends on BFIN_UART1_CTSRTS && !BF548 + default -1 + help + Refer to arch/blackfin/mach-*/include/mach/gpio.h to see the GPIO map. + +config SERIAL_BFIN_UART2 + bool "Enable UART2" + depends on SERIAL_BFIN && (BF54x || BF538 || BF539) + help + Enable UART2 + +config BFIN_UART2_CTSRTS + bool "Enable UART2 hardware flow control" + depends on SERIAL_BFIN_UART2 + help + Enable hardware flow control in the driver. Using GPIO emulate the CTS/RTS + signal. + +config UART2_CTS_PIN + int "UART2 CTS pin" + depends on BFIN_UART2_CTSRTS && !BF548 + default -1 + help + Refer to arch/blackfin/mach-*/include/mach/gpio.h to see the GPIO map. + +config UART2_RTS_PIN + int "UART2 RTS pin" + depends on BFIN_UART2_CTSRTS && !BF548 + default -1 + help + Refer to arch/blackfin/mach-*/include/mach/gpio.h to see the GPIO map. + +config SERIAL_BFIN_UART3 + bool "Enable UART3" + depends on SERIAL_BFIN && (BF54x) + help + Enable UART3 + +config BFIN_UART3_CTSRTS + bool "Enable UART3 hardware flow control" + depends on SERIAL_BFIN_UART3 + help + Enable hardware flow control in the driver. Using GPIO emulate the CTS/RTS + signal. + +config UART3_CTS_PIN + int "UART3 CTS pin" + depends on BFIN_UART3_CTSRTS && !BF548 + default -1 + help + Refer to arch/blackfin/mach-*/include/mach/gpio.h to see the GPIO map. + +config UART3_RTS_PIN + int "UART3 RTS pin" + depends on BFIN_UART3_CTSRTS && !BF548 + default -1 + help + Refer to arch/blackfin/mach-*/include/mach/gpio.h to see the GPIO map. + +config SERIAL_IMX + bool "IMX serial port support" + depends on ARM && (ARCH_IMX || ARCH_MXC) + select SERIAL_CORE + select RATIONAL + help + If you have a machine based on a Motorola IMX CPU you + can enable its onboard serial port by enabling this option. + +config SERIAL_IMX_CONSOLE + bool "Console on IMX serial port" + depends on SERIAL_IMX + select SERIAL_CORE_CONSOLE + help + If you have enabled the serial port on the Motorola IMX + CPU you can make it the console by answering Y to this option. + + Even if you say Y here, the currently visible virtual console + (/dev/tty0) will still be used as the system console by default, but + you can alter that using a kernel command line option such as + "console=ttySA0". (Try "man bootparam" or see the documentation of + your boot loader (lilo or loadlin) about how to pass options to the + kernel at boot time.) + +config SERIAL_UARTLITE + tristate "Xilinx uartlite serial port support" + depends on PPC32 || MICROBLAZE || MFD_TIMBERDALE + select SERIAL_CORE + help + Say Y here if you want to use the Xilinx uartlite serial controller. + + To compile this driver as a module, choose M here: the + module will be called uartlite. + +config SERIAL_UARTLITE_CONSOLE + bool "Support for console on Xilinx uartlite serial port" + depends on SERIAL_UARTLITE=y + select SERIAL_CORE_CONSOLE + help + Say Y here if you wish to use a Xilinx uartlite as the system + console (the system console is the device which receives all kernel + messages and warnings and which allows logins in single user mode). + +config SERIAL_SUNCORE + bool + depends on SPARC + select SERIAL_CORE + select SERIAL_CORE_CONSOLE + default y + +config SERIAL_SUNZILOG + tristate "Sun Zilog8530 serial support" + depends on SPARC + help + This driver supports the Zilog8530 serial ports found on many Sparc + systems. Say Y or M if you want to be able to these serial ports. + +config SERIAL_SUNZILOG_CONSOLE + bool "Console on Sun Zilog8530 serial port" + depends on SERIAL_SUNZILOG=y + help + If you would like to be able to use the Zilog8530 serial port + on your Sparc system as the console, you can do so by answering + Y to this option. + +config SERIAL_SUNSU + tristate "Sun SU serial support" + depends on SPARC && PCI + help + This driver supports the 8250 serial ports that run the keyboard and + mouse on (PCI) UltraSPARC systems. Say Y or M if you want to be able + to these serial ports. + +config SERIAL_SUNSU_CONSOLE + bool "Console on Sun SU serial port" + depends on SERIAL_SUNSU=y + help + If you would like to be able to use the SU serial port + on your Sparc system as the console, you can do so by answering + Y to this option. + +config SERIAL_MUX + tristate "Serial MUX support" + depends on GSC + select SERIAL_CORE + default y + ---help--- + Saying Y here will enable the hardware MUX serial driver for + the Nova, K class systems and D class with a 'remote control card'. + The hardware MUX is not 8250/16550 compatible therefore the + /dev/ttyB0 device is shared between the Serial MUX and the PDC + software console. The following steps need to be completed to use + the Serial MUX: + + 1. create the device entry (mknod /dev/ttyB0 c 11 0) + 2. Edit the /etc/inittab to start a getty listening on /dev/ttyB0 + 3. Add device ttyB0 to /etc/securetty (if you want to log on as + root on this console.) + 4. Change the kernel command console parameter to: console=ttyB0 + +config SERIAL_MUX_CONSOLE + bool "Support for console on serial MUX" + depends on SERIAL_MUX=y + select SERIAL_CORE_CONSOLE + default y + +config PDC_CONSOLE + bool "PDC software console support" + depends on PARISC && !SERIAL_MUX && VT + default n + help + Saying Y here will enable the software based PDC console to be + used as the system console. This is useful for machines in + which the hardware based console has not been written yet. The + following steps must be competed to use the PDC console: + + 1. create the device entry (mknod /dev/ttyB0 c 11 0) + 2. Edit the /etc/inittab to start a getty listening on /dev/ttyB0 + 3. Add device ttyB0 to /etc/securetty (if you want to log on as + root on this console.) + 4. Change the kernel command console parameter to: console=ttyB0 + +config SERIAL_SUNSAB + tristate "Sun Siemens SAB82532 serial support" + depends on SPARC && PCI + help + This driver supports the Siemens SAB82532 DUSCC serial ports on newer + (PCI) UltraSPARC systems. Say Y or M if you want to be able to these + serial ports. + +config SERIAL_SUNSAB_CONSOLE + bool "Console on Sun Siemens SAB82532 serial port" + depends on SERIAL_SUNSAB=y + help + If you would like to be able to use the SAB82532 serial port + on your Sparc system as the console, you can do so by answering + Y to this option. + +config SERIAL_SUNHV + bool "Sun4v Hypervisor Console support" + depends on SPARC64 + help + This driver supports the console device found on SUN4V Sparc + systems. Say Y if you want to be able to use this device. + +config SERIAL_IP22_ZILOG + tristate "SGI Zilog8530 serial support" + depends on SGI_HAS_ZILOG + select SERIAL_CORE + help + This driver supports the Zilog8530 serial ports found on SGI + systems. Say Y or M if you want to be able to these serial ports. + +config SERIAL_IP22_ZILOG_CONSOLE + bool "Console on SGI Zilog8530 serial port" + depends on SERIAL_IP22_ZILOG=y + select SERIAL_CORE_CONSOLE + +config SERIAL_SH_SCI + tristate "SuperH SCI(F) serial port support" + depends on HAVE_CLK && (SUPERH || H8300) + select SERIAL_CORE + +config SERIAL_SH_SCI_NR_UARTS + int "Maximum number of SCI(F) serial ports" + depends on SERIAL_SH_SCI + default "2" + +config SERIAL_SH_SCI_CONSOLE + bool "Support for console on SuperH SCI(F)" + depends on SERIAL_SH_SCI=y + select SERIAL_CORE_CONSOLE + +config SERIAL_PNX8XXX + bool "Enable PNX8XXX SoCs' UART Support" + depends on MIPS && (SOC_PNX8550 || SOC_PNX833X) + select SERIAL_CORE + help + If you have a MIPS-based Philips SoC such as PNX8550 or PNX8330 + and you want to use serial ports, say Y. Otherwise, say N. + +config SERIAL_PNX8XXX_CONSOLE + bool "Enable PNX8XX0 serial console" + depends on SERIAL_PNX8XXX + select SERIAL_CORE_CONSOLE + help + If you have a MIPS-based Philips SoC such as PNX8550 or PNX8330 + and you want to use serial console, say Y. Otherwise, say N. + +config SERIAL_CORE + tristate + +config SERIAL_CORE_CONSOLE + bool + +config CONSOLE_POLL + bool + +config SERIAL_68328 + bool "68328 serial support" + depends on M68328 || M68EZ328 || M68VZ328 + help + This driver supports the built-in serial port of the Motorola 68328 + (standard, EZ and VZ varieties). + +config SERIAL_68328_RTS_CTS + bool "Support RTS/CTS on 68328 serial port" + depends on SERIAL_68328 + +config SERIAL_MCF + bool "Coldfire serial support" + depends on COLDFIRE + select SERIAL_CORE + help + This serial driver supports the Freescale Coldfire serial ports. + +config SERIAL_MCF_BAUDRATE + int "Default baudrate for Coldfire serial ports" + depends on SERIAL_MCF + default 19200 + help + This setting lets you define what the default baudrate is for the + ColdFire serial ports. The usual default varies from board to board, + and this setting is a way of catering for that. + +config SERIAL_MCF_CONSOLE + bool "Coldfire serial console support" + depends on SERIAL_MCF + select SERIAL_CORE_CONSOLE + help + Enable a ColdFire internal serial port to be the system console. + +config SERIAL_68360_SMC + bool "68360 SMC uart support" + depends on M68360 + help + This driver supports the SMC serial ports of the Motorola 68360 CPU. + +config SERIAL_68360_SCC + bool "68360 SCC uart support" + depends on M68360 + help + This driver supports the SCC serial ports of the Motorola 68360 CPU. + +config SERIAL_68360 + bool + depends on SERIAL_68360_SMC || SERIAL_68360_SCC + default y + +config SERIAL_PMACZILOG + tristate "PowerMac z85c30 ESCC support" + depends on PPC_OF && PPC_PMAC + select SERIAL_CORE + help + This driver supports the Zilog z85C30 serial ports found on + PowerMac machines. + Say Y or M if you want to be able to these serial ports. + +config SERIAL_PMACZILOG_TTYS + bool "Use ttySn device nodes for Zilog z85c30" + depends on SERIAL_PMACZILOG + help + The pmac_zilog driver for the z85C30 chip on many powermacs + historically used the device numbers for /dev/ttySn. The + 8250 serial port driver also uses these numbers, which means + the two drivers being unable to coexist; you could not use + both z85C30 and 8250 type ports at the same time. + + If this option is not selected, the pmac_zilog driver will + use the device numbers allocated for /dev/ttyPZn. This allows + the pmac_zilog and 8250 drivers to co-exist, but may cause + existing userspace setups to break. Programs that need to + access the built-in serial ports on powermacs will need to + be reconfigured to use /dev/ttyPZn instead of /dev/ttySn. + + If you enable this option, any z85c30 ports in the system will + be registered as ttyS0 onwards as in the past, and you will be + unable to use the 8250 module for PCMCIA or other 16C550-style + UARTs. + + Say N unless you need the z85c30 ports on your powermac + to appear as /dev/ttySn. + +config SERIAL_PMACZILOG_CONSOLE + bool "Console on PowerMac z85c30 serial port" + depends on SERIAL_PMACZILOG=y + select SERIAL_CORE_CONSOLE + help + If you would like to be able to use the z85c30 serial port + on your PowerMac as the console, you can do so by answering + Y to this option. + +config SERIAL_LH7A40X + tristate "Sharp LH7A40X embedded UART support" + depends on ARM && ARCH_LH7A40X + select SERIAL_CORE + help + This enables support for the three on-board UARTs of the + Sharp LH7A40X series CPUs. Choose Y or M. + +config SERIAL_LH7A40X_CONSOLE + bool "Support for console on Sharp LH7A40X serial port" + depends on SERIAL_LH7A40X=y + select SERIAL_CORE_CONSOLE + help + Say Y here if you wish to use one of the serial ports as the + system console--the system console is the device which + receives all kernel messages and warnings and which allows + logins in single user mode. + + Even if you say Y here, the currently visible framebuffer console + (/dev/tty0) will still be used as the default system console, but + you can alter that using a kernel command line, for example + "console=ttyAM1". + +config SERIAL_CPM + tristate "CPM SCC/SMC serial port support" + depends on CPM2 || 8xx + select SERIAL_CORE + help + This driver supports the SCC and SMC serial ports on Motorola + embedded PowerPC that contain a CPM1 (8xx) or CPM2 (8xxx) + +config SERIAL_CPM_CONSOLE + bool "Support for console on CPM SCC/SMC serial port" + depends on SERIAL_CPM=y + select SERIAL_CORE_CONSOLE + help + Say Y here if you wish to use a SCC or SMC CPM UART as the system + console (the system console is the device which receives all kernel + messages and warnings and which allows logins in single user mode). + + Even if you say Y here, the currently visible framebuffer console + (/dev/tty0) will still be used as the system console by default, but + you can alter that using a kernel command line option such as + "console=ttyCPM0". (Try "man bootparam" or see the documentation of + your boot loader (lilo or loadlin) about how to pass options to the + kernel at boot time.) + +config SERIAL_SGI_L1_CONSOLE + bool "SGI Altix L1 serial console support" + depends on IA64_GENERIC || IA64_SGI_SN2 + select SERIAL_CORE + select SERIAL_CORE_CONSOLE + help + If you have an SGI Altix and you would like to use the system + controller serial port as your console (you want this!), + say Y. Otherwise, say N. + +config SERIAL_MPC52xx + tristate "Freescale MPC52xx/MPC512x family PSC serial support" + depends on PPC_MPC52xx || PPC_MPC512x + select SERIAL_CORE + help + This driver supports MPC52xx and MPC512x PSC serial ports. If you would + like to use them, you must answer Y or M to this option. Note that + for use as console, it must be included in kernel and not as a + module. + +config SERIAL_MPC52xx_CONSOLE + bool "Console on a Freescale MPC52xx/MPC512x family PSC serial port" + depends on SERIAL_MPC52xx=y + select SERIAL_CORE_CONSOLE + help + Select this options if you'd like to use one of the PSC serial port + of the Freescale MPC52xx family as a console. + +config SERIAL_MPC52xx_CONSOLE_BAUD + int "Freescale MPC52xx/MPC512x family PSC serial port baud" + depends on SERIAL_MPC52xx_CONSOLE=y + default "9600" + help + Select the MPC52xx console baud rate. + This value is only used if the bootloader doesn't pass in the + console baudrate + +config SERIAL_ICOM + tristate "IBM Multiport Serial Adapter" + depends on PCI && (PPC_ISERIES || PPC_PSERIES) + select SERIAL_CORE + select FW_LOADER + help + This driver is for a family of multiport serial adapters + including 2 port RVX, 2 port internal modem, 4 port internal + modem and a split 1 port RVX and 1 port internal modem. + + This driver can also be built as a module. If so, the module + will be called icom. + +config SERIAL_M32R_SIO + bool "M32R SIO I/F" + depends on M32R + default y + select SERIAL_CORE + help + Say Y here if you want to use the M32R serial controller. + +config SERIAL_M32R_SIO_CONSOLE + bool "use SIO console" + depends on SERIAL_M32R_SIO=y + select SERIAL_CORE_CONSOLE + help + Say Y here if you want to support a serial console. + + If you use an M3T-M32700UT or an OPSPUT platform, + please say also y for SERIAL_M32R_PLDSIO. + +config SERIAL_M32R_PLDSIO + bool "M32R SIO I/F on a PLD" + depends on SERIAL_M32R_SIO=y && (PLAT_OPSPUT || PLAT_USRV || PLAT_M32700UT) + default n + help + Say Y here if you want to use the M32R serial controller + on a PLD (Programmable Logic Device). + + If you use an M3T-M32700UT or an OPSPUT platform, + please say Y. + +config SERIAL_TXX9 + bool "TMPTX39XX/49XX SIO support" + depends on HAS_TXX9_SERIAL + select SERIAL_CORE + default y + +config HAS_TXX9_SERIAL + bool + +config SERIAL_TXX9_NR_UARTS + int "Maximum number of TMPTX39XX/49XX SIO ports" + depends on SERIAL_TXX9 + default "6" + +config SERIAL_TXX9_CONSOLE + bool "TMPTX39XX/49XX SIO Console support" + depends on SERIAL_TXX9=y + select SERIAL_CORE_CONSOLE + +config SERIAL_TXX9_STDSERIAL + bool "TX39XX/49XX SIO act as standard serial" + depends on !SERIAL_8250 && SERIAL_TXX9 + +config SERIAL_VR41XX + tristate "NEC VR4100 series Serial Interface Unit support" + depends on CPU_VR41XX + select SERIAL_CORE + help + If you have a NEC VR4100 series processor and you want to use + Serial Interface Unit(SIU) or Debug Serial Interface Unit(DSIU) + (not include VR4111/VR4121 DSIU), say Y. Otherwise, say N. + +config SERIAL_VR41XX_CONSOLE + bool "Enable NEC VR4100 series Serial Interface Unit console" + depends on SERIAL_VR41XX=y + select SERIAL_CORE_CONSOLE + help + If you have a NEC VR4100 series processor and you want to use + a console on a serial port, say Y. Otherwise, say N. + +config SERIAL_JSM + tristate "Digi International NEO PCI Support" + depends on PCI + select SERIAL_CORE + help + This is a driver for Digi International's Neo series + of cards which provide multiple serial ports. You would need + something like this to connect more than two modems to your Linux + box, for instance in order to become a dial-in server. This driver + supports PCI boards only. + + If you have a card like this, say Y here, otherwise say N. + + To compile this driver as a module, choose M here: the + module will be called jsm. + +config SERIAL_SGI_IOC4 + tristate "SGI IOC4 controller serial support" + depends on (IA64_GENERIC || IA64_SGI_SN2) && SGI_IOC4 + select SERIAL_CORE + help + If you have an SGI Altix with an IOC4 based Base IO card + and wish to use the serial ports on this card, say Y. + Otherwise, say N. + +config SERIAL_SGI_IOC3 + tristate "SGI Altix IOC3 serial support" + depends on (IA64_GENERIC || IA64_SGI_SN2) && SGI_IOC3 + select SERIAL_CORE + help + If you have an SGI Altix with an IOC3 serial card, + say Y or M. Otherwise, say N. + +config SERIAL_MSM + bool "MSM on-chip serial port support" + depends on ARM && ARCH_MSM + select SERIAL_CORE + +config SERIAL_MSM_CONSOLE + bool "MSM serial console support" + depends on SERIAL_MSM=y + select SERIAL_CORE_CONSOLE + +config SERIAL_NETX + tristate "NetX serial port support" + depends on ARM && ARCH_NETX + select SERIAL_CORE + help + If you have a machine based on a Hilscher NetX SoC you + can enable its onboard serial port by enabling this option. + + To compile this driver as a module, choose M here: the + module will be called netx-serial. + +config SERIAL_NETX_CONSOLE + bool "Console on NetX serial port" + depends on SERIAL_NETX=y + select SERIAL_CORE_CONSOLE + help + If you have enabled the serial port on the Hilscher NetX SoC + you can make it the console by answering Y to this option. + +config SERIAL_OF_PLATFORM + tristate "Serial port on Open Firmware platform bus" + depends on PPC_OF || MICROBLAZE + depends on SERIAL_8250 || SERIAL_OF_PLATFORM_NWPSERIAL + help + If you have a PowerPC based system that has serial ports + on a platform specific bus, you should enable this option. + Currently, only 8250 compatible ports are supported, but + others can easily be added. + +config SERIAL_OF_PLATFORM_NWPSERIAL + tristate "NWP serial port driver" + depends on PPC_OF && PPC_DCR + select SERIAL_OF_PLATFORM + select SERIAL_CORE_CONSOLE + select SERIAL_CORE + help + This driver supports the cell network processor nwp serial + device. + +config SERIAL_OF_PLATFORM_NWPSERIAL_CONSOLE + bool "Console on NWP serial port" + depends on SERIAL_OF_PLATFORM_NWPSERIAL=y + select SERIAL_CORE_CONSOLE + help + Support for Console on the NWP serial ports. + +config SERIAL_QE + tristate "Freescale QUICC Engine serial port support" + depends on QUICC_ENGINE + select SERIAL_CORE + select FW_LOADER + default n + help + This driver supports the QE serial ports on Freescale embedded + PowerPC that contain a QUICC Engine. + +config SERIAL_SC26XX + tristate "SC2681/SC2692 serial port support" + depends on SNI_RM + select SERIAL_CORE + help + This is a driver for the onboard serial ports of + older RM400 machines. + +config SERIAL_SC26XX_CONSOLE + bool "Console on SC2681/SC2692 serial port" + depends on SERIAL_SC26XX + select SERIAL_CORE_CONSOLE + help + Support for Console on SC2681/SC2692 serial ports. + +config SERIAL_BFIN_SPORT + tristate "Blackfin SPORT emulate UART (EXPERIMENTAL)" + depends on BLACKFIN && EXPERIMENTAL + select SERIAL_CORE + help + Enable SPORT emulate UART on Blackfin series. + + To compile this driver as a module, choose M here: the + module will be called bfin_sport_uart. + +choice + prompt "Baud rate for Blackfin SPORT UART" + depends on SERIAL_BFIN_SPORT + default SERIAL_SPORT_BAUD_RATE_57600 + help + Choose a baud rate for the SPORT UART, other uart settings are + 8 bit, 1 stop bit, no parity, no flow control. + +config SERIAL_SPORT_BAUD_RATE_115200 + bool "115200" + +config SERIAL_SPORT_BAUD_RATE_57600 + bool "57600" + +config SERIAL_SPORT_BAUD_RATE_38400 + bool "38400" + +config SERIAL_SPORT_BAUD_RATE_19200 + bool "19200" + +config SERIAL_SPORT_BAUD_RATE_9600 + bool "9600" +endchoice + +config SPORT_BAUD_RATE + int + depends on SERIAL_BFIN_SPORT + default 115200 if (SERIAL_SPORT_BAUD_RATE_115200) + default 57600 if (SERIAL_SPORT_BAUD_RATE_57600) + default 38400 if (SERIAL_SPORT_BAUD_RATE_38400) + default 19200 if (SERIAL_SPORT_BAUD_RATE_19200) + default 9600 if (SERIAL_SPORT_BAUD_RATE_9600) + +config SERIAL_TIMBERDALE + tristate "Support for timberdale UART" + depends on MFD_TIMBERDALE + select SERIAL_CORE + ---help--- + Add support for UART controller on timberdale. + +config SERIAL_BCM63XX + tristate "bcm63xx serial port support" + select SERIAL_CORE + depends on BCM63XX + help + If you have a bcm63xx CPU, you can enable its onboard + serial port by enabling this options. + + To compile this driver as a module, choose M here: the + module will be called bcm963xx_uart. + +config SERIAL_BCM63XX_CONSOLE + bool "Console on bcm63xx serial port" + depends on SERIAL_BCM63XX=y + select SERIAL_CORE_CONSOLE + help + If you have enabled the serial port on the bcm63xx CPU + you can make it the console by answering Y to this option. + +config SERIAL_GRLIB_GAISLER_APBUART + tristate "GRLIB APBUART serial support" + depends on OF + ---help--- + Add support for the GRLIB APBUART serial port. + +config SERIAL_GRLIB_GAISLER_APBUART_CONSOLE + bool "Console on GRLIB APBUART serial port" + depends on SERIAL_GRLIB_GAISLER_APBUART=y + select SERIAL_CORE_CONSOLE + help + Support for running a console on the GRLIB APBUART + +endmenu Index: trunk/sw/linux/linux-2.6.33.1-ao68000/drivers/serial/de2_70_console.c =================================================================== --- trunk/sw/linux/linux-2.6.33.1-ao68000/drivers/serial/de2_70_console.c (nonexistent) +++ trunk/sw/linux/linux-2.6.33.1-ao68000/drivers/serial/de2_70_console.c (revision 2) @@ -0,0 +1,79 @@ +/* + * de2_70_console: simple console driver for Terasic DE2-70 board. Based on uartlite.c + * + * Copyright (C) 2010 Aleksander Osman + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +#define DE2_70_NAME "ttyDE2" + +/* --------------------------------------------------------------------- + * Console driver operations + */ + +static void de2_70_console_write(struct console *co, const char *s, + unsigned int count) +{ + volatile char *tst = (char *)0xE0000000; + + while(count-- > 0) { + tst[0] = s[0]; + s++; + } +} + +static int __devinit de2_70_console_setup(struct console *co, char *options) +{ + return 0; +} + +static struct console de2_70_console = { + .name = DE2_70_NAME, + .write = de2_70_console_write, + .setup = de2_70_console_setup, + .flags = CON_PRINTBUFFER, + .index = -1, /* Specified on the cmdline (e.g. console=ttyUL0 ) */ +}; + +static int __init de2_70_console_init(void) +{ + register_console(&de2_70_console); + return 0; +} + +console_initcall(de2_70_console_init); + +/* --------------------------------------------------------------------- + * Module setup/teardown + */ + +int __init de2_70_init(void) +{ + return 0; +} + +void __exit de2_70_exit(void) +{ +} + +module_init(de2_70_init); +module_exit(de2_70_exit); + +MODULE_AUTHOR("Aleksander Osman <>"); +MODULE_DESCRIPTION("DE2-70 console"); +MODULE_LICENSE("GPL"); Index: trunk/sw/linux/linux-2.6.33.1-ao68000/drivers/serial/Makefile =================================================================== --- trunk/sw/linux/linux-2.6.33.1-ao68000/drivers/serial/Makefile (nonexistent) +++ trunk/sw/linux/linux-2.6.33.1-ao68000/drivers/serial/Makefile (revision 2) @@ -0,0 +1,85 @@ +# +# Makefile for the kernel serial device drivers. +# + +obj-$(CONFIG_SERIAL_CORE) += serial_core.o +obj-$(CONFIG_SERIAL_21285) += 21285.o +obj-$(CONFIG_DE2_70_CONSOLE) += de2_70_console.o + +# These Sparc drivers have to appear before others such as 8250 +# which share ttySx minor node space. Otherwise console device +# names change and other unplesantries. +obj-$(CONFIG_SERIAL_SUNCORE) += suncore.o +obj-$(CONFIG_SERIAL_SUNHV) += sunhv.o +obj-$(CONFIG_SERIAL_SUNZILOG) += sunzilog.o +obj-$(CONFIG_SERIAL_SUNSU) += sunsu.o +obj-$(CONFIG_SERIAL_SUNSAB) += sunsab.o + +obj-$(CONFIG_SERIAL_8250) += 8250.o +obj-$(CONFIG_SERIAL_8250_PNP) += 8250_pnp.o +obj-$(CONFIG_SERIAL_8250_GSC) += 8250_gsc.o +obj-$(CONFIG_SERIAL_8250_PCI) += 8250_pci.o +obj-$(CONFIG_SERIAL_8250_HP300) += 8250_hp300.o +obj-$(CONFIG_SERIAL_8250_CS) += serial_cs.o +obj-$(CONFIG_SERIAL_8250_ACORN) += 8250_acorn.o +obj-$(CONFIG_SERIAL_8250_CONSOLE) += 8250_early.o +obj-$(CONFIG_SERIAL_8250_FOURPORT) += 8250_fourport.o +obj-$(CONFIG_SERIAL_8250_ACCENT) += 8250_accent.o +obj-$(CONFIG_SERIAL_8250_BOCA) += 8250_boca.o +obj-$(CONFIG_SERIAL_8250_EXAR_ST16C554) += 8250_exar_st16c554.o +obj-$(CONFIG_SERIAL_8250_HUB6) += 8250_hub6.o +obj-$(CONFIG_SERIAL_8250_MCA) += 8250_mca.o +obj-$(CONFIG_SERIAL_AMBA_PL010) += amba-pl010.o +obj-$(CONFIG_SERIAL_AMBA_PL011) += amba-pl011.o +obj-$(CONFIG_SERIAL_CLPS711X) += clps711x.o +obj-$(CONFIG_SERIAL_PXA) += pxa.o +obj-$(CONFIG_SERIAL_PNX8XXX) += pnx8xxx_uart.o +obj-$(CONFIG_SERIAL_SA1100) += sa1100.o +obj-$(CONFIG_SERIAL_BCM63XX) += bcm63xx_uart.o +obj-$(CONFIG_SERIAL_BFIN) += bfin_5xx.o +obj-$(CONFIG_SERIAL_BFIN_SPORT) += bfin_sport_uart.o +obj-$(CONFIG_SERIAL_SAMSUNG) += samsung.o +obj-$(CONFIG_SERIAL_S3C2400) += s3c2400.o +obj-$(CONFIG_SERIAL_S3C2410) += s3c2410.o +obj-$(CONFIG_SERIAL_S3C2412) += s3c2412.o +obj-$(CONFIG_SERIAL_S3C2440) += s3c2440.o +obj-$(CONFIG_SERIAL_S3C24A0) += s3c24a0.o +obj-$(CONFIG_SERIAL_S3C6400) += s3c6400.o +obj-$(CONFIG_SERIAL_S5PC100) += s3c6400.o +obj-$(CONFIG_SERIAL_MAX3100) += max3100.o +obj-$(CONFIG_SERIAL_IP22_ZILOG) += ip22zilog.o +obj-$(CONFIG_SERIAL_MUX) += mux.o +obj-$(CONFIG_SERIAL_68328) += 68328serial.o +obj-$(CONFIG_SERIAL_68360) += 68360serial.o +obj-$(CONFIG_SERIAL_MCF) += mcf.o +obj-$(CONFIG_SERIAL_PMACZILOG) += pmac_zilog.o +obj-$(CONFIG_SERIAL_LH7A40X) += serial_lh7a40x.o +obj-$(CONFIG_SERIAL_DZ) += dz.o +obj-$(CONFIG_SERIAL_ZS) += zs.o +obj-$(CONFIG_SERIAL_SH_SCI) += sh-sci.o +obj-$(CONFIG_SERIAL_SGI_L1_CONSOLE) += sn_console.o +obj-$(CONFIG_SERIAL_CPM) += cpm_uart/ +obj-$(CONFIG_SERIAL_IMX) += imx.o +obj-$(CONFIG_SERIAL_MPC52xx) += mpc52xx_uart.o +obj-$(CONFIG_SERIAL_ICOM) += icom.o +obj-$(CONFIG_SERIAL_M32R_SIO) += m32r_sio.o +obj-$(CONFIG_SERIAL_MPSC) += mpsc.o +obj-$(CONFIG_SERIAL_SB1250_DUART) += sb1250-duart.o +obj-$(CONFIG_ETRAX_SERIAL) += crisv10.o +obj-$(CONFIG_SERIAL_SC26XX) += sc26xx.o +obj-$(CONFIG_SERIAL_JSM) += jsm/ +obj-$(CONFIG_SERIAL_TXX9) += serial_txx9.o +obj-$(CONFIG_SERIAL_VR41XX) += vr41xx_siu.o +obj-$(CONFIG_SERIAL_SGI_IOC4) += ioc4_serial.o +obj-$(CONFIG_SERIAL_SGI_IOC3) += ioc3_serial.o +obj-$(CONFIG_SERIAL_ATMEL) += atmel_serial.o +obj-$(CONFIG_SERIAL_UARTLITE) += uartlite.o +obj-$(CONFIG_SERIAL_MSM) += msm_serial.o +obj-$(CONFIG_SERIAL_NETX) += netx-serial.o +obj-$(CONFIG_SERIAL_OF_PLATFORM) += of_serial.o +obj-$(CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL) += nwpserial.o +obj-$(CONFIG_SERIAL_KS8695) += serial_ks8695.o +obj-$(CONFIG_KGDB_SERIAL_CONSOLE) += kgdboc.o +obj-$(CONFIG_SERIAL_QE) += ucc_uart.o +obj-$(CONFIG_SERIAL_TIMBERDALE) += timbuart.o +obj-$(CONFIG_SERIAL_GRLIB_GAISLER_APBUART) += apbuart.o Index: trunk/sw/linux/sector0.dat =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/sw/linux/sector0.dat =================================================================== --- trunk/sw/linux/sector0.dat (nonexistent) +++ trunk/sw/linux/sector0.dat (revision 2)

trunk/sw/linux/sector0.dat Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/sw/ao68000_tool/build/built-jar.properties =================================================================== --- trunk/sw/ao68000_tool/build/built-jar.properties (nonexistent) +++ trunk/sw/ao68000_tool/build/built-jar.properties (revision 2) @@ -0,0 +1,2 @@ +#Sun Mar 28 03:18:46 CEST 2010 +/home/alek/aktualne/ao68000/sw/ao68000_tool= Index: trunk/sw/ao68000_tool/build/classes/ao68000_tool/Parser.class =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/sw/ao68000_tool/build/classes/ao68000_tool/Parser.class =================================================================== --- trunk/sw/ao68000_tool/build/classes/ao68000_tool/Parser.class (nonexistent) +++ trunk/sw/ao68000_tool/build/classes/ao68000_tool/Parser.class (revision 2)

trunk/sw/ao68000_tool/build/classes/ao68000_tool/Parser.class Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/sw/ao68000_tool/build/classes/ao68000_tool/ParseParams.class =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/sw/ao68000_tool/build/classes/ao68000_tool/ParseParams.class =================================================================== --- trunk/sw/ao68000_tool/build/classes/ao68000_tool/ParseParams.class (nonexistent) +++ trunk/sw/ao68000_tool/build/classes/ao68000_tool/ParseParams.class (revision 2)

trunk/sw/ao68000_tool/build/classes/ao68000_tool/ParseParams.class Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/sw/ao68000_tool/build/classes/ao68000_tool/GenerateMicrocode.class =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/sw/ao68000_tool/build/classes/ao68000_tool/GenerateMicrocode.class =================================================================== --- trunk/sw/ao68000_tool/build/classes/ao68000_tool/GenerateMicrocode.class (nonexistent) +++ trunk/sw/ao68000_tool/build/classes/ao68000_tool/GenerateMicrocode.class (revision 2)

trunk/sw/ao68000_tool/build/classes/ao68000_tool/GenerateMicrocode.class Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/sw/ao68000_tool/build/classes/ao68000_tool/Microcode.class =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/sw/ao68000_tool/build/classes/ao68000_tool/Microcode.class =================================================================== --- trunk/sw/ao68000_tool/build/classes/ao68000_tool/Microcode.class (nonexistent) +++ trunk/sw/ao68000_tool/build/classes/ao68000_tool/Microcode.class (revision 2)

trunk/sw/ao68000_tool/build/classes/ao68000_tool/Microcode.class Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/sw/ao68000_tool/build/classes/ao68000_tool/Main.class =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/sw/ao68000_tool/build/classes/ao68000_tool/Main.class =================================================================== --- trunk/sw/ao68000_tool/build/classes/ao68000_tool/Main.class (nonexistent) +++ trunk/sw/ao68000_tool/build/classes/ao68000_tool/Main.class (revision 2)

trunk/sw/ao68000_tool/build/classes/ao68000_tool/Main.class Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/sw/ao68000_tool/build/classes/ao68000_tool/Tester.class =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/sw/ao68000_tool/build/classes/ao68000_tool/Tester.class =================================================================== --- trunk/sw/ao68000_tool/build/classes/ao68000_tool/Tester.class (nonexistent) +++ trunk/sw/ao68000_tool/build/classes/ao68000_tool/Tester.class (revision 2)

trunk/sw/ao68000_tool/build/classes/ao68000_tool/Tester.class Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/sw/ao68000_tool/build/classes/ao68000_tool/DocumentationTool.class =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/sw/ao68000_tool/build/classes/ao68000_tool/DocumentationTool.class =================================================================== --- trunk/sw/ao68000_tool/build/classes/ao68000_tool/DocumentationTool.class (nonexistent) +++ trunk/sw/ao68000_tool/build/classes/ao68000_tool/DocumentationTool.class (revision 2)

trunk/sw/ao68000_tool/build/classes/ao68000_tool/DocumentationTool.class Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/sw/ao68000_tool/dist/ao68000_tool.jar =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/sw/ao68000_tool/dist/ao68000_tool.jar =================================================================== --- trunk/sw/ao68000_tool/dist/ao68000_tool.jar (nonexistent) +++ trunk/sw/ao68000_tool/dist/ao68000_tool.jar (revision 2)

trunk/sw/ao68000_tool/dist/ao68000_tool.jar Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/sw/ao68000_tool/dist/README.TXT =================================================================== --- trunk/sw/ao68000_tool/dist/README.TXT (nonexistent) +++ trunk/sw/ao68000_tool/dist/README.TXT (revision 2) @@ -0,0 +1,33 @@ +======================== +BUILD OUTPUT DESCRIPTION +======================== + +When you build an Java application project that has a main class, the IDE +automatically copies all of the JAR +files on the projects classpath to your projects dist/lib folder. The IDE +also adds each of the JAR files to the Class-Path element in the application +JAR files manifest file (MANIFEST.MF). + +To run the project from the command line, go to the dist folder and +type the following: + +java -jar "ao68000_tool.jar" + +To distribute this project, zip up the dist folder (including the lib folder) +and distribute the ZIP file. + +Notes: + +* If two JAR files on the project classpath have the same name, only the first +JAR file is copied to the lib folder. +* Only JAR files are copied to the lib folder. +If the classpath contains other types of files or folders, none of the +classpath elements are copied to the lib folder. In such a case, +you need to copy the classpath elements to the lib folder manually after the build. +* If a library on the projects classpath also has a Class-Path element +specified in the manifest,the content of the Class-Path element has to be on +the projects runtime path. +* To set a main class in a standard Java project, right-click the project node +in the Projects window and choose Properties. Then click Run and enter the +class name in the Main Class field. Alternatively, you can manually type the +class name in the manifest Main-Class element. Index: trunk/sw/ao68000_tool/nbproject/project.properties =================================================================== --- trunk/sw/ao68000_tool/nbproject/project.properties (nonexistent) +++ trunk/sw/ao68000_tool/nbproject/project.properties (revision 2) @@ -0,0 +1,63 @@ +build.classes.dir=${build.dir}/classes +build.classes.excludes=**/*.java,**/*.form +# This directory is removed when the project is cleaned: +build.dir=build +build.generated.dir=${build.dir}/generated +build.generated.sources.dir=${build.dir}/generated-sources +# Only compile against the classpath explicitly listed here: +build.sysclasspath=ignore +build.test.classes.dir=${build.dir}/test/classes +build.test.results.dir=${build.dir}/test/results +# Uncomment to specify the preferred debugger connection transport: +#debug.transport=dt_socket +debug.classpath=\ + ${run.classpath} +debug.test.classpath=\ + ${run.test.classpath} +# This directory is removed when the project is cleaned: +dist.dir=dist +dist.jar=${dist.dir}/ao68000_tool.jar +dist.javadoc.dir=${dist.dir}/javadoc +excludes= +includes=** +jar.compress=false +javac.classpath= +# Space-separated list of extra javac options +javac.compilerargs= +javac.deprecation=false +javac.source=1.5 +javac.target=1.5 +javac.test.classpath=\ + ${javac.classpath}:\ + ${build.classes.dir}:\ + ${libs.junit.classpath}:\ + ${libs.junit_4.classpath} +javadoc.additionalparam= +javadoc.author=false +javadoc.encoding=${source.encoding} +javadoc.noindex=false +javadoc.nonavbar=false +javadoc.notree=false +javadoc.private=false +javadoc.splitindex=true +javadoc.use=true +javadoc.version=false +javadoc.windowtitle= +jaxbwiz.endorsed.dirs="${netbeans.home}/../ide12/modules/ext/jaxb/api" +main.class=ao68000_tool.Main +manifest.file=manifest.mf +meta.inf.dir=${src.dir}/META-INF +platform.active=default_platform +run.classpath=\ + ${javac.classpath}:\ + ${build.classes.dir} +# Space-separated list of JVM arguments used when running the project +# (you may also define separate properties like run-sys-prop.name=value instead of -Dname=value +# or test-sys-prop.name=value to set system properties for unit tests): +run.jvmargs= +run.test.classpath=\ + ${javac.test.classpath}:\ + ${build.test.classes.dir} +source.encoding=UTF-8 +src.dir=src +test.src.dir=test Index: trunk/sw/ao68000_tool/nbproject/project.xml =================================================================== --- trunk/sw/ao68000_tool/nbproject/project.xml (nonexistent) +++ trunk/sw/ao68000_tool/nbproject/project.xml (revision 2) @@ -0,0 +1,15 @@ + + + org.netbeans.modules.java.j2seproject + + + ao68000_tool + + + + + + + + + Index: trunk/sw/ao68000_tool/nbproject/genfiles.properties =================================================================== --- trunk/sw/ao68000_tool/nbproject/genfiles.properties (nonexistent) +++ trunk/sw/ao68000_tool/nbproject/genfiles.properties (revision 2) @@ -0,0 +1,8 @@ +build.xml.data.CRC32=2c4f0216 +build.xml.script.CRC32=9d8ae462 +build.xml.stylesheet.CRC32=958a1d3e@1.32.1.45 +# This file is used by a NetBeans-based IDE to track changes in generated files such as build-impl.xml. +# Do not edit this file. You may delete it but then the IDE will never regenerate such files for you. +nbproject/build-impl.xml.data.CRC32=2c4f0216 +nbproject/build-impl.xml.script.CRC32=2127d4d7 +nbproject/build-impl.xml.stylesheet.CRC32=576378a2@1.32.1.45 Index: trunk/sw/ao68000_tool/nbproject/private/private.properties =================================================================== --- trunk/sw/ao68000_tool/nbproject/private/private.properties (nonexistent) +++ trunk/sw/ao68000_tool/nbproject/private/private.properties (revision 2) @@ -0,0 +1,3 @@ +compile.on.save=true +jaxbwiz.endorsed.dirs=/home/alek/programy/netbeans-6.8/ide12/modules/ext/jaxb/api +user.properties.file=/home/alek/.netbeans/6.8/build.properties Index: trunk/sw/ao68000_tool/nbproject/private/private.xml =================================================================== --- trunk/sw/ao68000_tool/nbproject/private/private.xml (nonexistent) +++ trunk/sw/ao68000_tool/nbproject/private/private.xml (revision 2) @@ -0,0 +1,4 @@ + + + + Index: trunk/sw/ao68000_tool/nbproject/build-impl.xml =================================================================== --- trunk/sw/ao68000_tool/nbproject/build-impl.xml (nonexistent) +++ trunk/sw/ao68000_tool/nbproject/build-impl.xml (revision 2) @@ -0,0 +1,805 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Must set src.dir + Must set test.src.dir + Must set build.dir + Must set dist.dir + Must set build.classes.dir + Must set dist.javadoc.dir + Must set build.test.classes.dir + Must set build.test.results.dir + Must set build.classes.excludes + Must set dist.jar + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Must set javac.includes + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Must select some files in the IDE or set javac.includes + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + To run this application from the command line without Ant, try: + + + + + + + java -cp "${run.classpath.with.dist.jar}" ${main.class} + + + + + + + + + + + + + + + + + + + + + + + To run this application from the command line without Ant, try: + + java -jar "${dist.jar.resolved}" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Must select one file in the IDE or set run.class + + + + Must select one file in the IDE or set run.class + + + + + + + + + + + + + + + + + + + + + + + Must select one file in the IDE or set debug.class + + + + + Must select one file in the IDE or set debug.class + + + + + Must set fix.includes + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Must select some files in the IDE or set javac.includes + + + + + + + + + + + + + + + + + + + + Some tests failed; see details above. + + + + + + + + + Must select some files in the IDE or set test.includes + + + + Some tests failed; see details above. + + + + + Must select one file in the IDE or set test.class + + + + + + + + + + + + + + + + + + + + + + + + + + + Must select one file in the IDE or set applet.url + + + + + + + + + Must select one file in the IDE or set applet.url + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: trunk/sw/ao68000_tool/src/ao68000_tool/GenerateMicrocode.java =================================================================== --- trunk/sw/ao68000_tool/src/ao68000_tool/GenerateMicrocode.java (nonexistent) +++ trunk/sw/ao68000_tool/src/ao68000_tool/GenerateMicrocode.java (revision 2) @@ -0,0 +1,255 @@ +/* + * Copyright 2010, Aleksander Osman, alfik@poczta.fm. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, are + * permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND + * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +package ao68000_tool; + +import java.io.OutputStream; +import java.util.Vector; +import java.util.HashMap; +import java.util.HashSet; + +class GenerateMicrocode { + static void entry(boolean newline, String name) throws Exception { + /* + * if newline is true: end of last line + * if name is "offset_" + label: branch label + * if name is "label_" + label: label declaration + */ + + if(ParseParams.prefixes == null || labels == null || lines == null) throw new Exception("Entry validator not initialized."); + + // save last line + if(newline == true && current_line != null && current_line.size() > 0) lines.add(current_line); + // prepare a new line + if(newline == true) current_line = new HashMap(); + + // save label location + if(name.startsWith("label_")) { + String label = name.substring(6); + if(labels.containsKey(label)) throw new Exception("Double label declaration: " + label); + labels.put(label, lines.size()); + return; + } + + // get prefix + String prefix = "PROCEDURE_"; + if(name.startsWith("offset_")) { + String label = name.substring(7); + name = "label_" + label; + } + else { + prefix = null; + for(String p : ParseParams.prefixes) { + if(name.startsWith(p)) { + prefix = p; + break; + } + } + } + + if(prefix == null) throw new Exception("Unknown prefix for name: " + name); + + // check for double prefix + if(current_line.containsKey(prefix)) throw new Exception("Double prefix call: " + prefix); + + // extend current line + current_line.put(prefix, name); + } + + static void fill_bit_part(int array[], int start, int end, int value) throws Exception { + while(start <= end) { + int bit = value & 0x1; + + array[start] = bit; + + value >>= 1; + start++; + } + } + static void final_process(OutputStream out) throws Exception { + if(ParseParams.prefixes == null || labels == null || lines == null) throw new Exception("Final validator not initialized."); + // add last line + if(current_line != null && current_line.size() > 0) lines.add(current_line); + + + int i=0; + // resolve labels + for(HashMap line : lines) { + if(line.containsKey("PROCEDURE_")) { + String value = line.get("PROCEDURE_"); + + if(value.startsWith("label_")) { + String label = value.substring(6); + + if(labels.containsKey(label) == false) throw new Exception("Unresolved label: " + label); + int label_value = labels.get(label); + + int delta = label_value - i; + + if(delta < 0 || delta > 15) throw new Exception("Label: " + label + " out of bounds: " + delta); + line.put("PROCEDURE_", "value_" + delta); + } + } + i++; + } + + // prepare output header + int depth = 1; + while(depth < lines.size()) depth *= 2; + + out.write(new String("DEPTH = " + depth + ";\n").getBytes()); + out.write(new String("WIDTH = " + bit_line.length + ";\n").getBytes()); + out.write(new String("ADDRESS_RADIX = DEC;\n").getBytes()); + out.write(new String("DATA_RADIX = BIN;\n").getBytes()); + out.write(new String("CONTENT\n").getBytes()); + out.write(new String("BEGIN\n").getBytes()); + + i=0; + HashSet set = new HashSet(); + Vector bit_lines = new Vector(); + // prepare final bit array + for(HashMap line : lines) { + for(int j=0; j=0; j--) { + bits += bit_line[j]; + } + set.add(bits); + bit_lines.add(bits); + out.write(new String(bits + ";\n").getBytes()); + + i++; + } + out.write(new String("END;\n").getBytes()); + + + // prepare a compact microcode with a microcode decoder + // microcode reduced to 500x8 bits = 4000 bits, but microcode decoder takes about 1000 LE + // so currently unused +/* + i = set.size(); + int bit_size = 0; + while(i > 0) { + bit_size++; + i /= 2; + } + System.out.println("Set size: " + set.size() + ", bit size: " + bit_size + ", bit_line.length: " + bit_line.length); + + String empty_line = ""; + i = 0; + while(i < bit_line.length) { + empty_line += "0"; + i++; + } + + + String verilog = "assign micro_data =" + "\n"; + + verilog += "(encoded == " + bit_size + "'d" + 0 + ") ? " + bit_line.length + "'b" + empty_line + " :" + "\n"; + HashMap bit_line_numbers = new HashMap(); + i = 1; + for(String line : set) { + verilog += "(encoded == " + bit_size + "'d" + i + ") ? " + bit_line.length + "'b" + line + " :" + "\n"; + + bit_line_numbers.put(line, i); + i++; + } + verilog += bit_line.length + "'b" + empty_line + ";" + "\n"; + + i=0; + for(String line : bit_lines) { + String addr = "" + i + ": "; + while(addr.length() < 8) addr = " " + addr; + System.out.print(addr); + + String content = "" + bit_line_numbers.get(line) + ";"; + System.out.println(content); + + i++; + } + System.out.println("Verilog:\n" + verilog); +*/ + } + static void print_microcode_defines(OutputStream out) throws Exception { + if(ParseParams.prefix_locations == null || ParseParams.prefixes == null) throw new Exception("No prefix_locations or prefixes set."); + + out.write(new String("/*! \\file microcode_locations.v\n * \\brief Definitions of microcode locations.\n */\n").getBytes()); + + for(String s : ParseParams.prefixes) { + int start = ParseParams.prefix_locations.get(s + "start"); + int end = ParseParams.prefix_locations.get(s + "end"); + + String short_name = s.substring(0, s.length()-1); + short_name = short_name.toLowerCase(); + + out.write(new String("`define MICRO_DATA_" + short_name + " " + "micro_data[" + end + ":" + start + "]\n").getBytes()); + } + out.write(new String("\n").getBytes()); + + for(String label : labels.keySet()) { + if(label.startsWith("MICROPC_")) { + out.write(new String("`define " + label + " 9'd" + labels.get(label) + "\n").getBytes()); + } + } + } + static void generate(OutputStream microcode_os, OutputStream locations_os) throws Exception { + bit_line = new int[ParseParams.control_bit_offset]; + lines = new Vector>(); + labels = new HashMap(); + + Microcode.microcode(new Parser()); + + final_process(microcode_os); + print_microcode_defines(locations_os); + } + static HashMap current_line; + static Vector> lines; + static HashMap labels; + static int bit_line[]; +} Index: trunk/sw/ao68000_tool/src/ao68000_tool/Microcode.java =================================================================== --- trunk/sw/ao68000_tool/src/ao68000_tool/Microcode.java (nonexistent) +++ trunk/sw/ao68000_tool/src/ao68000_tool/Microcode.java (revision 2) @@ -0,0 +1,1537 @@ +/* + * Copyright 2010, Aleksander Osman, alfik@poczta.fm. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, are + * permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND + * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +package ao68000_tool; + +public class Microcode { + static void microcode(Parser p) throws Exception { + + p.label("reset"); + + p .GROUP_0_FLAG_SET(); + + // wait for instruction prefetch + p .BRANCH_procedure().PROCEDURE_wait_prefetch_valid(); + + // move SSP and PC from prefetch + p .AN_INPUT_FROM_PREFETCH_IR().AN_ADDRESS_SSP().AN_WRITE_ENABLE_SET() + .PC_FROM_PREFETCH_IR() + // jump to main loop + .BRANCH_procedure().PROCEDURE_jump_to_main_loop(); + + + p.label("MICROPC_ADDRESS_BUS_TRAP"); + + // save trap number and bus cycle extended information + p .TRAP_FROM_INTERRUPT() + .OP2_MOVE_ADDRESS_BUS_INFO() + // clear internal flags + .READ_MODIFY_WRITE_FLAG_CLEAR() + .INSTRUCTION_FLAG_SET() + .DO_READ_FLAG_CLEAR() + .DO_WRITE_FLAG_CLEAR() + .DO_INTERRUPT_FLAG_CLEAR() + + // check if group_0_flag already active + .BRANCH_group_0_flag().offset("address_bus_trap_group_0_flag_cleared"); + + // if group_0_flag active: block processor + p .DO_BLOCKED_FLAG_SET() + .BRANCH_procedure() + .PROCEDURE_wait_finished(); + + // continue processing trap + p .label("address_bus_trap_group_0_flag_cleared"); + p .GROUP_0_FLAG_SET(); + + //-- + // move PC to OP1 + p .OP1_FROM_PC(); + // move OP1 to result + p .ALU_SIMPLE_MOVE() + // move SR to OP1 + .OP1_FROM_SR(); + + // set supervisor, clear trace + p .ALU_SR_SET_TRAP(); + + //-- + // stack PC + p .SIZE_LONG().EA_REG_3b111().EA_MOD_PREDEC().EA_TYPE_ALL(); + p .BRANCH_procedure().PROCEDURE_call_load_ea(); + p .BRANCH_procedure().PROCEDURE_call_perform_ea_write(); + p .BRANCH_procedure().PROCEDURE_call_save_ea() + // move SR to result + .ALU_SIMPLE_MOVE() + // move IR to OP1 + .OP1_FROM_IR(); + + // stack SR + p .SIZE_WORD().EA_REG_3b111().EA_MOD_PREDEC().EA_TYPE_ALL(); + p .BRANCH_procedure().PROCEDURE_call_load_ea(); + p .BRANCH_procedure().PROCEDURE_call_perform_ea_write(); + p .BRANCH_procedure().PROCEDURE_call_save_ea() + // move IR to result + .ALU_SIMPLE_MOVE() + // move fault address to OP1 + .OP1_FROM_FAULT_ADDRESS(); + + //-- + // stack IR + p .BRANCH_procedure().PROCEDURE_call_load_ea(); + p .BRANCH_procedure().PROCEDURE_call_perform_ea_write(); + p .BRANCH_procedure().PROCEDURE_call_save_ea() + // move fault address to result + .ALU_SIMPLE_MOVE() + // move bus cycle info stored in OP2 to OP1 + .OP1_FROM_OP2(); + + // stack fault address + p .SIZE_LONG().EA_REG_3b111().EA_MOD_PREDEC().EA_TYPE_ALL(); + p .BRANCH_procedure().PROCEDURE_call_load_ea(); + p .BRANCH_procedure().PROCEDURE_call_perform_ea_write(); + p .BRANCH_procedure().PROCEDURE_call_save_ea() + // move bus cycle info from OP1 to result + .ALU_SIMPLE_MOVE(); + + // stack bus cycle info + p .SIZE_WORD().EA_REG_3b111().EA_MOD_PREDEC().EA_TYPE_ALL(); + p .BRANCH_procedure().PROCEDURE_call_load_ea(); + p .BRANCH_procedure().PROCEDURE_call_perform_ea_write(); + p .BRANCH_procedure().PROCEDURE_call_save_ea(); + + //-- + // load PC from exception vector table + p .ADDRESS_FROM_TRAP() + .SIZE_LONG().EA_REG_3b111().EA_MOD_PREDEC().EA_TYPE_ALL(); + p .BRANCH_procedure().PROCEDURE_call_perform_ea_read(); + p .ALU_SIMPLE_MOVE(); + + // wait for instruction prefetch + p .BRANCH_procedure().PROCEDURE_wait_prefetch_valid(); + + p .PC_FROM_RESULT(); + + // wait one cycle to check loaded PC: is it even ? + p .OP1_FROM_OP2(); + //-- + // jump to main loop + p .BRANCH_procedure().PROCEDURE_jump_to_main_loop(); + + p.label("MICROPC_TRAP_ENTRY"); + + //-- + // move PC to OP1 + p .OP1_FROM_PC(); + // move OP1 to result + p .ALU_SIMPLE_MOVE() + // move SR to OP1 + .OP1_FROM_SR(); + + // set supervisor, clear trace + p .ALU_SR_SET_TRAP(); + + //-- + // stack PC + p .SIZE_LONG().EA_REG_3b111().EA_MOD_PREDEC().EA_TYPE_ALL(); + p .BRANCH_procedure().PROCEDURE_call_load_ea(); + p .BRANCH_procedure().PROCEDURE_call_perform_ea_write(); + p .BRANCH_procedure().PROCEDURE_call_save_ea() + // move SR to result + .ALU_SIMPLE_MOVE(); + + // stack SR + p .SIZE_WORD().EA_REG_3b111().EA_MOD_PREDEC().EA_TYPE_ALL(); + p .BRANCH_procedure().PROCEDURE_call_load_ea(); + p .BRANCH_procedure().PROCEDURE_call_perform_ea_write(); + p .BRANCH_procedure().PROCEDURE_call_save_ea(); + + //-- + // load PC from exception vector table + p .ADDRESS_FROM_TRAP() + .SIZE_LONG().EA_REG_3b111().EA_MOD_PREDEC().EA_TYPE_ALL(); + p .BRANCH_procedure().PROCEDURE_call_perform_ea_read(); + p .ALU_SIMPLE_MOVE(); + + // wait for instruction prefetch + p .BRANCH_procedure().PROCEDURE_wait_prefetch_valid(); + + p .PC_FROM_RESULT(); + + // wait one cycle to check loaded PC: is it even ? + p .OP1_FROM_OP2(); + + //-- + // return + p .BRANCH_procedure().PROCEDURE_return(); + + + p.label("MICROPC_MAIN_LOOP"); + + // check if stop flag set and wait for valid prefetch and decode instruction + // execute instruction, instruction generated trap possible + p .BRANCH_stop_flag_wait_ir_decode().offset("main_loop_after_execution") + // clear read-modify-write flag always + .READ_MODIFY_WRITE_FLAG_CLEAR() + + // save trace flag, only when valid prefetch and valid instruction and stop flag cleared + .TRACE_FLAG_COPY_WHEN_NO_STOP() + + // save first instruction word, only when prefetch valid and stop flag cleared + .IR_LOAD_WHEN_PREFETCH_VALID() + // clear group 0 flag, only when valid prefetch and stop flag cleared + .GROUP_0_FLAG_CLEAR_WHEN_VALID_PREFETCH() + + // increment PC by 2, only when valid prefetch and valid instruction and stop flag cleared + .PC_INCR_BY_2_IN_MAIN_LOOP() + // clear instruction flag, only when valid prefetch and valid instruction and stop flag cleared + .INSTRUCTION_FLAG_CLEAR_IN_MAIN_LOOP(); + + // call trap + p .TRAP_FROM_DECODER() + .INSTRUCTION_FLAG_SET() + .BRANCH_procedure().PROCEDURE_call_trap(); + // after trap jump to main loop + p .BRANCH_procedure().PROCEDURE_jump_to_main_loop(); + + // jump here after execution + p .label("main_loop_after_execution"); + + // check if trace flag set and check external interrupt + p .BRANCH_trace_flag_and_interrupt().offset("main_loop_interrupt") + // set instruction flag, always + .INSTRUCTION_FLAG_SET(); + + // call trap + p .TRAP_TRACE() + .STOP_FLAG_CLEAR() + .BRANCH_procedure().PROCEDURE_call_trap(); + // after trap continue + + // jump here if trace flag not set and interupt pending + p .label("main_loop_interrupt"); + + // check external interrupt + p .DO_INTERRUPT_FLAG_SET_IF_ACTIVE() + .BRANCH_procedure().PROCEDURE_interrupt_mask(); + + p .BRANCH_procedure().PROCEDURE_wait_finished() + .ALU_SR_SET_INTERRUPT(); + + p .DO_INTERRUPT_FLAG_CLEAR() + .TRAP_FROM_INTERRUPT() + .STOP_FLAG_CLEAR() + .BRANCH_procedure().PROCEDURE_call_trap(); + + // after trap jump to main loop + p .BRANCH_procedure().PROCEDURE_jump_to_main_loop(); + + // **************************************************************** EA + + // load ea: to address register + + // (An), (An)+: + p.label("MICROPC_LOAD_EA_An"); + p.label("MICROPC_LOAD_EA_An_plus"); + + p .ADDRESS_FROM_AN_OUTPUT() + .BRANCH_procedure().PROCEDURE_return(); + + // -(An): + p.label("MICROPC_LOAD_EA_minus_An"); + + p .ADDRESS_FROM_AN_OUTPUT(); + p .ADDRESS_DECR_BY_SIZE() + .BRANCH_procedure().PROCEDURE_return(); + + // (d16, An): + p.label("MICROPC_LOAD_EA_d16_An"); + + p .BRANCH_procedure().PROCEDURE_wait_prefetch_valid(); + + p .INDEX_0() + .OFFSET_IMM_16() + .PC_INCR_BY_2() + .ADDRESS_FROM_AN_OUTPUT(); + + p .ADDRESS_FROM_BASE_INDEX_OFFSET() + .BRANCH_procedure().PROCEDURE_return(); + + // (d8, An, Xn): + p.label("MICROPC_LOAD_EA_d8_An_Xn"); + + p .BRANCH_procedure().PROCEDURE_wait_prefetch_valid() + .ADDRESS_FROM_AN_OUTPUT(); + + p .AN_ADDRESS_FROM_EXTENDED() + .DN_ADDRESS_FROM_EXTENDED() + .OFFSET_IMM_8(); + + p .AN_ADDRESS_FROM_EXTENDED() + .INDEX_LOAD_EXTENDED() + .PC_INCR_BY_2(); + + p .ADDRESS_FROM_BASE_INDEX_OFFSET() + .BRANCH_procedure().PROCEDURE_return(); + + // (xxx).W: + p.label("MICROPC_LOAD_EA_xxx_W"); + + p .BRANCH_procedure().PROCEDURE_wait_prefetch_valid(); + + p .ADDRESS_FROM_IMM_16() + .PC_INCR_BY_2() + .BRANCH_procedure().PROCEDURE_return(); + + // (xxx).L: + p.label("MICROPC_LOAD_EA_xxx_L"); + + p .BRANCH_procedure().PROCEDURE_wait_prefetch_valid(); + + p .ADDRESS_FROM_IMM_32() + .PC_INCR_BY_4() + .BRANCH_procedure().PROCEDURE_return(); + + // (d16, PC): + p.label("MICROPC_LOAD_EA_d16_PC"); + + p .BRANCH_procedure().PROCEDURE_wait_prefetch_valid(); + + p .INDEX_0() + .OFFSET_IMM_16(); + + p .ADDRESS_FROM_PC_INDEX_OFFSET() + .PC_INCR_BY_2() + .BRANCH_procedure().PROCEDURE_return(); + + // (d8, PC, Xn): + p.label("MICROPC_LOAD_EA_d8_PC_Xn"); + + p .BRANCH_procedure().PROCEDURE_wait_prefetch_valid(); + + p .AN_ADDRESS_FROM_EXTENDED() + .DN_ADDRESS_FROM_EXTENDED() + .OFFSET_IMM_8(); + + p .AN_ADDRESS_FROM_EXTENDED() + .INDEX_LOAD_EXTENDED(); + + p .ADDRESS_FROM_PC_INDEX_OFFSET() + .PC_INCR_BY_2() + .BRANCH_procedure().PROCEDURE_return(); + + p.label("MICROPC_LOAD_EA_illegal_command"); + + // call trap + p .TRAP_ILLEGAL_INSTR() + .BRANCH_procedure().PROCEDURE_call_trap(); + // after trap jump to main loop + p .BRANCH_procedure().PROCEDURE_jump_to_main_loop(); + + + // perform_ea_read: memory, Dn,An,immediate + + // Dn: + p.label("MICROPC_PERFORM_EA_READ_Dn"); + + p .OP1_FROM_DN() + .BRANCH_procedure().PROCEDURE_return(); + + // An: + p.label("MICROPC_PERFORM_EA_READ_An"); + + p .OP1_FROM_AN() + .BRANCH_procedure().PROCEDURE_return(); + + // immediate + p.label("MICROPC_PERFORM_EA_READ_imm"); + + p .BRANCH_procedure().PROCEDURE_wait_prefetch_valid(); + + p .OP1_FROM_IMMEDIATE() + .PC_INCR_BY_SIZE() + .BRANCH_procedure().PROCEDURE_return(); + + // memory + p.label("MICROPC_PERFORM_EA_READ_memory"); + + p .DO_READ_FLAG_SET() + .BRANCH_procedure().PROCEDURE_wait_finished(); + + p .DO_READ_FLAG_CLEAR() + .OP1_FROM_DATA() + .BRANCH_procedure().PROCEDURE_return(); + + // perform ea write: memory, Dn,An + // size of operand matters: select in memory write + + // Dn: + p.label("MICROPC_PERFORM_EA_WRITE_Dn"); + + p .DN_WRITE_ENABLE_SET() + .BRANCH_procedure().PROCEDURE_return(); + + + // An: + p.label("MICROPC_PERFORM_EA_WRITE_An"); + + p .AN_WRITE_ENABLE_SET() + .BRANCH_procedure().PROCEDURE_return(); + + // memory: + p.label("MICROPC_PERFORM_EA_WRITE_memory"); + + p .DATA_WRITE_FROM_RESULT() + .DO_WRITE_FLAG_SET() + .BRANCH_procedure().PROCEDURE_wait_finished(); + + p .DO_WRITE_FLAG_CLEAR() + .BRANCH_procedure().PROCEDURE_return(); + + // save ea: (An)+,-(An) + + // (An)+: + p.label("MICROPC_SAVE_EA_An_plus"); + + p .ADDRESS_INCR_BY_SIZE(); + + p .AN_INPUT_FROM_ADDRESS() + .AN_WRITE_ENABLE_SET() + .BRANCH_procedure().PROCEDURE_return(); + + // -(An) + p.label("MICROPC_SAVE_EA_minus_An"); + + p .AN_INPUT_FROM_ADDRESS() + .AN_WRITE_ENABLE_SET() + .BRANCH_procedure().PROCEDURE_return(); + + // **************************************************************** Instructions + + p.label("MICROPC_MOVEP_memory_to_register"); + + p .SIZE_BYTE().EA_REG_IR_2_0().EA_MOD_INDIRECTOFFSET().EA_TYPE_ALL(); + p .BRANCH_procedure().PROCEDURE_call_read(); + + p .ALU_MOVEP_M2R_1() + .ADDRESS_INCR_BY_2() + .BRANCH_procedure().PROCEDURE_call_perform_ea_read(); + + p .ALU_MOVEP_M2R_2() + .ADDRESS_INCR_BY_2() + .BRANCH_procedure().PROCEDURE_call_perform_ea_read(); + + p .ALU_MOVEP_M2R_3() + .ADDRESS_INCR_BY_2() + .BRANCH_procedure().PROCEDURE_call_perform_ea_read(); + + p .ALU_MOVEP_M2R_4() + .SIZE_1().EA_REG_IR_11_9().EA_MOD_DN().EA_TYPE_ALL(); + p .BRANCH_procedure().PROCEDURE_call_perform_ea_write(); + + p .BRANCH_procedure().PROCEDURE_return(); + + p.label("MICROPC_MOVEP_register_to_memory"); + + p .SIZE_1_PLUS().EA_REG_IR_11_9().EA_MOD_DN().EA_TYPE_ALL(); + p .BRANCH_procedure().PROCEDURE_call_perform_ea_read(); + + p .SIZE_BYTE().EA_REG_IR_2_0().EA_MOD_INDIRECTOFFSET().EA_TYPE_ALL(); + p .BRANCH_procedure().PROCEDURE_call_load_ea(); + + p .ALU_MOVEP_R2M_1() + .BRANCH_procedure().PROCEDURE_call_perform_ea_write(); + + p .ADDRESS_INCR_BY_2() + .ALU_MOVEP_R2M_2() + .BRANCH_procedure().PROCEDURE_call_perform_ea_write(); + + p .BRANCH_movep_16().offset("movep_16"); + + p .ADDRESS_INCR_BY_2() + .ALU_MOVEP_R2M_3() + .BRANCH_procedure().PROCEDURE_call_perform_ea_write(); + + p .ADDRESS_INCR_BY_2() + .ALU_MOVEP_R2M_4() + .BRANCH_procedure().PROCEDURE_call_perform_ea_write(); + + // jump here if word operation + p .label("movep_16"); + + p .BRANCH_procedure().PROCEDURE_return(); + + p.label("MICROPC_MOVEM_memory_to_register"); + + p .SIZE_WORD().EA_REG_3b100().EA_MOD_3b111().EA_TYPE_ALL() + .BRANCH_procedure().PROCEDURE_wait_prefetch_valid_32(); + + p .OP1_FROM_IMMEDIATE() + .PC_INCR_BY_SIZE(); + + p .MOVEM_REG_FROM_OP1() + .MOVEM_MODREG_LOAD_0() + .MOVEM_LOOP_LOAD_0() + .SIZE_2().EA_REG_IR_2_0().EA_MOD_IR_5_3().EA_TYPE_CONTROL_POSTINC(); + + p .BRANCH_procedure().PROCEDURE_call_load_ea(); + + // push current micro pc on stack + p .BRANCH_procedure().PROCEDURE_push_micropc(); + + // check if loop finished + p .BRANCH_movem_loop().offset("movem_memory_to_register_loop"); + + // check if operation on register required + p .BRANCH_movem_reg().offset("movem_memory_to_register_reg"); + + p .SIZE_2().EA_REG_IR_2_0().EA_MOD_IR_5_3().EA_TYPE_CONTROL_POSTINC(); + p .BRANCH_procedure().PROCEDURE_call_perform_ea_read(); + + p .ALU_SIGN_EXTEND() + .ADDRESS_INCR_BY_SIZE() + .SIZE_LONG().EA_REG_MOVEM_REG_2_0().EA_MOD_MOVEM_MOD_5_3().EA_TYPE_DN_AN(); + p .BRANCH_procedure().PROCEDURE_call_perform_ea_write(); + + // jump here if operation on register not required + p .label("movem_memory_to_register_reg"); + + p .MOVEM_MODREG_INCR_BY_1() + .MOVEM_REG_SHIFT_RIGHT() + .MOVEM_LOOP_INCR_BY_1() + .BRANCH_procedure().PROCEDURE_return(); + + // jump here if loop finished + p .label("movem_memory_to_register_loop"); + + p .BRANCH_procedure().PROCEDURE_pop_micropc() + .SIZE_2().EA_REG_IR_2_0().EA_MOD_IR_5_3().EA_TYPE_CONTROL_POSTINC(); + + p .BRANCH_procedure().PROCEDURE_call_save_ea() + .ADDRESS_DECR_BY_SIZE(); + + p .BRANCH_procedure().PROCEDURE_return(); + + p.label("MICROPC_MOVEM_register_to_memory_predecrement"); + + p .SIZE_WORD().EA_REG_3b100().EA_MOD_3b111().EA_TYPE_ALL() + .BRANCH_procedure().PROCEDURE_wait_prefetch_valid_32(); + + p .OP1_FROM_IMMEDIATE() + .PC_INCR_BY_SIZE(); + + p .MOVEM_REG_FROM_OP1() + .MOVEM_MODREG_LOAD_6b001111() + .MOVEM_LOOP_LOAD_0() + .SIZE_2().EA_REG_IR_2_0().EA_MOD_IR_5_3().EA_TYPE_CONTROLALTER_PREDEC(); + + p .BRANCH_procedure().PROCEDURE_call_load_ea(); + + // push current micro pc on stack + p .BRANCH_procedure().PROCEDURE_push_micropc(); + + // check if loop finished + p .BRANCH_movem_loop().offset("movem_register_to_memory_predecrement_loop"); + + // check if operation on register required + p .BRANCH_movem_reg().offset("movem_register_to_memory_predecrement_reg"); + + p .SIZE_2().EA_REG_MOVEM_REG_2_0().EA_MOD_MOVEM_MOD_5_3().EA_TYPE_DN_AN(); + p .BRANCH_procedure().PROCEDURE_call_perform_ea_read(); + + p .ALU_SIGN_EXTEND() + .SIZE_2().EA_REG_IR_2_0().EA_MOD_IR_5_3().EA_TYPE_CONTROLALTER_PREDEC(); + p .BRANCH_procedure().PROCEDURE_call_perform_ea_write(); + + p .ADDRESS_DECR_BY_SIZE(); + + // jump here if operation on register not required + p .label("movem_register_to_memory_predecrement_reg"); + + p .MOVEM_MODREG_DECR_BY_1() + .MOVEM_REG_SHIFT_RIGHT() + .MOVEM_LOOP_INCR_BY_1() + .BRANCH_procedure().PROCEDURE_return(); + + // jump here if loop finished + p .label("movem_register_to_memory_predecrement_loop"); + + p .BRANCH_procedure().PROCEDURE_pop_micropc() + .ADDRESS_INCR_BY_SIZE(); + + p .BRANCH_procedure().PROCEDURE_call_save_ea(); + + p .BRANCH_procedure().PROCEDURE_return(); + + p.label("MICROPC_MOVEM_register_to_memory_control"); + + p .SIZE_WORD().EA_REG_3b100().EA_MOD_3b111().EA_TYPE_ALL() + .BRANCH_procedure().PROCEDURE_wait_prefetch_valid_32(); + + p .OP1_FROM_IMMEDIATE() + .PC_INCR_BY_SIZE(); + + p .MOVEM_REG_FROM_OP1() + .MOVEM_MODREG_LOAD_0() + .MOVEM_LOOP_LOAD_0() + .SIZE_2().EA_REG_IR_2_0().EA_MOD_IR_5_3().EA_TYPE_CONTROLALTER_PREDEC(); + + p .BRANCH_procedure().PROCEDURE_call_load_ea(); + + // push current micro pc on stack + p .BRANCH_procedure().PROCEDURE_push_micropc(); + + // check if loop finished + p .BRANCH_movem_loop().offset("movem_register_to_memory_control_loop"); + + // check if operation on register required + p .BRANCH_movem_reg().offset("movem_register_to_memory_control_reg"); + + p .SIZE_2().EA_REG_MOVEM_REG_2_0().EA_MOD_MOVEM_MOD_5_3().EA_TYPE_DN_AN(); + p .BRANCH_procedure().PROCEDURE_call_perform_ea_read(); + + p .ALU_SIGN_EXTEND() + .SIZE_2().EA_REG_IR_2_0().EA_MOD_IR_5_3().EA_TYPE_CONTROLALTER_PREDEC(); + p .BRANCH_procedure().PROCEDURE_call_perform_ea_write(); + + p .ADDRESS_INCR_BY_SIZE(); + + // jump here if operation on register not required + p .label("movem_register_to_memory_control_reg"); + + p .MOVEM_MODREG_INCR_BY_1() + .MOVEM_REG_SHIFT_RIGHT() + .MOVEM_LOOP_INCR_BY_1() + .BRANCH_procedure().PROCEDURE_return(); + + // jump here if loop finished + p .label("movem_register_to_memory_control_loop"); + + p .BRANCH_procedure().PROCEDURE_pop_micropc(); + + p .BRANCH_procedure().PROCEDURE_return(); + + p.label("MICROPC_LEA"); + + p .SIZE_LONG().EA_REG_IR_2_0().EA_MOD_IR_5_3().EA_TYPE_CONTROL(); + p .BRANCH_procedure().PROCEDURE_call_load_ea(); + + p .OP1_FROM_ADDRESS(); + + p .ALU_SIMPLE_MOVE() + .SIZE_LONG().EA_REG_IR_11_9().EA_MOD_AN().EA_TYPE_ALL(); + + p .BRANCH_procedure().PROCEDURE_call_perform_ea_write(); + + p .BRANCH_procedure().PROCEDURE_return(); + + p.label("MICROPC_PEA"); + + p .SIZE_LONG().EA_REG_IR_2_0().EA_MOD_IR_5_3().EA_TYPE_CONTROL(); + p .BRANCH_procedure().PROCEDURE_call_load_ea(); + + p .OP1_FROM_ADDRESS(); + + p .ALU_SIMPLE_MOVE() + .SIZE_LONG().EA_REG_3b111().EA_MOD_PREDEC().EA_TYPE_ALL(); + + p .BRANCH_procedure().PROCEDURE_call_load_ea(); + + p .BRANCH_procedure().PROCEDURE_call_write(); + + p.label("MICROPC_ANDI_EORI_ORI_ADDI_SUBI"); +//+++ + p .SIZE_3().EA_REG_3b100().EA_MOD_3b111().EA_TYPE_ALL() + .BRANCH_procedure().PROCEDURE_wait_prefetch_valid_32(); + + p .OP1_FROM_IMMEDIATE() + .PC_INCR_BY_SIZE() + + .SIZE_3().EA_REG_IR_2_0().EA_MOD_IR_5_3().EA_TYPE_DATAALTER(); + + p .OP2_FROM_OP1() + .BRANCH_procedure().PROCEDURE_call_read(); + + p .ALU_ARITHMETIC_LOGIC() + .BRANCH_procedure().PROCEDURE_call_write(); + + p.label("MICROPC_ORI_to_CCR_ORI_to_SR_ANDI_to_CCR_ANDI_to_SR_EORI_to_CCR_EORI_to_SR"); +//+ + p .SIZE_3().EA_REG_3b100().EA_MOD_3b111().EA_TYPE_ALL() + .BRANCH_procedure().PROCEDURE_wait_prefetch_valid_32(); + + p .OP1_FROM_IMMEDIATE() + .PC_INCR_BY_SIZE(); + + p .OP2_FROM_OP1() + .OP1_FROM_SR(); + + p .ALU_ARITHMETIC_LOGIC(); + + p .OP1_FROM_RESULT(); + + p .ALU_MOVE_TO_CCR_SR_RTE_RTR_STOP_LOGIC_TO_CCR_SR() + .BRANCH_procedure().PROCEDURE_return(); + + p.label("MICROPC_CMPI"); +//+ + p .SIZE_3().EA_REG_3b100().EA_MOD_3b111().EA_TYPE_ALL() + .BRANCH_procedure().PROCEDURE_wait_prefetch_valid_32(); + + p .OP1_FROM_IMMEDIATE() + .PC_INCR_BY_SIZE() + + .SIZE_3().EA_REG_IR_2_0().EA_MOD_IR_5_3().EA_TYPE_DATAALTER(); + + p .OP2_FROM_OP1() + .BRANCH_procedure().PROCEDURE_call_read(); + + p .ALU_ARITHMETIC_LOGIC() + .BRANCH_procedure().PROCEDURE_call_save_ea(); + + p .BRANCH_procedure().PROCEDURE_return(); + + p.label("MICROPC_ABCD_SBCD_ADDX_SUBX"); + + p .SIZE_3().EA_REG_IR_2_0().EA_MOD_DN_PREDEC().EA_TYPE_ALL(); + + p .BRANCH_procedure().PROCEDURE_call_load_ea(); + p .BRANCH_procedure().PROCEDURE_call_perform_ea_read(); + p .BRANCH_procedure().PROCEDURE_call_save_ea(); + + p .OP2_FROM_OP1() + .SIZE_3().EA_REG_IR_11_9().EA_MOD_DN_PREDEC().EA_TYPE_ALL(); + + p .BRANCH_procedure().PROCEDURE_call_load_ea(); + p .BRANCH_procedure().PROCEDURE_call_perform_ea_read(); + + p .ALU_ABCD_SBCD_ADDX_SUBX() + .BRANCH_procedure().PROCEDURE_call_write(); + + p.label("MICROPC_EXG"); + + p .SIZE_LONG().EA_REG_IR_2_0().EA_MOD_IR_5_3().EA_TYPE_DN_AN(); + p .BRANCH_procedure().PROCEDURE_call_perform_ea_read(); + + p .ALU_SIMPLE_MOVE() + .SIZE_LONG().EA_REG_IR_11_9().EA_MOD_DN_AN_EXG().EA_TYPE_ALL(); + + p .BRANCH_procedure().PROCEDURE_call_perform_ea_read(); + p .BRANCH_procedure().PROCEDURE_call_perform_ea_write(); + + p .ALU_SIMPLE_MOVE() + .SIZE_LONG().EA_REG_IR_2_0().EA_MOD_IR_5_3().EA_TYPE_DN_AN(); + + p .BRANCH_procedure().PROCEDURE_call_perform_ea_write(); + + p .BRANCH_procedure().PROCEDURE_return(); + + + p.label("MICROPC_CMPM"); + + p .SIZE_3().EA_REG_IR_2_0().EA_MOD_POSTINC().EA_TYPE_ALL(); + + p .BRANCH_procedure().PROCEDURE_call_read(); + p .BRANCH_procedure().PROCEDURE_call_save_ea(); + + p .OP2_FROM_OP1() + .SIZE_3().EA_REG_IR_11_9().EA_MOD_POSTINC().EA_TYPE_ALL(); + + p .BRANCH_procedure().PROCEDURE_call_read(); + + p .ALU_ARITHMETIC_LOGIC() + .BRANCH_procedure().PROCEDURE_call_save_ea(); + + p .BRANCH_procedure().PROCEDURE_return(); + + p.label("MICROPC_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR_all_immediate_register"); + + p .SIZE_3().EA_REG_IR_11_9().EA_MOD_DN().EA_TYPE_ALL(); + p .BRANCH_procedure().PROCEDURE_call_perform_ea_read(); + + p .OP2_FROM_OP1() + .SIZE_3().EA_REG_IR_2_0().EA_MOD_DN().EA_TYPE_ALL(); + p .BRANCH_procedure().PROCEDURE_call_perform_ea_read(); + + p .OP2_LOAD_COUNT(); + + p .ALU_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR_prepare(); + + p .BRANCH_procedure().PROCEDURE_push_micropc(); + + p .BRANCH_operand2().offset("shift_rotate_immediate_loop"); + + p .ALU_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR(); + p .OP1_FROM_RESULT() + .OP2_DECR_BY_1() + .BRANCH_procedure().PROCEDURE_return(); + + // jump here if loop finished + p .label("shift_rotate_immediate_loop"); + + p .BRANCH_procedure().PROCEDURE_pop_micropc(); + + p .BRANCH_procedure().PROCEDURE_call_perform_ea_write(); + + p .BRANCH_procedure().PROCEDURE_return(); + + p.label("MICROPC_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR_all_memory"); + + p .SIZE_WORD().EA_REG_IR_2_0().EA_MOD_IR_5_3().EA_TYPE_MEMORYALTER(); + + p .BRANCH_procedure().PROCEDURE_call_read(); + + p .OP2_LOAD_1(); + + p .ALU_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR_prepare(); + p .ALU_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR(); + + p .BRANCH_procedure().PROCEDURE_call_write(); + + p.label("MICROPC_MOVE"); + + p .SIZE_4().EA_REG_IR_2_0().EA_MOD_IR_5_3().EA_TYPE_ALL(); + + p .BRANCH_procedure().PROCEDURE_call_read(); + p .BRANCH_procedure().PROCEDURE_call_save_ea(); + + p .ALU_SIMPLE_MOVE() + .SIZE_4().EA_REG_IR_11_9().EA_MOD_IR_8_6().EA_TYPE_DATAALTER(); + + p .BRANCH_procedure().PROCEDURE_call_load_ea(); + p .BRANCH_procedure().PROCEDURE_call_perform_ea_write(); + p .BRANCH_procedure().PROCEDURE_call_save_ea(); + p .ALU_MOVE() + .BRANCH_procedure().PROCEDURE_return(); + + p.label("MICROPC_MOVEA"); + + p .SIZE_4().EA_REG_IR_2_0().EA_MOD_IR_5_3().EA_TYPE_ALL(); + + p .BRANCH_procedure().PROCEDURE_call_read(); + p .BRANCH_procedure().PROCEDURE_call_save_ea(); + + p .ALU_SIGN_EXTEND() + .SIZE_4().EA_REG_IR_11_9().EA_MOD_AN().EA_TYPE_ALL(); + + p .BRANCH_procedure().PROCEDURE_call_perform_ea_write(); + + p .BRANCH_procedure().PROCEDURE_return(); + + p.label("MICROPC_EOR"); + + p .SIZE_3().EA_REG_IR_11_9().EA_MOD_DN().EA_TYPE_ALL(); + + p .BRANCH_procedure().PROCEDURE_call_perform_ea_read(); + + p .OP2_FROM_OP1() + .SIZE_3().EA_REG_IR_2_0().EA_MOD_IR_5_3().EA_TYPE_DATAALTER(); + + p .BRANCH_procedure().PROCEDURE_call_read(); + + p .ALU_ARITHMETIC_LOGIC() + .BRANCH_procedure().PROCEDURE_call_write(); + + p.label("MICROPC_ADD_to_mem_SUB_to_mem_AND_to_mem_OR_to_mem"); + + p .SIZE_3().EA_REG_IR_11_9().EA_MOD_DN().EA_TYPE_ALL(); + + p .BRANCH_procedure().PROCEDURE_call_perform_ea_read(); + + p .OP2_FROM_OP1() + .SIZE_3().EA_REG_IR_2_0().EA_MOD_IR_5_3().EA_TYPE_MEMORYALTER(); + + p .BRANCH_procedure().PROCEDURE_call_read(); + + p .ALU_ARITHMETIC_LOGIC() + .BRANCH_procedure().PROCEDURE_call_write(); + + p.label("MICROPC_ADD_to_Dn_SUB_to_Dn_AND_to_Dn_OR_to_Dn"); + + p .SIZE_3().EA_REG_IR_2_0().EA_MOD_IR_5_3().EA_TYPE_ALL(); + + p .BRANCH_procedure().PROCEDURE_call_read(); + p .BRANCH_procedure().PROCEDURE_call_save_ea(); + + p .OP2_FROM_OP1() + .SIZE_3().EA_REG_IR_11_9().EA_MOD_DN().EA_TYPE_ALL(); + + p .BRANCH_procedure().PROCEDURE_call_perform_ea_read(); + + p .ALU_ARITHMETIC_LOGIC() + .BRANCH_procedure().PROCEDURE_call_perform_ea_write(); + + p .BRANCH_procedure().PROCEDURE_return(); + + p.label("MICROPC_CMP"); + + p .SIZE_3().EA_REG_IR_2_0().EA_MOD_IR_5_3().EA_TYPE_ALL(); + + p .BRANCH_procedure().PROCEDURE_call_read(); + p .BRANCH_procedure().PROCEDURE_call_save_ea(); + + p .OP2_FROM_OP1() + .SIZE_3().EA_REG_IR_11_9().EA_MOD_DN().EA_TYPE_ALL(); + + p .BRANCH_procedure().PROCEDURE_call_perform_ea_read(); + + p .ALU_ARITHMETIC_LOGIC() + .BRANCH_procedure().PROCEDURE_return(); + + p.label("MICROPC_ADDA_SUBA"); + + p .SIZE_5().EA_REG_IR_2_0().EA_MOD_IR_5_3().EA_TYPE_ALL(); + + p .BRANCH_procedure().PROCEDURE_call_read(); + p .BRANCH_procedure().PROCEDURE_call_save_ea(); + + p .OP2_FROM_OP1() + .SIZE_LONG().EA_REG_IR_11_9().EA_MOD_AN().EA_TYPE_ALL(); + + p .BRANCH_procedure().PROCEDURE_call_perform_ea_read(); + + p .ALU_ADDA_SUBA_CMPA_ADDQ_SUBQ() + .BRANCH_procedure().PROCEDURE_call_perform_ea_write(); + + p .BRANCH_procedure().PROCEDURE_return(); + + p.label("MICROPC_CMPA"); + + p .SIZE_5().EA_REG_IR_2_0().EA_MOD_IR_5_3().EA_TYPE_ALL(); + + p .BRANCH_procedure().PROCEDURE_call_read(); + p .BRANCH_procedure().PROCEDURE_call_save_ea(); + + p .OP2_FROM_OP1() + .SIZE_LONG().EA_REG_IR_11_9().EA_MOD_AN().EA_TYPE_ALL(); + + p .BRANCH_procedure().PROCEDURE_call_perform_ea_read(); + + p .ALU_ADDA_SUBA_CMPA_ADDQ_SUBQ() + .BRANCH_procedure().PROCEDURE_return(); + + p.label("MICROPC_CHK"); + + p .SIZE_WORD().EA_REG_IR_2_0().EA_MOD_IR_5_3().EA_TYPE_DATA(); + + p .BRANCH_procedure().PROCEDURE_call_read(); + p .BRANCH_procedure().PROCEDURE_call_save_ea(); + + p .OP2_FROM_OP1() + .SIZE_WORD().EA_REG_IR_11_9().EA_MOD_DN().EA_TYPE_ALL(); + + p .BRANCH_procedure().PROCEDURE_call_perform_ea_read(); + + p .ALU_CHK(); + + p .BRANCH_special_01().offset("chk_no_trap"); + p .TRAP_CHK() + .BRANCH_procedure().PROCEDURE_call_trap(); + // after return continue + + // jump here if no trap + p .label("chk_no_trap"); + + p .BRANCH_procedure().PROCEDURE_return(); + + p.label("MICROPC_MULS_MULU_DIVS_DIVU"); + + p .SIZE_WORD().EA_REG_IR_2_0().EA_MOD_IR_5_3().EA_TYPE_DATA(); + + p .BRANCH_procedure().PROCEDURE_call_read(); + p .BRANCH_procedure().PROCEDURE_call_save_ea(); + + p .OP2_FROM_OP1() + .SIZE_LONG().EA_REG_IR_11_9().EA_MOD_DN().EA_TYPE_ALL(); + + p .BRANCH_procedure().PROCEDURE_call_perform_ea_read(); + + p .ALU_MULS_MULU_DIVS_DIVU() + .MOVEM_LOOP_LOAD_0(); + + p .BRANCH_special_01().offset("div_no_div_by_zero_trap"); + p .TRAP_DIV_BY_ZERO() + .BRANCH_procedure().PROCEDURE_call_trap(); + // return after return + p .BRANCH_procedure().PROCEDURE_return(); + + // jump here if no trap + p .label("div_no_div_by_zero_trap"); + + // push current micro pc on stack + p .BRANCH_procedure().PROCEDURE_push_micropc(); + + // check if loop finished + p .BRANCH_movem_loop().offset("mult_div_loop_0"); + p .MOVEM_LOOP_INCR_BY_1() + .BRANCH_procedure().PROCEDURE_return(); + + // jump here after first loop finished + p .label("mult_div_loop_0"); + + p .BRANCH_procedure().PROCEDURE_pop_micropc() + .MOVEM_LOOP_LOAD_0(); + + // push current micro pc on stack + p .BRANCH_procedure().PROCEDURE_push_micropc(); + + // check if loop finished + p .BRANCH_movem_loop().offset("mult_div_loop_1"); + p .MOVEM_LOOP_INCR_BY_1() + .BRANCH_procedure().PROCEDURE_return(); + + // jump here after second loop finished + p .label("mult_div_loop_1"); + + p .ALU_MULS_MULU_DIVS_DIVU() + .BRANCH_procedure().PROCEDURE_pop_micropc(); + + p .BRANCH_special_10().offset("mult_div_overflow"); + p .BRANCH_procedure().PROCEDURE_call_perform_ea_write(); + + // jump here if overflow + p .label("mult_div_overflow"); + + p .BRANCH_procedure().PROCEDURE_return(); + + p.label("MICROPC_MOVEQ"); + + p .OP1_MOVEQ() + .SIZE_LONG().EA_REG_IR_11_9().EA_MOD_DN().EA_TYPE_ALL(); + + p .ALU_MOVE() + .BRANCH_procedure().PROCEDURE_call_perform_ea_write(); + + p .BRANCH_procedure().PROCEDURE_return(); + + p.label("MICROPC_BCHG_BCLR_BSET_immediate"); + + p .SIZE_BYTE().EA_REG_3b100().EA_MOD_3b111().EA_TYPE_ALL() + .BRANCH_procedure().PROCEDURE_wait_prefetch_valid_32(); + + p .OP1_FROM_IMMEDIATE() + .PC_INCR_BY_SIZE(); + + p .OP2_FROM_OP1() + .SIZE_6().EA_REG_IR_2_0().EA_MOD_IR_5_3().EA_TYPE_DATAALTER(); + + p .BRANCH_procedure().PROCEDURE_call_read(); + + p .ALU_BCHG_BCLR_BSET_BTST() + .BRANCH_procedure().PROCEDURE_call_write(); + + p.label("MICROPC_BTST_immediate"); + + p .SIZE_BYTE().EA_REG_3b100().EA_MOD_3b111().EA_TYPE_ALL() + .BRANCH_procedure().PROCEDURE_wait_prefetch_valid_32(); + + p .OP1_FROM_IMMEDIATE() + .PC_INCR_BY_SIZE(); + + p .OP2_FROM_OP1() + .SIZE_6().EA_REG_IR_2_0().EA_MOD_IR_5_3().EA_TYPE_DATA(); + + p .BRANCH_procedure().PROCEDURE_call_read(); + p .BRANCH_procedure().PROCEDURE_call_save_ea(); + + p .ALU_BCHG_BCLR_BSET_BTST() + .BRANCH_procedure().PROCEDURE_return(); + + p.label("MICROPC_BCHG_BCLR_BSET_register"); + + p .SIZE_6().EA_REG_IR_11_9().EA_MOD_DN().EA_TYPE_ALL(); + + p .BRANCH_procedure().PROCEDURE_call_perform_ea_read(); + + p .OP2_FROM_OP1() + .SIZE_6().EA_REG_IR_2_0().EA_MOD_IR_5_3().EA_TYPE_DATAALTER(); + + p .BRANCH_procedure().PROCEDURE_call_read(); + + p .ALU_BCHG_BCLR_BSET_BTST() + .BRANCH_procedure().PROCEDURE_call_write(); + + p.label("MICROPC_BTST_register"); + + p .SIZE_6().EA_REG_IR_11_9().EA_MOD_DN().EA_TYPE_ALL(); + + p .BRANCH_procedure().PROCEDURE_call_perform_ea_read(); + + p .OP2_FROM_OP1() + .SIZE_6().EA_REG_IR_2_0().EA_MOD_IR_5_3().EA_TYPE_DATA(); + + p .BRANCH_procedure().PROCEDURE_call_read(); + p .BRANCH_procedure().PROCEDURE_call_save_ea(); + + p .ALU_BCHG_BCLR_BSET_BTST() + .BRANCH_procedure().PROCEDURE_return(); + + p.label("MICROPC_TAS"); + + p .READ_MODIFY_WRITE_FLAG_SET() + .SIZE_BYTE().EA_REG_IR_2_0().EA_MOD_IR_5_3().EA_TYPE_DATAALTER(); + + p .BRANCH_procedure().PROCEDURE_call_read(); + + p .ALU_TAS() + .BRANCH_procedure().PROCEDURE_call_perform_ea_write(); + + p .BRANCH_procedure().PROCEDURE_call_save_ea(); + + p .READ_MODIFY_WRITE_FLAG_CLEAR() + .BRANCH_procedure().PROCEDURE_return(); + + p.label("MICROPC_NEGX_CLR_NEG_NOT_NBCD"); + + p .SIZE_3().EA_REG_IR_2_0().EA_MOD_IR_5_3().EA_TYPE_DATAALTER(); + + p .BRANCH_procedure().PROCEDURE_call_read(); + + p .ALU_NEGX_CLR_NEG_NOT_NBCD_SWAP_EXT() + .BRANCH_procedure().PROCEDURE_call_write(); + + p.label("MICROPC_SWAP_EXT"); + + p .SIZE_2().EA_REG_IR_2_0().EA_MOD_DN().EA_TYPE_ALL(); + + p .BRANCH_procedure().PROCEDURE_call_perform_ea_read(); + + p .ALU_NEGX_CLR_NEG_NOT_NBCD_SWAP_EXT() + .BRANCH_procedure().PROCEDURE_call_perform_ea_write(); + + p .BRANCH_procedure().PROCEDURE_return(); + + p.label("MICROPC_TST"); + + p .SIZE_3().EA_REG_IR_2_0().EA_MOD_IR_5_3().EA_TYPE_DATAALTER(); + + p .BRANCH_procedure().PROCEDURE_call_read(); + p .BRANCH_procedure().PROCEDURE_call_save_ea(); + + p .ALU_MOVE() + .BRANCH_procedure().PROCEDURE_return(); + + p.label("MICROPC_ADDQ_SUBQ_not_An"); + + p .OP2_ADDQ_SUBQ() + .SIZE_3().EA_REG_IR_2_0().EA_MOD_IR_5_3().EA_TYPE_DATAALTER(); + + p .BRANCH_procedure().PROCEDURE_call_read(); + + p .ALU_ARITHMETIC_LOGIC() + .BRANCH_procedure().PROCEDURE_call_write(); + + p.label("MICROPC_ADDQ_SUBQ_An"); + + p .OP2_ADDQ_SUBQ() + .SIZE_LONG().EA_REG_IR_2_0().EA_MOD_AN().EA_TYPE_ALL(); + + p .BRANCH_procedure().PROCEDURE_call_perform_ea_read(); + + p .ALU_ADDA_SUBA_CMPA_ADDQ_SUBQ() + .BRANCH_procedure().PROCEDURE_call_perform_ea_write(); + + p .BRANCH_procedure().PROCEDURE_return(); + + p.label("MICROPC_Scc"); + + p .BRANCH_condition_0().offset("scc_condition_0"); + p .OP1_LOAD_ONES(); + + // jump here if condition is false + p .label("scc_condition_0"); + + p .BRANCH_condition_1().offset("scc_condition_1"); + p .OP1_LOAD_ZEROS(); + + // jump here if condition is true + p .label("scc_condition_1"); + + p .ALU_SIMPLE_MOVE() + .SIZE_BYTE().EA_REG_IR_2_0().EA_MOD_IR_5_3().EA_TYPE_DATAALTER(); + + p .BRANCH_procedure().PROCEDURE_call_load_ea(); + p .BRANCH_procedure().PROCEDURE_call_write(); + + p.label("MICROPC_Bcc_BRA"); + + p .OP1_FROM_PC(); + + p .ALU_SIMPLE_MOVE() + .BRANCH_ir().offset("bcc_bra_no_word"); + + p .SIZE_WORD().EA_REG_3b100().EA_MOD_3b111().EA_TYPE_ALL() + .BRANCH_procedure().PROCEDURE_wait_prefetch_valid_32(); + + p .OP1_FROM_IMMEDIATE() + .PC_INCR_BY_SIZE(); + + // jump here if no need to load extra immediate word + p .label("bcc_bra_no_word"); + + p .BRANCH_condition_0().offset("bcc_bra_no_branch"); + + p .OP2_FROM_OP1(); + p .OP2_MOVE_OFFSET() + .OP1_FROM_RESULT(); + + p .ALU_SIMPLE_LONG_ADD(); + + // wait for instruction prefetch + p .BRANCH_procedure().PROCEDURE_wait_prefetch_valid(); + + p .PC_FROM_RESULT(); + + // wait for PC check + p .ALU_SIMPLE_MOVE(); + + // jump here if no branch + p .label("bcc_bra_no_branch"); + + p .BRANCH_procedure().PROCEDURE_return(); + + p.label("MICROPC_DBcc"); + + p .BRANCH_condition_1().offset("dbcc_condition_true"); + + p .OP2_LOAD_1() + .SIZE_WORD().EA_REG_IR_2_0().EA_MOD_DN().EA_TYPE_ALL(); + + p .BRANCH_procedure().PROCEDURE_call_perform_ea_read(); + + p .ALU_SIMPLE_LONG_SUB(); + + p .BRANCH_procedure().PROCEDURE_call_perform_ea_write(); + + p .OP1_FROM_PC() + .SIZE_WORD().EA_REG_3b100().EA_MOD_3b111().EA_TYPE_ALL() + .BRANCH_procedure().PROCEDURE_wait_prefetch_valid_32(); + + p .OP1_FROM_IMMEDIATE() + .ALU_SIMPLE_MOVE(); + + p .BRANCH_result().offset("dbcc_condition_true"); + + p .OP2_FROM_OP1() + .OP1_FROM_RESULT(); + + p .ALU_SIMPLE_LONG_ADD() + // wait for instruction prefetch + .BRANCH_procedure().PROCEDURE_wait_prefetch_valid(); + + p .PC_FROM_RESULT(); + + // wait for PC check + p .ALU_SIMPLE_MOVE(); + + p .BRANCH_procedure().PROCEDURE_return(); + + // jump here if condition is true + p .label("dbcc_condition_true"); + + p .PC_INCR_BY_2() + .BRANCH_procedure().PROCEDURE_return(); + + p.label("MICROPC_MOVE_FROM_SR"); + + p .OP1_FROM_SR() + .SIZE_WORD().EA_REG_IR_2_0().EA_MOD_IR_5_3().EA_TYPE_DATAALTER(); + + p .ALU_SIMPLE_MOVE() + .BRANCH_procedure().PROCEDURE_call_load_ea(); + + p .BRANCH_procedure().PROCEDURE_call_write(); + + p.label("MICROPC_MOVE_TO_CCR_MOVE_TO_SR"); + + p .SIZE_WORD().EA_REG_IR_2_0().EA_MOD_IR_5_3().EA_TYPE_DATA(); + + p .BRANCH_procedure().PROCEDURE_call_read(); + p .BRANCH_procedure().PROCEDURE_call_save_ea(); + + p .ALU_MOVE_TO_CCR_SR_RTE_RTR_STOP_LOGIC_TO_CCR_SR() + .BRANCH_procedure().PROCEDURE_return(); + + p.label("MICROPC_MOVE_USP_to_USP"); + + p .SIZE_LONG().EA_REG_IR_2_0().EA_MOD_AN().EA_TYPE_ALL(); + + p .BRANCH_procedure().PROCEDURE_call_perform_ea_read(); + + p .ALU_SIMPLE_MOVE(); + + p .AN_ADDRESS_USP() + .AN_WRITE_ENABLE_SET(); + + p .BRANCH_procedure().PROCEDURE_return(); + + + p.label("MICROPC_MOVE_USP_to_An"); + + p .OP1_FROM_USP() + .SIZE_LONG().EA_REG_IR_2_0().EA_MOD_AN().EA_TYPE_ALL(); + + p .ALU_SIMPLE_MOVE() + .BRANCH_procedure().PROCEDURE_call_perform_ea_write(); + + p .BRANCH_procedure().PROCEDURE_return(); + + p.label("MICROPC_LINK"); + + // load An to OP1 + p .SIZE_LONG().EA_REG_IR_2_0().EA_MOD_AN().EA_TYPE_ALL(); + p .BRANCH_procedure().PROCEDURE_call_perform_ea_read(); + + // move OP1 to result + p .ALU_LINK_MOVE() + .SIZE_LONG().EA_REG_3b111().EA_MOD_PREDEC().EA_TYPE_ALL(); + + // write result to (SP) + p .BRANCH_procedure().PROCEDURE_call_load_ea(); + p .BRANCH_procedure().PROCEDURE_call_perform_ea_write(); + p .BRANCH_procedure().PROCEDURE_call_save_ea(); + + // load SP to OP1 + p .SIZE_LONG().EA_REG_3b111().EA_MOD_AN().EA_TYPE_ALL(); + p .BRANCH_procedure().PROCEDURE_call_perform_ea_read(); + + // move OP1 to result + p .ALU_SIMPLE_MOVE() + .SIZE_LONG().EA_REG_IR_2_0().EA_MOD_AN().EA_TYPE_ALL(); + + // save result to An + p .BRANCH_procedure().PROCEDURE_call_perform_ea_write(); + + // load offset word to OP1 + p .SIZE_WORD().EA_REG_3b100().EA_MOD_3b111().EA_TYPE_ALL() + .BRANCH_procedure().PROCEDURE_wait_prefetch_valid_32(); + + p .OP1_FROM_IMMEDIATE() + .PC_INCR_BY_SIZE(); + + // move OP1 to OP2 + p .OP2_FROM_OP1() + .SIZE_LONG().EA_REG_3b111().EA_MOD_AN().EA_TYPE_ALL(); + + // load SP to OP1 + p .BRANCH_procedure().PROCEDURE_call_perform_ea_read(); + + // add offset and SP to SP + p .ALU_SIMPLE_LONG_ADD() + .BRANCH_procedure().PROCEDURE_call_perform_ea_write(); + + p .BRANCH_procedure().PROCEDURE_return(); + + p.label("MICROPC_ULNK"); + // load An to OP1 + p .SIZE_LONG().EA_REG_IR_2_0().EA_MOD_AN().EA_TYPE_ALL(); + p .BRANCH_procedure().PROCEDURE_call_perform_ea_read(); + + // move OP1 to result + p .ALU_SIMPLE_MOVE() + .SIZE_LONG().EA_REG_3b111().EA_MOD_AN().EA_TYPE_ALL(); + + // save result to SP + p .BRANCH_procedure().PROCEDURE_call_perform_ea_write(); + + // load (SP) to OP1 + p .SIZE_LONG().EA_REG_3b111().EA_MOD_POSTINC().EA_TYPE_ALL(); + p .BRANCH_procedure().PROCEDURE_call_load_ea(); + p .BRANCH_procedure().PROCEDURE_call_perform_ea_read(); + p .BRANCH_procedure().PROCEDURE_call_save_ea(); + + // move OP1 to result + p .ALU_SIMPLE_MOVE() + .SIZE_LONG().EA_REG_IR_2_0().EA_MOD_AN().EA_TYPE_ALL(); + + // save result to An + p .BRANCH_procedure().PROCEDURE_call_perform_ea_write(); + + p .BRANCH_procedure().PROCEDURE_return(); + + p.label("MICROPC_BSR"); + + p .OP1_FROM_PC(); + + p .ALU_SIMPLE_MOVE() + .BRANCH_ir().offset("bsr_no_word"); + p .SIZE_WORD().EA_REG_3b100().EA_MOD_3b111().EA_TYPE_ALL() + .BRANCH_procedure().PROCEDURE_wait_prefetch_valid_32(); + + p .OP1_FROM_IMMEDIATE() + .PC_INCR_BY_SIZE(); + + // jump here if no need to load extra immediate word + p .label("bsr_no_word"); + + p .OP2_FROM_OP1(); + p .OP2_MOVE_OFFSET() + .OP1_FROM_RESULT(); + + p .ALU_SIMPLE_LONG_ADD(); + + // wait for instruction prefetch + p .BRANCH_procedure().PROCEDURE_wait_prefetch_valid(); + + p .OP1_FROM_PC() + .PC_FROM_RESULT(); + + p .SIZE_LONG().EA_REG_3b111().EA_MOD_PREDEC().EA_TYPE_ALL(); + + p .ALU_SIMPLE_MOVE() + .BRANCH_procedure().PROCEDURE_call_load_ea(); + + p .BRANCH_procedure().PROCEDURE_call_write(); + + p.label("MICROPC_JMP"); + + p .SIZE_LONG().EA_REG_IR_2_0().EA_MOD_IR_5_3().EA_TYPE_CONTROL(); + + p .BRANCH_procedure().PROCEDURE_call_load_ea(); + + p .OP1_FROM_ADDRESS(); + p .ALU_SIMPLE_MOVE(); + + // wait for instruction prefetch + p .BRANCH_procedure().PROCEDURE_wait_prefetch_valid(); + + p .PC_FROM_RESULT(); + + // wait for PC check + p .ALU_SIMPLE_MOVE(); + + p .BRANCH_procedure().PROCEDURE_return(); + + p.label("MICROPC_JSR"); + + p .SIZE_LONG().EA_REG_IR_2_0().EA_MOD_IR_5_3().EA_TYPE_CONTROL(); + + p .BRANCH_procedure().PROCEDURE_call_load_ea(); + + p .OP1_FROM_ADDRESS(); + p .ALU_SIMPLE_MOVE(); + + // wait for instruction prefetch + p .BRANCH_procedure().PROCEDURE_wait_prefetch_valid(); + + p .OP1_FROM_PC() + .PC_FROM_RESULT(); + + p .SIZE_LONG().EA_REG_3b111().EA_MOD_PREDEC().EA_TYPE_ALL(); + + p .ALU_SIMPLE_MOVE() + .BRANCH_procedure().PROCEDURE_call_load_ea(); + + p .BRANCH_procedure().PROCEDURE_call_write(); + + p.label("MICROPC_RTE_RTR"); + + p .SIZE_WORD().EA_REG_3b111().EA_MOD_POSTINC().EA_TYPE_ALL(); + + p .BRANCH_procedure().PROCEDURE_call_read(); + p .BRANCH_procedure().PROCEDURE_call_save_ea(); + + p .ALU_SIMPLE_MOVE() + .SIZE_LONG().EA_REG_3b111().EA_MOD_POSTINC().EA_TYPE_ALL(); + + p .BRANCH_procedure().PROCEDURE_call_read(); + p .BRANCH_procedure().PROCEDURE_call_save_ea(); + + p .ALU_SIMPLE_MOVE() + .OP1_FROM_RESULT(); + p .ALU_MOVE_TO_CCR_SR_RTE_RTR_STOP_LOGIC_TO_CCR_SR(); + + // wait for instruction prefetch + p .BRANCH_procedure().PROCEDURE_wait_prefetch_valid(); + + p .PC_FROM_RESULT(); + + // wait for PC check + p .ALU_SIMPLE_MOVE(); + + p .BRANCH_procedure().PROCEDURE_return(); + + p.label("MICROPC_RTS"); + + p .SIZE_LONG().EA_REG_3b111().EA_MOD_POSTINC().EA_TYPE_ALL(); + + p .BRANCH_procedure().PROCEDURE_call_read(); + p .BRANCH_procedure().PROCEDURE_call_save_ea(); + + p .ALU_SIMPLE_MOVE(); + + // wait for instruction prefetch + p .BRANCH_procedure().PROCEDURE_wait_prefetch_valid(); + + p .PC_FROM_RESULT(); + + // wait for PC check + p .ALU_SIMPLE_MOVE(); + + p .BRANCH_procedure().PROCEDURE_return(); + + p.label("MICROPC_NOP"); + + p .BRANCH_procedure().PROCEDURE_return(); + + p.label("MICROPC_TRAP"); + + p .TRAP_TRAP() + .BRANCH_procedure().PROCEDURE_call_trap(); + + p .BRANCH_procedure().PROCEDURE_return(); + + p.label("MICROPC_TRAPV"); + + p .BRANCH_V().offset("trapv_no_trap"); + + p .TRAP_TRAPV() + .BRANCH_procedure().PROCEDURE_call_trap(); + + // jump here if overflow == 0 + p .label("trapv_no_trap"); + + p .BRANCH_procedure().PROCEDURE_return(); + + p.label("MICROPC_RESET"); + + p .DO_RESET_FLAG_SET(); + p .BRANCH_procedure().PROCEDURE_wait_finished(); + + p .DO_RESET_FLAG_CLEAR() + .BRANCH_procedure().PROCEDURE_return(); + + p.label("MICROPC_STOP"); + + p .SIZE_WORD().EA_REG_3b100().EA_MOD_3b111().EA_TYPE_ALL() + .BRANCH_procedure().PROCEDURE_wait_prefetch_valid_32(); + + p .OP1_FROM_IMMEDIATE() + .PC_INCR_BY_SIZE(); + + p .ALU_MOVE_TO_CCR_SR_RTE_RTR_STOP_LOGIC_TO_CCR_SR() + .STOP_FLAG_SET() + .BRANCH_procedure().PROCEDURE_return(); + } +} Index: trunk/sw/ao68000_tool/src/ao68000_tool/Main.java =================================================================== --- trunk/sw/ao68000_tool/src/ao68000_tool/Main.java (nonexistent) +++ trunk/sw/ao68000_tool/src/ao68000_tool/Main.java (revision 2) @@ -0,0 +1,110 @@ +/* + * Copyright 2010, Aleksander Osman, alfik@poczta.fm. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, are + * permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND + * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +package ao68000_tool; + +import java.io.File; +import java.io.FileOutputStream; + +public class Main { + /** + * Print program call arguments description and exit. + */ + static void print_call_arguments() { + System.out.println("Can not parse program arguments."); + System.out.println(""); + System.out.println("ao68000_tool accepts the following syntax:"); + System.out.println(" [operation arguments]"); + System.out.println(""); + System.out.println("The following are available:"); + System.out.println("\t parser "); + System.out.println("\t microcode "); + System.out.println("\t "); + System.out.println("\t test "); + System.out.println("\t spec_extract "); + System.out.println(""); + System.out.println("For more information please read the ao68000 IP core documentation."); + + System.exit(1); + } + + /** + * @param args - program arguments described in method + * print_call_arguments(). + */ + public static void main(String[] args) { + try { + // check program call arguments + if(args[0].equals("parser") == true && args.length != 3) print_call_arguments(); + else if(args[0].equals("microcode") == true && args.length != 4) print_call_arguments(); + else if(args[0].equals("test") == true && args.length != 5) print_call_arguments(); + else if(args[0].equals("spec_extract") == true && args.length != 3) print_call_arguments(); + + if(args[0].equals("parser")) { + String java = ParseParams.parse(args[1]); + + FileOutputStream output = new FileOutputStream(args[2]); + output.write(java.getBytes()); + output.close(); + } + else if(args[0].equals("microcode")) { + ParseParams.parse(args[1]); + + FileOutputStream microcode_os = new FileOutputStream(args[2]); + FileOutputStream locations_os = new FileOutputStream(args[3]); + + GenerateMicrocode.generate(microcode_os, locations_os); + + microcode_os.close(); + locations_os.close(); + } + else if(args[0].equals("test")) { + File exe1 = new File(args[1]); + File exe2 = new File(args[2]); + + int start = Integer.parseInt(args[3]); + int end = Integer.parseInt(args[4]); + + Tester.start_test(exe1, exe2, start, end); + } + else if(args[0].equals("spec_extract")) { + DocumentationTool.extract(args[1], args[2]); + } + + System.exit(0); + } + catch(Exception e) { + e.printStackTrace(); + + try { + while(true) { + Thread.sleep(1000); + } + } + catch(Exception e2) { + e2.printStackTrace(); + } + } + } +} Index: trunk/sw/ao68000_tool/src/ao68000_tool/Tester.java =================================================================== --- trunk/sw/ao68000_tool/src/ao68000_tool/Tester.java (nonexistent) +++ trunk/sw/ao68000_tool/src/ao68000_tool/Tester.java (revision 2) @@ -0,0 +1,365 @@ +/* + * Copyright 2010, Aleksander Osman, alfik@poczta.fm. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, are + * permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND + * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +package ao68000_tool; + +import java.io.File; +import java.util.HashMap; +import java.util.Random; +import java.util.Vector; + +/* + * 0000 0000 ss ddd DDD : ORI + * + * 0000 rrr1 00 ddd DDD : BTST + * 0000 ddd1 ss 001 sss : MOVEP from memory + * + * 0000 rrr1 01 ddd DDD : BCHG + * 0000 rrr1 10 ddd DDD : BCLR + * 0000 rrr1 11 ddd DDD : BSET + * + * 0000 0010 ss ddd DDD : ANDI + * + * 0000 0100 ss ddd DDD : SUBI + * + * 0000 0110 ss ddd DDD : ADDI + * + * 0000 1000 00 ddd DDD : BTST imm + * 0000 1000 01 ddd DDD : BCHG imm + * 0000 1000 10 ddd DDD : BCLR imm + * 0000 1000 11 ddd DDD : BSET imm + * + * 0000 1010 ss ddd DDD : EORI + * 0000 1100 ss ddd DDD : CMPI + * + * 0000 1110 xx xxx xxx : illegal instruction + * + * 00ss DDDd dd sss SSS : MOVE + * 00ss DDD0 01 sss SSS : MOVEA + * + * 0100 0000 ss ddd DDD : NEGX + * 0100 0000 11 ddd DDD : MOVE FROM SR + * + * 0100 0001 00 xxx xxx : illegal instruction + * + * 0100 rrrs s0 ddd DDD : CHK + * 0100 rrr1 11 ddd DDD : LEA + * + * 0100 0010 ss ddd DDD : CLR + * + * 0100 0100 ss ddd DDD : NEG + * 0100 0100 11 sss SSS : MOVE TO CCR + * 0100 0110 ss ddd DDD : NOT + * 0100 0110 11 sss SSS : MOVE TO SR + * + * 0100 1000 00 ddd DDD : NBCD + * 0100 1000 01 000 rrr : SWAP + * + * 0100 1000 01 001 xxx : illegal instruction + * 0100 1000 01 ddd DDD : PEA + * + * 0100 1000 ss ddd DDD : EXT + * 0100 1000 ss 001 rrr : MOVEM register to memory + * + * 0100 1010 ss ddd DDD : TST + * 0100 1010 11 ddd DDD : TAS + * + * 0100 1010 11 111 100 : ILLEGAL + * + * 0100 1100 ss ddd DDD : MOVEM memory to register + * + * 0100 1110 01 00i iii : TRAP + * + * 0100 1110 01 010 rrr : LNK + * 0100 1110 01 011 rrr : ULNK + * + * 0100 1110 01 10d rrr : MOVE USP + * + * 0100 1110 01 110 000 : RESET + * 0100 1110 01 110 001 : NOP + * 0100 1110 01 110 010 : STOP + * 0100 1110 01 110 011 : RTE + * 0100 1110 01 110 100 : illegal instruction + * 0100 1110 01 110 101 : RTS + * 0100 1110 01 110 110 : TRAPV + * 0100 1110 01 110 111 : RTR + * + * 0100 1110 01 111 xxx : illegal instruction + * 0100 1110 10 sss SSS : JSR + * 0100 1110 11 sss SSS : JMP + * + * 0101 cccc 11 001 rrr : DBcc + * 0101 cccc 11 ddd DDD : Scc + * 0101 qqq1 ss ddd DDD : SUBQ + * 0101 qqq0 ss ddd DDD : ADDQ + * + * 0110 0001 dd ddd ddd : BSR + * 0110 0000 dd ddd ddd : BRA + * 0110 cccc dd ddd ddd : Bcc + * + * 0111 rrr0 dd ddd ddd : MOVEQ + * + * 1011 rrro oo sss SSS : CMP + * 1011 rrro oo sss SSS : CMPA + * 1011 ddd1 ss 001 sss : CMPM + * 1011 ssso oo ddd DDD : EOR + * + * 1101 rrro oo eee EEE : ADD + * 1100 rrro oo eee EEE : AND + * 1000 rrro oo eee EEE : OR + * 1001 rrro oo eee EEE : SUB + * + * 1001 rrro oo sss SSS : SUBA + * 1101 rrro oo sss SSS : ADDA + * + * 1101 ddd1 oo 00m sss : ADDX + * 1001 ddd1 oo 00m sss : SUBX + * + * 1100 ddd1 00 00m sss : ABCD + * 1000 ddd1 00 00m sss : SBCD + * + * 1100 ddd1 oo ooo aaa : EXG + * + * 1100 ddd0 11 sss SSS : MULU + * 1100 ddd1 11 sss SSS : MULS + * 1000 ddd0 11 sss SSS : DIVU + * 1000 ddd1 11 sss SSS : DIVS + * + * 1110 000d 11 sss SSS : ASL,ASR memory + * 1110 cccd ss i00 rrr : ASL,ASR register/immediate + * 1110 001d 11 sss SSS : LSL,LSR memory + * 1110 cccd ss i01 rrr : LSL,LSR register/immediate + * 1110 011d 11 sss SSS : ROL,ROR memory + * 1110 cccd ss i11 rrr : ROL,ROR register/immediate + * 1110 010d 11 sss SSS : ROXL,ROXR memory + * 1110 cccd ss i10 rrr : ROXL,ROXR register/immediate + */ + +public class Tester { + static int get_random(Random random, boolean must_be_even) { + if(global_zero) return 0; + while(true) { + int rand = random.nextInt(); + if(must_be_even == false) return rand; + else if(must_be_even == true && (rand % 2) == 0) return rand; + } + } + static int get_random_bit(Random random) { + if(global_zero) return 0; + return (random.nextInt() % 2 == 0) ? 0 : 1; + } + static int get_random_ipm(Random random) { + if(global_zero) return 0; + int rand = random.nextInt(); + rand = rand % 8; + return (rand < 0) ? -rand : rand; + } + static String get_8_char_hex_string(int val) throws Exception { + String s = Integer.toHexString(val>>>2); + while(s.length() < 8) s = "0" + s; + return s.substring(s.length()-8); + } + static String get_4_char_hex_string(int val) throws Exception { + String s = Integer.toHexString(val); + while(s.length() < 4) s = "0" + s; + return s.substring(s.length()-4); + } + + static void start_test(File exe1, File exe2, int start, int end) throws Exception { + random = new Random(); + for(int i=start; i map_exe1 = start_test_process(common, exe1); + if(map_exe1 == null) throw new Exception("Exe1 odd address read/write."); + + + program_output += "\nRunning exe2: " + exe2.getName() + "\n"; + common.remove(0); + common.add(0, exe2.getCanonicalPath()); + HashMap map_exe2 = start_test_process(common, exe2); + if(map_exe2 == null) throw new Exception("Exe2 odd address read/write."); + + boolean failed = false; + boolean is_blocked = (map_exe1.containsKey("processor blocked") && map_exe2.containsKey("processor blocked")) ? true : false; + for(String key : map_exe1.keySet()) { + String value_emu = map_exe1.get(key); + String value_verilog = map_exe2.get(key); + map_exe2.remove(key); + + // if processor blocked, do not compare PC and SSP registers + if(is_blocked && key.equals("PC")) continue; + if(is_blocked && key.equals("SSP")) continue; + + if(value_emu.equals(value_verilog) == false) { + if(failed == false) System.out.println(""); + System.out.println("Key mismatch: " + key + ": Exe1=" + value_emu + " / Exe2=" + value_verilog); + failed = true; + } + } + for(String key : map_exe2.keySet()) { + if(failed == false) System.out.println(""); + System.out.println("Key mismatch: " + key + ": EXE1=" + null + " / EXE2=" + map_exe2.get(key)); + failed = true; + } + + if(failed) { + System.out.println(""); + throw new Exception("Mismatch detected. Program output:\n" + program_output); + } + } + catch(Exception e) { + String result = ""; + for(String s : common) { + result += s + "\n"; + } + throw new Exception(e.getMessage() + "\nCommon dump:\n" + result + "\nInstruction:\n" + instruction); + } + } + static HashMap start_test_process(Vector common, File file) throws Exception { + + Runtime runtime = Runtime.getRuntime(); + String result = ""; + String addresses = "\n"; + int count=0; + while(true) { + result = ""; + if(file.isDirectory() == false) file = new File(file.getParent()); + Process p = runtime.exec(common.toArray(new String[0]), null, file); + + int read = p.getInputStream().read(); + while(read != -1) { + result += (char)read; + read = p.getInputStream().read(); + } + p.waitFor(); + p.getErrorStream().close(); + p.getInputStream().close(); + p.getOutputStream().close(); + + if(p.exitValue() == 0) break; + else { + int index = result.indexOf("Missing argument: MEM"); + int index2 = result.indexOf("on odd address"); + if(index != -1) { + index += new String("Missing argument: MEM").length(); + result = result.substring(index, index+8); + addresses += result + "\n"; + + String to_add = "+MEM" + result + "=" + Integer.toHexString(get_random(random, false)); + if(to_add.length() > 4+8+1+8) throw new Exception("Illegal memory value length: " + to_add); + common.add(to_add); + } + else if(index2 != -1) { + throw new Exception("Odd address:" + result); + } + else throw new Exception("Error running process:\n" + result); + } + + count++; + if(count == 100) throw new Exception("Number of memory reads exceeded: " + common.firstElement() + " " + addresses); + } + + program_output += result; + + result = result.substring(result.indexOf("START TEST") + new String("START TEST").length()); + String split[] = result.split("\n"); + + HashMap map = new HashMap(); + for(int i=0; i= next_end) { + deep--; + start = next_end + 5; + } + else if(next_start == -1 && next_end != -1) { + deep--; + start = next_end + 5; + } + else throw new Exception("Error parsing file."); + } + String result = all.substring(start_saved, start) + ">"; + + //System.out.println("s: " + start_saved + ", e: " + start); + //System.out.println(result); + + result = result.replaceAll("

", " "); + result = result.replaceAll("

", " "); + + int max=0; + while(result.indexOf("href=\"", max) != -1) { + int i = result.indexOf("href=\"", max); + max = i+6; + + if(result.substring(i).startsWith("href=\"http:")) continue; + + result = result.substring(0, i) + "href=\"file://./doxygen/html/" + result.substring(i+6); + } + + // save output + FileOutputStream out = new FileOutputStream(dest); + out.write(result.getBytes()); + out.close(); + } +} Index: trunk/sw/ao68000_tool/src/ao68000_tool/Parser.java =================================================================== --- trunk/sw/ao68000_tool/src/ao68000_tool/Parser.java (nonexistent) +++ trunk/sw/ao68000_tool/src/ao68000_tool/Parser.java (revision 2) @@ -0,0 +1,719 @@ +package ao68000_tool; +class Parser { + boolean newline; + Parser() { this(true); } + Parser(boolean newline) { this.newline = newline; } + Parser EA_REG_IR_2_0() throws Exception { + GenerateMicrocode.entry(newline, "EA_REG_IR_2_0"); + return new Parser(false); + } + Parser EA_REG_IR_11_9() throws Exception { + GenerateMicrocode.entry(newline, "EA_REG_IR_11_9"); + return new Parser(false); + } + Parser EA_REG_MOVEM_REG_2_0() throws Exception { + GenerateMicrocode.entry(newline, "EA_REG_MOVEM_REG_2_0"); + return new Parser(false); + } + Parser EA_REG_3b111() throws Exception { + GenerateMicrocode.entry(newline, "EA_REG_3b111"); + return new Parser(false); + } + Parser EA_REG_3b100() throws Exception { + GenerateMicrocode.entry(newline, "EA_REG_3b100"); + return new Parser(false); + } + Parser EA_MOD_IR_5_3() throws Exception { + GenerateMicrocode.entry(newline, "EA_MOD_IR_5_3"); + return new Parser(false); + } + Parser EA_MOD_MOVEM_MOD_5_3() throws Exception { + GenerateMicrocode.entry(newline, "EA_MOD_MOVEM_MOD_5_3"); + return new Parser(false); + } + Parser EA_MOD_IR_8_6() throws Exception { + GenerateMicrocode.entry(newline, "EA_MOD_IR_8_6"); + return new Parser(false); + } + Parser EA_MOD_PREDEC() throws Exception { + GenerateMicrocode.entry(newline, "EA_MOD_PREDEC"); + return new Parser(false); + } + Parser EA_MOD_3b111() throws Exception { + GenerateMicrocode.entry(newline, "EA_MOD_3b111"); + return new Parser(false); + } + Parser EA_MOD_DN_PREDEC() throws Exception { + GenerateMicrocode.entry(newline, "EA_MOD_DN_PREDEC"); + return new Parser(false); + } + Parser EA_MOD_DN_AN_EXG() throws Exception { + GenerateMicrocode.entry(newline, "EA_MOD_DN_AN_EXG"); + return new Parser(false); + } + Parser EA_MOD_POSTINC() throws Exception { + GenerateMicrocode.entry(newline, "EA_MOD_POSTINC"); + return new Parser(false); + } + Parser EA_MOD_AN() throws Exception { + GenerateMicrocode.entry(newline, "EA_MOD_AN"); + return new Parser(false); + } + Parser EA_MOD_DN() throws Exception { + GenerateMicrocode.entry(newline, "EA_MOD_DN"); + return new Parser(false); + } + Parser EA_MOD_INDIRECTOFFSET() throws Exception { + GenerateMicrocode.entry(newline, "EA_MOD_INDIRECTOFFSET"); + return new Parser(false); + } + Parser EA_TYPE_ALL() throws Exception { + GenerateMicrocode.entry(newline, "EA_TYPE_ALL"); + return new Parser(false); + } + Parser EA_TYPE_CONTROL_POSTINC() throws Exception { + GenerateMicrocode.entry(newline, "EA_TYPE_CONTROL_POSTINC"); + return new Parser(false); + } + Parser EA_TYPE_CONTROLALTER_PREDEC() throws Exception { + GenerateMicrocode.entry(newline, "EA_TYPE_CONTROLALTER_PREDEC"); + return new Parser(false); + } + Parser EA_TYPE_CONTROL() throws Exception { + GenerateMicrocode.entry(newline, "EA_TYPE_CONTROL"); + return new Parser(false); + } + Parser EA_TYPE_DATAALTER() throws Exception { + GenerateMicrocode.entry(newline, "EA_TYPE_DATAALTER"); + return new Parser(false); + } + Parser EA_TYPE_DN_AN() throws Exception { + GenerateMicrocode.entry(newline, "EA_TYPE_DN_AN"); + return new Parser(false); + } + Parser EA_TYPE_MEMORYALTER() throws Exception { + GenerateMicrocode.entry(newline, "EA_TYPE_MEMORYALTER"); + return new Parser(false); + } + Parser EA_TYPE_DATA() throws Exception { + GenerateMicrocode.entry(newline, "EA_TYPE_DATA"); + return new Parser(false); + } + Parser OP1_FROM_OP2() throws Exception { + GenerateMicrocode.entry(newline, "OP1_FROM_OP2"); + return new Parser(false); + } + Parser OP1_FROM_ADDRESS() throws Exception { + GenerateMicrocode.entry(newline, "OP1_FROM_ADDRESS"); + return new Parser(false); + } + Parser OP1_FROM_DATA() throws Exception { + GenerateMicrocode.entry(newline, "OP1_FROM_DATA"); + return new Parser(false); + } + Parser OP1_FROM_IMMEDIATE() throws Exception { + GenerateMicrocode.entry(newline, "OP1_FROM_IMMEDIATE"); + return new Parser(false); + } + Parser OP1_FROM_RESULT() throws Exception { + GenerateMicrocode.entry(newline, "OP1_FROM_RESULT"); + return new Parser(false); + } + Parser OP1_MOVEQ() throws Exception { + GenerateMicrocode.entry(newline, "OP1_MOVEQ"); + return new Parser(false); + } + Parser OP1_FROM_PC() throws Exception { + GenerateMicrocode.entry(newline, "OP1_FROM_PC"); + return new Parser(false); + } + Parser OP1_LOAD_ZEROS() throws Exception { + GenerateMicrocode.entry(newline, "OP1_LOAD_ZEROS"); + return new Parser(false); + } + Parser OP1_LOAD_ONES() throws Exception { + GenerateMicrocode.entry(newline, "OP1_LOAD_ONES"); + return new Parser(false); + } + Parser OP1_FROM_SR() throws Exception { + GenerateMicrocode.entry(newline, "OP1_FROM_SR"); + return new Parser(false); + } + Parser OP1_FROM_USP() throws Exception { + GenerateMicrocode.entry(newline, "OP1_FROM_USP"); + return new Parser(false); + } + Parser OP1_FROM_AN() throws Exception { + GenerateMicrocode.entry(newline, "OP1_FROM_AN"); + return new Parser(false); + } + Parser OP1_FROM_DN() throws Exception { + GenerateMicrocode.entry(newline, "OP1_FROM_DN"); + return new Parser(false); + } + Parser OP1_FROM_IR() throws Exception { + GenerateMicrocode.entry(newline, "OP1_FROM_IR"); + return new Parser(false); + } + Parser OP1_FROM_FAULT_ADDRESS() throws Exception { + GenerateMicrocode.entry(newline, "OP1_FROM_FAULT_ADDRESS"); + return new Parser(false); + } + Parser OP2_FROM_OP1() throws Exception { + GenerateMicrocode.entry(newline, "OP2_FROM_OP1"); + return new Parser(false); + } + Parser OP2_LOAD_1() throws Exception { + GenerateMicrocode.entry(newline, "OP2_LOAD_1"); + return new Parser(false); + } + Parser OP2_LOAD_COUNT() throws Exception { + GenerateMicrocode.entry(newline, "OP2_LOAD_COUNT"); + return new Parser(false); + } + Parser OP2_ADDQ_SUBQ() throws Exception { + GenerateMicrocode.entry(newline, "OP2_ADDQ_SUBQ"); + return new Parser(false); + } + Parser OP2_MOVE_OFFSET() throws Exception { + GenerateMicrocode.entry(newline, "OP2_MOVE_OFFSET"); + return new Parser(false); + } + Parser OP2_MOVE_ADDRESS_BUS_INFO() throws Exception { + GenerateMicrocode.entry(newline, "OP2_MOVE_ADDRESS_BUS_INFO"); + return new Parser(false); + } + Parser OP2_DECR_BY_1() throws Exception { + GenerateMicrocode.entry(newline, "OP2_DECR_BY_1"); + return new Parser(false); + } + Parser ADDRESS_INCR_BY_SIZE() throws Exception { + GenerateMicrocode.entry(newline, "ADDRESS_INCR_BY_SIZE"); + return new Parser(false); + } + Parser ADDRESS_DECR_BY_SIZE() throws Exception { + GenerateMicrocode.entry(newline, "ADDRESS_DECR_BY_SIZE"); + return new Parser(false); + } + Parser ADDRESS_INCR_BY_2() throws Exception { + GenerateMicrocode.entry(newline, "ADDRESS_INCR_BY_2"); + return new Parser(false); + } + Parser ADDRESS_FROM_AN_OUTPUT() throws Exception { + GenerateMicrocode.entry(newline, "ADDRESS_FROM_AN_OUTPUT"); + return new Parser(false); + } + Parser ADDRESS_FROM_BASE_INDEX_OFFSET() throws Exception { + GenerateMicrocode.entry(newline, "ADDRESS_FROM_BASE_INDEX_OFFSET"); + return new Parser(false); + } + Parser ADDRESS_FROM_IMM_16() throws Exception { + GenerateMicrocode.entry(newline, "ADDRESS_FROM_IMM_16"); + return new Parser(false); + } + Parser ADDRESS_FROM_IMM_32() throws Exception { + GenerateMicrocode.entry(newline, "ADDRESS_FROM_IMM_32"); + return new Parser(false); + } + Parser ADDRESS_FROM_PC_INDEX_OFFSET() throws Exception { + GenerateMicrocode.entry(newline, "ADDRESS_FROM_PC_INDEX_OFFSET"); + return new Parser(false); + } + Parser ADDRESS_FROM_TRAP() throws Exception { + GenerateMicrocode.entry(newline, "ADDRESS_FROM_TRAP"); + return new Parser(false); + } + Parser SIZE_BYTE() throws Exception { + GenerateMicrocode.entry(newline, "SIZE_BYTE"); + return new Parser(false); + } + Parser SIZE_WORD() throws Exception { + GenerateMicrocode.entry(newline, "SIZE_WORD"); + return new Parser(false); + } + Parser SIZE_LONG() throws Exception { + GenerateMicrocode.entry(newline, "SIZE_LONG"); + return new Parser(false); + } + Parser SIZE_1() throws Exception { + GenerateMicrocode.entry(newline, "SIZE_1"); + return new Parser(false); + } + Parser SIZE_1_PLUS() throws Exception { + GenerateMicrocode.entry(newline, "SIZE_1_PLUS"); + return new Parser(false); + } + Parser SIZE_2() throws Exception { + GenerateMicrocode.entry(newline, "SIZE_2"); + return new Parser(false); + } + Parser SIZE_3() throws Exception { + GenerateMicrocode.entry(newline, "SIZE_3"); + return new Parser(false); + } + Parser SIZE_4() throws Exception { + GenerateMicrocode.entry(newline, "SIZE_4"); + return new Parser(false); + } + Parser SIZE_5() throws Exception { + GenerateMicrocode.entry(newline, "SIZE_5"); + return new Parser(false); + } + Parser SIZE_6() throws Exception { + GenerateMicrocode.entry(newline, "SIZE_6"); + return new Parser(false); + } + Parser MOVEM_MODREG_LOAD_0() throws Exception { + GenerateMicrocode.entry(newline, "MOVEM_MODREG_LOAD_0"); + return new Parser(false); + } + Parser MOVEM_MODREG_LOAD_6b001111() throws Exception { + GenerateMicrocode.entry(newline, "MOVEM_MODREG_LOAD_6b001111"); + return new Parser(false); + } + Parser MOVEM_MODREG_INCR_BY_1() throws Exception { + GenerateMicrocode.entry(newline, "MOVEM_MODREG_INCR_BY_1"); + return new Parser(false); + } + Parser MOVEM_MODREG_DECR_BY_1() throws Exception { + GenerateMicrocode.entry(newline, "MOVEM_MODREG_DECR_BY_1"); + return new Parser(false); + } + Parser MOVEM_LOOP_LOAD_0() throws Exception { + GenerateMicrocode.entry(newline, "MOVEM_LOOP_LOAD_0"); + return new Parser(false); + } + Parser MOVEM_LOOP_INCR_BY_1() throws Exception { + GenerateMicrocode.entry(newline, "MOVEM_LOOP_INCR_BY_1"); + return new Parser(false); + } + Parser MOVEM_REG_FROM_OP1() throws Exception { + GenerateMicrocode.entry(newline, "MOVEM_REG_FROM_OP1"); + return new Parser(false); + } + Parser MOVEM_REG_SHIFT_RIGHT() throws Exception { + GenerateMicrocode.entry(newline, "MOVEM_REG_SHIFT_RIGHT"); + return new Parser(false); + } + Parser IR_LOAD_WHEN_PREFETCH_VALID() throws Exception { + GenerateMicrocode.entry(newline, "IR_LOAD_WHEN_PREFETCH_VALID"); + return new Parser(false); + } + Parser PC_FROM_RESULT() throws Exception { + GenerateMicrocode.entry(newline, "PC_FROM_RESULT"); + return new Parser(false); + } + Parser PC_INCR_BY_2() throws Exception { + GenerateMicrocode.entry(newline, "PC_INCR_BY_2"); + return new Parser(false); + } + Parser PC_INCR_BY_4() throws Exception { + GenerateMicrocode.entry(newline, "PC_INCR_BY_4"); + return new Parser(false); + } + Parser PC_INCR_BY_SIZE() throws Exception { + GenerateMicrocode.entry(newline, "PC_INCR_BY_SIZE"); + return new Parser(false); + } + Parser PC_FROM_PREFETCH_IR() throws Exception { + GenerateMicrocode.entry(newline, "PC_FROM_PREFETCH_IR"); + return new Parser(false); + } + Parser PC_INCR_BY_2_IN_MAIN_LOOP() throws Exception { + GenerateMicrocode.entry(newline, "PC_INCR_BY_2_IN_MAIN_LOOP"); + return new Parser(false); + } + Parser TRAP_ILLEGAL_INSTR() throws Exception { + GenerateMicrocode.entry(newline, "TRAP_ILLEGAL_INSTR"); + return new Parser(false); + } + Parser TRAP_DIV_BY_ZERO() throws Exception { + GenerateMicrocode.entry(newline, "TRAP_DIV_BY_ZERO"); + return new Parser(false); + } + Parser TRAP_CHK() throws Exception { + GenerateMicrocode.entry(newline, "TRAP_CHK"); + return new Parser(false); + } + Parser TRAP_TRAPV() throws Exception { + GenerateMicrocode.entry(newline, "TRAP_TRAPV"); + return new Parser(false); + } + Parser TRAP_PRIVIL_VIOLAT() throws Exception { + GenerateMicrocode.entry(newline, "TRAP_PRIVIL_VIOLAT"); + return new Parser(false); + } + Parser TRAP_TRACE() throws Exception { + GenerateMicrocode.entry(newline, "TRAP_TRACE"); + return new Parser(false); + } + Parser TRAP_TRAP() throws Exception { + GenerateMicrocode.entry(newline, "TRAP_TRAP"); + return new Parser(false); + } + Parser TRAP_FROM_DECODER() throws Exception { + GenerateMicrocode.entry(newline, "TRAP_FROM_DECODER"); + return new Parser(false); + } + Parser TRAP_FROM_INTERRUPT() throws Exception { + GenerateMicrocode.entry(newline, "TRAP_FROM_INTERRUPT"); + return new Parser(false); + } + Parser OFFSET_IMM_8() throws Exception { + GenerateMicrocode.entry(newline, "OFFSET_IMM_8"); + return new Parser(false); + } + Parser OFFSET_IMM_16() throws Exception { + GenerateMicrocode.entry(newline, "OFFSET_IMM_16"); + return new Parser(false); + } + Parser INDEX_0() throws Exception { + GenerateMicrocode.entry(newline, "INDEX_0"); + return new Parser(false); + } + Parser INDEX_LOAD_EXTENDED() throws Exception { + GenerateMicrocode.entry(newline, "INDEX_LOAD_EXTENDED"); + return new Parser(false); + } + Parser STOP_FLAG_SET() throws Exception { + GenerateMicrocode.entry(newline, "STOP_FLAG_SET"); + return new Parser(false); + } + Parser STOP_FLAG_CLEAR() throws Exception { + GenerateMicrocode.entry(newline, "STOP_FLAG_CLEAR"); + return new Parser(false); + } + Parser TRACE_FLAG_COPY_WHEN_NO_STOP() throws Exception { + GenerateMicrocode.entry(newline, "TRACE_FLAG_COPY_WHEN_NO_STOP"); + return new Parser(false); + } + Parser GROUP_0_FLAG_SET() throws Exception { + GenerateMicrocode.entry(newline, "GROUP_0_FLAG_SET"); + return new Parser(false); + } + Parser GROUP_0_FLAG_CLEAR_WHEN_VALID_PREFETCH() throws Exception { + GenerateMicrocode.entry(newline, "GROUP_0_FLAG_CLEAR_WHEN_VALID_PREFETCH"); + return new Parser(false); + } + Parser INSTRUCTION_FLAG_SET() throws Exception { + GenerateMicrocode.entry(newline, "INSTRUCTION_FLAG_SET"); + return new Parser(false); + } + Parser INSTRUCTION_FLAG_CLEAR_IN_MAIN_LOOP() throws Exception { + GenerateMicrocode.entry(newline, "INSTRUCTION_FLAG_CLEAR_IN_MAIN_LOOP"); + return new Parser(false); + } + Parser READ_MODIFY_WRITE_FLAG_SET() throws Exception { + GenerateMicrocode.entry(newline, "READ_MODIFY_WRITE_FLAG_SET"); + return new Parser(false); + } + Parser READ_MODIFY_WRITE_FLAG_CLEAR() throws Exception { + GenerateMicrocode.entry(newline, "READ_MODIFY_WRITE_FLAG_CLEAR"); + return new Parser(false); + } + Parser DO_RESET_FLAG_SET() throws Exception { + GenerateMicrocode.entry(newline, "DO_RESET_FLAG_SET"); + return new Parser(false); + } + Parser DO_RESET_FLAG_CLEAR() throws Exception { + GenerateMicrocode.entry(newline, "DO_RESET_FLAG_CLEAR"); + return new Parser(false); + } + Parser DO_INTERRUPT_FLAG_SET_IF_ACTIVE() throws Exception { + GenerateMicrocode.entry(newline, "DO_INTERRUPT_FLAG_SET_IF_ACTIVE"); + return new Parser(false); + } + Parser DO_INTERRUPT_FLAG_CLEAR() throws Exception { + GenerateMicrocode.entry(newline, "DO_INTERRUPT_FLAG_CLEAR"); + return new Parser(false); + } + Parser DO_READ_FLAG_SET() throws Exception { + GenerateMicrocode.entry(newline, "DO_READ_FLAG_SET"); + return new Parser(false); + } + Parser DO_READ_FLAG_CLEAR() throws Exception { + GenerateMicrocode.entry(newline, "DO_READ_FLAG_CLEAR"); + return new Parser(false); + } + Parser DO_WRITE_FLAG_SET() throws Exception { + GenerateMicrocode.entry(newline, "DO_WRITE_FLAG_SET"); + return new Parser(false); + } + Parser DO_WRITE_FLAG_CLEAR() throws Exception { + GenerateMicrocode.entry(newline, "DO_WRITE_FLAG_CLEAR"); + return new Parser(false); + } + Parser DO_BLOCKED_FLAG_SET() throws Exception { + GenerateMicrocode.entry(newline, "DO_BLOCKED_FLAG_SET"); + return new Parser(false); + } + Parser DATA_WRITE_FROM_RESULT() throws Exception { + GenerateMicrocode.entry(newline, "DATA_WRITE_FROM_RESULT"); + return new Parser(false); + } + Parser AN_ADDRESS_FROM_EXTENDED() throws Exception { + GenerateMicrocode.entry(newline, "AN_ADDRESS_FROM_EXTENDED"); + return new Parser(false); + } + Parser AN_ADDRESS_USP() throws Exception { + GenerateMicrocode.entry(newline, "AN_ADDRESS_USP"); + return new Parser(false); + } + Parser AN_ADDRESS_SSP() throws Exception { + GenerateMicrocode.entry(newline, "AN_ADDRESS_SSP"); + return new Parser(false); + } + Parser AN_WRITE_ENABLE_SET() throws Exception { + GenerateMicrocode.entry(newline, "AN_WRITE_ENABLE_SET"); + return new Parser(false); + } + Parser AN_INPUT_FROM_ADDRESS() throws Exception { + GenerateMicrocode.entry(newline, "AN_INPUT_FROM_ADDRESS"); + return new Parser(false); + } + Parser AN_INPUT_FROM_PREFETCH_IR() throws Exception { + GenerateMicrocode.entry(newline, "AN_INPUT_FROM_PREFETCH_IR"); + return new Parser(false); + } + Parser DN_ADDRESS_FROM_EXTENDED() throws Exception { + GenerateMicrocode.entry(newline, "DN_ADDRESS_FROM_EXTENDED"); + return new Parser(false); + } + Parser DN_WRITE_ENABLE_SET() throws Exception { + GenerateMicrocode.entry(newline, "DN_WRITE_ENABLE_SET"); + return new Parser(false); + } + Parser ALU_SR_SET_INTERRUPT() throws Exception { + GenerateMicrocode.entry(newline, "ALU_SR_SET_INTERRUPT"); + return new Parser(false); + } + Parser ALU_SR_SET_TRAP() throws Exception { + GenerateMicrocode.entry(newline, "ALU_SR_SET_TRAP"); + return new Parser(false); + } + Parser ALU_MOVEP_M2R_1() throws Exception { + GenerateMicrocode.entry(newline, "ALU_MOVEP_M2R_1"); + return new Parser(false); + } + Parser ALU_MOVEP_M2R_2() throws Exception { + GenerateMicrocode.entry(newline, "ALU_MOVEP_M2R_2"); + return new Parser(false); + } + Parser ALU_MOVEP_M2R_3() throws Exception { + GenerateMicrocode.entry(newline, "ALU_MOVEP_M2R_3"); + return new Parser(false); + } + Parser ALU_MOVEP_M2R_4() throws Exception { + GenerateMicrocode.entry(newline, "ALU_MOVEP_M2R_4"); + return new Parser(false); + } + Parser ALU_MOVEP_R2M_1() throws Exception { + GenerateMicrocode.entry(newline, "ALU_MOVEP_R2M_1"); + return new Parser(false); + } + Parser ALU_MOVEP_R2M_2() throws Exception { + GenerateMicrocode.entry(newline, "ALU_MOVEP_R2M_2"); + return new Parser(false); + } + Parser ALU_MOVEP_R2M_3() throws Exception { + GenerateMicrocode.entry(newline, "ALU_MOVEP_R2M_3"); + return new Parser(false); + } + Parser ALU_MOVEP_R2M_4() throws Exception { + GenerateMicrocode.entry(newline, "ALU_MOVEP_R2M_4"); + return new Parser(false); + } + Parser ALU_SIGN_EXTEND() throws Exception { + GenerateMicrocode.entry(newline, "ALU_SIGN_EXTEND"); + return new Parser(false); + } + Parser ALU_ARITHMETIC_LOGIC() throws Exception { + GenerateMicrocode.entry(newline, "ALU_ARITHMETIC_LOGIC"); + return new Parser(false); + } + Parser ALU_ABCD_SBCD_ADDX_SUBX() throws Exception { + GenerateMicrocode.entry(newline, "ALU_ABCD_SBCD_ADDX_SUBX"); + return new Parser(false); + } + Parser ALU_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR_prepare() throws Exception { + GenerateMicrocode.entry(newline, "ALU_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR_prepare"); + return new Parser(false); + } + Parser ALU_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR() throws Exception { + GenerateMicrocode.entry(newline, "ALU_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR"); + return new Parser(false); + } + Parser ALU_MOVE() throws Exception { + GenerateMicrocode.entry(newline, "ALU_MOVE"); + return new Parser(false); + } + Parser ALU_ADDA_SUBA_CMPA_ADDQ_SUBQ() throws Exception { + GenerateMicrocode.entry(newline, "ALU_ADDA_SUBA_CMPA_ADDQ_SUBQ"); + return new Parser(false); + } + Parser ALU_CHK() throws Exception { + GenerateMicrocode.entry(newline, "ALU_CHK"); + return new Parser(false); + } + Parser ALU_MULS_MULU_DIVS_DIVU() throws Exception { + GenerateMicrocode.entry(newline, "ALU_MULS_MULU_DIVS_DIVU"); + return new Parser(false); + } + Parser ALU_BCHG_BCLR_BSET_BTST() throws Exception { + GenerateMicrocode.entry(newline, "ALU_BCHG_BCLR_BSET_BTST"); + return new Parser(false); + } + Parser ALU_TAS() throws Exception { + GenerateMicrocode.entry(newline, "ALU_TAS"); + return new Parser(false); + } + Parser ALU_NEGX_CLR_NEG_NOT_NBCD_SWAP_EXT() throws Exception { + GenerateMicrocode.entry(newline, "ALU_NEGX_CLR_NEG_NOT_NBCD_SWAP_EXT"); + return new Parser(false); + } + Parser ALU_SIMPLE_LONG_ADD() throws Exception { + GenerateMicrocode.entry(newline, "ALU_SIMPLE_LONG_ADD"); + return new Parser(false); + } + Parser ALU_SIMPLE_LONG_SUB() throws Exception { + GenerateMicrocode.entry(newline, "ALU_SIMPLE_LONG_SUB"); + return new Parser(false); + } + Parser ALU_MOVE_TO_CCR_SR_RTE_RTR_STOP_LOGIC_TO_CCR_SR() throws Exception { + GenerateMicrocode.entry(newline, "ALU_MOVE_TO_CCR_SR_RTE_RTR_STOP_LOGIC_TO_CCR_SR"); + return new Parser(false); + } + Parser ALU_SIMPLE_MOVE() throws Exception { + GenerateMicrocode.entry(newline, "ALU_SIMPLE_MOVE"); + return new Parser(false); + } + Parser ALU_LINK_MOVE() throws Exception { + GenerateMicrocode.entry(newline, "ALU_LINK_MOVE"); + return new Parser(false); + } + Parser BRANCH_movem_loop() throws Exception { + GenerateMicrocode.entry(newline, "BRANCH_movem_loop"); + return new Parser(false); + } + Parser BRANCH_movem_reg() throws Exception { + GenerateMicrocode.entry(newline, "BRANCH_movem_reg"); + return new Parser(false); + } + Parser BRANCH_operand2() throws Exception { + GenerateMicrocode.entry(newline, "BRANCH_operand2"); + return new Parser(false); + } + Parser BRANCH_special_01() throws Exception { + GenerateMicrocode.entry(newline, "BRANCH_special_01"); + return new Parser(false); + } + Parser BRANCH_special_10() throws Exception { + GenerateMicrocode.entry(newline, "BRANCH_special_10"); + return new Parser(false); + } + Parser BRANCH_condition_0() throws Exception { + GenerateMicrocode.entry(newline, "BRANCH_condition_0"); + return new Parser(false); + } + Parser BRANCH_condition_1() throws Exception { + GenerateMicrocode.entry(newline, "BRANCH_condition_1"); + return new Parser(false); + } + Parser BRANCH_result() throws Exception { + GenerateMicrocode.entry(newline, "BRANCH_result"); + return new Parser(false); + } + Parser BRANCH_V() throws Exception { + GenerateMicrocode.entry(newline, "BRANCH_V"); + return new Parser(false); + } + Parser BRANCH_movep_16() throws Exception { + GenerateMicrocode.entry(newline, "BRANCH_movep_16"); + return new Parser(false); + } + Parser BRANCH_stop_flag_wait_ir_decode() throws Exception { + GenerateMicrocode.entry(newline, "BRANCH_stop_flag_wait_ir_decode"); + return new Parser(false); + } + Parser BRANCH_ir() throws Exception { + GenerateMicrocode.entry(newline, "BRANCH_ir"); + return new Parser(false); + } + Parser BRANCH_trace_flag_and_interrupt() throws Exception { + GenerateMicrocode.entry(newline, "BRANCH_trace_flag_and_interrupt"); + return new Parser(false); + } + Parser BRANCH_group_0_flag() throws Exception { + GenerateMicrocode.entry(newline, "BRANCH_group_0_flag"); + return new Parser(false); + } + Parser BRANCH_procedure() throws Exception { + GenerateMicrocode.entry(newline, "BRANCH_procedure"); + return new Parser(false); + } + Parser PROCEDURE_call_load_ea() throws Exception { + GenerateMicrocode.entry(newline, "PROCEDURE_call_load_ea"); + return new Parser(false); + } + Parser PROCEDURE_call_perform_ea_read() throws Exception { + GenerateMicrocode.entry(newline, "PROCEDURE_call_perform_ea_read"); + return new Parser(false); + } + Parser PROCEDURE_call_perform_ea_write() throws Exception { + GenerateMicrocode.entry(newline, "PROCEDURE_call_perform_ea_write"); + return new Parser(false); + } + Parser PROCEDURE_call_save_ea() throws Exception { + GenerateMicrocode.entry(newline, "PROCEDURE_call_save_ea"); + return new Parser(false); + } + Parser PROCEDURE_return() throws Exception { + GenerateMicrocode.entry(newline, "PROCEDURE_return"); + return new Parser(false); + } + Parser PROCEDURE_wait_finished() throws Exception { + GenerateMicrocode.entry(newline, "PROCEDURE_wait_finished"); + return new Parser(false); + } + Parser PROCEDURE_wait_prefetch_valid() throws Exception { + GenerateMicrocode.entry(newline, "PROCEDURE_wait_prefetch_valid"); + return new Parser(false); + } + Parser PROCEDURE_wait_prefetch_valid_32() throws Exception { + GenerateMicrocode.entry(newline, "PROCEDURE_wait_prefetch_valid_32"); + return new Parser(false); + } + Parser PROCEDURE_jump_to_main_loop() throws Exception { + GenerateMicrocode.entry(newline, "PROCEDURE_jump_to_main_loop"); + return new Parser(false); + } + Parser PROCEDURE_push_micropc() throws Exception { + GenerateMicrocode.entry(newline, "PROCEDURE_push_micropc"); + return new Parser(false); + } + Parser PROCEDURE_call_trap() throws Exception { + GenerateMicrocode.entry(newline, "PROCEDURE_call_trap"); + return new Parser(false); + } + Parser PROCEDURE_pop_micropc() throws Exception { + GenerateMicrocode.entry(newline, "PROCEDURE_pop_micropc"); + return new Parser(false); + } + Parser PROCEDURE_interrupt_mask() throws Exception { + GenerateMicrocode.entry(newline, "PROCEDURE_interrupt_mask"); + return new Parser(false); + } + Parser PROCEDURE_call_read() throws Exception { + GenerateMicrocode.entry(newline, "PROCEDURE_call_read"); + return new Parser(false); + } + Parser PROCEDURE_call_write() throws Exception { + GenerateMicrocode.entry(newline, "PROCEDURE_call_write"); + return new Parser(false); + } + void label(String label) throws Exception { GenerateMicrocode.entry(newline, "label_" + label); } + Parser offset(String label) throws Exception { + GenerateMicrocode.entry(newline, "offset_" + label); + return new Parser(false); + } +} Index: trunk/sw/ao68000_tool/src/ao68000_tool/ParseParams.java =================================================================== --- trunk/sw/ao68000_tool/src/ao68000_tool/ParseParams.java (nonexistent) +++ trunk/sw/ao68000_tool/src/ao68000_tool/ParseParams.java (revision 2) @@ -0,0 +1,121 @@ +/* + * Copyright 2010, Aleksander Osman, alfik@poczta.fm. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, are + * permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND + * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +package ao68000_tool; + +import java.io.File; +import java.io.FileInputStream; +import java.util.Vector; +import java.util.regex.Matcher; +import java.util.regex.Pattern; +import java.util.HashMap; + +class ParseParams { + /** + * Parse microcode_params.v to get information about what to control with the microcode, + * that is, about the microcode parameters. + * + * @param file_name - path to microcode_params.v, + * @return - the contents of Parser.java, + * @throws Exception - in case of file read error. + */ + static String parse(String file_name) throws Exception { + // load file + File file = new File(file_name); + byte bytes[] = new byte[(int)file.length()]; + FileInputStream in = new FileInputStream(file); + if( in.read(bytes) != bytes.length ) throw new Exception("Can not read from file: " + file.getCanonicalPath()); + in.close(); + + // prepare Parser.java header and constructors + String java = ""; + java += "package ao68000_tool;" + "\n"; + java += "class Parser {" + "\n"; + java += "\t" + "boolean newline;" + "\n"; + java += "\t" + "Parser() { this(true); }" + "\n"; + java += "\t" + "Parser(boolean newline) { this.newline = newline; }" + "\n"; + + // prepare data structures to keep information about the microcode parameters + prefixes = new Vector(); + prefix_locations = new HashMap(); + name_values = new HashMap(); + + // split read file into lines + String string = new String(bytes); + String tokens[] = string.split("\\n"); + + // prepare patterns, initialize counters + Pattern pat = Pattern.compile("`define\\s*(\\S+)\\s*(\\d+)'d(\\d+).*"); + int last_parameter_size = 0; + control_bit_offset = 0; + + // parse each line + for(String s : tokens) { + Matcher m0 = pat.matcher(s); + + // match parameter names and values + if( m0.matches() ) { + String name = m0.group(1); + int size = Integer.parseInt(m0.group(2)); + int value = Integer.parseInt(m0.group(3)); + + // check if parameter name ends with _IDLE + if(name.endsWith("_IDLE")) { + last_parameter_size = size; + + String prefix = name.substring(0, name.length()-5); + + prefixes.add(prefix + "_"); + prefix_locations.put(prefix + "_start", control_bit_offset); + prefix_locations.put(prefix + "_end", control_bit_offset+last_parameter_size-1); + control_bit_offset += last_parameter_size; + } + else { + java += "\t" + "Parser " + name + "() throws Exception {" + "\n"; + java += "\t\t" + "GenerateMicrocode.entry(newline, \"" + name + "\");" + "\n"; + java += "\t\t" + "return new Parser(false);" + "\n"; + java += "\t" + "}" + "\n"; + + name_values.put(name, value); + } + } + } + + // prepare Parser.java ending + java += "\t" + "void label(String label) throws Exception { GenerateMicrocode.entry(newline, \"label_\" + label); }" + "\n"; + java += "\t" + "Parser offset(String label) throws Exception {" + "\n"; + java += "\t\t" + "GenerateMicrocode.entry(newline, \"offset_\" + label);" + "\n"; + java += "\t\t" + "return new Parser(false);" + "\n"; + java += "\t" + "}" + "\n"; + + java += "}" + "\n"; + + return java; + } + + static Vector prefixes; + static HashMap name_values; + static HashMap prefix_locations; + static int control_bit_offset; +} Index: trunk/sw/ao68000_tool/manifest.mf =================================================================== --- trunk/sw/ao68000_tool/manifest.mf (nonexistent) +++ trunk/sw/ao68000_tool/manifest.mf (revision 2) @@ -0,0 +1,3 @@ +Manifest-Version: 1.0 +X-COMMENT: Main-Class will be added automatically by build + Index: trunk/sw/ao68000_tool/Makefile =================================================================== --- trunk/sw/ao68000_tool/Makefile (nonexistent) +++ trunk/sw/ao68000_tool/Makefile (revision 2) @@ -0,0 +1,21 @@ +ifndef AO68000_BASE +AO68000_BASE := $(CURDIR)/../.. +endif + +AO68000_RTL := $(AO68000_BASE)/rtl/verilog/ao68000 + +help: + @echo -e "Select operation to perform. Type 'make' followed by the name of the operation." + @echo + @echo -e "Available operations:" + @echo -e "microcode \t- compile microcode for the ao68000." + @echo -e "compile_tool \t- compile the ao68000_tool. Ant tool required." + @echo + @exit 0 + +./dist/ao68000_tool.jar: + ant jar + +microcode: ./dist/ao68000_tool.jar + java -jar ./dist/ao68000_tool.jar parser $(AO68000_RTL)/microcode_params.v ./src/ao68000_tool/Parser.java + java -jar ./dist/ao68000_tool.jar microcode $(AO68000_RTL)/microcode_params.v $(AO68000_RTL)/microcode/microcode.mif $(AO68000_RTL)/microcode/microcode_locations.v Index: trunk/sw/ao68000_tool/build.xml =================================================================== --- trunk/sw/ao68000_tool/build.xml (nonexistent) +++ trunk/sw/ao68000_tool/build.xml (revision 2) @@ -0,0 +1,74 @@ + + + + + + + + + + + Builds, tests, and runs the project ao68000_tool. + + + Index: trunk/sw/nbcd_abcd_sbcd/nbcd_abcd_sbcd.c =================================================================== --- trunk/sw/nbcd_abcd_sbcd/nbcd_abcd_sbcd.c (nonexistent) +++ trunk/sw/nbcd_abcd_sbcd/nbcd_abcd_sbcd.c (revision 2) @@ -0,0 +1,300 @@ +/* + * Copyright 2010, Aleksander Osman, alfik@poczta.fm. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, are + * permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND + * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +/* +struct from_68knotes_t { + unsigned char operand; + unsigned int x; + unsigned char unadjusted; + unsigned char adjusted; + unsigned int v; +}; +struct from_68knotes_t from_68knotes[] = { + { 0x00, 0, 0x00, 0x00, 0 }, + { 0x00, 1, 0xFF, 0x99, 0 }, + { 0xFF, 0, 0x01, 0x9B, 0 }, + { 0xFF, 1, 0x00, 0x9A, 0 }, + { 0x01, 0, 0xFF, 0x99, 0 }, + { 0x01, 1, 0xFE, 0x98, 0 }, + { 0x0F, 0, 0xF1, 0x8B, 0 }, + { 0x0F, 1, 0xF0, 0x8A, 0 }, + { 0xF0, 0, 0x10, 0xB0, 0 }, + { 0xF0, 1, 0x0F, 0xA9, 0 }, + { 0x9A, 0, 0x66, 0x00, 0 }, + { 0x9A, 1, 0x65, 0xFF, 0 }, + { 0x99, 0, 0x67, 0x01, 0 }, + { 0x99, 1, 0x66, 0x00, 0 }, + { 0x10, 0, 0xF0, 0x90, 0 }, + { 0x10, 1, 0xEF, 0x89, 0 }, + { 0x7F, 0, 0x81, 0x1B, 1 }, + { 0x7F, 1, 0x80, 0x1A, 1 }, + { 0x80, 0, 0x80, 0x20, 1 }, + { 0x80, 1, 0x7F, 0x19, 0 }, + { 0x81, 0, 0x7F, 0x19, 0 }, + { 0x81, 1, 0x7E, 0x18, 0 } +}; +*/ + +struct input_t { + unsigned char src; + unsigned char dst; + + unsigned int x; + unsigned int z; + unsigned int v; +}; + +struct output_t { + unsigned char result; + + unsigned int c; + unsigned int v; + unsigned int z; + unsigned int n; + unsigned int x; +}; + +struct output_t uae_nbcd(struct input_t in) { + signed char src = in.dst; + + unsigned short newv_lo = - (src & 0xF) - in.x; + unsigned short newv_hi = - (src & 0xF0); + unsigned short newv; + int cflg; + if (newv_lo > 9) { newv_lo -= 6; } + newv = newv_hi + newv_lo; cflg = (newv & 0x1F0) > 0x90; + if (cflg) newv -= 0x60; + + struct output_t out; + out.c = cflg ? 1 : 0; + out.x = out.c; + out.z = in.z & ((((signed char)(newv)) == 0) ? 1 : 0); + out.n = (((signed char)(newv)) < 0) ? 1 : 0; + out.v = in.v; + + out.result = (newv) & 0xff; + return out; +} +struct output_t verilog_nbcd(struct input_t in) { + struct output_t out; + + unsigned char l = 25 - ((in.dst) & 0x0F); + unsigned char h = 25 - (((in.dst) & 0xF0) >> 4); + + if( ((in.dst) & 0x0F) > 9 ) h -= 1; + + l &= 0x0F; + h &= 0x0F; + + if(in.x == 0) { + if(l == 9) { + l = 0; + h = (h==9) ? 0 : h+1; + } + else if(l == 0xF) { + l = 0; + h += 1; + } + else { + l += 1; + } + } + + l &= 0x0F; + h &= 0x0F; + + out.result = (h << 4) + l; + + out.v = in.v; + out.z = in.z & ((out.result == 0) ? 1 : 0); + out.c = out.x = (in.dst == 0 && in.x == 0) ? 0 : 1; + out.n = (((out.result) & 0x80) == 0) ? 0 : 1; + + return out; +} + +struct output_t uae_abcd(struct input_t in) { + signed char src = in.src; + signed char dst = in.dst; + + unsigned short newv_lo = (src & 0xF) + (dst & 0xF) + (in.x ? 1 : 0); + unsigned short newv_hi = (src & 0xF0) + (dst & 0xF0); + unsigned short newv, tmp_newv; + int cflg; + newv = tmp_newv = newv_hi + newv_lo; if (newv_lo > 9) { newv += 6; } + cflg = (newv & 0x3F0) > 0x90; + if (cflg) newv += 0x60; + + struct output_t out; + out.c = cflg; + out.x = out.c; + out.z = in.z & (((signed char)(newv)) == 0); + out.n = ((signed char)(newv)) < 0; + out.v = (tmp_newv & 0x80) == 0 && (newv & 0x80) != 0; + out.result = (newv) & 0xff; + + return out; +} +struct output_t verilog_abcd(struct input_t in) { + + unsigned char l = (in.src & 0x0F) + (in.dst & 0x0F) + in.x; + unsigned char h = ((in.src & 0xF0) >> 4) + ((in.dst & 0xF0) >> 4); + + int tmp = (in.src + in.dst + in.x) & 0x80; + + l = (l > 0x09) ? (l+6) : l; + h = (l > 0x1F) ? (h+2) : + (l > 0x0F) ? (h+1) : h; + h = (h > 0x09) ? (h+6) : h; + + struct output_t out; + out.c = (h > 0x09) ? 1 : 0; + out.x = out.c; + + l &= 0x0F; + h &= 0x0F; + + out.result = (h << 4) + l; + + out.z = in.z & (out.result == 0); + out.n = ((out.result & 0x80) == 0x80) ? 1 : 0; + out.v = (tmp == 0) && ((out.result & 0x80) != 0); + + return out; +} + +struct output_t uae_sbcd(struct input_t in) { + signed char src = in.src; + signed char dst = in.dst; + + unsigned short newv_lo = (dst & 0xF) - (src & 0xF) - (in.x ? 1 : 0); + unsigned short newv_hi = (dst & 0xF0) - (src & 0xF0); + unsigned short newv, tmp_newv; + int bcd = 0; + newv = tmp_newv = newv_hi + newv_lo; + if (newv_lo & 0xF0) { newv -= 6; bcd = 6; }; + if ((((dst & 0xFF) - (src & 0xFF) - (in.x ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; } + + struct output_t out; + out.c = (((dst & 0xFF) - (src & 0xFF) - bcd - (in.x ? 1 : 0)) & 0x300) > 0xFF; + out.x = out.c; + out.z = in.z & (((signed char)(newv)) == 0); + out.n = ((signed char)(newv)) < 0; + out.v = (tmp_newv & 0x80) != 0 && (newv & 0x80) == 0; + out.result = (newv) & 0xff; + + return out; +} + +struct output_t verilog_sbcd(struct input_t in) { + + unsigned char l = 32 + (in.dst & 0x0F) - (in.src & 0x0F) - in.x; + unsigned char h = 32 + ((in.dst & 0xF0) >> 4) - ((in.src & 0xF0) >> 4); + + int tmp = in.dst - in.src - in.x; + + l = (l < 32) ? (l-6) : l; + h = (l < 16) ? (h-2) : + (l < 32) ? (h-1) : h; + h = (h < 32 && (tmp & 0x100) > 0xFF) ? (h-6) : h; + + struct output_t out; + out.c = (h < 32) ? 1 : 0; + out.x = out.c; + + l &= 0x0F; + h &= 0x0F; + + out.result = (h << 4) + l; + + out.z = in.z & (out.result == 0); + out.n = ((out.result & 0x80) == 0x80) ? 1 : 0; + out.v = ((tmp & 0x80) != 0) && ((out.result & 0x80) == 0); + + return out; +} + +void compare(struct input_t in, struct output_t uae, struct output_t verilog) { + if( uae.result == verilog.result && + uae.c == verilog.c && + uae.v == verilog.v && + uae.z == verilog.z && + uae.n == verilog.n && + uae.x == verilog.x + ) return; + + //printf("%hhx + %hhx + %x: | ", in.dst, in.src, in.x); + //printf("%hhx - %hhx - %x: | ", in.dst, in.src, in.x); + + printf("[Mismatch: in.dst: %hhx, in.src: %hhx, in.x: %x] ", in.dst, in.src, in.x); + + if( uae.result != verilog.result ) printf("result: %hhx != %hhx | ", uae.result, verilog.result); + if( uae.c != verilog.c ) printf("c: %x != %x | ", uae.c, verilog.c); + if( uae.v != verilog.v ) printf("v: %x != %x | ", uae.v, verilog.v); + if( uae.z != verilog.z ) printf("z: %x != %x | ", uae.z, verilog.z); + if( uae.n != verilog.n ) printf("n: %x != %x | ", uae.n, verilog.n); + if( uae.x != verilog.x ) printf("x: %x != %x | ", uae.x, verilog.x); + printf("\n"); +} + +int main(int argc, char **argv) { + struct input_t in; + + int i,j,k,l,m; + for(i=0; i<256; i++) { + for(j=0; j<256; j++) { + for(k=0; k<2; k++) { + for(l=0; l<2; l++) { + for(m=0; m<2; m++) { + in.src = i; + in.dst = j; + in.x = k; + in.z = l; + in.v = m; + + struct output_t uae0 = uae_nbcd(in); + struct output_t verilog0 = verilog_nbcd(in); + + compare(in, uae0, verilog0); + + struct output_t uae1 = uae_abcd(in); + struct output_t verilog1 = verilog_abcd(in); + + compare(in, uae1, verilog1); + + struct output_t uae2 = uae_sbcd(in); + struct output_t verilog2 = verilog_sbcd(in); + + compare(in, uae2, verilog2); + } + } + } + } + } + + return 0; +} + Index: trunk/syn/altera/run/full_system/full_system.qpf =================================================================== --- trunk/syn/altera/run/full_system/full_system.qpf (nonexistent) +++ trunk/syn/altera/run/full_system/full_system.qpf (revision 2) @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2009 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II +# Version 9.1 Build 222 10/21/2009 SJ Web Edition +# Date created = 21:50:15 March 02, 2010 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "9.1" +DATE = "21:50:15 March 02, 2010" + +# Revisions + +PROJECT_REVISION = "full_system" Index: trunk/syn/altera/run/full_system/full_system.qsf =================================================================== --- trunk/syn/altera/run/full_system/full_system.qsf (nonexistent) +++ trunk/syn/altera/run/full_system/full_system.qsf (revision 2) @@ -0,0 +1,167 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2009 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II +# Version 9.1 Build 222 10/21/2009 SJ Web Edition +# Date created = 21:50:15 March 02, 2010 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# full_system_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone II" +set_global_assignment -name DEVICE EP2C70F896C6 +set_global_assignment -name TOP_LEVEL_ENTITY full_system +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:50:15 MARCH 02, 2010" +set_global_assignment -name LAST_QUARTUS_VERSION 9.1 +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 896 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6 +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_global_assignment -name VERILOG_FILE ao68000.v +set_global_assignment -name VERILOG_FILE altera_specific/alu_mult_div.v +set_global_assignment -name VERILOG_FILE altera_specific/register_ram.v +set_global_assignment -name VERILOG_FILE altera_specific/microcode_rom.v +set_global_assignment -name VERILOG_FILE ssram.v +set_global_assignment -name VERILOG_FILE early_boot.v +set_global_assignment -name VERILOG_FILE full_system.v +set_global_assignment -name VERILOG_FILE sd.v +set_global_assignment -name VERILOG_FILE serial_txd.v +set_global_assignment -name VERILOG_FILE timer.v +set_location_assignment PIN_R3 -to clk_i +set_location_assignment PIN_AA23 -to rst_i +set_location_assignment PIN_T26 -to sd_clk_o +set_location_assignment PIN_W29 -to sd_dat_io +set_location_assignment PIN_W28 -to sd_cmd_io +set_location_assignment PIN_AJ6 -to sd_debug[0] +set_location_assignment PIN_AK5 -to sd_debug[1] +set_location_assignment PIN_AJ5 -to sd_debug[2] +set_location_assignment PIN_AJ4 -to sd_debug[3] +set_location_assignment PIN_AK3 -to sd_debug[4] +set_location_assignment PIN_AH4 -to sd_debug[5] +set_location_assignment PIN_D21 -to uart_rxd +set_location_assignment PIN_E21 -to uart_txd +set_location_assignment PIN_G22 -to uart_cts +set_location_assignment PIN_F23 -to uart_rts +set_location_assignment PIN_AG8 -to ssram_address[0] +set_location_assignment PIN_AF8 -to ssram_address[1] +set_location_assignment PIN_AF14 -to ssram_address[10] +set_location_assignment PIN_AG14 -to ssram_address[11] +set_location_assignment PIN_AE15 -to ssram_address[12] +set_location_assignment PIN_AF15 -to ssram_address[13] +set_location_assignment PIN_AC16 -to ssram_address[14] +set_location_assignment PIN_AF20 -to ssram_address[15] +set_location_assignment PIN_AG20 -to ssram_address[16] +set_location_assignment PIN_AE11 -to ssram_address[17] +set_location_assignment PIN_AF11 -to ssram_address[18] +#set_location_assignment PIN_AG10 -to ssram_address[19] +set_location_assignment PIN_AH7 -to ssram_address[2] +#set_location_assignment PIN_AG9 -to ssram_address[20] +set_location_assignment PIN_AG7 -to ssram_address[3] +set_location_assignment PIN_AG6 -to ssram_address[4] +set_location_assignment PIN_AG5 -to ssram_address[5] +set_location_assignment PIN_AE12 -to ssram_address[6] +set_location_assignment PIN_AG12 -to ssram_address[7] +set_location_assignment PIN_AD13 -to ssram_address[8] +set_location_assignment PIN_AE13 -to ssram_address[9] +set_location_assignment PIN_AG17 -to ssram_adsc_n +set_location_assignment PIN_AC18 -to ssram_adsp_n +set_location_assignment PIN_AD16 -to ssram_advance_n +set_location_assignment PIN_AC21 -to ssram_byteen0_n +set_location_assignment PIN_AC20 -to ssram_byteen1_n +set_location_assignment PIN_AD20 -to ssram_byteen2_n +set_location_assignment PIN_AH20 -to ssram_byteen3_n +set_location_assignment PIN_AH19 -to ssram_ce1_n +set_location_assignment PIN_AG19 -to ssram_ce2 +set_location_assignment PIN_AD22 -to ssram_ce3_n +set_location_assignment PIN_AD7 -to ssram_clk +#set_location_assignment PIN_AK9 -to SRAM_DPA[0] +#set_location_assignment PIN_AJ23 -to SRAM_DPA[1] +#set_location_assignment PIN_AK20 -to SRAM_DPA[2] +#set_location_assignment PIN_AJ9 -to SRAM_DPA[3] +set_location_assignment PIN_AH10 -to ssram_data[0] +set_location_assignment PIN_AJ10 -to ssram_data[1] +set_location_assignment PIN_AH17 -to ssram_data[10] +set_location_assignment PIN_AJ18 -to ssram_data[11] +set_location_assignment PIN_AH18 -to ssram_data[12] +set_location_assignment PIN_AK19 -to ssram_data[13] +set_location_assignment PIN_AJ19 -to ssram_data[14] +set_location_assignment PIN_AK23 -to ssram_data[15] +set_location_assignment PIN_AJ20 -to ssram_data[16] +set_location_assignment PIN_AK21 -to ssram_data[17] +set_location_assignment PIN_AJ21 -to ssram_data[18] +set_location_assignment PIN_AK22 -to ssram_data[19] +set_location_assignment PIN_AK10 -to ssram_data[2] +set_location_assignment PIN_AJ22 -to ssram_data[20] +set_location_assignment PIN_AH15 -to ssram_data[21] +set_location_assignment PIN_AJ15 -to ssram_data[22] +set_location_assignment PIN_AJ16 -to ssram_data[23] +set_location_assignment PIN_AK14 -to ssram_data[24] +set_location_assignment PIN_AJ14 -to ssram_data[25] +set_location_assignment PIN_AJ13 -to ssram_data[26] +set_location_assignment PIN_AH13 -to ssram_data[27] +set_location_assignment PIN_AK12 -to ssram_data[28] +set_location_assignment PIN_AK7 -to ssram_data[29] +set_location_assignment PIN_AJ11 -to ssram_data[3] +set_location_assignment PIN_AJ8 -to ssram_data[30] +set_location_assignment PIN_AK8 -to ssram_data[31] +set_location_assignment PIN_AK11 -to ssram_data[4] +set_location_assignment PIN_AH12 -to ssram_data[5] +set_location_assignment PIN_AJ12 -to ssram_data[6] +set_location_assignment PIN_AH16 -to ssram_data[7] +set_location_assignment PIN_AK17 -to ssram_data[8] +set_location_assignment PIN_AJ17 -to ssram_data[9] +set_location_assignment PIN_AG18 -to ssram_globalw_n +set_location_assignment PIN_AD18 -to ssram_oe_n +set_location_assignment PIN_AF18 -to ssram_writeen_n + +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED" +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_location_assignment PIN_AC13 -to pc_debug[0] +set_location_assignment PIN_AB13 -to pc_debug[1] +set_location_assignment PIN_AC12 -to pc_debug[2] +set_location_assignment PIN_AB12 -to pc_debug[3] +set_location_assignment PIN_AC11 -to pc_debug[4] +set_location_assignment PIN_AD9 -to pc_debug[5] +set_location_assignment PIN_AD8 -to pc_debug[6] +set_location_assignment PIN_AJ7 -to pc_debug[7] +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS" +set_global_assignment -name FITTER_EFFORT "AUTO FIT" +set_global_assignment -name SMART_RECOMPILE ON +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file Index: trunk/syn/altera/bin/Makefile =================================================================== --- trunk/syn/altera/bin/Makefile (nonexistent) +++ trunk/syn/altera/bin/Makefile (revision 2) @@ -0,0 +1,22 @@ +help: + @echo -e "Select project to synthesise. Type 'make' followed by the name of the project." + @echo + @echo -e "Available projects:" + @echo -e "full_system \t- system for Terasic DE2-70 board, consists of:" + @echo -e "\t\t ao68000 processor core," + @echo -e "\t\t SSRAM controller," + @echo -e "\t\t SDHC controller," + @echo -e "\t\t serial output," + @echo -e "\t\t boot controller." + @echo + @exit 0 + +full_system: + mkdir -p ./../out/full_system + cp ./../run/full_system/* ./../out/full_system/ + cp ./../../../rtl/verilog/full_system/* ./../out/full_system/ + cp -R ./../../../rtl/verilog/ao68000/* ./../out/full_system/ + cd ./../out/full_system && quartus_sh --flow compile full_system + +clean: + rm -f -R ./../out/full_system Index: trunk/Makefile =================================================================== --- trunk/Makefile (nonexistent) +++ trunk/Makefile (revision 2) @@ -0,0 +1,38 @@ +AO68000_BASE := $(CURDIR) +export AO68000_BASE + +help: + @echo -e "Select operation to perform. Type 'make' followed by the name of the operation." + @echo + @echo -e "Available operations:" + @echo -e "synthesise \t- synthesise full_system SoC with ao68000 processor." + @echo -e "compare \t- run RTL-Software comparison." + @echo -e "docs \t- unpack Doxygen documentation." + @echo -e "clean \t- clean all." + @echo -e "commit \t- commit project to SVN repository." + @echo + @exit 0 + +synthesise: + $(MAKE) -C $(AO68000_BASE)/syn/altera/bin full_system + +docs: + $(MAKE) -C $(AO68000_BASE)/doc unpack + +compare: + $(MAKE) -C $(AO68000_BASE)/sw/ao68000_tool microcode + $(MAKE) -C $(AO68000_BASE)/sim/rtl_sim/bin tb_ao68000 + $(MAKE) -C $(AO68000_BASE)/sim/sw_emulators/bin winuae + $(MAKE) -C $(AO68000_BASE)/sim/rtl_sw_compare/bin tb_ao68000_with_winuae + +clean: + $(MAKE) -C $(AO68000_BASE)/bench/sw_emulators/winuae clean + $(MAKE) -C $(AO68000_BASE)/bench/verilog/tb_ao68000 clean + $(MAKE) -C $(AO68000_BASE)/doc clean + $(MAKE) -C $(AO68000_BASE)/sim/rtl_sim/bin clean + $(MAKE) -C $(AO68000_BASE)/sim/rtl_sw_compare/bin clean + $(MAKE) -C $(AO68000_BASE)/sim/sw_emulators/bin clean + $(MAKE) -C $(AO68000_BASE)/syn/altera/bin clean + +commit: clean + svn commit

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microcode_branch

Setting up the core

Resetting the core

Processor modes

Processor states

WISHBONE IO Ports

Other IO Ports

Requirements

System-on-Chip

Step-by-step instruction to prepare the system

Notes

Linux console output

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