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URL https://opencores.org/ocsvn/apbi2c/apbi2c/trunk

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    /apbi2c
    from Rev 5 to Rev 6
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Rev 5 → Rev 6

/trunk/rtl/module_i2c.v
93,10 → 93,10
input [DWIDTH-1:0] fifo_tx_data_out,
 
//INTERFACE WITH FIFO RECEIVER
input fifo_rx_wr_en,
input fifo_rx_f_full,
input fifo_rx_f_empty,
output [DWIDTH-1:0] fifo_rx_data_in,
output reg fifo_rx_wr_en,
output reg [DWIDTH-1:0] fifo_rx_data_in,
 
//INTERFACE WITH REGISTER CONFIGURATION
input [AWIDTH-1:0] DATA_CONFIG_REG,
119,8 → 119,7
assign RX_EMPTY = (fifo_rx_f_empty == 1'b1)? 1'b1:1'b0;
 
//THIS COUNT IS USED TO CONTROL DATA ACCROSS FSM
reg [1:0] count;
 
reg [1:0] count_tx;
//CONTROL CLOCK AND COUNTER
reg [11:0] count_send_data;
reg BR_CLK_O;
129,8 → 128,6
//RESPONSE USED TO HOLD SIGNAL TO ACK OR NACK
reg RESPONSE;
 
 
 
// TX PARAMETERS USED TO STATE MACHINE
 
localparam [5:0] TX_IDLE = 6'd0, //IDLE
190,11 → 187,6
reg [5:0] next_state_tx;
 
//ASSIGN REGISTERS TO BIDIRETIONAL PORTS
/*
TODO:
We still working on verilog and we no have RX yet. So conections may change in time we are making progress on source code.
 
*/
assign SDA = SDA_OUT;
assign SCL = BR_CLK_O;
 
680,19 → 672,19
else
begin
 
if(count == 2'd0)
if(count_tx == 2'd0)
begin
next_state_tx = TX_ADRESS_1;
end
else if(count == 2'd1)
else if(count_tx == 2'd1)
begin
next_state_tx = TX_DATA0_1;
end
else if(count == 2'd2)
else if(count_tx == 2'd2)
begin
next_state_tx = TX_DATA1_1;
end
else if(count == 2'd3)
else if(count_tx == 2'd3)
begin
next_state_tx = TX_STOP;
end
708,19 → 700,19
end
else
begin
if(count == 2'd0)
if(count_tx == 2'd0)
begin
next_state_tx = TX_CONTROLIN_1;
end
else if(count == 2'd1)
else if(count_tx == 2'd1)
begin
next_state_tx = TX_ADRESS_1;
end
else if(count == 2'd2)
else if(count_tx == 2'd2)
begin
next_state_tx = TX_DATA0_1;
end
else if(count == 2'd3)
else if(count_tx == 2'd3)
begin
next_state_tx = TX_DATA1_1;
end
745,7 → 737,7
 
 
end
//SEQUENTIAL
//SEQUENTIAL TX
always@(posedge PCLK)
begin
 
757,7 → 749,7
state_tx <= TX_IDLE;
SDA_OUT<= 1'b1;
fifo_tx_rd_en <= 1'b0;
count <= 2'd0;
count_tx <= 2'd0;
BR_CLK_O <= 1'b1;
RESPONSE<= 1'b0;
end
809,7 → 801,8
 
if(count_send_data == DATA_CONFIG_REG[13:2]- 12'd1)
begin
SDA_OUT<=fifo_tx_data_out[0:0];
SDA_OUT<=fifo_tx_data_out[0:0];
count_tx <= 2'd0;
end
 
end
1765,28 → 1758,28
begin
 
 
if(count == 2'd0)
if(count_tx == 2'd0)
begin
count <= count + 2'd1;
count_tx <= count_tx + 2'd1;
BR_CLK_O <= 1'b1;
SDA_OUT<=fifo_tx_data_out[8:8];
end
else if(count == 2'd1)
else if(count_tx == 2'd1)
begin
count <= count + 2'd1;
count_tx <= count_tx + 2'd1;
BR_CLK_O <= 1'b1;
SDA_OUT<=fifo_tx_data_out[16:16];
end
else if(count == 2'd2)
else if(count_tx == 2'd2)
begin
count <= count + 2'd1;
count_tx <= count_tx + 2'd1;
BR_CLK_O <= 1'b1;
SDA_OUT<=fifo_tx_data_out[24:24];
end
else if(count == 2'd3)
else if(count_tx == 2'd3)
begin
BR_CLK_O <= 1'b1;
count <= 2'd0;
count_tx <= 2'd0;
end
 
count_send_data <= 12'd0;
1803,7 → 1796,7
begin
count_send_data <= count_send_data + 12'd1;
if(count_send_data < DATA_CONFIG_REG[13:2]/12'd2-12'd2)
if(count_send_data < DATA_CONFIG_REG[13:2]/12'd2)
begin
SDA_OUT<=1'b0;
end
1816,7 → 1809,7
SDA_OUT<=1'b0;
end
 
if(count_send_data < DATA_CONFIG_REG[13:2]/12'd2-12'd2)
if(count_send_data < DATA_CONFIG_REG[13:2]/12'd2)
begin
BR_CLK_O <= 1'b1;
end
1834,28 → 1827,28
begin
count_send_data <= 12'd0;
 
if(count == 2'd0)
if(count_tx == 2'd0)
begin
count <= 2'd0;
count_tx <= 2'd0;
BR_CLK_O <= 1'b1;
SDA_OUT<=fifo_tx_data_out[0:0];
end
else if(count == 2'd1)
else if(count_tx == 2'd1)
begin
count <= 2'd1;
count_tx <= 2'd1;
BR_CLK_O <= 1'b1;
SDA_OUT<=fifo_tx_data_out[8:8];
end
else if(count == 2'd2)
else if(count_tx == 2'd2)
begin
count <= 2'd2;
count_tx <= 2'd2;
BR_CLK_O <= 1'b1;
SDA_OUT<=fifo_tx_data_out[16:16];
end
else if(count == 2'd3)
else if(count_tx == 2'd3)
begin
BR_CLK_O <= 1'b1;
count <= 2'd3;
count_tx <= 2'd3;
SDA_OUT<=fifo_tx_data_out[24:24];
end
 
1895,5 → 1888,788
end
 
 
// RX PARAMETERS USED TO STATE MACHINE
 
localparam [5:0] RX_IDLE = 6'd0, //IDLE
 
RX_START = 6'd1,//START BIT
 
RX_CONTROLIN_1 = 6'd2, //START BYTE
RX_CONTROLIN_2 = 6'd3,
RX_CONTROLIN_3 = 6'd4,
RX_CONTROLIN_4 = 6'd5,
RX_CONTROLIN_5 = 6'd6,
RX_CONTROLIN_6 = 6'd7,
RX_CONTROLIN_7 = 6'd8,
RX_CONTROLIN_8 = 6'd9, //END FIRST BYTE
 
RX_RESPONSE_CIN =6'd10, //RESPONSE
 
RX_ADRESS_1 = 6'd11,//START BYTE
RX_ADRESS_2 = 6'd12,
RX_ADRESS_3 = 6'd13,
RX_ADRESS_4 = 6'd14,
RX_ADRESS_5 = 6'd15,
RX_ADRESS_6 = 6'd16,
RX_ADRESS_7 = 6'd17,
RX_ADRESS_8 = 6'd18,//END FIRST BYTE
 
RX_RESPONSE_ADRESS =6'd19, //RESPONSE
 
RX_DATA0_1 = 6'd20,//START BYTE
RX_DATA0_2 = 6'd21,
RX_DATA0_3 = 6'd22,
RX_DATA0_4 = 6'd23,
RX_DATA0_5 = 6'd24,
RX_DATA0_6 = 6'd25,
RX_DATA0_7 = 6'd26,
RX_DATA0_8 = 6'd27,//END FIRST BYTE
 
RX_RESPONSE_DATA0_1 = 6'd28, //RESPONSE
RX_DATA1_1 = 6'd29,//START BYTE
RX_DATA1_2 = 6'd30,
RX_DATA1_3 = 6'd31,
RX_DATA1_4 = 6'd32,
RX_DATA1_5 = 6'd33,
RX_DATA1_6 = 6'd34,
RX_DATA1_7 = 6'd35,
RX_DATA1_8 = 6'd36,//END FIRST BYTE
 
RX_RESPONSE_DATA1_1 = 6'd37,//RESPONSE
 
RX_DELAY_BYTES = 6'd38,//USED ONLY IN ACK TO DELAY BETWEEN
RX_NACK = 6'd39,//USED ONLY IN ACK TO DELAY BETWEEN BYTES
RX_STOP = 6'd40;//USED TO SEND STOP BIT
 
//STATE CONTROL
reg [5:0] state_rx;
reg [5:0] next_state_rx;
 
reg [11:0] count_receive_data;
 
reg [1:0] count_rx;
 
//COMBINATIONAL BLOCK RX
 
always@(*)
begin
 
 
next_state_rx = state_rx;
 
case(state_rx)//STATE_RX IS MORE SECURE CHANGE ONLY IF YOU KNOW WHAT ARE YOU DOING
RX_IDLE:
begin
//OBEYING SPEC
if(DATA_CONFIG_REG[1] == 1'b0 && DATA_CONFIG_REG[0] == 1'b0)
begin
next_state_rx = RX_IDLE;
end
else if(DATA_CONFIG_REG[1] == 1'b1 && DATA_CONFIG_REG[0] == 1'b1)
begin
next_state_rx = RX_IDLE;
end
else if(DATA_CONFIG_REG[1] == 1'b1 && DATA_CONFIG_REG[0] == 1'b0 && SDA == 1'b0 && SCL == 1'b1)
begin
next_state_rx = RX_START;
end
end
RX_START:
begin
 
if(SDA == 1'b0 && SCL == 1'b1)
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_START;
end
else
begin
next_state_rx = RX_CONTROLIN_1;
end
end
else
begin
next_state_rx = RX_IDLE;
end
end
RX_CONTROLIN_1:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_CONTROLIN_1;
end
else
begin
next_state_rx = RX_CONTROLIN_2;
end
end
RX_CONTROLIN_2:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_CONTROLIN_2;
end
else
begin
next_state_rx = RX_CONTROLIN_3;
end
end
RX_CONTROLIN_3:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_CONTROLIN_3;
end
else
begin
next_state_rx = RX_CONTROLIN_4;
end
end
RX_CONTROLIN_4:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_CONTROLIN_4;
end
else
begin
next_state_rx = RX_CONTROLIN_5;
end
end
RX_CONTROLIN_5:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_CONTROLIN_5;
end
else
begin
next_state_rx = RX_CONTROLIN_6;
end
end
RX_CONTROLIN_6:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_CONTROLIN_6;
end
else
begin
next_state_rx = RX_CONTROLIN_7;
end
end
RX_CONTROLIN_7:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_CONTROLIN_7;
end
else
begin
next_state_rx = RX_CONTROLIN_8;
end
end
RX_CONTROLIN_8:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_CONTROLIN_8;
end
else
begin
next_state_rx = RX_RESPONSE_CIN;
end
end
RX_RESPONSE_CIN:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_CONTROLIN_8;
end
else
begin
next_state_rx = RX_RESPONSE_CIN;
end
end
 
RX_ADRESS_1:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_ADRESS_1;
end
else
begin
next_state_rx = RX_ADRESS_2;
end
end
RX_ADRESS_2:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_ADRESS_2;
end
else
begin
next_state_rx = RX_ADRESS_3;
end
end
RX_ADRESS_3:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_ADRESS_3;
end
else
begin
next_state_rx = RX_ADRESS_4;
end
end
RX_ADRESS_4:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_ADRESS_4;
end
else
begin
next_state_rx = RX_ADRESS_5;
end
end
RX_ADRESS_5:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_ADRESS_5;
end
else
begin
next_state_rx = RX_ADRESS_6;
end
end
RX_ADRESS_6:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_ADRESS_6;
end
else
begin
next_state_rx = RX_ADRESS_7;
end
end
RX_ADRESS_7:
begin
 
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_ADRESS_7;
end
else
begin
next_state_rx = RX_ADRESS_8;
end
 
end
RX_ADRESS_8:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_ADRESS_8;
end
else
begin
next_state_rx = RX_RESPONSE_ADRESS;
end
end
RX_RESPONSE_ADRESS:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_RESPONSE_ADRESS;
end
else
begin
next_state_rx = RX_DATA0_1;
end
end
 
RX_DATA0_1:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_DATA0_1;
end
else
begin
next_state_rx = RX_DATA0_2;
end
end
RX_DATA0_2:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_DATA0_2;
end
else
begin
next_state_rx = RX_DATA0_3;
end
end
RX_DATA0_3:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_DATA0_3;
end
else
begin
next_state_rx = RX_DATA0_4;
end
end
RX_DATA0_4:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_DATA0_4;
end
else
begin
next_state_rx = RX_DATA0_5;
end
end
RX_DATA0_5:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_DATA0_5;
end
else
begin
next_state_rx = RX_DATA0_6;
end
end
RX_DATA0_6:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_DATA0_6;
end
else
begin
next_state_rx = RX_DATA0_7;
end
end
RX_DATA0_7:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_DATA0_7;
end
else
begin
next_state_rx = RX_DATA0_8;
end
end
RX_DATA0_8:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_DATA0_8;
end
else
begin
next_state_rx = RX_RESPONSE_DATA0_1;
end
end
RX_RESPONSE_DATA0_1:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_RESPONSE_DATA0_1;
end
else
begin
next_state_rx = RX_DATA1_1;
end
end
RX_DATA1_1:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_DATA1_1;
end
else
begin
next_state_rx = RX_DATA1_2;
end
end
RX_DATA1_2:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_DATA1_1;
end
else
begin
next_state_rx = RX_DATA1_3;
end
end
RX_DATA1_3:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_DATA1_3;
end
else
begin
next_state_rx = RX_DATA1_4;
end
end
RX_DATA1_4:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_DATA1_4;
end
else
begin
next_state_rx = RX_DATA1_5;
end
end
RX_DATA1_5:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_DATA1_5;
end
else
begin
next_state_rx = RX_DATA1_6;
end
end
RX_DATA1_6:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_DATA1_6;
end
else
begin
next_state_rx = RX_DATA1_7;
end
end
RX_DATA1_7:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_DATA1_7;
end
else
begin
next_state_rx = RX_DATA1_8;
end
end
RX_DATA1_8:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_DATA1_8;
end
else
begin
next_state_rx = RX_RESPONSE_DATA1_1;
end
end
RX_RESPONSE_DATA1_1:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_RESPONSE_DATA1_1;
end
else
begin
next_state_rx = RX_DELAY_BYTES;
end
end
RX_DELAY_BYTES:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_DELAY_BYTES;
end
else
begin
 
if(count_rx == 2'd0)
begin
next_state_rx = RX_ADRESS_1;
end
else if(count_rx == 2'd1)
begin
next_state_rx = RX_DATA0_1;
end
else if(count_rx == 2'd2)
begin
next_state_rx = RX_DATA1_1;
end
else if(count_rx == 2'd3)
begin
next_state_rx = RX_STOP;
end
end
end
RX_NACK:
begin
 
if(count_receive_data != DATA_CONFIG_REG[13:2]*2'd2)
begin
next_state_rx = RX_NACK;
end
else
begin
if(count_rx == 2'd0)
begin
next_state_rx = RX_CONTROLIN_1;
end
else if(count_rx == 2'd1)
begin
next_state_rx = RX_ADRESS_1;
end
else if(count_rx == 2'd2)
begin
next_state_rx = RX_DATA0_1;
end
else if(count_rx == 2'd3)
begin
next_state_rx = RX_DATA1_1;
end
end
 
 
end
RX_STOP:
begin
 
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_STOP;
end
else
begin
next_state_rx = RX_IDLE;
end
 
end
default:
begin
next_state_rx = RX_IDLE;
end
endcase
end
 
 
//SEQUENTIAL BLOCK RX
 
always@(posedge PCLK)
begin
 
if(!PRESETn)
begin
//SIGNALS MUST BE RESETED
count_receive_data <= 12'd0;
state_rx <= RX_IDLE;
fifo_rx_wr_en <= 1'b0;
count_rx <= 2'd0;
end
else
begin
 
state_rx <= next_state_rx;
 
case(state_rx)//STATE_RX IS MORE SECURE CHANGE ONLY IF YOU KNOW WHAT ARE YOU DOING
RX_IDLE:
begin
if(SDA == 1'b0 && SCL == 1'b1)
begin
count_receive_data <= count_receive_data +12'd1;
end
else
begin
count_receive_data <= 12'd0;
end
end
RX_START:
begin
if(SDA == 1'b0 && SCL == 1'b0)
begin
count_receive_data <= count_receive_data +12'd1;
end
else
begin
count_receive_data <= 12'd0;
end
end
RX_CONTROLIN_1:
begin
end
RX_CONTROLIN_2:
begin
 
end
RX_CONTROLIN_3:
begin
 
end
RX_CONTROLIN_4:
begin
 
end
RX_CONTROLIN_5:
begin
 
end
RX_CONTROLIN_6:
begin
 
end
RX_CONTROLIN_7:
begin
 
end
RX_CONTROLIN_8:
begin
 
end
RX_RESPONSE_CIN:
begin
 
end
RX_ADRESS_1:
begin
end
RX_ADRESS_2:
begin
end
RX_ADRESS_3:
begin
end
RX_ADRESS_4:
begin
end
RX_ADRESS_5:
begin
end
RX_ADRESS_6:
begin
end
RX_ADRESS_7:
begin
end
RX_ADRESS_8:
begin
end
RX_RESPONSE_ADRESS:
begin
 
end
RX_DATA0_1:
begin
 
end
RX_DATA0_2:
begin
 
end
RX_DATA0_3:
begin
 
end
RX_DATA0_4:
begin
 
end
RX_DATA0_5:
begin
 
end
RX_DATA0_6:
begin
 
end
RX_DATA0_7:
begin
 
end
RX_DATA0_8:
begin
 
end
RX_RESPONSE_DATA0_1:
begin
end
 
RX_DATA1_1:
begin
 
end
RX_DATA1_2:
begin
 
end
RX_DATA1_3:
begin
 
end
RX_DATA1_4:
begin
 
end
RX_DATA1_5:
begin
 
end
RX_DATA1_6:
begin
 
end
RX_DATA1_7:
begin
 
end
RX_DATA1_8:
begin
 
end
RX_RESPONSE_DATA1_1:
begin
end
RX_DELAY_BYTES:
begin
 
end
RX_NACK:
begin
 
 
end
RX_STOP:
begin
 
 
end
default:
begin
count_receive_data <= 12'd4095;
fifo_rx_wr_en <= 1'b0;
count_rx <= 2'd3;
end
endcase
end
end
 
endmodule

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