OpenCores
URL https://opencores.org/ocsvn/async_sdm_noc/async_sdm_noc/trunk

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Rev 60 → Rev 61

/clos_opt/clos_opt/stg/ibctl.v
0,0 → 1,49
// Verilog model for ibctl
// Generated by petrify 4.2 (compiled 15-Oct-03 at 3:06 PM)
// CPU time for synthesis (host <unknown>): 0.07 seconds
// Estimated area = 8.00
 
// The circuit is self-resetting and does not need reset pin.
 
module ibctl_net (
dec,
do,
doa,
eof,
dia,
eofa,
deca
);
 
input dec;
input do;
input doa;
input eof;
 
output dia;
output eofa;
output deca;
 
 
// Functions not mapped into library gates:
// ----------------------------------------
 
// Equation: dia = eof + do
or _U0 (dia, do, eof);
 
// Equation: eofa = eof' eofa + doa'
not _U1 (_X0, doa);
not _U2 (_X1, eof);
and _U3 (_X2, _X1, eofa);
or _U4 (eofa, _X0, _X2);
 
// Equation: deca = eof' eofa + doa'
not _U5 (_X3, doa);
not _U6 (_X4, eof);
and _U7 (_X5, _X4, eofa);
or _U8 (deca, _X3, _X5);
 
 
// signal values at the initial state:
// !dec !do !doa !eof !dia eofa deca
endmodule
/clos_opt/clos_opt/stg/ibctl.g
0,0 → 1,56
# the STG for the controller of the last stage of input buffers
# eofa- is intentionally postponed after doa- for simplier circuit
# it is assumed dec+ happen before hdd(do+) already in realy circuits they can occure simultaneously
# However, this assumption simplify the STG and do not cause any malfunction in real circuit
# the control circuit generated by Petrify is ibctl.v
# using command: petrify ibctl.g -vl ibctl.v -rst0 -topt -icsc5 -fr10 -o ibctl.g.csc
#
# Wei Song, 16/06/2011 <wsong83@gmail.com>
 
 
.model ibctl
 
.inputs dec do doa eof
.outputs dia eofa deca
.dummy hdd data_data
 
.initial state eofa deca
 
.graph
 
Data do+/1
do+/1 dia+/1
do+/1 doa+/1
dia+/1 do-/1
doa+/1 do-/1
do-/1 dia-/1
do-/1 doa-/1
dia-/1 data_data
doa-/1 data_data
data_data Data
 
Data eof+
eof+ dia+/2
eof+ doa+/2
doa+/2 deca-
deca- dec-
dec- doa-/2
doa+/2 eofa-
eofa- eof-
dia+/2 eof-
eof- doa-/2
eof- dia-/2
doa-/2 deca+
doa-/2 eofa+
dia-/2 dec+
deca+ dec+
dec+ hdd
eofa+ hdd
 
 
hdd Data
 
.marking {<dia-/2,dec+> <eofa+,hdd> <deca+,dec+>}
 
 
.end
/clos_opt/clos_opt/stg/ibctl.g.ps
0,0 → 1,1158
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/clos_opt/common/src/addr_dec.v
0,0 → 1,43
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
XY address decoder, 1-of-4 code
* Assuming the output will be capture for long time
* The withdrawal of inputs are not guarded
History:
14/07/2010 Initial version. <wsong83@gmail.com>
*/
 
module addr_dec(/*AUTOARG*/
// Outputs
dec,
// Inputs
locx, locy, tarx, tary
);
input [7:0] locx, locy; // the local addresses
input [7:0] tarx, tary; // the target addresses in the incoming frame
output [4:0] dec; // the decoded routing request
 
wire [3:0][2:0] cmp; // compare results
 
comp4 X0 (.a(tarx[3:0]), .b(locx[3:0]), .q(dec[0]));
comp4 X1 (.a(tarx[7:4]), .b(locx[7:4]), .q(dec[1]));
comp4 Y0 (.a(tary[3:0]), .b(locy[3:0]), .q(dec[2]));
comp4 Y1 (.a(tary[7:4]), .b(locy[7:4]), .q(dec[3]));
 
assign dec[0] = dec[1][1] | (dec[1][2]&dec[0][1]); // south, tarx < locx
assign dec[1] = dec[1][2]&dec[0][2]&(dec[3][0]|(dec[3][2]&dec[2][0])); // west, tary > locy
assign dec[2] = dec[1][0] | (dec[1][2]&dec[0][0]); // north, tarx < locx
assign dec[3] = dec[1][2]&dec[0][2]&(dec[3][1]|(dec[3][2]&dec[2][1])); // west, tary < locy
assign dec[4] = dec[3][2]&dec[2][2]&dec[1][2]&dec[0][2];
endmodule // addr_dec

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