OpenCores
URL https://opencores.org/ocsvn/async_sdm_noc/async_sdm_noc/trunk

Subversion Repositories async_sdm_noc

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /async_sdm_noc/branches
    from Rev 73 to Rev 74
    ↔ Reverse comparison
  •

Rev 73 → Rev 74

/clos_opt/clos_opt/src/subc_ctl.v File deleted \ No newline at end of file
/clos_opt/clos_opt/src/input_buf.v
143,11 → 143,13
end // block: DP
endgenerate
 
generate for(i=2; i<PD; i++) begin: DPA
assign pdan[i] = rst_n ? ~(pda[i]|pd4[i-1]) : 0;
assign pd4an[i] = pdan[i];
end
generate
for(i=2; i<PD; i++) begin: DPA
assign pdan[i] = rst_n ? ~(pda[i]|pd4[i-1]) : 0;
assign pd4an[i] = pdan[i];
end
 
// in case only one pipeline stage is configured
if(PD>1)
assign ia = pda[PD]|pd4[PD-1];
else
189,11 → 191,11
routing_decision // the comparator
RTD(
.addrx ( addrx )
,.addry ( addry )
,.pipe_xd ( pipe_xd )
,.pipe_yd ( pipe_yd )
,.decision ( raw_dec )
.addrx ( addrx ),
.addry ( addry ),
.pipe_xd ( pipe_xd ),
.pipe_yd ( pipe_yd ),
.decision ( raw_dec )
);
 
// translate it into the XY dec; not QDI here as the circuit can be slow
205,10 → 207,12
PDEC (
.d_in_a ( rta ),
.d_out ( dec_reg ),
.d_in ( raw_dec ),
.d_out_a ( xy_dec )
.d_in ( xy_dec ),
.d_out_a ( decan )
);
 
assign decan = ~(&deca);
 
// generate the arbiter request signals
assign deco =
DIR == 0 ? {dec_reg[4],dec_reg[2],dec_reg[1],dec_reg[3]} : // south port
231,18 → 235,6
for(j=0; j<SCN; j++) begin: SC
// the sub-channel controller
ppc SCH_C (
.nack ( pdan[0][j] ),
.rt_rst ( rtrst[j] ),
.ai2cb ( oa[j] ),
.ack ( pda[1][j] ),
.eof ( pd4[0][j] ),
.rt_ra ( rt_ack ),
.rt_err ( rt_err ),
.rst_n ( rst_n )
);
assign pd4an[0][j] = pdan[0][j];
 
ppc SCH_C (
.deca ( deca[j] ),
.dia ( pda1[j] ),
.eof ( pd4[0][j] ),
249,31 → 241,46
.doa ( acko[j]|(pda[0][j]&rt_err) ), // to handle faulty frames
.dec ( rta )
);
 
// the lookahead pipeline
`ifdef ENABLE_LOOKAHEAD
c2n CD (.q(acko[j]), .a(oa[j]), .b(pda[0][j])); // the C2N gate to avoid early withdrawal
`else
assign acko = ai2cb;
assign acko[j] = oa[j];
`endif
 
// the ack lines for the last two pipeline stages
assign pdan[0][j] = (~oa[j])&rst_n;
assign pda4n[0][j] = (~deca[j])&rst_n;
assign pdan[1][j] = (~pda1[j])&rst_n;
assign pda4n[1][j] = pdan[1][j];
end // block: SC
`else // !`ifdef ENABLE_CHANNEL_SLICING
subc_ctl SCH_C (
.nack ( pdan[0] ),
.rt_rst ( rtrst ),
.ai2cb ( oa ),
.ack ( pda[1] ),
.eof ( pd4[0] ),
.rt_ra ( rt_ack ),
.rt_err ( rt_err ),
.rst_n ( rst_n )
);
assign pd4an[0] = pdan[0];
ppc SCH_C (
.deca ( deca ),
.dia ( pda1 ),
.eof ( pd4[0] ),
.doa ( acko|(pda[0]&rt_err) ), // to handle faulty frames
.dec ( rta )
);
// the lookahead pipeline
`ifdef ENABLE_LOOKAHEAD
c2n CD (.q(acko), .a(oa), .b(pda[0])); // the C2N gate to avoid early withdrawal
`else
assign acko = oa;
`endif
// the ack lines for the last two pipeline stages
assign pdan[0] = (~oa)&rst_n;
assign pda4n[0] = (~deca)&rst_n;
assign pdan[1] = (~pda1)&rst_n;
assign pda4n[1] = pdan[1];
`endif // !`ifdef ENABLE_CHANNEL_SLICING
// the router controller part
assign rten = ~rt_ack;
assign frame_end = &rtrst;
 
endmodule // inp_buf
 
 
/clos_opt/clos_opt/src/clos_buf.v
20,7 → 20,17
// the router structure definitions
`include "define.v"
 
module clos (/*AUTOARG*/);
module clos (/*AUTOARG*/
// Outputs
so0, so1, so2, so3, wo0, wo1, wo2, wo3, no0, no1, no2, no3, eo0,
eo1, eo2, eo3, lo0, lo1, lo2, lo3, so4, wo4, no4, eo4, lo4, sia,
wia, nia, eia, lia,
// Inputs
si0, si1, si2, si3, wi0, wi1, wi2, wi3, ni0, ni1, ni2, ni3, ei0,
ei1, ei2, ei3, li0, li1, li2, li3, si4, wi4, ni4, ei4, li4, soa,
woa, noa, eoa, loa, soa4, woa4, noa4, eoa4, loa4, sdec, ndec, ldec,
wdec, edec
);
parameter MN = 2; // number of CMs
parameter NN = 2; // number of ports in an IM or OM, equ. to number of virtual circuits
44,17 → 54,17
output [NN-1:0][SCN-1:0] so4, wo4, no4, eo4, lo4;
output [NN-1:0][SCN-1:0] sia, wia, nia, eia, lia;
input [NN-1:0][SCN-1:0] soa, woa, noa, eoa, loa;
`ifdef ENABLE_BUFFERED_CLOS
// `ifdef ENABLE_BUFFERED_CLOS
input [NN-1:0][SCN-1:0] soa4, woa4, noa4, eoa4, loa4; // the eof ack from output buffers
`endif
// `endif
`else
input [NN-1:0] si4, wi4, ni4, ei4, li4;
output [NN-1:0] so4, wo4, no4, eo4, lo4;
output [NN-1:0] sia, wia, nia, eia, lia;
input [NN-1:0] soa, woa, noa, eoa, loa;
`ifdef ENABLE_BUFFERED_CLOS
// `ifdef ENABLE_BUFFERED_CLOS
input [NN-1:0] soa4, woa4, noa4, eoa4, loa4; // the eof ack from output buffers
`endif
// `endif
`endif // !`ifdef ENABLE_CHANNEL_SLICING
 
input [NN-1:0][3:0] sdec, ndec, ldec; // the routing requests
/clos_opt/clos_opt/src/output_buf.v
0,0 → 1,162
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
Output buffer for Wormhole/SDM routers.
*** SystemVerilog is used ***
References
* Lookahead pipelines
Montek Singh and Steven M. Nowick}, The design of high-performance dynamic asynchronous pipelines: lookahead style, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2007(15), 1256-1269. doi:10.1109/TVLSI.2007.902205
History:
26/05/2009 Initial version. <wsong83@gmail.com>
20/09/2010 Supporting channel slicing and SDM using macro difinitions. <wsong83@gmail.com>
22/10/2010 Parameterize the number of pipelines in output buffers. <wsong83@gmail.com>
23/05/2011 Clean up for opensource. <wsong83@gmail.com>
21/06/2011 Move the eof logic in every pipeline stage outside the pipe4 module. <wsong83@gmail.com>
20/07/2011 Preparation for the buffered Clos switch. <wsong83@gmail.com>
 
*/
 
// the router structure definitions
`include "define.v"
 
// the out buffer
module outp_buf (/*AUTOARG*/
// Outputs
o0, o1, o2, o3, o4, ia, ia4,
// Inputs
rst_n, i0, i1, i2, i3, i4, oa
);
parameter DW = 16; // the datawidth of a single virtual circuit
parameter PD = 2; // buffer depth
parameter SCN = DW/2; // the number of 1-of-4 sub-channel in each virtual circuit
 
input rst_n; // global reset, active low
input [SCN-1:0] i0, i1, i2, i3; // data input
output [SCN-1:0] o0, o1, o2, o3; // data output
wire [PD:0][SCN-1:0] pd0, pd1, pd2, pd3; // data wires for the internal pipeline satges
`ifdef ENABLE_CHANNEL_SLICING
input [SCN-1:0] i4, oa; // eof and ack
output [SCN-1:0] o4, ia;
wire [SCN-1:0] ian_dly;
wire [PD:0][SCN-1:0] pd4, pda, pdan, pd4an; // internal eof and ack
`else
input i4, oa; // eof and ack
output o4, ia, ia4;
wire ian_dly;
wire [PD:0] pd4, pda, pdan, pd4an; // internal eof and ack
`endif
 
 
//-------------------------- pipeline ---------------------------------------//
genvar i,j;
generate for(i=0; i<PD; i++) begin: DP
`ifdef ENABLE_CHANNEL_SLICING
for(j=0; j<SCN; j++) begin: SC
pipe4 #(.DW(2))
P (
.o0 ( pd0[i][j] ),
.o1 ( pd1[i][j] ),
.o2 ( pd2[i][j] ),
.o3 ( pd3[i][j] ),
.ia ( pda[i+1][j] ),
.i0 ( pd0[i+1][j] ),
.i1 ( pd1[i+1][j] ),
.i2 ( pd2[i+1][j] ),
.i3 ( pd3[i+1][j] ),
.oa ( pdan[i][j] )
);
 
pipen #(.DW(1))
PEoF (
.d_in_a ( ),
.d_out ( pd4[i][j] ),
.d_in ( pd4[i+1][j] ),
.d_out_a ( pd4an[i][j] )
);
end // block: SC
 
`else // !`ifdef ENABLE_CHANNEL_SLICING
pipe4 #(.DW(DW))
P (
.o0 ( pd0[i] ),
.o1 ( pd1[i] ),
.o2 ( pd2[i] ),
.o3 ( pd3[i] ),
.ia ( pda[i+1] ),
.i0 ( pd0[i+1] ),
.i1 ( pd1[i+1] ),
.i2 ( pd2[i+1] ),
.i3 ( pd3[i+1] ),
.oa ( pdan[i] )
);
 
pipen #(.DW(1))
PEoF (
.d_in_a ( ),
.d_out ( pd4[i] ),
.d_in ( pd4[i+1] ),
.d_out_a ( pd4an[i] )
);
`endif // !`ifdef ENABLE_CHANNEL_SLICING
end // block: DP
endgenerate
// generate the ack lines for data pipelines
generate for(i=1; i<PD; i++) begin: DPA
assign pdan[i] = rst_n ? ~(pda[i]|pd4[i-1]) : 0;
end
endgenerate
 
// generate the input ack, add the AND gate if lookahead pipelines are used
generate
`ifdef ENABLE_CHANNEL_SLICING
for(j=0; j<SCN; j++) begin: SCA
`ifdef ENABLE_LOOKAHEAD
and ACKG (ia[j], pda[PD][j], ian_dly[j]);
delay DLY ( .q(ian_dly[j]), .a(pdan[PD-1][j]));
`else
assign ia[j] = pda[PD][j];
`endif
assign ia4[j] = pd4[PD-1][j];
assign pdan[0][j] = (~oa[j])&rst_n;
assign pd4an[0][j] = pdan[0][j];
end
`else
`ifdef ENABLE_LOOKAHEAD
and ACKG (ia, pda[PD], ian_dly);
delay DLY ( .q(ian_dly), .a(pdan[PD-1]));
`else
assign ia = pda[PD];
`endif
assign ia4 = pd4[PD-1];
assign pdan[0] = (~oa)&rst_n;
assign pd4an[0] = pdan[0];
`endif // !`ifdef ENABLE_LOOKAHEAD
endgenerate
// name change
assign pd0[PD] = i0;
assign pd1[PD] = i1;
assign pd2[PD] = i2;
assign pd3[PD] = i3;
assign pd4[PD] = i4;
assign o0 = pd0[0];
assign o1 = pd1[0];
assign o2 = pd2[0];
assign o3 = pd3[0];
assign o4 = pd4[0];
 
endmodule // outp_buf
 
clos_opt/clos_opt/src/output_buf.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.