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Rev 23 → Rev 28

/sdm/src/input_buf.v
169,12 → 169,12
);
 
// keep the routing decision until the tail flit is received by all sub-channels
c2p C_RTD0 ( .a1(raw_dec[0]), .a0((~frame_end)&rst_n), .q(dec_reg[0]));
c2p C_RTD1 ( .a1(raw_dec[1]), .a0((~frame_end)&rst_n), .q(dec_reg[1]));
c2p C_RT_XEQ (.a1(raw_dec[2]), .a0((~frame_end)&rst_n), .q(x_equal) );
c2p C_RTD2 ( .a1(raw_dec[3]), .a0(x_equal), .q(dec_reg[2]));
c2p C_RTD3 ( .a1(raw_dec[4]), .a0(x_equal), .q(dec_reg[3]));
c2p C_RTD4 ( .a1(raw_dec[5]), .a0(x_equal), .q(dec_reg[4]));
c2p C_RTD0 ( .b(raw_dec[0]), .a((~frame_end)&rst_n), .q(dec_reg[0]));
c2p C_RTD1 ( .b(raw_dec[1]), .a((~frame_end)&rst_n), .q(dec_reg[1]));
c2p C_RT_XEQ (.b(raw_dec[2]), .a((~frame_end)&rst_n), .q(x_equal) );
c2p C_RTD2 ( .b(raw_dec[3]), .a(x_equal), .q(dec_reg[2]));
c2p C_RTD3 ( .b(raw_dec[4]), .a(x_equal), .q(dec_reg[3]));
c2p C_RTD4 ( .b(raw_dec[5]), .a(x_equal), .q(dec_reg[4]));
 
// generate the arbiter request signals
assign arb_r =
/sdm/src/clos_sch.v
21,7 → 21,7
10/06/2010 Change to use PIM structure <wsong83@gmail.com>
23/08/2010 Fix the non-QDI request withdraw process <wsong83@gmail.com>
23/09/2010 Modified for Clos SDM router <wsong83@gmail.com>
25/05/2011 Clean up for opensource. <wsong83@gmail.com>
27/05/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
88,7 → 88,7
.ira ( cmra[0] ),
.oreq ( sr ),
.ora ( sra ),
.gnt ( imc[0] )
.cfg ( imc[0] )
);
 
// the C-element to force the request withdrawal sequence
113,7 → 113,7
.ira ( cmra[1] ),
.oreq ( wr ),
.ora ( wra ),
.gnt ( imc[1] )
.cfg ( imc[1] )
);
 
generate for(i=0; i<N; i++) begin: WA
137,7 → 137,7
.ira ( cmra[2] ),
.oreq ( nr ),
.ora ( nra ),
.gnt ( imc[2] )
.cfg ( imc[2] )
);
 
generate for(i=0; i<N; i++) begin: NA
161,7 → 161,7
.ira ( cmra[3] ),
.oreq ( er ),
.ora ( era ),
.gnt ( imc[3] )
.cfg ( imc[3] )
);
 
generate for(i=0; i<N; i++) begin: EA
185,7 → 185,7
.ira ( cmra[4] ),
.oreq ( lr ),
.ora ( lra ),
.gnt ( imc[4] )
.cfg ( imc[4] )
);
 
generate for(i=0; i<N; i++) begin: LA
/sdm/src/subc_ctl.v
52,12 → 52,12
wire acken; // active low ack enable
`ifdef ENABLE_LOOKAHEAD
c2n CD (.q(acko), .a0(ai2cb), .a1(ack)); // the C2N gate to avoid early withdrawal
c2n CD (.q(acko), .a(ai2cb), .b(ack)); // the C2N gate to avoid early withdrawal
`else
assign acko = ai2cb;
`endif
c2p CEN (.a1(eof), .a0(acko), .q(fend));
c2p CEN (.b(eof), .a(acko), .q(fend));
c2 C (.a0(rt_ra), .a1(fend), .q(csc));
nand U1 ( acken, rt_ra, ~csc);
nor U2 ( rt_rst, fend, ~csc);
/sdm/src/im_alloc.v
22,7 → 22,7
05/11/2009 Speed up the arbiter. <wsong83@gmail.com>
10/06/2010 [Major] change to use PIM structure. <wsong83@gmail.com>
23/08/2010 Fix the non-QDI request withdraw process. <wsong83@gmail.com>
25/05/2011 Clean up for opensource. <wsong83@gmail.com>
27/05/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
86,9 → 86,9
for(i=0; i<VCN; i++) begin: IPC
for(j=0; j<CMN; j++) begin: OPC
`ifdef ENABLE_CRRD
IPr[i][j] = |IMr[i];
assign IPr[i][j] = |IMr[i];
`else
IPr[i][j] = |IPrm[i][j];
assign IPr[i][j] = |IPrm[i][j];
for(k=0; k<SN; k++) begin: DIRC
c2p IPRen (.q(IPrm[i][j][k]), .a0(IMr[i][k]), .a1(~CMs[j][k]));
end
118,6 → 118,9
assign IPr[i] = |IMr[i];
end
endgenerate
assign OPrst_n[0] = rst_n;
`endif // !`ifndef ENABLE_MRMA
endmodule // im_alloc
/sdm/src/router.v
403,7 → 403,7
);
`else // Crossbar based SDM
 
crossbar #(.VCN(VCN), .VCW(DW))
dcb_xy #(.VCN(VCN), .VCW(DW))
CB (
.so0 ( c2s0 ),
.so1 ( c2s1 ),
/sdm/src/sdm_sch.v
18,7 → 18,7
History:
28/09/2009 Initial version. <wsong83@gmail.com>
25/05/2011 Clean up for opensource. <wsong83@gmail.com>
27/05/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
29,7 → 29,7
// Outputs
sack, wack, nack, eack, lack, scfg, ncfg, wcfg, ecfg, lcfg,
// Inputs
sreq, nreq, lreq, wreq, ereq
sreq, nreq, lreq, wreq, ereq, rst_n
);
parameter VCN = 2; // the number of virtual circuits per port
229,13 → 229,15
generate
for(i=0; i<VCN; i++) begin: OPC
delay DLY ( .q(OPrst_n[i+1]), .a(OPrst_n[i])); // dont touch
assign SOPrdy[i] = (~SOPblk[i])&SOPrst_n[i+1];
assign WOPrdy[i] = (~WOPblk[i])&WOPrst_n[i+1];
assign NOPrdy[i] = (~NOPblk[i])&NOPrst_n[i+1];
assign EOPrdy[i] = (~EOPblk[i])&EOPrst_n[i+1];
assign LOPrdy[i] = (~LOPblk[i])&LOPrst_n[i+1];
assign SOPrdy[i] = (~SOPblk[i])&OPrst_n[i+1];
assign WOPrdy[i] = (~WOPblk[i])&OPrst_n[i+1];
assign NOPrdy[i] = (~NOPblk[i])&OPrst_n[i+1];
assign EOPrdy[i] = (~EOPblk[i])&OPrst_n[i+1];
assign LOPrdy[i] = (~LOPblk[i])&OPrst_n[i+1];
end
endgenerate
 
assign OPrst_n[0] = rst_n;
`endif // !`ifndef ENABLE_MRMA
/sdm/syn/script/source.tcl
0,0 → 1,37
# Asynchronous SDM NoC
# (C)2011 Wei Song
# Advanced Processor Technologies Group
# Computer Science, the Univ. of Manchester, UK
#
# Authors:
# Wei Song wsong83@gmail.com
#
# License: LGPL 3.0 or later
#
# Source files for the wormhole/SDM routers
#
# History:
# 26/05/2011 Initial version. <wsong83@gmail.com>
 
# the common verilog source files between VC and SDM
analyze -format verilog ../../common/src/cell_lib.v
analyze -format verilog ../../common/src/ctree.v
analyze -format sverilog ../../common/src/dcb.v
analyze -format sverilog ../../common/src/dcb_xy.v
analyze -format sverilog ../../common/src/dclos.v
analyze -format sverilog ../../common/src/mnma.v
analyze -format sverilog ../../common/src/mrma.v
analyze -format verilog ../../common/src/mutex_arb.v
analyze -format sverilog ../../common/src/pipe4.v
analyze -format sverilog ../../common/src/rcb.v
analyze -format verilog ../../common/src/tree_arb.v
 
# the private code of wormhole/SDM routers
analyze -format sverilog ../src/clos_sch.v
analyze -format sverilog ../src/cm_alloc.v
analyze -format sverilog ../src/im_alloc.v
analyze -format sverilog ../src/input_buf.v
analyze -format sverilog ../src/output_buf.v
analyze -format sverilog ../src/router.v
analyze -format sverilog ../src/sdm_sch.v
analyze -format sverilog ../src/subc_ctl.v
/sdm/syn/script/constraint.tcl
0,0 → 1,84
# Asynchronous SDM NoC
# (C)2011 Wei Song
# Advanced Processor Technologies Group
# Computer Science, the Univ. of Manchester, UK
#
# Authors:
# Wei Song wsong83@gmail.com
#
# License: LGPL 3.0 or later
#
# Constraints for wormhole/SDM routers
#
# History:
# 26/05/2011 Initial version. <wsong83@gmail.com>
 
# loading the baic cell constraints
source ../../common/script/cell_constraint.tcl
 
# ensure the basic blocks are not ungrouped for better debugging capability
set_ungroup [get_references -hierarchical inp_buf*] false
set_ungroup [get_references -hierarchical outp_buf*] false
set_ungroup CB false
set_ungroup ALLOC false
 
 
######### break the timing loops in the design ##############
 
# route decision address bus
set_disable_timing [get_cells -hierarchical Px_* ] -from A -to Z
set_disable_timing [get_cells -hierarchical Px_* ] -from B -to Z
set_disable_timing [get_cells -hierarchical Py_* ] -from A -to Z
set_disable_timing [get_cells -hierarchical Py_* ] -from B -to Z
 
# input buffer control input
foreach_in_collection celln [get_references -hierarchical inp_buf_*] {
set_disable_timing [get_object_name $celln]/C_RTD0/U2 -from B -to Z
set_disable_timing [get_object_name $celln]/C_RTD1/U2 -from B -to Z
set_disable_timing [get_object_name $celln]/C_RT_XEQ/U2 -from B -to Z
}
 
# the delay cell in the lookahead pipeline
# It is not a problem to get errors here if ENABLE_LOOKAHEAD is not defined.
foreach_in_collection celln [get_references -hierarchical outp_buf_*] {
set_disable_timing [get_object_name $celln]/DLY/U -from A -to Z
}
 
# set some timing path ending points
set DPD []
set DPA []
foreach_in_collection celln [get_references -hierarchical dc2_*] {
append_to_collection DPD [ get_pins [get_object_name $celln]/U1/B]
append_to_collection DPD [ get_pins [get_object_name $celln]/U2/A]
append_to_collection DPA [ get_pins [get_object_name $celln]/U1/A]
append_to_collection DPA [ get_pins [get_object_name $celln]/U3/A]
}
 
set IODI [filter [get_ports *i*] "@port_direction == in"]
set IODO [filter [get_ports *o*] "@port_direction == out"]
set IOAI [filter [get_ports *i*] "@port_direction == out"]
set IOAO [filter [get_ports *o*] "@port_direction == in"]
 
# set the timing constraints for data paths and ack paths
# For better speed performance, please tune these delay and factors according different cell libraries
set DATA_dly 5
set ACK_dly 8
 
set_max_delay [expr ${DATA_dly} * 1.00] -from ${DPA} -to ${DPD} -group G_DATA
set_max_delay [expr ${ACK_dly} * 1.00] -from ${DPA} -to ${DPA} -group G_ACK
set_max_delay [expr ${DATA_dly} * 0.30] -from ${IODI} -to ${DPD} -group G_DATA
set_max_delay [expr ${ACK_dly} * 0.75] -from ${DPA} -to ${IOAI} -group G_ACK
set_max_delay [expr ${DATA_dly} * 0.70] -from ${DPA} -to ${IODO} -group G_DATA
set_max_delay [expr ${ACK_dly} * 0.25] -from ${IOAO} -to ${DPA} -group G_ACK
 
group_path -weight 1.5 -critical_range 40 -name G_DATA
group_path -weight 1.5 -critical_range 40 -name G_ACK
 
set_critical_range 20 ${current_design}
 
set_max_leakage_power 0.0
set_max_dynamic_power 0.0
set_max_area 0
 
# timing path disabled by user constraints
suppress_message TIM-175
/sdm/syn/script/cleanup.tcl
0,0 → 1,4
rm *
rm -fr work
rm -fr file
 
/sdm/syn/script/compile.tcl
0,0 → 1,67
# Asynchronous SDM NoC
# (C)2011 Wei Song
# Advanced Processor Technologies Group
# Computer Science, the Univ. of Manchester, UK
#
# Authors:
# Wei Song wsong83@gmail.com
#
# License: LGPL 3.0 or later
#
# Synthesis script
# currently using the Nangate 45nm cell lib.
#
# History:
# 26/05/2009 Initial version. <wsong83@gmail.com>
 
set rm_top router
set rm_para "VCN=>1, DW=>8, IPD=>1, OPD=>1"
 
# working directory
if {[file exists work ] && [file isdirectory work ]} {
file delete -force work
}
file mkdir work
define_design_lib work -path work
 
if {![file exists file ]} {
file mkdir file
}
 
# set the technology libraries
source ../../common/script/tech.tcl
 
# read in source codes
source script/source.tcl
 
# elaborate the design
elaborate ${rm_top} -parameters ${rm_para}
 
link
 
check_design
 
# read in constraints
echo "It will be many errors in this step. Normally they are fine. For further info. please read the comments in the constraint scripts."
source script/constraint.tcl
 
link
 
#report loops
report_timing -loops -max_paths 2
 
compile -boundary_optimization
 
 
define_name_rules verilog -allowed "A-Za-z0-9_" -first_restricted "\\"
change_name -rules verilog -hierarchy
 
write -format verilog -hierarchy -out file/${current_design}_syn.v $current_design
write_sdf -significant_digits 5 file/${current_design}.sdf
write_sdc file/${current_design}.sdc
 
report_constraints -verbose
 
report_constraints
report_area
exit
/sdm/define.v
11,14 → 11,25
Router configuration header file for SDM routers.
Possible configuration combinations:
* Wormhole (set VCN to 1)
ENABLE_EOF [ENABLE_CHANNEL_SLICING] [ENABLE_LOOKAHEAD]
* SDM (set VCN > 1 without define ENABLE_CLOS)
ENABLE_EOF [ENABLE_CHANNEL_SLICING] [ENABLE_LOOKAHEAD] [ENABLE_MRMA]
* SDM-Clos (set VCN > 1 and define ENABLE_CLOS)
ENABLE_EOF ENABLE_CLOS [ENABLE_CHANNEL_SLICING] [ENABLE_LOOKAHEAD] [ENABLE_CRRD [ENABLE_MRMA]]
The combinations not presented above are illegal, which may produce unexpected failures.
History:
20/09/2009 Initial version. <wsong83@gmail.com>
23/05/2011 Clean up for opensource. <wsong83@gmail.com>
26/05/2011 Add ENABLE_MRMA and configuration explanations. <wsong83@gmail.com>
*/
 
// if VCN > 1, set ENABLE_CLOS to use the 2-stage Clos switch for less switching area
`define ENABLE_CLOS
// `define ENABLE_CLOS
 
// Using the asynchronous virsion of the Concurrent round-robine dispatching
// algorithm for the 2-stage Clos can save some area but introduce a 5%
31,10 → 42,10
// `define ENABLE_MRMA
 
// set to enable channel slicing for fast data paths
`define ENABLE_CHANNEL_SLICING
// `define ENABLE_CHANNEL_SLICING
 
// set to use the early acknowledge of lokkahead pipelines in the critical cycle
`define ENABLE_LOOKAHEAD
// `define ENABLE_LOOKAHEAD
 
// always set in wormhole and SDM routers to enable the eof bit in data pipeline stages
`define ENABLE_EOF
/common/script/cell_constraint.tcl
13,10 → 13,11
#
# History:
# 03/07/2009 Initial version. <wsong83@gmail.com>
# 21/05/2011 Change to the Nangate cell library. <wsong83@gmail.com>
# 27/05/2011 Change to the Nangate cell library. <wsong83@gmail.com>
 
set_dont_touch mutex
set_dont_touch mutex2
set_dont_touch delay
# It is not a problem if there is no delay cells in the design.
 
uniquify -force
 
38,14 → 39,16
foreach_in_collection celln [get_references -hierarchical c2n_*] {
set_disable_timing [get_object_name $celln]/U1 -from B -to Z
}
# It is not a problem if there is no c2n cells in the design.
 
# c2p gates
foreach_in_collection celln [get_references -hierarchical c2p_*] {
set_disable_timing [get_object_name $celln]/U1 -from B -to O
set_disable_timing [get_object_name $celln]/U1 -from B -to Z
}
# It is not a problem if there is no c2p cells in the design.
 
# mutex gates
foreach_in_collection celln [get_references -hierarchical mutex_*] {
foreach_in_collection celln [get_references -hierarchical mutex2_*] {
set_disable_timing [get_object_name $celln]/U1 -from A2 -to ZN
set_disable_timing [get_object_name $celln]/U4 -from A2 -to ZN
set_dont_touch [get_object_name $celln]/U2
57,6 → 60,7
set_disable_timing [get_object_name $celln]/U2 -from B -to Z
set_disable_timing [get_object_name $celln]/U3 -from B -to Z
}
# It is not a problem if MRMA is not used in the design.
 
# tarb
foreach_in_collection celln [get_references -hierarchical tarb_*] {
63,9 → 67,34
set_disable_timing [get_object_name $celln]/U2 -from A -to Z
set_disable_timing [get_object_name $celln]/U3 -from A -to Z
}
# It is not a problem if tree arbiter is not used in the design.
 
# cr_blk
foreach_in_collection celln [get_references -hierarchical cr_blk_*] {
set_disable_timing [get_object_name $celln]/XG/U1 -from C -to Z
}
# It is not a problem if MRMA is not used in the design.
 
# mrma multi-resource match arbiter
foreach_in_collection celln [get_references -hierarchical mrma_*] {
set_disable_timing [get_object_name $celln]/*.AND_*G* -from B -to Z
set_disable_timing [get_object_name $celln]/*.AND_RG* -from A -to Z
}
# It is not a problem if MRMA is not used in the design.
 
# dcb data crossbar
foreach_in_collection celln [get_references -hierarchical dcb_*] {
set_disable_timing [get_object_name $celln]/*.A* -from B -to Z
}
 
# dcb data crossbar
foreach_in_collection celln [get_references -hierarchical rcb_*] {
set_disable_timing [get_object_name $celln]/*.A* -from B -to Z
}
#It is not a problem if there is no rcb modules in the design.
 
# mnmr m-n match allocator
foreach_in_collection celln [get_references -hierarchical mnma_*] {
set_disable_timing [get_object_name $celln]/*.AND_OPRen* -from B -to Z
}
#It is not a problem if MNMA is not used in the design.
/common/script/tech.tcl
19,7 → 19,7
 
set rm_library "Nangate_typ.db"
 
set search_path [concat ${search_path} "${rm_lib_dirs}/"]
set search_path [concat ${search_path} "${rm_lib_dirs}/" ".."]
 
set synthetic_library dw_foundation.sldb
set link_library [list *]
/common/src/mrma.v
19,7 → 19,7
History:
05/09/2009 Initial version. <wsong83@gmail.com>
05/11/2009 Speed up the arbiter. <wsong83@gmail.com>
24/05/2011 Clean up for opensource. <wsong83@gmail.com>
27/05/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
45,9 → 45,9
 
wire [M-1:0][N-1:0] hs; // match results
wire [M-1:0][N-1:0] blk; // blockage
wire [N-1:0][M-1:0] cblk; // shuffled blockage
wire [M-1:0] rblk; // resource blockage
wire [N-1:0] cblk; // client blockage
wire [N-1:0][M-1:0] sblk; // shuffled blockage
wire [M-1:0] rbi; // resource blockage
wire [N-1:0] cbi; // client blockage
wire [N-1:0] cg, cm; // client requests
wire [M-1:0] rg, rm; // resource requests
82,13 → 82,13
);
// shuffle the blockage
assign cblk[j][i] = blk[i][j];
assign sblk[j][i] = blk[i][j];
 
// shuffle the configuration
assign scfg[j][i] = cfg[i][j];
// store the match results
c2p C (.q(cfg[i][j]), .a0(c[j]), .a1(hs[i][j]));
c2p C (.q(cfg[i][j]), .a(c[j]), .b(hs[i][j]));
end // block: Clm
end // block: Row
97,15 → 97,16
for(i=0; i<M; i++) begin: RB
assign rbi[i] = (|blk[i]) & rst_n;
and AND_RG (rm[i], r[i], ~ra[i], rst_n);
ra[i] = |cfg[i];
assign ra[i] = |cfg[i];
end
 
// combine the column blockage and generate input requests
for(j=0; j<N; j++) begin: CB
assign cbi[j] = (|cblk[j]) & rst_n;
assign cbi[j] = (|sblk[j]) & rst_n;
and AND_CG (cm[j], c[j], ~ca[j], rst_n);
assign ca[j] = |scfg[j];
end
endgenerate
endmodule // im_arb
endmodule // mrma
 
/common/src/pipe4.v
15,7 → 15,7
History:
05/05/2009 Initial version. <wsong83@gmail.com>
17/04/2011 Replace the common ack generation. <wsong83@gmail.com>
23/05/2011 Clean up for opensource. <wsong83@gmail.com>
26/05/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
41,12 → 41,12
output ia; // output ack
 
`ifdef ENABLE_EOF
input o4; // the eof bit
output i4;
output o4; // the eof bit
input i4;
`endif
// internal signals
wire [2*SCN-2:0] tack;
wire [SCN-1:0] tack;
// generate the ack line
genvar i;
61,7 → 61,7
 
// the eof bit
`ifdef ENABLE_EOF
dc2 DD_DC4 (.d(i4), .a(oa[SCN-1]), .q(o4));
dc2 DD_DC4 (.d(i4), .a(oa), .q(o4));
`endif
 
// generate the input ack
/common/src/tree_arb.v
46,7 → 46,7
end
else if(MR == 2) // special case: only two input
begin: MA_2
mutex ME0 (
mutex2 ME0 (
.a ( req[0] ),
.b ( req[1] ),
.qa ( gnt[0] ),
56,7 → 56,7
else
begin: MA_N
 
mutex ME0 (
mutex2 ME0 (
.a ( mreq[0] ),
.b ( mreq[1] ),
.qa ( rgnt[0] ),
/common/src/cell_lib.v
79,7 → 79,7
endmodule
 
// 2-input MUTEX cell, Nangate
module mutex ( a, b, qa, qb ); // !!! dont touch !!!
module mutex2 ( a, b, qa, qb ); // !!! dont touch !!!
 
input a, b; // request inputs
output qa, qb; // grant outputs
120,7 → 120,7
wire n1, n2; // internal wires
wire [1:0] mgnt; // outputs of the MUTEX
 
mutex ME ( .a(req[0]), .b(req[1]), .qa(mgnt[0]), .qb(mgnt[1]) );
mutex2 ME ( .a(req[0]), .b(req[1]), .qa(mgnt[0]), .qb(mgnt[1]) );
c2n C0 ( .a(ntgnt), .b(n2), .q(ngnt[0]) );
c2n C1 ( .a(ntgnt), .b(n1), .q(ngnt[1]) );
nand U1 (treq, n1, n2);
/common/src/mutex_arb.v
37,7 → 37,7
generate
for(i=0; i<wd; i=i+1) begin:lv
for(j=i+1; j<wd; j=j+1) begin:b
mutex ME ( .a(arb_w[i][j-1]), .b(arb_w[j][i]), .qa(arb_w[i][j]), .qb(arb_w[j][i+1]));
mutex2 ME ( .a(arb_w[i][j-1]), .b(arb_w[j][i]), .qa(arb_w[i][j]), .qb(arb_w[j][i+1]));
end
assign arb_w[i][0] = req[i];
assign gnt[i] = arb_w[i][wd-1];
/common/src/rcb.v
15,7 → 15,7
History:
10/12/2009 Initial version. <wsong83@gmail.com>
23/05/2011 Use SystemVerilog for wire declaration. <wsong83@gmail.com>
23/05/2011 Clean up for opensource. <wsong83@gmail.com>
27/05/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
33,11 → 33,11
input [NN-1:0][DW-1:0] ireq; // input requests
output [NN-1:0] ira; // ack for input requests
output [MN-1:0][DW-1:0] oreq; // output requests
input [DW-1:0] ora; // ack for output requests
input [MN-1:0] ora; // ack for output requests
input [MN-1:0][NN-1:0] cfg; // the crossbar configuration
wire [MN-1:0][DW-1:0][NN-1-1:0] m; // the internal wires for requests
wire [NN-1:0][MN-1:0] ma; // the internal wires for acks
wire [MN-1:0][DW-1:0][NN-1:0] m; // the internal wires for requests
wire [NN-1:0][MN-1:0] ma; // the internal wires for acks
// generate variable
genvar i, j, k;
45,8 → 45,8
// request matrix
generate
for (i=0; i<MN; i++) begin: EN
for (j=0; j<DW; j=j+1) begin: SC
for (k=0; k<NN; k=k+1) begin: IP
for (j=0; j<DW; j++) begin: SC
for (k=0; k<NN; k++) begin: IP
and AC (m[i][j][k], ireq[k][j], cfg[i][k]);
end
58,8 → 58,8
 
// ack matrix
generate
for (k=0; k<NN; k=k+1) begin: ENA
for (i=0; i<MN; i=i+1) begin: OP
for (k=0; k<NN; k++) begin: ENA
for (i=0; i<MN; i++) begin: OP
and AC (ma[k][i], ora[i], cfg[i][k]);
end
/common/src/mnma.v
27,7 → 27,7
 
module mnma(/*AUTOARG*/
// Outputs
cfg,
ra, cfg,
// Inputs
r
);
35,6 → 35,7
parameter M = 2; // number of resources
 
input [N-1:0][M-1:0] r; // input requests
output [N-1:0] ra; // ack to input requests
output [M-1:0][N-1:0] cfg; // configuration to the crssbar
 
wire [M-1:0][N-1:0] OPr;
66,6 → 67,9
.req ( IPr[i] ),
.gnt ( IPg[i] )
);
 
// the input ack
assign ra[i] = |IPg[i];
end
endgenerate
 
/.
. Property changes : Added: svn:mergeinfo ## -0,0 +0,1 ## Merged /async_sdm_noc/branches/init:r24-27

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