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Rev 37 → Rev 47

/sdm/tb/ni.h
15,7 → 15,7
20/08/2008 Initial version. <wsong83@gmail.com>
30/09/2010 Use template style packet definition. <wsong83@gmail.com>
16/10/2010 Support SDM. <wsong83@gmail.com>
30/05/2011 CLean up for opensource. <wsong83@gmail.com>
30/05/2011 Clean up for opensource. <wsong83@gmail.com>
 
*/
 
/sdm/src/input_buf.v
24,7 → 24,8
05/05/2009 Initial version. <wsong83@gmail.com>
20/09/2010 Supporting channel slicing and SDM using macro difinitions. <wsong83@gmail.com>
24/05/2011 Clean up for opensource. <wsong83@gmail.com>
01/06/2011 Use the comp4 common comparator rather than the chain_comparator defined in this module. <wsong83@gmail.com>
*/
 
// the router structure definitions
250,10 → 251,10
wire [2:0] x_cmp [1:0];
wire [2:0] y_cmp [1:0];
 
chain_comparator X0 ( .a(pipe_xd[3:0]), .b(addrx[3:0]), .q(x_cmp[0]));
chain_comparator X1 ( .a(pipe_xd[7:4]), .b(addrx[7:4]), .q(x_cmp[1]));
chain_comparator Y0 ( .a(pipe_yd[3:0]), .b(addry[3:0]), .q(y_cmp[0]));
chain_comparator Y1 ( .a(pipe_yd[7:4]), .b(addry[7:4]), .q(y_cmp[1]));
comp4 X0 ( .a(pipe_xd[3:0]), .b(addrx[3:0]), .q(x_cmp[0]));
comp4 X1 ( .a(pipe_xd[7:4]), .b(addrx[7:4]), .q(x_cmp[1]));
comp4 Y0 ( .a(pipe_yd[3:0]), .b(addry[3:0]), .q(y_cmp[0]));
comp4 Y1 ( .a(pipe_yd[7:4]), .b(addry[7:4]), .q(y_cmp[1]));
 
assign decision[0] = x_cmp[1][0] | (x_cmp[1][2]&x_cmp[0][0]); // frame x > addr x
assign decision[1] = x_cmp[1][1] | (x_cmp[1][2]&x_cmp[0][1]); // frame x < addr x
263,26 → 264,3
assign decision[5] = y_cmp[1][2] & y_cmp[0][2]; // frame y = addr y
 
endmodule // routing_decision
 
 
// the 1-of-4 comparator
module chain_comparator (
a
,b
,q
);
 
input [3:0] a;
input [3:0] b;
output [2:0] q;
 
// a > b
assign q[0] = (a[3]&(|b[2:0])) | (a[2]&(|b[1:0])) | (a[1]&(|b[0:0]));
 
// a < b
assign q[1] = (a[2]&(|b[3:3])) | (a[1]&(|b[3:2])) | (a[0]&(|b[3:1]));
 
// a = b
assign q[2] = (a[3]&b[3]) | (a[2]&b[2]) | (a[1]&b[1]) | (a[0]&b[0]);
 
endmodule // chain_comparator
/sdm/syn/script/source.tcl
12,6 → 12,7
#
# History:
# 26/05/2011 Initial version. <wsong83@gmail.com>
# 02/06/2011 Use separated comp4 file. <wsong83@gmail.com>
 
# the common verilog source files between VC and SDM
analyze -format verilog ../../common/src/cell_lib.v
25,6 → 26,7
analyze -format sverilog ../../common/src/pipe4.v
analyze -format sverilog ../../common/src/rcb.v
analyze -format verilog ../../common/src/tree_arb.v
analyze -format verilog ../../common/src/comp4.v
 
# the private code of wormhole/SDM routers
analyze -format sverilog ../src/clos_sch.v
/common/src/pipen.v
0,0 → 1,43
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
A single 4-phase 1-of-n pipeline stage.
History:
05/05/2009 Initial version. <wsong83@gmail.com>
01/06/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
module pipen(/*AUTOARG*/
// Outputs
d_in_a, d_out,
// Inputs
d_in, d_out_a
);
 
parameter DW = 4; // the wire count, the "n" of the 1-of-n code
input [DW-1:0] d_in;
output d_in_a;
output [DW-1:0] d_out;
input d_out_a;
 
genvar i;
// the data pipe stage
generate for (i=0; i<DW; i=i+1) begin:DD
dc2 DC (.d(d_in[i]), .a(d_out_a), .q(d_out[i]));
end endgenerate
 
assign d_in_a = |d_out;
 
endmodule // pipen
/common/src/comp4.v
0,0 → 1,39
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
1-of-4 data comparator
History:
11/05/2010 Initial version. <wsong83@gmail.com>
01/06/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
module comp4 (/*AUTOARG*/
// Outputs
q,
// Inputs
a, b
);
 
input [3:0] a, b; // the data inputs to be compared
output [2:0] q; // the comparison result
 
// a > b
assign q[0] = (a[3]&(|b[2:0])) | (a[2]&(|b[1:0])) | (a[1]&(|b[0:0]));
 
// a < b
assign q[1] = (a[2]&(|b[3:3])) | (a[1]&(|b[3:2])) | (a[0]&(|b[3:1]));
 
// a = b
assign q[2] = (a[3]&b[3]) | (a[2]&b[2]) | (a[1]&b[1]) | (a[0]&b[0]);
 
endmodule // comp4
/vc/define.h
0,0 → 1,51
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
The define file for the SystemC test modules
History:
05/06/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
#ifndef NOC_DEF_H_
#define NOC_DEF_H_
 
#define SC_INCLUDE_DYNAMIC_PROCESSES
#include "sim_ana.h"
#include "pdu_def.h"
 
// channel bandwidth
const unsigned int ChBW = 1; // the data width of a single virtual circuit in unit of bytes
const unsigned int SubChN = 2; // the number of virtual circuits or VCs per direction
const unsigned int FSIZE_MAX = 512; // the longest frame has 512 bytes of data
 
const unsigned int DIMX = 4; // the X size of the mesh network
const unsigned int DIMY = 4; // the Y size of the mesh network
const unsigned int FLEN = 64; // the payload size of a frame in unit of bytes
 
const unsigned int BufDepth = 2; // the depth of the input buffer (only useful in VC routers to determine the inital tokens in output ports)
 
const double FFreq = 0.1; // Node injection rate, in unit of MFlit/second, 0 means the maximal inject rate
 
const double Record_Period = 1e3 * 1e3; // the interval of recording the average performance to log files, in unit of ps
const double Warm_UP = 0e4 * 1e3; // the warm up time of performance analysis, in unit of ps
const double SIM_TIME = 1e3 * 1e3; // the overall simulation time of the netowrk, in unit of ns
 
extern sim_ana * ANA; // declaration of the global simulation analysis module
 
typedef pdu_flit<ChBW> FLIT; // define the template of flit
typedef pdu_frame<ChBW> FRAME; // define the template of frame
 
// Channel Slicing will alter the port format
// #define ENABLE_CHANNEL_CLISING
 
#endif
/vc/tb/netnode.v
0,0 → 1,68
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
The SystemC module of network node including the processing element and the network interface.
Currently the transmission FIFO is 500 frame deep.
History:
27/02/2011 Initial version. <wsong83@gmail.com>
05/06/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
`include "define.v"
 
module NetNode (
doa, doc, do0, do1, do2, do3, doft, dovc, doca,
dia, dic, di0, di1, di2, di3, dift, divc, dica,
rst_n)
//
// The foreign attribute string value must be a SystemC value.
//
(* integer foreign = "SystemC";
*);
//
// Verilog port names must match port names exactly as they appear in the
// sc_module class in SystemC; they must also match in order, mode, and type.
//
parameter DW = 32;
parameter VCN = 1;
parameter FT = 3;
parameter x = 2;
parameter y = 2;
parameter SCN = DW/2;
output doa ;
output [VCN-1:0] doc ;
input [SCN-1:0] do0 ;
input [SCN-1:0] do1 ;
input [SCN-1:0] do2 ;
input [SCN-1:0] do3 ;
input [FT-1:0] doft;
input [VCN-1:0] dovc;
input [VCN-1:0] doca;
input dia;
input [VCN-1:0] dic;
output [SCN-1:0] di0;
output [SCN-1:0] di1;
output [SCN-1:0] di2;
output [SCN-1:0] di3;
output [FT-1:0] dift;
output [VCN-1:0] divc;
output [VCN-1:0] dica;
 
input rst_n;
 
endmodule // NetNode
 
/vc/tb/netnode.h
0,0 → 1,148
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
The SystemC module of network node including the processing element and the network interface.
Currently the transmission FIFO is 500 frame deep.
History:
26/02/2011 Initial version. <wsong83@gmail.com>
04/03/2011 Support VC router. <wsong83@gmail.com>
05/06/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
#ifndef NETNODE_H_
#define NETNODE_H_
 
#include "define.h"
#include <systemc.h>
#include "ni.h"
#include "procelem.h"
#include "rtdriver.h"
 
class NetNode : public sc_module {
public:
RTDriver * LIOD; /* driving and convert I/O to/from router local port */
Network_Adapter * NI; /* network interface */
ProcElem * PE; /* processor element */
 
// signals for router
sc_out< sc_logic > doa ;
sc_out< sc_lv<SubChN > > doc ;
sc_in< sc_lv<ChBW*4 > > do0 ;
sc_in< sc_lv<ChBW*4 > > do1 ;
sc_in< sc_lv<ChBW*4 > > do2 ;
sc_in< sc_lv<ChBW*4 > > do3 ;
sc_in< sc_lv<3> > doft;
sc_in< sc_lv<SubChN > > dovc;
sc_in< sc_lv<SubChN > > doca;
sc_in< sc_logic > dia;
sc_in< sc_lv<SubChN > > dic;
sc_out< sc_lv<ChBW*4 > > di0;
sc_out< sc_lv<ChBW*4 > > di1;
sc_out< sc_lv<ChBW*4 > > di2;
sc_out< sc_lv<ChBW*4 > > di3;
sc_out< sc_lv<3> > dift;
sc_out< sc_lv<SubChN > > divc;
sc_out< sc_lv<SubChN > > dica;
 
sc_in<sc_logic > rst_n; /* global active-low reset */
 
// signals between IOD and NI
sc_fifo<pdu_flit<ChBW> > * NI2P ; /* flit fifo, from NI to IO driver */
sc_fifo<pdu_flit<ChBW> > * P2NI ; /* flit fifo, from IO driver to NI */
sc_signal<bool> CP [SubChN]; /* credit input */
sc_signal<bool> CPa [SubChN]; /* credit ack */
 
// signals between NI and FG/FS
sc_fifo<pdu_frame<ChBW> > * FIQ; /* the frame fifo, from PE to NI */
sc_fifo<pdu_frame<ChBW> > * FOQ; /* the frame fifo, from NI to PE */
sc_signal<bool> brst_n; /* the reset in the SystemC modules */
 
int x, y; /* private local address */
 
SC_CTOR(NetNode)
: doa("doa"), doc("doc"),
do0("do0"), do1("do1"), do2("do2"), do3("do3"),
doft("doft"), dovc("dovc"), doca("doca"),
dia("dia"), dic("dic"),
di0("di0"), di1("di1"), di2("di2"), di3("di3"),
dift("dift"), divc("divc"), dica("dica"),
rst_n("rst_n")
{
// dynamically get the parameters from Verilog test bench
ncsc_get_param("x", x);
ncsc_get_param("y", y);
 
// initialization
LIOD = new RTDriver("LIOD");
NI = new Network_Adapter("NI", x, y);
PE = new ProcElem("PE", x, y);
NI2P = new sc_fifo<pdu_flit<ChBW> >(1);
P2NI = new sc_fifo<pdu_flit<ChBW> >(1);
FIQ = new sc_fifo<pdu_frame<ChBW> >(500);/* currently the fifo from PE is 500 frame deep */
FOQ = new sc_fifo<pdu_frame<ChBW> >(1);
 
// connections
LIOD->NI2P(*NI2P);
LIOD->P2NI(*P2NI);
LIOD->rtid[0](di0);
LIOD->rtod[0](do0);
LIOD->rtid[1](di1);
LIOD->rtod[1](do1);
LIOD->rtid[2](di2);
LIOD->rtod[2](do2);
LIOD->rtid[3](di3);
LIOD->rtod[3](do3);
LIOD->rtift(dift);
LIOD->rtivc(divc);
LIOD->rtia(dia);
LIOD->rtic(dic);
LIOD->rtica(dica);
LIOD->rtoft(doft);
LIOD->rtovc(dovc);
LIOD->rtoa(doa);
LIOD->rtoc(doc);
LIOD->rtoca(doca);
for(unsigned int j=0; j<SubChN; j++) {
LIOD->CP[j](CP[j]);
LIOD->CPa[j](CPa[j]);
}
 
NI->frame_in(*FIQ);
NI->frame_out(*FOQ);
NI->IP(*P2NI);
NI->OP(*NI2P);
for(unsigned int j=0; j<SubChN; j++) {
NI->CP[j](CP[j]);
NI->CPa[j](CPa[j]);
}
PE->rst_n(brst_n);
PE->Fout(*FIQ);
PE->Fin(*FOQ);
 
brst_n.write(false);
 
SC_METHOD(rst_proc);
sensitive << rst_n;
}
 
void rst_proc() {
bool mrst_n;
mrst_n = rst_n.read().is_01() ? rst_n.read().to_bool() : false;
brst_n.write(mrst_n);
}
};
 
 
#endif
/vc/tb/rtdriver.cpp
0,0 → 1,306
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
The port driver between NI and router.
History:
02/05/2010 Initial version. <wsong83@gmail.com>
03/06/2011 Remove the sc_unit datatype to support data width larger than 64. <wsong83@gmail.com>
*/
 
#include "rtdriver.h"
 
RTDriver::RTDriver(sc_module_name mname)
: sc_module(mname),
NI2P("NI2P"),
P2NI("P2NI"),
rtia("rtia"),
rtic("rtic"),
rtica("rtica"),
rtoa("rtoa"),
rtoc("rtoc"),
rtoca("rtoca")
{
SC_METHOD(IPdetect);
sensitive << rtia;
 
SC_METHOD(OPdetect);
sensitive << rtod[0] << rtod[1] << rtod[2] << rtod[3] << rtovc << rtoft;
 
SC_METHOD(Creditdetect);
for(unsigned int i = 0; i<SubChN; i++) {
sensitive << CPa[i];
sensitive << out_cred[i];
}
sensitive << rtic << rtoca;
 
SC_THREAD(send);
SC_THREAD(recv);
 
rtinp_sig = false;
rtoutp_sig = false;
}
void RTDriver::IPdetect() {
sc_logic ack_lv_high, ack_lv_low; // the sc_logic ack
 
ack_lv_high = rtia.read();
ack_lv_low = rtia.read();
 
if(ack_lv_high.is_01() && ack_lv_high.to_bool())
rtinp_sig = true;
if(ack_lv_low.is_01() && (!ack_lv_low.to_bool()))
rtinp_sig = false;
}
 
void RTDriver::OPdetect() {
sc_lv<ChBW*4> data_lv; // the ORed data
sc_logic data_lv_high, data_lv_low;
sc_lv<SubChN> vc_lv; // the local copy of vc number
sc_lv<3> ft_lv; // the local copy of flit type
 
data_lv = rtod[0].read() | rtod[1].read() | rtod[2].read() | rtod[3].read();
vc_lv = rtovc.read();
ft_lv = rtoft.read();
data_lv_high = (sc_logic)(data_lv.and_reduce()) & (sc_logic)(vc_lv.or_reduce()) & (sc_logic)(ft_lv.or_reduce());
data_lv_low = (sc_logic)(data_lv.or_reduce()) | (sc_logic)(vc_lv.or_reduce()) | (sc_logic)(ft_lv.or_reduce());
 
if(data_lv_high.is_01() && data_lv_high.to_bool())
rtoutp_sig = true;
if(data_lv_high.is_01() && (!data_lv_low.to_bool()))
rtoutp_sig = false;
}
 
void RTDriver::Creditdetect() {
sc_lv<SubChN> mic; // the local input credit
sc_lv<SubChN> mica; // the local input credit ack
sc_lv<SubChN> moc; // the local output credit;
sc_lv<SubChN> moca; // the local output credit ack;
mic = rtic.read();
moca = rtoca.read();
 
for(unsigned int i=0; i<SubChN; i++) {
CP[i].write(mic[i].is_01()? mic[i].to_bool():false);
out_cred_ack[i] = moca[i].is_01()? moca[i].to_bool():false;
mica[i] = CPa[i].read();
moc[i] = out_cred[i];
}
 
rtica.write(mica);
rtoc.write(moc);
}
 
void RTDriver::send() {
FLIT mflit; // the local flit buffer
unsigned int i, j; // local loop index
sc_lv<ChBW*4> mdata[4]; // local data copy
sc_lv<SubChN> mvc; // local vcn
sc_lv<3> mft; // local flit type
// initialize the output ports
mdata[0] = 0;
mdata[1] = 0;
mdata[2] = 0;
mdata[3] = 0;
mvc = 0;
mft = 0;
 
 
rtid[0].write(mdata[0]);
rtid[1].write(mdata[1]);
rtid[2].write(mdata[2]);
rtid[3].write(mdata[3]);
rtivc.write(mvc);
rtift.write(mft);
 
while(true) {
mflit = NI2P->read(); // read in the flit
 
// write the flit
if(mflit.ftype == F_HD) {
// the target address
mdata[mflit.addrx&0x3][0] = SC_LOGIC_1;
mdata[(mflit.addrx&0xc)>>2][1] = SC_LOGIC_1;
mdata[mflit.addry&0x3][2] = SC_LOGIC_1;
mdata[(mflit.addry&0xc)>>2][3] = SC_LOGIC_1;
for(i=0,j=4; i<(ChBW-1)*4; i++, j++) {
switch((mflit[i/4] >> ((i%4)*2)) & 0x3) {
case 0: mdata[0][j] = SC_LOGIC_1; break;
case 1: mdata[1][j] = SC_LOGIC_1; break;
case 2: mdata[2][j] = SC_LOGIC_1; break;
case 3: mdata[3][j] = SC_LOGIC_1; break;
}
}
} else {
for(i=0; i<ChBW*4; i++) {
switch((mflit[i/4] >> ((i%4)*2)) & 0x3) {
case 0: mdata[0][i] = SC_LOGIC_1; break;
case 1: mdata[1][i] = SC_LOGIC_1; break;
case 2: mdata[2][i] = SC_LOGIC_1; break;
case 3: mdata[3][i] = SC_LOGIC_1; break;
}
}
}
// flit type
switch(mflit.ftype) {
case F_HD: mft[0] = SC_LOGIC_1; break;
case F_DAT: mft[1] = SC_LOGIC_1; break;
case F_TL: mft[2] = SC_LOGIC_1; break;
default: break;
}
// VC number
mvc[mflit.vcn] = SC_LOGIC_1;
// write to the port
rtid[0].write(mdata[0]);
rtid[1].write(mdata[1]);
rtid[2].write(mdata[2]);
rtid[3].write(mdata[3]);
rtivc.write(mvc);
rtift.write(mft);
 
// wait for the router to capture the data
wait(rtinp_sig.posedge_event());
wait(0.2, SC_NS); // a delay to avoid data override
// clear the data
mdata[0] = 0;
mdata[1] = 0;
mdata[2] = 0;
mdata[3] = 0;
mvc = 0;
mft = 0;
rtid[0].write(mdata[0]);
rtid[1].write(mdata[1]);
rtid[2].write(mdata[2]);
rtid[3].write(mdata[3]);
rtivc.write(mvc);
rtift.write(mft);
// wait for the input port be ready again
wait(rtinp_sig.negedge_event());
wait(0.2, SC_NS); // a delay to avoid data override
}
}
 
void RTDriver::recv() {
FLIT mflit; // the local flit buffer
sc_lv<ChBW*4> mdata[4]; // local data copy
sc_lv<SubChN> mvc; // local vc number
sc_lv<3> mft; // local flit type
sc_logic mack = SC_LOGIC_0; // local copy of ack
sc_lv<4> dd; // the current 1-of-4 data under process
unsigned int i, j; // local loop index
// initialize the ack signal
rtoa.write(mack);
 
while(true) {
// wait for an incoming flit
wait(rtoutp_sig.posedge_event());
if(out_cred_ack[mflit.vcn].read())
wait(out_cred_ack[mflit.vcn].negedge_event());
 
// clear the flit
mflit.clear();
 
// analyse the flit
mdata[0] = rtod[0].read();
mdata[1] = rtod[1].read();
mdata[2] = rtod[2].read();
mdata[3] = rtod[3].read();
mft = rtoft.read();
mvc = rtovc.read();
 
switch(mft.to_uint()) {
case 1: mflit.ftype = F_HD; break;
case 2: mflit.ftype = F_DAT; break;
case 4: mflit.ftype = F_TL; break;
default: mflit.ftype = F_IDLE; // shoudle not happen
}
if(mflit.ftype == F_HD) {
// fetch the address
dd[0] = mdata[0][0]; dd[1] = mdata[1][0]; dd[2] = mdata[2][0]; dd[3] = mdata[3][0];
mflit.addrx |= (c1o42b(dd.to_uint()) << 0);
dd[0] = mdata[0][1]; dd[1] = mdata[1][1]; dd[2] = mdata[2][1]; dd[3] = mdata[3][1];
mflit.addrx |= (c1o42b(dd.to_uint()) << 2);
dd[0] = mdata[0][2]; dd[1] = mdata[1][2]; dd[2] = mdata[2][2]; dd[3] = mdata[3][2];
mflit.addry |= (c1o42b(dd.to_uint()) << 0);
dd[0] = mdata[0][3]; dd[1] = mdata[1][3]; dd[2] = mdata[2][3]; dd[3] = mdata[3][3];
mflit.addry |= (c1o42b(dd.to_uint()) << 2);
// fill in data
for(i=1; i<ChBW; i++) {
for(j=0; j<4; j++) {
dd[0] = mdata[0][i*4+j];
dd[1] = mdata[1][i*4+j];
dd[2] = mdata[2][i*4+j];
dd[3] = mdata[3][i*4+j];
mflit[i-1] |= c1o42b(dd.to_uint()) << j*2;
}
}
} else{
for(i=0; i<ChBW; i++) {
for(j=0; j<4; j++) {
dd[0] = mdata[0][i*4+j];
dd[1] = mdata[1][i*4+j];
dd[2] = mdata[2][i*4+j];
dd[3] = mdata[3][i*4+j];
mflit[i] |= c1o42b(dd.to_uint()) << j*2;
}
}
}
// get the binary vc number
unsigned int fvcn = mvc.to_uint();
while(fvcn != 1) {
mflit.vcn += 1;
fvcn >>= 1;
}
 
// send the flit to the NI
P2NI->write(mflit);
 
// send back a credit
out_cred[mflit.vcn] = true;
wait(0.2, SC_NS); // a delay to avoid data override
rtoa.write(~mack); // notify that data is captured
 
// wait for the data withdrawal
wait(rtoutp_sig.negedge_event());
if(!out_cred_ack[mflit.vcn].read())
wait(out_cred_ack[mflit.vcn].posedge_event());
 
wait(0.2, SC_NS); // a delay to avoid data override
rtoa.write(mack); // notify that data is captured
out_cred[mflit.vcn] = false;
}
}
 
unsigned int RTDriver::c1o42b(unsigned int dd) {
switch(dd) {
case 1: return 0;
case 2: return 1;
case 4: return 2;
case 8: return 3;
default: return 0xff;
}
}
/vc/tb/noc_top.v
0,0 → 1,160
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
The mesh network for simulation.
History:
03/03/2011 Initial version. <wsong83@gmail.com>
04/03/2011 Support VC. <wsong83@gmail.com>
05/06/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
// the router structure definitions
`include "define.v"
 
module noc_top(/*AUTOARG*/
// Inputs
rst_n
);
input rst_n;
 
parameter DW = 32;
parameter VCN = 1;
parameter FT = 3;
parameter DIMX = 8;
parameter DIMY = 8;
parameter SCN = DW/2;
 
wire [DIMX-1:0][DIMY-1:0][3:0][SCN-1:0] di0, di1, di2, di3;
wire [DIMX-1:0][DIMY-1:0][3:0][SCN-1:0] do0, do1, do2, do3;
wire [DIMX-1:0][DIMY-1:0][3:0] dia, doa;
wire [DIMX-1:0][DIMY-1:0][3:0][FT-1:0] dift, doft;
wire [DIMX-1:0][DIMY-1:0][3:0][VCN-1:0] divc, dovc;
wire [DIMX-1:0][DIMY-1:0][3:0][VCN-1:0] dic, doc;
wire [DIMX-1:0][DIMY-1:0][3:0][VCN-1:0] dica, doca;
 
genvar x, y;
 
generate for(x=0; x<DIMX; x++) begin: DX
for(y=0; y<DIMY; y++) begin: DY
node_top #(.DW(DW), .VCN(VCN), .FT(FT), .x(x), .y(y))
NN (
.si0 (di0[x][y][0]), .si1 (di1[x][y][0]), .si2 (di2[x][y][0]), .si3 (di3[x][y][0]), .sia (dia[x][y][0]), .sift(dift[x][y][0]), .sivc(divc[x][y][0]), .sic(dic[x][y][0]), .sica(dica[x][y][0]),
.wi0 (di0[x][y][1]), .wi1 (di1[x][y][1]), .wi2 (di2[x][y][1]), .wi3 (di3[x][y][1]), .wia (dia[x][y][1]), .wift(dift[x][y][1]), .wivc(divc[x][y][1]), .wic(dic[x][y][1]), .wica(dica[x][y][1]),
.ni0 (di0[x][y][2]), .ni1 (di1[x][y][2]), .ni2 (di2[x][y][2]), .ni3 (di3[x][y][2]), .nia (dia[x][y][2]), .nift(dift[x][y][2]), .nivc(divc[x][y][2]), .nic(dic[x][y][2]), .nica(dica[x][y][2]),
.ei0 (di0[x][y][3]), .ei1 (di1[x][y][3]), .ei2 (di2[x][y][3]), .ei3 (di3[x][y][3]), .eia (dia[x][y][3]), .eift(dift[x][y][3]), .eivc(divc[x][y][3]), .eic(dic[x][y][3]), .eica(dica[x][y][3]),
.so0 (do0[x][y][0]), .so1 (do1[x][y][0]), .so2 (do2[x][y][0]), .so3 (do3[x][y][0]), .soa (doa[x][y][0]), .soft(doft[x][y][0]), .sovc(dovc[x][y][0]), .soc(doc[x][y][0]), .soca(doca[x][y][0]),
.wo0 (do0[x][y][1]), .wo1 (do1[x][y][1]), .wo2 (do2[x][y][1]), .wo3 (do3[x][y][1]), .woa (doa[x][y][1]), .woft(doft[x][y][1]), .wovc(dovc[x][y][1]), .woc(doc[x][y][1]), .woca(doca[x][y][1]),
.no0 (do0[x][y][2]), .no1 (do1[x][y][2]), .no2 (do2[x][y][2]), .no3 (do3[x][y][2]), .noa (doa[x][y][2]), .noft(doft[x][y][2]), .novc(dovc[x][y][2]), .noc(doc[x][y][2]), .noca(doca[x][y][2]),
.eo0 (do0[x][y][3]), .eo1 (do1[x][y][3]), .eo2 (do2[x][y][3]), .eo3 (do3[x][y][3]), .eoa (doa[x][y][3]), .eoft(doft[x][y][3]), .eovc(dovc[x][y][3]), .eoc(doc[x][y][3]), .eoca(doca[x][y][3]),
.rst_n(rst_n)
);
// north link
if(x==0) begin
assign di0[x][y][2] = do0[x][y][2];
assign di1[x][y][2] = do1[x][y][2];
assign di2[x][y][2] = do2[x][y][2];
assign di3[x][y][2] = do3[x][y][2];
assign doa[x][y][2] = dia[x][y][2];
assign dift[x][y][2] = doft[x][y][2];
assign divc[x][y][2] = dovc[x][y][2];
assign doc[x][y][2] = dic[x][y][2];
assign dica[x][y][2] = doca[x][y][2];
end else begin
assign di0[x][y][2] = do0[x-1][y][0];
assign di1[x][y][2] = do1[x-1][y][0];
assign di2[x][y][2] = do2[x-1][y][0];
assign di3[x][y][2] = do3[x-1][y][0];
assign doa[x-1][y][0] = dia[x][y][2];
assign dift[x][y][2] = doft[x-1][y][0];
assign divc[x][y][2] = dovc[x-1][y][0];
assign doc[x-1][y][0] = dic[x][y][2];
assign dica[x][y][2] = doca[x-1][y][0];
end
 
// south link
if(x==DIMX-1) begin
assign di0[x][y][0] = do0[x][y][0];
assign di1[x][y][0] = do1[x][y][0];
assign di2[x][y][0] = do2[x][y][0];
assign di3[x][y][0] = do3[x][y][0];
assign doa[x][y][0] = dia[x][y][0];
assign dift[x][y][0] = doft[x][y][0];
assign divc[x][y][0] = dovc[x][y][0];
assign doc[x][y][0] = dic[x][y][0];
assign dica[x][y][0] = doca[x][y][0];
end else begin
assign di0[x][y][0] = do0[x+1][y][2];
assign di1[x][y][0] = do1[x+1][y][2];
assign di2[x][y][0] = do2[x+1][y][2];
assign di3[x][y][0] = do3[x+1][y][2];
assign doa[x+1][y][2] = dia[x][y][0];
assign dift[x][y][0] = doft[x+1][y][2];
assign divc[x][y][0] = dovc[x+1][y][2];
assign doc[x+1][y][2] = dic[x][y][0];
assign dica[x][y][0] = doca[x+1][y][2];
end
 
// west link
if(y==0) begin
assign di0[x][y][1] = do0[x][y][1];
assign di1[x][y][1] = do1[x][y][1];
assign di2[x][y][1] = do2[x][y][1];
assign di3[x][y][1] = do3[x][y][1];
assign doa[x][y][1] = dia[x][y][1];
assign dift[x][y][1] = doft[x][y][1];
assign divc[x][y][1] = dovc[x][y][1];
assign doc[x][y][1] = dic[x][y][1];
assign dica[x][y][1] = doca[x][y][1];
end else begin
assign di0[x][y][1] = do0[x][y-1][3];
assign di1[x][y][1] = do1[x][y-1][3];
assign di2[x][y][1] = do2[x][y-1][3];
assign di3[x][y][1] = do3[x][y-1][3];
assign doa[x][y-1][3] = dia[x][y][1];
assign dift[x][y][1] = doft[x][y-1][3];
assign divc[x][y][1] = dovc[x][y-1][3];
assign doc[x][y-1][3] = dic[x][y][1];
assign dica[x][y][1] = doca[x][y-1][3];
end // else: !if(y==0)
 
// east link
if(y==DIMY-1) begin
assign di0[x][y][3] = do0[x][y][3];
assign di1[x][y][3] = do1[x][y][3];
assign di2[x][y][3] = do2[x][y][3];
assign di3[x][y][3] = do3[x][y][3];
assign doa[x][y][3] = dia[x][y][3];
assign dift[x][y][3] = doft[x][y][3];
assign divc[x][y][3] = dovc[x][y][3];
assign doc[x][y][3] = dic[x][y][3];
assign dica[x][y][3] = doca[x][y][3];
end else begin
assign di0[x][y][3] = do0[x][y+1][1];
assign di1[x][y][3] = do1[x][y+1][1];
assign di2[x][y][3] = do2[x][y+1][1];
assign di3[x][y][3] = do3[x][y+1][1];
assign doa[x][y+1][1] = dia[x][y][3];
assign dift[x][y][3] = doft[x][y+1][1];
assign divc[x][y][3] = dovc[x][y+1][1];
assign doc[x][y+1][1] = dic[x][y][3];
assign dica[x][y][3] = doca[x][y+1][1];
end // else: !if(y==DIMY-1)
 
end // block: DY
end // block: DX
endgenerate
endmodule // noc_top
/vc/tb/ni.cpp
0,0 → 1,147
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
A SystemC network adapter/interface for NoC simulation.
History:
23/12/2008 Initial version. <wsong83@gmail.com>
30/09/2010 Use template style packet definition. <wsong83@gmail.com>
16/10/2010 Support SDM. <wsong83@gmail.com>
05/06/2011 Clean up for opensource. <wsong83@gmail.com>
 
*/
 
#include "ni.h"
 
Network_Adapter::Network_Adapter(
sc_module_name name // module name
,unsigned int x // location x
,unsigned int y // location y
):
sc_module(name),
frame_in("FrmIn"),
frame_out("FrmOut"),
IP("IP"),
OP("OP"),
loc_x(x),
loc_y(y),
oflit(1)
{
sc_spawn_options opt;
 
for(unsigned int i=0; i<SubChN; i++) {
token[i] = BufDepth/2;
}
 
for(unsigned int i=0; i<SubChN; i++) {
sc_spawn(sc_bind(&Network_Adapter::ibuffer_thread, this, i), NULL, &opt);
sc_spawn(sc_bind(&Network_Adapter::obuffer_thread, this, i), NULL, &opt);
sc_spawn(sc_bind(&Network_Adapter::credit_update, this, i), NULL, &opt);
}
SC_THREAD(oport);
SC_THREAD(iport);
 
}
 
Network_Adapter::~Network_Adapter()
{
}
 
// read in the incoming frame
void Network_Adapter::ibuffer_thread(unsigned int ii){
FRAME mframe;
FLIT mflit;
 
while(1){
mframe.clear();
while(1) {
mflit = iflit[ii].read();
mframe << mflit;
if(mflit.ftype == F_TL) break;
}
 
frame_out->write(mframe);
}
}
 
// send out a frame
void Network_Adapter::obuffer_thread(unsigned int ii){
 
FRAME mframe;
FLIT mflit;
 
while(1){
mframe = frame_in->read();
while(1) {
mframe >> mflit;
mflit.vcn = ii;
 
//fetch a token
if(token[ii] == 0)
wait(token_arrive[ii]);
token[ii]--;
 
oflit.write(mflit);
 
if(mflit.ftype == F_TL) break;
}
}
}
 
 
void Network_Adapter::oport() {
FLIT mflit;
while(1) {
mflit = oflit.read();
OP->write(mflit);
}
}
 
void Network_Adapter::iport() {
FLIT mflit;
while(1) {
mflit = IP->read();
iflit[mflit.vcn].write(mflit);
}
}
 
void Network_Adapter::credit_update(unsigned int ii) {
 
CPa[ii].write(false);
while(1) {
if(!CP[ii].read())
wait(CP[ii].posedge_event());
token[ii]++;
token_arrive[ii].notify();
CPa[ii].write(true);
 
wait(CP[ii].negedge_event());
CPa[ii].write(false);
}
}
bool Network_Adapter::check_frame(const FRAME& frame)
{
// TODO: check the integerity, dummy right noe
return true;
}
 
 
 
 
/vc/tb/rtdriver.h
0,0 → 1,72
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
The port driver between NI and router.
History:
27/04/2010 Initial version. <wsong83@gmail.com>
03/06/2011 Remove the sc_unit datatype to support data width larger than 64. <wsong83@gmail.com>
*/
 
#ifndef RT_DRIVER_H_
#define RT_DRIVER_H_
 
#include "define.h"
#include <systemc.h>
#include "pdu_def.h"
 
SC_MODULE(RTDriver) {
 
public:
// port with network interface
sc_port<sc_fifo_in_if<FLIT> > NI2P;
sc_port<sc_fifo_out_if<FLIT> > P2NI;
sc_out<bool> CP [SubChN];
sc_in<bool > CPa [SubChN];
// signals from interface to router
sc_out<sc_lv<ChBW*4> > rtid [4];
sc_out<sc_lv<3> > rtift;
sc_out<sc_lv<SubChN> > rtivc;
sc_in<sc_logic> rtia;
sc_in<sc_lv<SubChN> > rtic;
sc_out<sc_lv<SubChN> > rtica;
 
sc_in<sc_lv<ChBW*4> > rtod [4];
sc_in<sc_lv<3> > rtoft;
sc_in<sc_lv<SubChN> > rtovc;
sc_out<sc_logic> rtoa;
sc_out<sc_lv<SubChN> > rtoc;
sc_in<sc_lv<SubChN> > rtoca;
 
// local variable
sc_signal<bool> out_cred[SubChN]; /* the input credit */
sc_signal<bool> out_cred_ack[SubChN]; /* the input credit ack */
 
SC_HAS_PROCESS(RTDriver);
RTDriver(sc_module_name name);
void IPdetect(); // Method to detect the router input port
void OPdetect(); // Method to detect the router output port
void Creditdetect(); // Method to detect the credit ports
void send(); // thread of sending a flit
void recv(); // thread to recveive a flit
 
sc_signal<bool> rtinp_sig; // fire when the router input port is ready for a new flit
sc_signal<bool> rtoutp_sig; // fire when the router output port has a new flit
unsigned int c1o42b(unsigned int); // convert 1-of-4 to binary
};
 
 
#endif
/vc/tb/noctb.v
0,0 → 1,48
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
Test bench.
History:
03/03/2011 Initial version. <wsong83@gmail.com>
05/06/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
`timescale 1ns/1ps
 
module noctb;
parameter DW = 8; // the data width of a single virtual circuit
parameter VCN = 2; // the number of VCs per direction
parameter DIMX = 4; // the X dimension
parameter DIMY = 4; // the Y dimension
reg rst_n;
noc_top #(.DW(DW), .VCN(VCN), .DIMX(DIMX), .DIMY(DIMY))
NoC (.rst_n(rst_n)); // the mesh network
 
AnaProc ANAM(); // the global performance analyser
initial begin
rst_n = 0;
 
# 133;
 
rst_n = 1;
 
end
 
endmodule // noctb
 
 
 
/vc/tb/rtwrapper.v
0,0 → 1,283
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
The wrapper for the synthesized router.
History:
28/05/2009 Initial version. <wsong83@gmail.com>
05/06/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
// the router structure definitions
`include "define.v"
 
module router_hdl(/*AUTOARG*/
// Outputs
sia, wia, nia, eia, lia, sic, wic, nic, eic, lic, so0, so1, so2,
so3, wo0, wo1, wo2, wo3, no0, no1, no2, no3, eo0, eo1, eo2, eo3,
lo0, lo1, lo2, lo3, soft, woft, noft, eoft, loft, sovc, wovc, novc,
eovc, lovc, soca, woca, noca, eoca, loca,
// Inputs
si0, si1, si2, si3, wi0, wi1, wi2, wi3, ni0, ni1, ni2, ni3, ei0,
ei1, ei2, ei3, li0, li1, li2, li3, sift, wift, nift, eift, lift,
sivc, wivc, nivc, eivc, livc, sica, wica, nica, eica, lica, soa,
woa, noa, eoa, loa, soc, woc, noc, eoc, loc, addrx, addry, rst_n
);
 
parameter VCN = 1; // number of virtual circuits in each direction. When VCN == 1, it is a wormhole router
parameter DW = 32; // the datawidth of a single virtual circuit, the total data width of the router is DW*VCN
parameter FT = 3;// the number of types of flits
parameter SCN = DW/2; // the number of 1-of-4 sub-channel in each virtual circuit
input [SCN-1:0] si0, si1, si2, si3;
input [SCN-1:0] wi0, wi1, wi2, wi3;
input [SCN-1:0] ni0, ni1, ni2, ni3;
input [SCN-1:0] ei0, ei1, ei2, ei3;
input [SCN-1:0] li0, li1, li2, li3;
input [FT-1:0] sift, wift, nift, eift, lift;
input [VCN-1:0] sivc, wivc, nivc, eivc, livc;
output sia, wia, nia, eia, lia;
output [VCN-1:0] sic, wic, nic, eic, lic;
input [VCN-1:0] sica, wica, nica, eica, lica;
output [SCN-1:0] so0, so1, so2, so3;
output [SCN-1:0] wo0, wo1, wo2, wo3;
output [SCN-1:0] no0, no1, no2, no3;
output [SCN-1:0] eo0, eo1, eo2, eo3;
output [SCN-1:0] lo0, lo1, lo2, lo3;
output [FT-1:0] soft, woft, noft, eoft, loft;
output [VCN-1:0] sovc, wovc, novc, eovc, lovc;
input soa, woa, noa, eoa, loa;
input [VCN-1:0] soc, woc, noc, eoc, loc;
output [VCN-1:0] soca, woca, noca, eoca, loca;
 
input [7:0] addrx, addry;
input rst_n;
wire [SCN-1:0] psi0, psi1, psi2, psi3;
wire [SCN-1:0] pwi0, pwi1, pwi2, pwi3;
wire [SCN-1:0] pni0, pni1, pni2, pni3;
wire [SCN-1:0] pei0, pei1, pei2, pei3;
wire [SCN-1:0] pli0, pli1, pli2, pli3;
wire [FT-1:0] psift, pwift, pnift, peift, plift;
wire [VCN-1:0] psivc, pwivc, pnivc, peivc, plivc;
wire psia, pwia, pnia, peia, plia;
wire [VCN-1:0] psic, pwic, pnic, peic, plic;
wire [VCN-1:0] psica, pwica, pnica, peica, plica;
wire [SCN-1:0] pso0, pso1, pso2, pso3;
wire [SCN-1:0] pwo0, pwo1, pwo2, pwo3;
wire [SCN-1:0] pno0, pno1, pno2, pno3;
wire [SCN-1:0] peo0, peo1, peo2, peo3;
wire [SCN-1:0] plo0, plo1, plo2, plo3;
wire [FT-1:0] psoft, pwoft, pnoft, peoft, ploft;
wire [VCN-1:0] psovc, pwovc, pnovc, peovc, plovc;
wire psoa, pwoa, pnoa, peoa, ploa;
wire [VCN-1:0] psoc, pwoc, pnoc, peoc, ploc;
wire [VCN-1:0] psoca, pwoca, pnoca, peoca, ploca;
wire [7:0] paddrx, paddry;
wire prst_n;
 
router RT (
.sia ( psia ),
.wia ( pwia ),
.nia ( pnia ),
.eia ( peia ),
.lia ( plia ),
.sic ( psic ),
.wic ( pwic ),
.nic ( pnic ),
.eic ( peic ),
.lic ( plic ),
.so0 ( pso0 ),
.so1 ( pso1 ),
.so2 ( pso2 ),
.so3 ( pso3 ),
.wo0 ( pwo0 ),
.wo1 ( pwo1 ),
.wo2 ( pwo2 ),
.wo3 ( pwo3 ),
.no0 ( pno0 ),
.no1 ( pno1 ),
.no2 ( pno2 ),
.no3 ( pno3 ),
.eo0 ( peo0 ),
.eo1 ( peo1 ),
.eo2 ( peo2 ),
.eo3 ( peo3 ),
.lo0 ( plo0 ),
.lo1 ( plo1 ),
.lo2 ( plo2 ),
.lo3 ( plo3 ),
.soft ( psoft ),
.woft ( pwoft ),
.noft ( pnoft ),
.eoft ( peoft ),
.loft ( ploft ),
.sovc ( psovc ),
.wovc ( pwovc ),
.novc ( pnovc ),
.eovc ( peovc ),
.lovc ( plovc ),
.soca ( psoca ),
.woca ( pwoca ),
.noca ( pnoca ),
.eoca ( peoca ),
.loca ( ploca ),
.si0 ( psi0 ),
.si1 ( psi1 ),
.si2 ( psi2 ),
.si3 ( psi3 ),
.wi0 ( pwi0 ),
.wi1 ( pwi1 ),
.wi2 ( pwi2 ),
.wi3 ( pwi3 ),
.ni0 ( pni0 ),
.ni1 ( pni1 ),
.ni2 ( pni2 ),
.ni3 ( pni3 ),
.ei0 ( pei0 ),
.ei1 ( pei1 ),
.ei2 ( pei2 ),
.ei3 ( pei3 ),
.li0 ( pli0 ),
.li1 ( pli1 ),
.li2 ( pli2 ),
.li3 ( pli3 ),
.sift ( psift ),
.wift ( pwift ),
.nift ( pnift ),
.eift ( peift ),
.lift ( plift ),
.sivc ( psivc ),
.wivc ( pwivc ),
.nivc ( pnivc ),
.eivc ( peivc ),
.livc ( plivc ),
.sica ( psica ),
.wica ( pwica ),
.nica ( pnica ),
.eica ( peica ),
.lica ( plica ),
.soa ( psoa ),
.woa ( pwoa ),
.noa ( pnoa ),
.eoa ( peoa ),
.loa ( ploa ),
.soc ( psoc ),
.woc ( pwoc ),
.noc ( pnoc ),
.eoc ( peoc ),
.loc ( ploc ),
.addrx ( paddrx ),
.addry ( paddry ),
.rst_n ( prst_n )
);
assign sia = psia ;
assign wia = pwia ;
assign nia = pnia ;
assign eia = peia ;
assign lia = plia ;
assign sic = psic ;
assign wic = pwic ;
assign nic = pnic ;
assign eic = peic ;
assign lic = plic ;
assign so0 = pso0 ;
assign so1 = pso1 ;
assign so2 = pso2 ;
assign so3 = pso3 ;
assign wo0 = pwo0 ;
assign wo1 = pwo1 ;
assign wo2 = pwo2 ;
assign wo3 = pwo3 ;
assign no0 = pno0 ;
assign no1 = pno1 ;
assign no2 = pno2 ;
assign no3 = pno3 ;
assign eo0 = peo0 ;
assign eo1 = peo1 ;
assign eo2 = peo2 ;
assign eo3 = peo3 ;
assign lo0 = plo0 ;
assign lo1 = plo1 ;
assign lo2 = plo2 ;
assign lo3 = plo3 ;
assign soft = psoft ;
assign woft = pwoft ;
assign noft = pnoft ;
assign eoft = peoft ;
assign loft = ploft ;
assign sovc = psovc ;
assign wovc = pwovc ;
assign novc = pnovc ;
assign eovc = peovc ;
assign lovc = plovc ;
assign soca = psoca ;
assign woca = pwoca ;
assign noca = pnoca ;
assign eoca = peoca ;
assign loca = ploca ;
assign psi0 = si0 ;
assign psi1 = si1 ;
assign psi2 = si2 ;
assign psi3 = si3 ;
assign pwi0 = wi0 ;
assign pwi1 = wi1 ;
assign pwi2 = wi2 ;
assign pwi3 = wi3 ;
assign pni0 = ni0 ;
assign pni1 = ni1 ;
assign pni2 = ni2 ;
assign pni3 = ni3 ;
assign pei0 = ei0 ;
assign pei1 = ei1 ;
assign pei2 = ei2 ;
assign pei3 = ei3 ;
assign pli0 = li0 ;
assign pli1 = li1 ;
assign pli2 = li2 ;
assign pli3 = li3 ;
assign psift = sift ;
assign pwift = wift ;
assign pnift = nift ;
assign peift = eift ;
assign plift = lift ;
assign psivc = sivc ;
assign pwivc = wivc ;
assign pnivc = nivc ;
assign peivc = eivc ;
assign plivc = livc ;
assign psica = sica ;
assign pwica = wica ;
assign pnica = nica ;
assign peica = eica ;
assign plica = lica ;
assign psoa = soa ;
assign pwoa = woa ;
assign pnoa = noa ;
assign peoa = eoa ;
assign ploa = loa ;
assign psoc = soc ;
assign pwoc = woc ;
assign pnoc = noc ;
assign peoc = eoc ;
assign ploc = loc ;
assign paddrx = addrx ;
assign paddry = addry ;
assign prst_n = rst_n ;
 
initial $sdf_annotate("../syn/file/router.sdf", RT);
endmodule
/vc/tb/node_top.v
0,0 → 1,125
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
A network node including a router, a NI and a processing element.
History:
03/03/2011 Initial version. <wsong83@gmail.com>
04/03/2011 Support VC. <wsong83@gmail.com>
05/06/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
// the router structure definitions
`include "define.v"
 
module node_top(/*AUTOARG*/
// Outputs
sia, wia, nia, eia, sic, wic, nic, eic, so0, so1, so2, so3, wo0,
wo1, wo2, wo3, no0, no1, no2, no3, eo0, eo1, eo2, eo3, soft, woft,
noft, eoft, sovc, wovc, novc, eovc, soca, woca, noca, eoca,
// Inputs
si0, si1, si2, si3, wi0, wi1, wi2, wi3, ni0, ni1, ni2, ni3, ei0,
ei1, ei2, ei3, sift, wift, nift, eift, sivc, wivc, nivc, eivc,
sica, wica, nica, eica, soa, woa, noa, eoa, soc, woc, noc, eoc,
rst_n
);
parameter DW = 32;
parameter VCN = 1;
parameter FT = 3;
parameter x = 0;
parameter y = 0;
parameter SCN = DW/2;
 
input [SCN-1:0] si0, si1, si2, si3;
input [SCN-1:0] wi0, wi1, wi2, wi3;
input [SCN-1:0] ni0, ni1, ni2, ni3;
input [SCN-1:0] ei0, ei1, ei2, ei3;
input [FT-1:0] sift, wift, nift, eift;
input [VCN-1:0] sivc, wivc, nivc, eivc;
output sia, wia, nia, eia;
output [VCN-1:0] sic, wic, nic, eic;
input [VCN-1:0] sica, wica, nica, eica;
 
output [SCN-1:0] so0, so1, so2, so3;
output [SCN-1:0] wo0, wo1, wo2, wo3;
output [SCN-1:0] no0, no1, no2, no3;
output [SCN-1:0] eo0, eo1, eo2, eo3;
output [FT-1:0] soft, woft, noft, eoft;
output [VCN-1:0] sovc, wovc, novc, eovc;
input soa, woa, noa, eoa;
input [VCN-1:0] soc, woc, noc, eoc;
output [VCN-1:0] soca, woca, noca, eoca;
 
wire [SCN-1:0] li0, li1, li2, li3;
wire [SCN-1:0] lo0, lo1, lo2, lo3;
wire [FT-1:0] lift;
wire [VCN-1:0] livc;
wire lia;
wire [VCN-1:0] lic;
wire [VCN-1:0] lica;
wire [FT-1:0] loft;
wire [VCN-1:0] lovc;
wire loa;
wire [VCN-1:0] loc;
wire [VCN-1:0] loca;
 
input rst_n;
 
// the network node
NetNode #(.DW(DW), .VCN(VCN), .FT(FT), .x(x), .y(y))
Node (
.doa(loa), .doc(loc),
.do0(lo0), .do1(lo1), .do2(lo2), .do3(lo3),
.doft(loft), .dovc(lovc), .doca(loca),
.dia(lia), .dic(lic),
.di0(li0), .di1(li1), .di2(li2), .di3(li3),
.dift(lift), .divc(livc), .dica(lica),
.rst_n(rst_n)
);
// router wrapper
router_hdl #(.DW(DW), .VCN(VCN))
RTN (
.so0(so0), .so1(so1), .so2(so2), .so3(so3), .soa(soa), .soft(soft), .sovc(sovc), .soc(soc), .soca(soca),
.wo0(wo0), .wo1(wo1), .wo2(wo2), .wo3(wo3), .woa(woa), .woft(woft), .wovc(wovc), .woc(woc), .woca(woca),
.no0(no0), .no1(no1), .no2(no2), .no3(no3), .noa(noa), .noft(noft), .novc(novc), .noc(noc), .noca(noca),
.eo0(eo0), .eo1(eo1), .eo2(eo2), .eo3(eo3), .eoa(eoa), .eoft(eoft), .eovc(eovc), .eoc(eoc), .eoca(eoca),
.lo0(lo0), .lo1(lo1), .lo2(lo2), .lo3(lo3), .loa(loa), .loft(loft), .lovc(lovc), .loc(loc), .loca(loca),
.si0(si0), .si1(si1), .si2(si2), .si3(si3), .sia(sia), .sift(sift), .sivc(sivc), .sic(sic), .sica(sica),
.wi0(wi0), .wi1(wi1), .wi2(wi2), .wi3(wi3), .wia(wia), .wift(wift), .wivc(wivc), .wic(wic), .wica(wica),
.ni0(ni0), .ni1(ni1), .ni2(ni2), .ni3(ni3), .nia(nia), .nift(nift), .nivc(nivc), .nic(nic), .nica(nica),
.ei0(ei0), .ei1(ei1), .ei2(ei2), .ei3(ei3), .eia(eia), .eift(eift), .eivc(eivc), .eic(eic), .eica(eica),
.li0(li0), .li1(li1), .li2(li2), .li3(li3), .lia(lia), .lift(lift), .livc(livc), .lic(lic), .lica(lica),
.addrx (b2chain(x)),
.addry (b2chain(y)),
.rst_n (rst_n)
);
 
// binary to 1-of-4 (Chain) converter
function [7:0] b2chain;
input [3:0] data;
begin
b2chain[0] = (data[1:0] == 2'b00);
b2chain[1] = (data[1:0] == 2'b01);
b2chain[2] = (data[1:0] == 2'b10);
b2chain[3] = (data[1:0] == 2'b11);
b2chain[4] = (data[3:2] == 2'b00);
b2chain[5] = (data[3:2] == 2'b01);
b2chain[6] = (data[3:2] == 2'b10);
b2chain[7] = (data[3:2] == 2'b11);
end
endfunction
 
endmodule // node_top
/vc/tb/ni.h
0,0 → 1,69
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
Network interface for the VC router.
History:
20/08/2008 Initial version. <wsong83@gmail.com>
30/09/2010 Use template style packet definition. <wsong83@gmail.com>
05/06/2011 Clean up for opensource. <wsong83@gmail.com>
 
*/
 
#ifndef NETWORK_ADAPTER_H_
#define NETWORK_ADAPTER_H_
 
#include "define.h"
#include <systemc.h>
 
SC_MODULE(Network_Adapter)
{
public:
SC_HAS_PROCESS(Network_Adapter);
Network_Adapter(
sc_module_name name // module name
,unsigned int x // location x
,unsigned int y // location y
);
~Network_Adapter();
// interface with processor
sc_port<sc_fifo_in_if<FRAME> > frame_in; // frame for transmission
sc_port<sc_fifo_out_if<FRAME> > frame_out; // frame for receiving
// interface with router
sc_port<sc_fifo_in_if<FLIT> > IP; // input port from IO driver
sc_port<sc_fifo_out_if<FLIT> > OP; // output port to IO driver
sc_in<bool> CP [SubChN]; // the credit input from the router input buffer
sc_out<bool> CPa [SubChN]; // ack to the credit
 
private:
unsigned int loc_x,loc_y; // location information
sc_fifo<FLIT> oflit; // the current flit under transmission
sc_fifo<FLIT> iflit [SubChN]; // the current flits under receiving from all input VCs
unsigned int token [SubChN]; // the token ready for each output VC
sc_event token_arrive [SubChN]; // the token ready event
// functional thread
void ibuffer_thread(unsigned int); // input buffer respond thread
void obuffer_thread(unsigned int); // output buffer respond thread
void oport(); // the thread transmitting flit
void iport(); // the thread receiving flits
void credit_update(unsigned int); // receive credits and update the available tokens
 
// other functions
bool check_frame(const FRAME& frame); // check the correctness of frame received
};
 
#endif
 
/vc/tb/netnode.cpp
0,0 → 1,23
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
The SystemC module of network node including the processing element and the network interface.
Currently the transmission FIFO is 500 frame deep.
History:
26/02/2011 Initial version. <wsong83@gmail.com>
*/
 
#include "netnode.h"
 
NCSC_MODULE_EXPORT(NetNode)
 
/vc/src/fcctl.v
0,0 → 1,62
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
Flow control unit.
History:
31/03/2010 Initial version. <wsong83@gmail.com>
12/05/2010 Use MPxP crossbar. <wsong83@gmail.com>
02/06/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
module fcctl ( /*AUTOARG*/
// Outputs
afc, ro,
// Inputs
credit, ri, rst
);
parameter VCN = 2; // number of VCs per direction
parameter PD = 3; // depth of an input VC buffer
input [VCN-1:0] credit; // credit input from the next router
output [VCN-1:0] afc; // ack for the credit input
input [VCN-1:0] ri; // VC request from VCA
output [VCN-1:0] ro; // credit grant output
input rst; // active high reset
 
wire [PD:0][VCN-1:0] cp, cpa;
 
genvar i,j;
 
// the credit pipeline
generate
for(i=0; i<PD; i++) begin: P
for(j=0; j<VCN; j++) begin: V
cpipe CP (.cia(cpa[i][j]), .co(cp[i+1][j]), .rst(rst), .ci(cp[i][j]), .coa(cpa[i+1][j]));
end
end
endgenerate
 
// grant a credit to a VC request
generate
for(i=0; i<VCN; i++) begin:R
dc2 CR (.a(ri[i]), .d(cp[PD][i]), .q(cpa[PD][i]));
end
endgenerate
 
assign ro = cpa[PD];
assign cp[0] = credit;
assign afc = cpa[0];
 
endmodule // fcctl
 
/vc/src/rcb_vc.v
0,0 → 1,139
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
The request crossbar in the VC allocator of VC routers.
History:
04/04/2010 Initial version. <wsong83@gmail.com>
01/06/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
module rcb_vc (/*AUTOARG*/
// Outputs
ro, srt, nrt, lrt, wrt, ert, wctla, ectla, lctla, sctla, nctla,
// Inputs
ri, go, wctl, ectl, lctl, sctl, nctl
);
 
parameter VCN = 2; // the number of VCs per direction
 
input [4:0][VCN-1:0][1:0] ri; // the request input from all inputs
output [4:0][VCN-1:0] ro; // the request output to all output port arbiters
input [4:0][VCN-1:0] go; // the granted VC info from all output port arbiters
output [VCN-1:0][3:0] srt, nrt, lrt; // routing guide to all input ports
output [VCN-1:0][1:0] wrt, ert;
input [VCN*4*VCN-1:0] wctl, ectl, lctl; // the configuration from VCA
input [VCN*2*VCN-1:0] sctl, nctl;
output [VCN*4*VCN-1:0] wctla, ectla, lctla; // the ack to VCA, fire when the frame is sent
output [VCN*2*VCN-1:0] sctla, nctla;
 
wire [VCN*4*VCN-1:0][1:0] wri, eri, lri;
wire [VCN*4*VCN-1:0] wgi, wgo, wro, egi, ego, ero, lgi, lgo, lro;
wire [VCN*2*VCN-1:0][1:0] sri, nri;
wire [VCN*2*VCN-1:0] sgi, sgo, sro, ngi, ngo, nro;
wire [4*VCN*VCN-1:0] wgis, egis, lgis;
wire [2*VCN*VCN-1:0] sgis, ngis;
genvar i,j;
generate
for(i=0; i<VCN; i++) begin:RI
// shuffle the input requests to all output ports
for(j=0; j<VCN; j++) begin: J
assign sri[i*2*VCN+0*VCN+j] = ri[2][j];
assign sri[i*2*VCN+1*VCN+j] = ri[4][j];
assign wri[i*4*VCN+0*VCN+j] = ri[0][j];
assign wri[i*4*VCN+1*VCN+j] = ri[2][j];
assign wri[i*4*VCN+2*VCN+j] = ri[3][j];
assign wri[i*4*VCN+3*VCN+j] = ri[4][j];
assign nri[i*2*VCN+0*VCN+j] = ri[0][j];
assign nri[i*2*VCN+1*VCN+j] = ri[4][j];
assign eri[i*4*VCN+0*VCN+j] = ri[0][j];
assign eri[i*4*VCN+1*VCN+j] = ri[1][j];
assign eri[i*4*VCN+2*VCN+j] = ri[2][j];
assign eri[i*4*VCN+3*VCN+j] = ri[4][j];
assign lri[i*4*VCN+0*VCN+j] = ri[0][j];
assign lri[i*4*VCN+1*VCN+j] = ri[1][j];
assign lri[i*4*VCN+2*VCN+j] = ri[2][j];
assign lri[i*4*VCN+3*VCN+j] = ri[3][j];
end
 
// generate the requests to output port arbiters
assign ro[0][i] = |sro[i*2*VCN +: 2*VCN];
assign ro[1][i] = |wro[i*4*VCN +: 4*VCN];
assign ro[2][i] = |nro[i*2*VCN +: 2*VCN];
assign ro[3][i] = |ero[i*4*VCN +: 4*VCN];
assign ro[4][i] = |lro[i*4*VCN +: 4*VCN];
 
// demux to duplicate the grant to all input ports
assign sgo[i*2*VCN +: 2*VCN] = {2*VCN{go[0][i]}};
assign wgo[i*4*VCN +: 4*VCN] = {4*VCN{go[1][i]}};
assign ngo[i*2*VCN +: 2*VCN] = {2*VCN{go[2][i]}};
assign ego[i*4*VCN +: 4*VCN] = {4*VCN{go[3][i]}};
assign lgo[i*4*VCN +: 4*VCN] = {4*VCN{go[4][i]}};
 
// generate the routing guide from output grants (sgo -- lgo)
assign srt[i] = {|lgis[(0*VCN+i)*VCN +: VCN], |egis[(0*VCN+i)*VCN +: VCN], |ngis[(0*VCN+i)*VCN +: VCN], |wgis[(0*VCN+i)*VCN +: VCN]};
assign wrt[i] = {|lgis[(1*VCN+i)*VCN +: VCN], |egis[(1*VCN+i)*VCN +: VCN]};
assign nrt[i] = {|lgis[(2*VCN+i)*VCN +: VCN], |egis[(2*VCN+i)*VCN +: VCN], |wgis[(1*VCN+i)*VCN +: VCN], |sgis[(0*VCN+i)*VCN +: VCN]};
assign ert[i] = {|lgis[(3*VCN+i)*VCN +: VCN], |wgis[(2*VCN+i)*VCN +: VCN]};
assign lrt[i] = {|egis[(3*VCN+i)*VCN +: VCN], |ngis[(1*VCN+i)*VCN +: VCN], |wgis[(3*VCN+i)*VCN +: VCN], |sgis[(1*VCN+i)*VCN +: VCN]};
 
// part of the routing guide process
for(j=0; j<4*VCN; j++) begin:SB
assign wgis[j*VCN+i] = wgi[i*4*VCN+j];
assign egis[j*VCN+i] = egi[i*4*VCN+j];
assign lgis[j*VCN+i] = lgi[i*4*VCN+j];
end
 
for(j=0; j<2*VCN; j++) begin:SL
assign sgis[j*VCN+i] = sgi[i*2*VCN+j];
assign ngis[j*VCN+i] = ngi[i*2*VCN+j];
end
end
 
// cross points
for(i=0; i<VCN*4*VCN; i++) begin:BB
RCBB W (.ri(wri[i]), .ro(wro[i]), .go(wgo[i]), .gi(wgi[i]), .ctl(wctl[i]), .ctla(wctla[i]));
RCBB E (.ri(eri[i]), .ro(ero[i]), .go(ego[i]), .gi(egi[i]), .ctl(ectl[i]), .ctla(ectla[i]));
RCBB L (.ri(lri[i]), .ro(lro[i]), .go(lgo[i]), .gi(lgi[i]), .ctl(lctl[i]), .ctla(lctla[i]));
end
for(i=0; i<VCN*2*VCN; i++) begin:BL
RCBB S (.ri(sri[i]), .ro(sro[i]), .go(sgo[i]), .gi(sgi[i]), .ctl(sctl[i]), .ctla(sctla[i]));
RCBB N (.ri(nri[i]), .ro(nro[i]), .go(ngo[i]), .gi(ngi[i]), .ctl(nctl[i]), .ctla(nctla[i]));
end
endgenerate
 
endmodule // rcb_vc
 
// Request CrossBar cross point Block
module RCBB (ri, ro, go, gi, ctl, ctla);
input [1:0] ri; // requests from input ports (0: data and head, 1: eof)
output ro; // requests to output ports
input go; // grant from output ports
output gi; // grant to input ports, later translated into routing guide
input ctl; // configuration from VCA
output ctla; // configuration ack to VCA, fire after ri[1] fires
 
wire [1:0] m;
 
c2 I0 (.a0(ri[1]), .a1(ctl), .q(m[1]));
and I1 ( m[0], ri[0], ctl);
or I2 ( ro, m[0], m[1]);
c2 I3 ( .a0(ro), .a1(go), .q(gi));
c2 IA ( .a0(m[1]), .a1(go), .q(ctla));
endmodule // RCBB
 
 
/vc/src/cpipe.v
0,0 → 1,42
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
The full dual-rail pipeline stage for the credit fifo in VC routers.
It has a reset pin to feed a token into every cpipe stage.
History:
31/03/2010 Initial version. <wsong83@gmail.com>
01/06/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
module cpipe (/*AUTOARG*/
// Outputs
cia, co,
// Inputs
rst, ci, coa
);
input rst; // active high reset
input ci; // credit input
output cia; // credit input ack
output co; // credit output
input coa; // credit output ack
 
wire c0, c1; // internal wires
 
dc2 C0 ( .d(ci), .a(~c1), .q(c0));
dc2 C1 ( .d(c0|rst), .a((~coa)|rst), .q(c1));
 
assign co = (~rst)&c1;
assign cia = c0;
 
endmodule // cpipe
/vc/src/dcb_vc.v
0,0 → 1,310
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
data crossbar for the VC router
History:
04/04/2010 Initial version. <wsong83@gmail.com>
12/05/2010 Use MPxP crossbar. <wsong83@gmail.com>
02/06/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
module dcb_vc (/*AUTOARG*/
// Outputs
dia, do0, do1, do2, do3, dot,
// Inputs
di0, di1, di2, di3, dit, srtg, nrtg, lrtg, wrtg, ertg, doa
);
parameter DW = 32; // data width of a VC
parameter FT = 3; // wire count of the flit tyoe bus
parameter VCN = 2; // number of VC per direction
parameter SCN = DW/2;
 
input [4:0][VCN-1:0][SCN-1:0] di0, di1, di2, di3; // data input
input [4:0][VCN-1:0][FT-1:0] dit; // flit type input
output [4:0][VCN-1:0] dia; // input ack
input [VCN-1:0][3:0] srtg, nrtg, lrtg; // routing guide
input [VCN-1:0][1:0] wrtg, ertg;
 
output [4:0][SCN-1:0] do0, do1, do2, do3; // data output
output [4:0][FT-1:0] dot; // flit type output
input [4:0] doa; // output ack
 
// internal wires
wire [VCN-1:0][3:0][SCN-1:0] s0, s1, s2, s3;
wire [VCN-1:0][3:0][FT-1:0] sft;
wire [VCN-1:0][3:0] sa;
wire [VCN-1:0][1:0][SCN-1:0] w0, w1, w2, w3;
wire [VCN-1:0][1:0][FT-1:0] wft;
wire [VCN-1:0][1:0] wa;
wire [VCN-1:0][3:0][SCN-1:0] n0, n1, n2, n3;
wire [VCN-1:0][3:0][FT-1:0] nft;
wire [VCN-1:0][3:0] na;
wire [VCN-1:0][1:0][SCN-1:0] e0, e1, e2, e3;
wire [VCN-1:0][1:0][FT-1:0] eft;
wire [VCN-1:0][1:0] ea;
wire [VCN-1:0][3:0][SCN-1:0] l0, l1, l2, l3;
wire [VCN-1:0][3:0][FT-1:0] lft;
wire [VCN-1:0][3:0] la;
 
wire [3:0][SCN-1:0][VCN-1:0] ss0, ss1, ss2, ss3;
wire [3:0][FT-1:0][VCN-1:0] ssft;
wire [1:0][SCN-1:0][VCN-1:0] sw0, sw1, sw2, sw3;
wire [1:0][FT-1:0][VCN-1:0] swft;
wire [3:0][SCN-1:0][VCN-1:0] sn0, sn1, sn2, sn3;
wire [3:0][FT-1:0][VCN-1:0] snft;
wire [1:0][SCN-1:0][VCN-1:0] se0, se1, se2, se3;
wire [1:0][FT-1:0][VCN-1:0] seft;
wire [3:0][SCN-1:0][VCN-1:0] sl0, sl1, sl2, sl3;
wire [3:0][FT-1:0][VCN-1:0] slft;
 
wire [3:0][SCN-1:0] ms0, ms1, ms2, ms3;
wire [3:0][FT-1:0] msft;
wire [1:0][SCN-1:0] mw0, mw1, mw2, mw3;
wire [1:0][FT-1:0] mwft;
wire [3:0][SCN-1:0] mn0, mn1, mn2, mn3;
wire [3:0][FT-1:0] mnft;
wire [1:0][SCN-1:0] me0, me1, me2, me3;
wire [1:0][FT-1:0] meft;
wire [3:0][SCN-1:0] ml0, ml1, ml2, ml3;
wire [3:0][FT-1:0] mlft;
 
genvar i,j,k;
generate
// demux using the routing guides
for(i=0; i<VCN; i++) begin: IMX
vcdmux #(.DW(DW), .VCN(4))
SDMX(
.dia ( dia[0][i] ),
.do0 ( s0[i] ),
.do1 ( s1[i] ),
.do2 ( s2[i] ),
.do3 ( s3[i] ),
.dot ( sft[i] ),
.di0 ( di0[0][i] ),
.di1 ( di1[0][i] ),
.di2 ( di2[0][i] ),
.di3 ( di3[0][i] ),
.dit ( dit[0][i] ),
.divc ( srtg[i] ),
.doa ( sa[i] )
);
vcdmux #(.DW(DW), .VCN(2))
WDMX(
.dia ( dia[1][i] ),
.do0 ( w0[i] ),
.do1 ( w1[i] ),
.do2 ( w2[i] ),
.do3 ( w3[i] ),
.dot ( wft[i] ),
.di0 ( di0[1][i] ),
.di1 ( di1[1][i] ),
.di2 ( di2[1][i] ),
.di3 ( di3[1][i] ),
.dit ( dit[1][i] ),
.divc ( wrtg[i] ),
.doa ( wa[i] )
);
 
vcdmux #(.DW(DW), .VCN(4))
NDMX(
.dia ( dia[2][i] ),
.do0 ( n0[i] ),
.do1 ( n1[i] ),
.do2 ( n2[i] ),
.do3 ( n3[i] ),
.dot ( nft[i] ),
.di0 ( di0[2][i] ),
.di1 ( di1[2][i] ),
.di2 ( di2[2][i] ),
.di3 ( di3[2][i] ),
.dit ( dit[2][i] ),
.divc ( nrtg[i] ),
.doa ( na[i] )
);
vcdmux #(.DW(DW), .VCN(2))
EDMX(
.dia ( dia[3][i] ),
.do0 ( e0[i] ),
.do1 ( e1[i] ),
.do2 ( e2[i] ),
.do3 ( e3[i] ),
.dot ( eft[i] ),
.di0 ( di0[3][i] ),
.di1 ( di1[3][i] ),
.di2 ( di2[3][i] ),
.di3 ( di3[3][i] ),
.dit ( dit[3][i] ),
.divc ( ertg[i] ),
.doa ( ea[i] )
);
 
vcdmux #(.DW(DW), .VCN(4))
LDMX(
.dia ( dia[4][i] ),
.do0 ( l0[i] ),
.do1 ( l1[i] ),
.do2 ( l2[i] ),
.do3 ( l3[i] ),
.dot ( lft[i] ),
.di0 ( di0[4][i] ),
.di1 ( di1[4][i] ),
.di2 ( di2[4][i] ),
.di3 ( di3[4][i] ),
.dit ( dit[4][i] ),
.divc ( lrtg[i] ),
.doa ( la[i] )
);
// acknowledgement
c2 SA0 (.a0(srtg[i][0]), .a1(doa[1]), .q(sa[i][0]));
c2 SA1 (.a0(srtg[i][1]), .a1(doa[2]), .q(sa[i][1]));
c2 SA2 (.a0(srtg[i][2]), .a1(doa[3]), .q(sa[i][2]));
c2 SA3 (.a0(srtg[i][3]), .a1(doa[4]), .q(sa[i][3]));
c2 WA0 (.a0(wrtg[i][0]), .a1(doa[3]), .q(wa[i][0]));
c2 WA1 (.a0(wrtg[i][1]), .a1(doa[4]), .q(wa[i][1]));
c2 NA0 (.a0(nrtg[i][0]), .a1(doa[0]), .q(na[i][0]));
c2 NA1 (.a0(nrtg[i][1]), .a1(doa[1]), .q(na[i][1]));
c2 NA2 (.a0(nrtg[i][2]), .a1(doa[3]), .q(na[i][2]));
c2 NA3 (.a0(nrtg[i][3]), .a1(doa[4]), .q(na[i][3]));
c2 EA0 (.a0(ertg[i][0]), .a1(doa[1]), .q(ea[i][0]));
c2 EA1 (.a0(ertg[i][1]), .a1(doa[4]), .q(ea[i][1]));
c2 LA0 (.a0(lrtg[i][0]), .a1(doa[0]), .q(la[i][0]));
c2 LA1 (.a0(lrtg[i][1]), .a1(doa[1]), .q(la[i][1]));
c2 LA2 (.a0(lrtg[i][2]), .a1(doa[2]), .q(la[i][2]));
c2 LA3 (.a0(lrtg[i][3]), .a1(doa[3]), .q(la[i][3]));
 
end // block: IMX
endgenerate
 
generate
for(i=0; i<VCN; i++) begin: V
for(j=0; j<4; j++) begin: D0
for(k=0; k<SCN; k++) begin: D
assign ss0[j][k][i] = s0[i][j][k];
assign ss1[j][k][i] = s1[i][j][k];
assign ss2[j][k][i] = s2[i][j][k];
assign ss3[j][k][i] = s3[i][j][k];
assign sn0[j][k][i] = n0[i][j][k];
assign sn1[j][k][i] = n1[i][j][k];
assign sn2[j][k][i] = n2[i][j][k];
assign sn3[j][k][i] = n3[i][j][k];
assign sl0[j][k][i] = l0[i][j][k];
assign sl1[j][k][i] = l1[i][j][k];
assign sl2[j][k][i] = l2[i][j][k];
assign sl3[j][k][i] = l3[i][j][k];
end // block: D
for(k=0; k<FT; k++) begin: T
assign ssft[j][k][i] = sft[i][j][k];
assign snft[j][k][i] = nft[i][j][k];
assign slft[j][k][i] = lft[i][j][k];
end // block: T
end // block: D0
for(j=0; j<2; j++) begin: D1
for(k=0; k<SCN; k++) begin: D
assign sw0[j][k][i] = w0[i][j][k];
assign sw1[j][k][i] = w1[i][j][k];
assign sw2[j][k][i] = w2[i][j][k];
assign sw3[j][k][i] = w3[i][j][k];
assign se0[j][k][i] = e0[i][j][k];
assign se1[j][k][i] = e1[i][j][k];
assign se2[j][k][i] = e2[i][j][k];
assign se3[j][k][i] = e3[i][j][k];
end // block: D
for(k=0; k<FT; k++) begin: T
assign swft[j][k][i] = wft[i][j][k];
assign seft[j][k][i] = eft[i][j][k];
end // block: T
end // block: D1
end
 
for(j=0; j<4; j++) begin: D2
for(k=0; k<SCN; k++) begin: D
assign ms0[j][k] = |ss0[j][k];
assign ms1[j][k] = |ss1[j][k];
assign ms2[j][k] = |ss2[j][k];
assign ms3[j][k] = |ss3[j][k];
assign mn0[j][k] = |sn0[j][k];
assign mn1[j][k] = |sn1[j][k];
assign mn2[j][k] = |sn2[j][k];
assign mn3[j][k] = |sn3[j][k];
assign ml0[j][k] = |sl0[j][k];
assign ml1[j][k] = |sl1[j][k];
assign ml2[j][k] = |sl2[j][k];
assign ml3[j][k] = |sl3[j][k];
end // block: D
for(k=0; k<FT; k++) begin: T
assign msft[j][k] = |ssft[j][k];
assign mnft[j][k] = |snft[j][k];
assign mlft[j][k] = |slft[j][k];
end
end // block: D2
 
for(j=0; j<2; j++) begin: D4
for(k=0; k<SCN; k++) begin: D
assign mw0[j][k] = |sw0[j][k];
assign mw1[j][k] = |sw1[j][k];
assign mw2[j][k] = |sw2[j][k];
assign mw3[j][k] = |sw3[j][k];
assign me0[j][k] = |se0[j][k];
assign me1[j][k] = |se1[j][k];
assign me2[j][k] = |se2[j][k];
assign me3[j][k] = |se3[j][k];
end // block: D
for(k=0; k<FT; k++) begin: T
assign mwft[j][k] = |swft[j][k];
assign meft[j][k] = |seft[j][k];
end // block: T
end // block: D4
endgenerate
// south output
assign do0[0] = mn0[0]|ml0[0];
assign do1[0] = mn1[0]|ml1[0];
assign do2[0] = mn2[0]|ml2[0];
assign do3[0] = mn3[0]|ml3[0];
assign dot[0] = mnft[0]|mlft[0];
 
// west output
assign do0[1] = ms0[0]|mn0[1]|me0[0]|ml0[1];
assign do1[1] = ms1[0]|mn1[1]|me1[0]|ml1[1];
assign do2[1] = ms2[0]|mn2[1]|me2[0]|ml2[1];
assign do3[1] = ms3[0]|mn3[1]|me3[0]|ml3[1];
assign dot[1] = msft[0]|mnft[1]|meft[0]|mlft[1];
 
// south output
assign do0[2] = ms0[1]|ml0[2];
assign do1[2] = ms1[1]|ml1[2];
assign do2[2] = ms2[1]|ml2[2];
assign do3[2] = ms3[1]|ml3[2];
assign dot[2] = msft[1]|mlft[2];
 
// east output
assign do0[3] = ms0[2]|mw0[0]|mn0[2]|ml0[3];
assign do1[3] = ms1[2]|mw1[0]|mn1[2]|ml1[3];
assign do2[3] = ms2[2]|mw2[0]|mn2[2]|ml2[3];
assign do3[3] = ms3[2]|mw3[0]|mn3[2]|ml3[3];
assign dot[3] = msft[2]|mwft[0]|mnft[2]|mlft[3];
 
// local output
assign do0[4] = ms0[3]|mw0[1]|mn0[3]|me0[1];
assign do1[4] = ms1[3]|mw1[1]|mn1[3]|me1[1];
assign do2[4] = ms2[3]|mw2[1]|mn2[3]|me2[1];
assign do3[4] = ms3[3]|mw3[1]|mn3[3]|me3[1];
assign dot[4] = msft[3]|mwft[1]|mnft[3]|meft[1];
 
 
endmodule // dcb_vc
/vc/src/router.v
0,0 → 1,424
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
Asynchronous VC router.
History:
05/04/2010 Initial version. <wsong83@gmail.com>
02/06/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
module router (/*AUTOARG*/
// Outputs
sia, wia, nia, eia, lia, sic, wic, nic, eic, lic, so0, so1, so2,
so3, wo0, wo1, wo2, wo3, no0, no1, no2, no3, eo0, eo1, eo2, eo3,
lo0, lo1, lo2, lo3, soft, woft, noft, eoft, loft, sovc, wovc, novc,
eovc, lovc, soca, woca, noca, eoca, loca,
// Inputs
si0, si1, si2, si3, wi0, wi1, wi2, wi3, ni0, ni1, ni2, ni3, ei0,
ei1, ei2, ei3, li0, li1, li2, li3, sift, wift, nift, eift, lift,
sivc, wivc, nivc, eivc, livc, sica, wica, nica, eica, lica, soa,
woa, noa, eoa, loa, soc, woc, noc, eoc, loc, addrx, addry, rst_n
);
 
parameter VCN = 2; // number of VCs per direction
parameter DW = 32; // data width of an input port
parameter PD = 1; // the depth of a input VC buffer
parameter FT = 3; // the number of flit types, currently 3 (HD, DATA, TAIL)
parameter FCPD = PD;
parameter SCN = DW/2;
 
// input ports
input [SCN-1:0] si0, si1, si2, si3;
input [SCN-1:0] wi0, wi1, wi2, wi3;
input [SCN-1:0] ni0, ni1, ni2, ni3;
input [SCN-1:0] ei0, ei1, ei2, ei3;
input [SCN-1:0] li0, li1, li2, li3;
input [FT-1:0] sift, wift, nift, eift, lift;
input [VCN-1:0] sivc, wivc, nivc, eivc, livc;
output sia, wia, nia, eia, lia;
output [VCN-1:0] sic, wic, nic, eic, lic;
input [VCN-1:0] sica, wica, nica, eica, lica;
 
// output ports
output [SCN-1:0] so0, so1, so2, so3;
output [SCN-1:0] wo0, wo1, wo2, wo3;
output [SCN-1:0] no0, no1, no2, no3;
output [SCN-1:0] eo0, eo1, eo2, eo3;
output [SCN-1:0] lo0, lo1, lo2, lo3;
output [FT-1:0] soft, woft, noft, eoft, loft;
output [VCN-1:0] sovc, wovc, novc, eovc, lovc;
input soa, woa, noa, eoa, loa;
input [VCN-1:0] soc, woc, noc, eoc, loc;
output [VCN-1:0] soca, woca, noca, eoca, loca;
 
// local address, in 1-of-4 format
input [7:0] addrx, addry;
// active-low reset
input rst_n;
 
//----------------------------------
// input to crossbar
wire [VCN-1:0][SCN-1:0] s2cb0, s2cb1, s2cb2, s2cb3;
wire [VCN-1:0][SCN-1:0] w2cb0, w2cb1, w2cb2, w2cb3;
wire [VCN-1:0][SCN-1:0] n2cb0, n2cb1, n2cb2, n2cb3;
wire [VCN-1:0][SCN-1:0] e2cb0, e2cb1, e2cb2, e2cb3;
wire [VCN-1:0][SCN-1:0] l2cb0, l2cb1, l2cb2, l2cb3;
wire [VCN-1:0][FT-1:0] s2cbt, w2cbt, n2cbt, e2cbt, l2cbt;
wire [VCN-1:0][3:0] s2cbrtg, n2cbrtg, l2cbrtg;
wire [VCN-1:0][1:0] w2cbrtg, e2cbrtg;
wire [VCN-1:0] s2cba, w2cba, n2cba, e2cba, l2cba;
 
// VC requests
wire [VCN-1:0][3:0] svcr, nvcr, lvcr;
wire [VCN-1:0] svcra, nvcra, lvcra;
wire [VCN-1:0][1:0] wvcr, evcr;
wire [VCN-1:0] wvcra, evcra;
 
// SW requests
wire [VCN-1:0][1:0] siswr, wiswr, niswr, eiswr, liswr;
wire [VCN-1:0][3:0] siswrt, niswrt, liswrt;
wire [VCN-1:0][1:0] wiswrt, eiswrt;
 
// crossbar to output
wire [SCN-1:0] cb2s0, cb2s1, cb2s2, cb2s3;
wire [SCN-1:0] cb2w0, cb2w1, cb2w2, cb2w3;
wire [SCN-1:0] cb2n0, cb2n1, cb2n2, cb2n3;
wire [SCN-1:0] cb2e0, cb2e1, cb2e2, cb2e3;
wire [SCN-1:0] cb2l0, cb2l1, cb2l2, cb2l3;
wire [FT-1:0] cb2st, cb2wt, cb2nt, cb2et, cb2lt;
wire cb2sa, cb2wa, cb2na, cb2ea, cb2la;
 
// SW requests to VC arbiters in output buffers
wire [VCN-1:0] soswr, woswr, noswr, eoswr, loswr;
wire [VCN-1:0] soswa, woswa, noswa, eoswa, loswa;
 
//-------------------------------------
// south input buffer
inpbuf #(.DW(DW), .VCN(VCN), .DIR(0), .SN(4), .PD(PD), .FT(FT))
SIB (
.dia ( sia ),
.cor ( sic ),
.do0 ( s2cb0 ),
.do1 ( s2cb1 ),
.do2 ( s2cb2 ),
.do3 ( s2cb3 ),
.dot ( s2cbt ),
.dortg ( s2cbrtg ),
.vcr ( svcr ),
.swr ( siswr ),
.di0 ( si0 ),
.di1 ( si1 ),
.di2 ( si2 ),
.di3 ( si3 ),
.dit ( sift ),
.divc ( sivc ),
.coa ( sica ),
.doa ( s2cba ),
.vcra ( svcra ),
.swrt ( siswrt ),
.addrx ( addrx ),
.addry ( addry ),
.rst_n ( rst_n )
);
 
// west input buffer
inpbuf #(.DW(DW), .VCN(VCN), .DIR(1), .SN(2), .PD(PD), .FT(FT))
WIB (
.dia ( wia ),
.cor ( wic ),
.do0 ( w2cb0 ),
.do1 ( w2cb1 ),
.do2 ( w2cb2 ),
.do3 ( w2cb3 ),
.dot ( w2cbt ),
.dortg ( w2cbrtg ),
.vcr ( wvcr ),
.swr ( wiswr ),
.di0 ( wi0 ),
.di1 ( wi1 ),
.di2 ( wi2 ),
.di3 ( wi3 ),
.dit ( wift ),
.divc ( wivc ),
.coa ( wica ),
.doa ( w2cba ),
.vcra ( wvcra ),
.swrt ( wiswrt ),
.addrx ( addrx ),
.addry ( addry ),
.rst_n ( rst_n )
);
// north input buffer
inpbuf #(.DW(DW), .VCN(VCN), .DIR(2), .SN(4), .PD(PD), .FT(FT))
NIB (
.dia ( nia ),
.cor ( nic ),
.do0 ( n2cb0 ),
.do1 ( n2cb1 ),
.do2 ( n2cb2 ),
.do3 ( n2cb3 ),
.dot ( n2cbt ),
.dortg ( n2cbrtg ),
.vcr ( nvcr ),
.swr ( niswr ),
.di0 ( ni0 ),
.di1 ( ni1 ),
.di2 ( ni2 ),
.di3 ( ni3 ),
.dit ( nift ),
.divc ( nivc ),
.coa ( nica ),
.doa ( n2cba ),
.vcra ( nvcra ),
.swrt ( niswrt ),
.addrx ( addrx ),
.addry ( addry ),
.rst_n ( rst_n )
);
// east input buffer
inpbuf #(.DW(DW), .VCN(VCN), .DIR(3), .SN(2), .PD(PD), .FT(FT))
EIB (
.dia ( eia ),
.cor ( eic ),
.do0 ( e2cb0 ),
.do1 ( e2cb1 ),
.do2 ( e2cb2 ),
.do3 ( e2cb3 ),
.dot ( e2cbt ),
.dortg ( e2cbrtg ),
.vcr ( evcr ),
.swr ( eiswr ),
.di0 ( ei0 ),
.di1 ( ei1 ),
.di2 ( ei2 ),
.di3 ( ei3 ),
.dit ( eift ),
.divc ( eivc ),
.coa ( eica ),
.doa ( e2cba ),
.vcra ( evcra ),
.swrt ( eiswrt ),
.addrx ( addrx ),
.addry ( addry ),
.rst_n ( rst_n )
);
// local input buffer
inpbuf #(.DW(DW), .VCN(VCN), .DIR(4), .SN(4), .PD(PD), .FT(FT))
LIB (
.dia ( lia ),
.cor ( lic ),
.do0 ( l2cb0 ),
.do1 ( l2cb1 ),
.do2 ( l2cb2 ),
.do3 ( l2cb3 ),
.dot ( l2cbt ),
.dortg ( l2cbrtg ),
.vcr ( lvcr ),
.swr ( liswr ),
.di0 ( li0 ),
.di1 ( li1 ),
.di2 ( li2 ),
.di3 ( li3 ),
.dit ( lift ),
.divc ( livc ),
.coa ( lica ),
.doa ( l2cba ),
.vcra ( lvcra ),
.swrt ( liswrt ),
.addrx ( addrx ),
.addry ( addry ),
.rst_n ( rst_n )
);
 
// south output buffer
outpbuf #(.DW(DW), .VCN(VCN), .FT(FT), .FCPD(FCPD))
SOB (
.dia ( cb2sa ),
.do0 ( so0 ),
.do1 ( so1 ),
.do2 ( so2 ),
.do3 ( so3 ),
.dot ( soft ),
.dovc ( sovc ),
.afc ( soca ),
.vca ( soswa ),
.di0 ( cb2s0 ),
.di1 ( cb2s1 ),
.di2 ( cb2s2 ),
.di3 ( cb2s3 ),
.dit ( cb2st ),
.doa ( soa ),
.credit( soc ),
.vcr ( soswr ),
.rst_n ( rst_n )
);
 
// west output buffer
outpbuf #(.DW(DW), .VCN(VCN), .FT(FT), .FCPD(FCPD))
WOB (
.dia ( cb2wa ),
.do0 ( wo0 ),
.do1 ( wo1 ),
.do2 ( wo2 ),
.do3 ( wo3 ),
.dot ( woft ),
.dovc ( wovc ),
.afc ( woca ),
.vca ( woswa ),
.di0 ( cb2w0 ),
.di1 ( cb2w1 ),
.di2 ( cb2w2 ),
.di3 ( cb2w3 ),
.dit ( cb2wt ),
.doa ( woa ),
.credit( woc ),
.vcr ( woswr ),
.rst_n ( rst_n )
);
 
// north output buffer
outpbuf #(.DW(DW), .VCN(VCN), .FT(FT), .FCPD(FCPD))
NOB (
.dia ( cb2na ),
.do0 ( no0 ),
.do1 ( no1 ),
.do2 ( no2 ),
.do3 ( no3 ),
.dot ( noft ),
.dovc ( novc ),
.afc ( noca ),
.vca ( noswa ),
.di0 ( cb2n0 ),
.di1 ( cb2n1 ),
.di2 ( cb2n2 ),
.di3 ( cb2n3 ),
.dit ( cb2nt ),
.doa ( noa ),
.credit( noc ),
.vcr ( noswr ),
.rst_n ( rst_n )
);
 
// east output buffer
outpbuf #(.DW(DW), .VCN(VCN), .FT(FT), .FCPD(FCPD))
EOB (
.dia ( cb2ea ),
.do0 ( eo0 ),
.do1 ( eo1 ),
.do2 ( eo2 ),
.do3 ( eo3 ),
.dot ( eoft ),
.dovc ( eovc ),
.afc ( eoca ),
.vca ( eoswa ),
.di0 ( cb2e0 ),
.di1 ( cb2e1 ),
.di2 ( cb2e2 ),
.di3 ( cb2e3 ),
.dit ( cb2et ),
.doa ( eoa ),
.credit( eoc ),
.vcr ( eoswr ),
.rst_n ( rst_n )
);
 
// east output buffer
outpbuf #(.DW(DW), .VCN(VCN), .FT(FT), .FCPD(FCPD))
LOB (
.dia ( cb2la ),
.do0 ( lo0 ),
.do1 ( lo1 ),
.do2 ( lo2 ),
.do3 ( lo3 ),
.dot ( loft ),
.dovc ( lovc ),
.afc ( loca ),
.vca ( loswa ),
.di0 ( cb2l0 ),
.di1 ( cb2l1 ),
.di2 ( cb2l2 ),
.di3 ( cb2l3 ),
.dit ( cb2lt ),
.doa ( loa ),
.credit( loc ),
.vcr ( loswr ),
.rst_n ( rst_n )
);
 
// VC allocator
vcalloc #(.VCN(VCN))
ALLOC (
.svcra ( svcra ),
.wvcra ( wvcra ),
.nvcra ( nvcra ),
.evcra ( evcra ),
.lvcra ( lvcra ),
.sswa ( siswrt ),
.wswa ( wiswrt ),
.nswa ( niswrt ),
.eswa ( eiswrt ),
.lswa ( liswrt ),
.sosr ( soswr ),
.wosr ( woswr ),
.nosr ( noswr ),
.eosr ( eoswr ),
.losr ( loswr ),
.svcr ( svcr ),
.nvcr ( nvcr ),
.lvcr ( lvcr ),
.wvcr ( wvcr ),
.evcr ( evcr ),
.sswr ( siswr ),
.wswr ( wiswr ),
.nswr ( niswr ),
.eswr ( eiswr ),
.lswr ( liswr ),
.sosa ( soswa ),
.wosa ( woswa ),
.nosa ( noswa ),
.eosa ( eoswa ),
.losa ( loswa ),
.rst_n ( rst_n )
);
 
// crossbar
dcb_vc #(.DW(DW), .FT(FT), .VCN(VCN))
CB (
.dia ( {l2cba, e2cba, n2cba, w2cba, s2cba} ),
.do0 ( {cb2l0, cb2e0, cb2n0, cb2w0, cb2s0} ),
.do1 ( {cb2l1, cb2e1, cb2n1, cb2w1, cb2s1} ),
.do2 ( {cb2l2, cb2e2, cb2n2, cb2w2, cb2s2} ),
.do3 ( {cb2l3, cb2e3, cb2n3, cb2w3, cb2s3} ),
.dot ( {cb2lt, cb2et, cb2nt, cb2wt, cb2st} ),
.di0 ( {l2cb0, e2cb0, n2cb0, w2cb0, s2cb0} ),
.di1 ( {l2cb1, e2cb1, n2cb1, w2cb1, s2cb1} ),
.di2 ( {l2cb2, e2cb2, n2cb2, w2cb2, s2cb2} ),
.di3 ( {l2cb3, e2cb3, n2cb3, w2cb3, s2cb3} ),
.dit ( {l2cbt, e2cbt, n2cbt, w2cbt, s2cbt} ),
.srtg ( s2cbrtg ),
.nrtg ( n2cbrtg ),
.lrtg ( l2cbrtg ),
.wrtg ( w2cbrtg ),
.ertg ( e2cbrtg ),
.doa ( {cb2la, cb2ea, cb2na, cb2wa, cb2sa} )
);
endmodule // router
 
/vc/src/ddmux.v
0,0 → 1,57
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
Demux for a 1-of-n buffer stage.
History:
31/03/2010 Initial version. <wsong83@gmail.com>
02/06/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
module ddmux ( /*AUTOARG*/
// Outputs
d_in_a, d_out,
// Inputs
d_in, d_sel, d_out_a
);
parameter VCN = 2; // number of output VCs
parameter DW = 32; // data width of the input
 
input [DW-1:0] d_in;
input [VCN-1:0] d_sel;
output d_in_a;
 
output [VCN-1:0][DW-1:0] d_out;
input [VCN-1:0] d_out_a;
genvar i,j;
 
/*
generate
for (i=0; i<VCN; i++) begin: VCD
for(j=0; j<DW; j++) begin: D
c2 C (.a0(d_in[j]), .a1(d_sel[i]), .q(d_out[i][j]));
end
end
endgenerate
*/
generate
for (i=0; i<VCN; i++) begin: VCD
assign d_out[i] = d_sel[i] ? d_in : 0;
end
endgenerate
assign d_in_a = |d_out_a;
 
endmodule // ddmux
 
/vc/src/inpbuf.v
0,0 → 1,285
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
The input buffer for VC routers.
History:
01/04/2010 Initial version. <wsong83@gmail.com>
12/05/2010 Use MPxP crossbars. <wsong83@gmail.com>
17/04/2010 Remove unnecessary pipeline stages. <wsong83@gmail.com>
02/06/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
module inpbuf (/*AUTOARG*/
// Outputs
dia, cor, do0, do1, do2, do3, dot, dortg, vcr, swr,
// Inputs
di0, di1, di2, di3, dit, divc, coa, doa, vcra, swrt, addrx, addry,
rst_n
);
 
parameter DW = 32; // data width
parameter VCN = 2; // VC number
parameter DIR = 0; // 0-4 south, west, north, east, local
parameter SN = 2; // maximal output port number
parameter PD = 3; // the depth of the input buffer pipeline
parameter SCN = DW/2; // number of 1-of-4 sub-channels
parameter FT = 3; // flit type, now 3, HOF, BOF, EOF
// data IP
input [SCN-1:0] di0, di1, di2, di3;
input [FT-1:0] dit;
input [VCN-1:0] divc;
output dia;
 
// credit flow-control
output [VCN-1:0] cor;
input [VCN-1:0] coa;
 
// data to crossbar
output [VCN-1:0][SCN-1:0] do0,do1,do2,do3;
output [VCN-1:0][FT-1:0] dot;
output [VCN-1:0][SN-1:0] dortg;
input [VCN-1:0] doa;
 
// request to VC allocator
output [VCN-1:0][SN-1:0] vcr;
input [VCN-1:0] vcra;
 
// output to SW allocator
output [VCN-1:0][1:0] swr;
 
// routing guide for SW DEMUX
input [VCN-1:0][SN-1:0] swrt;
 
// local addresses
input [7:0] addrx, addry;
 
input rst_n;
 
//-----------------------------
// VC_MUX
wire ivma, rua;
wire [SCN-1:0] di0m, di1m, di2m, di3m;
wire [FT-1:0] ditm;
wire [VCN-1:0] divcm;
wire [VCN-1:0] muxa;
// VC_BUF
wire [2*PD:0][VCN-1:0][SCN-1:0] vcd0, vcd1, vcd2, vcd3; // VC data
wire [2*PD:0][VCN-1:0][FT-1:0] vcdt; // VC flit type
wire [2*PD:0][VCN-1:0][SCN-1:0] vcdad, vcdadn; // VC ack
wire [2*PD:0][VCN-1:0] vcdat, vcdatn; // VC data ack and type ack
wire [1:0][VCN-1:0] vcda; // the comman ack
 
// control path
wire [2*PD:2*PD-2][VCN-1:0][1:0] vcft; // flit type on control path
wire [2*PD:2*PD-2][VCN-1:0] vcfta, vcftan; // flit type ack, on control path
wire [VCN-1:0] vcdam; // need an extra ack internal signal
wire [VCN-1:0][SN-1:0] rtg; // routing direction guide
wire [VCN-1:0] doan;
// last stage of input buffer
wire [VCN-1:0] vcor;
wire [VCN-1:0] vcog;
wire [VCN-1:0] swa;
 
genvar gbd, gvc, gsub, i;
 
//---------------------------------------------
// the input VCDMUX
vcdmux #(.VCN(VCN), .DW(DW))
IVM (
.dia ( ivma ),
.do0 ( vcd0[0] ),
.do1 ( vcd1[0] ),
.do2 ( vcd2[0] ),
.do3 ( vcd3[0] ),
.dot ( vcdt[0] ),
.di0 ( di0m ),
.di1 ( di1m ),
.di2 ( di2m ),
.di3 ( di3m ),
.dit ( ditm ),
.divc ( divcm ),
.doa ( muxa )
);
 
//c2 IVMA (.a0(ivma), .a1(rua), .q(dia)); divc is not checked
ctree #(.DW(3)) ACKT(.ci({ivma, rua, (|divcm)}), .co(dia));
assign di0m = rst_n ? di0 : 0;
assign di1m = rst_n ? di1 : 0;
assign di2m = rst_n ? di2 : 0;
assign di3m = rst_n ? di3 : 0;
assign ditm = rst_n ? dit : 0;
assign divcm = rst_n ? divc : 0;
 
//---------------------------------------------
// the VC buffers
generate
for(gbd=0; gbd<PD*2-2; gbd++) begin:BFN
for(gvc=0; gvc<VCN; gvc++) begin:V
for(gsub=0; gsub<SCN; gsub++) begin:SC
pipe4 #(.DW(2))
DP (
.ia ( vcdad[gbd][gvc][gsub] ),
.o0 ( vcd0[gbd+1][gvc][gsub] ),
.o1 ( vcd1[gbd+1][gvc][gsub] ),
.o2 ( vcd2[gbd+1][gvc][gsub] ),
.o3 ( vcd3[gbd+1][gvc][gsub] ),
.i0 ( vcd0[gbd][gvc][gsub] ),
.i1 ( vcd1[gbd][gvc][gsub] ),
.i2 ( vcd2[gbd][gvc][gsub] ),
.i3 ( vcd3[gbd][gvc][gsub] ),
.oa ( vcdadn[gbd+1][gvc][gsub] )
);
assign vcdadn[gbd+1][gvc][gsub] = (~vcdad[gbd+1][gvc][gsub])&rst_n;
end // block: SC
pipen #(.DW(FT))
TP (
.d_in ( vcdt[gbd][gvc] ),
.d_in_a ( vcdat[gbd][gvc] ),
.d_out ( vcdt[gbd+1][gvc] ),
.d_out_a ( vcdatn[gbd+1][gvc] )
);
assign vcdatn[gbd+1][gvc] = (~vcdat[gbd+1][gvc])&rst_n;
end // block: V
end // block: BFN
 
for(gvc=0; gvc<VCN; gvc++) begin:BFNV
if(PD>1) begin:ACKG
ctree #(.DW(SCN+1)) ACKT(.ci({vcdat[0],vcdad[0]}), .co(muxa[gvc]));
assign vcdad[PD*2-2][gvc] = {SCN{vcda[0][gvc]}};
assign vcdat[PD*2-2] = vcda[0][gvc];
end else begin
assign muxa[gvc] = vcda[0][gvc];
end
end // block: V
endgenerate
 
// the last two stages of VC buffers, separate flit type and data
generate
for(gbd=PD*2-2; gbd<PD*2; gbd++) begin:BFL2
for(gvc=0; gvc<VCN; gvc++) begin:V
for(gsub=0; gsub<SCN; gsub++) begin:SC
pipe4 #(.DW(2))
DP (
.ia ( vcdad[gbd][gvc][gsub] ),
.o0 ( vcd0[gbd+1][gvc][gsub] ),
.o1 ( vcd1[gbd+1][gvc][gsub] ),
.o2 ( vcd2[gbd+1][gvc][gsub] ),
.o3 ( vcd3[gbd+1][gvc][gsub] ),
.i0 ( vcd0[gbd][gvc][gsub] ),
.i1 ( vcd1[gbd][gvc][gsub] ),
.i2 ( vcd2[gbd][gvc][gsub] ),
.i3 ( vcd3[gbd][gvc][gsub] ),
.oa ( vcdadn[gbd+1][gvc][gsub] )
);
assign vcdadn[gbd+1][gvc][gsub] = (~vcdad[gbd+1][gvc][gsub])&rst_n;
end // block: SC
pipen #(.DW(FT))
TP (
.d_in ( vcdt[gbd][gvc] ),
.d_in_a ( vcdat[gbd][gvc] ),
.d_out ( vcdt[gbd+1][gvc] ),
.d_out_a ( vcdatn[gbd+1][gvc] )
);
 
assign vcdatn[gbd+1][gvc] = (~vcdat[gbd+1][gvc])&rst_n;
 
pipen #(.DW(2))
CTP (
.d_in ( vcft[gbd][gvc] ),
.d_in_a ( vcfta[gbd][gvc] ),
.d_out ( vcft[gbd+1][gvc] ),
.d_out_a ( vcftan[gbd+1][gvc] )
);
 
assign vcftan[gbd+1][gvc] = (~vcfta[gbd+1][gvc])&rst_n;
end // block: V
end // block: BFL2
 
for(gvc=0; gvc<VCN; gvc++) begin:BFL2V
ctree #(.DW(SCN+2)) ACKT(.ci({vcfta[PD*2-2][gvc], vcdat[PD*2-2][gvc], vcdad[PD*2-2][gvc]}), .co(vcda[0][gvc]));
assign vcdat[PD*2][gvc] = vcda[1][gvc];
assign vcdad[PD*2][gvc] = {SCN{vcda[1][gvc]}};
assign vcfta[PD*2][gvc] = swa[gvc];
assign vcft[PD*2-2][gvc] = {vcdt[PD*2-2][gvc][FT-1], |vcdt[PD*2-2][gvc][FT-2:0]};
assign swr[gvc] = vcft[PD*2][gvc];
end
 
endgenerate
 
// the routing guide pipeline stage
generate
for(gvc=0; gvc<VCN; gvc++) begin:R
pipen #(.DW(SN))
RP (
.d_in ( swrt[gvc] ),
.d_in_a ( swa[gvc] ),
.d_out ( rtg[gvc] ),
.d_out_a ( (~vcda[1][gvc])&rst_n )
);
end
endgenerate
 
generate
for(gvc=0; gvc<VCN; gvc++) begin:LPS
 
// credit control
dc2 FCP (.q(cor[gvc]), .d(|rtg[gvc]), .a((~coa[gvc])&rst_n));
 
// output name conversation
assign do0[gvc] = vcd0[PD*2][gvc];
assign do1[gvc] = vcd1[PD*2][gvc];
assign do2[gvc] = vcd2[PD*2][gvc];
assign do3[gvc] = vcd3[PD*2][gvc];
 
assign dot[gvc] = vcdt[PD*2][gvc];
assign dortg[gvc] = rtg[gvc];
 
c2 AC (.q(vcda[1][gvc]), .a0(cor[gvc]), .a1(doa[gvc]));
 
end // block: LPS
endgenerate
// routing unit
rtu #(.VCN(VCN), .DIR(DIR), .SN(SN), .PD(PD))
RTC (
.dia ( rua ),
.dort ( vcr ),
.rst_n ( rst_n ),
.di0 ( di0m[3:0] ),
.di1 ( di1m[3:0] ),
.di2 ( di2m[3:0] ),
.di3 ( di3m[3:0] ),
.dit ( ditm ),
.divc ( divcm ),
.addrx ( addrx ),
.addry ( addry ),
.doa ( vcra )
);
endmodule // inpbuf
 
 
 
 
/vc/src/outpbuf.v
0,0 → 1,127
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
The output buffer for VC routers.
History:
04/04/2010 Initial version. <wsong83@gmail.com>
12/05/2010 Use MPxP crossbars. <wsong83@gmail.com>
08/05/2010 Remove unnecessary pipeline stages. <wsong83@gmail.com>
02/06/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
module outpbuf (/*AUTOARG*/
// Outputs
dia, do0, do1, do2, do3, dot, dovc, afc, vca,
// Inputs
di0, di1, di2, di3, dit, doa, credit, vcr, rst_n
);
parameter DW = 32; // data width
parameter VCN = 4; // VC number
parameter FT = 3; // flit type, now 3, HOF, BOF, EOF
parameter FCPD = 3; // the depth of the credit pipeline
parameter SCN = DW/2;
 
//data in
input [SCN-1:0] di0, di1, di2, di3;
input [FT-1:0] dit;
output dia;
 
// data out
output [SCN-1:0] do0, do1, do2, do3;
output [FT-1:0] dot;
output [VCN-1:0] dovc;
input doa;
 
// credit
input [VCN-1:0] credit;
output [VCN-1:0] afc;
 
// vc requests in
input [VCN-1:0] vcr;
output [VCN-1:0] vca;
 
// active-low reset
input rst_n;
 
//--------------------------------------------------------------
wire [VCN-1:0] vcro, vcg, vcgl, vcrm;
wire [SCN-1:0] doan, diad;
wire dian, diavc, diavcn, diat;
genvar i, gsub;
// flow control controller
fcctl #(.VCN(VCN), .PD(FCPD))
FCU (
.afc ( afc ),
.ro ( vcro ),
.credit ( credit ),
.ri ( vcr ),
.rst ( ~rst_n )
);
 
// VC arbiter
mutex_arb #(.wd(VCN)) Sch (.req(vcro), .gnt(vcg));
 
// the control logic for VC arbiter
generate
for(i=0; i<VCN; i++)begin:SCEN
c2 C (.a0(vcg[i]), .a1(diavcn), .q(vcgl[i]));
end
endgenerate
assign diavcn = (~diavc)&rst_n;
 
// output data buffer
generate
for(gsub=0; gsub<SCN; gsub++) begin:SC
pipe4 #(.DW(2))
L0D (
.ia ( diad[gsub] ),
.o0 ( do0[gsub] ),
.o1 ( do1[gsub] ),
.o2 ( do2[gsub] ),
.o3 ( do3[gsub] ),
.i0 ( di0[gsub] ),
.i1 ( di1[gsub] ),
.i2 ( di2[gsub] ),
.i3 ( di3[gsub] ),
.oa ( doan[gsub] )
);
assign doan[gsub] = (~doa)&rst_n;
end // block: SC
endgenerate
 
pipen #(.DW(FT))
L0T (
.d_in ( dit ),
.d_in_a ( diat ),
.d_out ( dot ),
.d_out_a ( (~doa)&rst_n )
);
ctree #(.DW(SCN+2)) ACKT (.ci({diavc,diat, diad}), .co(dia));
pipen #(.DW(VCN))
LSV (
.d_in ( vcgl ),
.d_in_a ( diavc ),
.d_out ( dovc ),
.d_out_a ( (~doa)&rst_n )
);
 
assign vca = dovc;
 
endmodule // outpbuf
 
 
/vc/src/vcdmux.v
0,0 → 1,71
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
Demux for a VC buffer stage.
History:
31/03/2010 Initial version. <wsong83@gmail.com>
02/06/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
module vcdmux ( /*AUTOARG*/
// Outputs
dia, do0, do1, do2, do3, dot,
// Inputs
di0, di1, di2, di3, dit, divc, doa
);
parameter VCN = 2; // number of output VCs
parameter DW = 32; // data width of the input
parameter SCN = DW/2;
 
input [SCN-1:0] di0, di1, di2, di3;
input [2:0] dit;
input [VCN-1:0] divc;
output dia;
 
output [VCN-1:0][SCN-1:0] do0, do1, do2, do3;
output [VCN-1:0][2:0] dot;
input [VCN-1:0] doa;
genvar i,j;
 
/*
generate
for (i=0; i<VCN; i++) begin: VCD
for(j=0; j<SCN; j++) begin: D
c2 C0 (.a0(di0[j]), .a1(divc[i]), .q(do0[i][j]));
c2 C1 (.a0(di1[j]), .a1(divc[i]), .q(do1[i][j]));
c2 C2 (.a0(di2[j]), .a1(divc[i]), .q(do2[i][j]));
c2 C3 (.a0(di3[j]), .a1(divc[i]), .q(do3[i][j]));
end
for(j=0; j<3; j++) begin: T
c2 C0 (.a0(dit[j]), .a1(divc[i]), .q(dot[i][j]));
end
end
endgenerate
*/
generate
for (i=0; i<VCN; i++) begin: VCD
assign do0[i] = divc[i] ? di0 : 0;
assign do1[i] = divc[i] ? di1 : 0;
assign do2[i] = divc[i] ? di2 : 0;
assign do3[i] = divc[i] ? di3 : 0;
assign dot[i] = divc[i] ? dit : 0;
end
endgenerate
 
assign dia = |doa;
 
endmodule // vcdmux
 
/vc/src/vca.v
0,0 → 1,418
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
VC allocator.
History:
05/04/2010 Initial version. <wsong83@gmail.com>
29/09/2010 Use the asynchronous PIM alg. (MNMA) <wsong83@gmail.com>
03/10/2010 Add VCREN c2n gates to defer the withdrawal of request until data switch is withdrawn. <wsong83@gmail.com>
02/06/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
// the router structure definitions
`include "define.v"
 
module vcalloc (/*AUTOARG*/
// Outputs
svcra, wvcra, nvcra, evcra, lvcra, sswa, wswa, nswa, eswa, lswa,
sosr, wosr, nosr, eosr, losr,
// Inputs
svcr, nvcr, lvcr, wvcr, evcr, sswr, wswr, nswr, eswr, lswr, sosa,
wosa, nosa, eosa, losa, rst_n
);
 
parameter VCN = 4; // number of VCs
 
input [VCN-1:0][3:0] svcr, nvcr, lvcr; // VC requests from input VCs
input [VCN-1:0][1:0] wvcr, evcr;
output [VCN-1:0] svcra,wvcra, nvcra, evcra, lvcra; // ack to VC requests
input [VCN-1:0][1:0] sswr, wswr, nswr, eswr, lswr; // SW requests from input VCs
output [VCN-1:0][3:0] sswa, nswa, lswa; // ack/routing guide to input VCs
output [VCN-1:0][1:0] wswa, eswa;
output [VCN-1:0] sosr, wosr, nosr, eosr, losr; // SW requests to output VCs
input [VCN-1:0] sosa, wosa, nosa, eosa, losa;
input rst_n; // active-low reset
wire [VCN-1:0][3:0] msvcr, mnvcr, mlvcr; // shuffled VC requests
wire [VCN-1:0][1:0] mwvcr, mevcr;
 
wire [VCN-1:0][3:0][VCN-1:0] wcfg, ecfg, lcfg; // configuration signals from VCA to Req CB
wire [VCN-1:0][1:0][VCN-1:0] scfg, ncfg;
 
wire [VCN-1:0][3:0][VCN-1:0] mwcfg, mecfg, mlcfg; // the cfg before the AND gates
wire [VCN-1:0][1:0][VCN-1:0] mscfg, mncfg;
wire [VCN-1:0][3:0][VCN-1:0] wcfga, ecfga, lcfga; // cfg ack from req CB
wire [VCN-1:0][1:0][VCN-1:0] scfga, ncfga;
`ifndef ENABLE_MRMA
wire [1:0][VCN-1:0][VCN-1:0] i2sr, i2nr; // input to output requests
wire [3:0][VCN-1:0][VCN-1:0] i2wr, i2er, i2lr;
`else
wire [1:0][VCN-1:0] i2sr, i2nr; // input to output requests
wire [3:0][VCN-1:0] i2wr, i2er, i2lr;
`endif
wire [1:0][VCN-1:0] i2sa, i2na; // ack for i2(dir)r
wire [3:0][VCN-1:0] i2wa, i2ea, i2la;
 
// other wires for shuffle purposes
wire [VCN-1:0][3:0][VCN-1:0] svcram, nvcram, lvcram;
wire [VCN-1:0][1:0][VCN-1:0] wvcram, evcram;
wire [VCN-1:0][3:0][VCN-1:0] svcrami, nvcrami, lvcrami;
wire [VCN-1:0][1:0][VCN-1:0] wvcrami, evcrami;
wire [VCN-1:0][3:0] svcrai, nvcrai, lvcrai;
wire [VCN-1:0][1:0] wvcrai, evcrai;
wire [VCN-1:0][3:0] svcraii, nvcraii, lvcraii;
wire [VCN-1:0][1:0] wvcraii, evcraii;
`ifdef ENABLE_MRMA
wire [VCN:0] vcrst_n; // the buffered resets to avoid metastability
wire [VCN-1:0] svcrdy, svcrdya; // south vc ready status
wire [VCN-1:0] wvcrdy, wvcrdya; // west vc ready status
wire [VCN-1:0] nvcrdy, nvcrdya; // north vc ready status
wire [VCN-1:0] evcrdy, evcrdya; // east vc ready status
wire [VCN-1:0] lvcrdy, lvcrdya; // local vc ready status
`endif
 
genvar i, j;
generate
for(i=0; i<VCN; i++) begin:SF
assign svcra[i] = {svcrai[i][0]|svcrai[i][1]|svcrai[i][2]|svcrai[i][3]};
assign wvcra[i] = {wvcrai[i][0]|wvcrai[i][1]};
assign nvcra[i] = {nvcrai[i][0]|nvcrai[i][1]|nvcrai[i][2]|nvcrai[i][3]};
assign evcra[i] = {evcrai[i][0]|evcrai[i][1]};
assign lvcra[i] = {lvcrai[i][0]|lvcrai[i][1]|lvcrai[i][2]|lvcrai[i][3]};
or VCRENn0( mnvcr[i][0], nvcr[i][0], (|nvcram[i][0])&rst_n);
or VCRENl0( mlvcr[i][0], lvcr[i][0], (|lvcram[i][0])&rst_n);
or VCRENs0( msvcr[i][0], svcr[i][0], (|svcram[i][0])&rst_n);
or VCRENn1( mnvcr[i][1], nvcr[i][1], (|nvcram[i][1])&rst_n);
or VCRENe0( mevcr[i][0], evcr[i][0], (|evcram[i][0])&rst_n);
or VCRENl1( mlvcr[i][1], lvcr[i][1], (|lvcram[i][1])&rst_n);
or VCRENs1( msvcr[i][1], svcr[i][1], (|svcram[i][1])&rst_n);
or VCRENl2( mlvcr[i][2], lvcr[i][2], (|lvcram[i][2])&rst_n);
or VCRENs2( msvcr[i][2], svcr[i][2], (|svcram[i][2])&rst_n);
or VCRENw0( mwvcr[i][0], wvcr[i][0], (|wvcram[i][0])&rst_n);
or VCRENn2( mnvcr[i][2], nvcr[i][2], (|nvcram[i][2])&rst_n);
or VCRENl3( mlvcr[i][3], lvcr[i][3], (|lvcram[i][3])&rst_n);
or VCRENs3( msvcr[i][3], svcr[i][3], (|svcram[i][3])&rst_n);
or VCRENw1( mwvcr[i][1], wvcr[i][1], (|wvcram[i][1])&rst_n);
or VCRENn3( mnvcr[i][3], nvcr[i][3], (|nvcram[i][3])&rst_n);
or VCRENe1( mevcr[i][1], evcr[i][1], (|evcram[i][1])&rst_n);
 
and VCAOs0 (svcrai[i][0], (|svcrami[i][0]), svcraii[i][0]);
and VCAOs1 (svcrai[i][1], (|svcrami[i][1]), svcraii[i][1]);
and VCAOs2 (svcrai[i][2], (|svcrami[i][2]), svcraii[i][2]);
and VCAOs3 (svcrai[i][3], (|svcrami[i][3]), svcraii[i][3]);
and VCAOw0 (wvcrai[i][0], (|wvcrami[i][0]), wvcraii[i][0]);
and VCAOw1 (wvcrai[i][1], (|wvcrami[i][1]), wvcraii[i][1]);
and VCAOn0 (nvcrai[i][0], (|nvcrami[i][0]), nvcraii[i][0]);
and VCAOn1 (nvcrai[i][1], (|nvcrami[i][1]), nvcraii[i][1]);
and VCAOn2 (nvcrai[i][2], (|nvcrami[i][2]), nvcraii[i][2]);
and VCAOn3 (nvcrai[i][3], (|nvcrami[i][3]), nvcraii[i][3]);
and VCAOe0 (evcrai[i][0], (|evcrami[i][0]), evcraii[i][0]);
and VCAOe1 (evcrai[i][1], (|evcrami[i][1]), evcraii[i][1]);
and VCAOl0 (lvcrai[i][0], (|lvcrami[i][0]), lvcraii[i][0]);
and VCAOl1 (lvcrai[i][1], (|lvcrami[i][1]), lvcraii[i][1]);
and VCAOl2 (lvcrai[i][2], (|lvcrami[i][2]), lvcraii[i][2]);
and VCAOl3 (lvcrai[i][3], (|lvcrami[i][3]), lvcraii[i][3]);
or VCAIs0 (svcraii[i][0], (~svcr[i][0]), (|svcram[i][0]));
or VCAIs1 (svcraii[i][1], (~svcr[i][1]), (|svcram[i][1]));
or VCAIs2 (svcraii[i][2], (~svcr[i][2]), (|svcram[i][2]));
or VCAIs3 (svcraii[i][3], (~svcr[i][3]), (|svcram[i][3]));
or VCAIw0 (wvcraii[i][0], (~wvcr[i][0]), (|wvcram[i][0]));
or VCAIw1 (wvcraii[i][1], (~wvcr[i][1]), (|wvcram[i][1]));
or VCAIn0 (nvcraii[i][0], (~nvcr[i][0]), (|nvcram[i][0]));
or VCAIn1 (nvcraii[i][1], (~nvcr[i][1]), (|nvcram[i][1]));
or VCAIn2 (nvcraii[i][2], (~nvcr[i][2]), (|nvcram[i][2]));
or VCAIn3 (nvcraii[i][3], (~nvcr[i][3]), (|nvcram[i][3]));
or VCAIe0 (evcraii[i][0], (~evcr[i][0]), (|evcram[i][0]));
or VCAIe1 (evcraii[i][1], (~evcr[i][1]), (|evcram[i][1]));
or VCAIl0 (lvcraii[i][0], (~lvcr[i][0]), (|lvcram[i][0]));
or VCAIl1 (lvcraii[i][1], (~lvcr[i][1]), (|lvcram[i][1]));
or VCAIl2 (lvcraii[i][2], (~lvcr[i][2]), (|lvcram[i][2]));
or VCAIl3 (lvcraii[i][3], (~lvcr[i][3]), (|lvcram[i][3]));
`ifdef ENABLE_MRMA
assign i2sr[0][i] = mnvcr[i][0];
assign i2sr[1][i] = mlvcr[i][0];
assign i2wr[0][i] = msvcr[i][0];
assign i2wr[1][i] = mnvcr[i][1];
assign i2wr[2][i] = mevcr[i][0];
assign i2wr[3][i] = mlvcr[i][1];
assign i2nr[0][i] = msvcr[i][1];
assign i2nr[1][i] = mlvcr[i][2];
assign i2er[0][i] = msvcr[i][2];
assign i2er[1][i] = mwvcr[i][0];
assign i2er[2][i] = mnvcr[i][2];
assign i2er[3][i] = mlvcr[i][3];
assign i2lr[0][i] = msvcr[i][3];
assign i2lr[1][i] = mwvcr[i][1];
assign i2lr[2][i] = mnvcr[i][3];
assign i2lr[3][i] = mevcr[i][1];
`endif // `ifndef ENABLE_MRMA
 
for(j=0; j<VCN; j++) begin : CO
`ifndef ENABLE_MRMA
assign i2sr[0][i][j] = mnvcr[i][0];
assign i2sr[1][i][j] = mlvcr[i][0];
assign i2wr[0][i][j] = msvcr[i][0];
assign i2wr[1][i][j] = mnvcr[i][1];
assign i2wr[2][i][j] = mevcr[i][0];
assign i2wr[3][i][j] = mlvcr[i][1];
assign i2nr[0][i][j] = msvcr[i][1];
assign i2nr[1][i][j] = mlvcr[i][2];
assign i2er[0][i][j] = msvcr[i][2];
assign i2er[1][i][j] = mwvcr[i][0];
assign i2er[2][i][j] = mnvcr[i][2];
assign i2er[3][i][j] = mlvcr[i][3];
assign i2lr[0][i][j] = msvcr[i][3];
assign i2lr[1][i][j] = mwvcr[i][1];
assign i2lr[2][i][j] = mnvcr[i][3];
assign i2lr[3][i][j] = mevcr[i][1];
`endif // `ifndef ENABLE_MRMA
assign svcram[i][0][j] = wcfga[j][0][i];
assign svcram[i][1][j] = ncfga[j][0][i];
assign svcram[i][2][j] = ecfga[j][0][i];
assign svcram[i][3][j] = lcfga[j][0][i];
assign wvcram[i][0][j] = ecfga[j][1][i];
assign wvcram[i][1][j] = lcfga[j][1][i];
assign nvcram[i][0][j] = scfga[j][0][i];
assign nvcram[i][1][j] = wcfga[j][1][i];
assign nvcram[i][2][j] = ecfga[j][2][i];
assign nvcram[i][3][j] = lcfga[j][2][i];
assign evcram[i][0][j] = wcfga[j][2][i];
assign evcram[i][1][j] = lcfga[j][3][i];
assign lvcram[i][0][j] = scfga[j][1][i];
assign lvcram[i][1][j] = wcfga[j][3][i];
assign lvcram[i][2][j] = ncfga[j][1][i];
assign lvcram[i][3][j] = ecfga[j][3][i];
 
assign svcrami[i][0][j] = mwcfg[j][0][i];
assign svcrami[i][1][j] = mncfg[j][0][i];
assign svcrami[i][2][j] = mecfg[j][0][i];
assign svcrami[i][3][j] = mlcfg[j][0][i];
assign wvcrami[i][0][j] = mecfg[j][1][i];
assign wvcrami[i][1][j] = mlcfg[j][1][i];
assign nvcrami[i][0][j] = mscfg[j][0][i];
assign nvcrami[i][1][j] = mwcfg[j][1][i];
assign nvcrami[i][2][j] = mecfg[j][2][i];
assign nvcrami[i][3][j] = mlcfg[j][2][i];
assign evcrami[i][0][j] = mwcfg[j][2][i];
assign evcrami[i][1][j] = mlcfg[j][3][i];
assign lvcrami[i][0][j] = mscfg[j][1][i];
assign lvcrami[i][1][j] = mwcfg[j][3][i];
assign lvcrami[i][2][j] = mncfg[j][1][i];
assign lvcrami[i][3][j] = mecfg[j][3][i];
 
and CFGENw0 (wcfg[j][0][i], svcr[i][0], mwcfg[j][0][i]);
and CFGENn0 (ncfg[j][0][i], svcr[i][1], mncfg[j][0][i]);
and CFGENe0 (ecfg[j][0][i], svcr[i][2], mecfg[j][0][i]);
and CFGENl0 (lcfg[j][0][i], svcr[i][3], mlcfg[j][0][i]);
and CFGENe1 (ecfg[j][1][i], wvcr[i][0], mecfg[j][1][i]);
and CFGENl1 (lcfg[j][1][i], wvcr[i][1], mlcfg[j][1][i]);
and CFGENs0 (scfg[j][0][i], nvcr[i][0], mscfg[j][0][i]);
and CFGENw1 (wcfg[j][1][i], nvcr[i][1], mwcfg[j][1][i]);
and CFGENe2 (ecfg[j][2][i], nvcr[i][2], mecfg[j][2][i]);
and CFGENl2 (lcfg[j][2][i], nvcr[i][3], mlcfg[j][2][i]);
and CFGENw2 (wcfg[j][2][i], evcr[i][0], mwcfg[j][2][i]);
and CFGENl3 (lcfg[j][3][i], evcr[i][1], mlcfg[j][3][i]);
and CFGENs1 (scfg[j][1][i], lvcr[i][0], mscfg[j][1][i]);
and CFGENw3 (wcfg[j][3][i], lvcr[i][1], mwcfg[j][3][i]);
and CFGENn1 (ncfg[j][1][i], lvcr[i][2], mncfg[j][1][i]);
and CFGENe3 (ecfg[j][3][i], lvcr[i][3], mecfg[j][3][i]);
end // block: CO
end // block: SF
endgenerate
// the requests crossbar
rcb_vc #(.VCN(VCN))
RSW (
.ro ( {losr, eosr, nosr, wosr, sosr} ),
.srt ( sswa ),
.wrt ( wswa ),
.nrt ( nswa ),
.ert ( eswa ),
.lrt ( lswa ),
.ri ( {lswr, eswr, nswr, wswr, sswr} ),
.go ( {losa, eosa, nosa, wosa, sosa} ),
.wctl ( wcfg ),
.ectl ( ecfg ),
.lctl ( lcfg ),
.sctl ( scfg ),
.nctl ( ncfg ),
.wctla ( wcfga ),
.ectla ( ecfga ),
.lctla ( lcfga ),
.sctla ( scfga ),
.nctla ( ncfga )
);
 
// the VC allocators
`ifndef ENABLE_MRMA
mnma #(.N(2*VCN), .M(VCN))
SVA (
.r ( i2sr ),
.cfg ( mscfg ),
.ra ( )
);
 
mnma #(.N(4*VCN), .M(VCN))
WVA (
.r ( i2wr ),
.cfg ( mwcfg ),
.ra ( )
);
mnma #(.N(2*VCN), .M(VCN))
NVA (
.r ( i2nr ),
.cfg ( mncfg ),
.ra ( )
);
 
mnma #(.N(4*VCN), .M(VCN))
EVA (
.r ( i2er ),
.cfg ( mecfg ),
.ra ( )
);
 
mnma #(.N(4*VCN), .M(VCN))
LVA (
.r ( i2lr ),
.cfg ( mlcfg ),
.ra ( )
);
`else // !`ifndef ENABLE_MRMA
mrma #(.N(2*VCN), .M(VCN))
SVA (
.c ( i2sr ),
.cfg ( mscfg ),
.ca ( ),
.r ( svcrdy ),
.ra ( svcrdya ),
.rst_n ( rst_n )
);
 
mrma #(.N(4*VCN), .M(VCN))
WVA (
.c ( i2wr ),
.cfg ( mwcfg ),
.ca ( ),
.r ( wvcrdy ),
.ra ( wvcrdya ),
.rst_n ( rst_n )
);
mrma #(.N(2*VCN), .M(VCN))
NVA (
.c ( i2nr ),
.cfg ( mncfg ),
.ca ( ),
.r ( nvcrdy ),
.ra ( nvcrdya ),
.rst_n ( rst_n )
);
 
mrma #(.N(4*VCN), .M(VCN))
EVA (
.c ( i2er ),
.cfg ( mecfg ),
.ca ( ),
.r ( evcrdy ),
.ra ( evcrdya ),
.rst_n ( rst_n )
);
 
mrma #(.N(4*VCN), .M(VCN))
LVA (
.c ( i2lr ),
.cfg ( mlcfg ),
.ca ( ),
.r ( lvcrdy ),
.ra ( lvcrdya ),
.rst_n ( rst_n )
);
 
generate
for(i=0; i<VCN; i++) begin: OPC
delay DLY ( .q(vcrst_n[i+1]), .a(vcrst_n[i])); // dont touch
assign svcrdy[i] = (~svcrdya[i])&vcrst_n[i+1];
assign wvcrdy[i] = (~wvcrdya[i])&vcrst_n[i+1];
assign nvcrdy[i] = (~nvcrdya[i])&vcrst_n[i+1];
assign evcrdy[i] = (~evcrdya[i])&vcrst_n[i+1];
assign lvcrdy[i] = (~lvcrdya[i])&vcrst_n[i+1];
end
endgenerate
 
assign vcrst_n[0] = rst_n;
 
`endif // !`ifndef ENABLE_MRMA
endmodule // vcalloc
 
/* logic of the control logic generated from petrify
 
// Verilog model for vca_ctl
// Generated by petrify 4.2 (compiled 15-Oct-03 at 3:06 PM)
// CPU time for synthesis (host <unknown>): 0.04 seconds
// Estimated area = 72.00
 
// The circuit is self-resetting and does not need reset pin.
 
module vca_ctl_net (
vcri,
cfg,
vcrai,
vcro,
cfgen,
vcrao
);
 
input vcri;
input cfg;
input vcrai;
 
output vcro;
output cfgen;
output vcrao;
 
 
// Functions not mapped into library gates:
// ----------------------------------------
 
// Equation: vcro = vcri + vcrai
or _U0 (vcro, vcrai, vcri);
 
// Equation: cfgen = vcri
buf _U1 (cfgen, vcri);
 
// Equation: vcrao = cfg (vcri' + vcrai)
not _U1 (_X1, vcri);
and _U2 (_X0, vcrai, cfg);
and _U3 (_X2, cfg, _X1);
or _U4 (vcrao, _X0, _X2);
 
 
// signal values at the initial state:
// !vcri !cfg !vcrai !vcro !cfgen !vcrao
endmodule
*/
vc/src/vca.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: vc/src/rtu.v =================================================================== --- vc/src/rtu.v (nonexistent) +++ vc/src/rtu.v (revision 47) @@ -0,0 +1,187 @@ +/* + Asynchronous SDM NoC + (C)2011 Wei Song + Advanced Processor Technologies Group + Computer Science, the Univ. of Manchester, UK + + Authors: + Wei Song wsong83@gmail.com + + License: LGPL 3.0 or later + + The routing calculation unit in every input buffer. + p0 -> L -> p1 -> RTC -> p2 -> L -> p3 -> DEMUX -> p[0] -> L -> p[1] -> L -> p[2] -> L -> p[3] -> L -> p[4] + + History: + 02/04/2010 Initial version. + 02/06/2011 Clean up for opensource. + 08/06/2011 The selection pin of the demux must be considered in the ack process. + +*/ + +module rtu (/*AUTOARG*/ + // Outputs + dia, dort, + // Inputs + rst_n, di0, di1, di2, di3, dit, divc, addrx, addry, doa + ); + parameter VCN = 2; + parameter DIR = 0; + parameter SN = 4; + parameter PD = 2; + + input rst_n; + input [3:0] di0, di1, di2, di3; + input [2:0] dit; + input [VCN-1:0] divc; + output dia; + + input [7:0] addrx, addry; + + output [VCN-1:0][SN-1:0] dort; + input [VCN-1:0] doa; + + //------------------------------------------ + wire p0an, p0ap, p0den, p0ad, p0avc; + wire [3:0] p1d0, p1d1, p1d2, p1d3; + wire [VCN-1:0] p1vc; + wire p1a, p1ad, p1avc, p1an; + wire [SN-1:0] p2d; + wire [VCN-1:0] p2vc; + wire p2a, p2ad, p2avc, p2an; + wire [SN-1:0] p3d; + wire [VCN-1:0] p3vc; + wire p3a, p3an, p3ad; + wire [PD*2:0][VCN-1:0][SN-1:0] pd; + wire [PD*2:0][VCN-1:0] pda, pdan; + + wire [2:0] x_cmp [1:0]; + wire [2:0] y_cmp [1:0]; + wire [5:0] dec; + wire ds, dw, dn, de, dl; + + + genvar gvc, gbd, i; + + //------------------------------------------ + // p0 -> L -> p1 + + c2 CP0DE ( .a0(dit[0]), .a1(p1an), .q(p0den)); + c2 CP0A ( .a0(p0ad), .a1(p0avc), .q(p0ap)); + assign p0an = |dit[2:1]; + assign dia = p0an | p0ap; + + pipe4 #(.DW(8)) + L0D ( + .ia ( p0ad ), + .o0 ( p1d0 ), + .o1 ( p1d1 ), + .o2 ( p1d2 ), + .o3 ( p1d3 ), + .i0 ( di0 ), + .i1 ( di1 ), + .i2 ( di2 ), + .i3 ( di3 ), + .oa ( p0den ) + ); + + pipen #(.DW(VCN)) + L0V ( + .d_in ( divc ), + .d_in_a ( p0avc ), + .d_out ( p1vc ), + .d_out_a ( p0den ) + ); + + // p1 -> RTC -> p2 + comp4 X0 ( .a({p1d3[0], p1d2[0], p1d1[0], p1d0[0]}), .b(addrx[3:0]), .q(x_cmp[0])); + comp4 X1 ( .a({p1d3[1], p1d2[1], p1d1[1], p1d0[1]}), .b(addrx[7:4]), .q(x_cmp[1])); + comp4 Y0 ( .a({p1d3[2], p1d2[2], p1d1[2], p1d0[2]}), .b(addry[3:0]), .q(y_cmp[0])); + comp4 Y1 ( .a({p1d3[3], p1d2[3], p1d1[3], p1d0[3]}), .b(addry[7:4]), .q(y_cmp[1])); + + assign dec[0] = x_cmp[1][0] | (x_cmp[1][2]&x_cmp[0][0]); // frame x > addr x + assign dec[1] = x_cmp[1][1] | (x_cmp[1][2]&x_cmp[0][1]); // frame x < addr x + assign dec[2] = x_cmp[1][2] & x_cmp[0][2]; // frame x = addr x + assign dec[3] = y_cmp[1][0] | (y_cmp[1][2]&y_cmp[0][0]); // frame y > addr y + assign dec[4] = y_cmp[1][1] | (y_cmp[1][2]&y_cmp[0][1]); // frame y < addr y + assign dec[5] = y_cmp[1][2] & y_cmp[0][2]; // frame y = addr y + + assign ds = dec[0]; + assign dw = dec[2]&dec[4]; + assign dn = dec[1]; + assign de = dec[2]&dec[3]; + assign dl = dec[2]&dec[5]; + + assign p2d = + DIR == 0 ? {dl, de, dn, dw} : // south port + DIR == 1 ? {dl, de} : // west port + DIR == 2 ? {dl, de, dw, ds} : // north port + DIR == 3 ? {dl, dw} : // east port + {de, dn, dw, ds} ; // local port + + assign p2vc = p1vc; + assign p1an = p2an; + + // p2 -> L -> p3 + + c2 CP2A ( .a0(p2ad), .a1(p2avc), .q(p2a)); + assign p2an = (~p2a) & rst_n; + + pipen #(.DW(SN)) + L2R ( + .d_in ( p2d ), + .d_in_a ( p2ad ), + .d_out ( p3d ), + .d_out_a ( p3an ) + ); + + pipen #(.DW(VCN)) + L2V ( + .d_in ( p2vc ), + .d_in_a ( p2avc ), + .d_out ( p3vc ), + .d_out_a ( p3an ) + ); + + // p3 -> DEMUX -> pd[0] + ddmux #(.DW(SN), .VCN(VCN)) + RTDM ( + .d_in_a ( p3ad ), + .d_out ( pd[0] ), + .d_in ( p3d ), + .d_sel ( p3vc ), + .d_out_a ( pda[0]) + ); + + c2 CP3A (.q(p3a), .a0(p3ad), .a1(|p3vc)); + assign p3an = (~p3a) & rst_n; + + // pd pipeline + generate + for(gbd=0; gbd +# + +# make sure the LDVHOME environment is ready for NC-Simulator, IUS/LDV, Cadence +export NCSC_GCC=${LDVHOME}/tools/systemc/gcc/bin/g++ + +CXXFLAG="-c -g -Wall -I../../common/tb -I../tb -I../" + +# remove the files from last run +rm -fr INCA_libs +rm *.o +rm *.so + +# compile verilog files +# cell library +ncvlog -nowarn RECOMP ../../lib/NangateOpenCellLibrary_typical_conditional.v +# synthesized design +ncvlog ../syn/file/router_syn.v +# other verilog test bench files +ncvlog -incdir ../ ../../common/tb/anaproc.v +ncvlog -sv -incdir ../ ../tb/rtwrapper.v +ncvlog -incdir ../ ../tb/netnode.v +ncvlog -sv -incdir ../ ../tb/noc_top.v +ncvlog -sv -incdir ../ ../tb/node_top.v +ncvlog ../tb/noctb.v + +#compile SystemC files +ncsc -compiler $NCSC_GCC -cflags "${CXXFLAG}" ../../common/tb/sim_ana.cpp +ncsc -compiler $NCSC_GCC -cflags "${CXXFLAG}" ../../common/tb/anaproc.cpp +ncsc -compiler $NCSC_GCC -cflags "${CXXFLAG}" ../tb/netnode.cpp +ncsc -compiler $NCSC_GCC -cflags "${CXXFLAG}" ../tb/ni.cpp +ncsc -compiler $NCSC_GCC -cflags "${CXXFLAG}" ../tb/rtdriver.cpp + +# build the run time link library +${NCSC_GCC} -Wl -shared -o sysc.so -L${CDS_LNX86_ROOT}/ldv_2009_sc/tools/lib \ + sim_ana.o anaproc.o netnode.o ni.o rtdriver.o \ + ${CDS_LNX86_ROOT}/ldv_2009_sc/tools/systemc/lib/gnu/libncscCoSim_sh.so \ + ${CDS_LNX86_ROOT}/ldv_2009_sc/tools/systemc/lib/gnu/libncscCoroutines_sh.so \ + ${CDS_LNX86_ROOT}/ldv_2009_sc/tools/systemc/lib/gnu/libsystemc_sh.so + +# elaborate the simulation +ncelab -timescale 1ns/1ps -access +rwc -loadsc sysc.so worklib.noctb +
vc/sim/compile.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: vc/syn/script/source.tcl =================================================================== --- vc/syn/script/source.tcl (nonexistent) +++ vc/syn/script/source.tcl (revision 47) @@ -0,0 +1,38 @@ +# Asynchronous SDM NoC +# (C)2011 Wei Song +# Advanced Processor Technologies Group +# Computer Science, the Univ. of Manchester, UK +# +# Authors: +# Wei Song wsong83@gmail.com +# +# License: LGPL 3.0 or later +# +# Source files for the VC routers +# +# History: +# 02/06/2011 Initial version. + +# the common verilog source files between VC and SDM +analyze -format verilog ../../common/src/cell_lib.v +analyze -format verilog ../../common/src/ctree.v +analyze -format sverilog ../../common/src/mnma.v +analyze -format sverilog ../../common/src/mrma.v +analyze -format verilog ../../common/src/mutex_arb.v +analyze -format sverilog ../../common/src/pipe4.v +analyze -format sverilog ../../common/src/pipen.v +analyze -format verilog ../../common/src/tree_arb.v +analyze -format verilog ../../common/src/comp4.v + +# the private code of wormhole/SDM routers +analyze -format sverilog ../src/cpipe.v +analyze -format sverilog ../src/dcb_vc.v +analyze -format sverilog ../src/ddmux.v +analyze -format sverilog ../src/inpbuf.v +analyze -format sverilog ../src/outpbuf.v +analyze -format sverilog ../src/router.v +analyze -format sverilog ../src/fcctl.v +analyze -format sverilog ../src/rcb_vc.v +analyze -format sverilog ../src/rtu.v +analyze -format sverilog ../src/vca.v +analyze -format sverilog ../src/vcdmux.v Index: vc/syn/script/constraint.tcl =================================================================== --- vc/syn/script/constraint.tcl (nonexistent) +++ vc/syn/script/constraint.tcl (revision 47) @@ -0,0 +1,77 @@ +# Asynchronous SDM NoC +# (C)2011 Wei Song +# Advanced Processor Technologies Group +# Computer Science, the Univ. of Manchester, UK +# +# Authors: +# Wei Song wsong83@gmail.com +# +# License: LGPL 3.0 or later +# +# Constraints for wormhole/SDM routers +# +# History: +# 26/05/2011 Initial version. + +# loading the baic cell constraints +source ../../common/script/cell_constraint.tcl + +# ensure the basic blocks are not ungrouped for better debugging capability +set_ungroup [get_references -hierarchical inp_buf*] false +set_ungroup [get_references -hierarchical outp_buf*] false +set_ungroup CB false +set_ungroup ALLOC false + + +######### break the timing loops in the design ############## + +# the cross points in the VCA +foreach_in_collection celln [get_references -hierarchical RCBB_*] { + set_disable_timing [get_object_name $celln]/I1 -from B -to Z + set_disable_timing [get_object_name $celln]/I0/U1 -from B -to Z + set_disable_timing [get_object_name $celln]/I0/U3 -from A -to Z + set_disable_timing [get_object_name $celln]/I3/U1 -from A -to Z + set_disable_timing [get_object_name $celln]/I3/U2 -from A -to Z + +} + +set_disable_timing [get_cells ALLOC/*VCAO*] -from A -to Z + +# set some timing path ending points +set DPD [] +set DPA [] +foreach_in_collection celln [get_references -hierarchical dc2_*] { + append_to_collection DPD [ get_pins [get_object_name $celln]/U1/B] + append_to_collection DPD [ get_pins [get_object_name $celln]/U2/A] + append_to_collection DPA [ get_pins [get_object_name $celln]/U1/A] + append_to_collection DPA [ get_pins [get_object_name $celln]/U3/A] +} + +set IODI [filter [get_ports *i*] "@port_direction == in"] +set IODO [filter [get_ports *o*] "@port_direction == out"] +set IOAI [filter [get_ports *i*] "@port_direction == out"] +set IOAO [filter [get_ports *o*] "@port_direction == in"] + +# set the timing constraints for data paths and ack paths +# For better speed performance, please tune these delay and factors according different cell libraries +set DATA_dly 1.0 +set ACK_dly 1.6 + +set_max_delay [expr ${DATA_dly} * 1.00] -from ${DPA} -to ${DPD} -group G_DATA +set_max_delay [expr ${ACK_dly} * 1.00] -from ${DPA} -to ${DPA} -group G_ACK +set_max_delay [expr ${DATA_dly} * 0.30] -from ${IODI} -to ${DPD} -group G_DATA +set_max_delay [expr ${ACK_dly} * 0.75] -from ${DPA} -to ${IOAI} -group G_ACK +set_max_delay [expr ${DATA_dly} * 0.70] -from ${DPA} -to ${IODO} -group G_DATA +set_max_delay [expr ${ACK_dly} * 0.25] -from ${IOAO} -to ${DPA} -group G_ACK + +group_path -weight 1.5 -critical_range 40 -name G_DATA +group_path -weight 1.5 -critical_range 40 -name G_ACK + +set_critical_range 20 ${current_design} + +set_max_leakage_power 0.0 +set_max_dynamic_power 0.0 +set_max_area 0 + +# timing path disabled by user constraints +suppress_message TIM-175 Index: vc/syn/script/cleanup.tcl =================================================================== --- vc/syn/script/cleanup.tcl (nonexistent) +++ vc/syn/script/cleanup.tcl (revision 47) @@ -0,0 +1,4 @@ +rm * +rm -fr work +rm -fr file + Index: vc/syn/script/compile.tcl =================================================================== --- vc/syn/script/compile.tcl (nonexistent) +++ vc/syn/script/compile.tcl (revision 47) @@ -0,0 +1,67 @@ +# Asynchronous SDM NoC +# (C)2011 Wei Song +# Advanced Processor Technologies Group +# Computer Science, the Univ. of Manchester, UK +# +# Authors: +# Wei Song wsong83@gmail.com +# +# License: LGPL 3.0 or later +# +# Synthesis script +# currently using the Nangate 45nm cell lib. +# +# History: +# 31/05/2009 Initial version. + +set rm_top router +set rm_para "VCN=>2, DW=>8, PD=>1" + +# working directory +if {[file exists work ] && [file isdirectory work ]} { + file delete -force work +} +file mkdir work +define_design_lib work -path work + +if {![file exists file ]} { + file mkdir file +} + +# set the technology libraries +source ../../common/script/tech.tcl + +# read in source codes +source script/source.tcl + +# elaborate the design +elaborate ${rm_top} -parameters ${rm_para} +rename_design ${current_design} router + +link + +check_design + +# read in constraints +echo "It will be many errors in this step. Normally they are fine. For further info. please read the comments in the constraint scripts." +source script/constraint.tcl + +link + +#report loops +report_timing -loops -max_paths 2 + +compile -boundary_optimization + + +define_name_rules verilog -allowed "A-Za-z0-9_" -first_restricted "\\" +change_name -rules verilog -hierarchy + +write -format verilog -hierarchy -out file/${current_design}_syn.v $current_design +write_sdf -significant_digits 5 file/${current_design}.sdf + +report_constraints -verbose + +report_constraints +report_area +exit Index: vc/define.v =================================================================== --- vc/define.v (revision 37) +++ vc/define.v (revision 47) @@ -13,8 +13,9 @@ History: 20/09/2009 Initial version. - 23/05/2011 Clean up for opensource. + 05/06/2011 Clean up for opensource. */ -// currently VC router does not have any configurable structure variables +// Whether use the MRMA instead of MNMA allocators in the VC allocator +// `define ENABLE_MRMA
/.
. Property changes : Modified: svn:mergeinfo ## -0,0 +0,1 ## Merged /async_sdm_noc/branches/init:r37-46

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