OpenCores
URL https://opencores.org/ocsvn/atlas_core/atlas_core/trunk

Subversion Repositories atlas_core

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /atlas_core/trunk
    from Rev 35 to Rev 36
    ↔ Reverse comparison
  •

Rev 35 → Rev 36

/rtl/BOOT_MEM.vhd
18,14 → 18,14
entity boot_mem is
port (
-- host interface --
clk_i : in std_logic; -- global clock line
i_adr_i : in std_logic_vector(15 downto 0); -- instruction adr
i_dat_o : out std_logic_vector(15 downto 0); -- instruction out
d_en_i : in std_logic; -- access enable
d_rw_i : in std_logic; -- read/write
d_adr_i : in std_logic_vector(15 downto 0); -- data adr
d_dat_i : in std_logic_vector(15 downto 0); -- data in
d_dat_o : out std_logic_vector(15 downto 0) -- data out
clk_i : in std_ulogic; -- global clock line
i_adr_i : in std_ulogic_vector(15 downto 0); -- instruction adr
i_dat_o : out std_ulogic_vector(15 downto 0); -- instruction out
d_en_i : in std_ulogic; -- access enable
d_rw_i : in std_ulogic; -- read/write
d_adr_i : in std_ulogic_vector(15 downto 0); -- data adr
d_dat_i : in std_ulogic_vector(15 downto 0); -- data in
d_dat_o : out std_ulogic_vector(15 downto 0) -- data out
);
end boot_mem;
 
36,7 → 36,7
constant log2_mem_size_c : natural := log2(mem_size_c/2); -- address width (word boundary!)
 
-- memory type --
type mem_file_t is array (0 to (mem_size_c/2)-1) of std_logic_vector(15 downto 0); -- word mem!
type mem_file_t is array (0 to (mem_size_c/2)-1) of std_ulogic_vector(15 downto 0); -- word mem!
 
-- memory image (bootloader program) --
------------------------------------------------------
/rtl/CTRL.vhd
22,39 → 22,39
-- ## Global Control ##
-- ###############################################################################################
 
clk_i : in std_logic; -- global clock line
ce_i : in std_logic; -- clock enable
rst_i : in std_logic; -- global reset line, sync, high-active
clk_i : in std_ulogic; -- global clock line
ce_i : in std_ulogic; -- clock enable
rst_i : in std_ulogic; -- global reset line, sync, high-active
 
-- ###############################################################################################
-- ## Decoder Interface ##
-- ###############################################################################################
 
op_dec_ctrl_i : in std_logic_vector(ctrl_width_c-1 downto 0); -- decoder ctrl lines
multi_cyc_o : out std_logic; -- multi-cycle indicator
multi_cyc_req_i : in std_logic; -- multi-cycle request
instr_i : in std_logic_vector(data_width_c-1 downto 0); -- instruction input
instr_reg_o : out std_logic_vector(data_width_c-1 downto 0); -- instruction register
op_dec_ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- decoder ctrl lines
multi_cyc_o : out std_ulogic; -- multi-cycle indicator
multi_cyc_req_i : in std_ulogic; -- multi-cycle request
instr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- instruction input
instr_reg_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction register
 
-- ###############################################################################################
-- ## Control Lines ##
-- ###############################################################################################
 
of_ctrl_bus_o : out std_logic_vector(ctrl_width_c-1 downto 0); -- of stage control
ex_ctrl_bus_o : out std_logic_vector(ctrl_width_c-1 downto 0); -- ex stage control
ma_ctrl_bus_o : out std_logic_vector(ctrl_width_c-1 downto 0); -- ma stage control
wb_ctrl_bus_o : out std_logic_vector(ctrl_width_c-1 downto 0); -- wb stage control
of_ctrl_bus_o : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- of stage control
ex_ctrl_bus_o : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- ex stage control
ma_ctrl_bus_o : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- ma stage control
wb_ctrl_bus_o : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- wb stage control
 
-- ###############################################################################################
-- ## Function Control ##
-- ###############################################################################################
 
cond_true_i : in std_logic; -- condition is true
valid_branch_i : in std_logic; -- valid branch detected
exc_taken_i : in std_logic; -- exception taken
wake_up_i : in std_logic; -- wake up from sleep
exc_pos_o : out std_logic; -- exception would be possible
stop_pc_o : out std_logic -- freeze program counter
cond_true_i : in std_ulogic; -- condition is true
valid_branch_i : in std_ulogic; -- valid branch detected
exc_taken_i : in std_ulogic; -- exception taken
wake_up_i : in std_ulogic; -- wake up from sleep
exc_pos_o : out std_ulogic; -- exception would be possible
stop_pc_o : out std_ulogic -- freeze program counter
);
end ctrl;
 
61,34 → 61,27
architecture ctrl_structure of ctrl is
 
-- pipeline register --
signal ex_ctrl_ff : std_logic_vector(ctrl_width_c-1 downto 0);
signal ex_ctrl_buf : std_logic_vector(ctrl_width_c-1 downto 0);
signal ma_ctrl_ff : std_logic_vector(ctrl_width_c-1 downto 0);
signal wb_ctrl_ff : std_logic_vector(ctrl_width_c-1 downto 0);
signal ex_ctrl_ff : std_ulogic_vector(ctrl_width_c-1 downto 0);
signal ex_ctrl_buf : std_ulogic_vector(ctrl_width_c-1 downto 0);
signal ma_ctrl_ff : std_ulogic_vector(ctrl_width_c-1 downto 0);
signal wb_ctrl_ff : std_ulogic_vector(ctrl_width_c-1 downto 0);
 
-- branch arbiter --
signal dis_cycle_ff : std_logic;
signal dis_cycle : std_logic;
signal dis_cycle_ff : std_ulogic;
signal dis_cycle : std_ulogic;
 
-- instruction fetch arbiter --
signal dis_if : std_logic;
signal mem_dependecy : std_logic;
signal multi_cyc_ff : std_logic;
signal ir_backup_reg : std_logic_vector(data_width_c-1 downto 0);
signal ir_backup_ctrl : std_logic;
signal dis_if : std_ulogic;
signal mem_dependecy : std_ulogic;
signal multi_cyc_ff : std_ulogic;
signal ir_backup_reg : std_ulogic_vector(data_width_c-1 downto 0);
signal ir_backup_ctrl : std_ulogic;
 
-- system enable/start-up control --
signal sys_enable : std_logic;
signal start_ff : std_logic;
signal sleep_flag : std_logic;
signal sys_enable : std_ulogic;
signal start_ff : std_ulogic;
signal sleep_flag : std_ulogic;
 
-- ex lddd --
-- signal ex_a_ma_fwd : std_logic;
-- signal ex_a_wb_fwd : std_logic;
-- signal ex_b_ma_fwd : std_logic;
-- signal ex_b_wb_fwd : std_logic;
-- signal ex_c_wb_fwd : std_logic;
 
begin
 
-- System Enable-FF ------------------------------------------------------------------------------------
114,7 → 107,6
sys_enable <= (not sleep_flag) and start_ff;
 
 
 
-- Stage 0: Pipeline Flow Arbiter ----------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
flow_arbiter: process(clk_i)
141,7 → 133,7
-- temporal data dependency detector for memory-load operations --
---------------------------------------------------------------------
t_ddd: process(op_dec_ctrl_i, ex_ctrl_ff)
variable a_match_v, b_match_v : std_logic;
variable a_match_v, b_match_v : std_ulogic;
begin
-- operand a dependency? --
a_match_v := '0';
196,21 → 188,11
instr_reg_o <= instr_i when (ir_backup_ctrl = '0') else ir_backup_reg;
 
 
 
-- stage 1: operand fetch ------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
of_ctrl_bus_o <= op_dec_ctrl_i;
 
 
-- -- local data dependency detector for ex stage (pre-processed in of-stage) --
-- ex_a_ma_fwd <= '1' when ((op_dec_ctrl_i(ctrl_ra_3_c downto ctrl_ra_0_c) = ex_ctrl_buf(ctrl_rd_3_c downto ctrl_rd_0_c)) and (op_dec_ctrl_i(ctrl_ra_is_pc_c) = '0')) else '0';
-- ex_a_wb_fwd <= '1' when ((op_dec_ctrl_i(ctrl_ra_3_c downto ctrl_ra_0_c) = ma_ctrl_ff(ctrl_rd_3_c downto ctrl_rd_0_c)) and (op_dec_ctrl_i(ctrl_ra_is_pc_c) = '0')) else '0';
-- ex_b_ma_fwd <= '1' when ((op_dec_ctrl_i(ctrl_rb_3_c downto ctrl_rb_0_c) = ex_ctrl_buf(ctrl_rd_3_c downto ctrl_rd_0_c)) and (op_dec_ctrl_i(ctrl_rb_is_imm_c) = '0')) else '0';
-- ex_b_wb_fwd <= '1' when ((op_dec_ctrl_i(ctrl_rb_3_c downto ctrl_rb_0_c) = ma_ctrl_ff(ctrl_rd_3_c downto ctrl_rd_0_c)) and (op_dec_ctrl_i(ctrl_rb_is_imm_c) = '0')) else '0';
-- ex_c_wb_fwd <= '1' when ((op_dec_ctrl_i(ctrl_rb_3_c downto ctrl_rb_0_c) = ma_ctrl_ff(ctrl_rd_3_c downto ctrl_rd_0_c))) else '0';
 
 
 
-- Stage 2: Execution ----------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
ex_stage: process (clk_i)
219,14 → 201,9
if (rst_i = '1') then
ex_ctrl_ff <= (others => '0');
elsif (ce_i = '1') then
ex_ctrl_ff <= op_dec_ctrl_i;
ex_ctrl_ff(ctrl_en_c) <= op_dec_ctrl_i(ctrl_en_c) and (not dis_cycle);
ex_ctrl_ff(ctrl_mcyc_c) <= multi_cyc_ff; -- un-interruptable multi-cycle operation?
-- ex_ctrl_ff(ctrl_a_ex_ma_fw_c) <= ex_a_ma_fwd;
-- ex_ctrl_ff(ctrl_a_ex_wb_fw_c) <= ex_a_wb_fwd;
-- ex_ctrl_ff(ctrl_b_ex_ma_fw_c) <= ex_b_ma_fwd;
-- ex_ctrl_ff(ctrl_b_ex_wb_fw_c) <= ex_b_wb_fwd;
-- ex_ctrl_ff(ctrl_c_ex_wb_fw_c) <= ex_c_wb_fwd;
ex_ctrl_ff <= op_dec_ctrl_i;
ex_ctrl_ff(ctrl_en_c) <= op_dec_ctrl_i(ctrl_en_c) and (not dis_cycle);
ex_ctrl_ff(ctrl_mcyc_c) <= multi_cyc_ff; -- un-interruptable multi-cycle operation?
end if;
end if;
end process ex_stage;
248,7 → 225,6
exc_pos_o <= ex_ctrl_ff(ctrl_en_c) and (not ex_ctrl_ff(ctrl_mcyc_c)); -- exception would be possible and no in-interuptable op
 
 
 
-- Stage 3: Memory Access ------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
ma_stage: process (clk_i)
274,7 → 250,6
ma_ctrl_bus_o <= ma_ctrl_ff;
 
 
 
-- Stage 4: Write Back ---------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
wb_stage: process (clk_i)
295,5 → 270,4
 
 
 
 
end ctrl_structure;
/rtl/ATLAS_pkg.vhd
31,14 → 31,14
constant data_width_c : natural := 16; -- processing data width
constant data_bytes_c : natural := data_width_c/8; -- processing data width in bytes
constant align_lsb_c : natural := data_bytes_c/2; -- lsb of adr word boundary
constant link_reg_adr_c : std_logic_vector(02 downto 0) := "111"; -- link reg for calls
constant stack_pnt_adr_c : std_logic_vector(02 downto 0) := "110"; -- stack pointer
constant boot_page_c : std_logic_vector(15 downto 0) := x"8000"; -- boot pages begin
constant boot_adr_c : std_logic_vector(15 downto 0) := x"0000"; -- boot address
constant start_page_c : std_logic_vector(15 downto 0) := boot_page_c; -- start page
constant start_adr_c : std_logic_vector(15 downto 0) := boot_adr_c; -- start address
constant user_mode_c : std_logic := '0'; -- user mode indicator
constant system_mode_c : std_logic := '1'; -- system mode indicator
constant link_reg_adr_c : std_ulogic_vector(02 downto 0) := "111"; -- link reg for calls
constant stack_pnt_adr_c : std_ulogic_vector(02 downto 0) := "110"; -- stack pointer
constant boot_page_c : std_ulogic_vector(15 downto 0) := x"8000"; -- boot pages begin
constant boot_adr_c : std_ulogic_vector(15 downto 0) := x"0000"; -- boot address
constant start_page_c : std_ulogic_vector(15 downto 0) := boot_page_c; -- start page
constant start_adr_c : std_ulogic_vector(15 downto 0) := boot_adr_c; -- start address
constant user_mode_c : std_ulogic := '0'; -- user mode indicator
constant system_mode_c : std_ulogic := '1'; -- system mode indicator
constant branch_slots_en_c : boolean := false; -- use branch delay slots (highly experimental!!!)
constant ldil_sign_ext_c : boolean := true; -- use sign extension when loading low byte
constant reg_branches_en_c : boolean := true; -- synthesize register-based branches
47,19 → 47,19
 
-- Interrupt/Exception Vectors (word-address) ---------------------------------------------
-- -------------------------------------------------------------------------------------------
constant res_int_vec_c : std_logic_vector(15 downto 0) := x"0000"; -- use boot address instead!
constant irq0_int_vec_c : std_logic_vector(15 downto 0) := x"0001"; -- external int line 0 IRQ
constant irq1_int_vec_c : std_logic_vector(15 downto 0) := x"0002"; -- external int line 1 IRQ
constant cmd_err_int_vec_c : std_logic_vector(15 downto 0) := x"0003"; -- instruction/access error
constant swi_int_vec_c : std_logic_vector(15 downto 0) := x"0004"; -- software IRQ
constant res_int_vec_c : std_ulogic_vector(15 downto 0) := x"0000"; -- use boot address instead!
constant irq0_int_vec_c : std_ulogic_vector(15 downto 0) := x"0001"; -- external int line 0 IRQ
constant irq1_int_vec_c : std_ulogic_vector(15 downto 0) := x"0002"; -- external int line 1 IRQ
constant cmd_err_int_vec_c : std_ulogic_vector(15 downto 0) := x"0003"; -- instruction/access error
constant swi_int_vec_c : std_ulogic_vector(15 downto 0) := x"0004"; -- software IRQ
 
 
-- Wishbone Bus Constants -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant wb_classic_cyc_c : std_logic_vector(2 downto 0) := "000"; -- classic cycle
constant wb_con_bst_cyc_c : std_logic_vector(2 downto 0) := "001"; -- constant address burst
constant wb_inc_bst_cyc_c : std_logic_vector(2 downto 0) := "010"; -- incrementing address burst
constant wb_end_bst_cyc_c : std_logic_vector(2 downto 0) := "111"; -- burst end
constant wb_classic_cyc_c : std_ulogic_vector(2 downto 0) := "000"; -- classic cycle
constant wb_con_bst_cyc_c : std_ulogic_vector(2 downto 0) := "001"; -- constant address burst
constant wb_inc_bst_cyc_c : std_ulogic_vector(2 downto 0) := "010"; -- incrementing address burst
constant wb_end_bst_cyc_c : std_ulogic_vector(2 downto 0) := "111"; -- burst end
 
 
-- Machine Status Register ----------------------------------------------------------------
188,16 → 188,8
-- Conditional write back --
constant ctrl_cond_wb_c : natural := 55; -- is cond write back?
 
-- -- EX Forwarding --
-- constant ctrl_a_ex_ma_fw_c : natural := 56; -- obsolete
-- constant ctrl_a_ex_wb_fw_c : natural := 57; -- obsolete
-- constant ctrl_b_ex_ma_fw_c : natural := 58; -- obsolete
-- constant ctrl_b_ex_wb_fw_c : natural := 59; -- obsolete
-- constant ctrl_c_ex_wb_fw_c : natural := 60; -- obsolete
 
-- Bus Size --
constant ctrl_width_c : natural := 56; -- control bus size
-- constant ctrl_width_c : natural := 61; -- obsolete
 
-- Progress Redefinitions --
constant ctrl_wb_en_c : natural := ctrl_rd_wb_c; -- valid write back
231,72 → 223,72
 
-- Condition Codes ------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant cond_eq_c : std_logic_vector(3 downto 0) := "0000"; -- equal
constant cond_ne_c : std_logic_vector(3 downto 0) := "0001"; -- not equal
constant cond_cs_c : std_logic_vector(3 downto 0) := "0010"; -- unsigned higher or same
constant cond_cc_c : std_logic_vector(3 downto 0) := "0011"; -- unsigned lower
constant cond_mi_c : std_logic_vector(3 downto 0) := "0100"; -- negative
constant cond_pl_c : std_logic_vector(3 downto 0) := "0101"; -- positive or zero
constant cond_os_c : std_logic_vector(3 downto 0) := "0110"; -- overflow
constant cond_oc_c : std_logic_vector(3 downto 0) := "0111"; -- no overflow
constant cond_hi_c : std_logic_vector(3 downto 0) := "1000"; -- unsigned higher
constant cond_ls_c : std_logic_vector(3 downto 0) := "1001"; -- unsigned lower or same
constant cond_ge_c : std_logic_vector(3 downto 0) := "1010"; -- greater than or equal
constant cond_lt_c : std_logic_vector(3 downto 0) := "1011"; -- less than
constant cond_gt_c : std_logic_vector(3 downto 0) := "1100"; -- greater than
constant cond_le_c : std_logic_vector(3 downto 0) := "1101"; -- less than or equal
constant cond_ts_c : std_logic_vector(3 downto 0) := "1110"; -- transfer flag set
constant cond_al_c : std_logic_vector(3 downto 0) := "1111"; -- always
constant cond_eq_c : std_ulogic_vector(3 downto 0) := "0000"; -- equal
constant cond_ne_c : std_ulogic_vector(3 downto 0) := "0001"; -- not equal
constant cond_cs_c : std_ulogic_vector(3 downto 0) := "0010"; -- unsigned higher or same
constant cond_cc_c : std_ulogic_vector(3 downto 0) := "0011"; -- unsigned lower
constant cond_mi_c : std_ulogic_vector(3 downto 0) := "0100"; -- negative
constant cond_pl_c : std_ulogic_vector(3 downto 0) := "0101"; -- positive or zero
constant cond_os_c : std_ulogic_vector(3 downto 0) := "0110"; -- overflow
constant cond_oc_c : std_ulogic_vector(3 downto 0) := "0111"; -- no overflow
constant cond_hi_c : std_ulogic_vector(3 downto 0) := "1000"; -- unsigned higher
constant cond_ls_c : std_ulogic_vector(3 downto 0) := "1001"; -- unsigned lower or same
constant cond_ge_c : std_ulogic_vector(3 downto 0) := "1010"; -- greater than or equal
constant cond_lt_c : std_ulogic_vector(3 downto 0) := "1011"; -- less than
constant cond_gt_c : std_ulogic_vector(3 downto 0) := "1100"; -- greater than
constant cond_le_c : std_ulogic_vector(3 downto 0) := "1101"; -- less than or equal
constant cond_ts_c : std_ulogic_vector(3 downto 0) := "1110"; -- transfer flag set
constant cond_al_c : std_ulogic_vector(3 downto 0) := "1111"; -- always
 
 
-- ALU Function Select --------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant fs_inc_c : std_logic_vector(3 downto 0) := "0000"; -- add immediate
constant fs_dec_c : std_logic_vector(3 downto 0) := "0001"; -- subtract immediate
constant fs_add_c : std_logic_vector(3 downto 0) := "0010"; -- add
constant fs_adc_c : std_logic_vector(3 downto 0) := "0011"; -- add with carry
constant fs_sub_c : std_logic_vector(3 downto 0) := "0100"; -- subtract
constant fs_sbc_c : std_logic_vector(3 downto 0) := "0101"; -- subtract with carry
constant fs_cmp_c : std_logic_vector(3 downto 0) := "0110"; -- compare (sub)
constant fs_cpx_c : std_logic_vector(3 downto 0) := "0111"; -- extende compare with flags (sbc)
constant fs_and_c : std_logic_vector(3 downto 0) := "1000"; -- logical and
constant fs_orr_c : std_logic_vector(3 downto 0) := "1001"; -- logical or
constant fs_eor_c : std_logic_vector(3 downto 0) := "1010"; -- logical xor
constant fs_nand_c : std_logic_vector(3 downto 0) := "1011"; -- logical nand
constant fs_bic_c : std_logic_vector(3 downto 0) := "1100"; -- bit clear
constant fs_teq_c : std_logic_vector(3 downto 0) := "1101"; -- compare by logical and
constant fs_tst_c : std_logic_vector(3 downto 0) := "1110"; -- compare by logical xor
constant fs_sft_c : std_logic_vector(3 downto 0) := "1111"; -- shift operation
constant fs_inc_c : std_ulogic_vector(3 downto 0) := "0000"; -- add immediate
constant fs_dec_c : std_ulogic_vector(3 downto 0) := "0001"; -- subtract immediate
constant fs_add_c : std_ulogic_vector(3 downto 0) := "0010"; -- add
constant fs_adc_c : std_ulogic_vector(3 downto 0) := "0011"; -- add with carry
constant fs_sub_c : std_ulogic_vector(3 downto 0) := "0100"; -- subtract
constant fs_sbc_c : std_ulogic_vector(3 downto 0) := "0101"; -- subtract with carry
constant fs_cmp_c : std_ulogic_vector(3 downto 0) := "0110"; -- compare (sub)
constant fs_cpx_c : std_ulogic_vector(3 downto 0) := "0111"; -- extende compare with flags (sbc)
constant fs_and_c : std_ulogic_vector(3 downto 0) := "1000"; -- logical and
constant fs_orr_c : std_ulogic_vector(3 downto 0) := "1001"; -- logical or
constant fs_eor_c : std_ulogic_vector(3 downto 0) := "1010"; -- logical xor
constant fs_nand_c : std_ulogic_vector(3 downto 0) := "1011"; -- logical nand
constant fs_bic_c : std_ulogic_vector(3 downto 0) := "1100"; -- bit clear
constant fs_teq_c : std_ulogic_vector(3 downto 0) := "1101"; -- compare by logical and
constant fs_tst_c : std_ulogic_vector(3 downto 0) := "1110"; -- compare by logical xor
constant fs_sft_c : std_ulogic_vector(3 downto 0) := "1111"; -- shift operation
 
-- Pseudo Intructions --
constant fs_ld_user_c : std_logic_vector(3 downto 0) := fs_orr_c; -- load from user bank
constant fs_st_user_c : std_logic_vector(3 downto 0) := fs_and_c; -- store to user bank
constant fs_ld_msr_c : std_logic_vector(3 downto 0) := fs_cmp_c; -- load from msr
constant fs_st_msr_c : std_logic_vector(3 downto 0) := fs_cpx_c; -- store to msr
constant fs_ld_pc_c : std_logic_vector(3 downto 0) := fs_tst_c; -- load from pc
constant fs_st_pc_c : std_logic_vector(3 downto 0) := fs_teq_c; -- store to pc
constant fs_ld_user_c : std_ulogic_vector(3 downto 0) := fs_orr_c; -- load from user bank
constant fs_st_user_c : std_ulogic_vector(3 downto 0) := fs_and_c; -- store to user bank
constant fs_ld_msr_c : std_ulogic_vector(3 downto 0) := fs_cmp_c; -- load from msr
constant fs_st_msr_c : std_ulogic_vector(3 downto 0) := fs_cpx_c; -- store to msr
constant fs_ld_pc_c : std_ulogic_vector(3 downto 0) := fs_tst_c; -- load from pc
constant fs_st_pc_c : std_ulogic_vector(3 downto 0) := fs_teq_c; -- store to pc
 
-- Elementary ALU Operations --
constant alu_adc_c : std_logic_vector(2 downto 0) := "000"; -- add with carry
constant alu_sbc_c : std_logic_vector(2 downto 0) := "001"; -- subtract with carry
constant alu_bic_c : std_logic_vector(2 downto 0) := "010"; -- bit clear
constant alu_sft_c : std_logic_vector(2 downto 0) := "011"; -- shift operation
constant alu_and_c : std_logic_vector(2 downto 0) := "100"; -- logical and
constant alu_orr_c : std_logic_vector(2 downto 0) := "101"; -- logical or
constant alu_eor_c : std_logic_vector(2 downto 0) := "110"; -- logical xor
constant alu_nand_c : std_logic_vector(2 downto 0) := "111"; -- logical nand
constant alu_adc_c : std_ulogic_vector(2 downto 0) := "000"; -- add with carry
constant alu_sbc_c : std_ulogic_vector(2 downto 0) := "001"; -- subtract with carry
constant alu_bic_c : std_ulogic_vector(2 downto 0) := "010"; -- bit clear
constant alu_sft_c : std_ulogic_vector(2 downto 0) := "011"; -- shift operation
constant alu_and_c : std_ulogic_vector(2 downto 0) := "100"; -- logical and
constant alu_orr_c : std_ulogic_vector(2 downto 0) := "101"; -- logical or
constant alu_eor_c : std_ulogic_vector(2 downto 0) := "110"; -- logical xor
constant alu_nand_c : std_ulogic_vector(2 downto 0) := "111"; -- logical nand
 
 
-- Shifter Control ------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant sft_swp_c : std_logic_vector(2 downto 0) := "000"; -- swap halfwords
constant sft_asr_c : std_logic_vector(2 downto 0) := "001"; -- arithemtical right shift
constant sft_rol_c : std_logic_vector(2 downto 0) := "010"; -- rotate left
constant sft_ror_c : std_logic_vector(2 downto 0) := "011"; -- rotate right
constant sft_lsl_c : std_logic_vector(2 downto 0) := "100"; -- logical shift left
constant sft_lsr_c : std_logic_vector(2 downto 0) := "101"; -- logical shift right
constant sft_rlc_c : std_logic_vector(2 downto 0) := "110"; -- rotate left through carry
constant sft_rrc_c : std_logic_vector(2 downto 0) := "111"; -- rotate right through carry
constant sft_swp_c : std_ulogic_vector(2 downto 0) := "000"; -- swap halfwords
constant sft_asr_c : std_ulogic_vector(2 downto 0) := "001"; -- arithemtical right shift
constant sft_rol_c : std_ulogic_vector(2 downto 0) := "010"; -- rotate left
constant sft_ror_c : std_ulogic_vector(2 downto 0) := "011"; -- rotate right
constant sft_lsl_c : std_ulogic_vector(2 downto 0) := "100"; -- logical shift left
constant sft_lsr_c : std_ulogic_vector(2 downto 0) := "101"; -- logical shift right
constant sft_rlc_c : std_ulogic_vector(2 downto 0) := "110"; -- rotate left through carry
constant sft_rrc_c : std_ulogic_vector(2 downto 0) := "111"; -- rotate right through carry
 
 
-- Cool Stuff -----------------------------------------------------------------------------
320,489 → 312,489
 
-- Component: Data Register File ----------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component reg_file
port (
-- global control --
clk_i : in std_logic; -- global clock line
ce_i : in std_logic; -- clock enable
rst_i : in std_logic; -- global reset line, sync, high-active
component reg_file
port (
-- global control --
clk_i : in std_ulogic; -- global clock line
ce_i : in std_ulogic; -- clock enable
rst_i : in std_ulogic; -- global reset line, sync, high-active
 
-- function control --
wb_ctrl_bus_i : in std_logic_vector(ctrl_width_c-1 downto 0); -- wb stage control
of_ctrl_bus_i : in std_logic_vector(ctrl_width_c-1 downto 0); -- of stage control
-- function control --
wb_ctrl_bus_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- wb stage control
of_ctrl_bus_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- of stage control
 
-- data input --
wb_data_i : in std_logic_vector(data_width_c-1 downto 0); -- write back data
immediate_i : in std_logic_vector(data_width_c-1 downto 0); -- immediates
pc_1d_i : in std_logic_vector(data_width_c-1 downto 0); -- pc 1x delayed
wb_fwd_i : in std_logic_vector(fwd_width_c-1 downto 0); -- wb stage forwarding path
-- data input --
wb_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write back data
immediate_i : in std_ulogic_vector(data_width_c-1 downto 0); -- immediates
pc_1d_i : in std_ulogic_vector(data_width_c-1 downto 0); -- pc 1x delayed
wb_fwd_i : in std_ulogic_vector(fwd_width_c-1 downto 0); -- wb stage forwarding path
 
-- data output --
op_a_data_o : out std_logic_vector(data_width_c-1 downto 0); -- operand a output
op_b_data_o : out std_logic_vector(data_width_c-1 downto 0); -- operand b output
op_c_data_o : out std_logic_vector(data_width_c-1 downto 0) -- operand c output
);
end component;
-- data output --
op_a_data_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand a output
op_b_data_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand b output
op_c_data_o : out std_ulogic_vector(data_width_c-1 downto 0) -- operand c output
);
end component;
 
 
-- Component: Arithmetic/Logic Unit -------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component alu
port (
-- global control --
clk_i : in std_logic; -- global clock line
ce_i : in std_logic; -- clock enable
rst_i : in std_logic; -- global reset line, sync, high-active
component alu
port (
-- global control --
clk_i : in std_ulogic; -- global clock line
ce_i : in std_ulogic; -- clock enable
rst_i : in std_ulogic; -- global reset line, sync, high-active
 
-- function control --
ex_ctrl_bus_i : in std_logic_vector(ctrl_width_c-1 downto 0); -- stage control
flag_bus_i : in std_logic_vector(flag_bus_width_c-1 downto 0); -- flag input
-- function control --
ex_ctrl_bus_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- stage control
flag_bus_i : in std_ulogic_vector(flag_bus_width_c-1 downto 0); -- flag input
 
-- data input --
op_a_i : in std_logic_vector(data_width_c-1 downto 0); -- operand a input
op_b_i : in std_logic_vector(data_width_c-1 downto 0); -- operand b input
op_c_i : in std_logic_vector(data_width_c-1 downto 0); -- operand c input
pc_1d_i : in std_logic_vector(data_width_c-1 downto 0); -- 1x delayed pc
ma_fwd_i : in std_logic_vector(fwd_width_c-1 downto 0); -- ma stage forwarding path
wb_fwd_i : in std_logic_vector(fwd_width_c-1 downto 0); -- wb stage forwarding path
-- data input --
op_a_i : in std_ulogic_vector(data_width_c-1 downto 0); -- operand a input
op_b_i : in std_ulogic_vector(data_width_c-1 downto 0); -- operand b input
op_c_i : in std_ulogic_vector(data_width_c-1 downto 0); -- operand c input
pc_1d_i : in std_ulogic_vector(data_width_c-1 downto 0); -- 1x delayed pc
ma_fwd_i : in std_ulogic_vector(fwd_width_c-1 downto 0); -- ma stage forwarding path
wb_fwd_i : in std_ulogic_vector(fwd_width_c-1 downto 0); -- wb stage forwarding path
 
-- data output --
flag_bus_o : out std_logic_vector(flag_bus_width_c-1 downto 0); -- flag output
mask_t_flag_o : out std_logic; -- t-flag for mask generation
msr_data_o : out std_logic_vector(data_width_c-1 downto 0); -- msr write data
alu_res_o : out std_logic_vector(data_width_c-1 downto 0); -- alu result
mul_res_o : out std_logic_vector(2*data_width_c-1 downto 0); -- mul result
bp_opa_o : out std_logic_vector(data_width_c-1 downto 0); -- operand a bypass
bp_opc_o : out std_logic_vector(data_width_c-1 downto 0); -- operand c bypass
cp_cp0_en_o : out std_logic; -- access to cp0
cp_cp1_en_o : out std_logic; -- access to cp1
cp_op_o : out std_logic; -- data transfer/operation
cp_rw_o : out std_logic; -- read/write access
cp_cmd_o : out std_logic_vector(cp_cmd_width_c-1 downto 0); -- register addresses / cmd
cp_dat_o : out std_logic_vector(data_width_c-1 downto 0); -- write data
mem_req_o : out std_logic -- data memory access request for next cycle
);
end component;
-- data output --
flag_bus_o : out std_ulogic_vector(flag_bus_width_c-1 downto 0); -- flag output
mask_t_flag_o : out std_ulogic; -- t-flag for mask generation
msr_data_o : out std_ulogic_vector(data_width_c-1 downto 0); -- msr write data
alu_res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- alu result
mul_res_o : out std_ulogic_vector(2*data_width_c-1 downto 0); -- mul result
bp_opa_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand a bypass
bp_opc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand c bypass
cp_cp0_en_o : out std_ulogic; -- access to cp0
cp_cp1_en_o : out std_ulogic; -- access to cp1
cp_op_o : out std_ulogic; -- data transfer/operation
cp_rw_o : out std_ulogic; -- read/write access
cp_cmd_o : out std_ulogic_vector(cp_cmd_width_c-1 downto 0); -- register addresses / cmd
cp_dat_o : out std_ulogic_vector(data_width_c-1 downto 0); -- write data
mem_req_o : out std_ulogic -- data memory access request for next cycle
);
end component;
 
 
-- Component: Machine Status System -------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component sys_reg
port (
-- global control --
clk_i : in std_logic; -- global clock line
ce_i : in std_logic; -- clock enable
rst_i : in std_logic; -- global reset line, asyc
component sys_reg
port (
-- global control --
clk_i : in std_ulogic; -- global clock line
ce_i : in std_ulogic; -- clock enable
rst_i : in std_ulogic; -- global reset line, asyc
-- function control --
ex_ctrl_bus_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- ex stage control
ma_ctrl_bus_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- ma stage control
ext_int_req0_i : in std_ulogic; -- external interrupt request 0
ext_int_req1_i : in std_ulogic; -- external interrupt request 1
-- data input --
flag_bus_i : in std_ulogic_vector(flag_bus_width_c-1 downto 0); -- flag input
exc_pos_i : in std_ulogic; -- external interrupt would be possible
stop_pc : in std_ulogic; -- freeze pc
pc_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- pc write data
msr_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- msr write data
-- data output --
flag_bus_o : out std_ulogic_vector(flag_bus_width_c-1 downto 0); -- flag output
valid_branch_o : out std_ulogic; -- valid branch detected
exc_executed_o : out std_ulogic; -- executed exception
wake_up_o : out std_ulogic; -- wake-up signal
rd_msr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data msr
pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- pc output
pc_1d_o : out std_ulogic_vector(data_width_c-1 downto 0); -- pc 1x delayed
cp_ptc_o : out std_ulogic; -- user coprocessor protection
cond_true_o : out std_ulogic; -- condition is true
mode_o : out std_ulogic; -- current operating mode
mode_ff_o : out std_ulogic -- delayed current mode
);
end component;
 
-- function control --
ex_ctrl_bus_i : in std_logic_vector(ctrl_width_c-1 downto 0); -- ex stage control
ma_ctrl_bus_i : in std_logic_vector(ctrl_width_c-1 downto 0); -- ma stage control
ext_int_req0_i : in std_logic; -- external interrupt request 0
ext_int_req1_i : in std_logic; -- external interrupt request 1
 
-- data input --
flag_bus_i : in std_logic_vector(flag_bus_width_c-1 downto 0); -- flag input
exc_pos_i : in std_logic; -- external interrupt would be possible
stop_pc : in std_logic; -- freeze pc
pc_data_i : in std_logic_vector(data_width_c-1 downto 0); -- pc write data
msr_data_i : in std_logic_vector(data_width_c-1 downto 0); -- msr write data
 
-- data output --
flag_bus_o : out std_logic_vector(flag_bus_width_c-1 downto 0); -- flag output
valid_branch_o : out std_logic; -- valid branch detected
exc_executed_o : out std_logic; -- executed exception
wake_up_o : out std_logic; -- wake-up signal
rd_msr_o : out std_logic_vector(data_width_c-1 downto 0); -- read data msr
pc_o : out std_logic_vector(data_width_c-1 downto 0); -- pc output
pc_1d_o : out std_logic_vector(data_width_c-1 downto 0); -- pc 1x delayed
cp_ptc_o : out std_logic; -- user coprocessor protection
cond_true_o : out std_logic; -- condition is true
mode_o : out std_logic; -- current operating mode
mode_ff_o : out std_logic -- delayed current mode
);
end component;
 
 
-- Component: Memory Access Control -------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component mem_acc
port (
-- global control --
clk_i : in std_logic; -- global clock line
ce_i : in std_logic; -- clock enable
rst_i : in std_logic; -- global reset line, asyc
component mem_acc
port (
-- global control --
clk_i : in std_ulogic; -- global clock line
ce_i : in std_ulogic; -- clock enable
rst_i : in std_ulogic; -- global reset line, asyc
-- function control --
ma_ctrl_bus_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- ma stage control
-- data input --
alu_res_i : in std_ulogic_vector(data_width_c-1 downto 0); -- alu result
mul_res_i : in std_ulogic_vector(2*data_width_c-1 downto 0); -- mul result
adr_base_i : in std_ulogic_vector(data_width_c-1 downto 0); -- op_a bypass
data_bp_i : in std_ulogic_vector(data_width_c-1 downto 0); -- op_b bypass
cp_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- coprocessor rd data
rd_msr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- read data msr
wb_fwd_i : in std_ulogic_vector(fwd_width_c-1 downto 0); -- wb stage forwarding path
-- data output --
data_o : out std_ulogic_vector(data_width_c-1 downto 0); -- data output
mem_adr_fb_o : out std_ulogic_vector(data_width_c-1 downto 0); -- memory address feedback
ma_fwd_o : out std_ulogic_vector(fwd_width_c-1 downto 0); -- ma stage forwarding path
-- memory (w) interface --
mem_adr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- address output
mem_dat_o : out std_ulogic_vector(data_width_c-1 downto 0); -- write data output
mem_rw_o : out std_ulogic -- read write
);
end component;
 
-- function control --
ma_ctrl_bus_i : in std_logic_vector(ctrl_width_c-1 downto 0); -- ma stage control
 
-- data input --
alu_res_i : in std_logic_vector(data_width_c-1 downto 0); -- alu result
mul_res_i : in std_logic_vector(2*data_width_c-1 downto 0); -- mul result
adr_base_i : in std_logic_vector(data_width_c-1 downto 0); -- op_a bypass
data_bp_i : in std_logic_vector(data_width_c-1 downto 0); -- op_b bypass
cp_data_i : in std_logic_vector(data_width_c-1 downto 0); -- coprocessor rd data
rd_msr_i : in std_logic_vector(data_width_c-1 downto 0); -- read data msr
wb_fwd_i : in std_logic_vector(fwd_width_c-1 downto 0); -- wb stage forwarding path
 
-- data output --
data_o : out std_logic_vector(data_width_c-1 downto 0); -- data output
mem_adr_fb_o : out std_logic_vector(data_width_c-1 downto 0); -- memory address feedback
ma_fwd_o : out std_logic_vector(fwd_width_c-1 downto 0); -- ma stage forwarding path
 
-- memory (w) interface --
mem_adr_o : out std_logic_vector(data_width_c-1 downto 0); -- address output
mem_dat_o : out std_logic_vector(data_width_c-1 downto 0); -- write data output
mem_rw_o : out std_logic -- read write
);
end component;
 
 
-- Component: Data Write Back Unit --------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component wb_unit
port (
-- global control --
clk_i : in std_logic; -- global clock line
ce_i : in std_logic; -- clock enable
rst_i : in std_logic; -- global reset line, sync, high-active
component wb_unit
port (
-- global control --
clk_i : in std_ulogic; -- global clock line
ce_i : in std_ulogic; -- clock enable
rst_i : in std_ulogic; -- global reset line, sync, high-active
-- function control --
wb_ctrl_bus_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- wb stage control
-- data input --
mem_wb_dat_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
alu_wb_dat_i : in std_ulogic_vector(data_width_c-1 downto 0); -- alu read data
mem_adr_fb_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory address feedback
-- data output --
wb_data_o : out std_ulogic_vector(data_width_c-1 downto 0); -- write back data
wb_fwd_o : out std_ulogic_vector(fwd_width_c-1 downto 0) -- wb stage forwarding path
);
end component;
 
-- function control --
wb_ctrl_bus_i : in std_logic_vector(ctrl_width_c-1 downto 0); -- wb stage control
 
-- data input --
mem_wb_dat_i : in std_logic_vector(data_width_c-1 downto 0); -- memory read data
alu_wb_dat_i : in std_logic_vector(data_width_c-1 downto 0); -- alu read data
mem_adr_fb_i : in std_logic_vector(data_width_c-1 downto 0); -- memory address feedback
 
-- data output --
wb_data_o : out std_logic_vector(data_width_c-1 downto 0); -- write back data
wb_fwd_o : out std_logic_vector(fwd_width_c-1 downto 0) -- wb stage forwarding path
);
end component;
 
 
-- Component: Control System --------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component ctrl
port (
-- global control --
clk_i : in std_logic; -- global clock line
ce_i : in std_logic; -- clock enable
rst_i : in std_logic; -- global reset line, sync, high-active
component ctrl
port (
-- global control --
clk_i : in std_ulogic; -- global clock line
ce_i : in std_ulogic; -- clock enable
rst_i : in std_ulogic; -- global reset line, sync, high-active
-- decoder interface --
op_dec_ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- decoder ctrl lines
multi_cyc_o : out std_ulogic; -- multi-cycle indicator
multi_cyc_req_i : in std_ulogic; -- multi-cycle request
instr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- instruction input
instr_reg_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction register
-- control lines --
of_ctrl_bus_o : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- of stage control
ex_ctrl_bus_o : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- ex stage control
ma_ctrl_bus_o : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- ma stage control
wb_ctrl_bus_o : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- wb stage control
-- function control --
cond_true_i : in std_ulogic; -- condition is true
valid_branch_i : in std_ulogic; -- valid branch detected
exc_taken_i : in std_ulogic; -- exception taken
wake_up_i : in std_ulogic; -- wake up from sleep
exc_pos_o : out std_ulogic; -- exception would be possible
stop_pc_o : out std_ulogic -- freeze program counter
);
end component;
 
-- decoder interface --
op_dec_ctrl_i : in std_logic_vector(ctrl_width_c-1 downto 0); -- decoder ctrl lines
multi_cyc_o : out std_logic; -- multi-cycle indicator
multi_cyc_req_i : in std_logic; -- multi-cycle request
instr_i : in std_logic_vector(data_width_c-1 downto 0); -- instruction input
instr_reg_o : out std_logic_vector(data_width_c-1 downto 0); -- instruction register
 
-- control lines --
of_ctrl_bus_o : out std_logic_vector(ctrl_width_c-1 downto 0); -- of stage control
ex_ctrl_bus_o : out std_logic_vector(ctrl_width_c-1 downto 0); -- ex stage control
ma_ctrl_bus_o : out std_logic_vector(ctrl_width_c-1 downto 0); -- ma stage control
wb_ctrl_bus_o : out std_logic_vector(ctrl_width_c-1 downto 0); -- wb stage control
 
-- function control --
cond_true_i : in std_logic; -- condition is true
valid_branch_i : in std_logic; -- valid branch detected
exc_taken_i : in std_logic; -- exception taken
wake_up_i : in std_logic; -- wake up from sleep
exc_pos_o : out std_logic; -- exception would be possible
stop_pc_o : out std_logic -- freeze program counter
);
end component;
 
 
-- Component: Opcode Decoder --------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component op_dec
port (
-- decoder interface input --
instr_i : in std_logic_vector(data_width_c-1 downto 0); -- instruction input
instr_adr_i : in std_logic_vector(data_width_c-1 downto 0); -- corresponding address
t_flag_i : in std_logic; -- t-flag input
m_flag_i : in std_logic; -- mode flag input
multi_cyc_i : in std_logic; -- multi-cycle indicator
cp_ptc_i : in std_logic; -- user coprocessor protection
component op_dec
port (
-- decoder interface input --
instr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- instruction input
instr_adr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- corresponding address
t_flag_i : in std_ulogic; -- t-flag input
m_flag_i : in std_ulogic; -- mode flag input
multi_cyc_i : in std_ulogic; -- multi-cycle indicator
cp_ptc_i : in std_ulogic; -- user coprocessor protection
-- decoder interface output --
multi_cyc_req_o : out std_ulogic; -- multi-cycle reqest
ctrl_o : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- decoder ctrl lines
imm_o : out std_ulogic_vector(data_width_c-1 downto 0) -- immediate
);
end component;
 
-- decoder interface output --
multi_cyc_req_o : out std_logic; -- multi-cycle reqest
ctrl_o : out std_logic_vector(ctrl_width_c-1 downto 0); -- decoder ctrl lines
imm_o : out std_logic_vector(data_width_c-1 downto 0) -- immediate
);
end component;
 
 
-- Component: Atlas CPU Core --------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component atlas_cpu
port (
-- global control --
clk_i : in std_logic; -- global clock line
rst_i : in std_logic; -- global reset line, sync, high-active
ce_i : in std_logic; -- global clock enable, high-active
component atlas_cpu
port (
-- global control --
clk_i : in std_ulogic; -- global clock line
rst_i : in std_ulogic; -- global reset line, sync, high-active
ce_i : in std_ulogic; -- global clock enable, high-active
-- instruction interface --
instr_adr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction byte adr
instr_dat_i : in std_ulogic_vector(data_width_c-1 downto 0); -- instruction input
-- memory arbitration --
sys_mode_o : out std_ulogic; -- current operating mode
sys_int_o : out std_ulogic; -- interrupt processing
-- memory system --
mem_req_o : out std_ulogic; -- mem access in next cycle
mem_rw_o : out std_ulogic; -- read write
mem_adr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- data byte adr
mem_dat_o : out std_ulogic_vector(data_width_c-1 downto 0); -- write data
mem_dat_i : in std_ulogic_vector(data_width_c-1 downto 0); -- read data
-- coprocessor interface --
usr_cp_en_o : out std_ulogic; -- access to cp0
sys_cp_en_o : out std_ulogic; -- access to cp1
cp_op_o : out std_ulogic; -- data transfer/processing
cp_rw_o : out std_ulogic; -- read/write access
cp_cmd_o : out std_ulogic_vector(cp_cmd_width_c-1 downto 0); -- register addresses / cmd
cp_dat_o : out std_ulogic_vector(data_width_c-1 downto 0); -- write data
cp_dat_i : in std_ulogic_vector(data_width_c-1 downto 0); -- read data cp0 or cp1
-- external interrupt lines --
ext_int_0_i : in std_ulogic; -- external interrupt request 0
ext_int_1_i : in std_ulogic -- external interrupt request 1
);
end component;
 
-- instruction interface --
instr_adr_o : out std_logic_vector(data_width_c-1 downto 0); -- instruction byte adr
instr_dat_i : in std_logic_vector(data_width_c-1 downto 0); -- instruction input
 
-- memory arbitration --
sys_mode_o : out std_logic; -- current operating mode
sys_int_o : out std_logic; -- interrupt processing
 
-- memory system --
mem_req_o : out std_logic; -- mem access in next cycle
mem_rw_o : out std_logic; -- read write
mem_adr_o : out std_logic_vector(data_width_c-1 downto 0); -- data byte adr
mem_dat_o : out std_logic_vector(data_width_c-1 downto 0); -- write data
mem_dat_i : in std_logic_vector(data_width_c-1 downto 0); -- read data
 
-- coprocessor interface --
usr_cp_en_o : out std_logic; -- access to cp0
sys_cp_en_o : out std_logic; -- access to cp1
cp_op_o : out std_logic; -- data transfer/processing
cp_rw_o : out std_logic; -- read/write access
cp_cmd_o : out std_logic_vector(cp_cmd_width_c-1 downto 0); -- register addresses / cmd
cp_dat_o : out std_logic_vector(data_width_c-1 downto 0); -- write data
cp_dat_i : in std_logic_vector(data_width_c-1 downto 0); -- read data cp0 or cp1
 
-- external interrupt lines --
ext_int_0_i : in std_logic; -- external interrupt request 0
ext_int_1_i : in std_logic -- external interrupt request 1
);
end component;
 
 
-- Component: System Controller Core 0 ----------------------------------------------------
-- -------------------------------------------------------------------------------------------
component sys_0_core
port (
-- host interface --
clk_i : in std_logic; -- global clock line
rst_i : in std_logic; -- global reset line, sync, high-active
ice_i : in std_logic; -- interface clock enable, high-active
w_en_i : in std_logic; -- write enable
r_en_i : in std_logic; -- read enable
adr_i : in std_logic_vector(02 downto 0); -- access address
dat_i : in std_logic_vector(15 downto 0); -- write data
dat_o : out std_logic_vector(15 downto 0); -- read data
component sys_0_core
port (
-- host interface --
clk_i : in std_ulogic; -- global clock line
rst_i : in std_ulogic; -- global reset line, sync, high-active
ice_i : in std_ulogic; -- interface clock enable, high-active
w_en_i : in std_ulogic; -- write enable
r_en_i : in std_ulogic; -- read enable
adr_i : in std_ulogic_vector(02 downto 0); -- access address
dat_i : in std_ulogic_vector(15 downto 0); -- write data
dat_o : out std_ulogic_vector(15 downto 0); -- read data
-- interrupt lines --
timer_irq_o : out std_ulogic; -- timer irq
irq_i : in std_ulogic_vector(07 downto 0); -- irq input
irq_o : out std_ulogic -- interrupt request
);
end component;
 
-- interrupt lines --
timer_irq_o : out std_logic; -- timer irq
irq_i : in std_logic_vector(07 downto 0); -- irq input
irq_o : out std_logic -- interrupt request
);
end component;
 
 
-- Component: System Controller Core 1 ----------------------------------------------------
-- -------------------------------------------------------------------------------------------
component sys_1_core
component sys_1_core
generic (
-- clock speed configuration --
clk_speed_g : std_logic_vector(31 downto 0) := (others => '0') -- clock speed (in hz)
);
port (
-- host interface --
clk_i : in std_logic; -- global clock line
rst_i : in std_logic; -- global reset line, sync, high-active
ice_i : in std_logic; -- interface clock enable, high-active
w_en_i : in std_logic; -- write enable
r_en_i : in std_logic; -- read enable
adr_i : in std_logic_vector(02 downto 0); -- access address
dat_i : in std_logic_vector(15 downto 0); -- write data
dat_o : out std_logic_vector(15 downto 0); -- read data
sys_mode_i : in std_logic; -- current operating mode
int_exe_i : in std_logic; -- interrupt beeing executed
-- clock speed configuration --
clk_speed_g : std_ulogic_vector(31 downto 0) := (others => '0') -- clock speed (in hz)
);
port (
-- host interface --
clk_i : in std_ulogic; -- global clock line
rst_i : in std_ulogic; -- global reset line, sync, high-active
ice_i : in std_ulogic; -- interface clock enable, high-active
w_en_i : in std_ulogic; -- write enable
r_en_i : in std_ulogic; -- read enable
adr_i : in std_ulogic_vector(02 downto 0); -- access address
dat_i : in std_ulogic_vector(15 downto 0); -- write data
dat_o : out std_ulogic_vector(15 downto 0); -- read data
sys_mode_i : in std_ulogic; -- current operating mode
int_exe_i : in std_ulogic; -- interrupt beeing executed
-- memory interface --
mem_ip_adr_o : out std_ulogic_vector(15 downto 0); -- instruction page
mem_dp_adr_o : out std_ulogic_vector(15 downto 0) -- data page
);
end component;
 
-- memory interface --
mem_ip_adr_o : out std_logic_vector(15 downto 0); -- instruction page
mem_dp_adr_o : out std_logic_vector(15 downto 0) -- data page
);
end component;
 
 
-- Component: Communication Controller Core 0 ---------------------------------------------
-- -------------------------------------------------------------------------------------------
component com_0_core
port (
-- host interface --
clk_i : in std_logic; -- global clock line
rst_i : in std_logic; -- global reset line, sync, high-active
ice_i : in std_logic; -- interface clock enable, high-active
w_en_i : in std_logic; -- write enable
r_en_i : in std_logic; -- read enable
adr_i : in std_logic_vector(02 downto 0); -- access address
dat_i : in std_logic_vector(15 downto 0); -- write data
dat_o : out std_logic_vector(15 downto 0); -- read data
component com_0_core
port (
-- host interface --
clk_i : in std_ulogic; -- global clock line
rst_i : in std_ulogic; -- global reset line, sync, high-active
ice_i : in std_ulogic; -- interface clock enable, high-active
w_en_i : in std_ulogic; -- write enable
r_en_i : in std_ulogic; -- read enable
adr_i : in std_ulogic_vector(02 downto 0); -- access address
dat_i : in std_ulogic_vector(15 downto 0); -- write data
dat_o : out std_ulogic_vector(15 downto 0); -- read data
-- memory interface --
uart_rx_irq_o : out std_ulogic; -- uart irq "data available"
uart_tx_irq_o : out std_ulogic; -- uart irq "sending done"
spi_irq_o : out std_ulogic; -- spi irq "transfer done"
pio_irq_o : out std_ulogic; -- pio input pin change irq
-- io interface --
uart_txd_o : out std_ulogic; -- uart serial output
uart_rxd_i : in std_ulogic; -- uart serial input
spi_mosi_o : out std_ulogic_vector(07 downto 0); -- serial data out
spi_miso_i : in std_ulogic_vector(07 downto 0); -- serial data in
spi_sck_o : out std_ulogic_vector(07 downto 0); -- serial clock out
spi_cs_o : out std_ulogic_vector(07 downto 0); -- chip select (low active)
pio_in_i : in std_ulogic_vector(15 downto 0); -- parallel input
pio_out_o : out std_ulogic_vector(15 downto 0); -- parallel output
sys_io_i : in std_ulogic_vector(07 downto 0); -- system input
sys_io_o : out std_ulogic_vector(07 downto 0) -- system output
);
end component;
 
-- memory interface --
uart_rx_irq_o : out std_logic; -- uart irq "data available"
uart_tx_irq_o : out std_logic; -- uart irq "sending done"
spi_irq_o : out std_logic; -- spi irq "transfer done"
pio_irq_o : out std_logic; -- pio input pin change irq
 
-- io interface --
uart_txd_o : out std_logic; -- uart serial output
uart_rxd_i : in std_logic; -- uart serial input
spi_mosi_o : out std_logic_vector(07 downto 0); -- serial data out
spi_miso_i : in std_logic_vector(07 downto 0); -- serial data in
spi_sck_o : out std_logic_vector(07 downto 0); -- serial clock out
spi_cs_o : out std_logic_vector(07 downto 0); -- chip select (low active)
pio_in_i : in std_logic_vector(15 downto 0); -- parallel input
pio_out_o : out std_logic_vector(15 downto 0); -- parallel output
sys_io_i : in std_logic_vector(07 downto 0); -- system input
sys_io_o : out std_logic_vector(07 downto 0) -- system output
);
end component;
 
 
-- Component: Communication Controller Core 1 ---------------------------------------------
-- -------------------------------------------------------------------------------------------
component com_1_core
port (
-- host interface --
clk_i : in std_logic; -- global clock line
rst_i : in std_logic; -- global reset line, sync, high-active
ice_i : in std_logic; -- interface clock enable, high-active
w_en_i : in std_logic; -- write enable
r_en_i : in std_logic; -- read enable
cmd_exe_i : in std_logic; -- execute command
adr_i : in std_logic_vector(02 downto 0); -- access address/command
dat_i : in std_logic_vector(15 downto 0); -- write data
dat_o : out std_logic_vector(15 downto 0); -- read data
irq_o : out std_logic; -- interrupt request
component com_1_core
port (
-- host interface --
clk_i : in std_ulogic; -- global clock line
rst_i : in std_ulogic; -- global reset line, sync, high-active
ice_i : in std_ulogic; -- interface clock enable, high-active
w_en_i : in std_ulogic; -- write enable
r_en_i : in std_ulogic; -- read enable
cmd_exe_i : in std_ulogic; -- execute command
adr_i : in std_ulogic_vector(02 downto 0); -- access address/command
dat_i : in std_ulogic_vector(15 downto 0); -- write data
dat_o : out std_ulogic_vector(15 downto 0); -- read data
irq_o : out std_ulogic; -- interrupt request
-- wishbone bus --
wb_clk_o : out std_ulogic; -- bus clock
wb_rst_o : out std_ulogic; -- bus reset, sync, high active
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
wb_sel_o : out std_ulogic_vector(01 downto 0); -- byte select
wb_data_o : out std_ulogic_vector(15 downto 0); -- data out
wb_data_i : in std_ulogic_vector(15 downto 0); -- data in
wb_we_o : out std_ulogic; -- read/write
wb_cyc_o : out std_ulogic; -- cycle enable
wb_stb_o : out std_ulogic; -- strobe
wb_ack_i : in std_ulogic; -- acknowledge
wb_err_i : in std_ulogic -- bus error
);
end component;
 
-- wishbone bus --
wb_clk_o : out std_logic; -- bus clock
wb_rst_o : out std_logic; -- bus reset, sync, high active
wb_adr_o : out std_logic_vector(31 downto 0); -- address
wb_sel_o : out std_logic_vector(01 downto 0); -- byte select
wb_data_o : out std_logic_vector(15 downto 0); -- data out
wb_data_i : in std_logic_vector(15 downto 0); -- data in
wb_we_o : out std_logic; -- read/write
wb_cyc_o : out std_logic; -- cycle enable
wb_stb_o : out std_logic; -- strobe
wb_ack_i : in std_logic; -- acknowledge
wb_err_i : in std_logic -- bus error
);
end component;
 
 
-- Component: System Coprocessor ----------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component system_cp
generic (
-- configuration --
clock_speed_g : std_logic_vector(31 downto 0) -- clock speed in hz
);
port (
-- global control --
clk_i : in std_logic; -- global clock line
rst_i : in std_logic; -- global reset line, sync, high-active
ice_i : in std_logic; -- interface clock enable, high-active
component system_cp
generic (
-- configuration --
clock_speed_g : std_ulogic_vector(31 downto 0) -- clock speed in hz
);
port (
-- global control --
clk_i : in std_ulogic; -- global clock line
rst_i : in std_ulogic; -- global reset line, sync, high-active
ice_i : in std_ulogic; -- interface clock enable, high-active
-- processor interface --
cp_en_i : in std_ulogic; -- access coprocessor
cp_op_i : in std_ulogic; -- data transfer/processing
cp_rw_i : in std_ulogic; -- read/write access
cp_cmd_i : in std_ulogic_vector(cp_cmd_width_c-1 downto 0); -- register addresses / cmd
cp_dat_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write data
cp_dat_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data
cp_irq_o : out std_ulogic; -- unit interrupt request
sys_mode_i : in std_ulogic; -- current operating mode
int_exe_i : in std_ulogic; -- interrupt beeing executed
-- memory interface --
mem_ip_adr_o : out std_ulogic_vector(15 downto 0); -- instruction page
mem_dp_adr_o : out std_ulogic_vector(15 downto 0); -- data page
-- io interface --
uart_rxd_i : in std_ulogic; -- receiver input
uart_txd_o : out std_ulogic; -- uart transmitter output
spi_mosi_o : out std_ulogic_vector(07 downto 0); -- serial data out
spi_miso_i : in std_ulogic_vector(07 downto 0); -- serial data in
spi_sck_o : out std_ulogic_vector(07 downto 0); -- serial clock out
spi_cs_o : out std_ulogic_vector(07 downto 0); -- chip select (low active)
pio_out_o : out std_ulogic_vector(15 downto 0); -- parallel output
pio_in_i : in std_ulogic_vector(15 downto 0); -- parallel input
sys_out_o : out std_ulogic_vector(07 downto 0); -- system output
sys_in_i : in std_ulogic_vector(07 downto 0); -- system input
irq_i : in std_ulogic; -- irq
-- wishbone bus --
wb_clk_o : out std_ulogic; -- bus clock
wb_rst_o : out std_ulogic; -- bus reset, sync, high active
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
wb_sel_o : out std_ulogic_vector(01 downto 0); -- byte select
wb_data_o : out std_ulogic_vector(15 downto 0); -- data out
wb_data_i : in std_ulogic_vector(15 downto 0); -- data in
wb_we_o : out std_ulogic; -- read/write
wb_cyc_o : out std_ulogic; -- cycle enable
wb_stb_o : out std_ulogic; -- strobe
wb_ack_i : in std_ulogic; -- acknowledge
wb_err_i : in std_ulogic -- bus error
);
end component;
 
-- processor interface --
cp_en_i : in std_logic; -- access coprocessor
cp_op_i : in std_logic; -- data transfer/processing
cp_rw_i : in std_logic; -- read/write access
cp_cmd_i : in std_logic_vector(cp_cmd_width_c-1 downto 0); -- register addresses / cmd
cp_dat_i : in std_logic_vector(data_width_c-1 downto 0); -- write data
cp_dat_o : out std_logic_vector(data_width_c-1 downto 0); -- read data
cp_irq_o : out std_logic; -- unit interrupt request
sys_mode_i : in std_logic; -- current operating mode
int_exe_i : in std_logic; -- interrupt beeing executed
 
-- memory interface --
mem_ip_adr_o : out std_logic_vector(15 downto 0); -- instruction page
mem_dp_adr_o : out std_logic_vector(15 downto 0); -- data page
 
-- io interface --
uart_rxd_i : in std_logic; -- receiver input
uart_txd_o : out std_logic; -- uart transmitter output
spi_mosi_o : out std_logic_vector(07 downto 0); -- serial data out
spi_miso_i : in std_logic_vector(07 downto 0); -- serial data in
spi_sck_o : out std_logic_vector(07 downto 0); -- serial clock out
spi_cs_o : out std_logic_vector(07 downto 0); -- chip select (low active)
pio_out_o : out std_logic_vector(15 downto 0); -- parallel output
pio_in_i : in std_logic_vector(15 downto 0); -- parallel input
sys_out_o : out std_logic_vector(07 downto 0); -- system output
sys_in_i : in std_logic_vector(07 downto 0); -- system input
irq_i : in std_logic; -- irq
 
-- wishbone bus --
wb_clk_o : out std_logic; -- bus clock
wb_rst_o : out std_logic; -- bus reset, sync, high active
wb_adr_o : out std_logic_vector(31 downto 0); -- address
wb_sel_o : out std_logic_vector(01 downto 0); -- byte select
wb_data_o : out std_logic_vector(15 downto 0); -- data out
wb_data_i : in std_logic_vector(15 downto 0); -- data in
wb_we_o : out std_logic; -- read/write
wb_cyc_o : out std_logic; -- cycle enable
wb_stb_o : out std_logic; -- strobe
wb_ack_i : in std_logic; -- acknowledge
wb_err_i : in std_logic -- bus error
);
end component;
 
 
-- Component: memory gateway --------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component mem_gate
port (
-- host interface --
clk_i : in std_logic; -- global clock line
rst_i : in std_logic; -- global reset line, sync, high-active
component mem_gate
port (
-- host interface --
clk_i : in std_ulogic; -- global clock line
rst_i : in std_ulogic; -- global reset line, sync, high-active
i_adr_i : in std_ulogic_vector(15 downto 0); -- instruction adr
i_dat_o : out std_ulogic_vector(15 downto 0); -- instruction out
d_req_i : in std_ulogic; -- request access in next cycle
d_rw_i : in std_ulogic; -- read/write
d_adr_i : in std_ulogic_vector(15 downto 0); -- data adr
d_dat_i : in std_ulogic_vector(15 downto 0); -- data in
d_dat_o : out std_ulogic_vector(15 downto 0); -- data out
mem_ip_adr_i : in std_ulogic_vector(15 downto 0); -- instruction page
mem_dp_adr_i : in std_ulogic_vector(15 downto 0); -- data page
-- boot rom interface --
boot_i_adr_o : out std_ulogic_vector(15 downto 0); -- instruction adr
boot_i_dat_i : in std_ulogic_vector(15 downto 0); -- instruction out
boot_d_en_o : out std_ulogic; -- access enable
boot_d_rw_o : out std_ulogic; -- read/write
boot_d_adr_o : out std_ulogic_vector(15 downto 0); -- data adr
boot_d_dat_o : out std_ulogic_vector(15 downto 0); -- data in
boot_d_dat_i : in std_ulogic_vector(15 downto 0); -- data out
-- memory interface --
mem_i_page_o : out std_ulogic_vector(15 downto 0); -- instruction page
mem_i_adr_o : out std_ulogic_vector(15 downto 0); -- instruction adr
mem_i_dat_i : in std_ulogic_vector(15 downto 0); -- instruction out
mem_d_en_o : out std_ulogic; -- access enable
mem_d_rw_o : out std_ulogic; -- read/write
mem_d_page_o : out std_ulogic_vector(15 downto 0); -- data page
mem_d_adr_o : out std_ulogic_vector(15 downto 0); -- data adr
mem_d_dat_o : out std_ulogic_vector(15 downto 0); -- data in
mem_d_dat_i : in std_ulogic_vector(15 downto 0) -- data out
);
end component;
 
i_adr_i : in std_logic_vector(15 downto 0); -- instruction adr
i_dat_o : out std_logic_vector(15 downto 0); -- instruction out
d_req_i : in std_logic; -- request access in next cycle
d_rw_i : in std_logic; -- read/write
d_adr_i : in std_logic_vector(15 downto 0); -- data adr
d_dat_i : in std_logic_vector(15 downto 0); -- data in
d_dat_o : out std_logic_vector(15 downto 0); -- data out
mem_ip_adr_i : in std_logic_vector(15 downto 0); -- instruction page
mem_dp_adr_i : in std_logic_vector(15 downto 0); -- data page
 
-- boot rom interface --
boot_i_adr_o : out std_logic_vector(15 downto 0); -- instruction adr
boot_i_dat_i : in std_logic_vector(15 downto 0); -- instruction out
boot_d_en_o : out std_logic; -- access enable
boot_d_rw_o : out std_logic; -- read/write
boot_d_adr_o : out std_logic_vector(15 downto 0); -- data adr
boot_d_dat_o : out std_logic_vector(15 downto 0); -- data in
boot_d_dat_i : in std_logic_vector(15 downto 0); -- data out
 
-- memory interface --
mem_i_page_o : out std_logic_vector(15 downto 0); -- instruction page
mem_i_adr_o : out std_logic_vector(15 downto 0); -- instruction adr
mem_i_dat_i : in std_logic_vector(15 downto 0); -- instruction out
mem_d_en_o : out std_logic; -- access enable
mem_d_rw_o : out std_logic; -- read/write
mem_d_page_o : out std_logic_vector(15 downto 0); -- data page
mem_d_adr_o : out std_logic_vector(15 downto 0); -- data adr
mem_d_dat_o : out std_logic_vector(15 downto 0); -- data in
mem_d_dat_i : in std_logic_vector(15 downto 0) -- data out
);
end component;
 
 
-- Component: Bootloader Memory -----------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component boot_mem
port (
-- host interface --
clk_i : in std_logic; -- global clock line
i_adr_i : in std_logic_vector(15 downto 0); -- instruction adr
i_dat_o : out std_logic_vector(15 downto 0); -- instruction out
d_en_i : in std_logic; -- access enable
d_rw_i : in std_logic; -- read/write
d_adr_i : in std_logic_vector(15 downto 0); -- data adr
d_dat_i : in std_logic_vector(15 downto 0); -- data in
d_dat_o : out std_logic_vector(15 downto 0) -- data out
);
end component;
component boot_mem
port (
-- host interface --
clk_i : in std_ulogic; -- global clock line
i_adr_i : in std_ulogic_vector(15 downto 0); -- instruction adr
i_dat_o : out std_ulogic_vector(15 downto 0); -- instruction out
d_en_i : in std_ulogic; -- access enable
d_rw_i : in std_ulogic; -- read/write
d_adr_i : in std_ulogic_vector(15 downto 0); -- data adr
d_dat_i : in std_ulogic_vector(15 downto 0); -- data in
d_dat_o : out std_ulogic_vector(15 downto 0) -- data out
);
end component;
 
end atlas_core_package;
 
811,7 → 803,6
-- Function: Logarithm Base 2 -------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
function log2(temp : natural) return natural is
variable result : natural;
begin
for i in 0 to integer'high loop
if (2**i >= temp) then
/rtl/COM_0_CORE.vhd
24,38 → 24,38
-- ## Host Interface ##
-- ###############################################################################################
 
clk_i : in std_logic; -- global clock line
rst_i : in std_logic; -- global reset line, sync, high-active
ice_i : in std_logic; -- interface clock enable, high-active
w_en_i : in std_logic; -- write enable
r_en_i : in std_logic; -- read enable
adr_i : in std_logic_vector(02 downto 0); -- access address
dat_i : in std_logic_vector(15 downto 0); -- write data
dat_o : out std_logic_vector(15 downto 0); -- read data
clk_i : in std_ulogic; -- global clock line
rst_i : in std_ulogic; -- global reset line, sync, high-active
ice_i : in std_ulogic; -- interface clock enable, high-active
w_en_i : in std_ulogic; -- write enable
r_en_i : in std_ulogic; -- read enable
adr_i : in std_ulogic_vector(02 downto 0); -- access address
dat_i : in std_ulogic_vector(15 downto 0); -- write data
dat_o : out std_ulogic_vector(15 downto 0); -- read data
 
-- ###############################################################################################
-- ## Interrupt Lines ##
-- ###############################################################################################
 
uart_rx_irq_o : out std_logic; -- uart irq "data available"
uart_tx_irq_o : out std_logic; -- uart irq "sending done"
spi_irq_o : out std_logic; -- spi irq "transfer done"
pio_irq_o : out std_logic; -- pio input pin change irq
uart_rx_irq_o : out std_ulogic; -- uart irq "data available"
uart_tx_irq_o : out std_ulogic; -- uart irq "sending done"
spi_irq_o : out std_ulogic; -- spi irq "transfer done"
pio_irq_o : out std_ulogic; -- pio input pin change irq
 
-- ###############################################################################################
-- ## Communication Lines ##
-- ###############################################################################################
 
uart_txd_o : out std_logic; -- uart serial output
uart_rxd_i : in std_logic; -- uart serial input
spi_mosi_o : out std_logic_vector(07 downto 0); -- serial data out
spi_miso_i : in std_logic_vector(07 downto 0); -- serial data in
spi_sck_o : out std_logic_vector(07 downto 0); -- serial clock out
spi_cs_o : out std_logic_vector(07 downto 0); -- chip select (low active)
pio_in_i : in std_logic_vector(15 downto 0); -- parallel input
pio_out_o : out std_logic_vector(15 downto 0); -- parallel output
sys_io_i : in std_logic_vector(07 downto 0); -- system input
sys_io_o : out std_logic_vector(07 downto 0) -- system output
uart_txd_o : out std_ulogic; -- uart serial output
uart_rxd_i : in std_ulogic; -- uart serial input
spi_mosi_o : out std_ulogic_vector(07 downto 0); -- serial data out
spi_miso_i : in std_ulogic_vector(07 downto 0); -- serial data in
spi_sck_o : out std_ulogic_vector(07 downto 0); -- serial clock out
spi_cs_o : out std_ulogic_vector(07 downto 0); -- chip select (low active)
pio_in_i : in std_ulogic_vector(15 downto 0); -- parallel input
pio_out_o : out std_ulogic_vector(15 downto 0); -- parallel output
sys_io_i : in std_ulogic_vector(07 downto 0); -- system input
sys_io_o : out std_ulogic_vector(07 downto 0) -- system output
);
end com_0_core;
 
62,89 → 62,89
architecture com_0_core_behav of com_0_core is
 
-- Module Addresses --
constant uart_rtx_sd_reg_c : std_logic_vector(02 downto 0) := "000"; -- R/W: UART RTX data + status flags
constant uart_prsc_reg_c : std_logic_vector(02 downto 0) := "001"; -- R/W: UART prescaler register
constant com_ctrl_reg_c : std_logic_vector(02 downto 0) := "010"; -- R/W: COM control register
constant spi_data_reg_c : std_logic_vector(02 downto 0) := "011"; -- R/W: SPI RTX data register
constant spi_cs_reg_c : std_logic_vector(02 downto 0) := "100"; -- R/W: SPI chip select register
constant pio_in_reg_c : std_logic_vector(02 downto 0) := "101"; -- R: PIO input register
constant pio_out_reg_c : std_logic_vector(02 downto 0) := "110"; -- R/W: PIO output register
constant sys_io_reg_c : std_logic_vector(02 downto 0) := "111"; -- R/W: System parallel in/out
constant uart_rtx_sd_reg_c : std_ulogic_vector(02 downto 0) := "000"; -- R/W: UART RTX data + status flags
constant uart_prsc_reg_c : std_ulogic_vector(02 downto 0) := "001"; -- R/W: UART prescaler register
constant com_ctrl_reg_c : std_ulogic_vector(02 downto 0) := "010"; -- R/W: COM control register
constant spi_data_reg_c : std_ulogic_vector(02 downto 0) := "011"; -- R/W: SPI RTX data register
constant spi_cs_reg_c : std_ulogic_vector(02 downto 0) := "100"; -- R/W: SPI chip select register
constant pio_in_reg_c : std_ulogic_vector(02 downto 0) := "101"; -- R: PIO input register
constant pio_out_reg_c : std_ulogic_vector(02 downto 0) := "110"; -- R/W: PIO output register
constant sys_io_reg_c : std_ulogic_vector(02 downto 0) := "111"; -- R/W: System parallel in/out
 
-- CTRL Register --
constant spi_cr_dir_flag_c : natural := 0; -- R/W: 0: MSB first, 1: LSB first
constant spi_cr_cpol_c : natural := 1; -- R/W: clock polarity, 1: idle '1' clock, 0: idle '0' clock
constant spi_cr_cpha_c : natural := 2; -- R/W: edge offset: 0: first edge, 1: second edge
constant spi_cr_bsy_c : natural := 3; -- R: transceiver is busy when '1'
constant spi_cr_auto_cs_c : natural := 4; -- R/W: Auto apply CS when '1'
constant uart_tx_busy_c : natural := 5; -- R: UART transmitter is busy
constant uart_en_c : natural := 6; -- R/W: UART enable
constant uart_ry_ovf_c : natural := 7; -- R: UART Rx overflow corruption
constant spi_cr_ln_lsb_c : natural := 8; -- R/W: data length lsb
constant spi_cr_ln_msb_c : natural := 11; -- R/W: data length msb
constant spi_cr_prsc_lsb_c : natural := 12; -- R/W: SPI clock prescaler lsb
constant spi_cr_prsc_msb_c : natural := 15; -- R/W: SPI clock prescaler msb
constant spi_cr_dir_flag_c : natural := 0; -- R/W: 0: MSB first, 1: LSB first
constant spi_cr_cpol_c : natural := 1; -- R/W: clock polarity, 1: idle '1' clock, 0: idle '0' clock
constant spi_cr_cpha_c : natural := 2; -- R/W: edge offset: 0: first edge, 1: second edge
constant spi_cr_bsy_c : natural := 3; -- R: transceiver is busy when '1'
constant spi_cr_auto_cs_c : natural := 4; -- R/W: Auto apply CS when '1'
constant uart_tx_busy_c : natural := 5; -- R: UART transmitter is busy
constant uart_en_c : natural := 6; -- R/W: UART enable
constant uart_ry_ovf_c : natural := 7; -- R: UART Rx overflow corruption
constant spi_cr_ln_lsb_c : natural := 8; -- R/W: data length lsb
constant spi_cr_ln_msb_c : natural := 11; -- R/W: data length msb
constant spi_cr_prsc_lsb_c : natural := 12; -- R/W: SPI clock prescaler lsb
constant spi_cr_prsc_msb_c : natural := 15; -- R/W: SPI clock prescaler msb
 
-- UART Control Flags (UART RTX REG) --
constant uart_rx_ready_c : natural := 15; -- R: Data received
constant uart_rx_ready_c : natural := 15; -- R: Data received
 
-- uart registers --
signal uart_rx_reg : std_logic_vector(07 downto 0);
signal uart_prsc_reg : std_logic_vector(15 downto 0);
signal uart_rx_reg : std_ulogic_vector(07 downto 0);
signal uart_prsc_reg : std_ulogic_vector(15 downto 0);
 
-- uart transceiver --
signal uart_rx_sync : std_logic_vector(03 downto 0);
signal uart_tx_bsy_flag : std_logic;
signal uart_dcor_flag : std_logic;
signal uart_rx_bsy_flag : std_logic;
signal uart_tx_sreg : std_logic_vector(09 downto 0);
signal uart_rx_sreg : std_logic_vector(09 downto 0);
signal uart_tx_bit_cnt : std_logic_vector(03 downto 0);
signal uart_rx_bit_cnt : std_logic_vector(03 downto 0);
signal uart_tx_baud_cnt : std_logic_vector(15 downto 0);
signal uart_rx_baud_cnt : std_logic_vector(15 downto 0);
signal uart_rx_ready : std_logic;
signal uart_rx_ready_sync : std_logic;
signal uart_rx_sync : std_ulogic_vector(03 downto 0);
signal uart_tx_bsy_flag : std_ulogic;
signal uart_dcor_flag : std_ulogic;
signal uart_rx_bsy_flag : std_ulogic;
signal uart_tx_sreg : std_ulogic_vector(09 downto 0);
signal uart_rx_sreg : std_ulogic_vector(09 downto 0);
signal uart_tx_bit_cnt : std_ulogic_vector(03 downto 0);
signal uart_rx_bit_cnt : std_ulogic_vector(03 downto 0);
signal uart_tx_baud_cnt : std_ulogic_vector(15 downto 0);
signal uart_rx_baud_cnt : std_ulogic_vector(15 downto 0);
signal uart_rx_ready : std_ulogic;
signal uart_rx_ready_sync : std_ulogic;
 
-- spi registers --
signal spi_tx_reg : std_logic_vector(15 downto 0);
signal spi_rx_reg : std_logic_vector(15 downto 0);
signal spi_rx_reg_nxt : std_logic_vector(15 downto 0);
signal spi_cs_reg : std_logic_vector(07 downto 0);
signal com_config_reg : std_logic_vector(15 downto 0);
signal spi_tx_reg : std_ulogic_vector(15 downto 0);
signal spi_rx_reg : std_ulogic_vector(15 downto 0);
signal spi_rx_reg_nxt : std_ulogic_vector(15 downto 0);
signal spi_cs_reg : std_ulogic_vector(07 downto 0);
signal com_config_reg : std_ulogic_vector(15 downto 0);
 
-- spi transceiver --
signal spi_in_buf : std_logic_vector(01 downto 0);
signal spi_mosi_nxt : std_logic;
signal spi_sck_nxt : std_logic;
signal spi_mosi_ff : std_logic;
signal spi_cs_ff : std_logic_vector(07 downto 0);
signal spi_cs_ff_nxt : std_logic_vector(07 downto 0);
signal spi_irq : std_logic;
signal spi_in_buf : std_ulogic_vector(01 downto 0);
signal spi_mosi_nxt : std_ulogic;
signal spi_sck_nxt : std_ulogic;
signal spi_mosi_ff : std_ulogic;
signal spi_cs_ff : std_ulogic_vector(07 downto 0);
signal spi_cs_ff_nxt : std_ulogic_vector(07 downto 0);
signal spi_irq : std_ulogic;
 
-- spi arbiter --
type spi_arb_state_type is (idle, start_trans, transmit_0, transmit_1, finish);
signal spi_arb_state : spi_arb_state_type;
signal spi_arb_state_nxt : spi_arb_state_type;
signal spi_bit_cnt : std_logic_vector(04 downto 0);
signal spi_bit_cnt_nxt : std_logic_vector(04 downto 0);
signal spi_rx_sft : std_logic_vector(15 downto 0); -- rx shift registers
signal spi_rx_sft_nxt : std_logic_vector(15 downto 0); -- rx shift registers
signal spi_tx_sft : std_logic_vector(15 downto 0); -- tx shift registers
signal spi_tx_sft_nxt : std_logic_vector(15 downto 0); -- tx shift registers
signal spi_prsc_cnt : std_logic_vector(15 downto 0);
signal spi_prsc_cnt_nxt : std_logic_vector(15 downto 0);
signal spi_busy_flag : std_logic;
signal spi_busy_flag_nxt : std_logic;
signal spi_sck_ff : std_logic;
signal spi_miso : std_logic;
signal spi_arb_state : spi_arb_state_type;
signal spi_arb_state_nxt : spi_arb_state_type;
signal spi_bit_cnt : std_ulogic_vector(04 downto 0);
signal spi_bit_cnt_nxt : std_ulogic_vector(04 downto 0);
signal spi_rx_sft : std_ulogic_vector(15 downto 0); -- rx shift registers
signal spi_rx_sft_nxt : std_ulogic_vector(15 downto 0); -- rx shift registers
signal spi_tx_sft : std_ulogic_vector(15 downto 0); -- tx shift registers
signal spi_tx_sft_nxt : std_ulogic_vector(15 downto 0); -- tx shift registers
signal spi_prsc_cnt : std_ulogic_vector(15 downto 0);
signal spi_prsc_cnt_nxt : std_ulogic_vector(15 downto 0);
signal spi_busy_flag : std_ulogic;
signal spi_busy_flag_nxt : std_ulogic;
signal spi_sck_ff : std_ulogic;
signal spi_miso : std_ulogic;
 
-- pio registers --
signal pio_out_data : std_logic_vector(15 downto 0);
signal pio_in_data : std_logic_vector(15 downto 0);
signal pio_sync : std_logic_vector(15 downto 0);
signal sys_io_i_ff : std_logic_vector(07 downto 0);
signal sys_io_o_ff : std_logic_vector(07 downto 0);
signal pio_out_data : std_ulogic_vector(15 downto 0);
signal pio_in_data : std_ulogic_vector(15 downto 0);
signal pio_sync : std_ulogic_vector(15 downto 0);
signal sys_io_i_ff : std_ulogic_vector(07 downto 0);
signal sys_io_o_ff : std_ulogic_vector(07 downto 0);
 
begin
 
190,7 → 190,6
pio_irq_o <= '0' when (pio_sync = pio_in_data) else '1';
 
 
 
-- Read Access -----------------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
r_acc: process(adr_i, uart_tx_bsy_flag, uart_rx_ready, uart_rx_reg, uart_prsc_reg, com_config_reg, sys_io_o_ff,
215,7 → 214,6
end process r_acc;
 
 
 
-- UART Flag Arbiter -----------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
uart_flag_ctrl: process(clk_i)
244,7 → 242,6
uart_tx_irq_o <= not uart_tx_bsy_flag;
 
 
 
-- Transmitter Unit ------------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
uart_transmitter: process(clk_i)
276,12 → 273,12
uart_tx_baud_cnt <= uart_prsc_reg;
if (uart_tx_bit_cnt /= "0000") then
uart_tx_sreg <= '1' & uart_tx_sreg(9 downto 1);
uart_tx_bit_cnt <= std_logic_vector(unsigned(uart_tx_bit_cnt) - 1);
uart_tx_bit_cnt <= std_ulogic_vector(unsigned(uart_tx_bit_cnt) - 1);
else
uart_tx_bsy_flag <= '0'; -- done
end if;
else
uart_tx_baud_cnt <= std_logic_vector(unsigned(uart_tx_baud_cnt) - 1);
uart_tx_baud_cnt <= std_ulogic_vector(unsigned(uart_tx_baud_cnt) - 1);
end if;
end if;
end if;
292,7 → 289,6
uart_txd_o <= uart_tx_sreg(0);
 
 
 
-- UART Receiver Unit ----------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
uart_receiver: process(clk_i)
332,13 → 328,13
uart_rx_baud_cnt <= uart_prsc_reg;
if (uart_rx_bit_cnt /= "0000") then
uart_rx_sreg <= uart_rx_sync(0) & uart_rx_sreg(9 downto 1);
uart_rx_bit_cnt <= std_logic_vector(unsigned(uart_rx_bit_cnt) - 1);
uart_rx_bit_cnt <= std_ulogic_vector(unsigned(uart_rx_bit_cnt) - 1);
else
uart_rx_bsy_flag <= '0'; -- done
uart_rx_reg <= uart_rx_sreg(9 downto 2);
end if;
else
uart_rx_baud_cnt <= std_logic_vector(unsigned(uart_rx_baud_cnt) - 1);
uart_rx_baud_cnt <= std_ulogic_vector(unsigned(uart_rx_baud_cnt) - 1);
end if;
end if;
end if;
346,7 → 342,6
end process uart_receiver;
 
 
 
-- SPI Transceiver Unit --------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
spi_arb_sync: process(clk_i)
387,10 → 382,9
end process spi_arb_sync;
 
 
 
spi_arb_comb: process(spi_arb_state, com_config_reg, spi_rx_sft, spi_tx_sft, spi_bit_cnt, spi_prsc_cnt, spi_in_buf,
spi_rx_reg, spi_mosi_ff, spi_cs_ff, spi_cs_reg, spi_tx_reg, w_en_i, adr_i, spi_busy_flag, ice_i)
variable prsc_match_v : std_logic;
variable prsc_match_v : std_ulogic;
begin
-- defaults --
spi_arb_state_nxt <= spi_arb_state; -- arbiter state
427,7 → 421,7
 
when transmit_0 => -- first half of bit transmission
spi_cs_ff_nxt <= spi_cs_ff; -- keep cs alive
spi_prsc_cnt_nxt <= std_logic_vector(unsigned(spi_prsc_cnt) + 1);
spi_prsc_cnt_nxt <= std_ulogic_vector(unsigned(spi_prsc_cnt) + 1);
spi_sck_nxt <= com_config_reg(spi_cr_cpol_c) xor com_config_reg(spi_cr_cpha_c);
if (com_config_reg(spi_cr_dir_flag_c) = '0') then -- msb first
spi_mosi_nxt <= spi_tx_sft(to_integer(unsigned(com_config_reg(spi_cr_ln_msb_c downto spi_cr_ln_lsb_c))));
441,10 → 435,10
 
when transmit_1 => -- second half of bit transmission
spi_cs_ff_nxt <= spi_cs_ff; -- keep cs alive
spi_prsc_cnt_nxt <= std_logic_vector(unsigned(spi_prsc_cnt) + 1);
spi_prsc_cnt_nxt <= std_ulogic_vector(unsigned(spi_prsc_cnt) + 1);
spi_sck_nxt <= not (com_config_reg(spi_cr_cpol_c) xor com_config_reg(spi_cr_cpha_c));
if (prsc_match_v = '1') then -- second half completed
spi_bit_cnt_nxt <= std_logic_vector(unsigned(spi_bit_cnt) + 1);
spi_bit_cnt_nxt <= std_ulogic_vector(unsigned(spi_bit_cnt) + 1);
spi_prsc_cnt_nxt <= (others => '0');
if (com_config_reg(spi_cr_dir_flag_c) = '0') then -- msb first
spi_tx_sft_nxt <= spi_tx_sft(14 downto 0) & '0'; -- left shift
474,8 → 468,8
 
-- spi io interface --
spi_io: process(spi_cs_ff, spi_mosi_ff, spi_sck_ff, spi_miso_i)
variable spi_miso_bus_v : std_logic_vector(7 downto 0);
variable spi_miso_v : std_logic;
variable spi_miso_bus_v : std_ulogic_vector(7 downto 0);
variable spi_miso_v : std_ulogic;
begin
spi_miso_bus_v := spi_miso_i and (not spi_cs_ff);
spi_miso_v := '0';
/rtl/SYS_0_CORE.vhd
23,22 → 23,22
-- ## Host Interface ##
-- ###############################################################################################
 
clk_i : in std_logic; -- global clock line
rst_i : in std_logic; -- global reset line, sync, high-active
ice_i : in std_logic; -- interface clock enable, high-active
w_en_i : in std_logic; -- write enable
r_en_i : in std_logic; -- read enable
adr_i : in std_logic_vector(02 downto 0); -- access address
dat_i : in std_logic_vector(15 downto 0); -- write data
dat_o : out std_logic_vector(15 downto 0); -- read data
clk_i : in std_ulogic; -- global clock line
rst_i : in std_ulogic; -- global reset line, sync, high-active
ice_i : in std_ulogic; -- interface clock enable, high-active
w_en_i : in std_ulogic; -- write enable
r_en_i : in std_ulogic; -- read enable
adr_i : in std_ulogic_vector(02 downto 0); -- access address
dat_i : in std_ulogic_vector(15 downto 0); -- write data
dat_o : out std_ulogic_vector(15 downto 0); -- read data
 
-- ###############################################################################################
-- ## Interrupt Lines ##
-- ###############################################################################################
 
timer_irq_o : out std_logic; -- timer irq
irq_i : in std_logic_vector(07 downto 0); -- irq input
irq_o : out std_logic -- interrupt request
timer_irq_o : out std_ulogic; -- timer irq
irq_i : in std_ulogic_vector(07 downto 0); -- irq input
irq_o : out std_ulogic -- interrupt request
);
end sys_0_core;
 
45,48 → 45,48
architecture sys_0_core_behav of sys_0_core is
 
-- Module Addresses --
constant irq_sm_reg_c : std_logic_vector(02 downto 0) := "000"; -- R/W: Interrupt source and mask
constant irq_conf_reg_c : std_logic_vector(02 downto 0) := "001"; -- R/W: Interrupt type configuration
constant irq_sm_reg_c : std_ulogic_vector(02 downto 0) := "000"; -- R/W: Interrupt source and mask
constant irq_conf_reg_c : std_ulogic_vector(02 downto 0) := "001"; -- R/W: Interrupt type configuration
-- lo byte: '1': level triggered, '0': edge triggered
-- hi byte: '1': high level/rising edge, '0': low level/falling edge
constant timer_cnt_reg_c : std_logic_vector(02 downto 0) := "010"; -- R/W: Timer counter register
constant timer_thr_reg_c : std_logic_vector(02 downto 0) := "011"; -- R/W: Timer threshold register
constant timer_prsc_reg_c : std_logic_vector(02 downto 0) := "100"; -- R/W: Timer prescaler register
constant lfsr_data_reg_c : std_logic_vector(02 downto 0) := "101"; -- R/W: LFSR data register
constant lfsr_poly_reg_c : std_logic_vector(02 downto 0) := "110"; -- R/W: LFSR polynomial register
constant timer_cnt_reg_c : std_ulogic_vector(02 downto 0) := "010"; -- R/W: Timer counter register
constant timer_thr_reg_c : std_ulogic_vector(02 downto 0) := "011"; -- R/W: Timer threshold register
constant timer_prsc_reg_c : std_ulogic_vector(02 downto 0) := "100"; -- R/W: Timer prescaler register
constant lfsr_data_reg_c : std_ulogic_vector(02 downto 0) := "101"; -- R/W: LFSR data register
constant lfsr_poly_reg_c : std_ulogic_vector(02 downto 0) := "110"; -- R/W: LFSR polynomial register
-- bit 15: '0' new value after read access, '1' free running mode
constant reserved_reg_c : std_logic_vector(02 downto 0) := "111"; -- RESERVED
constant reserved_reg_c : std_ulogic_vector(02 downto 0) := "111"; -- RESERVED
 
-- IRQ Registers --
signal irq_mask_reg : std_logic_vector(07 downto 0);
signal irq_source_reg : std_logic_vector(02 downto 0);
signal irq_conf_reg : std_logic_vector(15 downto 0);
signal irq_mask_reg : std_ulogic_vector(07 downto 0);
signal irq_source_reg : std_ulogic_vector(02 downto 0);
signal irq_conf_reg : std_ulogic_vector(15 downto 0);
 
-- Internals --
signal irq_sync_0 : std_logic_vector(07 downto 0);
signal irq_sync_1 : std_logic_vector(07 downto 0);
signal irq_raw_req : std_logic_vector(07 downto 0);
signal irq_buf : std_logic_vector(07 downto 0);
signal irq_id : std_logic_vector(02 downto 0);
signal irq_ack_mask : std_logic_vector(07 downto 0);
signal irq_ack_mask_ff : std_logic_vector(07 downto 0);
signal irq_lock : std_logic;
signal irq_sync_0 : std_ulogic_vector(07 downto 0);
signal irq_sync_1 : std_ulogic_vector(07 downto 0);
signal irq_raw_req : std_ulogic_vector(07 downto 0);
signal irq_buf : std_ulogic_vector(07 downto 0);
signal irq_id : std_ulogic_vector(02 downto 0);
signal irq_ack_mask : std_ulogic_vector(07 downto 0);
signal irq_ack_mask_ff : std_ulogic_vector(07 downto 0);
signal irq_lock : std_ulogic;
 
-- Timer Registers --
signal tmr_cnt_reg : std_logic_vector(15 downto 0);
signal tmr_thr_reg : std_logic_vector(15 downto 0);
signal tmr_prsc_reg : std_logic_vector(15 downto 0);
signal tmr_prsc_cnt : std_logic_vector(15 downto 0);
signal tmr_cnt_reg : std_ulogic_vector(15 downto 0);
signal tmr_thr_reg : std_ulogic_vector(15 downto 0);
signal tmr_prsc_reg : std_ulogic_vector(15 downto 0);
signal tmr_prsc_cnt : std_ulogic_vector(15 downto 0);
 
-- Timer Signals --
signal tmr_prsc_match : std_logic;
signal tmr_thres_zero : std_logic;
signal tmr_prsc_match : std_ulogic;
signal tmr_thres_zero : std_ulogic;
 
-- LFSR Registers --
signal lfsr_data : std_logic_vector(15 downto 0);
signal lfsr_poly : std_logic_vector(15 downto 0);
signal lfsr_new : std_logic_vector(15 downto 0);
signal lfsr_noise : std_logic;
signal lfsr_data : std_ulogic_vector(15 downto 0);
signal lfsr_poly : std_ulogic_vector(15 downto 0);
signal lfsr_new : std_ulogic_vector(15 downto 0);
signal lfsr_noise : std_ulogic;
 
begin
 
132,12 → 132,12
if (tmr_prsc_match = '1') or (tmr_thres_zero = '1') then -- prescaler increment
tmr_prsc_cnt <= (others => '0');
else
tmr_prsc_cnt <= std_logic_vector(unsigned(tmr_prsc_cnt) + 1);
tmr_prsc_cnt <= std_ulogic_vector(unsigned(tmr_prsc_cnt) + 1);
end if;
if (tmr_cnt_reg = tmr_thr_reg) then -- counter increment
tmr_cnt_reg <= (others => '0');
elsif (tmr_thres_zero = '0') and (tmr_prsc_match = '1') then
tmr_cnt_reg <= std_logic_vector(unsigned(tmr_cnt_reg) + 1);
tmr_cnt_reg <= std_ulogic_vector(unsigned(tmr_cnt_reg) + 1);
end if;
end if;
 
171,7 → 171,6
timer_irq_o <= '1' when ((tmr_cnt_reg = tmr_thr_reg) and (tmr_thres_zero = '0')) else '0';
 
 
 
-- Read Access -----------------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
r_acc: process(adr_i, irq_mask_reg, irq_conf_reg, irq_source_reg, tmr_cnt_reg, tmr_thr_reg,
190,7 → 189,6
end process r_acc;
 
 
 
-- Interrupt Detector ----------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
irq_detector: process(irq_mask_reg, irq_conf_reg, irq_sync_0, irq_sync_1)
213,7 → 211,6
end process irq_detector;
 
 
 
-- Interrupt Request Buffer ----------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
irq_buffer: process(clk_i)
246,7 → 243,6
irq_o <= irq_lock;
 
 
 
-- Interrupt Priority Encoder --------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
irq_pr_enc: process(irq_buf)
255,7 → 251,7
irq_ack_mask <= (others => '0');
for i in 0 to 7 loop
if (irq_buf(i) = '1') then
irq_id <= std_logic_vector(to_unsigned(i,3));
irq_id <= std_ulogic_vector(to_unsigned(i,3));
irq_ack_mask(i) <= '1';
exit;
end if;
263,7 → 259,6
end process irq_pr_enc;
 
 
 
-- LFSR Update -----------------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
lfsr_update: process(lfsr_data, lfsr_poly, lfsr_noise)
/rtl/SYS_1_CORE.vhd
21,7 → 21,7
-- ## Clock Speed Configuration ##
-- ###############################################################################################
generic (
clk_speed_g : std_logic_vector(31 downto 0) := (others => '0') -- clock speed (in Hz)
clk_speed_g : std_ulogic_vector(31 downto 0) := (others => '0') -- clock speed (in Hz)
);
port (
-- ###############################################################################################
28,24 → 28,24
-- ## Host Interface ##
-- ###############################################################################################
 
clk_i : in std_logic; -- global clock line
rst_i : in std_logic; -- global reset line, sync, high-active
ice_i : in std_logic; -- interface clock enable, high-active
w_en_i : in std_logic; -- write enable
r_en_i : in std_logic; -- read enable
adr_i : in std_logic_vector(02 downto 0); -- access address
dat_i : in std_logic_vector(15 downto 0); -- write data
dat_o : out std_logic_vector(15 downto 0); -- read data
clk_i : in std_ulogic; -- global clock line
rst_i : in std_ulogic; -- global reset line, sync, high-active
ice_i : in std_ulogic; -- interface clock enable, high-active
w_en_i : in std_ulogic; -- write enable
r_en_i : in std_ulogic; -- read enable
adr_i : in std_ulogic_vector(02 downto 0); -- access address
dat_i : in std_ulogic_vector(15 downto 0); -- write data
dat_o : out std_ulogic_vector(15 downto 0); -- read data
 
sys_mode_i : in std_logic; -- current operating mode
int_exe_i : in std_logic; -- interrupt beeing executed
sys_mode_i : in std_ulogic; -- current operating mode
int_exe_i : in std_ulogic; -- interrupt beeing executed
 
-- ###############################################################################################
-- ## Memory Interface ##
-- ###############################################################################################
 
mem_ip_adr_o : out std_logic_vector(15 downto 0); -- instruction page
mem_dp_adr_o : out std_logic_vector(15 downto 0) -- data page
mem_ip_adr_o : out std_ulogic_vector(15 downto 0); -- instruction page
mem_dp_adr_o : out std_ulogic_vector(15 downto 0) -- data page
);
end sys_1_core;
 
52,33 → 52,33
architecture sys_1_core_behav of sys_1_core is
 
-- register addresses --
constant mmu_irq_base_c : std_logic_vector(02 downto 0) := "000"; -- r/w: base page for irqs
constant mmu_sys_i_page_c : std_logic_vector(02 downto 0) := "001"; -- r/w: system mode i page
constant mmu_sys_d_page_c : std_logic_vector(02 downto 0) := "010"; -- r/w: system mode d page
constant mmu_usr_i_page_c : std_logic_vector(02 downto 0) := "011"; -- r/w: user mode i page
constant mmu_usr_d_page_c : std_logic_vector(02 downto 0) := "100"; -- r/w: user mode d page
constant mmu_i_page_link_c : std_logic_vector(02 downto 0) := "101"; -- r: linked i page
constant mmu_d_page_link_c : std_logic_vector(02 downto 0) := "110"; -- r: linked d page
constant mmu_sys_info_c : std_logic_vector(02 downto 0) := "111"; -- r: system info
constant mmu_irq_base_c : std_ulogic_vector(02 downto 0) := "000"; -- r/w: base page for irqs
constant mmu_sys_i_page_c : std_ulogic_vector(02 downto 0) := "001"; -- r/w: system mode i page
constant mmu_sys_d_page_c : std_ulogic_vector(02 downto 0) := "010"; -- r/w: system mode d page
constant mmu_usr_i_page_c : std_ulogic_vector(02 downto 0) := "011"; -- r/w: user mode i page
constant mmu_usr_d_page_c : std_ulogic_vector(02 downto 0) := "100"; -- r/w: user mode d page
constant mmu_i_page_link_c : std_ulogic_vector(02 downto 0) := "101"; -- r: linked i page
constant mmu_d_page_link_c : std_ulogic_vector(02 downto 0) := "110"; -- r: linked d page
constant mmu_sys_info_c : std_ulogic_vector(02 downto 0) := "111"; -- r: system info
-- sys info register (uses auto-pointer):
-- 1st read access: clock speed low
-- 2nd read access: clock speed high
 
-- registers --
signal mmu_irq_base : std_logic_vector(15 downto 0);
signal mmu_sys_i_page : std_logic_vector(15 downto 0);
signal mmu_sys_d_page : std_logic_vector(15 downto 0);
signal mmu_usr_i_page : std_logic_vector(15 downto 0);
signal mmu_usr_d_page : std_logic_vector(15 downto 0);
signal mmu_i_page_link : std_logic_vector(15 downto 0);
signal mmu_d_page_link : std_logic_vector(15 downto 0);
signal mmu_irq_base : std_ulogic_vector(15 downto 0);
signal mmu_sys_i_page : std_ulogic_vector(15 downto 0);
signal mmu_sys_d_page : std_ulogic_vector(15 downto 0);
signal mmu_usr_i_page : std_ulogic_vector(15 downto 0);
signal mmu_usr_d_page : std_ulogic_vector(15 downto 0);
signal mmu_i_page_link : std_ulogic_vector(15 downto 0);
signal mmu_d_page_link : std_ulogic_vector(15 downto 0);
 
-- buffers / local signals --
signal i_sys_tmp, i_usr_tmp : std_logic_vector(15 downto 0);
signal d_sys_tmp, d_usr_tmp : std_logic_vector(15 downto 0);
signal mode_buf : std_logic_vector(01 downto 0);
signal sys_info : std_logic_vector(15 downto 0);
signal sys_info_adr : std_logic_vector(01 downto 0);
signal i_sys_tmp, i_usr_tmp : std_ulogic_vector(15 downto 0);
signal d_sys_tmp, d_usr_tmp : std_ulogic_vector(15 downto 0);
signal mode_buf : std_ulogic_vector(01 downto 0);
signal sys_info : std_ulogic_vector(15 downto 0);
signal sys_info_adr : std_ulogic_vector(01 downto 0);
 
begin
 
133,8 → 133,8
when mmu_sys_d_page_c => mmu_sys_d_page <= dat_i; -- system data page
when mmu_usr_i_page_c => mmu_usr_i_page <= dat_i; -- user instruction page
when mmu_usr_d_page_c => mmu_usr_d_page <= dat_i; -- user data page
-- when mmu_i_page_link_c => mmu_i_page_link <= dat_i; -- instruction page link
-- when mmu_d_page_link_c => mmu_d_page_link <= dat_i; -- data page link
-- when mmu_i_page_link_c => mmu_i_page_link <= dat_i; -- instruction page link
-- when mmu_d_page_link_c => mmu_d_page_link <= dat_i; -- data page link
when others => null; -- do nothing
end case;
end if;
147,7 → 147,6
mem_dp_adr_o <= d_usr_tmp when (sys_mode_i = user_mode_c) else d_sys_tmp;
 
 
 
-- MMU Read Access -------------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
r_acc: process(adr_i, mmu_irq_base, mmu_sys_i_page, mmu_sys_d_page, mmu_usr_i_page,
167,7 → 166,6
end process r_acc;
 
 
 
-- System Info Output Control --------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
sys_info_ctrl: process(clk_i)
176,7 → 174,7
if (rst_i = '1') then
sys_info_adr <= (others => '0');
elsif (r_en_i = '1') and (ice_i = '1') and (adr_i = mmu_sys_info_c) then
sys_info_adr <= std_logic_vector(unsigned(sys_info_adr) + 1);
sys_info_adr <= std_ulogic_vector(unsigned(sys_info_adr) + 1);
end if;
end if;
end process sys_info_ctrl;
/rtl/COM_1_CORE.vhd
24,33 → 24,33
-- ## Host Interface ##
-- ###############################################################################################
 
clk_i : in std_logic; -- global clock line
rst_i : in std_logic; -- global reset line, sync, high-active
ice_i : in std_logic; -- interface clock enable, high-active
w_en_i : in std_logic; -- write enable
r_en_i : in std_logic; -- read enable
cmd_exe_i : in std_logic; -- execute command
adr_i : in std_logic_vector(02 downto 0); -- access address/command
dat_i : in std_logic_vector(15 downto 0); -- write data
dat_o : out std_logic_vector(15 downto 0); -- read data
irq_o : out std_logic; -- interrupt request
clk_i : in std_ulogic; -- global clock line
rst_i : in std_ulogic; -- global reset line, sync, high-active
ice_i : in std_ulogic; -- interface clock enable, high-active
w_en_i : in std_ulogic; -- write enable
r_en_i : in std_ulogic; -- read enable
cmd_exe_i : in std_ulogic; -- execute command
adr_i : in std_ulogic_vector(02 downto 0); -- access address/command
dat_i : in std_ulogic_vector(15 downto 0); -- write data
dat_o : out std_ulogic_vector(15 downto 0); -- read data
irq_o : out std_ulogic; -- interrupt request
 
-- ###############################################################################################
-- ## Wishbone Bus ##
-- ###############################################################################################
 
wb_clk_o : out std_logic; -- bus clock
wb_rst_o : out std_logic; -- bus reset, sync, high active
wb_adr_o : out std_logic_vector(31 downto 0); -- address
wb_sel_o : out std_logic_vector(01 downto 0); -- byte select
wb_data_o : out std_logic_vector(15 downto 0); -- data out
wb_data_i : in std_logic_vector(15 downto 0); -- data in
wb_we_o : out std_logic; -- read/write
wb_cyc_o : out std_logic; -- cycle enable
wb_stb_o : out std_logic; -- strobe
wb_ack_i : in std_logic; -- acknowledge
-- wb_halt_i : in std_logic; -- halt transfer
wb_err_i : in std_logic -- bus error
wb_clk_o : out std_ulogic; -- bus clock
wb_rst_o : out std_ulogic; -- bus reset, sync, high active
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
wb_sel_o : out std_ulogic_vector(01 downto 0); -- byte select
wb_data_o : out std_ulogic_vector(15 downto 0); -- data out
wb_data_i : in std_ulogic_vector(15 downto 0); -- data in
wb_we_o : out std_ulogic; -- read/write
wb_cyc_o : out std_ulogic; -- cycle enable
wb_stb_o : out std_ulogic; -- strobe
wb_ack_i : in std_ulogic; -- acknowledge
-- wb_halt_i : in std_ulogic; -- halt transfer
wb_err_i : in std_ulogic -- bus error
);
end com_1_core;
 
57,66 → 57,66
architecture com_1_core_behav of com_1_core is
 
-- Module Addresses --
constant ctrl_reg_c : std_logic_vector(02 downto 0) := "000"; -- R/W: control register (see below)
constant base_adr_l_reg_c : std_logic_vector(02 downto 0) := "001"; -- R/W: base address low
constant base_adr_h_reg_c : std_logic_vector(02 downto 0) := "010"; -- R/W: base address high
constant adr_offset_c : std_logic_vector(02 downto 0) := "011"; -- R/W: address offset (2's comp)
constant rtx_fifo_c : std_logic_vector(02 downto 0) := "100"; -- R/W: Read/write FIFO
constant timeout_val_c : std_logic_vector(02 downto 0) := "101"; -- R/W: Bus timeout cycles
constant ctrl_reg_c : std_ulogic_vector(02 downto 0) := "000"; -- R/W: control register (see below)
constant base_adr_l_reg_c : std_ulogic_vector(02 downto 0) := "001"; -- R/W: base address low
constant base_adr_h_reg_c : std_ulogic_vector(02 downto 0) := "010"; -- R/W: base address high
constant adr_offset_c : std_ulogic_vector(02 downto 0) := "011"; -- R/W: address offset (2's comp)
constant rtx_fifo_c : std_ulogic_vector(02 downto 0) := "100"; -- R/W: Read/write FIFO
constant timeout_val_c : std_ulogic_vector(02 downto 0) := "101"; -- R/W: Bus timeout cycles
 
-- Module Operations --
constant cmd_init_rtrans_c : std_logic_vector(02 downto 0) := "000"; -- start READ transfer
constant cmd_init_wtrans_c : std_logic_vector(02 downto 0) := "001"; -- start WRITE transfer
constant cmd_init_rtrans_c : std_ulogic_vector(02 downto 0) := "000"; -- start READ transfer
constant cmd_init_wtrans_c : std_ulogic_vector(02 downto 0) := "001"; -- start WRITE transfer
 
-- CTRL Register Bits --
constant done_irq_c : natural := 0; -- R: Transfer done (interrupt) flag
constant bus_err_irq_c : natural := 1; -- R: Wishbone bus error (interrupt) flag
constant timeout_irq_c : natural := 2; -- R: Wishbone bus timeout (interrupt) flag
constant done_irq_en_c : natural := 3; -- R/W: Allow IRQ for <transfer done>
constant bus_err_en_irq_c : natural := 4; -- R/W: Allow IRQ for <bus error>
constant timeout_en_irq_c : natural := 5; -- R/W: Allow IRQ for <bus timeout>
constant busy_flag_c : natural := 6; -- R: Transfer in progress (busy)
constant dir_flag_c : natural := 7; -- R: Direction of last transfer (1: write, 0: read)
constant burst_size_lsb_c : natural := 8; -- R/W: Burst size LSB
constant burst_size_msb_c : natural := 15; -- R/W: Burst size MSB
constant done_irq_c : natural := 0; -- R: Transfer done (interrupt) flag
constant bus_err_irq_c : natural := 1; -- R: Wishbone bus error (interrupt) flag
constant timeout_irq_c : natural := 2; -- R: Wishbone bus timeout (interrupt) flag
constant done_irq_en_c : natural := 3; -- R/W: Allow IRQ for <transfer done>
constant bus_err_en_irq_c : natural := 4; -- R/W: Allow IRQ for <bus error>
constant timeout_en_irq_c : natural := 5; -- R/W: Allow IRQ for <bus timeout>
constant busy_flag_c : natural := 6; -- R: Transfer in progress (busy)
constant dir_flag_c : natural := 7; -- R: Direction of last transfer (1: write, 0: read)
constant burst_size_lsb_c : natural := 8; -- R/W: Burst size LSB
constant burst_size_msb_c : natural := 15; -- R/W: Burst size MSB
 
-- Config Regs --
signal base_adr : std_logic_vector(31 downto 0); -- base address
signal adr_offset : std_logic_vector(15 downto 0); -- address offset (2's comp)
signal timeout_val : std_logic_vector(15 downto 0); -- timeout in cycles
signal base_adr : std_ulogic_vector(31 downto 0); -- base address
signal adr_offset : std_ulogic_vector(15 downto 0); -- address offset (2's comp)
signal timeout_val : std_ulogic_vector(15 downto 0); -- timeout in cycles
 
-- arbiter --
signal arb_busy : std_logic; -- arbiter busy flag
signal dir_ctrl : std_logic; -- direction of current/last transfer (0:read, 1:write)
signal burst_size : std_logic_vector(log2(wb_fifo_size_c)-1 downto 0);
signal ack_cnt : std_logic_vector(log2(wb_fifo_size_c)-1 downto 0);
signal wb_adr_offset : std_logic_vector(31 downto 0);
signal timeout_cnt : std_logic_vector(15 downto 0);
signal arb_busy : std_ulogic; -- arbiter busy flag
signal dir_ctrl : std_ulogic; -- direction of current/last transfer (0:read, 1:write)
signal burst_size : std_ulogic_vector(log2(wb_fifo_size_c)-1 downto 0);
signal ack_cnt : std_ulogic_vector(log2(wb_fifo_size_c)-1 downto 0);
signal wb_adr_offset : std_ulogic_vector(31 downto 0);
signal timeout_cnt : std_ulogic_vector(15 downto 0);
 
-- irq system --
signal bus_err_irq_en : std_logic;
signal trans_done_irq_en : std_logic;
signal timeout_irq_en : std_logic;
signal bus_err_irq : std_logic;
signal trans_done_irq : std_logic;
signal timeout_irq : std_logic;
signal bus_err_irq_en : std_ulogic;
signal trans_done_irq_en : std_ulogic;
signal timeout_irq_en : std_ulogic;
signal bus_err_irq : std_ulogic;
signal trans_done_irq : std_ulogic;
signal timeout_irq : std_ulogic;
 
-- rtx fifo --
type rtx_fifo_t is array (0 to wb_fifo_size_c-1) of std_logic_vector(15 downto 0);
signal tx_fifo, rx_fifo : rtx_fifo_t := (others => (others => '0'));
signal rx_fifo_r_pnt : std_logic_vector(log2(wb_fifo_size_c)-1 downto 0);
signal rx_fifo_w_pnt : std_logic_vector(log2(wb_fifo_size_c)-1 downto 0);
signal tx_fifo_r_pnt : std_logic_vector(log2(wb_fifo_size_c)-1 downto 0);
signal tx_fifo_w_pnt : std_logic_vector(log2(wb_fifo_size_c)-1 downto 0);
type rtx_fifo_t is array (0 to wb_fifo_size_c-1) of std_ulogic_vector(15 downto 0);
signal tx_fifo, rx_fifo : rtx_fifo_t := (others => (others => '0'));
signal rx_fifo_r_pnt : std_ulogic_vector(log2(wb_fifo_size_c)-1 downto 0);
signal rx_fifo_w_pnt : std_ulogic_vector(log2(wb_fifo_size_c)-1 downto 0);
signal tx_fifo_r_pnt : std_ulogic_vector(log2(wb_fifo_size_c)-1 downto 0);
signal tx_fifo_w_pnt : std_ulogic_vector(log2(wb_fifo_size_c)-1 downto 0);
 
-- wb sync --
signal wb_data_i_ff : std_logic_vector(15 downto 0); -- data in buffer
signal wb_ack_ff : std_logic; -- acknowledge buffer
signal wb_err_ff : std_logic; -- bus error
signal wb_adr : std_logic_vector(31 downto 0);
signal wb_adr_buf : std_logic_vector(31 downto 0);
signal wb_stb_buf : std_logic;
signal wb_cyc_buf : std_logic;
signal wb_data_i_ff : std_ulogic_vector(15 downto 0); -- data in buffer
signal wb_ack_ff : std_ulogic; -- acknowledge buffer
signal wb_err_ff : std_ulogic; -- bus error
signal wb_adr : std_ulogic_vector(31 downto 0);
signal wb_adr_buf : std_ulogic_vector(31 downto 0);
signal wb_stb_buf : std_ulogic;
signal wb_cyc_buf : std_ulogic;
 
begin
 
153,7 → 153,6
end process w_acc;
 
 
 
-- Read Access -----------------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
r_acc: process(adr_i, base_adr, adr_offset, arb_busy, dir_ctrl, burst_size, bus_err_irq_en,
182,7 → 181,6
end process r_acc;
 
 
 
-- Host FIFO Access ------------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
fifo_acc: process(clk_i)
196,7 → 194,7
if ((w_en_i and (arb_busy nand dir_ctrl)) = '1') then -- valid write to tx fifo?
tx_fifo(to_integer(unsigned(tx_fifo_w_pnt))) <= dat_i;
if (tx_fifo_w_pnt /= burst_size) then
tx_fifo_w_pnt <= std_logic_vector(unsigned(tx_fifo_w_pnt) + 1); -- inc tx fifo write pointer
tx_fifo_w_pnt <= std_ulogic_vector(unsigned(tx_fifo_w_pnt) + 1); -- inc tx fifo write pointer
else
tx_fifo_w_pnt <= (others => '0');
end if;
203,7 → 201,7
end if;
if ((r_en_i and (arb_busy nand (not dir_ctrl))) = '1') then -- valid read from rx fifo?
if (rx_fifo_r_pnt /= burst_size) then
rx_fifo_r_pnt <= std_logic_vector(unsigned(rx_fifo_r_pnt) + 1); -- inc rx fifo read pointer
rx_fifo_r_pnt <= std_ulogic_vector(unsigned(rx_fifo_r_pnt) + 1); -- inc rx fifo read pointer
else
rx_fifo_r_pnt <= (others => '0');
end if;
214,7 → 212,6
end process fifo_acc;
 
 
 
-- Address Offset --------------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
adr_offset_comp: process(adr_offset)
226,7 → 223,6
end process adr_offset_comp;
 
 
 
-- Interrupt Output ------------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
irq_o <= (bus_err_irq and bus_err_irq_en) or
234,7 → 230,6
(timeout_irq and timeout_irq_en); -- use edge trigger!
 
 
 
-- Bus Synchronizer ------------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
bus_sync: process(clk_i)
259,7 → 254,6
wb_rst_o <= rst_i;
 
 
 
-- Bus Arbiter ------------------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
bus_arbiter: process(clk_i)
332,16 → 326,16
wb_adr <= wb_adr_buf;
wb_stb_o <= wb_stb_buf;
wb_cyc_o <= wb_cyc_buf;
timeout_cnt <= std_logic_vector(unsigned(timeout_cnt) + 1);
timeout_cnt <= std_ulogic_vector(unsigned(timeout_cnt) + 1);
 
-- read transfer ------------------------
if (dir_ctrl = '0') then
if (wb_ack_ff = '1') then
rx_fifo(to_integer(unsigned(rx_fifo_w_pnt))) <= wb_data_i_ff;
rx_fifo_w_pnt <= std_logic_vector(unsigned(rx_fifo_w_pnt) + 1); -- inc rx fifo write pointer
rx_fifo_w_pnt <= std_ulogic_vector(unsigned(rx_fifo_w_pnt) + 1); -- inc rx fifo write pointer
end if;
if (rx_fifo_w_pnt /= burst_size) then -- all transfered?
wb_adr_buf <= std_logic_vector(unsigned(wb_adr_buf) + unsigned(wb_adr_offset)); -- adr
wb_adr_buf <= std_ulogic_vector(unsigned(wb_adr_buf) + unsigned(wb_adr_offset)); -- adr
wb_stb_buf <= '1';
else
wb_stb_buf <= '0';
351,8 → 345,8
else
wb_data_o <= tx_fifo(to_integer(unsigned(tx_fifo_r_pnt)));
if (tx_fifo_r_pnt /= burst_size) then -- all transfered?
tx_fifo_r_pnt <= std_logic_vector(unsigned(tx_fifo_r_pnt) + 1); -- inc tx fifo read pointer
wb_adr_buf <= std_logic_vector(unsigned(wb_adr_buf) + unsigned(wb_adr_offset)); -- adr
tx_fifo_r_pnt <= std_ulogic_vector(unsigned(tx_fifo_r_pnt) + 1); -- inc tx fifo read pointer
wb_adr_buf <= std_ulogic_vector(unsigned(wb_adr_buf) + unsigned(wb_adr_offset)); -- adr
wb_stb_buf <= '1';
else
wb_stb_buf <= '0';
367,7 → 361,7
arb_busy <= '0'; -- done
trans_done_irq <= '1';
else
ack_cnt <= std_logic_vector(unsigned(ack_cnt) + 1);
ack_cnt <= std_ulogic_vector(unsigned(ack_cnt) + 1);
wb_cyc_buf <= '1';
end if;
end if;
/rtl/SYSTEM_CP.vhd
20,7 → 20,7
-- ## Module Configuration ##
-- ###############################################################################################
generic (
clock_speed_g : std_logic_vector(31 downto 0) := x"00000000" -- clock speed in Hz
clock_speed_g : std_ulogic_vector(31 downto 0) := x"00000000" -- clock speed in Hz
);
port (
-- ###############################################################################################
27,31 → 27,31
-- ## Global Control ##
-- ###############################################################################################
 
CLK_I : IN STD_LOGIC; -- GLOBAL CLOCK LINE
RST_I : IN STD_LOGIC; -- GLOBAL RESET LINE, SYNC, HIGH-ACTIVE
ICE_I : IN STD_LOGIC; -- INTERFACE CLOCK ENABLE, HIGH-ACTIVE
clk_i : in std_ulogic; -- global clock line
rst_i : in std_ulogic; -- global reset line, sync, high-active
ice_i : in std_ulogic; -- interface clock enable, high-active
 
-- ###############################################################################################
-- ## Processor Interface ##
-- ###############################################################################################
 
cp_en_i : in std_logic; -- access coprocessor
cp_op_i : in std_logic; -- data transfer/processing
cp_rw_i : in std_logic; -- read/write access
cp_cmd_i : in std_logic_vector(cp_cmd_width_c-1 downto 0); -- register addresses / cmd
cp_dat_i : in std_logic_vector(data_width_c-1 downto 0); -- write data
cp_dat_o : out std_logic_vector(data_width_c-1 downto 0); -- read data
cp_irq_o : out std_logic; -- unit interrupt request
cp_en_i : in std_ulogic; -- access coprocessor
cp_op_i : in std_ulogic; -- data transfer/processing
cp_rw_i : in std_ulogic; -- read/write access
cp_cmd_i : in std_ulogic_vector(cp_cmd_width_c-1 downto 0); -- register addresses / cmd
cp_dat_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write data
cp_dat_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data
cp_irq_o : out std_ulogic; -- unit interrupt request
 
sys_mode_i : in std_logic; -- current operating mode
int_exe_i : in std_logic; -- interrupt beeing executed
sys_mode_i : in std_ulogic; -- current operating mode
int_exe_i : in std_ulogic; -- interrupt beeing executed
 
-- ###############################################################################################
-- ## Memory Interface ##
-- ###############################################################################################
 
mem_ip_adr_o : out std_logic_vector(15 downto 0); -- instruction page
mem_dp_adr_o : out std_logic_vector(15 downto 0); -- data page
mem_ip_adr_o : out std_ulogic_vector(15 downto 0); -- instruction page
mem_dp_adr_o : out std_ulogic_vector(15 downto 0); -- data page
 
-- ###############################################################################################
-- ## Peripheral Communication Interface ##
58,41 → 58,41
-- ###############################################################################################
 
-- uart --
uart_rxd_i : in std_logic; -- receiver input
uart_txd_o : out std_logic; -- uart transmitter output
uart_rxd_i : in std_ulogic; -- receiver input
uart_txd_o : out std_ulogic; -- uart transmitter output
 
-- spi --
spi_mosi_o : out std_logic_vector(07 downto 0); -- serial data out
spi_miso_i : in std_logic_vector(07 downto 0); -- serial data in
spi_sck_o : out std_logic_vector(07 downto 0); -- serial clock out
spi_cs_o : out std_logic_vector(07 downto 0); -- chip select (low active)
spi_mosi_o : out std_ulogic_vector(07 downto 0); -- serial data out
spi_miso_i : in std_ulogic_vector(07 downto 0); -- serial data in
spi_sck_o : out std_ulogic_vector(07 downto 0); -- serial clock out
spi_cs_o : out std_ulogic_vector(07 downto 0); -- chip select (low active)
 
-- parallel io --
pio_out_o : out std_logic_vector(15 downto 0); -- parallel output
pio_in_i : in std_logic_vector(15 downto 0); -- parallel input
pio_out_o : out std_ulogic_vector(15 downto 0); -- parallel output
pio_in_i : in std_ulogic_vector(15 downto 0); -- parallel input
 
-- system io --
sys_out_o : out std_logic_vector(07 downto 0); -- system output
sys_in_i : in std_logic_vector(07 downto 0); -- system input
sys_out_o : out std_ulogic_vector(07 downto 0); -- system output
sys_in_i : in std_ulogic_vector(07 downto 0); -- system input
 
-- irqs --
irq_i : in std_logic; -- IRQ
irq_i : in std_ulogic; -- IRQ
 
-- ###############################################################################################
-- ## Wishbone Bus ##
-- ###############################################################################################
 
wb_clk_o : out std_logic; -- bus clock
wb_rst_o : out std_logic; -- bus reset, sync, high active
wb_adr_o : out std_logic_vector(31 downto 0); -- address
wb_sel_o : out std_logic_vector(01 downto 0); -- byte select
wb_data_o : out std_logic_vector(15 downto 0); -- data out
wb_data_i : in std_logic_vector(15 downto 0); -- data in
wb_we_o : out std_logic; -- read/write
wb_cyc_o : out std_logic; -- cycle enable
wb_stb_o : out std_logic; -- strobe
wb_ack_i : in std_logic; -- acknowledge
wb_err_i : in std_logic -- bus error
wb_clk_o : out std_ulogic; -- bus clock
wb_rst_o : out std_ulogic; -- bus reset, sync, high active
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
wb_sel_o : out std_ulogic_vector(01 downto 0); -- byte select
wb_data_o : out std_ulogic_vector(15 downto 0); -- data out
wb_data_i : in std_ulogic_vector(15 downto 0); -- data in
wb_we_o : out std_ulogic; -- read/write
wb_cyc_o : out std_ulogic; -- cycle enable
wb_stb_o : out std_ulogic; -- strobe
wb_ack_i : in std_ulogic; -- acknowledge
wb_err_i : in std_ulogic -- bus error
);
end system_cp;
 
99,36 → 99,36
architecture system_cp_behav of system_cp is
 
-- module addresses --
constant sys0_module_c : std_logic_vector(1 downto 0) := "00";
constant sys1_module_c : std_logic_vector(1 downto 0) := "01";
constant com0_module_c : std_logic_vector(1 downto 0) := "10";
constant com1_module_c : std_logic_vector(1 downto 0) := "11";
constant sys0_module_c : std_ulogic_vector(1 downto 0) := "00";
constant sys1_module_c : std_ulogic_vector(1 downto 0) := "01";
constant com0_module_c : std_ulogic_vector(1 downto 0) := "10";
constant com1_module_c : std_ulogic_vector(1 downto 0) := "11";
 
-- module interface --
type module_interface_t is record
data_o : std_logic_vector(data_width_c-1 downto 0);
w_en : std_logic;
r_en : std_logic;
cmd_exe : std_logic;
data_o : std_ulogic_vector(data_width_c-1 downto 0);
w_en : std_ulogic;
r_en : std_ulogic;
cmd_exe : std_ulogic;
end record;
 
signal sys_0_module : module_interface_t;
signal sys_1_module : module_interface_t;
signal com_0_module : module_interface_t;
signal com_1_module : module_interface_t;
signal sys_0_module : module_interface_t;
signal sys_1_module : module_interface_t;
signal com_0_module : module_interface_t;
signal com_1_module : module_interface_t;
 
-- raw interrupt signals --
signal int_assign : std_logic_vector(7 downto 0);
signal timer_irq : std_logic;
signal uart_rx_irq : std_logic;
signal uart_tx_irq : std_logic;
signal spi_irq : std_logic;
signal pio_irq : std_logic;
signal wb_core_irq : std_logic;
signal int_assign : std_ulogic_vector(7 downto 0);
signal timer_irq : std_ulogic;
signal uart_rx_irq : std_ulogic;
signal uart_tx_irq : std_ulogic;
signal spi_irq : std_ulogic;
signal pio_irq : std_ulogic;
signal wb_core_irq : std_ulogic;
 
-- internals --
signal read_acc : std_logic; -- true read access
signal cmd_exe : std_logic; -- true coprocessor command
signal read_acc : std_ulogic; -- true read access
signal cmd_exe : std_ulogic; -- true coprocessor command
 
begin
 
135,7 → 135,7
-- Write Access Logic ----------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
ctrl_w_acc: process(cp_en_i, cp_rw_i, cp_op_i, cp_cmd_i)
variable valid_acc_v : std_logic;
variable valid_acc_v : std_ulogic;
begin
-- valid write access? --
valid_acc_v := cp_en_i and cp_rw_i and cp_op_i;
155,7 → 155,6
end process ctrl_w_acc;
 
 
 
-- Read Access Logic -----------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
ctrl_r_acc: process(clk_i)
186,8 → 185,8
com_0_module.r_en <= read_acc when (cp_cmd_i(cp_op_b_msb_c-1 downto cp_op_b_lsb_c) = com0_module_c) else '0';
com_1_module.r_en <= read_acc when (cp_cmd_i(cp_op_b_msb_c-1 downto cp_op_b_lsb_c) = com1_module_c) else '0';
 
-- module execute command --
cmd_exe <= cp_en_i and (not cp_op_i); -- true coprocessor command
-- module execute command --
cmd_exe <= cp_en_i and (not cp_op_i); -- true coprocessor command
sys_0_module.cmd_exe <= cmd_exe when (cp_cmd_i(cp_op_b_msb_c-1 downto cp_op_b_lsb_c) = sys0_module_c) else '0';
sys_1_module.cmd_exe <= cmd_exe when (cp_cmd_i(cp_op_b_msb_c-1 downto cp_op_b_lsb_c) = sys1_module_c) else '0';
com_0_module.cmd_exe <= cmd_exe when (cp_cmd_i(cp_op_b_msb_c-1 downto cp_op_b_lsb_c) = com0_module_c) else '0';
194,7 → 193,6
com_1_module.cmd_exe <= cmd_exe when (cp_cmd_i(cp_op_b_msb_c-1 downto cp_op_b_lsb_c) = com1_module_c) else '0';
 
 
 
-- System Controller 0 ---------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
system_ctrl_0: sys_0_core
226,7 → 224,6
int_assign(7) <= irq_i; -- 'external' irq
 
 
 
-- System Controller 1 ---------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
system_ctrl_1: sys_1_core
254,7 → 251,6
);
 
 
 
-- Communication Controller 0 --------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
communication_ctrl_0: com_0_core
289,7 → 285,6
);
 
 
 
-- Communication Controller 1 --------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
communication_ctrl_1: com_1_core
/rtl/WB_UNIT.vhd
21,30 → 21,30
-- ## Global Control ##
-- ###############################################################################################
 
CLK_I : IN STD_LOGIC; -- GLOBAL CLOCK LINE
CE_I : IN STD_LOGIC; -- CLOCK ENABLE
RST_I : IN STD_LOGIC; -- GLOBAL RESET LINE, SYNC, HIGH-ACTIVE
clk_i : in std_ulogic; -- global clock line
ce_i : in std_ulogic; -- clock enable
rst_i : in std_ulogic; -- global reset line, sync, high-active
 
-- ###############################################################################################
-- ## Function Control ##
-- ###############################################################################################
 
wb_ctrl_bus_i : in std_logic_vector(ctrl_width_c-1 downto 0); -- wb stage control
wb_ctrl_bus_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- wb stage control
 
-- ###############################################################################################
-- ## Data Input ##
-- ###############################################################################################
 
mem_wb_dat_i : in std_logic_vector(data_width_c-1 downto 0); -- memory read data
alu_wb_dat_i : in std_logic_vector(data_width_c-1 downto 0); -- alu read data
mem_adr_fb_i : in std_logic_vector(data_width_c-1 downto 0); -- memory address feedback
mem_wb_dat_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
alu_wb_dat_i : in std_ulogic_vector(data_width_c-1 downto 0); -- alu read data
mem_adr_fb_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory address feedback
 
-- ###############################################################################################
-- ## Data Output ##
-- ###############################################################################################
 
wb_data_o : out std_logic_vector(data_width_c-1 downto 0); -- write back data
wb_fwd_o : out std_logic_vector(fwd_width_c-1 downto 0) -- wb stage forwarding path
wb_data_o : out std_ulogic_vector(data_width_c-1 downto 0); -- write back data
wb_fwd_o : out std_ulogic_vector(fwd_width_c-1 downto 0) -- wb stage forwarding path
);
end wb_unit;
 
51,14 → 51,14
architecture wb_structure of wb_unit is
 
-- pipeline register --
signal alu_ff : std_logic_vector(data_width_c-1 downto 0);
signal alu_ff : std_ulogic_vector(data_width_c-1 downto 0);
 
-- write-back source select --
signal wb_data_int : std_logic_vector(data_width_c-1 downto 0);
signal wb_data_int : std_ulogic_vector(data_width_c-1 downto 0);
 
-- aligned mem data --
signal mem_adr_fb : std_logic_vector(data_width_c-1 downto 0);
signal mem_wb_dat_int : std_logic_vector(data_width_c-1 downto 0);
signal mem_adr_fb : std_ulogic_vector(data_width_c-1 downto 0);
signal mem_wb_dat_int : std_ulogic_vector(data_width_c-1 downto 0);
 
begin
 
78,11 → 78,10
end process pipe_reg;
 
 
 
-- Data Alignment --------------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
dat_align: process(mem_adr_fb, mem_wb_dat_i)
variable dat_end_v : std_logic_vector(data_width_c-1 downto 0);
variable dat_end_v : std_ulogic_vector(data_width_c-1 downto 0);
begin
-- endianness converter --
if (big_endian_c = false) then
104,7 → 103,6
end process dat_align;
 
 
 
-- Module Data Output ----------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
-- route mem data if valid mem-read-access
112,7 → 110,6
wb_data_o <= wb_data_int;
 
 
 
-- Forwarding Path Output ------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
 
127,5 → 124,4
 
 
 
 
end wb_structure;
/rtl/SYS_REG.vhd
24,44 → 24,44
-- ## Global Control ##
-- ###############################################################################################
 
clk_i : in std_logic; -- global clock line
ce_i : in std_logic; -- clock enable
rst_i : in std_logic; -- global reset line, sync, high-active
clk_i : in std_ulogic; -- global clock line
ce_i : in std_ulogic; -- clock enable
rst_i : in std_ulogic; -- global reset line, sync, high-active
 
-- ###############################################################################################
-- ## Function Control ##
-- ###############################################################################################
 
ex_ctrl_bus_i : in std_logic_vector(ctrl_width_c-1 downto 0); -- ex stage control
ma_ctrl_bus_i : in std_logic_vector(ctrl_width_c-1 downto 0); -- ma stage control
ext_int_req0_i : in std_logic; -- external interrupt request 0
ext_int_req1_i : in std_logic; -- external interrupt request 1
ex_ctrl_bus_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- ex stage control
ma_ctrl_bus_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- ma stage control
ext_int_req0_i : in std_ulogic; -- external interrupt request 0
ext_int_req1_i : in std_ulogic; -- external interrupt request 1
 
-- ###############################################################################################
-- ## Data Input ##
-- ###############################################################################################
 
flag_bus_i : in std_logic_vector(flag_bus_width_c-1 downto 0); -- flag input
exc_pos_i : in std_logic; -- exception would be possible
stop_pc : in std_logic; -- freeze pc
pc_data_i : in std_logic_vector(data_width_c-1 downto 0); -- pc write data
msr_data_i : in std_logic_vector(data_width_c-1 downto 0); -- msr write data
flag_bus_i : in std_ulogic_vector(flag_bus_width_c-1 downto 0); -- flag input
exc_pos_i : in std_ulogic; -- exception would be possible
stop_pc : in std_ulogic; -- freeze pc
pc_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- pc write data
msr_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- msr write data
 
-- ###############################################################################################
-- ## Data Output ##
-- ###############################################################################################
 
flag_bus_o : out std_logic_vector(flag_bus_width_c-1 downto 0); -- flag output
valid_branch_o : out std_logic; -- valid branch detected
exc_executed_o : out std_logic; -- executed executed
wake_up_o : out std_logic; -- wake-up signal
rd_msr_o : out std_logic_vector(data_width_c-1 downto 0); -- read data msr
pc_o : out std_logic_vector(data_width_c-1 downto 0); -- pc output
pc_1d_o : out std_logic_vector(data_width_c-1 downto 0); -- pc 1x delayed
cp_ptc_o : out std_logic; -- user coprocessor protection
cond_true_o : out std_logic; -- condition is true
mode_o : out std_logic; -- current operating mode
mode_ff_o : out std_logic -- delayed current mode
flag_bus_o : out std_ulogic_vector(flag_bus_width_c-1 downto 0); -- flag output
valid_branch_o : out std_ulogic; -- valid branch detected
exc_executed_o : out std_ulogic; -- executed executed
wake_up_o : out std_ulogic; -- wake-up signal
rd_msr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data msr
pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- pc output
pc_1d_o : out std_ulogic_vector(data_width_c-1 downto 0); -- pc 1x delayed
cp_ptc_o : out std_ulogic; -- user coprocessor protection
cond_true_o : out std_ulogic; -- condition is true
mode_o : out std_ulogic; -- current operating mode
mode_ff_o : out std_ulogic -- delayed current mode
);
end sys_reg;
 
68,20 → 68,20
architecture sr_structure of sys_reg is
 
-- system register --
signal sys_reg_pc : std_logic_vector(data_width_c-1 downto 0);
signal sys_reg_msr : std_logic_vector(data_width_c-1 downto 0);
signal pc_1d_tmp : std_logic_vector(data_width_c-1 downto 0);
signal sys_reg_pc : std_ulogic_vector(data_width_c-1 downto 0);
signal sys_reg_msr : std_ulogic_vector(data_width_c-1 downto 0);
signal pc_1d_tmp : std_ulogic_vector(data_width_c-1 downto 0);
 
-- branch system --
signal valid_branch : std_logic;
signal valid_branch : std_ulogic;
 
-- interrupt system --
signal int_req : std_logic;
signal int_vector : std_logic_vector(15 downto 0);
signal xint_sync : std_logic_vector(01 downto 0);
signal int_req : std_ulogic;
signal int_vector : std_ulogic_vector(15 downto 0);
signal xint_sync : std_ulogic_vector(01 downto 0);
 
-- mode flag delay buffer --
signal mode_buffer : std_logic_vector(02 downto 0);
signal mode_buffer : std_ulogic_vector(02 downto 0);
 
begin
 
88,7 → 88,7
-- External Interrupt Sychronizer ----------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
xi_synchronizer: process(clk_i)
variable valid_int_req_v : std_logic;
variable valid_int_req_v : std_ulogic;
begin
if rising_edge(clk_i) then
if (rst_i = '1') then
105,8 → 105,8
-- Exception Priority System ---------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
exc_sys: process(ex_ctrl_bus_i, xint_sync, exc_pos_i, sys_reg_msr)
variable xint0_en_v, xint1_en_v : std_logic;
variable xint0_valid_v, xint1_valid_v : std_logic;
variable xint0_en_v, xint1_en_v : std_ulogic;
variable xint0_valid_v, xint1_valid_v : std_ulogic;
begin
-- external interrupt enable --
-- => external_int is possible and int_source is enabled and global_ints are enabled
119,7 → 119,7
wake_up_o <= (xint0_en_v and xint_sync(0)) or (xint1_en_v and xint_sync(1));
 
-- exception priority list and encoding --
if ((xint0_valid_v = '1') and (xint_sync(0) = '1')) then -- external interrupt 0
if ((xint0_valid_v = '1') and (xint_sync(0) = '1')) then -- external interrupt 0
int_req <= '1';
int_vector <= irq0_int_vec_c;
elsif ((xint1_valid_v = '1') and (xint_sync(1) = '1')) then -- external interrupt 1
141,11 → 141,10
exc_executed_o <= int_req;
 
 
 
-- System Register Update ------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
sr_update: process(clk_i, sys_reg_msr, ex_ctrl_bus_i, mode_buffer)
variable m_msr_acc_v : std_logic_vector(2 downto 0);
variable m_msr_acc_v : std_ulogic_vector(2 downto 0);
begin
-- manual msr access mode (from ex stage) --
m_msr_acc_v := mode_buffer(1) & ex_ctrl_bus_i(ctrl_msr_am_1_c downto ctrl_msr_am_0_c);
255,9 → 254,9
-- automatic pc update --------------------------------------------------
elsif (stop_pc = '0') then -- update instruction address
if (word_mode_en_c = false) then -- byte-addressed memory
sys_reg_pc <= std_logic_vector(unsigned(sys_reg_pc) + 2); -- byte increment
sys_reg_pc <= std_ulogic_vector(unsigned(sys_reg_pc) + 2); -- byte increment
else -- word-addressed memory
sys_reg_pc <= std_logic_vector(unsigned(sys_reg_pc) + 1); -- word increment
sys_reg_pc <= std_ulogic_vector(unsigned(sys_reg_pc) + 1); -- word increment
end if;
end if;
 
266,7 → 265,6
end process sr_update;
 
 
 
-- MSR Flag Output -------------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
flag_bus_o(flag_z_c) <= sys_reg_msr(msr_usr_z_flag_c) when (mode_buffer(1) = user_mode_c) else sys_reg_msr(msr_sys_z_flag_c);
280,11 → 278,10
mode_ff_o <= mode_buffer(2); -- delayed current operating mode (for of stage)
 
 
 
-- MSR Data-Read Access --------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
msr_rd_acc: process(ma_ctrl_bus_i, sys_reg_msr, mode_buffer)
variable msr_r_mode_v : std_logic_vector(2 downto 0);
variable msr_r_mode_v : std_ulogic_vector(2 downto 0);
begin
msr_r_mode_v := mode_buffer(0) & ma_ctrl_bus_i(ctrl_msr_am_1_c downto ctrl_msr_am_0_c); -- access from ma stage
rd_msr_o <= (others => '0');
318,7 → 315,6
end process msr_rd_acc;
 
 
 
-- PC, M-Flag and UCP_P-Flag Delay Generator -----------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
delay_gen: process(clk_i)
339,11 → 335,6
end if;
end process delay_gen;
 
-- sys_reg_msr(msr_mode_flag_c) -> m-flag for if stage
-- mode_buffer(2) -> m-flag for of stage
-- mode_buffer(1) -> m-flag for ex stage
-- mode_buffer(0) -> m-flag for ma stage
 
-- pc outputs --
pc_out_driver: process(sys_reg_pc)
begin
353,14 → 344,13
pc_1d_o <= pc_1d_tmp; -- 1x delayed
 
 
 
-- Branch Detector -------------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
branch_detector: process(ex_ctrl_bus_i, sys_reg_msr, int_req, mode_buffer)
variable z_v, c_v, o_v, n_v, t_v : std_logic;
variable valid_v : std_logic;
variable valid_branch_v : std_logic;
variable manual_branch_v : std_logic;
variable z_v, c_v, o_v, n_v, t_v : std_ulogic;
variable valid_v : std_ulogic;
variable valid_branch_v : std_ulogic;
variable manual_branch_v : std_ulogic;
begin
 
-- flag isolation (instruction from ex stage) --
/rtl/ATLAS_CPU.vhd
22,16 → 22,16
-- ## Global Control ##
-- ###############################################################################################
 
clk_i : in std_logic; -- global clock line
rst_i : in std_logic; -- global reset line, sync, high-active
ce_i : in std_logic; -- clock enable, high-active
clk_i : in std_ulogic; -- global clock line
rst_i : in std_ulogic; -- global reset line, sync, high-active
ce_i : in std_ulogic; -- clock enable, high-active
 
-- ###############################################################################################
-- ## Instruction Interface ##
-- ###############################################################################################
 
instr_adr_o : out std_logic_vector(data_width_c-1 downto 0); -- instruction byte adr
instr_dat_i : in std_logic_vector(data_width_c-1 downto 0); -- instruction input
instr_adr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction byte adr
instr_dat_i : in std_ulogic_vector(data_width_c-1 downto 0); -- instruction input
 
-- ###############################################################################################
-- ## Data Interface ##
38,34 → 38,34
-- ###############################################################################################
 
-- memory arbitration --
sys_mode_o : out std_logic; -- current operating mode
sys_int_o : out std_logic; -- interrupt processing
sys_mode_o : out std_ulogic; -- current operating mode
sys_int_o : out std_ulogic; -- interrupt processing
 
-- memory system --
mem_req_o : out std_logic; -- mem access in next cycle
mem_rw_o : out std_logic; -- read write
mem_adr_o : out std_logic_vector(data_width_c-1 downto 0); -- data byte adr
mem_dat_o : out std_logic_vector(data_width_c-1 downto 0); -- write data
mem_dat_i : in std_logic_vector(data_width_c-1 downto 0); -- read data
mem_req_o : out std_ulogic; -- mem access in next cycle
mem_rw_o : out std_ulogic; -- read write
mem_adr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- data byte adr
mem_dat_o : out std_ulogic_vector(data_width_c-1 downto 0); -- write data
mem_dat_i : in std_ulogic_vector(data_width_c-1 downto 0); -- read data
 
-- ###############################################################################################
-- ## Coprocessor Interface ##
-- ###############################################################################################
 
usr_cp_en_o : out std_logic; -- access to cp0
sys_cp_en_o : out std_logic; -- access to cp1
cp_op_o : out std_logic; -- data transfer/processing
cp_rw_o : out std_logic; -- read/write access
cp_cmd_o : out std_logic_vector(cp_cmd_width_c-1 downto 0); -- register addresses / cmd
cp_dat_o : out std_logic_vector(data_width_c-1 downto 0); -- write data
cp_dat_i : in std_logic_vector(data_width_c-1 downto 0); -- read data cp0 or cp1
usr_cp_en_o : out std_ulogic; -- access to cp0
sys_cp_en_o : out std_ulogic; -- access to cp1
cp_op_o : out std_ulogic; -- data transfer/processing
cp_rw_o : out std_ulogic; -- read/write access
cp_cmd_o : out std_ulogic_vector(cp_cmd_width_c-1 downto 0); -- register addresses / cmd
cp_dat_o : out std_ulogic_vector(data_width_c-1 downto 0); -- write data
cp_dat_i : in std_ulogic_vector(data_width_c-1 downto 0); -- read data cp0 or cp1
 
-- ###############################################################################################
-- ## External Interrupt Lines ##
-- ###############################################################################################
 
ext_int_0_i : in std_logic; -- external interrupt request 0
ext_int_1_i : in std_logic -- external interrupt request 1
ext_int_0_i : in std_ulogic; -- external interrupt request 0
ext_int_1_i : in std_ulogic -- external interrupt request 1
);
end atlas_cpu;
 
72,61 → 72,61
architecture atlas_cpu_behav of atlas_cpu is
 
-- global nets --
signal g_clk : std_logic; -- global clock line
signal g_rst : std_logic; -- global reset line
signal g_ce : std_logic; -- global clock enable
signal g_clk : std_ulogic; -- global clock line
signal g_rst : std_ulogic; -- global reset line
signal g_ce : std_ulogic; -- global clock enable
 
-- control lines --
signal of_ctrl : std_logic_vector(ctrl_width_c-1 downto 0);
signal ex_ctrl : std_logic_vector(ctrl_width_c-1 downto 0);
signal ma_ctrl : std_logic_vector(ctrl_width_c-1 downto 0);
signal wb_ctrl : std_logic_vector(ctrl_width_c-1 downto 0);
signal of_ctrl : std_ulogic_vector(ctrl_width_c-1 downto 0);
signal ex_ctrl : std_ulogic_vector(ctrl_width_c-1 downto 0);
signal ma_ctrl : std_ulogic_vector(ctrl_width_c-1 downto 0);
signal wb_ctrl : std_ulogic_vector(ctrl_width_c-1 downto 0);
 
-- forwarding paths --
signal ma_fwd : std_logic_vector(fwd_width_c-1 downto 0);
signal wb_fwd : std_logic_vector(fwd_width_c-1 downto 0);
signal ma_fwd : std_ulogic_vector(fwd_width_c-1 downto 0);
signal wb_fwd : std_ulogic_vector(fwd_width_c-1 downto 0);
 
-- data lines --
signal wb_data : std_logic_vector(data_width_c-1 downto 0); -- write back data
signal op_a_data : std_logic_vector(data_width_c-1 downto 0); -- operand a data
signal op_b_data : std_logic_vector(data_width_c-1 downto 0); -- operand b data
signal op_c_data : std_logic_vector(data_width_c-1 downto 0); -- operand c data
signal bp_a_data : std_logic_vector(data_width_c-1 downto 0); -- operand a bypass
signal bp_c_data : std_logic_vector(data_width_c-1 downto 0); -- operand c bypass
signal alu_res : std_logic_vector(data_width_c-1 downto 0); -- alu result
signal mul_res : std_logic_vector(2*data_width_c-1 downto 0); -- mul result
signal immediate : std_logic_vector(data_width_c-1 downto 0); -- immediate value
signal t_flag : std_logic; -- transfer flag
signal ma_data : std_logic_vector(data_width_c-1 downto 0); -- ma stage result
signal mem_adr_fb : std_logic_vector(data_width_c-1 downto 0); -- mem adr feedback
signal wb_data : std_ulogic_vector(data_width_c-1 downto 0); -- write back data
signal op_a_data : std_ulogic_vector(data_width_c-1 downto 0); -- operand a data
signal op_b_data : std_ulogic_vector(data_width_c-1 downto 0); -- operand b data
signal op_c_data : std_ulogic_vector(data_width_c-1 downto 0); -- operand c data
signal bp_a_data : std_ulogic_vector(data_width_c-1 downto 0); -- operand a bypass
signal bp_c_data : std_ulogic_vector(data_width_c-1 downto 0); -- operand c bypass
signal alu_res : std_ulogic_vector(data_width_c-1 downto 0); -- alu result
signal mul_res : std_ulogic_vector(2*data_width_c-1 downto 0); -- mul result
signal immediate : std_ulogic_vector(data_width_c-1 downto 0); -- immediate value
signal t_flag : std_ulogic; -- transfer flag
signal ma_data : std_ulogic_vector(data_width_c-1 downto 0); -- ma stage result
signal mem_adr_fb : std_ulogic_vector(data_width_c-1 downto 0); -- mem adr feedback
 
-- program counter --
signal pc_1d : std_logic_vector(data_width_c-1 downto 0); -- 1x delayed pc
signal stop_pc : std_logic; -- freeze pc
signal pc_1d : std_ulogic_vector(data_width_c-1 downto 0); -- 1x delayed pc
signal stop_pc : std_ulogic; -- freeze pc
 
-- flag stuff --
signal alu_flag_i : std_logic_vector(flag_bus_width_c-1 downto 0); -- alu flag input
signal alu_flag_o : std_logic_vector(flag_bus_width_c-1 downto 0); -- alu flag output
signal msr_w_data : std_logic_vector(data_width_c-1 downto 0); -- msr write data
signal msr_r_data : std_logic_vector(data_width_c-1 downto 0); -- msr read data
signal alu_flag_i : std_ulogic_vector(flag_bus_width_c-1 downto 0); -- alu flag input
signal alu_flag_o : std_ulogic_vector(flag_bus_width_c-1 downto 0); -- alu flag output
signal msr_w_data : std_ulogic_vector(data_width_c-1 downto 0); -- msr write data
signal msr_r_data : std_ulogic_vector(data_width_c-1 downto 0); -- msr read data
 
-- control signals --
signal valid_branch : std_logic; -- taken branch
signal exc_pos : std_logic; -- exception would be possible
signal exc_taken : std_logic; -- async interrupt taken
signal wake_up_call : std_logic; -- wake up from sleep
signal mode : std_logic; -- current operating mode
signal mode_ff : std_logic; -- delayed current operating mode
signal cond_true : std_logic; -- condition is true
signal valid_branch : std_ulogic; -- taken branch
signal exc_pos : std_ulogic; -- exception would be possible
signal exc_taken : std_ulogic; -- async interrupt taken
signal wake_up_call : std_ulogic; -- wake up from sleep
signal mode : std_ulogic; -- current operating mode
signal mode_ff : std_ulogic; -- delayed current operating mode
signal cond_true : std_ulogic; -- condition is true
 
-- opcode decoder --
signal op_ctrl : std_logic_vector(ctrl_width_c-1 downto 0); -- decoder contorl output
signal multi_cyc : std_logic; -- multi-cycle indicator
signal multi_cyc_req : std_logic; -- multi-cycle reqest
signal instr_reg : std_logic_vector(data_width_c-1 downto 0); -- instruction register
signal op_ctrl : std_ulogic_vector(ctrl_width_c-1 downto 0); -- decoder contorl output
signal multi_cyc : std_ulogic; -- multi-cycle indicator
signal multi_cyc_req : std_ulogic; -- multi-cycle reqest
signal instr_reg : std_ulogic_vector(data_width_c-1 downto 0); -- instruction register
 
-- coprocessor --
signal cp_ptc : std_logic; -- user coprocessor protection
signal cp_ptc : std_ulogic; -- user coprocessor protection
 
begin
 
137,95 → 137,92
g_rst <= rst_i;
 
 
 
-- Opcode Decoder --------------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
opcode_decoder: op_dec
port map (
-- decoder interface input --
instr_i => instr_reg, -- instruction input
instr_adr_i => pc_1d, -- corresponding address
t_flag_i => t_flag, -- t-flag input
m_flag_i => mode_ff, -- mode flag input
multi_cyc_i => multi_cyc, -- multi-cycle indicator
cp_ptc_i => cp_ptc, -- coprocessor protection
port map (
-- decoder interface input --
instr_i => instr_reg, -- instruction input
instr_adr_i => pc_1d, -- corresponding address
t_flag_i => t_flag, -- t-flag input
m_flag_i => mode_ff, -- mode flag input
multi_cyc_i => multi_cyc, -- multi-cycle indicator
cp_ptc_i => cp_ptc, -- coprocessor protection
 
-- decoder interface output --
multi_cyc_req_o => multi_cyc_req, -- multi-cycle reqest
ctrl_o => op_ctrl, -- decoder ctrl lines
imm_o => immediate -- immediate
);
-- decoder interface output --
multi_cyc_req_o => multi_cyc_req, -- multi-cycle reqest
ctrl_o => op_ctrl, -- decoder ctrl lines
imm_o => immediate -- immediate
);
 
 
 
-- Control System --------------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
control_spine: ctrl
port map (
-- global control --
clk_i => g_clk, -- global clock line
ce_i => g_ce, -- clock enable
rst_i => g_rst, -- global reset line, sync, high-active
port map (
-- global control --
clk_i => g_clk, -- global clock line
ce_i => g_ce, -- clock enable
rst_i => g_rst, -- global reset line, sync, high-active
 
-- decoder interface --
op_dec_ctrl_i => op_ctrl, -- decoder ctrl lines
multi_cyc_o => multi_cyc, -- multi-cycle indicator
multi_cyc_req_i => multi_cyc_req, -- multi-cycle request
instr_i => instr_dat_i, -- instruction input
instr_reg_o => instr_reg, -- instruction register
-- decoder interface --
op_dec_ctrl_i => op_ctrl, -- decoder ctrl lines
multi_cyc_o => multi_cyc, -- multi-cycle indicator
multi_cyc_req_i => multi_cyc_req, -- multi-cycle request
instr_i => instr_dat_i, -- instruction input
instr_reg_o => instr_reg, -- instruction register
 
-- control lines --
of_ctrl_bus_o => of_ctrl, -- of stage control
ex_ctrl_bus_o => ex_ctrl, -- ex stage control
ma_ctrl_bus_o => ma_ctrl, -- ma stage control
wb_ctrl_bus_o => wb_ctrl, -- wb stage control
-- control lines --
of_ctrl_bus_o => of_ctrl, -- of stage control
ex_ctrl_bus_o => ex_ctrl, -- ex stage control
ma_ctrl_bus_o => ma_ctrl, -- ma stage control
wb_ctrl_bus_o => wb_ctrl, -- wb stage control
 
-- function control --
cond_true_i => cond_true, -- condition is true
valid_branch_i => valid_branch, -- valid branch detected
exc_taken_i => exc_taken, -- excation execute
wake_up_i => wake_up_call, -- wake up from sleep
exc_pos_o => exc_pos, -- exception would be possible
stop_pc_o => stop_pc -- freeze program counter
);
-- function control --
cond_true_i => cond_true, -- condition is true
valid_branch_i => valid_branch, -- valid branch detected
exc_taken_i => exc_taken, -- excation execute
wake_up_i => wake_up_call, -- wake up from sleep
exc_pos_o => exc_pos, -- exception would be possible
stop_pc_o => stop_pc -- freeze program counter
);
 
 
 
-- Machine Status System -------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
system_reg: sys_reg
port map (
-- global control --
clk_i => g_clk, -- global clock line
ce_i => g_ce, -- clock enable
rst_i => g_rst, -- global reset line, asyc
port map (
-- global control --
clk_i => g_clk, -- global clock line
ce_i => g_ce, -- clock enable
rst_i => g_rst, -- global reset line, asyc
 
-- function control --
ex_ctrl_bus_i => ex_ctrl, -- ex stage control
ma_ctrl_bus_i => ma_ctrl, -- ma stage control
ext_int_req0_i => ext_int_0_i, -- external interrupt request 0
ext_int_req1_i => ext_int_1_i, -- external interrupt request 1
-- function control --
ex_ctrl_bus_i => ex_ctrl, -- ex stage control
ma_ctrl_bus_i => ma_ctrl, -- ma stage control
ext_int_req0_i => ext_int_0_i, -- external interrupt request 0
ext_int_req1_i => ext_int_1_i, -- external interrupt request 1
 
-- data input --
flag_bus_i => alu_flag_o, -- flag input
exc_pos_i => exc_pos, -- exception would be possible
stop_pc => stop_pc, -- freeze pc
pc_data_i => alu_res, -- pc write data
msr_data_i => msr_w_data, -- msr write data
-- data input --
flag_bus_i => alu_flag_o, -- flag input
exc_pos_i => exc_pos, -- exception would be possible
stop_pc => stop_pc, -- freeze pc
pc_data_i => alu_res, -- pc write data
msr_data_i => msr_w_data, -- msr write data
 
-- data output --
flag_bus_o => alu_flag_i, -- flag output
valid_branch_o => valid_branch, -- valid branch detected
exc_executed_o => exc_taken, -- executed exception
wake_up_o => wake_up_call, -- wake-up signal
rd_msr_o => msr_r_data, -- read data msr
pc_o => instr_adr_o, -- pc output
pc_1d_o => pc_1d, -- pc 1x delayed
cp_ptc_o => cp_ptc, -- coprocessor protection
cond_true_o => cond_true, -- condition is true
mode_o => mode, -- current mode
mode_ff_o => mode_ff -- delayed current mode
);
-- data output --
flag_bus_o => alu_flag_i, -- flag output
valid_branch_o => valid_branch, -- valid branch detected
exc_executed_o => exc_taken, -- executed exception
wake_up_o => wake_up_call, -- wake-up signal
rd_msr_o => msr_r_data, -- read data msr
pc_o => instr_adr_o, -- pc output
pc_1d_o => pc_1d, -- pc 1x delayed
cp_ptc_o => cp_ptc, -- coprocessor protection
cond_true_o => cond_true, -- condition is true
mode_o => mode, -- current mode
mode_ff_o => mode_ff -- delayed current mode
);
 
-- control lines --
sys_mode_o <= mode; -- current operating mode
232,134 → 229,130
sys_int_o <= exc_taken; -- exception taken
 
 
 
-- OF Stage --------------------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
operand_fetch: reg_file
port map (
-- global control --
clk_i => g_clk, -- global clock line
ce_i => g_ce, -- clock enable
rst_i => g_rst, -- global reset line, sync, high-active
port map (
-- global control --
clk_i => g_clk, -- global clock line
ce_i => g_ce, -- clock enable
rst_i => g_rst, -- global reset line, sync, high-active
-- function control --
wb_ctrl_bus_i => wb_ctrl, -- wb stage control
of_ctrl_bus_i => of_ctrl, -- of stage control
-- data input --
wb_data_i => wb_data, -- write back data
immediate_i => immediate, -- immediates
pc_1d_i => pc_1d, -- pc 1x delayed
wb_fwd_i => wb_fwd, -- wb stage forwarding path
-- data output --
op_a_data_o => op_a_data, -- operand a output
op_b_data_o => op_b_data, -- operand b output
op_c_data_o => op_c_data -- operand c output
);
 
-- function control --
wb_ctrl_bus_i => wb_ctrl, -- wb stage control
of_ctrl_bus_i => of_ctrl, -- of stage control
 
-- data input --
wb_data_i => wb_data, -- write back data
immediate_i => immediate, -- immediates
pc_1d_i => pc_1d, -- pc 1x delayed
wb_fwd_i => wb_fwd, -- wb stage forwarding path
 
-- data output --
op_a_data_o => op_a_data, -- operand a output
op_b_data_o => op_b_data, -- operand b output
op_c_data_o => op_c_data -- operand c output
);
 
 
 
-- EX Stage --------------------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
executor: alu
port map (
-- global control --
clk_i => g_clk, -- global clock line
ce_i => g_ce, -- clock enable
rst_i => g_rst, -- global reset line, sync, high-active
port map (
-- global control --
clk_i => g_clk, -- global clock line
ce_i => g_ce, -- clock enable
rst_i => g_rst, -- global reset line, sync, high-active
-- function control --
ex_ctrl_bus_i => ex_ctrl, -- stage control
flag_bus_i => alu_flag_i, -- flag input
-- data input --
op_a_i => op_a_data, -- operand a input
op_b_i => op_b_data, -- operand b input
op_c_i => op_c_data, -- operand c input
pc_1d_i => pc_1d, -- 1x delayed pc
ma_fwd_i => ma_fwd, -- ma stage forwarding path
wb_fwd_i => wb_fwd, -- wb stage forwarding path
-- data output --
flag_bus_o => alu_flag_o, -- flag output
mask_t_flag_o => t_flag, -- t-flag for mask generation
msr_data_o => msr_w_data, -- msr write data
alu_res_o => alu_res, -- alu result
mul_res_o => mul_res, -- mul result
bp_opa_o => bp_a_data, -- operand a bypass
bp_opc_o => bp_c_data, -- operand c bypass
-- coprocessor interface --
cp_cp0_en_o => usr_cp_en_o, -- access to cp0
cp_cp1_en_o => sys_cp_en_o, -- access to cp1
cp_op_o => cp_op_o, -- data transfer/operation
cp_rw_o => cp_rw_o, -- read/write access
cp_cmd_o => cp_cmd_o, -- register addresses / cmd
cp_dat_o => cp_dat_o, -- write data
-- memory access --
mem_req_o => mem_req_o -- data memory access request for next cycle
);
 
-- function control --
ex_ctrl_bus_i => ex_ctrl, -- stage control
flag_bus_i => alu_flag_i, -- flag input
 
-- data input --
op_a_i => op_a_data, -- operand a input
op_b_i => op_b_data, -- operand b input
op_c_i => op_c_data, -- operand c input
pc_1d_i => pc_1d, -- 1x delayed pc
ma_fwd_i => ma_fwd, -- ma stage forwarding path
wb_fwd_i => wb_fwd, -- wb stage forwarding path
 
-- data output --
flag_bus_o => alu_flag_o, -- flag output
mask_t_flag_o => t_flag, -- t-flag for mask generation
msr_data_o => msr_w_data, -- msr write data
alu_res_o => alu_res, -- alu result
mul_res_o => mul_res, -- mul result
bp_opa_o => bp_a_data, -- operand a bypass
bp_opc_o => bp_c_data, -- operand c bypass
 
-- coprocessor interface --
cp_cp0_en_o => usr_cp_en_o, -- access to cp0
cp_cp1_en_o => sys_cp_en_o, -- access to cp1
cp_op_o => cp_op_o, -- data transfer/operation
cp_rw_o => cp_rw_o, -- read/write access
cp_cmd_o => cp_cmd_o, -- register addresses / cmd
cp_dat_o => cp_dat_o, -- write data
 
-- memory access --
mem_req_o => mem_req_o -- data memory access request for next cycle
);
 
 
 
-- MA Stage --------------------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
memory_access: mem_acc
port map (
-- global control --
clk_i => g_clk, -- global clock line
ce_i => g_ce, -- clock enable
rst_i => g_rst, -- global reset line, asyc
port map (
-- global control --
clk_i => g_clk, -- global clock line
ce_i => g_ce, -- clock enable
rst_i => g_rst, -- global reset line, asyc
-- function control --
ma_ctrl_bus_i => ma_ctrl, -- ma stage control
-- data input --
alu_res_i => alu_res, -- alu result
mul_res_i => mul_res, -- mul result
adr_base_i => bp_a_data, -- op_a bypass
data_bp_i => bp_c_data, -- op_b bypass
cp_data_i => cp_dat_i, -- coprocessor rd data
rd_msr_i => msr_r_data, -- read data msr
wb_fwd_i => wb_fwd, -- wb stage forwarding path
-- data output --
data_o => ma_data, -- data output
mem_adr_fb_o => mem_adr_fb, -- memory address feedback
ma_fwd_o => ma_fwd, -- ma stage forwarding path
-- memory (w) interface --
mem_adr_o => mem_adr_o, -- address output
mem_dat_o => mem_dat_o, -- write data output
mem_rw_o => mem_rw_o -- read write
);
 
-- function control --
ma_ctrl_bus_i => ma_ctrl, -- ma stage control
 
-- data input --
alu_res_i => alu_res, -- alu result
mul_res_i => mul_res, -- mul result
adr_base_i => bp_a_data, -- op_a bypass
data_bp_i => bp_c_data, -- op_b bypass
cp_data_i => cp_dat_i, -- coprocessor rd data
rd_msr_i => msr_r_data, -- read data msr
wb_fwd_i => wb_fwd, -- wb stage forwarding path
 
-- data output --
data_o => ma_data, -- data output
mem_adr_fb_o => mem_adr_fb, -- memory address feedback
ma_fwd_o => ma_fwd, -- ma stage forwarding path
 
-- memory (w) interface --
mem_adr_o => mem_adr_o, -- address output
mem_dat_o => mem_dat_o, -- write data output
mem_rw_o => mem_rw_o -- read write
);
 
 
 
-- WB Stage --------------------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
write_back: wb_unit
port map (
-- global control --
clk_i => g_clk, -- global clock line
ce_i => g_ce, -- clock enable
rst_i => g_rst, -- global reset line, sync, high-active
port map (
-- global control --
clk_i => g_clk, -- global clock line
ce_i => g_ce, -- clock enable
rst_i => g_rst, -- global reset line, sync, high-active
 
-- function control --
wb_ctrl_bus_i => wb_ctrl, -- wb stage control
-- function control --
wb_ctrl_bus_i => wb_ctrl, -- wb stage control
 
-- data input --
mem_wb_dat_i => mem_dat_i, -- memory read data
alu_wb_dat_i => ma_data, -- alu read data
mem_adr_fb_i => mem_adr_fb, -- memory address feedback
-- data input --
mem_wb_dat_i => mem_dat_i, -- memory read data
alu_wb_dat_i => ma_data, -- alu read data
mem_adr_fb_i => mem_adr_fb, -- memory address feedback
 
-- data output --
wb_data_o => wb_data, -- write back data
wb_fwd_o => wb_fwd -- wb stage forwarding path
);
-- data output --
wb_data_o => wb_data, -- write back data
wb_fwd_o => wb_fwd -- wb stage forwarding path
);
 
 
 
end ATLAS_CPU_BEHAV;
end atlas_cpu_behav;
/rtl/ATLAS_2K_BASE_TOP.vhd
29,8 → 29,8
-- ## Global Signals ##
-- ###############################################################################################
 
clk_i : in std_logic; -- global clock line
rstn_i : in std_logic; -- global reset line, low-active
clk_i : in std_ulogic; -- global clock line
rstn_i : in std_ulogic; -- global reset line, low-active
 
-- ###############################################################################################
-- ## IO Interface ##
37,38 → 37,38
-- ###############################################################################################
 
-- uart --
uart_rxd_i : in std_logic; -- receiver input
uart_txd_o : out std_logic; -- uart transmitter output
uart_rxd_i : in std_ulogic; -- receiver input
uart_txd_o : out std_ulogic; -- uart transmitter output
 
-- spi --
spi_mosi_o : out std_logic_vector(07 downto 0); -- serial data out
spi_miso_i : in std_logic_vector(07 downto 0); -- serial data in
spi_sck_o : out std_logic_vector(07 downto 0); -- serial clock out
spi_cs_o : out std_logic_vector(07 downto 0); -- chip select (low active)
spi_mosi_o : out std_ulogic_vector(07 downto 0); -- serial data out
spi_miso_i : in std_ulogic_vector(07 downto 0); -- serial data in
spi_sck_o : out std_ulogic_vector(07 downto 0); -- serial clock out
spi_cs_o : out std_ulogic_vector(07 downto 0); -- chip select (low active)
 
-- pio --
pio_out_o : out std_logic_vector(15 downto 0); -- parallel output
pio_in_i : in std_logic_vector(15 downto 0); -- parallel input
pio_out_o : out std_ulogic_vector(15 downto 0); -- parallel output
pio_in_i : in std_ulogic_vector(15 downto 0); -- parallel input
 
-- system io (bootloader, nos, ...) --
sys_out_o : out std_logic_vector(07 downto 0); -- system output
sys_in_i : in std_logic_vector(07 downto 0); -- system input
sys_out_o : out std_ulogic_vector(07 downto 0); -- system output
sys_in_i : in std_ulogic_vector(07 downto 0); -- system input
 
-- ###############################################################################################
-- ## Wishbone Bus ##
-- ###############################################################################################
 
wb_clk_o : out std_logic; -- bus clock
wb_rst_o : out std_logic; -- bus reset, sync, high active
wb_adr_o : out std_logic_vector(31 downto 0); -- address
wb_sel_o : out std_logic_vector(01 downto 0); -- byte select
wb_data_o : out std_logic_vector(15 downto 0); -- data out
wb_data_i : in std_logic_vector(15 downto 0); -- data in
wb_we_o : out std_logic; -- read/write
wb_cyc_o : out std_logic; -- cycle enable
wb_stb_o : out std_logic; -- strobe
wb_ack_i : in std_logic; -- acknowledge
wb_err_i : in std_logic -- bus error
wb_clk_o : out std_ulogic; -- bus clock
wb_rst_o : out std_ulogic; -- bus reset, sync, high active
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
wb_sel_o : out std_ulogic_vector(01 downto 0); -- byte select
wb_data_o : out std_ulogic_vector(15 downto 0); -- data out
wb_data_i : in std_ulogic_vector(15 downto 0); -- data in
wb_we_o : out std_ulogic; -- read/write
wb_cyc_o : out std_ulogic; -- cycle enable
wb_stb_o : out std_ulogic; -- strobe
wb_ack_i : in std_ulogic; -- acknowledge
wb_err_i : in std_ulogic -- bus error
);
end atlas_2k_base_top;
 
78,52 → 78,52
-- -------------------------------------------------------------------------------------------
component atlas_2k_top
generic (
clk_speed_g : std_logic_vector(31 downto 0) := (others => '0') -- clock speed (in hz)
);
port (
clk_i : in std_logic; -- global clock line
rst_i : in std_logic; -- global reset line, sync, high-active
ce_i : in std_logic; -- global clock enable, high active
cp_en_o : out std_logic; -- access to cp0
cp_ice_o : out std_logic; -- cp interface clock enable
cp_op_o : out std_logic; -- data transfer/processing
cp_rw_o : out std_logic; -- read/write access
cp_cmd_o : out std_logic_vector(08 downto 0); -- register addresses / cmd
cp_dat_o : out std_logic_vector(data_width_c-1 downto 0); -- write data
cp_dat_i : in std_logic_vector(data_width_c-1 downto 0); -- read data cp0
mem_i_page_o : out std_logic_vector(data_width_c-1 downto 0); -- instruction page
mem_i_adr_o : out std_logic_vector(data_width_c-1 downto 0); -- instruction adr
mem_i_dat_i : in std_logic_vector(data_width_c-1 downto 0); -- instruction input
mem_d_en_o : out std_logic; -- access enable
mem_d_rw_o : out std_logic; -- read/write
mem_d_page_o : out std_logic_vector(data_width_c-1 downto 0); -- data page
mem_d_adr_o : out std_logic_vector(data_width_c-1 downto 0); -- data adr
mem_d_dat_o : out std_logic_vector(data_width_c-1 downto 0); -- data out
mem_d_dat_i : in std_logic_vector(data_width_c-1 downto 0); -- data in
critical_irq_i : in std_logic; -- critical error irq
uart_rxd_i : in std_logic; -- receiver input
uart_txd_o : out std_logic; -- uart transmitter output
spi_mosi_o : out std_logic_vector(07 downto 0); -- serial data out
spi_miso_i : in std_logic_vector(07 downto 0); -- serial data in
spi_sck_o : out std_logic_vector(07 downto 0); -- serial clock out
spi_cs_o : out std_logic_vector(07 downto 0); -- chip select (low active)
pio_out_o : out std_logic_vector(15 downto 0); -- parallel output
pio_in_i : in std_logic_vector(15 downto 0); -- parallel input
sys_out_o : out std_logic_vector(07 downto 0); -- system parallel output
sys_in_i : in std_logic_vector(07 downto 0); -- system parallel input
irq_i : in std_logic; -- irq
wb_clk_o : out std_logic; -- bus clock
wb_rst_o : out std_logic; -- bus reset, sync, high active
wb_adr_o : out std_logic_vector(31 downto 0); -- address
wb_sel_o : out std_logic_vector(01 downto 0); -- byte select
wb_data_o : out std_logic_vector(15 downto 0); -- data out
wb_data_i : in std_logic_vector(15 downto 0); -- data in
wb_we_o : out std_logic; -- read/write
wb_cyc_o : out std_logic; -- cycle enable
wb_stb_o : out std_logic; -- strobe
wb_ack_i : in std_logic; -- acknowledge
wb_err_i : in std_logic -- bus error
);
clk_speed_g : std_ulogic_vector(31 downto 0) := (others => '0') -- clock speed (in hz)
);
port (
clk_i : in std_ulogic; -- global clock line
rst_i : in std_ulogic; -- global reset line, sync, high-active
ce_i : in std_ulogic; -- global clock enable, high active
cp_en_o : out std_ulogic; -- access to cp0
cp_ice_o : out std_ulogic; -- cp interface clock enable
cp_op_o : out std_ulogic; -- data transfer/processing
cp_rw_o : out std_ulogic; -- read/write access
cp_cmd_o : out std_ulogic_vector(08 downto 0); -- register addresses / cmd
cp_dat_o : out std_ulogic_vector(data_width_c-1 downto 0); -- write data
cp_dat_i : in std_ulogic_vector(data_width_c-1 downto 0); -- read data cp0
mem_i_page_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction page
mem_i_adr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction adr
mem_i_dat_i : in std_ulogic_vector(data_width_c-1 downto 0); -- instruction input
mem_d_en_o : out std_ulogic; -- access enable
mem_d_rw_o : out std_ulogic; -- read/write
mem_d_page_o : out std_ulogic_vector(data_width_c-1 downto 0); -- data page
mem_d_adr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- data adr
mem_d_dat_o : out std_ulogic_vector(data_width_c-1 downto 0); -- data out
mem_d_dat_i : in std_ulogic_vector(data_width_c-1 downto 0); -- data in
critical_irq_i : in std_ulogic; -- critical error irq
uart_rxd_i : in std_ulogic; -- receiver input
uart_txd_o : out std_ulogic; -- uart transmitter output
spi_mosi_o : out std_ulogic_vector(07 downto 0); -- serial data out
spi_miso_i : in std_ulogic_vector(07 downto 0); -- serial data in
spi_sck_o : out std_ulogic_vector(07 downto 0); -- serial clock out
spi_cs_o : out std_ulogic_vector(07 downto 0); -- chip select (low active)
pio_out_o : out std_ulogic_vector(15 downto 0); -- parallel output
pio_in_i : in std_ulogic_vector(15 downto 0); -- parallel input
sys_out_o : out std_ulogic_vector(07 downto 0); -- system parallel output
sys_in_i : in std_ulogic_vector(07 downto 0); -- system parallel input
irq_i : in std_ulogic; -- irq
wb_clk_o : out std_ulogic; -- bus clock
wb_rst_o : out std_ulogic; -- bus reset, sync, high active
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
wb_sel_o : out std_ulogic_vector(01 downto 0); -- byte select
wb_data_o : out std_ulogic_vector(15 downto 0); -- data out
wb_data_i : in std_ulogic_vector(15 downto 0); -- data in
wb_we_o : out std_ulogic; -- read/write
wb_cyc_o : out std_ulogic; -- cycle enable
wb_stb_o : out std_ulogic; -- strobe
wb_ack_i : in std_ulogic; -- acknowledge
wb_err_i : in std_ulogic -- bus error
);
end component;
 
-- RAM ------------------------------------------------------------------------------------
130,49 → 130,49
-- -------------------------------------------------------------------------------------------
component int_ram
generic (
mem_size_g : natural := 256 -- memory size in words
);
port (
-- host interface --
clk_i : in std_logic; -- global clock line
i_adr_i : in std_logic_vector(31 downto 0); -- instruction adr
i_dat_o : out std_logic_vector(15 downto 0); -- instruction out
d_en_i : in std_logic; -- access enable
d_rw_i : in std_logic; -- read/write
d_adr_i : in std_logic_vector(31 downto 0); -- data adr
d_dat_i : in std_logic_vector(15 downto 0); -- data in
d_dat_o : out std_logic_vector(15 downto 0) -- data out
);
mem_size_g : natural := 256 -- memory size in words
);
port (
-- host interface --
clk_i : in std_ulogic; -- global clock line
i_adr_i : in std_ulogic_vector(31 downto 0); -- instruction adr
i_dat_o : out std_ulogic_vector(15 downto 0); -- instruction out
d_en_i : in std_ulogic; -- access enable
d_rw_i : in std_ulogic; -- read/write
d_adr_i : in std_ulogic_vector(31 downto 0); -- data adr
d_dat_i : in std_ulogic_vector(15 downto 0); -- data in
d_dat_o : out std_ulogic_vector(15 downto 0) -- data out
);
end component;
 
-- *** USER CONFIGURATION ***
-- ***********************************************************************************************
constant clk_speed_c : std_logic_vector(31 downto 0) := x"02FAF080"; -- clock speed in Hz (here =50MHz)
constant num_pages_c : natural := 4; -- number of pages (must be a power of 2)
constant page_size_c : natural := 4096; -- page size in bytes (must be a power of 2)
constant clk_speed_c : std_ulogic_vector(31 downto 0) := x"02FAF080"; -- clock speed in Hz (here =50MHz)
constant num_pages_c : natural := 4; -- number of pages (must be a power of 2)
constant page_size_c : natural := 4096; -- page size in bytes (must be a power of 2)
-- ***********************************************************************************************
 
-- internals... -
constant ram_size_c : natural := num_pages_c*page_size_c; -- internal ram size in bytes
constant ld_pg_size_c : natural := log2(page_size_c); -- page select address width
constant ld_num_pg_c : natural := log2(num_pages_c); -- page size address width
constant ram_size_c : natural := num_pages_c*page_size_c; -- internal ram size in bytes
constant ld_pg_size_c : natural := log2(page_size_c); -- page select address width
constant ld_num_pg_c : natural := log2(num_pages_c); -- page size address width
 
-- global signals --
signal g_clk : std_logic;
signal g_rst : std_logic;
signal g_clk : std_ulogic;
signal g_rst : std_ulogic;
 
-- memory interface --
signal i_adr, d_adr : std_logic_vector(data_width_c-1 downto 0);
signal i_page, d_page : std_logic_vector(data_width_c-1 downto 0);
signal d_en : std_logic;
signal d_rw : std_logic;
signal i_dat_o, d_dat_o : std_logic_vector(data_width_c-1 downto 0);
signal d_dat_i : std_logic_vector(data_width_c-1 downto 0);
signal mem_d_adr : std_logic_vector(31 downto 0);
signal mem_i_adr : std_logic_vector(31 downto 0);
signal i_adr, d_adr : std_ulogic_vector(data_width_c-1 downto 0);
signal i_page, d_page : std_ulogic_vector(data_width_c-1 downto 0);
signal d_en : std_ulogic;
signal d_rw : std_ulogic;
signal i_dat_o, d_dat_o : std_ulogic_vector(data_width_c-1 downto 0);
signal d_dat_i : std_ulogic_vector(data_width_c-1 downto 0);
signal mem_d_adr : std_ulogic_vector(31 downto 0);
signal mem_i_adr : std_ulogic_vector(31 downto 0);
 
-- irq --
signal critical_irq : std_logic;
signal critical_irq : std_ulogic;
 
begin
 
182,68 → 182,66
g_clk <= clk_i;
 
 
 
-- Core ------------------------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
the_core_of_the_problem: atlas_2k_top
generic map (
clk_speed_g => clk_speed_c -- clock speed (in hz)
)
port map (
clk_i => g_clk, -- global clock line
rst_i => g_rst, -- global reset line, sync, high-active
ce_i => '1', -- global clock enable, high active
generic map (
clk_speed_g => clk_speed_c -- clock speed (in hz)
)
port map (
clk_i => g_clk, -- global clock line
rst_i => g_rst, -- global reset line, sync, high-active
ce_i => '1', -- global clock enable, high active
 
cp_en_o => open, -- access to cp0
cp_ice_o => open, -- cp interface clock enable
cp_op_o => open, -- data transfer/processing
cp_rw_o => open, -- read/write access
cp_cmd_o => open, -- register addresses / cmd
cp_dat_o => open, -- write data
cp_dat_i => x"0000", -- read data cp0
cp_en_o => open, -- access to cp0
cp_ice_o => open, -- cp interface clock enable
cp_op_o => open, -- data transfer/processing
cp_rw_o => open, -- read/write access
cp_cmd_o => open, -- register addresses / cmd
cp_dat_o => open, -- write data
cp_dat_i => x"0000", -- read data cp0
 
mem_i_page_o => i_page, -- instruction page
mem_i_adr_o => i_adr, -- instruction adr
mem_i_dat_i => i_dat_o, -- instruction input
mem_d_en_o => d_en, -- access enable
mem_d_rw_o => d_rw, -- read/write
mem_d_page_o => d_page, -- data page
mem_d_adr_o => d_adr, -- data adr
mem_d_dat_o => d_dat_i, -- data out
mem_d_dat_i => d_dat_o, -- data in
critical_irq_i => critical_irq, -- critical error irq
mem_i_page_o => i_page, -- instruction page
mem_i_adr_o => i_adr, -- instruction adr
mem_i_dat_i => i_dat_o, -- instruction input
mem_d_en_o => d_en, -- access enable
mem_d_rw_o => d_rw, -- read/write
mem_d_page_o => d_page, -- data page
mem_d_adr_o => d_adr, -- data adr
mem_d_dat_o => d_dat_i, -- data out
mem_d_dat_i => d_dat_o, -- data in
critical_irq_i => critical_irq, -- critical error irq
 
uart_rxd_i => uart_rxd_i, -- receiver input
uart_txd_o => uart_txd_o, -- uart transmitter output
uart_rxd_i => uart_rxd_i, -- receiver input
uart_txd_o => uart_txd_o, -- uart transmitter output
 
spi_sck_o => spi_sck_o, -- serial clock output
spi_mosi_o => spi_mosi_o, -- serial data output
spi_miso_i => spi_miso_i, -- serial data input
spi_cs_o => spi_cs_o, -- device select - low-active
spi_sck_o => spi_sck_o, -- serial clock output
spi_mosi_o => spi_mosi_o, -- serial data output
spi_miso_i => spi_miso_i, -- serial data input
spi_cs_o => spi_cs_o, -- device select - low-active
 
pio_out_o => pio_out_o, -- parallel output
pio_in_i => pio_in_i, -- parallel input
pio_out_o => pio_out_o, -- parallel output
pio_in_i => pio_in_i, -- parallel input
 
sys_out_o => sys_out_o, -- system parallel output
sys_in_i => sys_in_i, -- system parallel input
sys_out_o => sys_out_o, -- system parallel output
sys_in_i => sys_in_i, -- system parallel input
 
irq_i => '0', -- irq - not used here
irq_i => '0', -- irq - not used here
 
wb_clk_o => wb_clk_o, -- bus clock
wb_rst_o => wb_rst_o, -- bus reset, sync, high active
wb_adr_o => wb_adr_o, -- address
wb_sel_o => wb_sel_o, -- byte select
wb_data_o => wb_data_o, -- data out
wb_data_i => wb_data_i, -- data in
wb_we_o => wb_we_o, -- read/write
wb_cyc_o => wb_cyc_o, -- cycle enable
wb_stb_o => wb_stb_o, -- strobe
wb_ack_i => wb_ack_i, -- acknowledge
wb_err_i => wb_err_i -- bus error
);
wb_clk_o => wb_clk_o, -- bus clock
wb_rst_o => wb_rst_o, -- bus reset, sync, high active
wb_adr_o => wb_adr_o, -- address
wb_sel_o => wb_sel_o, -- byte select
wb_data_o => wb_data_o, -- data out
wb_data_i => wb_data_i, -- data in
wb_we_o => wb_we_o, -- read/write
wb_cyc_o => wb_cyc_o, -- cycle enable
wb_stb_o => wb_stb_o, -- strobe
wb_ack_i => wb_ack_i, -- acknowledge
wb_err_i => wb_err_i -- bus error
);
 
 
 
-- Memory Mapping --------------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
memory_mapping: process(i_page, d_page, i_adr, d_adr)
262,27 → 260,25
end process memory_mapping;
 
 
 
-- Internal RAM ----------------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
internal_ram: int_ram
generic map (
mem_size_g => ram_size_c -- memory size in bytes
)
port map (
-- host interface --
clk_i => g_clk, -- global clock line
i_adr_i => mem_i_adr, -- instruction adr
i_dat_o => i_dat_o, -- instruction out
d_en_i => d_en, -- access enable
d_rw_i => d_rw, -- read/write
d_adr_i => mem_d_adr, -- data adr
d_dat_i => d_dat_i, -- data in
d_dat_o => d_dat_o -- data out
);
generic map (
mem_size_g => ram_size_c -- memory size in bytes
)
port map (
-- host interface --
clk_i => g_clk, -- global clock line
i_adr_i => mem_i_adr, -- instruction adr
i_dat_o => i_dat_o, -- instruction out
d_en_i => d_en, -- access enable
d_rw_i => d_rw, -- read/write
d_adr_i => mem_d_adr, -- data adr
d_dat_i => d_dat_i, -- data in
d_dat_o => d_dat_o -- data out
);
 
 
 
-- User Section ----------------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
critical_irq <= '0';
/rtl/REG_FILE.vhd
23,33 → 23,33
-- ## Global Control ##
-- ###############################################################################################
 
clk_i : in std_logic; -- global clock line
ce_i : in std_logic; -- clock enable
rst_i : in std_logic; -- global reset line, sync, high-active
clk_i : in std_ulogic; -- global clock line
ce_i : in std_ulogic; -- clock enable
rst_i : in std_ulogic; -- global reset line, sync, high-active
 
-- ###############################################################################################
-- ## Function Control ##
-- ###############################################################################################
 
wb_ctrl_bus_i : in std_logic_vector(ctrl_width_c-1 downto 0); -- wb stage control
of_ctrl_bus_i : in std_logic_vector(ctrl_width_c-1 downto 0); -- of stage control
wb_ctrl_bus_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- wb stage control
of_ctrl_bus_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- of stage control
 
-- ###############################################################################################
-- ## Data Input ##
-- ###############################################################################################
 
wb_data_i : in std_logic_vector(data_width_c-1 downto 0); -- write back data
immediate_i : in std_logic_vector(data_width_c-1 downto 0); -- immediates
pc_1d_i : in std_logic_vector(data_width_c-1 downto 0); -- pc 1x delayed
wb_fwd_i : in std_logic_vector(fwd_width_c-1 downto 0); -- WB stage forwarding path
wb_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write back data
immediate_i : in std_ulogic_vector(data_width_c-1 downto 0); -- immediates
pc_1d_i : in std_ulogic_vector(data_width_c-1 downto 0); -- pc 1x delayed
wb_fwd_i : in std_ulogic_vector(fwd_width_c-1 downto 0); -- WB stage forwarding path
 
-- ###############################################################################################
-- ## Data Output ##
-- ###############################################################################################
 
op_a_data_o : out std_logic_vector(data_width_c-1 downto 0); -- operand a output
op_b_data_o : out std_logic_vector(data_width_c-1 downto 0); -- operand b output
op_c_data_o : out std_logic_vector(data_width_c-1 downto 0) -- operand c output
op_a_data_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand a output
op_b_data_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand b output
op_c_data_o : out std_ulogic_vector(data_width_c-1 downto 0) -- operand c output
);
end reg_file;
 
56,12 → 56,12
architecture rf_structure of reg_file is
 
-- register file --
type reg_file_mem_type is array (2*8-1 downto 0) of std_logic_vector(data_width_c-1 downto 0);
signal reg_file_mem : reg_file_mem_type := (others => (others => '0'));
type reg_file_mem_type is array (2*8-1 downto 0) of std_ulogic_vector(data_width_c-1 downto 0);
signal reg_file_mem : reg_file_mem_type := (others => (others => '0'));
 
-- operand multiplexer --
signal op_a_int : std_logic_vector(data_width_c-1 downto 0);
signal op_b_int : std_logic_vector(data_width_c-1 downto 0);
signal op_a_int : std_ulogic_vector(data_width_c-1 downto 0);
signal op_b_int : std_ulogic_vector(data_width_c-1 downto 0);
 
begin
 
78,7 → 78,6
end process data_register_file;
 
 
 
-- Operand Fetch Forwarding Unit -----------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
of_fwd: process(wb_fwd_i, of_ctrl_bus_i, reg_file_mem)
99,7 → 98,6
end process of_fwd;
 
 
 
-- Operand Multiplexer ---------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
op_a_data_o <= pc_1d_i when (of_ctrl_bus_i(ctrl_ra_is_pc_c) = '1') else op_a_int;
/rtl/MEM_GATE.vhd
19,38 → 19,38
entity mem_gate is
port (
-- host interface --
clk_i : in std_logic; -- global clock line
rst_i : in std_logic; -- global reset line, sync, high-active
clk_i : in std_ulogic; -- global clock line
rst_i : in std_ulogic; -- global reset line, sync, high-active
 
i_adr_i : in std_logic_vector(15 downto 0); -- instruction adr
i_dat_o : out std_logic_vector(15 downto 0); -- instruction out
d_req_i : in std_logic; -- request access in next cycle
d_rw_i : in std_logic; -- read/write
d_adr_i : in std_logic_vector(15 downto 0); -- data adr
d_dat_i : in std_logic_vector(15 downto 0); -- data in
d_dat_o : out std_logic_vector(15 downto 0); -- data out
mem_ip_adr_i : in std_logic_vector(15 downto 0); -- instruction page
mem_dp_adr_i : in std_logic_vector(15 downto 0); -- data page
i_adr_i : in std_ulogic_vector(15 downto 0); -- instruction adr
i_dat_o : out std_ulogic_vector(15 downto 0); -- instruction out
d_req_i : in std_ulogic; -- request access in next cycle
d_rw_i : in std_ulogic; -- read/write
d_adr_i : in std_ulogic_vector(15 downto 0); -- data adr
d_dat_i : in std_ulogic_vector(15 downto 0); -- data in
d_dat_o : out std_ulogic_vector(15 downto 0); -- data out
mem_ip_adr_i : in std_ulogic_vector(15 downto 0); -- instruction page
mem_dp_adr_i : in std_ulogic_vector(15 downto 0); -- data page
 
-- boot rom interface --
boot_i_adr_o : out std_logic_vector(15 downto 0); -- instruction adr
boot_i_dat_i : in std_logic_vector(15 downto 0); -- instruction out
boot_d_en_o : out std_logic; -- access enable
boot_d_rw_o : out std_logic; -- read/write
boot_d_adr_o : out std_logic_vector(15 downto 0); -- data adr
boot_d_dat_o : out std_logic_vector(15 downto 0); -- data in
boot_d_dat_i : in std_logic_vector(15 downto 0); -- data out
boot_i_adr_o : out std_ulogic_vector(15 downto 0); -- instruction adr
boot_i_dat_i : in std_ulogic_vector(15 downto 0); -- instruction out
boot_d_en_o : out std_ulogic; -- access enable
boot_d_rw_o : out std_ulogic; -- read/write
boot_d_adr_o : out std_ulogic_vector(15 downto 0); -- data adr
boot_d_dat_o : out std_ulogic_vector(15 downto 0); -- data in
boot_d_dat_i : in std_ulogic_vector(15 downto 0); -- data out
 
-- memory interface --
mem_i_page_o : out std_logic_vector(15 downto 0); -- instruction page
mem_i_adr_o : out std_logic_vector(15 downto 0); -- instruction adr
mem_i_dat_i : in std_logic_vector(15 downto 0); -- instruction out
mem_d_en_o : out std_logic; -- access enable
mem_d_rw_o : out std_logic; -- read/write
mem_d_page_o : out std_logic_vector(15 downto 0); -- data page
mem_d_adr_o : out std_logic_vector(15 downto 0); -- data adr
mem_d_dat_o : out std_logic_vector(15 downto 0); -- data in
mem_d_dat_i : in std_logic_vector(15 downto 0) -- data out
mem_i_page_o : out std_ulogic_vector(15 downto 0); -- instruction page
mem_i_adr_o : out std_ulogic_vector(15 downto 0); -- instruction adr
mem_i_dat_i : in std_ulogic_vector(15 downto 0); -- instruction out
mem_d_en_o : out std_ulogic; -- access enable
mem_d_rw_o : out std_ulogic; -- read/write
mem_d_page_o : out std_ulogic_vector(15 downto 0); -- data page
mem_d_adr_o : out std_ulogic_vector(15 downto 0); -- data adr
mem_d_dat_o : out std_ulogic_vector(15 downto 0); -- data in
mem_d_dat_i : in std_ulogic_vector(15 downto 0) -- data out
);
end mem_gate;
 
57,9 → 57,9
architecture mem_gate_behav of mem_gate is
 
-- local signals --
signal mem_dacc_ff : std_logic;
signal d_gate_sel : std_logic;
signal i_gate_sel : std_logic;
signal mem_dacc_ff : std_ulogic;
signal d_gate_sel : std_ulogic;
signal i_gate_sel : std_ulogic;
 
begin
 
/rtl/ALU.vhd
22,51 → 22,51
-- ## Global Control ##
-- ###############################################################################################
 
clk_i : in std_logic; -- global clock line
ce_i : in std_logic; -- clock enable
rst_i : in std_logic; -- global reset line, sync, high-active
clk_i : in std_ulogic; -- global clock line
ce_i : in std_ulogic; -- clock enable
rst_i : in std_ulogic; -- global reset line, sync, high-active
 
-- ###############################################################################################
-- ## Function Control ##
-- ###############################################################################################
 
ex_ctrl_bus_i : in std_logic_vector(ctrl_width_c-1 downto 0); -- stage control
flag_bus_i : in std_logic_vector(flag_bus_width_c-1 downto 0); -- flag input
ex_ctrl_bus_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- stage control
flag_bus_i : in std_ulogic_vector(flag_bus_width_c-1 downto 0); -- flag input
 
-- ###############################################################################################
-- ## Data Input ##
-- ###############################################################################################
 
op_a_i : in std_logic_vector(data_width_c-1 downto 0); -- operand a input
op_b_i : in std_logic_vector(data_width_c-1 downto 0); -- operand b input
op_c_i : in std_logic_vector(data_width_c-1 downto 0); -- operand c input
op_a_i : in std_ulogic_vector(data_width_c-1 downto 0); -- operand a input
op_b_i : in std_ulogic_vector(data_width_c-1 downto 0); -- operand b input
op_c_i : in std_ulogic_vector(data_width_c-1 downto 0); -- operand c input
 
pc_1d_i : in std_logic_vector(data_width_c-1 downto 0); -- 1x delayed pc
pc_1d_i : in std_ulogic_vector(data_width_c-1 downto 0); -- 1x delayed pc
 
ma_fwd_i : in std_logic_vector(fwd_width_c-1 downto 0); -- ma stage forwarding path
wb_fwd_i : in std_logic_vector(fwd_width_c-1 downto 0); -- wb stage forwarding path
ma_fwd_i : in std_ulogic_vector(fwd_width_c-1 downto 0); -- ma stage forwarding path
wb_fwd_i : in std_ulogic_vector(fwd_width_c-1 downto 0); -- wb stage forwarding path
 
-- ###############################################################################################
-- ## Data Output ##
-- ###############################################################################################
 
flag_bus_o : out std_logic_vector(flag_bus_width_c-1 downto 0); -- flag output
mask_t_flag_o : out std_logic; -- t-flag for mask generation
flag_bus_o : out std_ulogic_vector(flag_bus_width_c-1 downto 0); -- flag output
mask_t_flag_o : out std_ulogic; -- t-flag for mask generation
 
msr_data_o : out std_logic_vector(data_width_c-1 downto 0); -- msr write data
alu_res_o : out std_logic_vector(data_width_c-1 downto 0); -- alu result
mul_res_o : out std_logic_vector(2*data_width_c-1 downto 0); -- mul result
bp_opa_o : out std_logic_vector(data_width_c-1 downto 0); -- operand a bypass
bp_opc_o : out std_logic_vector(data_width_c-1 downto 0); -- operand c bypass
msr_data_o : out std_ulogic_vector(data_width_c-1 downto 0); -- msr write data
alu_res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- alu result
mul_res_o : out std_ulogic_vector(2*data_width_c-1 downto 0); -- mul result
bp_opa_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand a bypass
bp_opc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand c bypass
 
cp_cp0_en_o : out std_logic; -- access to cp0
cp_cp1_en_o : out std_logic; -- access to cp1
cp_op_o : out std_logic; -- data transfer/operation
cp_rw_o : out std_logic; -- read/write access
cp_cmd_o : out std_logic_vector(cp_cmd_width_c-1 downto 0); -- register addresses / cmd
cp_dat_o : out std_logic_vector(data_width_c-1 downto 0); -- write data
cp_cp0_en_o : out std_ulogic; -- access to cp0
cp_cp1_en_o : out std_ulogic; -- access to cp1
cp_op_o : out std_ulogic; -- data transfer/operation
cp_rw_o : out std_ulogic; -- read/write access
cp_cmd_o : out std_ulogic_vector(cp_cmd_width_c-1 downto 0); -- register addresses / cmd
cp_dat_o : out std_ulogic_vector(data_width_c-1 downto 0); -- write data
 
mem_req_o : out std_logic -- data memory access request for next cycle
mem_req_o : out std_ulogic -- data memory access request for next cycle
);
end alu;
 
73,34 → 73,34
architecture alu_structure of alu is
 
-- pipeline register --
signal op_a_ff : std_logic_vector(data_width_c-1 downto 0);
signal op_b_ff : std_logic_vector(data_width_c-1 downto 0);
signal op_c_ff : std_logic_vector(data_width_c-1 downto 0);
signal op_a_ff : std_ulogic_vector(data_width_c-1 downto 0);
signal op_b_ff : std_ulogic_vector(data_width_c-1 downto 0);
signal op_c_ff : std_ulogic_vector(data_width_c-1 downto 0);
 
-- functional units output --
signal fu_arith_res : std_logic_vector(data_width_c-1 downto 0);
signal fu_arith_flg : std_logic_vector(1 downto 0); -- overflow & carry
signal fu_logic_res : std_logic_vector(data_width_c-1 downto 0);
signal fu_logic_flg : std_logic_vector(1 downto 0);
signal fu_shift_res : std_logic_vector(data_width_c-1 downto 0);
signal fu_shift_flg : std_logic_vector(1 downto 0);
signal fu_arith_res : std_ulogic_vector(data_width_c-1 downto 0);
signal fu_arith_flg : std_ulogic_vector(1 downto 0); -- overflow & carry
signal fu_logic_res : std_ulogic_vector(data_width_c-1 downto 0);
signal fu_logic_flg : std_ulogic_vector(1 downto 0);
signal fu_shift_res : std_ulogic_vector(data_width_c-1 downto 0);
signal fu_shift_flg : std_ulogic_vector(1 downto 0);
 
-- internal data lines --
signal op_a_int : std_logic_vector(data_width_c-1 downto 0);
signal op_b_int : std_logic_vector(data_width_c-1 downto 0);
signal op_c_int : std_logic_vector(data_width_c-1 downto 0);
signal alu_res_int : std_logic_vector(data_width_c-1 downto 0);
signal t_flag_func : std_logic;
signal parity_bit : std_logic;
signal transf_int : std_logic;
signal sel_bit : std_logic;
signal inv_bit : std_logic;
signal is_zero : std_logic;
signal extnd_zero : std_logic;
signal op_a_int : std_ulogic_vector(data_width_c-1 downto 0);
signal op_b_int : std_ulogic_vector(data_width_c-1 downto 0);
signal op_c_int : std_ulogic_vector(data_width_c-1 downto 0);
signal alu_res_int : std_ulogic_vector(data_width_c-1 downto 0);
signal t_flag_func : std_ulogic;
signal parity_bit : std_ulogic;
signal transf_int : std_ulogic;
signal sel_bit : std_ulogic;
signal inv_bit : std_ulogic;
signal is_zero : std_ulogic;
signal extnd_zero : std_ulogic;
 
-- multiplier --
signal mul_op_a : std_logic_vector(data_width_c-1 downto 0);
signal mul_op_b : std_logic_vector(data_width_c-1 downto 0);
signal mul_op_a : std_ulogic_vector(data_width_c-1 downto 0);
signal mul_op_b : std_ulogic_vector(data_width_c-1 downto 0);
 
begin
 
122,16 → 122,15
end process pipe_reg;
 
 
 
-- Execution Forwarding Unit ---------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
ex_fwd: process(ma_fwd_i, wb_fwd_i, ex_ctrl_bus_i, op_a_ff, op_b_ff, op_c_ff)
variable op_a_ma_match_v : std_logic;
variable op_b_ma_match_v : std_logic;
variable op_a_wb_match_v : std_logic;
variable op_b_wb_match_v : std_logic;
variable op_c_wb_match_v : std_logic;
variable op_a_tmp_v : std_logic_vector(data_width_c-1 downto 0);
variable op_a_ma_match_v : std_ulogic;
variable op_b_ma_match_v : std_ulogic;
variable op_a_wb_match_v : std_ulogic;
variable op_b_wb_match_v : std_ulogic;
variable op_c_wb_match_v : std_ulogic;
variable op_a_tmp_v : std_ulogic_vector(data_width_c-1 downto 0);
begin
 
-- data from early stages -> higher priority than data from later stages
161,12 → 160,6
if (wb_fwd_i(fwd_en_c) = '1') and (ex_ctrl_bus_i(ctrl_rb_3_c downto ctrl_rb_0_c) = wb_fwd_i(fwd_adr_3_c downto fwd_adr_0_c)) then
op_c_wb_match_v := '1';
end if;
-- op_a_ma_match_v := ma_fwd_i(fwd_en_c) and ex_ctrl_bus_i(ctrl_a_ex_ma_fw_c);
-- op_a_wb_match_v := wb_fwd_i(fwd_en_c) and ex_ctrl_bus_i(ctrl_a_ex_wb_fw_c);
-- op_b_ma_match_v := ma_fwd_i(fwd_en_c) and ex_ctrl_bus_i(ctrl_b_ex_ma_fw_c);
-- op_b_wb_match_v := wb_fwd_i(fwd_en_c) and ex_ctrl_bus_i(ctrl_b_ex_wb_fw_c);
-- op_c_wb_match_v := wb_fwd_i(fwd_en_c) and ex_ctrl_bus_i(ctrl_c_ex_wb_fw_c);
 
-- op a gating --
if (ex_ctrl_bus_i(ctrl_en_c) = '1') then
215,17 → 208,16
end process ex_fwd;
 
 
 
-- Functional Unit: Arithmetic Core --------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
fu_arithmetic_core: process(ex_ctrl_bus_i, op_a_int, op_b_int, flag_bus_i)
variable op_a_v, op_b_v : std_logic_vector(data_width_c-1 downto 0);
variable cflag_v : std_logic;
variable add_a_v, add_b_v : std_logic_vector(data_width_c downto 0);
variable add_cf_in_v : std_logic_vector(0 downto 0);
variable adder_c_sel_v : std_logic;
variable adder_carry_in_v : std_logic;
variable adder_tmp_v : std_logic_vector(data_width_c downto 0);
variable op_a_v, op_b_v : std_ulogic_vector(data_width_c-1 downto 0);
variable cflag_v : std_ulogic;
variable add_a_v, add_b_v : std_ulogic_vector(data_width_c downto 0);
variable add_cf_in_v : std_ulogic_vector(0 downto 0);
variable adder_c_sel_v : std_ulogic;
variable adder_carry_in_v : std_ulogic;
variable adder_tmp_v : std_ulogic_vector(data_width_c downto 0);
begin
 
-- operand insulation --
260,7 → 252,7
end case;
 
-- adder core --
adder_tmp_v := std_logic_vector(unsigned(add_a_v) + unsigned(add_b_v) + unsigned(add_cf_in_v(0 downto 0)));
adder_tmp_v := std_ulogic_vector(unsigned(add_a_v) + unsigned(add_b_v) + unsigned(add_cf_in_v(0 downto 0)));
fu_arith_res <= adder_tmp_v(data_width_c-1 downto 0); -- result, msb of adder_tmp_v is carry bit
-- adder flag carry output logic --
279,15 → 271,14
end process fu_arithmetic_core;
 
 
 
-- Functional Unit: Shifter Core -----------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
fu_shifter_core: process(ex_ctrl_bus_i, op_a_int, op_b_ff, flag_bus_i)
variable op_a_v, op_b_v : std_logic_vector(data_width_c-1 downto 0);
variable cflag_v : std_logic;
variable shifter_dat_v : std_logic_vector(data_width_c-1 downto 0);
variable shifter_carry_v : std_logic;
variable shifter_ovf_v : std_logic;
variable op_a_v, op_b_v : std_ulogic_vector(data_width_c-1 downto 0);
variable cflag_v : std_ulogic;
variable shifter_dat_v : std_ulogic_vector(data_width_c-1 downto 0);
variable shifter_carry_v : std_ulogic;
variable shifter_ovf_v : std_ulogic;
begin
 
-- operand insulation --
335,7 → 326,6
end process fu_shifter_core;
 
 
 
-- Functional Unit: Logical Core -----------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
fu_logic_core: process(ex_ctrl_bus_i, op_a_int, op_b_int, flag_bus_i)
358,7 → 348,6
end process fu_logic_core;
 
 
 
-- Function Selector -----------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
-- data result --
371,11 → 360,10
flag_bus_o(flag_o_c) <= fu_arith_flg(1) or fu_shift_flg(1) or fu_logic_flg(0);
 
 
 
-- Parity Computation ----------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
parity_gen: process(op_a_int)
variable par_v : std_logic;
variable par_v : std_ulogic;
begin
par_v := '0';
for i in 0 to data_width_c-1 loop
385,7 → 373,6
end process parity_gen;
 
 
 
-- Additional Flag Computation -------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
 
409,12 → 396,11
mask_t_flag_o <= transf_int when (ex_ctrl_bus_i(ctrl_en_c) = '1') and (ex_ctrl_bus_i(ctrl_tf_store_c) = '1') else flag_bus_i(flag_t_c);
 
 
 
-- Multiplier Kernel (signed) --------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
-- operand gating --
mul_op_a <= op_a_int when ((build_mul_c = true) and (ex_ctrl_bus_i(ctrl_use_mul_c) = '1')) else (others => '0');
mul_op_b <= op_b_int when ((build_mul_c = true) and (ex_ctrl_bus_i(ctrl_use_mul_c) = '1')) else (others => '0');
mul_op_a <= op_a_int when (ex_ctrl_bus_i(ctrl_use_mul_c) = '1') else (others => '0');
mul_op_b <= op_b_int when (ex_ctrl_bus_i(ctrl_use_mul_c) = '1') else (others => '0');
 
-- multiplier core (signed!) --
mul_buffer: process(clk_i)
423,10 → 409,14
if (rst_i = '1') then
mul_res_o <= (others => '0');
elsif (ce_i = '1') then
if (signed_mul_c = true) then
mul_res_o <= std_logic_vector(signed(mul_op_a) * signed(mul_op_b));
if (build_mul_c = true) then
if (signed_mul_c = true) then
mul_res_o <= std_ulogic_vector(signed(mul_op_a) * signed(mul_op_b));
else
mul_res_o <= std_ulogic_vector(unsigned(mul_op_a) * unsigned(mul_op_b));
end if;
else
mul_res_o <= std_logic_vector(unsigned(mul_op_a) * unsigned(mul_op_b));
mul_res_o <= (others => '0');
end if;
end if;
end if;
433,7 → 423,6
end process mul_buffer;
 
 
 
-- Module Data Output ----------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
 
460,4 → 449,4
 
 
 
end ALU_STRUCTURE;
end alu_structure;
/rtl/ATLAS_2K_TOP.vhd
21,44 → 21,44
-- ## Configuration ##
-- ###############################################################################################
generic (
clk_speed_g : std_logic_vector(31 downto 0) := x"00000000" -- clock speed (in Hz)
clk_speed_g : std_ulogic_vector(31 downto 0) := x"00000000" -- clock speed (in Hz)
);
-- ###############################################################################################
-- ## Global Control ##
-- ###############################################################################################
port (
clk_i : in std_logic; -- global clock line
rst_i : in std_logic; -- global reset line, sync, high-active
ce_i : in std_logic; -- global clock enable, high active
clk_i : in std_ulogic; -- global clock line
rst_i : in std_ulogic; -- global reset line, sync, high-active
ce_i : in std_ulogic; -- global clock enable, high active
 
-- ###############################################################################################
-- ## Coprocessor Interface ##
-- ###############################################################################################
 
cp_en_o : out std_logic; -- access to cp0
cp_ice_o : out std_logic; -- cp interface clock enable
cp_op_o : out std_logic; -- data transfer/processing
cp_rw_o : out std_logic; -- read/write access
cp_cmd_o : out std_logic_vector(08 downto 0); -- register addresses / cmd
cp_dat_o : out std_logic_vector(data_width_c-1 downto 0); -- write data
cp_dat_i : in std_logic_vector(data_width_c-1 downto 0); -- read data cp0
cp_en_o : out std_ulogic; -- access to cp0
cp_ice_o : out std_ulogic; -- cp interface clock enable
cp_op_o : out std_ulogic; -- data transfer/processing
cp_rw_o : out std_ulogic; -- read/write access
cp_cmd_o : out std_ulogic_vector(08 downto 0); -- register addresses / cmd
cp_dat_o : out std_ulogic_vector(data_width_c-1 downto 0); -- write data
cp_dat_i : in std_ulogic_vector(data_width_c-1 downto 0); -- read data cp0
 
-- ###############################################################################################
-- ## Memory Interface ##
-- ###############################################################################################
 
mem_i_page_o : out std_logic_vector(data_width_c-1 downto 0); -- instruction page
mem_i_adr_o : out std_logic_vector(data_width_c-1 downto 0); -- instruction adr
mem_i_dat_i : in std_logic_vector(data_width_c-1 downto 0); -- instruction input
mem_i_page_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction page
mem_i_adr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction adr
mem_i_dat_i : in std_ulogic_vector(data_width_c-1 downto 0); -- instruction input
 
mem_d_en_o : out std_logic; -- access enable
mem_d_rw_o : out std_logic; -- read/write
mem_d_page_o : out std_logic_vector(data_width_c-1 downto 0); -- data page
mem_d_adr_o : out std_logic_vector(data_width_c-1 downto 0); -- data adr
mem_d_dat_o : out std_logic_vector(data_width_c-1 downto 0); -- data out
mem_d_dat_i : in std_logic_vector(data_width_c-1 downto 0); -- data in
mem_d_en_o : out std_ulogic; -- access enable
mem_d_rw_o : out std_ulogic; -- read/write
mem_d_page_o : out std_ulogic_vector(data_width_c-1 downto 0); -- data page
mem_d_adr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- data adr
mem_d_dat_o : out std_ulogic_vector(data_width_c-1 downto 0); -- data out
mem_d_dat_i : in std_ulogic_vector(data_width_c-1 downto 0); -- data in
 
critical_irq_i : in std_logic; -- critical error irq
critical_irq_i : in std_ulogic; -- critical error irq
 
-- ###############################################################################################
-- ## IO Interface ##
65,41 → 65,41
-- ###############################################################################################
 
-- uart --
uart_rxd_i : in std_logic; -- uart receiver input
uart_txd_o : out std_logic; -- uart transmitter output
uart_rxd_i : in std_ulogic; -- uart receiver input
uart_txd_o : out std_ulogic; -- uart transmitter output
 
-- spi --
spi_mosi_o : out std_logic_vector(07 downto 0); -- serial data out
spi_miso_i : in std_logic_vector(07 downto 0); -- serial data in
spi_sck_o : out std_logic_vector(07 downto 0); -- serial clock out
spi_cs_o : out std_logic_vector(07 downto 0); -- chip select (low active)
spi_mosi_o : out std_ulogic_vector(07 downto 0); -- serial data out
spi_miso_i : in std_ulogic_vector(07 downto 0); -- serial data in
spi_sck_o : out std_ulogic_vector(07 downto 0); -- serial clock out
spi_cs_o : out std_ulogic_vector(07 downto 0); -- chip select (low active)
 
-- parallel io --
pio_out_o : out std_logic_vector(15 downto 0); -- parallel output
pio_in_i : in std_logic_vector(15 downto 0); -- parallel input
pio_out_o : out std_ulogic_vector(15 downto 0); -- parallel output
pio_in_i : in std_ulogic_vector(15 downto 0); -- parallel input
 
-- system io --
sys_out_o : out std_logic_vector(07 downto 0); -- system output
sys_in_i : in std_logic_vector(07 downto 0); -- system input
sys_out_o : out std_ulogic_vector(07 downto 0); -- system output
sys_in_i : in std_ulogic_vector(07 downto 0); -- system input
 
-- irqs --
irq_i : in std_logic; -- irq
irq_i : in std_ulogic; -- irq
 
-- ###############################################################################################
-- ## Wishbone Bus ##
-- ###############################################################################################
 
wb_clk_o : out std_logic; -- bus clock
wb_rst_o : out std_logic; -- bus reset, sync, high active
wb_adr_o : out std_logic_vector(31 downto 0); -- address
wb_sel_o : out std_logic_vector(01 downto 0); -- byte select
wb_data_o : out std_logic_vector(15 downto 0); -- data out
wb_data_i : in std_logic_vector(15 downto 0); -- data in
wb_we_o : out std_logic; -- read/write
wb_cyc_o : out std_logic; -- cycle enable
wb_stb_o : out std_logic; -- strobe
wb_ack_i : in std_logic; -- acknowledge
wb_err_i : in std_logic -- bus error
wb_clk_o : out std_ulogic; -- bus clock
wb_rst_o : out std_ulogic; -- bus reset, sync, high active
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
wb_sel_o : out std_ulogic_vector(01 downto 0); -- byte select
wb_data_o : out std_ulogic_vector(15 downto 0); -- data out
wb_data_i : in std_ulogic_vector(15 downto 0); -- data in
wb_we_o : out std_ulogic; -- read/write
wb_cyc_o : out std_ulogic; -- cycle enable
wb_stb_o : out std_ulogic; -- strobe
wb_ack_i : in std_ulogic; -- acknowledge
wb_err_i : in std_ulogic -- bus error
);
end atlas_2k_top;
 
106,44 → 106,44
architecture atlas_2k_top_behav of atlas_2k_top is
 
-- global control --
signal sys_mode : std_logic; -- current processor mode
signal sys_int_exe : std_logic; -- processing irq
signal sys_mode : std_ulogic; -- current processor mode
signal sys_int_exe : std_ulogic; -- processing irq
 
-- coprocessor signals --
signal usr_cp_en : std_logic; -- access user coprocessor
signal sys_cp_en : std_logic; -- access system coprocessor
signal cp_op : std_logic; -- transfer/data processing
signal cp_rw : std_logic; -- read/write access
signal cp_cmd : std_logic_vector(08 downto 0); -- register addresses / cmd
signal cp_w_data : std_logic_vector(data_width_c-1 downto 0); -- write data
signal sys_cp_drb : std_logic_vector(data_width_c-1 downto 0); -- system coprocessor data readback
signal cp_data_rb : std_logic_vector(data_width_c-1 downto 0); -- coprocessor data readback
signal usr_cp_en : std_ulogic; -- access user coprocessor
signal sys_cp_en : std_ulogic; -- access system coprocessor
signal cp_op : std_ulogic; -- transfer/data processing
signal cp_rw : std_ulogic; -- read/write access
signal cp_cmd : std_ulogic_vector(08 downto 0); -- register addresses / cmd
signal cp_w_data : std_ulogic_vector(data_width_c-1 downto 0); -- write data
signal sys_cp_drb : std_ulogic_vector(data_width_c-1 downto 0); -- system coprocessor data readback
signal cp_data_rb : std_ulogic_vector(data_width_c-1 downto 0); -- coprocessor data readback
 
-- cpu bus --
signal cpu_d_req : std_logic; -- data access request
signal cpu_d_rw : std_logic; -- read/write access
signal cpu_d_adr : std_logic_vector(data_width_c-1 downto 0); -- access address
signal cpu_d_w_data : std_logic_vector(data_width_c-1 downto 0); -- write data
signal cpu_d_r_data : std_logic_vector(data_width_c-1 downto 0); -- read data
signal cpu_i_adr : std_logic_vector(data_width_c-1 downto 0); -- instruction address
signal cpu_i_data : std_logic_vector(data_width_c-1 downto 0); -- instruction word
signal cp_dat_i_sync : std_logic_vector(data_width_c-1 downto 0); -- external input sync
signal cpu_d_req : std_ulogic; -- data access request
signal cpu_d_rw : std_ulogic; -- read/write access
signal cpu_d_adr : std_ulogic_vector(data_width_c-1 downto 0); -- access address
signal cpu_d_w_data : std_ulogic_vector(data_width_c-1 downto 0); -- write data
signal cpu_d_r_data : std_ulogic_vector(data_width_c-1 downto 0); -- read data
signal cpu_i_adr : std_ulogic_vector(data_width_c-1 downto 0); -- instruction address
signal cpu_i_data : std_ulogic_vector(data_width_c-1 downto 0); -- instruction word
signal cp_dat_i_sync : std_ulogic_vector(data_width_c-1 downto 0); -- external input sync
 
-- mmu --
signal i_page : std_logic_vector(data_width_c-1 downto 0); -- instruction page
signal d_page : std_logic_vector(data_width_c-1 downto 0); -- data page
signal i_page : std_ulogic_vector(data_width_c-1 downto 0); -- instruction page
signal d_page : std_ulogic_vector(data_width_c-1 downto 0); -- data page
 
-- boot mem --
signal boot_i_adr : std_logic_vector(15 downto 0); -- instruction adr
signal boot_i_dat : std_logic_vector(15 downto 0); -- instruction out
signal boot_d_en : std_logic; -- access enable
signal boot_d_rw : std_logic; -- read/write
signal boot_d_adr : std_logic_vector(15 downto 0); -- data adr
signal boot_d_dat_o : std_logic_vector(15 downto 0); -- data in
signal boot_d_dat_i : std_logic_vector(15 downto 0); -- data out
signal boot_i_adr : std_ulogic_vector(15 downto 0); -- instruction adr
signal boot_i_dat : std_ulogic_vector(15 downto 0); -- instruction out
signal boot_d_en : std_ulogic; -- access enable
signal boot_d_rw : std_ulogic; -- read/write
signal boot_d_adr : std_ulogic_vector(15 downto 0); -- data adr
signal boot_d_dat_o : std_ulogic_vector(15 downto 0); -- data in
signal boot_d_dat_i : std_ulogic_vector(15 downto 0); -- data out
 
-- irq lines --
signal sys_cp_irq : std_logic; -- irq from system coprocessor
signal sys_cp_irq : std_ulogic; -- irq from system coprocessor
 
begin
 
150,39 → 150,39
-- Atlas CPU Core --------------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
cpu_core: atlas_cpu
port map (
-- global control --
clk_i => clk_i, -- global clock line
rst_i => rst_i, -- global reset line, sync, high-active
ce_i => ce_i, -- clock enable
port map (
-- global control --
clk_i => clk_i, -- global clock line
rst_i => rst_i, -- global reset line, sync, high-active
ce_i => ce_i, -- clock enable
-- instruction interface --
instr_adr_o => cpu_i_adr, -- instruction byte adr
instr_dat_i => cpu_i_data, -- instruction input
-- data interface --
sys_mode_o => sys_mode, -- current operating mode
sys_int_o => sys_int_exe, -- interrupt processing
mem_req_o => cpu_d_req, -- mem access in next cycle
mem_rw_o => cpu_d_rw, -- read write
mem_adr_o => cpu_d_adr, -- data byte adr
mem_dat_o => cpu_d_w_data, -- write data
mem_dat_i => cpu_d_r_data, -- read data
-- coprocessor interface --
usr_cp_en_o => usr_cp_en, -- access to cp0
sys_cp_en_o => sys_cp_en, -- access to cp1
cp_op_o => cp_op, -- data transfer/processing
cp_rw_o => cp_rw, -- read/write access
cp_cmd_o => cp_cmd, -- register addresses / cmd
cp_dat_o => cp_w_data, -- write data
cp_dat_i => cp_data_rb, -- read data cp0 or cp1
-- interrupt lines --
ext_int_0_i => critical_irq_i, -- critical error irq
ext_int_1_i => sys_cp_irq -- sys cp irq
);
 
-- instruction interface --
instr_adr_o => cpu_i_adr, -- instruction byte adr
instr_dat_i => cpu_i_data, -- instruction input
 
-- data interface --
sys_mode_o => sys_mode, -- current operating mode
sys_int_o => sys_int_exe, -- interrupt processing
mem_req_o => cpu_d_req, -- mem access in next cycle
mem_rw_o => cpu_d_rw, -- read write
mem_adr_o => cpu_d_adr, -- data byte adr
mem_dat_o => cpu_d_w_data, -- write data
mem_dat_i => cpu_d_r_data, -- read data
 
-- coprocessor interface --
usr_cp_en_o => usr_cp_en, -- access to cp0
sys_cp_en_o => sys_cp_en, -- access to cp1
cp_op_o => cp_op, -- data transfer/processing
cp_rw_o => cp_rw, -- read/write access
cp_cmd_o => cp_cmd, -- register addresses / cmd
cp_dat_o => cp_w_data, -- write data
cp_dat_i => cp_data_rb, -- read data cp0 or cp1
 
-- interrupt lines --
ext_int_0_i => critical_irq_i, -- critical error irq
ext_int_1_i => sys_cp_irq -- sys cp irq
);
 
-- external cp data in sync --
cp_dat_in_sync: process (clk_i)
begin
209,122 → 209,120
cp_ice_o <= ce_i;
 
 
 
-- System Coprocessor ----------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
system_coprocessor: system_cp
generic map (
clock_speed_g => clk_speed_g -- clock speed in hz
)
port map (
-- global control --
clk_i => clk_i, -- global clock line
rst_i => rst_i, -- global reset line, sync, high-active
ice_i => ce_i, -- interface clock enable, high-active
generic map (
clock_speed_g => clk_speed_g -- clock speed in hz
)
port map (
-- global control --
clk_i => clk_i, -- global clock line
rst_i => rst_i, -- global reset line, sync, high-active
ice_i => ce_i, -- interface clock enable, high-active
-- processor interface --
cp_en_i => sys_cp_en, -- access coprocessor
cp_op_i => cp_op, -- data transfer/processing
cp_rw_i => cp_rw, -- read/write access
cp_cmd_i => cp_cmd, -- register addresses / cmd
cp_dat_i => cp_w_data, -- write data
cp_dat_o => sys_cp_drb, -- read data
cp_irq_o => sys_cp_irq, -- unit interrupt request
sys_mode_i => sys_mode, -- current operating mode
int_exe_i => sys_int_exe, -- interrupt beeing executed
-- memory interface --
mem_ip_adr_o => i_page, -- instruction page
mem_dp_adr_o => d_page, -- data page
-- io interface --
uart_rxd_i => uart_rxd_i, -- receiver input
uart_txd_o => uart_txd_o, -- uart transmitter output
spi_sck_o => spi_sck_o, -- serial clock output
spi_mosi_o => spi_mosi_o, -- serial data output
spi_miso_i => spi_miso_i, -- serial data input
spi_cs_o => spi_cs_o, -- device select
pio_out_o => pio_out_o, -- parallel output
pio_in_i => pio_in_i, -- parallel input
-- system io --
sys_out_o => sys_out_o, -- system parallel output
sys_in_i => sys_in_i, -- system parallel input
-- irq lines --
irq_i => irq_i, -- external irq
-- wishbone bus --
wb_clk_o => wb_clk_o, -- bus clock
wb_rst_o => wb_rst_o, -- bus reset, sync, high active
wb_adr_o => wb_adr_o, -- address
wb_sel_o => wb_sel_o, -- byte select
wb_data_o => wb_data_o, -- data out
wb_data_i => wb_data_i, -- data in
wb_we_o => wb_we_o, -- read/write
wb_cyc_o => wb_cyc_o, -- cycle enable
wb_stb_o => wb_stb_o, -- strobe
wb_ack_i => wb_ack_i, -- acknowledge
wb_err_i => wb_err_i -- bus error
);
 
-- processor interface --
cp_en_i => sys_cp_en, -- access coprocessor
cp_op_i => cp_op, -- data transfer/processing
cp_rw_i => cp_rw, -- read/write access
cp_cmd_i => cp_cmd, -- register addresses / cmd
cp_dat_i => cp_w_data, -- write data
cp_dat_o => sys_cp_drb, -- read data
cp_irq_o => sys_cp_irq, -- unit interrupt request
 
sys_mode_i => sys_mode, -- current operating mode
int_exe_i => sys_int_exe, -- interrupt beeing executed
 
-- memory interface --
mem_ip_adr_o => i_page, -- instruction page
mem_dp_adr_o => d_page, -- data page
 
-- io interface --
uart_rxd_i => uart_rxd_i, -- receiver input
uart_txd_o => uart_txd_o, -- uart transmitter output
spi_sck_o => spi_sck_o, -- serial clock output
spi_mosi_o => spi_mosi_o, -- serial data output
spi_miso_i => spi_miso_i, -- serial data input
spi_cs_o => spi_cs_o, -- device select
pio_out_o => pio_out_o, -- parallel output
pio_in_i => pio_in_i, -- parallel input
 
-- system io --
sys_out_o => sys_out_o, -- system parallel output
sys_in_i => sys_in_i, -- system parallel input
 
-- irq lines --
irq_i => irq_i, -- external irq
 
-- wishbone bus --
wb_clk_o => wb_clk_o, -- bus clock
wb_rst_o => wb_rst_o, -- bus reset, sync, high active
wb_adr_o => wb_adr_o, -- address
wb_sel_o => wb_sel_o, -- byte select
wb_data_o => wb_data_o, -- data out
wb_data_i => wb_data_i, -- data in
wb_we_o => wb_we_o, -- read/write
wb_cyc_o => wb_cyc_o, -- cycle enable
wb_stb_o => wb_stb_o, -- strobe
wb_ack_i => wb_ack_i, -- acknowledge
wb_err_i => wb_err_i -- bus error
);
 
 
-- Memory Gate -----------------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
memory_gate: mem_gate
port map (
-- host interface --
clk_i => clk_i, -- global clock line
rst_i => rst_i, -- global reset line, sync, high-active
port map (
-- host interface --
clk_i => clk_i, -- global clock line
rst_i => rst_i, -- global reset line, sync, high-active
i_adr_i => cpu_i_adr, -- instruction adr
i_dat_o => cpu_i_data, -- instruction out
d_req_i => cpu_d_req, -- request access in next cycle
d_rw_i => cpu_d_rw, -- read/write
d_adr_i => cpu_d_adr, -- data adr
d_dat_i => cpu_d_w_data, -- data in
d_dat_o => cpu_d_r_data, -- data out
mem_ip_adr_i => i_page, -- instruction page
mem_dp_adr_i => d_page, -- data page
-- boot rom interface --
boot_i_adr_o => boot_i_adr, -- instruction adr
boot_i_dat_i => boot_i_dat, -- instruction out
boot_d_en_o => boot_d_en, -- access enable
boot_d_rw_o => boot_d_rw, -- read/write
boot_d_adr_o => boot_d_adr, -- data adr
boot_d_dat_o => boot_d_dat_o, -- data in
boot_d_dat_i => boot_d_dat_i, -- data out
-- memory interface --
mem_i_page_o => mem_i_page_o, -- instruction page
mem_i_adr_o => mem_i_adr_o, -- instruction adr
mem_i_dat_i => mem_i_dat_i, -- instruction out
mem_d_en_o => mem_d_en_o, -- access enable
mem_d_rw_o => mem_d_rw_o, -- read/write
mem_d_page_o => mem_d_page_o, -- instruction page
mem_d_adr_o => mem_d_adr_o, -- data adr
mem_d_dat_o => mem_d_dat_o, -- data in
mem_d_dat_i => mem_d_dat_i -- data out
);
 
i_adr_i => cpu_i_adr, -- instruction adr
i_dat_o => cpu_i_data, -- instruction out
d_req_i => cpu_d_req, -- request access in next cycle
d_rw_i => cpu_d_rw, -- read/write
d_adr_i => cpu_d_adr, -- data adr
d_dat_i => cpu_d_w_data, -- data in
d_dat_o => cpu_d_r_data, -- data out
mem_ip_adr_i => i_page, -- instruction page
mem_dp_adr_i => d_page, -- data page
 
-- boot rom interface --
boot_i_adr_o => boot_i_adr, -- instruction adr
boot_i_dat_i => boot_i_dat, -- instruction out
boot_d_en_o => boot_d_en, -- access enable
boot_d_rw_o => boot_d_rw, -- read/write
boot_d_adr_o => boot_d_adr, -- data adr
boot_d_dat_o => boot_d_dat_o, -- data in
boot_d_dat_i => boot_d_dat_i, -- data out
 
-- memory interface --
mem_i_page_o => mem_i_page_o, -- instruction page
mem_i_adr_o => mem_i_adr_o, -- instruction adr
mem_i_dat_i => mem_i_dat_i, -- instruction out
mem_d_en_o => mem_d_en_o, -- access enable
mem_d_rw_o => mem_d_rw_o, -- read/write
mem_d_page_o => mem_d_page_o, -- instruction page
mem_d_adr_o => mem_d_adr_o, -- data adr
mem_d_dat_o => mem_d_dat_o, -- data in
mem_d_dat_i => mem_d_dat_i -- data out
);
 
 
 
-- Bootloader Memory -----------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
bootloader_mem: boot_mem
port map (
-- host interface --
clk_i => clk_i, -- global clock line
i_adr_i => boot_i_adr, -- instruction adr
i_dat_o => boot_i_dat, -- instruction out
d_en_i => boot_d_en, -- access enable
d_rw_i => boot_d_rw, -- read/write
d_adr_i => boot_d_adr, -- data adr
d_dat_i => boot_d_dat_o, -- data in
d_dat_o => boot_d_dat_i -- data out
);
port map (
-- host interface --
clk_i => clk_i, -- global clock line
i_adr_i => boot_i_adr, -- instruction adr
i_dat_o => boot_i_dat, -- instruction out
d_en_i => boot_d_en, -- access enable
d_rw_i => boot_d_rw, -- read/write
d_adr_i => boot_d_adr, -- data adr
d_dat_i => boot_d_dat_o, -- data in
d_dat_o => boot_d_dat_i -- data out
);
 
 
 
/rtl/MEM_ACC.vhd
23,45 → 23,45
-- ## Global Control ##
-- ###############################################################################################
 
clk_i : in std_logic; -- global clock line
ce_i : in std_logic; -- clock enable
rst_i : in std_logic; -- global reset line, sync, high-active
clk_i : in std_ulogic; -- global clock line
ce_i : in std_ulogic; -- clock enable
rst_i : in std_ulogic; -- global reset line, sync, high-active
 
-- ###############################################################################################
-- ## Function Control ##
-- ###############################################################################################
 
ma_ctrl_bus_i : in std_logic_vector(ctrl_width_c-1 downto 0); -- ma stage control
ma_ctrl_bus_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- ma stage control
 
-- ###############################################################################################
-- ## Data Input ##
-- ###############################################################################################
 
alu_res_i : in std_logic_vector(data_width_c-1 downto 0); -- alu result
mul_res_i : in std_logic_vector(2*data_width_c-1 downto 0); -- mul result
adr_base_i : in std_logic_vector(data_width_c-1 downto 0); -- op_a bypass
data_bp_i : in std_logic_vector(data_width_c-1 downto 0); -- op_b bypass
cp_data_i : in std_logic_vector(data_width_c-1 downto 0); -- coprocessor rd data
rd_msr_i : in std_logic_vector(data_width_c-1 downto 0); -- read data msr
alu_res_i : in std_ulogic_vector(data_width_c-1 downto 0); -- alu result
mul_res_i : in std_ulogic_vector(2*data_width_c-1 downto 0); -- mul result
adr_base_i : in std_ulogic_vector(data_width_c-1 downto 0); -- op_a bypass
data_bp_i : in std_ulogic_vector(data_width_c-1 downto 0); -- op_b bypass
cp_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- coprocessor rd data
rd_msr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- read data msr
 
wb_fwd_i : in std_logic_vector(fwd_width_c-1 downto 0); -- wb stage forwarding path
wb_fwd_i : in std_ulogic_vector(fwd_width_c-1 downto 0); -- wb stage forwarding path
 
-- ###############################################################################################
-- ## Data Output ##
-- ###############################################################################################
 
data_o : out std_logic_vector(data_width_c-1 downto 0); -- data output
mem_adr_fb_o : out std_logic_vector(data_width_c-1 downto 0); -- memory address feedback
data_o : out std_ulogic_vector(data_width_c-1 downto 0); -- data output
mem_adr_fb_o : out std_ulogic_vector(data_width_c-1 downto 0); -- memory address feedback
 
ma_fwd_o : out std_logic_vector(fwd_width_c-1 downto 0); -- ma stage forwarding path
ma_fwd_o : out std_ulogic_vector(fwd_width_c-1 downto 0); -- ma stage forwarding path
 
-- ###############################################################################################
-- ## Memory (w) Interface ##
-- ###############################################################################################
 
mem_adr_o : out std_logic_vector(data_width_c-1 downto 0); -- address output
mem_dat_o : out std_logic_vector(data_width_c-1 downto 0); -- write data output
mem_rw_o : out std_logic -- read write
mem_adr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- address output
mem_dat_o : out std_ulogic_vector(data_width_c-1 downto 0); -- write data output
mem_rw_o : out std_ulogic -- read write
);
end mem_acc;
 
68,19 → 68,19
architecture ma_structure of mem_acc is
 
-- pipeline register --
signal alu_res_ff : std_logic_vector(data_width_c-1 downto 0);
signal adr_base_ff : std_logic_vector(data_width_c-1 downto 0);
signal data_bp_ff : std_logic_vector(data_width_c-1 downto 0);
signal alu_res_ff : std_ulogic_vector(data_width_c-1 downto 0);
signal adr_base_ff : std_ulogic_vector(data_width_c-1 downto 0);
signal data_bp_ff : std_ulogic_vector(data_width_c-1 downto 0);
 
-- alu data buffer --
signal alu_res_buf : std_logic_vector(data_width_c-1 downto 0);
signal alu_res_buf : std_ulogic_vector(data_width_c-1 downto 0);
 
-- internal signals --
signal data_bp_int : std_logic_vector(data_width_c-1 downto 0);
signal alu_mac_dat : std_logic_vector(data_width_c-1 downto 0);
signal sys_cp_r_dat : std_logic_vector(data_width_c-1 downto 0);
signal sys_cp_alu_r_dat : std_logic_vector(data_width_c-1 downto 0);
signal mul_res_int : std_logic_vector(data_width_c-1 downto 0);
signal data_bp_int : std_ulogic_vector(data_width_c-1 downto 0);
signal alu_mac_dat : std_ulogic_vector(data_width_c-1 downto 0);
signal sys_cp_r_dat : std_ulogic_vector(data_width_c-1 downto 0);
signal sys_cp_alu_r_dat : std_ulogic_vector(data_width_c-1 downto 0);
signal mul_res_int : std_ulogic_vector(data_width_c-1 downto 0);
 
begin
 
104,7 → 104,6
end process pipe_reg;
 
 
 
-- Memory Access Forwarding Unit -----------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
ma_fwd: process(wb_fwd_i, ma_ctrl_bus_i, data_bp_ff)
118,12 → 117,11
end process ma_fwd;
 
 
 
-- Memory Address Generator and Data Alignment ---------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
w_mem_acc: process(ma_ctrl_bus_i, alu_res_buf, adr_base_ff, alu_res_ff, data_bp_int)
variable mem_adr_v : std_logic_vector(data_width_c-1 downto 0);
variable dat_end_v : std_logic_vector(data_width_c-1 downto 0);
variable mem_adr_v : std_ulogic_vector(data_width_c-1 downto 0);
variable dat_end_v : std_ulogic_vector(data_width_c-1 downto 0);
begin
-- address origin --
if (ma_ctrl_bus_i(ctrl_mem_daa_c) = '1') then
159,7 → 157,6
mem_rw_o <= ma_ctrl_bus_i(ctrl_mem_wr_c) and ma_ctrl_bus_i(ctrl_en_c);
 
 
 
-- Stage Data Multiplexer ------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
no_mul_unit: -- syntheszie no mul unit at all
188,7 → 185,6
data_o <= data_bp_ff when (ma_ctrl_bus_i(ctrl_link_c) = '1') else sys_cp_alu_r_dat;
 
 
 
-- Forwarding Path Output ------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
 
203,5 → 199,4
 
 
 
 
end MA_STRUCTURE;
/rtl/OP_DEC.vhd
21,35 → 21,35
-- ## Decoder Interface Input ##
-- ###############################################################################################
 
instr_i : in std_logic_vector(data_width_c-1 downto 0); -- instruction input
instr_adr_i : in std_logic_vector(data_width_c-1 downto 0); -- corresponding address
t_flag_i : in std_logic; -- t-flag input
m_flag_i : in std_logic; -- mode flag input
multi_cyc_i : in std_logic; -- multi-cycle indicator
cp_ptc_i : in std_logic; -- user coprocessor protection
instr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- instruction input
instr_adr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- corresponding address
t_flag_i : in std_ulogic; -- t-flag input
m_flag_i : in std_ulogic; -- mode flag input
multi_cyc_i : in std_ulogic; -- multi-cycle indicator
cp_ptc_i : in std_ulogic; -- user coprocessor protection
 
-- ###############################################################################################
-- ## Decoder Interface Output ##
-- ###############################################################################################
 
MULTI_CYC_REQ_O : OUT STD_LOGIC; -- MULTI-CYCLE REQEST
CTRL_O : OUT STD_LOGIC_VECTOR(CTRL_WIDTH_C-1 DOWNTO 0); -- DECODER CTRL LINES
IMM_O : OUT STD_LOGIC_VECTOR(DATA_WIDTH_C-1 DOWNTO 0) -- IMMEDIATE
multi_cyc_req_o : out std_ulogic; -- multi-cycle reqest
ctrl_o : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- decoder ctrl lines
imm_o : out std_ulogic_vector(data_width_c-1 downto 0) -- immediate
);
END OP_DEC;
end op_dec;
 
ARCHITECTURE OP_DEC_STRUCTURE OF OP_DEC IS
architecture op_dec_structure of op_dec is
 
-- FORMATED INSTRUCTION --
SIGNAL INSTR_INT : STD_LOGIC_VECTOR(15 DOWNTO 0);
-- formated instruction --
signal instr_int : std_ulogic_vector(15 downto 0);
 
BEGIN
begin
 
-- Data Format Converter -------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
data_conv: process(instr_i, instr_adr_i)
variable instr_sel_v : std_logic_vector(31 downto 0);
variable instr_tmp_v : std_logic_vector(15 downto 0);
variable instr_sel_v : std_ulogic_vector(31 downto 0);
variable instr_tmp_v : std_ulogic_vector(15 downto 0);
begin
instr_sel_v := (others => '0');
for i in 0 to data_width_c-1 loop
72,12 → 72,11
end process data_conv;
 
 
 
-- Opcode Decoder --------------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
opcode_decoder: process(instr_int, multi_cyc_i, t_flag_i, m_flag_i, cp_ptc_i)
variable mem_acc_temp_v : std_logic_vector(3 downto 0);
variable redundant_reg_v : std_logic;
variable mem_acc_temp_v : std_ulogic_vector(3 downto 0);
variable redundant_reg_v : std_ulogic;
begin
 
-- defaults --
524,5 → 523,4
 
 
 
 
end OP_DEC_STRUCTURE;
end op_dec_structure;
/rtl/INT_RAM.vhd
17,18 → 17,18
 
entity int_ram is
generic (
mem_size_g : natural := 256 -- memory size in bytes
mem_size_g : natural := 256 -- memory size in bytes
);
port (
-- host interface --
clk_i : in std_logic; -- global clock line
i_adr_i : in std_logic_vector(31 downto 0); -- instruction adr
i_dat_o : out std_logic_vector(15 downto 0); -- instruction out
d_en_i : in std_logic; -- access enable
d_rw_i : in std_logic; -- read/write
d_adr_i : in std_logic_vector(31 downto 0); -- data adr
d_dat_i : in std_logic_vector(15 downto 0); -- data in
d_dat_o : out std_logic_vector(15 downto 0) -- data out
clk_i : in std_ulogic; -- global clock line
i_adr_i : in std_ulogic_vector(31 downto 0); -- instruction adr
i_dat_o : out std_ulogic_vector(15 downto 0); -- instruction out
d_en_i : in std_ulogic; -- access enable
d_rw_i : in std_ulogic; -- read/write
d_adr_i : in std_ulogic_vector(31 downto 0); -- data adr
d_dat_i : in std_ulogic_vector(15 downto 0); -- data in
d_dat_o : out std_ulogic_vector(15 downto 0) -- data out
);
end int_ram;
 
38,7 → 38,7
constant log2_mem_size_c : natural := log2(mem_size_g/2); -- address width
 
-- memory type --
type int_mem_file_t is array (0 to (mem_size_g/2)-1) of std_logic_vector(data_width_c-1 downto 0);
type int_mem_file_t is array (0 to (mem_size_g/2)-1) of std_ulogic_vector(data_width_c-1 downto 0);
 
-- ======================================================================
signal mem_file : int_mem_file_t; -- use this for implementation

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.